1 //===-- PPCFrameLowering.cpp - PPC Frame Information ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PPC implementation of TargetFrameLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCFrameLowering.h"
15 #include "PPCInstrBuilder.h"
16 #include "PPCInstrInfo.h"
17 #include "PPCMachineFunctionInfo.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineModuleInfo.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/RegisterScavenging.h"
24 #include "llvm/IR/Function.h"
25 #include "llvm/Target/TargetOptions.h"
29 /// VRRegNo - Map from a numbered VR register to its enum value.
31 static const uint16_t VRRegNo[] = {
32 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
33 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
34 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
35 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
38 /// RemoveVRSaveCode - We have found that this function does not need any code
39 /// to manipulate the VRSAVE register, even though it uses vector registers.
40 /// This can happen when the only registers used are known to be live in or out
41 /// of the function. Remove all of the VRSAVE related code from the function.
42 /// FIXME: The removal of the code results in a compile failure at -O0 when the
43 /// function contains a function call, as the GPR containing original VRSAVE
44 /// contents is spilled and reloaded around the call. Without the prolog code,
45 /// the spill instruction refers to an undefined register. This code needs
46 /// to account for all uses of that GPR.
47 static void RemoveVRSaveCode(MachineInstr *MI) {
48 MachineBasicBlock *Entry = MI->getParent();
49 MachineFunction *MF = Entry->getParent();
51 // We know that the MTVRSAVE instruction immediately follows MI. Remove it.
52 MachineBasicBlock::iterator MBBI = MI;
54 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE);
55 MBBI->eraseFromParent();
57 bool RemovedAllMTVRSAVEs = true;
58 // See if we can find and remove the MTVRSAVE instruction from all of the
60 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) {
61 // If last instruction is a return instruction, add an epilogue
62 if (!I->empty() && I->back().isReturn()) {
64 for (MBBI = I->end(); MBBI != I->begin(); ) {
66 if (MBBI->getOpcode() == PPC::MTVRSAVE) {
67 MBBI->eraseFromParent(); // remove it.
72 RemovedAllMTVRSAVEs &= FoundIt;
76 // If we found and removed all MTVRSAVE instructions, remove the read of
78 if (RemovedAllMTVRSAVEs) {
80 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?");
82 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?");
83 MBBI->eraseFromParent();
86 // Finally, nuke the UPDATE_VRSAVE.
87 MI->eraseFromParent();
90 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the
91 // instruction selector. Based on the vector registers that have been used,
92 // transform this into the appropriate ORI instruction.
93 static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) {
94 MachineFunction *MF = MI->getParent()->getParent();
95 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
96 DebugLoc dl = MI->getDebugLoc();
98 unsigned UsedRegMask = 0;
99 for (unsigned i = 0; i != 32; ++i)
100 if (MF->getRegInfo().isPhysRegUsed(VRRegNo[i]))
101 UsedRegMask |= 1 << (31-i);
103 // Live in and live out values already must be in the mask, so don't bother
105 for (MachineRegisterInfo::livein_iterator
106 I = MF->getRegInfo().livein_begin(),
107 E = MF->getRegInfo().livein_end(); I != E; ++I) {
108 unsigned RegNo = TRI->getEncodingValue(I->first);
109 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg.
110 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
113 // Live out registers appear as use operands on return instructions.
114 for (MachineFunction::const_iterator BI = MF->begin(), BE = MF->end();
115 UsedRegMask != 0 && BI != BE; ++BI) {
116 const MachineBasicBlock &MBB = *BI;
117 if (MBB.empty() || !MBB.back().isReturn())
119 const MachineInstr &Ret = MBB.back();
120 for (unsigned I = 0, E = Ret.getNumOperands(); I != E; ++I) {
121 const MachineOperand &MO = Ret.getOperand(I);
122 if (!MO.isReg() || !PPC::VRRCRegClass.contains(MO.getReg()))
124 unsigned RegNo = TRI->getEncodingValue(MO.getReg());
125 UsedRegMask &= ~(1 << (31-RegNo));
129 // If no registers are used, turn this into a copy.
130 if (UsedRegMask == 0) {
131 // Remove all VRSAVE code.
132 RemoveVRSaveCode(MI);
136 unsigned SrcReg = MI->getOperand(1).getReg();
137 unsigned DstReg = MI->getOperand(0).getReg();
139 if ((UsedRegMask & 0xFFFF) == UsedRegMask) {
140 if (DstReg != SrcReg)
141 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
143 .addImm(UsedRegMask);
145 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
146 .addReg(SrcReg, RegState::Kill)
147 .addImm(UsedRegMask);
148 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) {
149 if (DstReg != SrcReg)
150 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
152 .addImm(UsedRegMask >> 16);
154 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
155 .addReg(SrcReg, RegState::Kill)
156 .addImm(UsedRegMask >> 16);
158 if (DstReg != SrcReg)
159 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
161 .addImm(UsedRegMask >> 16);
163 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
164 .addReg(SrcReg, RegState::Kill)
165 .addImm(UsedRegMask >> 16);
167 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
168 .addReg(DstReg, RegState::Kill)
169 .addImm(UsedRegMask & 0xFFFF);
172 // Remove the old UPDATE_VRSAVE instruction.
173 MI->eraseFromParent();
176 static bool spillsCR(const MachineFunction &MF) {
177 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
178 return FuncInfo->isCRSpilled();
181 static bool spillsVRSAVE(const MachineFunction &MF) {
182 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
183 return FuncInfo->isVRSAVESpilled();
186 static bool hasSpills(const MachineFunction &MF) {
187 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
188 return FuncInfo->hasSpills();
191 static bool hasNonRISpills(const MachineFunction &MF) {
192 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
193 return FuncInfo->hasNonRISpills();
196 /// determineFrameLayout - Determine the size of the frame and maximum call
198 unsigned PPCFrameLowering::determineFrameLayout(MachineFunction &MF,
200 bool UseEstimate) const {
201 MachineFrameInfo *MFI = MF.getFrameInfo();
203 // Get the number of bytes to allocate from the FrameInfo
205 UseEstimate ? MFI->estimateStackSize(MF) : MFI->getStackSize();
207 // Get stack alignments. The frame must be aligned to the greatest of these:
208 unsigned TargetAlign = getStackAlignment(); // alignment required per the ABI
209 unsigned MaxAlign = MFI->getMaxAlignment(); // algmt required by data in frame
210 unsigned AlignMask = std::max(MaxAlign, TargetAlign) - 1;
212 const PPCRegisterInfo *RegInfo =
213 static_cast<const PPCRegisterInfo*>(MF.getTarget().getRegisterInfo());
215 // If we are a leaf function, and use up to 224 bytes of stack space,
216 // don't have a frame pointer, calls, or dynamic alloca then we do not need
217 // to adjust the stack pointer (we fit in the Red Zone).
218 // The 32-bit SVR4 ABI has no Red Zone. However, it can still generate
219 // stackless code if all local vars are reg-allocated.
220 bool DisableRedZone = MF.getFunction()->getAttributes().
221 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoRedZone);
222 if (!DisableRedZone &&
223 (Subtarget.isPPC64() || // 32-bit SVR4, no stack-
224 !Subtarget.isSVR4ABI() || // allocated locals.
226 FrameSize <= 224 && // Fits in red zone.
227 !MFI->hasVarSizedObjects() && // No dynamic alloca.
228 !MFI->adjustsStack() && // No calls.
229 !RegInfo->hasBasePointer(MF)) { // No special alignment.
232 MFI->setStackSize(0);
236 // Get the maximum call frame size of all the calls.
237 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
239 // Maximum call frame needs to be at least big enough for linkage and 8 args.
240 unsigned minCallFrameSize = getMinCallFrameSize(Subtarget.isPPC64(),
241 Subtarget.isDarwinABI());
242 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize);
244 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so
245 // that allocations will be aligned.
246 if (MFI->hasVarSizedObjects())
247 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask;
249 // Update maximum call frame size.
251 MFI->setMaxCallFrameSize(maxCallFrameSize);
253 // Include call frame size in total.
254 FrameSize += maxCallFrameSize;
256 // Make sure the frame is aligned.
257 FrameSize = (FrameSize + AlignMask) & ~AlignMask;
259 // Update frame info.
261 MFI->setStackSize(FrameSize);
266 // hasFP - Return true if the specified function actually has a dedicated frame
268 bool PPCFrameLowering::hasFP(const MachineFunction &MF) const {
269 const MachineFrameInfo *MFI = MF.getFrameInfo();
270 // FIXME: This is pretty much broken by design: hasFP() might be called really
271 // early, before the stack layout was calculated and thus hasFP() might return
272 // true or false here depending on the time of call.
273 return (MFI->getStackSize()) && needsFP(MF);
276 // needsFP - Return true if the specified function should have a dedicated frame
277 // pointer register. This is true if the function has variable sized allocas or
278 // if frame pointer elimination is disabled.
279 bool PPCFrameLowering::needsFP(const MachineFunction &MF) const {
280 const MachineFrameInfo *MFI = MF.getFrameInfo();
282 // Naked functions have no stack frame pushed, so we don't have a frame
284 if (MF.getFunction()->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
288 return MF.getTarget().Options.DisableFramePointerElim(MF) ||
289 MFI->hasVarSizedObjects() ||
290 (MF.getTarget().Options.GuaranteedTailCallOpt &&
291 MF.getInfo<PPCFunctionInfo>()->hasFastCall());
294 void PPCFrameLowering::replaceFPWithRealFP(MachineFunction &MF) const {
295 bool is31 = needsFP(MF);
296 unsigned FPReg = is31 ? PPC::R31 : PPC::R1;
297 unsigned FP8Reg = is31 ? PPC::X31 : PPC::X1;
299 const PPCRegisterInfo *RegInfo =
300 static_cast<const PPCRegisterInfo*>(MF.getTarget().getRegisterInfo());
301 bool HasBP = RegInfo->hasBasePointer(MF);
302 unsigned BPReg = HasBP ? (unsigned) RegInfo->getBaseRegister(MF): FPReg;
303 unsigned BP8Reg = HasBP ? (unsigned) PPC::X30 : FPReg;
305 for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
307 for (MachineBasicBlock::iterator MBBI = BI->end(); MBBI != BI->begin(); ) {
309 for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I) {
310 MachineOperand &MO = MBBI->getOperand(I);
314 switch (MO.getReg()) {
333 void PPCFrameLowering::emitPrologue(MachineFunction &MF) const {
334 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
335 MachineBasicBlock::iterator MBBI = MBB.begin();
336 MachineFrameInfo *MFI = MF.getFrameInfo();
337 const PPCInstrInfo &TII =
338 *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo());
339 const PPCRegisterInfo *RegInfo =
340 static_cast<const PPCRegisterInfo*>(MF.getTarget().getRegisterInfo());
342 MachineModuleInfo &MMI = MF.getMMI();
343 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
345 bool needsFrameMoves = MMI.hasDebugInfo() ||
346 MF.getFunction()->needsUnwindTableEntry();
347 bool isPIC = MF.getTarget().getRelocationModel() == Reloc::PIC_;
349 // Get processor type.
350 bool isPPC64 = Subtarget.isPPC64();
352 bool isDarwinABI = Subtarget.isDarwinABI();
353 bool isSVR4ABI = Subtarget.isSVR4ABI();
354 assert((isDarwinABI || isSVR4ABI) &&
355 "Currently only Darwin and SVR4 ABIs are supported for PowerPC.");
357 // Prepare for frame info.
358 MCSymbol *FrameLabel = 0;
360 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it,
363 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
364 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
365 HandleVRSaveUpdate(MBBI, TII);
370 // Move MBBI back to the beginning of the function.
373 // Work out frame sizes.
374 unsigned FrameSize = determineFrameLayout(MF);
375 int NegFrameSize = -FrameSize;
376 if (!isInt<32>(NegFrameSize))
377 llvm_unreachable("Unhandled stack size!");
379 if (MFI->isFrameAddressTaken())
380 replaceFPWithRealFP(MF);
382 // Check if the link register (LR) must be saved.
383 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
384 bool MustSaveLR = FI->mustSaveLR();
385 const SmallVectorImpl<unsigned> &MustSaveCRs = FI->getMustSaveCRs();
386 // Do we have a frame pointer and/or base pointer for this function?
387 bool HasFP = hasFP(MF);
388 bool HasBP = RegInfo->hasBasePointer(MF);
390 unsigned SPReg = isPPC64 ? PPC::X1 : PPC::R1;
391 unsigned BPReg = RegInfo->getBaseRegister(MF);
392 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31;
393 unsigned LRReg = isPPC64 ? PPC::LR8 : PPC::LR;
394 unsigned ScratchReg = isPPC64 ? PPC::X0 : PPC::R0;
395 unsigned TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg
396 // ...(R12/X12 is volatile in both Darwin & SVR4, & can't be a function arg.)
397 const MCInstrDesc& MFLRInst = TII.get(isPPC64 ? PPC::MFLR8
399 const MCInstrDesc& StoreInst = TII.get(isPPC64 ? PPC::STD
401 const MCInstrDesc& StoreUpdtInst = TII.get(isPPC64 ? PPC::STDU
403 const MCInstrDesc& StoreUpdtIdxInst = TII.get(isPPC64 ? PPC::STDUX
405 const MCInstrDesc& LoadImmShiftedInst = TII.get(isPPC64 ? PPC::LIS8
407 const MCInstrDesc& OrImmInst = TII.get(isPPC64 ? PPC::ORI8
409 const MCInstrDesc& OrInst = TII.get(isPPC64 ? PPC::OR8
411 const MCInstrDesc& SubtractCarryingInst = TII.get(isPPC64 ? PPC::SUBFC8
413 const MCInstrDesc& SubtractImmCarryingInst = TII.get(isPPC64 ? PPC::SUBFIC8
416 // Regarding this assert: Even though LR is saved in the caller's frame (i.e.,
417 // LROffset is positive), that slot is callee-owned. Because PPC32 SVR4 has no
418 // Red Zone, an asynchronous event (a form of "callee") could claim a frame &
419 // overwrite it, so PPC32 SVR4 must claim at least a minimal frame to save LR.
420 assert((isPPC64 || !isSVR4ABI || !(!FrameSize && (MustSaveLR || HasFP))) &&
421 "FrameSize must be >0 to save/restore the FP or LR for 32-bit SVR4.");
423 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
428 MachineFrameInfo *FFI = MF.getFrameInfo();
429 int FPIndex = FI->getFramePointerSaveIndex();
430 assert(FPIndex && "No Frame Pointer Save Slot!");
431 FPOffset = FFI->getObjectOffset(FPIndex);
433 FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
440 MachineFrameInfo *FFI = MF.getFrameInfo();
441 int BPIndex = FI->getBasePointerSaveIndex();
442 assert(BPIndex && "No Base Pointer Save Slot!");
443 BPOffset = FFI->getObjectOffset(BPIndex);
446 PPCFrameLowering::getBasePointerSaveOffset(isPPC64,
452 // Get stack alignments.
453 unsigned MaxAlign = MFI->getMaxAlignment();
454 if (HasBP && MaxAlign > 1)
455 assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) &&
456 "Invalid alignment!");
458 // Frames of 32KB & larger require special handling because they cannot be
459 // indexed into with a simple STDU/STWU/STD/STW immediate offset operand.
460 bool isLargeFrame = !isInt<16>(NegFrameSize);
463 BuildMI(MBB, MBBI, dl, MFLRInst, ScratchReg);
465 assert((isPPC64 || MustSaveCRs.empty()) &&
466 "Prologue CR saving supported only in 64-bit mode");
468 if (!MustSaveCRs.empty()) { // will only occur for PPC64
469 MachineInstrBuilder MIB =
470 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFCR8), TempReg);
471 for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)
472 MIB.addReg(MustSaveCRs[i], RegState::ImplicitKill);
476 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
477 BuildMI(MBB, MBBI, dl, StoreInst)
483 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
484 BuildMI(MBB, MBBI, dl, StoreInst)
490 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
491 BuildMI(MBB, MBBI, dl, StoreInst)
496 if (!MustSaveCRs.empty()) // will only occur for PPC64
497 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW8))
498 .addReg(TempReg, getKillRegState(true))
502 // Skip the rest if this is a leaf function & all spills fit in the Red Zone.
503 if (!FrameSize) return;
505 // Adjust stack pointer: r1 += NegFrameSize.
506 // If there is a preferred stack alignment, align R1 now
509 // Save a copy of r1 as the base pointer.
510 BuildMI(MBB, MBBI, dl, OrInst, BPReg)
515 if (HasBP && MaxAlign > 1) {
517 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), ScratchReg)
520 .addImm(64 - Log2_32(MaxAlign));
522 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), ScratchReg)
525 .addImm(32 - Log2_32(MaxAlign))
528 BuildMI(MBB, MBBI, dl, SubtractImmCarryingInst, ScratchReg)
529 .addReg(ScratchReg, RegState::Kill)
530 .addImm(NegFrameSize);
532 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, TempReg)
533 .addImm(NegFrameSize >> 16);
534 BuildMI(MBB, MBBI, dl, OrImmInst, TempReg)
535 .addReg(TempReg, RegState::Kill)
536 .addImm(NegFrameSize & 0xFFFF);
537 BuildMI(MBB, MBBI, dl, SubtractCarryingInst, ScratchReg)
538 .addReg(ScratchReg, RegState::Kill)
539 .addReg(TempReg, RegState::Kill);
541 BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg)
542 .addReg(SPReg, RegState::Kill)
546 } else if (!isLargeFrame) {
547 BuildMI(MBB, MBBI, dl, StoreUpdtInst, SPReg)
549 .addImm(NegFrameSize)
553 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
554 .addImm(NegFrameSize >> 16);
555 BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
556 .addReg(ScratchReg, RegState::Kill)
557 .addImm(NegFrameSize & 0xFFFF);
558 BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg)
559 .addReg(SPReg, RegState::Kill)
564 // Add the "machine moves" for the instructions we generated above, but in
566 if (needsFrameMoves) {
567 // Mark effective beginning of when frame pointer becomes valid.
568 FrameLabel = MMI.getContext().CreateTempSymbol();
569 BuildMI(MBB, MBBI, dl, TII.get(PPC::PROLOG_LABEL)).addSym(FrameLabel);
571 // Show update of SP.
572 assert(NegFrameSize);
574 MCCFIInstruction::createDefCfaOffset(FrameLabel, NegFrameSize));
577 unsigned Reg = MRI->getDwarfRegNum(FPReg, true);
579 MCCFIInstruction::createOffset(FrameLabel, Reg, FPOffset));
583 unsigned Reg = MRI->getDwarfRegNum(BPReg, true);
585 MCCFIInstruction::createOffset(FrameLabel, Reg, BPOffset));
589 unsigned Reg = MRI->getDwarfRegNum(LRReg, true);
591 MCCFIInstruction::createOffset(FrameLabel, Reg, LROffset));
595 MCSymbol *ReadyLabel = 0;
597 // If there is a frame pointer, copy R1 into R31
599 BuildMI(MBB, MBBI, dl, OrInst, FPReg)
603 if (needsFrameMoves) {
604 ReadyLabel = MMI.getContext().CreateTempSymbol();
606 // Mark effective beginning of when frame pointer is ready.
607 BuildMI(MBB, MBBI, dl, TII.get(PPC::PROLOG_LABEL)).addSym(ReadyLabel);
609 unsigned Reg = MRI->getDwarfRegNum(FPReg, true);
610 MMI.addFrameInst(MCCFIInstruction::createDefCfaRegister(ReadyLabel, Reg));
614 if (needsFrameMoves) {
615 MCSymbol *Label = HasFP ? ReadyLabel : FrameLabel;
617 // Add callee saved registers to move list.
618 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
619 for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
620 unsigned Reg = CSI[I].getReg();
621 if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue;
623 // This is a bit of a hack: CR2LT, CR2GT, CR2EQ and CR2UN are just
624 // subregisters of CR2. We just need to emit a move of CR2.
625 if (PPC::CRBITRCRegClass.contains(Reg))
628 // For SVR4, don't emit a move for the CR spill slot if we haven't
630 if (isSVR4ABI && (PPC::CR2 <= Reg && Reg <= PPC::CR4)
631 && MustSaveCRs.empty())
634 // For 64-bit SVR4 when we have spilled CRs, the spill location
635 // is SP+8, not a frame-relative slot.
636 if (isSVR4ABI && isPPC64 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
637 MMI.addFrameInst(MCCFIInstruction::createOffset(
638 Label, MRI->getDwarfRegNum(PPC::CR2, true), 8));
642 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
643 MMI.addFrameInst(MCCFIInstruction::createOffset(
644 Label, MRI->getDwarfRegNum(Reg, true), Offset));
649 void PPCFrameLowering::emitEpilogue(MachineFunction &MF,
650 MachineBasicBlock &MBB) const {
651 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
652 assert(MBBI != MBB.end() && "Returning block has no terminator");
653 const PPCInstrInfo &TII =
654 *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo());
655 const PPCRegisterInfo *RegInfo =
656 static_cast<const PPCRegisterInfo*>(MF.getTarget().getRegisterInfo());
658 unsigned RetOpcode = MBBI->getOpcode();
661 assert((RetOpcode == PPC::BLR ||
662 RetOpcode == PPC::TCRETURNri ||
663 RetOpcode == PPC::TCRETURNdi ||
664 RetOpcode == PPC::TCRETURNai ||
665 RetOpcode == PPC::TCRETURNri8 ||
666 RetOpcode == PPC::TCRETURNdi8 ||
667 RetOpcode == PPC::TCRETURNai8) &&
668 "Can only insert epilog into returning blocks");
670 // Get alignment info so we know how to restore the SP.
671 const MachineFrameInfo *MFI = MF.getFrameInfo();
673 // Get the number of bytes allocated from the FrameInfo.
674 int FrameSize = MFI->getStackSize();
676 // Get processor type.
677 bool isPPC64 = Subtarget.isPPC64();
679 bool isDarwinABI = Subtarget.isDarwinABI();
680 bool isSVR4ABI = Subtarget.isSVR4ABI();
681 bool isPIC = MF.getTarget().getRelocationModel() == Reloc::PIC_;
683 // Check if the link register (LR) has been saved.
684 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
685 bool MustSaveLR = FI->mustSaveLR();
686 const SmallVectorImpl<unsigned> &MustSaveCRs = FI->getMustSaveCRs();
687 // Do we have a frame pointer and/or base pointer for this function?
688 bool HasFP = hasFP(MF);
689 bool HasBP = RegInfo->hasBasePointer(MF);
691 unsigned SPReg = isPPC64 ? PPC::X1 : PPC::R1;
692 unsigned BPReg = RegInfo->getBaseRegister(MF);
693 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31;
694 unsigned ScratchReg = isPPC64 ? PPC::X0 : PPC::R0;
695 unsigned TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg
696 const MCInstrDesc& MTLRInst = TII.get( isPPC64 ? PPC::MTLR8
698 const MCInstrDesc& LoadInst = TII.get( isPPC64 ? PPC::LD
700 const MCInstrDesc& LoadImmShiftedInst = TII.get( isPPC64 ? PPC::LIS8
702 const MCInstrDesc& OrImmInst = TII.get( isPPC64 ? PPC::ORI8
704 const MCInstrDesc& AddImmInst = TII.get( isPPC64 ? PPC::ADDI8
706 const MCInstrDesc& AddInst = TII.get( isPPC64 ? PPC::ADD8
709 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
714 MachineFrameInfo *FFI = MF.getFrameInfo();
715 int FPIndex = FI->getFramePointerSaveIndex();
716 assert(FPIndex && "No Frame Pointer Save Slot!");
717 FPOffset = FFI->getObjectOffset(FPIndex);
719 FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
726 MachineFrameInfo *FFI = MF.getFrameInfo();
727 int BPIndex = FI->getBasePointerSaveIndex();
728 assert(BPIndex && "No Base Pointer Save Slot!");
729 BPOffset = FFI->getObjectOffset(BPIndex);
732 PPCFrameLowering::getBasePointerSaveOffset(isPPC64,
738 bool UsesTCRet = RetOpcode == PPC::TCRETURNri ||
739 RetOpcode == PPC::TCRETURNdi ||
740 RetOpcode == PPC::TCRETURNai ||
741 RetOpcode == PPC::TCRETURNri8 ||
742 RetOpcode == PPC::TCRETURNdi8 ||
743 RetOpcode == PPC::TCRETURNai8;
746 int MaxTCRetDelta = FI->getTailCallSPDelta();
747 MachineOperand &StackAdjust = MBBI->getOperand(1);
748 assert(StackAdjust.isImm() && "Expecting immediate value.");
749 // Adjust stack pointer.
750 int StackAdj = StackAdjust.getImm();
751 int Delta = StackAdj - MaxTCRetDelta;
752 assert((Delta >= 0) && "Delta must be positive");
754 FrameSize += (StackAdj +Delta);
756 FrameSize += StackAdj;
759 // Frames of 32KB & larger require special handling because they cannot be
760 // indexed into with a simple LD/LWZ immediate offset operand.
761 bool isLargeFrame = !isInt<16>(FrameSize);
764 // In the prologue, the loaded (or persistent) stack pointer value is offset
765 // by the STDU/STDUX/STWU/STWUX instruction. Add this offset back now.
767 // If this function contained a fastcc call and GuaranteedTailCallOpt is
768 // enabled (=> hasFastCall()==true) the fastcc call might contain a tail
769 // call which invalidates the stack pointer value in SP(0). So we use the
770 // value of R31 in this case.
771 if (FI->hasFastCall()) {
772 assert(HasFP && "Expecting a valid frame pointer.");
774 BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
775 .addReg(FPReg).addImm(FrameSize);
777 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
778 .addImm(FrameSize >> 16);
779 BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
780 .addReg(ScratchReg, RegState::Kill)
781 .addImm(FrameSize & 0xFFFF);
782 BuildMI(MBB, MBBI, dl, AddInst)
787 } else if (!isLargeFrame && !HasBP && !MFI->hasVarSizedObjects()) {
788 BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
792 BuildMI(MBB, MBBI, dl, LoadInst, SPReg)
800 BuildMI(MBB, MBBI, dl, LoadInst, ScratchReg)
804 assert((isPPC64 || MustSaveCRs.empty()) &&
805 "Epilogue CR restoring supported only in 64-bit mode");
807 if (!MustSaveCRs.empty()) // will only occur for PPC64
808 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ8), TempReg)
813 BuildMI(MBB, MBBI, dl, LoadInst, FPReg)
818 BuildMI(MBB, MBBI, dl, LoadInst, BPReg)
822 if (!MustSaveCRs.empty()) // will only occur for PPC64
823 for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)
824 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTOCRF8), MustSaveCRs[i])
825 .addReg(TempReg, getKillRegState(i == e-1));
828 BuildMI(MBB, MBBI, dl, MTLRInst).addReg(ScratchReg);
830 // Callee pop calling convention. Pop parameter/linkage area. Used for tail
832 if (MF.getTarget().Options.GuaranteedTailCallOpt && RetOpcode == PPC::BLR &&
833 MF.getFunction()->getCallingConv() == CallingConv::Fast) {
834 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
835 unsigned CallerAllocatedAmt = FI->getMinReservedArea();
837 if (CallerAllocatedAmt && isInt<16>(CallerAllocatedAmt)) {
838 BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
839 .addReg(SPReg).addImm(CallerAllocatedAmt);
841 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
842 .addImm(CallerAllocatedAmt >> 16);
843 BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
844 .addReg(ScratchReg, RegState::Kill)
845 .addImm(CallerAllocatedAmt & 0xFFFF);
846 BuildMI(MBB, MBBI, dl, AddInst)
851 } else if (RetOpcode == PPC::TCRETURNdi) {
852 MBBI = MBB.getLastNonDebugInstr();
853 MachineOperand &JumpTarget = MBBI->getOperand(0);
854 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)).
855 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
856 } else if (RetOpcode == PPC::TCRETURNri) {
857 MBBI = MBB.getLastNonDebugInstr();
858 assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
859 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR));
860 } else if (RetOpcode == PPC::TCRETURNai) {
861 MBBI = MBB.getLastNonDebugInstr();
862 MachineOperand &JumpTarget = MBBI->getOperand(0);
863 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm());
864 } else if (RetOpcode == PPC::TCRETURNdi8) {
865 MBBI = MBB.getLastNonDebugInstr();
866 MachineOperand &JumpTarget = MBBI->getOperand(0);
867 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)).
868 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
869 } else if (RetOpcode == PPC::TCRETURNri8) {
870 MBBI = MBB.getLastNonDebugInstr();
871 assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
872 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8));
873 } else if (RetOpcode == PPC::TCRETURNai8) {
874 MBBI = MBB.getLastNonDebugInstr();
875 MachineOperand &JumpTarget = MBBI->getOperand(0);
876 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm());
880 /// MustSaveLR - Return true if this function requires that we save the LR
881 /// register onto the stack in the prolog and restore it in the epilog of the
883 static bool MustSaveLR(const MachineFunction &MF, unsigned LR) {
884 const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>();
886 // We need a save/restore of LR if there is any def of LR (which is
887 // defined by calls, including the PIC setup sequence), or if there is
888 // some use of the LR stack slot (e.g. for builtin_return_address).
889 // (LR comes in 32 and 64 bit versions.)
890 MachineRegisterInfo::def_iterator RI = MF.getRegInfo().def_begin(LR);
891 return RI !=MF.getRegInfo().def_end() || MFI->isLRStoreRequired();
895 PPCFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
896 RegScavenger *) const {
897 const PPCRegisterInfo *RegInfo =
898 static_cast<const PPCRegisterInfo*>(MF.getTarget().getRegisterInfo());
900 // Save and clear the LR state.
901 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
902 unsigned LR = RegInfo->getRARegister();
903 FI->setMustSaveLR(MustSaveLR(MF, LR));
904 MachineRegisterInfo &MRI = MF.getRegInfo();
905 MRI.setPhysRegUnused(LR);
907 // Save R31 if necessary
908 int FPSI = FI->getFramePointerSaveIndex();
909 bool isPPC64 = Subtarget.isPPC64();
910 bool isDarwinABI = Subtarget.isDarwinABI();
911 bool isPIC = MF.getTarget().getRelocationModel() == Reloc::PIC_;
912 MachineFrameInfo *MFI = MF.getFrameInfo();
914 // If the frame pointer save index hasn't been defined yet.
915 if (!FPSI && needsFP(MF)) {
916 // Find out what the fix offset of the frame pointer save area.
917 int FPOffset = getFramePointerSaveOffset(isPPC64, isDarwinABI);
918 // Allocate the frame index for frame pointer save area.
919 FPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
921 FI->setFramePointerSaveIndex(FPSI);
924 int BPSI = FI->getBasePointerSaveIndex();
925 if (!BPSI && RegInfo->hasBasePointer(MF)) {
926 int BPOffset = getBasePointerSaveOffset(isPPC64, isDarwinABI, isPIC);
927 // Allocate the frame index for the base pointer save area.
928 BPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, BPOffset, true);
930 FI->setBasePointerSaveIndex(BPSI);
933 // Reserve stack space to move the linkage area to in case of a tail call.
935 if (MF.getTarget().Options.GuaranteedTailCallOpt &&
936 (TCSPDelta = FI->getTailCallSPDelta()) < 0) {
937 MFI->CreateFixedObject(-1 * TCSPDelta, TCSPDelta, true);
940 // For 32-bit SVR4, allocate the nonvolatile CR spill slot iff the
941 // function uses CR 2, 3, or 4.
942 if (!isPPC64 && !isDarwinABI &&
943 (MRI.isPhysRegUsed(PPC::CR2) ||
944 MRI.isPhysRegUsed(PPC::CR3) ||
945 MRI.isPhysRegUsed(PPC::CR4))) {
946 int FrameIdx = MFI->CreateFixedObject((uint64_t)4, (int64_t)-4, true);
947 FI->setCRSpillFrameIndex(FrameIdx);
951 void PPCFrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF,
952 RegScavenger *RS) const {
953 // Early exit if not using the SVR4 ABI.
954 if (!Subtarget.isSVR4ABI()) {
955 addScavengingSpillSlot(MF, RS);
959 // Get callee saved register information.
960 MachineFrameInfo *FFI = MF.getFrameInfo();
961 const std::vector<CalleeSavedInfo> &CSI = FFI->getCalleeSavedInfo();
963 // Early exit if no callee saved registers are modified!
964 if (CSI.empty() && !needsFP(MF)) {
965 addScavengingSpillSlot(MF, RS);
969 unsigned MinGPR = PPC::R31;
970 unsigned MinG8R = PPC::X31;
971 unsigned MinFPR = PPC::F31;
972 unsigned MinVR = PPC::V31;
974 bool HasGPSaveArea = false;
975 bool HasG8SaveArea = false;
976 bool HasFPSaveArea = false;
977 bool HasVRSAVESaveArea = false;
978 bool HasVRSaveArea = false;
980 SmallVector<CalleeSavedInfo, 18> GPRegs;
981 SmallVector<CalleeSavedInfo, 18> G8Regs;
982 SmallVector<CalleeSavedInfo, 18> FPRegs;
983 SmallVector<CalleeSavedInfo, 18> VRegs;
985 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
986 unsigned Reg = CSI[i].getReg();
987 if (PPC::GPRCRegClass.contains(Reg)) {
988 HasGPSaveArea = true;
990 GPRegs.push_back(CSI[i]);
995 } else if (PPC::G8RCRegClass.contains(Reg)) {
996 HasG8SaveArea = true;
998 G8Regs.push_back(CSI[i]);
1003 } else if (PPC::F8RCRegClass.contains(Reg)) {
1004 HasFPSaveArea = true;
1006 FPRegs.push_back(CSI[i]);
1011 } else if (PPC::CRBITRCRegClass.contains(Reg) ||
1012 PPC::CRRCRegClass.contains(Reg)) {
1013 ; // do nothing, as we already know whether CRs are spilled
1014 } else if (PPC::VRSAVERCRegClass.contains(Reg)) {
1015 HasVRSAVESaveArea = true;
1016 } else if (PPC::VRRCRegClass.contains(Reg)) {
1017 HasVRSaveArea = true;
1019 VRegs.push_back(CSI[i]);
1025 llvm_unreachable("Unknown RegisterClass!");
1029 PPCFunctionInfo *PFI = MF.getInfo<PPCFunctionInfo>();
1030 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
1032 int64_t LowerBound = 0;
1034 // Take into account stack space reserved for tail calls.
1036 if (MF.getTarget().Options.GuaranteedTailCallOpt &&
1037 (TCSPDelta = PFI->getTailCallSPDelta()) < 0) {
1038 LowerBound = TCSPDelta;
1041 // The Floating-point register save area is right below the back chain word
1042 // of the previous stack frame.
1043 if (HasFPSaveArea) {
1044 for (unsigned i = 0, e = FPRegs.size(); i != e; ++i) {
1045 int FI = FPRegs[i].getFrameIdx();
1047 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1050 LowerBound -= (31 - TRI->getEncodingValue(MinFPR) + 1) * 8;
1053 // Check whether the frame pointer register is allocated. If so, make sure it
1054 // is spilled to the correct offset.
1056 HasGPSaveArea = true;
1058 int FI = PFI->getFramePointerSaveIndex();
1059 assert(FI && "No Frame Pointer Save Slot!");
1061 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1064 const PPCRegisterInfo *RegInfo =
1065 static_cast<const PPCRegisterInfo*>(MF.getTarget().getRegisterInfo());
1066 if (RegInfo->hasBasePointer(MF)) {
1067 HasGPSaveArea = true;
1069 int FI = PFI->getBasePointerSaveIndex();
1070 assert(FI && "No Base Pointer Save Slot!");
1072 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1075 // General register save area starts right below the Floating-point
1076 // register save area.
1077 if (HasGPSaveArea || HasG8SaveArea) {
1078 // Move general register save area spill slots down, taking into account
1079 // the size of the Floating-point register save area.
1080 for (unsigned i = 0, e = GPRegs.size(); i != e; ++i) {
1081 int FI = GPRegs[i].getFrameIdx();
1083 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1086 // Move general register save area spill slots down, taking into account
1087 // the size of the Floating-point register save area.
1088 for (unsigned i = 0, e = G8Regs.size(); i != e; ++i) {
1089 int FI = G8Regs[i].getFrameIdx();
1091 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1095 std::min<unsigned>(TRI->getEncodingValue(MinGPR),
1096 TRI->getEncodingValue(MinG8R));
1098 if (Subtarget.isPPC64()) {
1099 LowerBound -= (31 - MinReg + 1) * 8;
1101 LowerBound -= (31 - MinReg + 1) * 4;
1105 // For 32-bit only, the CR save area is below the general register
1106 // save area. For 64-bit SVR4, the CR save area is addressed relative
1107 // to the stack pointer and hence does not need an adjustment here.
1108 // Only CR2 (the first nonvolatile spilled) has an associated frame
1109 // index so that we have a single uniform save area.
1110 if (spillsCR(MF) && !(Subtarget.isPPC64() && Subtarget.isSVR4ABI())) {
1111 // Adjust the frame index of the CR spill slot.
1112 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1113 unsigned Reg = CSI[i].getReg();
1115 if ((Subtarget.isSVR4ABI() && Reg == PPC::CR2)
1116 // Leave Darwin logic as-is.
1117 || (!Subtarget.isSVR4ABI() &&
1118 (PPC::CRBITRCRegClass.contains(Reg) ||
1119 PPC::CRRCRegClass.contains(Reg)))) {
1120 int FI = CSI[i].getFrameIdx();
1122 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1126 LowerBound -= 4; // The CR save area is always 4 bytes long.
1129 if (HasVRSAVESaveArea) {
1130 // FIXME SVR4: Is it actually possible to have multiple elements in CSI
1131 // which have the VRSAVE register class?
1132 // Adjust the frame index of the VRSAVE spill slot.
1133 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1134 unsigned Reg = CSI[i].getReg();
1136 if (PPC::VRSAVERCRegClass.contains(Reg)) {
1137 int FI = CSI[i].getFrameIdx();
1139 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1143 LowerBound -= 4; // The VRSAVE save area is always 4 bytes long.
1146 if (HasVRSaveArea) {
1147 // Insert alignment padding, we need 16-byte alignment.
1148 LowerBound = (LowerBound - 15) & ~(15);
1150 for (unsigned i = 0, e = VRegs.size(); i != e; ++i) {
1151 int FI = VRegs[i].getFrameIdx();
1153 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1157 addScavengingSpillSlot(MF, RS);
1161 PPCFrameLowering::addScavengingSpillSlot(MachineFunction &MF,
1162 RegScavenger *RS) const {
1163 // Reserve a slot closest to SP or frame pointer if we have a dynalloc or
1164 // a large stack, which will require scavenging a register to materialize a
1167 // We need to have a scavenger spill slot for spills if the frame size is
1168 // large. In case there is no free register for large-offset addressing,
1169 // this slot is used for the necessary emergency spill. Also, we need the
1170 // slot for dynamic stack allocations.
1172 // The scavenger might be invoked if the frame offset does not fit into
1173 // the 16-bit immediate. We don't know the complete frame size here
1174 // because we've not yet computed callee-saved register spills or the
1175 // needed alignment padding.
1176 unsigned StackSize = determineFrameLayout(MF, false, true);
1177 MachineFrameInfo *MFI = MF.getFrameInfo();
1178 if (MFI->hasVarSizedObjects() || spillsCR(MF) || spillsVRSAVE(MF) ||
1179 hasNonRISpills(MF) || (hasSpills(MF) && !isInt<16>(StackSize))) {
1180 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
1181 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
1182 const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC;
1183 RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
1187 // Might we have over-aligned allocas?
1188 bool HasAlVars = MFI->hasVarSizedObjects() &&
1189 MFI->getMaxAlignment() > getStackAlignment();
1191 // These kinds of spills might need two registers.
1192 if (spillsCR(MF) || spillsVRSAVE(MF) || HasAlVars)
1193 RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
1201 PPCFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
1202 MachineBasicBlock::iterator MI,
1203 const std::vector<CalleeSavedInfo> &CSI,
1204 const TargetRegisterInfo *TRI) const {
1206 // Currently, this function only handles SVR4 32- and 64-bit ABIs.
1207 // Return false otherwise to maintain pre-existing behavior.
1208 if (!Subtarget.isSVR4ABI())
1211 MachineFunction *MF = MBB.getParent();
1212 const PPCInstrInfo &TII =
1213 *static_cast<const PPCInstrInfo*>(MF->getTarget().getInstrInfo());
1215 bool CRSpilled = false;
1216 MachineInstrBuilder CRMIB;
1218 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1219 unsigned Reg = CSI[i].getReg();
1220 // Only Darwin actually uses the VRSAVE register, but it can still appear
1221 // here if, for example, @llvm.eh.unwind.init() is used. If we're not on
1222 // Darwin, ignore it.
1223 if (Reg == PPC::VRSAVE && !Subtarget.isDarwinABI())
1226 // CR2 through CR4 are the nonvolatile CR fields.
1227 bool IsCRField = PPC::CR2 <= Reg && Reg <= PPC::CR4;
1229 // Add the callee-saved register as live-in; it's killed at the spill.
1232 if (CRSpilled && IsCRField) {
1233 CRMIB.addReg(Reg, RegState::ImplicitKill);
1237 // Insert the spill to the stack frame.
1239 PPCFunctionInfo *FuncInfo = MF->getInfo<PPCFunctionInfo>();
1240 if (Subtarget.isPPC64()) {
1241 // The actual spill will happen at the start of the prologue.
1242 FuncInfo->addMustSaveCR(Reg);
1245 FuncInfo->setSpillsCR();
1247 // 32-bit: FP-relative. Note that we made sure CR2-CR4 all have
1248 // the same frame index in PPCRegisterInfo::hasReservedSpillSlot.
1249 CRMIB = BuildMI(*MF, DL, TII.get(PPC::MFCR), PPC::R12)
1250 .addReg(Reg, RegState::ImplicitKill);
1252 MBB.insert(MI, CRMIB);
1253 MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::STW))
1255 getKillRegState(true)),
1256 CSI[i].getFrameIdx()));
1259 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1260 TII.storeRegToStackSlot(MBB, MI, Reg, true,
1261 CSI[i].getFrameIdx(), RC, TRI);
1268 restoreCRs(bool isPPC64, bool is31,
1269 bool CR2Spilled, bool CR3Spilled, bool CR4Spilled,
1270 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
1271 const std::vector<CalleeSavedInfo> &CSI, unsigned CSIIndex) {
1273 MachineFunction *MF = MBB.getParent();
1274 const PPCInstrInfo &TII =
1275 *static_cast<const PPCInstrInfo*>(MF->getTarget().getInstrInfo());
1277 unsigned RestoreOp, MoveReg;
1280 // This is handled during epilogue generation.
1283 // 32-bit: FP-relative
1284 MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::LWZ),
1286 CSI[CSIIndex].getFrameIdx()));
1287 RestoreOp = PPC::MTOCRF;
1292 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR2)
1293 .addReg(MoveReg, getKillRegState(!CR3Spilled && !CR4Spilled)));
1296 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR3)
1297 .addReg(MoveReg, getKillRegState(!CR4Spilled)));
1300 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR4)
1301 .addReg(MoveReg, getKillRegState(true)));
1304 void PPCFrameLowering::
1305 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1306 MachineBasicBlock::iterator I) const {
1307 const PPCInstrInfo &TII =
1308 *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo());
1309 if (MF.getTarget().Options.GuaranteedTailCallOpt &&
1310 I->getOpcode() == PPC::ADJCALLSTACKUP) {
1311 // Add (actually subtract) back the amount the callee popped on return.
1312 if (int CalleeAmt = I->getOperand(1).getImm()) {
1313 bool is64Bit = Subtarget.isPPC64();
1315 unsigned StackReg = is64Bit ? PPC::X1 : PPC::R1;
1316 unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0;
1317 unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI;
1318 unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4;
1319 unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS;
1320 unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI;
1321 MachineInstr *MI = I;
1322 DebugLoc dl = MI->getDebugLoc();
1324 if (isInt<16>(CalleeAmt)) {
1325 BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg)
1326 .addReg(StackReg, RegState::Kill)
1329 MachineBasicBlock::iterator MBBI = I;
1330 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg)
1331 .addImm(CalleeAmt >> 16);
1332 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg)
1333 .addReg(TmpReg, RegState::Kill)
1334 .addImm(CalleeAmt & 0xFFFF);
1335 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr), StackReg)
1336 .addReg(StackReg, RegState::Kill)
1341 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
1346 PPCFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
1347 MachineBasicBlock::iterator MI,
1348 const std::vector<CalleeSavedInfo> &CSI,
1349 const TargetRegisterInfo *TRI) const {
1351 // Currently, this function only handles SVR4 32- and 64-bit ABIs.
1352 // Return false otherwise to maintain pre-existing behavior.
1353 if (!Subtarget.isSVR4ABI())
1356 MachineFunction *MF = MBB.getParent();
1357 const PPCInstrInfo &TII =
1358 *static_cast<const PPCInstrInfo*>(MF->getTarget().getInstrInfo());
1359 bool CR2Spilled = false;
1360 bool CR3Spilled = false;
1361 bool CR4Spilled = false;
1362 unsigned CSIIndex = 0;
1364 // Initialize insertion-point logic; we will be restoring in reverse
1366 MachineBasicBlock::iterator I = MI, BeforeI = I;
1367 bool AtStart = I == MBB.begin();
1372 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1373 unsigned Reg = CSI[i].getReg();
1375 // Only Darwin actually uses the VRSAVE register, but it can still appear
1376 // here if, for example, @llvm.eh.unwind.init() is used. If we're not on
1377 // Darwin, ignore it.
1378 if (Reg == PPC::VRSAVE && !Subtarget.isDarwinABI())
1381 if (Reg == PPC::CR2) {
1383 // The spill slot is associated only with CR2, which is the
1384 // first nonvolatile spilled. Save it here.
1387 } else if (Reg == PPC::CR3) {
1390 } else if (Reg == PPC::CR4) {
1394 // When we first encounter a non-CR register after seeing at
1395 // least one CR register, restore all spilled CRs together.
1396 if ((CR2Spilled || CR3Spilled || CR4Spilled)
1397 && !(PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
1398 bool is31 = needsFP(*MF);
1399 restoreCRs(Subtarget.isPPC64(), is31,
1400 CR2Spilled, CR3Spilled, CR4Spilled,
1401 MBB, I, CSI, CSIIndex);
1402 CR2Spilled = CR3Spilled = CR4Spilled = false;
1405 // Default behavior for non-CR saves.
1406 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1407 TII.loadRegFromStackSlot(MBB, I, Reg, CSI[i].getFrameIdx(),
1409 assert(I != MBB.begin() &&
1410 "loadRegFromStackSlot didn't insert any code!");
1413 // Insert in reverse order.
1422 // If we haven't yet spilled the CRs, do so now.
1423 if (CR2Spilled || CR3Spilled || CR4Spilled) {
1424 bool is31 = needsFP(*MF);
1425 restoreCRs(Subtarget.isPPC64(), is31, CR2Spilled, CR3Spilled, CR4Spilled,
1426 MBB, I, CSI, CSIIndex);