1 //===-- PPCFrameLowering.h - Define frame lowering for PowerPC --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 #ifndef LLVM_LIB_TARGET_POWERPC_PPCFRAMELOWERING_H
14 #define LLVM_LIB_TARGET_POWERPC_PPCFRAMELOWERING_H
17 #include "llvm/ADT/STLExtras.h"
18 #include "llvm/CodeGen/TargetFrameLowering.h"
19 #include "llvm/Target/TargetMachine.h"
24 class PPCFrameLowering: public TargetFrameLowering {
25 const PPCSubtarget &Subtarget;
26 const unsigned ReturnSaveOffset;
27 const unsigned TOCSaveOffset;
28 const unsigned FramePointerSaveOffset;
29 const unsigned LinkageSize;
30 const unsigned BasePointerSaveOffset;
33 * Find register[s] that can be used in function prologue and epilogue
35 * Find register[s] that can be use as scratch register[s] in function
36 * prologue and epilogue to save various registers (Link Register, Base
37 * Pointer, etc.). Prefer R0/R12, if available. Otherwise choose whatever
38 * register[s] are available.
40 * This method will return true if it is able to find enough unique scratch
41 * registers (1 or 2 depending on the requirement). If it is unable to find
42 * enough available registers in the block, it will return false and set
43 * any passed output parameter that corresponds to a required unique register
46 * \param[in] MBB The machine basic block to find an available register for
47 * \param[in] UseAtEnd Specify whether the scratch register will be used at
48 * the end of the basic block (i.e., will the scratch
49 * register kill a register defined in the basic block)
50 * \param[in] TwoUniqueRegsRequired Specify whether this basic block will
51 * require two unique scratch registers.
52 * \param[out] SR1 The scratch register to use
53 * \param[out] SR2 The second scratch register. If this pointer is not null
54 * the function will attempt to set it to an available
55 * register regardless of whether there is a hard requirement
56 * for two unique scratch registers.
57 * \return true if the required number of registers was found.
58 * false if the required number of scratch register weren't available.
59 * If either output parameter refers to a required scratch register
60 * that isn't available, it will be set to an invalid value.
62 bool findScratchRegister(MachineBasicBlock *MBB,
64 bool TwoUniqueRegsRequired = false,
65 unsigned *SR1 = nullptr,
66 unsigned *SR2 = nullptr) const;
67 bool twoUniqueScratchRegsRequired(MachineBasicBlock *MBB) const;
70 * Create branch instruction for PPC::TCRETURN* (tail call return)
72 * \param[in] MBB that is terminated by PPC::TCRETURN*
74 void createTailCallBranchInstr(MachineBasicBlock &MBB) const;
77 PPCFrameLowering(const PPCSubtarget &STI);
79 unsigned determineFrameLayout(MachineFunction &MF,
81 bool UseEstimate = false) const;
83 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
85 void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
86 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
88 bool hasFP(const MachineFunction &MF) const override;
89 bool needsFP(const MachineFunction &MF) const;
90 void replaceFPWithRealFP(MachineFunction &MF) const;
92 void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs,
93 RegScavenger *RS = nullptr) const override;
94 void processFunctionBeforeFrameFinalized(MachineFunction &MF,
95 RegScavenger *RS = nullptr) const override;
96 void addScavengingSpillSlot(MachineFunction &MF, RegScavenger *RS) const;
98 bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
99 MachineBasicBlock::iterator MI,
100 const std::vector<CalleeSavedInfo> &CSI,
101 const TargetRegisterInfo *TRI) const override;
102 /// This function will assign callee saved gprs to volatile vector registers
103 /// for prologue spills when applicable. It returns false if there are any
104 /// registers which were not spilled to volatile vector registers.
106 assignCalleeSavedSpillSlots(MachineFunction &MF,
107 const TargetRegisterInfo *TRI,
108 std::vector<CalleeSavedInfo> &CSI) const override;
110 MachineBasicBlock::iterator
111 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
112 MachineBasicBlock::iterator I) const override;
114 bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
115 MachineBasicBlock::iterator MI,
116 std::vector<CalleeSavedInfo> &CSI,
117 const TargetRegisterInfo *TRI) const override;
119 /// targetHandlesStackFrameRounding - Returns true if the target is
120 /// responsible for rounding up the stack frame (probably at emitPrologue
122 bool targetHandlesStackFrameRounding() const override { return true; }
124 /// getReturnSaveOffset - Return the previous frame offset to save the
126 unsigned getReturnSaveOffset() const { return ReturnSaveOffset; }
128 /// getTOCSaveOffset - Return the previous frame offset to save the
129 /// TOC register -- 64-bit SVR4 ABI only.
130 unsigned getTOCSaveOffset() const { return TOCSaveOffset; }
132 /// getFramePointerSaveOffset - Return the previous frame offset to save the
134 unsigned getFramePointerSaveOffset() const { return FramePointerSaveOffset; }
136 /// getBasePointerSaveOffset - Return the previous frame offset to save the
138 unsigned getBasePointerSaveOffset() const { return BasePointerSaveOffset; }
140 /// getLinkageSize - Return the size of the PowerPC ABI linkage area.
142 unsigned getLinkageSize() const { return LinkageSize; }
145 getCalleeSavedSpillSlots(unsigned &NumEntries) const override;
147 bool enableShrinkWrapping(const MachineFunction &MF) const override;
149 /// Methods used by shrink wrapping to determine if MBB can be used for the
150 /// function prologue/epilogue.
151 bool canUseAsPrologue(const MachineBasicBlock &MBB) const override;
152 bool canUseAsEpilogue(const MachineBasicBlock &MBB) const override;
154 } // End llvm namespace