1 //===-- PPCISelDAGToDAG.cpp - PPC --pattern matching inst selector --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for PowerPC,
11 // converting from a legalized dag to a PPC dag.
13 //===----------------------------------------------------------------------===//
15 #include "MCTargetDesc/PPCMCTargetDesc.h"
16 #include "MCTargetDesc/PPCPredicates.h"
18 #include "PPCISelLowering.h"
19 #include "PPCMachineFunctionInfo.h"
20 #include "PPCSubtarget.h"
21 #include "PPCTargetMachine.h"
22 #include "llvm/ADT/APInt.h"
23 #include "llvm/ADT/DenseMap.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/ADT/SmallPtrSet.h"
26 #include "llvm/ADT/SmallVector.h"
27 #include "llvm/ADT/Statistic.h"
28 #include "llvm/Analysis/BranchProbabilityInfo.h"
29 #include "llvm/CodeGen/FunctionLoweringInfo.h"
30 #include "llvm/CodeGen/ISDOpcodes.h"
31 #include "llvm/CodeGen/MachineBasicBlock.h"
32 #include "llvm/CodeGen/MachineFunction.h"
33 #include "llvm/CodeGen/MachineInstrBuilder.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/SelectionDAG.h"
36 #include "llvm/CodeGen/SelectionDAGISel.h"
37 #include "llvm/CodeGen/SelectionDAGNodes.h"
38 #include "llvm/CodeGen/TargetInstrInfo.h"
39 #include "llvm/CodeGen/TargetRegisterInfo.h"
40 #include "llvm/CodeGen/ValueTypes.h"
41 #include "llvm/IR/BasicBlock.h"
42 #include "llvm/IR/DebugLoc.h"
43 #include "llvm/IR/Function.h"
44 #include "llvm/IR/GlobalValue.h"
45 #include "llvm/IR/InlineAsm.h"
46 #include "llvm/IR/InstrTypes.h"
47 #include "llvm/IR/Module.h"
48 #include "llvm/Support/Casting.h"
49 #include "llvm/Support/CodeGen.h"
50 #include "llvm/Support/CommandLine.h"
51 #include "llvm/Support/Compiler.h"
52 #include "llvm/Support/Debug.h"
53 #include "llvm/Support/ErrorHandling.h"
54 #include "llvm/Support/KnownBits.h"
55 #include "llvm/Support/MachineValueType.h"
56 #include "llvm/Support/MathExtras.h"
57 #include "llvm/Support/raw_ostream.h"
70 #define DEBUG_TYPE "ppc-codegen"
72 STATISTIC(NumSextSetcc,
73 "Number of (sext(setcc)) nodes expanded into GPR sequence.");
74 STATISTIC(NumZextSetcc,
75 "Number of (zext(setcc)) nodes expanded into GPR sequence.");
76 STATISTIC(SignExtensionsAdded,
77 "Number of sign extensions for compare inputs added.");
78 STATISTIC(ZeroExtensionsAdded,
79 "Number of zero extensions for compare inputs added.");
80 STATISTIC(NumLogicOpsOnComparison,
81 "Number of logical ops on i1 values calculated in GPR.");
82 STATISTIC(OmittedForNonExtendUses,
83 "Number of compares not eliminated as they have non-extending uses.");
85 "Number of compares lowered to setb.");
87 // FIXME: Remove this once the bug has been fixed!
88 cl::opt<bool> ANDIGlueBug("expose-ppc-andi-glue-bug",
89 cl::desc("expose the ANDI glue bug on PPC"), cl::Hidden);
92 UseBitPermRewriter("ppc-use-bit-perm-rewriter", cl::init(true),
93 cl::desc("use aggressive ppc isel for bit permutations"),
95 static cl::opt<bool> BPermRewriterNoMasking(
96 "ppc-bit-perm-rewriter-stress-rotates",
97 cl::desc("stress rotate selection in aggressive ppc isel for "
101 static cl::opt<bool> EnableBranchHint(
102 "ppc-use-branch-hint", cl::init(true),
103 cl::desc("Enable static hinting of branches on ppc"),
106 static cl::opt<bool> EnableTLSOpt(
107 "ppc-tls-opt", cl::init(true),
108 cl::desc("Enable tls optimization peephole"),
111 enum ICmpInGPRType { ICGPR_All, ICGPR_None, ICGPR_I32, ICGPR_I64,
112 ICGPR_NonExtIn, ICGPR_Zext, ICGPR_Sext, ICGPR_ZextI32,
113 ICGPR_SextI32, ICGPR_ZextI64, ICGPR_SextI64 };
115 static cl::opt<ICmpInGPRType> CmpInGPR(
116 "ppc-gpr-icmps", cl::Hidden, cl::init(ICGPR_All),
117 cl::desc("Specify the types of comparisons to emit GPR-only code for."),
118 cl::values(clEnumValN(ICGPR_None, "none", "Do not modify integer comparisons."),
119 clEnumValN(ICGPR_All, "all", "All possible int comparisons in GPRs."),
120 clEnumValN(ICGPR_I32, "i32", "Only i32 comparisons in GPRs."),
121 clEnumValN(ICGPR_I64, "i64", "Only i64 comparisons in GPRs."),
122 clEnumValN(ICGPR_NonExtIn, "nonextin",
123 "Only comparisons where inputs don't need [sz]ext."),
124 clEnumValN(ICGPR_Zext, "zext", "Only comparisons with zext result."),
125 clEnumValN(ICGPR_ZextI32, "zexti32",
126 "Only i32 comparisons with zext result."),
127 clEnumValN(ICGPR_ZextI64, "zexti64",
128 "Only i64 comparisons with zext result."),
129 clEnumValN(ICGPR_Sext, "sext", "Only comparisons with sext result."),
130 clEnumValN(ICGPR_SextI32, "sexti32",
131 "Only i32 comparisons with sext result."),
132 clEnumValN(ICGPR_SextI64, "sexti64",
133 "Only i64 comparisons with sext result.")));
136 //===--------------------------------------------------------------------===//
137 /// PPCDAGToDAGISel - PPC specific code to select PPC machine
138 /// instructions for SelectionDAG operations.
140 class PPCDAGToDAGISel : public SelectionDAGISel {
141 const PPCTargetMachine &TM;
142 const PPCSubtarget *PPCSubTarget;
143 const PPCTargetLowering *PPCLowering;
144 unsigned GlobalBaseReg;
147 explicit PPCDAGToDAGISel(PPCTargetMachine &tm, CodeGenOpt::Level OptLevel)
148 : SelectionDAGISel(tm, OptLevel), TM(tm) {}
150 bool runOnMachineFunction(MachineFunction &MF) override {
151 // Make sure we re-emit a set of the global base reg if necessary
153 PPCSubTarget = &MF.getSubtarget<PPCSubtarget>();
154 PPCLowering = PPCSubTarget->getTargetLowering();
155 SelectionDAGISel::runOnMachineFunction(MF);
157 if (!PPCSubTarget->isSVR4ABI())
158 InsertVRSaveCode(MF);
163 void PreprocessISelDAG() override;
164 void PostprocessISelDAG() override;
166 /// getI16Imm - Return a target constant with the specified value, of type
168 inline SDValue getI16Imm(unsigned Imm, const SDLoc &dl) {
169 return CurDAG->getTargetConstant(Imm, dl, MVT::i16);
172 /// getI32Imm - Return a target constant with the specified value, of type
174 inline SDValue getI32Imm(unsigned Imm, const SDLoc &dl) {
175 return CurDAG->getTargetConstant(Imm, dl, MVT::i32);
178 /// getI64Imm - Return a target constant with the specified value, of type
180 inline SDValue getI64Imm(uint64_t Imm, const SDLoc &dl) {
181 return CurDAG->getTargetConstant(Imm, dl, MVT::i64);
184 /// getSmallIPtrImm - Return a target constant of pointer type.
185 inline SDValue getSmallIPtrImm(unsigned Imm, const SDLoc &dl) {
186 return CurDAG->getTargetConstant(
187 Imm, dl, PPCLowering->getPointerTy(CurDAG->getDataLayout()));
190 /// isRotateAndMask - Returns true if Mask and Shift can be folded into a
191 /// rotate and mask opcode and mask operation.
192 static bool isRotateAndMask(SDNode *N, unsigned Mask, bool isShiftMask,
193 unsigned &SH, unsigned &MB, unsigned &ME);
195 /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
196 /// base register. Return the virtual register that holds this value.
197 SDNode *getGlobalBaseReg();
199 void selectFrameIndex(SDNode *SN, SDNode *N, unsigned Offset = 0);
201 // Select - Convert the specified operand from a target-independent to a
202 // target-specific node if it hasn't already been changed.
203 void Select(SDNode *N) override;
205 bool tryBitfieldInsert(SDNode *N);
206 bool tryBitPermutation(SDNode *N);
207 bool tryIntCompareInGPR(SDNode *N);
209 // tryTLSXFormLoad - Convert an ISD::LOAD fed by a PPCISD::ADD_TLS into
210 // an X-Form load instruction with the offset being a relocation coming from
211 // the PPCISD::ADD_TLS.
212 bool tryTLSXFormLoad(LoadSDNode *N);
213 // tryTLSXFormStore - Convert an ISD::STORE fed by a PPCISD::ADD_TLS into
214 // an X-Form store instruction with the offset being a relocation coming from
215 // the PPCISD::ADD_TLS.
216 bool tryTLSXFormStore(StoreSDNode *N);
217 /// SelectCC - Select a comparison of the specified values with the
218 /// specified condition code, returning the CR# of the expression.
219 SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC,
222 /// SelectAddrImm - Returns true if the address N can be represented by
223 /// a base register plus a signed 16-bit displacement [r+imm].
224 bool SelectAddrImm(SDValue N, SDValue &Disp,
226 return PPCLowering->SelectAddressRegImm(N, Disp, Base, *CurDAG, 0);
229 /// SelectAddrImmOffs - Return true if the operand is valid for a preinc
230 /// immediate field. Note that the operand at this point is already the
231 /// result of a prior SelectAddressRegImm call.
232 bool SelectAddrImmOffs(SDValue N, SDValue &Out) const {
233 if (N.getOpcode() == ISD::TargetConstant ||
234 N.getOpcode() == ISD::TargetGlobalAddress) {
242 /// SelectAddrIdx - Given the specified addressed, check to see if it can be
243 /// represented as an indexed [r+r] operation. Returns false if it can
244 /// be represented by [r+imm], which are preferred.
245 bool SelectAddrIdx(SDValue N, SDValue &Base, SDValue &Index) {
246 return PPCLowering->SelectAddressRegReg(N, Base, Index, *CurDAG);
249 /// SelectAddrIdxOnly - Given the specified addressed, force it to be
250 /// represented as an indexed [r+r] operation.
251 bool SelectAddrIdxOnly(SDValue N, SDValue &Base, SDValue &Index) {
252 return PPCLowering->SelectAddressRegRegOnly(N, Base, Index, *CurDAG);
255 /// SelectAddrImmX4 - Returns true if the address N can be represented by
256 /// a base register plus a signed 16-bit displacement that is a multiple of 4.
257 /// Suitable for use by STD and friends.
258 bool SelectAddrImmX4(SDValue N, SDValue &Disp, SDValue &Base) {
259 return PPCLowering->SelectAddressRegImm(N, Disp, Base, *CurDAG, 4);
262 bool SelectAddrImmX16(SDValue N, SDValue &Disp, SDValue &Base) {
263 return PPCLowering->SelectAddressRegImm(N, Disp, Base, *CurDAG, 16);
266 // Select an address into a single register.
267 bool SelectAddr(SDValue N, SDValue &Base) {
272 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
273 /// inline asm expressions. It is always correct to compute the value into
274 /// a register. The case of adding a (possibly relocatable) constant to a
275 /// register can be improved, but it is wrong to substitute Reg+Reg for
276 /// Reg in an asm, because the load or store opcode would have to change.
277 bool SelectInlineAsmMemoryOperand(const SDValue &Op,
278 unsigned ConstraintID,
279 std::vector<SDValue> &OutOps) override {
280 switch(ConstraintID) {
282 errs() << "ConstraintID: " << ConstraintID << "\n";
283 llvm_unreachable("Unexpected asm memory constraint");
284 case InlineAsm::Constraint_es:
285 case InlineAsm::Constraint_i:
286 case InlineAsm::Constraint_m:
287 case InlineAsm::Constraint_o:
288 case InlineAsm::Constraint_Q:
289 case InlineAsm::Constraint_Z:
290 case InlineAsm::Constraint_Zy:
291 // We need to make sure that this one operand does not end up in r0
292 // (because we might end up lowering this as 0(%op)).
293 const TargetRegisterInfo *TRI = PPCSubTarget->getRegisterInfo();
294 const TargetRegisterClass *TRC = TRI->getPointerRegClass(*MF, /*Kind=*/1);
296 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), dl, MVT::i32);
298 SDValue(CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS,
299 dl, Op.getValueType(),
302 OutOps.push_back(NewOp);
308 void InsertVRSaveCode(MachineFunction &MF);
310 StringRef getPassName() const override {
311 return "PowerPC DAG->DAG Pattern Instruction Selection";
314 // Include the pieces autogenerated from the target description.
315 #include "PPCGenDAGISel.inc"
318 bool trySETCC(SDNode *N);
320 void PeepholePPC64();
321 void PeepholePPC64ZExt();
322 void PeepholeCROps();
324 SDValue combineToCMPB(SDNode *N);
325 void foldBoolExts(SDValue &Res, SDNode *&N);
327 bool AllUsersSelectZero(SDNode *N);
328 void SwapAllSelectUsers(SDNode *N);
330 bool isOffsetMultipleOf(SDNode *N, unsigned Val) const;
331 void transferMemOperands(SDNode *N, SDNode *Result);
334 } // end anonymous namespace
336 /// InsertVRSaveCode - Once the entire function has been instruction selected,
337 /// all virtual registers are created and all machine instructions are built,
338 /// check to see if we need to save/restore VRSAVE. If so, do it.
339 void PPCDAGToDAGISel::InsertVRSaveCode(MachineFunction &Fn) {
340 // Check to see if this function uses vector registers, which means we have to
341 // save and restore the VRSAVE register and update it with the regs we use.
343 // In this case, there will be virtual registers of vector type created
344 // by the scheduler. Detect them now.
345 bool HasVectorVReg = false;
346 for (unsigned i = 0, e = RegInfo->getNumVirtRegs(); i != e; ++i) {
347 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
348 if (RegInfo->getRegClass(Reg) == &PPC::VRRCRegClass) {
349 HasVectorVReg = true;
353 if (!HasVectorVReg) return; // nothing to do.
355 // If we have a vector register, we want to emit code into the entry and exit
356 // blocks to save and restore the VRSAVE register. We do this here (instead
357 // of marking all vector instructions as clobbering VRSAVE) for two reasons:
359 // 1. This (trivially) reduces the load on the register allocator, by not
360 // having to represent the live range of the VRSAVE register.
361 // 2. This (more significantly) allows us to create a temporary virtual
362 // register to hold the saved VRSAVE value, allowing this temporary to be
363 // register allocated, instead of forcing it to be spilled to the stack.
365 // Create two vregs - one to hold the VRSAVE register that is live-in to the
366 // function and one for the value after having bits or'd into it.
367 unsigned InVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
368 unsigned UpdatedVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
370 const TargetInstrInfo &TII = *PPCSubTarget->getInstrInfo();
371 MachineBasicBlock &EntryBB = *Fn.begin();
373 // Emit the following code into the entry block:
374 // InVRSAVE = MFVRSAVE
375 // UpdatedVRSAVE = UPDATE_VRSAVE InVRSAVE
376 // MTVRSAVE UpdatedVRSAVE
377 MachineBasicBlock::iterator IP = EntryBB.begin(); // Insert Point
378 BuildMI(EntryBB, IP, dl, TII.get(PPC::MFVRSAVE), InVRSAVE);
379 BuildMI(EntryBB, IP, dl, TII.get(PPC::UPDATE_VRSAVE),
380 UpdatedVRSAVE).addReg(InVRSAVE);
381 BuildMI(EntryBB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(UpdatedVRSAVE);
383 // Find all return blocks, outputting a restore in each epilog.
384 for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
385 if (BB->isReturnBlock()) {
386 IP = BB->end(); --IP;
388 // Skip over all terminator instructions, which are part of the return
390 MachineBasicBlock::iterator I2 = IP;
391 while (I2 != BB->begin() && (--I2)->isTerminator())
394 // Emit: MTVRSAVE InVRSave
395 BuildMI(*BB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(InVRSAVE);
400 /// getGlobalBaseReg - Output the instructions required to put the
401 /// base address to use for accessing globals into a register.
403 SDNode *PPCDAGToDAGISel::getGlobalBaseReg() {
404 if (!GlobalBaseReg) {
405 const TargetInstrInfo &TII = *PPCSubTarget->getInstrInfo();
406 // Insert the set of GlobalBaseReg into the first MBB of the function
407 MachineBasicBlock &FirstMBB = MF->front();
408 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
409 const Module *M = MF->getFunction().getParent();
412 if (PPCLowering->getPointerTy(CurDAG->getDataLayout()) == MVT::i32) {
413 if (PPCSubTarget->isTargetELF()) {
414 GlobalBaseReg = PPC::R30;
415 if (M->getPICLevel() == PICLevel::SmallPIC) {
416 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MoveGOTtoLR));
417 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg);
418 MF->getInfo<PPCFunctionInfo>()->setUsesPICBase(true);
420 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR));
421 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg);
422 unsigned TempReg = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
423 BuildMI(FirstMBB, MBBI, dl,
424 TII.get(PPC::UpdateGBR), GlobalBaseReg)
425 .addReg(TempReg, RegState::Define).addReg(GlobalBaseReg);
426 MF->getInfo<PPCFunctionInfo>()->setUsesPICBase(true);
430 RegInfo->createVirtualRegister(&PPC::GPRC_and_GPRC_NOR0RegClass);
431 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR));
432 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg);
435 // We must ensure that this sequence is dominated by the prologue.
436 // FIXME: This is a bit of a big hammer since we don't get the benefits
437 // of shrink-wrapping whenever we emit this instruction. Considering
438 // this is used in any function where we emit a jump table, this may be
439 // a significant limitation. We should consider inserting this in the
440 // block where it is used and then commoning this sequence up if it
441 // appears in multiple places.
442 // Note: on ISA 3.0 cores, we can use lnia (addpcis) instead of
444 MF->getInfo<PPCFunctionInfo>()->setShrinkWrapDisabled(true);
445 GlobalBaseReg = RegInfo->createVirtualRegister(&PPC::G8RC_and_G8RC_NOX0RegClass);
446 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR8));
447 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR8), GlobalBaseReg);
450 return CurDAG->getRegister(GlobalBaseReg,
451 PPCLowering->getPointerTy(CurDAG->getDataLayout()))
455 /// isInt32Immediate - This method tests to see if the node is a 32-bit constant
456 /// operand. If so Imm will receive the 32-bit value.
457 static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
458 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
459 Imm = cast<ConstantSDNode>(N)->getZExtValue();
465 /// isInt64Immediate - This method tests to see if the node is a 64-bit constant
466 /// operand. If so Imm will receive the 64-bit value.
467 static bool isInt64Immediate(SDNode *N, uint64_t &Imm) {
468 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i64) {
469 Imm = cast<ConstantSDNode>(N)->getZExtValue();
475 // isInt32Immediate - This method tests to see if a constant operand.
476 // If so Imm will receive the 32 bit value.
477 static bool isInt32Immediate(SDValue N, unsigned &Imm) {
478 return isInt32Immediate(N.getNode(), Imm);
481 /// isInt64Immediate - This method tests to see if the value is a 64-bit
482 /// constant operand. If so Imm will receive the 64-bit value.
483 static bool isInt64Immediate(SDValue N, uint64_t &Imm) {
484 return isInt64Immediate(N.getNode(), Imm);
487 static unsigned getBranchHint(unsigned PCC, FunctionLoweringInfo *FuncInfo,
488 const SDValue &DestMBB) {
489 assert(isa<BasicBlockSDNode>(DestMBB));
491 if (!FuncInfo->BPI) return PPC::BR_NO_HINT;
493 const BasicBlock *BB = FuncInfo->MBB->getBasicBlock();
494 const Instruction *BBTerm = BB->getTerminator();
496 if (BBTerm->getNumSuccessors() != 2) return PPC::BR_NO_HINT;
498 const BasicBlock *TBB = BBTerm->getSuccessor(0);
499 const BasicBlock *FBB = BBTerm->getSuccessor(1);
501 auto TProb = FuncInfo->BPI->getEdgeProbability(BB, TBB);
502 auto FProb = FuncInfo->BPI->getEdgeProbability(BB, FBB);
504 // We only want to handle cases which are easy to predict at static time, e.g.
505 // C++ throw statement, that is very likely not taken, or calling never
506 // returned function, e.g. stdlib exit(). So we set Threshold to filter
509 // Below is LLVM branch weight table, we only want to handle case 1, 2
511 // Case Taken:Nontaken Example
512 // 1. Unreachable 1048575:1 C++ throw, stdlib exit(),
513 // 2. Invoke-terminating 1:1048575
514 // 3. Coldblock 4:64 __builtin_expect
515 // 4. Loop Branch 124:4 For loop
516 // 5. PH/ZH/FPH 20:12
517 const uint32_t Threshold = 10000;
519 if (std::max(TProb, FProb) / Threshold < std::min(TProb, FProb))
520 return PPC::BR_NO_HINT;
522 LLVM_DEBUG(dbgs() << "Use branch hint for '" << FuncInfo->Fn->getName()
523 << "::" << BB->getName() << "'\n"
524 << " -> " << TBB->getName() << ": " << TProb << "\n"
525 << " -> " << FBB->getName() << ": " << FProb << "\n");
527 const BasicBlockSDNode *BBDN = cast<BasicBlockSDNode>(DestMBB);
529 // If Dest BasicBlock is False-BasicBlock (FBB), swap branch probabilities,
530 // because we want 'TProb' stands for 'branch probability' to Dest BasicBlock
531 if (BBDN->getBasicBlock()->getBasicBlock() != TBB)
532 std::swap(TProb, FProb);
534 return (TProb > FProb) ? PPC::BR_TAKEN_HINT : PPC::BR_NONTAKEN_HINT;
537 // isOpcWithIntImmediate - This method tests to see if the node is a specific
538 // opcode and that it has a immediate integer right operand.
539 // If so Imm will receive the 32 bit value.
540 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
541 return N->getOpcode() == Opc
542 && isInt32Immediate(N->getOperand(1).getNode(), Imm);
545 void PPCDAGToDAGISel::selectFrameIndex(SDNode *SN, SDNode *N, unsigned Offset) {
547 int FI = cast<FrameIndexSDNode>(N)->getIndex();
548 SDValue TFI = CurDAG->getTargetFrameIndex(FI, N->getValueType(0));
549 unsigned Opc = N->getValueType(0) == MVT::i32 ? PPC::ADDI : PPC::ADDI8;
551 CurDAG->SelectNodeTo(SN, Opc, N->getValueType(0), TFI,
552 getSmallIPtrImm(Offset, dl));
554 ReplaceNode(SN, CurDAG->getMachineNode(Opc, dl, N->getValueType(0), TFI,
555 getSmallIPtrImm(Offset, dl)));
558 bool PPCDAGToDAGISel::isRotateAndMask(SDNode *N, unsigned Mask,
559 bool isShiftMask, unsigned &SH,
560 unsigned &MB, unsigned &ME) {
561 // Don't even go down this path for i64, since different logic will be
562 // necessary for rldicl/rldicr/rldimi.
563 if (N->getValueType(0) != MVT::i32)
567 unsigned Indeterminant = ~0; // bit mask marking indeterminant results
568 unsigned Opcode = N->getOpcode();
569 if (N->getNumOperands() != 2 ||
570 !isInt32Immediate(N->getOperand(1).getNode(), Shift) || (Shift > 31))
573 if (Opcode == ISD::SHL) {
574 // apply shift left to mask if it comes first
575 if (isShiftMask) Mask = Mask << Shift;
576 // determine which bits are made indeterminant by shift
577 Indeterminant = ~(0xFFFFFFFFu << Shift);
578 } else if (Opcode == ISD::SRL) {
579 // apply shift right to mask if it comes first
580 if (isShiftMask) Mask = Mask >> Shift;
581 // determine which bits are made indeterminant by shift
582 Indeterminant = ~(0xFFFFFFFFu >> Shift);
583 // adjust for the left rotate
585 } else if (Opcode == ISD::ROTL) {
591 // if the mask doesn't intersect any Indeterminant bits
592 if (Mask && !(Mask & Indeterminant)) {
594 // make sure the mask is still a mask (wrap arounds may not be)
595 return isRunOfOnes(Mask, MB, ME);
600 bool PPCDAGToDAGISel::tryTLSXFormStore(StoreSDNode *ST) {
601 SDValue Base = ST->getBasePtr();
602 if (Base.getOpcode() != PPCISD::ADD_TLS)
604 SDValue Offset = ST->getOffset();
605 if (!Offset.isUndef())
609 EVT MemVT = ST->getMemoryVT();
610 EVT RegVT = ST->getValue().getValueType();
613 switch (MemVT.getSimpleVT().SimpleTy) {
617 Opcode = (RegVT == MVT::i32) ? PPC::STBXTLS_32 : PPC::STBXTLS;
621 Opcode = (RegVT == MVT::i32) ? PPC::STHXTLS_32 : PPC::STHXTLS;
625 Opcode = (RegVT == MVT::i32) ? PPC::STWXTLS_32 : PPC::STWXTLS;
629 Opcode = PPC::STDXTLS;
633 SDValue Chain = ST->getChain();
634 SDVTList VTs = ST->getVTList();
635 SDValue Ops[] = {ST->getValue(), Base.getOperand(0), Base.getOperand(1),
637 SDNode *MN = CurDAG->getMachineNode(Opcode, dl, VTs, Ops);
638 transferMemOperands(ST, MN);
643 bool PPCDAGToDAGISel::tryTLSXFormLoad(LoadSDNode *LD) {
644 SDValue Base = LD->getBasePtr();
645 if (Base.getOpcode() != PPCISD::ADD_TLS)
647 SDValue Offset = LD->getOffset();
648 if (!Offset.isUndef())
652 EVT MemVT = LD->getMemoryVT();
653 EVT RegVT = LD->getValueType(0);
655 switch (MemVT.getSimpleVT().SimpleTy) {
659 Opcode = (RegVT == MVT::i32) ? PPC::LBZXTLS_32 : PPC::LBZXTLS;
663 Opcode = (RegVT == MVT::i32) ? PPC::LHZXTLS_32 : PPC::LHZXTLS;
667 Opcode = (RegVT == MVT::i32) ? PPC::LWZXTLS_32 : PPC::LWZXTLS;
671 Opcode = PPC::LDXTLS;
675 SDValue Chain = LD->getChain();
676 SDVTList VTs = LD->getVTList();
677 SDValue Ops[] = {Base.getOperand(0), Base.getOperand(1), Chain};
678 SDNode *MN = CurDAG->getMachineNode(Opcode, dl, VTs, Ops);
679 transferMemOperands(LD, MN);
684 /// Turn an or of two masked values into the rotate left word immediate then
685 /// mask insert (rlwimi) instruction.
686 bool PPCDAGToDAGISel::tryBitfieldInsert(SDNode *N) {
687 SDValue Op0 = N->getOperand(0);
688 SDValue Op1 = N->getOperand(1);
691 KnownBits LKnown = CurDAG->computeKnownBits(Op0);
692 KnownBits RKnown = CurDAG->computeKnownBits(Op1);
694 unsigned TargetMask = LKnown.Zero.getZExtValue();
695 unsigned InsertMask = RKnown.Zero.getZExtValue();
697 if ((TargetMask | InsertMask) == 0xFFFFFFFF) {
698 unsigned Op0Opc = Op0.getOpcode();
699 unsigned Op1Opc = Op1.getOpcode();
700 unsigned Value, SH = 0;
701 TargetMask = ~TargetMask;
702 InsertMask = ~InsertMask;
704 // If the LHS has a foldable shift and the RHS does not, then swap it to the
705 // RHS so that we can fold the shift into the insert.
706 if (Op0Opc == ISD::AND && Op1Opc == ISD::AND) {
707 if (Op0.getOperand(0).getOpcode() == ISD::SHL ||
708 Op0.getOperand(0).getOpcode() == ISD::SRL) {
709 if (Op1.getOperand(0).getOpcode() != ISD::SHL &&
710 Op1.getOperand(0).getOpcode() != ISD::SRL) {
712 std::swap(Op0Opc, Op1Opc);
713 std::swap(TargetMask, InsertMask);
716 } else if (Op0Opc == ISD::SHL || Op0Opc == ISD::SRL) {
717 if (Op1Opc == ISD::AND && Op1.getOperand(0).getOpcode() != ISD::SHL &&
718 Op1.getOperand(0).getOpcode() != ISD::SRL) {
720 std::swap(Op0Opc, Op1Opc);
721 std::swap(TargetMask, InsertMask);
726 if (isRunOfOnes(InsertMask, MB, ME)) {
727 if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) &&
728 isInt32Immediate(Op1.getOperand(1), Value)) {
729 Op1 = Op1.getOperand(0);
730 SH = (Op1Opc == ISD::SHL) ? Value : 32 - Value;
732 if (Op1Opc == ISD::AND) {
733 // The AND mask might not be a constant, and we need to make sure that
734 // if we're going to fold the masking with the insert, all bits not
735 // know to be zero in the mask are known to be one.
736 KnownBits MKnown = CurDAG->computeKnownBits(Op1.getOperand(1));
737 bool CanFoldMask = InsertMask == MKnown.One.getZExtValue();
739 unsigned SHOpc = Op1.getOperand(0).getOpcode();
740 if ((SHOpc == ISD::SHL || SHOpc == ISD::SRL) && CanFoldMask &&
741 isInt32Immediate(Op1.getOperand(0).getOperand(1), Value)) {
742 // Note that Value must be in range here (less than 32) because
743 // otherwise there would not be any bits set in InsertMask.
744 Op1 = Op1.getOperand(0).getOperand(0);
745 SH = (SHOpc == ISD::SHL) ? Value : 32 - Value;
750 SDValue Ops[] = { Op0, Op1, getI32Imm(SH, dl), getI32Imm(MB, dl),
752 ReplaceNode(N, CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops));
759 // Predict the number of instructions that would be generated by calling
761 static unsigned selectI64ImmInstrCountDirect(int64_t Imm) {
762 // Assume no remaining bits.
763 unsigned Remainder = 0;
764 // Assume no shift required.
767 // If it can't be represented as a 32 bit value.
768 if (!isInt<32>(Imm)) {
769 Shift = countTrailingZeros<uint64_t>(Imm);
770 int64_t ImmSh = static_cast<uint64_t>(Imm) >> Shift;
772 // If the shifted value fits 32 bits.
773 if (isInt<32>(ImmSh)) {
774 // Go with the shifted value.
777 // Still stuck with a 64 bit value.
784 // Intermediate operand.
787 // Handle first 32 bits.
788 unsigned Lo = Imm & 0xFFFF;
791 if (isInt<16>(Imm)) {
795 // Handle the Hi bits and Lo bits.
802 // If no shift, we're done.
803 if (!Shift) return Result;
805 // If Hi word == Lo word,
806 // we can use rldimi to insert the Lo word into Hi word.
807 if ((unsigned)(Imm & 0xFFFFFFFF) == Remainder) {
812 // Shift for next step if the upper 32-bits were not zero.
816 // Add in the last bits as required.
817 if ((Remainder >> 16) & 0xFFFF)
819 if (Remainder & 0xFFFF)
825 static uint64_t Rot64(uint64_t Imm, unsigned R) {
826 return (Imm << R) | (Imm >> (64 - R));
829 static unsigned selectI64ImmInstrCount(int64_t Imm) {
830 unsigned Count = selectI64ImmInstrCountDirect(Imm);
832 // If the instruction count is 1 or 2, we do not need further analysis
833 // since rotate + load constant requires at least 2 instructions.
837 for (unsigned r = 1; r < 63; ++r) {
838 uint64_t RImm = Rot64(Imm, r);
839 unsigned RCount = selectI64ImmInstrCountDirect(RImm) + 1;
840 Count = std::min(Count, RCount);
842 // See comments in selectI64Imm for an explanation of the logic below.
843 unsigned LS = findLastSet(RImm);
847 uint64_t OnesMask = -(int64_t) (UINT64_C(1) << (LS+1));
848 uint64_t RImmWithOnes = RImm | OnesMask;
850 RCount = selectI64ImmInstrCountDirect(RImmWithOnes) + 1;
851 Count = std::min(Count, RCount);
857 // Select a 64-bit constant. For cost-modeling purposes, selectI64ImmInstrCount
858 // (above) needs to be kept in sync with this function.
859 static SDNode *selectI64ImmDirect(SelectionDAG *CurDAG, const SDLoc &dl,
861 // Assume no remaining bits.
862 unsigned Remainder = 0;
863 // Assume no shift required.
866 // If it can't be represented as a 32 bit value.
867 if (!isInt<32>(Imm)) {
868 Shift = countTrailingZeros<uint64_t>(Imm);
869 int64_t ImmSh = static_cast<uint64_t>(Imm) >> Shift;
871 // If the shifted value fits 32 bits.
872 if (isInt<32>(ImmSh)) {
873 // Go with the shifted value.
876 // Still stuck with a 64 bit value.
883 // Intermediate operand.
886 // Handle first 32 bits.
887 unsigned Lo = Imm & 0xFFFF;
888 unsigned Hi = (Imm >> 16) & 0xFFFF;
890 auto getI32Imm = [CurDAG, dl](unsigned Imm) {
891 return CurDAG->getTargetConstant(Imm, dl, MVT::i32);
895 if (isInt<16>(Imm)) {
896 uint64_t SextImm = SignExtend64(Lo, 16);
897 SDValue SDImm = CurDAG->getTargetConstant(SextImm, dl, MVT::i64);
899 Result = CurDAG->getMachineNode(PPC::LI8, dl, MVT::i64, SDImm);
901 // Handle the Hi bits.
902 unsigned OpC = Hi ? PPC::LIS8 : PPC::LI8;
903 Result = CurDAG->getMachineNode(OpC, dl, MVT::i64, getI32Imm(Hi));
905 Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64,
906 SDValue(Result, 0), getI32Imm(Lo));
909 Result = CurDAG->getMachineNode(PPC::LIS8, dl, MVT::i64, getI32Imm(Hi));
912 // If no shift, we're done.
913 if (!Shift) return Result;
915 // If Hi word == Lo word,
916 // we can use rldimi to insert the Lo word into Hi word.
917 if ((unsigned)(Imm & 0xFFFFFFFF) == Remainder) {
919 { SDValue(Result, 0), SDValue(Result, 0), getI32Imm(Shift), getI32Imm(0)};
920 return CurDAG->getMachineNode(PPC::RLDIMI, dl, MVT::i64, Ops);
923 // Shift for next step if the upper 32-bits were not zero.
925 Result = CurDAG->getMachineNode(PPC::RLDICR, dl, MVT::i64,
928 getI32Imm(63 - Shift));
931 // Add in the last bits as required.
932 if ((Hi = (Remainder >> 16) & 0xFFFF)) {
933 Result = CurDAG->getMachineNode(PPC::ORIS8, dl, MVT::i64,
934 SDValue(Result, 0), getI32Imm(Hi));
936 if ((Lo = Remainder & 0xFFFF)) {
937 Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64,
938 SDValue(Result, 0), getI32Imm(Lo));
944 static SDNode *selectI64Imm(SelectionDAG *CurDAG, const SDLoc &dl,
946 unsigned Count = selectI64ImmInstrCountDirect(Imm);
948 // If the instruction count is 1 or 2, we do not need further analysis
949 // since rotate + load constant requires at least 2 instructions.
951 return selectI64ImmDirect(CurDAG, dl, Imm);
958 for (unsigned r = 1; r < 63; ++r) {
959 uint64_t RImm = Rot64(Imm, r);
960 unsigned RCount = selectI64ImmInstrCountDirect(RImm) + 1;
961 if (RCount < Count) {
968 // If the immediate to generate has many trailing zeros, it might be
969 // worthwhile to generate a rotated value with too many leading ones
970 // (because that's free with li/lis's sign-extension semantics), and then
971 // mask them off after rotation.
973 unsigned LS = findLastSet(RImm);
974 // We're adding (63-LS) higher-order ones, and we expect to mask them off
975 // after performing the inverse rotation by (64-r). So we need that:
976 // 63-LS == 64-r => LS == r-1
980 uint64_t OnesMask = -(int64_t) (UINT64_C(1) << (LS+1));
981 uint64_t RImmWithOnes = RImm | OnesMask;
983 RCount = selectI64ImmInstrCountDirect(RImmWithOnes) + 1;
984 if (RCount < Count) {
987 MatImm = RImmWithOnes;
993 return selectI64ImmDirect(CurDAG, dl, Imm);
995 auto getI32Imm = [CurDAG, dl](unsigned Imm) {
996 return CurDAG->getTargetConstant(Imm, dl, MVT::i32);
999 SDValue Val = SDValue(selectI64ImmDirect(CurDAG, dl, MatImm), 0);
1000 return CurDAG->getMachineNode(PPC::RLDICR, dl, MVT::i64, Val,
1001 getI32Imm(64 - RMin), getI32Imm(MaskEnd));
1004 static unsigned allUsesTruncate(SelectionDAG *CurDAG, SDNode *N) {
1005 unsigned MaxTruncation = 0;
1006 // Cannot use range-based for loop here as we need the actual use (i.e. we
1007 // need the operand number corresponding to the use). A range-based for
1008 // will unbox the use and provide an SDNode*.
1009 for (SDNode::use_iterator Use = N->use_begin(), UseEnd = N->use_end();
1010 Use != UseEnd; ++Use) {
1012 Use->isMachineOpcode() ? Use->getMachineOpcode() : Use->getOpcode();
1016 if (Use->isMachineOpcode())
1019 std::max(MaxTruncation, Use->getValueType(0).getSizeInBits());
1022 if (Use->isMachineOpcode())
1024 StoreSDNode *STN = cast<StoreSDNode>(*Use);
1025 unsigned MemVTSize = STN->getMemoryVT().getSizeInBits();
1026 if (MemVTSize == 64 || Use.getOperandNo() != 0)
1028 MaxTruncation = std::max(MaxTruncation, MemVTSize);
1035 if (Use.getOperandNo() != 0)
1037 MaxTruncation = std::max(MaxTruncation, 32u);
1043 if (Use.getOperandNo() != 0)
1045 MaxTruncation = std::max(MaxTruncation, 16u);
1051 if (Use.getOperandNo() != 0)
1053 MaxTruncation = std::max(MaxTruncation, 8u);
1057 return MaxTruncation;
1060 // Select a 64-bit constant.
1061 static SDNode *selectI64Imm(SelectionDAG *CurDAG, SDNode *N) {
1064 // Get 64 bit value.
1065 int64_t Imm = cast<ConstantSDNode>(N)->getZExtValue();
1066 if (unsigned MinSize = allUsesTruncate(CurDAG, N)) {
1067 uint64_t SextImm = SignExtend64(Imm, MinSize);
1068 SDValue SDImm = CurDAG->getTargetConstant(SextImm, dl, MVT::i64);
1069 if (isInt<16>(SextImm))
1070 return CurDAG->getMachineNode(PPC::LI8, dl, MVT::i64, SDImm);
1072 return selectI64Imm(CurDAG, dl, Imm);
1077 class BitPermutationSelector {
1081 // The bit number in the value, using a convention where bit 0 is the
1082 // lowest-order bit.
1085 // ConstZero means a bit we need to mask off.
1086 // Variable is a bit comes from an input variable.
1087 // VariableKnownToBeZero is also a bit comes from an input variable,
1088 // but it is known to be already zero. So we do not need to mask them.
1092 VariableKnownToBeZero
1095 ValueBit(SDValue V, unsigned I, Kind K = Variable)
1096 : V(V), Idx(I), K(K) {}
1097 ValueBit(Kind K = Variable)
1098 : V(SDValue(nullptr, 0)), Idx(UINT32_MAX), K(K) {}
1100 bool isZero() const {
1101 return K == ConstZero || K == VariableKnownToBeZero;
1104 bool hasValue() const {
1105 return K == Variable || K == VariableKnownToBeZero;
1108 SDValue getValue() const {
1109 assert(hasValue() && "Cannot get the value of a constant bit");
1113 unsigned getValueBitIndex() const {
1114 assert(hasValue() && "Cannot get the value bit index of a constant bit");
1119 // A bit group has the same underlying value and the same rotate factor.
1123 unsigned StartIdx, EndIdx;
1125 // This rotation amount assumes that the lower 32 bits of the quantity are
1126 // replicated in the high 32 bits by the rotation operator (which is done
1127 // by rlwinm and friends in 64-bit mode).
1129 // Did converting to Repl32 == true change the rotation factor? If it did,
1130 // it decreased it by 32.
1132 // Was this group coalesced after setting Repl32 to true?
1133 bool Repl32Coalesced;
1135 BitGroup(SDValue V, unsigned R, unsigned S, unsigned E)
1136 : V(V), RLAmt(R), StartIdx(S), EndIdx(E), Repl32(false), Repl32CR(false),
1137 Repl32Coalesced(false) {
1138 LLVM_DEBUG(dbgs() << "\tbit group for " << V.getNode() << " RLAmt = " << R
1139 << " [" << S << ", " << E << "]\n");
1143 // Information on each (Value, RLAmt) pair (like the number of groups
1144 // associated with each) used to choose the lowering method.
1145 struct ValueRotInfo {
1147 unsigned RLAmt = std::numeric_limits<unsigned>::max();
1148 unsigned NumGroups = 0;
1149 unsigned FirstGroupStartIdx = std::numeric_limits<unsigned>::max();
1150 bool Repl32 = false;
1152 ValueRotInfo() = default;
1154 // For sorting (in reverse order) by NumGroups, and then by
1155 // FirstGroupStartIdx.
1156 bool operator < (const ValueRotInfo &Other) const {
1157 // We need to sort so that the non-Repl32 come first because, when we're
1158 // doing masking, the Repl32 bit groups might be subsumed into the 64-bit
1159 // masking operation.
1160 if (Repl32 < Other.Repl32)
1162 else if (Repl32 > Other.Repl32)
1164 else if (NumGroups > Other.NumGroups)
1166 else if (NumGroups < Other.NumGroups)
1168 else if (RLAmt == 0 && Other.RLAmt != 0)
1170 else if (RLAmt != 0 && Other.RLAmt == 0)
1172 else if (FirstGroupStartIdx < Other.FirstGroupStartIdx)
1178 using ValueBitsMemoizedValue = std::pair<bool, SmallVector<ValueBit, 64>>;
1179 using ValueBitsMemoizer =
1180 DenseMap<SDValue, std::unique_ptr<ValueBitsMemoizedValue>>;
1181 ValueBitsMemoizer Memoizer;
1183 // Return a pair of bool and a SmallVector pointer to a memoization entry.
1184 // The bool is true if something interesting was deduced, otherwise if we're
1185 // providing only a generic representation of V (or something else likewise
1186 // uninteresting for instruction selection) through the SmallVector.
1187 std::pair<bool, SmallVector<ValueBit, 64> *> getValueBits(SDValue V,
1189 auto &ValueEntry = Memoizer[V];
1191 return std::make_pair(ValueEntry->first, &ValueEntry->second);
1192 ValueEntry.reset(new ValueBitsMemoizedValue());
1193 bool &Interesting = ValueEntry->first;
1194 SmallVector<ValueBit, 64> &Bits = ValueEntry->second;
1195 Bits.resize(NumBits);
1197 switch (V.getOpcode()) {
1200 if (isa<ConstantSDNode>(V.getOperand(1))) {
1201 unsigned RotAmt = V.getConstantOperandVal(1);
1203 const auto &LHSBits = *getValueBits(V.getOperand(0), NumBits).second;
1205 for (unsigned i = 0; i < NumBits; ++i)
1206 Bits[i] = LHSBits[i < RotAmt ? i + (NumBits - RotAmt) : i - RotAmt];
1208 return std::make_pair(Interesting = true, &Bits);
1212 if (isa<ConstantSDNode>(V.getOperand(1))) {
1213 unsigned ShiftAmt = V.getConstantOperandVal(1);
1215 const auto &LHSBits = *getValueBits(V.getOperand(0), NumBits).second;
1217 for (unsigned i = ShiftAmt; i < NumBits; ++i)
1218 Bits[i] = LHSBits[i - ShiftAmt];
1220 for (unsigned i = 0; i < ShiftAmt; ++i)
1221 Bits[i] = ValueBit(ValueBit::ConstZero);
1223 return std::make_pair(Interesting = true, &Bits);
1227 if (isa<ConstantSDNode>(V.getOperand(1))) {
1228 unsigned ShiftAmt = V.getConstantOperandVal(1);
1230 const auto &LHSBits = *getValueBits(V.getOperand(0), NumBits).second;
1232 for (unsigned i = 0; i < NumBits - ShiftAmt; ++i)
1233 Bits[i] = LHSBits[i + ShiftAmt];
1235 for (unsigned i = NumBits - ShiftAmt; i < NumBits; ++i)
1236 Bits[i] = ValueBit(ValueBit::ConstZero);
1238 return std::make_pair(Interesting = true, &Bits);
1242 if (isa<ConstantSDNode>(V.getOperand(1))) {
1243 uint64_t Mask = V.getConstantOperandVal(1);
1245 const SmallVector<ValueBit, 64> *LHSBits;
1246 // Mark this as interesting, only if the LHS was also interesting. This
1247 // prevents the overall procedure from matching a single immediate 'and'
1248 // (which is non-optimal because such an and might be folded with other
1249 // things if we don't select it here).
1250 std::tie(Interesting, LHSBits) = getValueBits(V.getOperand(0), NumBits);
1252 for (unsigned i = 0; i < NumBits; ++i)
1253 if (((Mask >> i) & 1) == 1)
1254 Bits[i] = (*LHSBits)[i];
1256 // AND instruction masks this bit. If the input is already zero,
1257 // we have nothing to do here. Otherwise, make the bit ConstZero.
1258 if ((*LHSBits)[i].isZero())
1259 Bits[i] = (*LHSBits)[i];
1261 Bits[i] = ValueBit(ValueBit::ConstZero);
1264 return std::make_pair(Interesting, &Bits);
1268 const auto &LHSBits = *getValueBits(V.getOperand(0), NumBits).second;
1269 const auto &RHSBits = *getValueBits(V.getOperand(1), NumBits).second;
1271 bool AllDisjoint = true;
1272 SDValue LastVal = SDValue();
1273 unsigned LastIdx = 0;
1274 for (unsigned i = 0; i < NumBits; ++i) {
1275 if (LHSBits[i].isZero() && RHSBits[i].isZero()) {
1276 // If both inputs are known to be zero and one is ConstZero and
1277 // another is VariableKnownToBeZero, we can select whichever
1278 // we like. To minimize the number of bit groups, we select
1279 // VariableKnownToBeZero if this bit is the next bit of the same
1280 // input variable from the previous bit. Otherwise, we select
1282 if (LHSBits[i].hasValue() && LHSBits[i].getValue() == LastVal &&
1283 LHSBits[i].getValueBitIndex() == LastIdx + 1)
1284 Bits[i] = LHSBits[i];
1285 else if (RHSBits[i].hasValue() && RHSBits[i].getValue() == LastVal &&
1286 RHSBits[i].getValueBitIndex() == LastIdx + 1)
1287 Bits[i] = RHSBits[i];
1289 Bits[i] = ValueBit(ValueBit::ConstZero);
1291 else if (LHSBits[i].isZero())
1292 Bits[i] = RHSBits[i];
1293 else if (RHSBits[i].isZero())
1294 Bits[i] = LHSBits[i];
1296 AllDisjoint = false;
1299 // We remember the value and bit index of this bit.
1300 if (Bits[i].hasValue()) {
1301 LastVal = Bits[i].getValue();
1302 LastIdx = Bits[i].getValueBitIndex();
1305 if (LastVal) LastVal = SDValue();
1313 return std::make_pair(Interesting = true, &Bits);
1315 case ISD::ZERO_EXTEND: {
1316 // We support only the case with zero extension from i32 to i64 so far.
1317 if (V.getValueType() != MVT::i64 ||
1318 V.getOperand(0).getValueType() != MVT::i32)
1321 const SmallVector<ValueBit, 64> *LHSBits;
1322 const unsigned NumOperandBits = 32;
1323 std::tie(Interesting, LHSBits) = getValueBits(V.getOperand(0),
1326 for (unsigned i = 0; i < NumOperandBits; ++i)
1327 Bits[i] = (*LHSBits)[i];
1329 for (unsigned i = NumOperandBits; i < NumBits; ++i)
1330 Bits[i] = ValueBit(ValueBit::ConstZero);
1332 return std::make_pair(Interesting, &Bits);
1334 case ISD::TRUNCATE: {
1335 EVT FromType = V.getOperand(0).getValueType();
1336 EVT ToType = V.getValueType();
1337 // We support only the case with truncate from i64 to i32.
1338 if (FromType != MVT::i64 || ToType != MVT::i32)
1340 const unsigned NumAllBits = FromType.getSizeInBits();
1341 SmallVector<ValueBit, 64> *InBits;
1342 std::tie(Interesting, InBits) = getValueBits(V.getOperand(0),
1344 const unsigned NumValidBits = ToType.getSizeInBits();
1346 // A 32-bit instruction cannot touch upper 32-bit part of 64-bit value.
1347 // So, we cannot include this truncate.
1348 bool UseUpper32bit = false;
1349 for (unsigned i = 0; i < NumValidBits; ++i)
1350 if ((*InBits)[i].hasValue() && (*InBits)[i].getValueBitIndex() >= 32) {
1351 UseUpper32bit = true;
1357 for (unsigned i = 0; i < NumValidBits; ++i)
1358 Bits[i] = (*InBits)[i];
1360 return std::make_pair(Interesting, &Bits);
1362 case ISD::AssertZext: {
1363 // For AssertZext, we look through the operand and
1364 // mark the bits known to be zero.
1365 const SmallVector<ValueBit, 64> *LHSBits;
1366 std::tie(Interesting, LHSBits) = getValueBits(V.getOperand(0),
1369 EVT FromType = cast<VTSDNode>(V.getOperand(1))->getVT();
1370 const unsigned NumValidBits = FromType.getSizeInBits();
1371 for (unsigned i = 0; i < NumValidBits; ++i)
1372 Bits[i] = (*LHSBits)[i];
1374 // These bits are known to be zero.
1375 for (unsigned i = NumValidBits; i < NumBits; ++i)
1376 Bits[i] = ValueBit((*LHSBits)[i].getValue(),
1377 (*LHSBits)[i].getValueBitIndex(),
1378 ValueBit::VariableKnownToBeZero);
1380 return std::make_pair(Interesting, &Bits);
1383 LoadSDNode *LD = cast<LoadSDNode>(V);
1384 if (ISD::isZEXTLoad(V.getNode()) && V.getResNo() == 0) {
1385 EVT VT = LD->getMemoryVT();
1386 const unsigned NumValidBits = VT.getSizeInBits();
1388 for (unsigned i = 0; i < NumValidBits; ++i)
1389 Bits[i] = ValueBit(V, i);
1391 // These bits are known to be zero.
1392 for (unsigned i = NumValidBits; i < NumBits; ++i)
1393 Bits[i] = ValueBit(V, i, ValueBit::VariableKnownToBeZero);
1395 // Zero-extending load itself cannot be optimized. So, it is not
1396 // interesting by itself though it gives useful information.
1397 return std::make_pair(Interesting = false, &Bits);
1402 for (unsigned i = 0; i < NumBits; ++i)
1403 Bits[i] = ValueBit(V, i);
1405 return std::make_pair(Interesting = false, &Bits);
1408 // For each value (except the constant ones), compute the left-rotate amount
1409 // to get it from its original to final position.
1410 void computeRotationAmounts() {
1412 RLAmt.resize(Bits.size());
1413 for (unsigned i = 0; i < Bits.size(); ++i)
1414 if (Bits[i].hasValue()) {
1415 unsigned VBI = Bits[i].getValueBitIndex();
1419 RLAmt[i] = Bits.size() - (VBI - i);
1420 } else if (Bits[i].isZero()) {
1422 RLAmt[i] = UINT32_MAX;
1424 llvm_unreachable("Unknown value bit type");
1428 // Collect groups of consecutive bits with the same underlying value and
1429 // rotation factor. If we're doing late masking, we ignore zeros, otherwise
1430 // they break up groups.
1431 void collectBitGroups(bool LateMask) {
1434 unsigned LastRLAmt = RLAmt[0];
1435 SDValue LastValue = Bits[0].hasValue() ? Bits[0].getValue() : SDValue();
1436 unsigned LastGroupStartIdx = 0;
1437 bool IsGroupOfZeros = !Bits[LastGroupStartIdx].hasValue();
1438 for (unsigned i = 1; i < Bits.size(); ++i) {
1439 unsigned ThisRLAmt = RLAmt[i];
1440 SDValue ThisValue = Bits[i].hasValue() ? Bits[i].getValue() : SDValue();
1441 if (LateMask && !ThisValue) {
1442 ThisValue = LastValue;
1443 ThisRLAmt = LastRLAmt;
1444 // If we're doing late masking, then the first bit group always starts
1445 // at zero (even if the first bits were zero).
1446 if (BitGroups.empty())
1447 LastGroupStartIdx = 0;
1450 // If this bit is known to be zero and the current group is a bit group
1451 // of zeros, we do not need to terminate the current bit group even the
1452 // Value or RLAmt does not match here. Instead, we terminate this group
1453 // when the first non-zero bit appears later.
1454 if (IsGroupOfZeros && Bits[i].isZero())
1457 // If this bit has the same underlying value and the same rotate factor as
1458 // the last one, then they're part of the same group.
1459 if (ThisRLAmt == LastRLAmt && ThisValue == LastValue)
1460 // We cannot continue the current group if this bits is not known to
1461 // be zero in a bit group of zeros.
1462 if (!(IsGroupOfZeros && ThisValue && !Bits[i].isZero()))
1465 if (LastValue.getNode())
1466 BitGroups.push_back(BitGroup(LastValue, LastRLAmt, LastGroupStartIdx,
1468 LastRLAmt = ThisRLAmt;
1469 LastValue = ThisValue;
1470 LastGroupStartIdx = i;
1471 IsGroupOfZeros = !Bits[LastGroupStartIdx].hasValue();
1473 if (LastValue.getNode())
1474 BitGroups.push_back(BitGroup(LastValue, LastRLAmt, LastGroupStartIdx,
1477 if (BitGroups.empty())
1480 // We might be able to combine the first and last groups.
1481 if (BitGroups.size() > 1) {
1482 // If the first and last groups are the same, then remove the first group
1483 // in favor of the last group, making the ending index of the last group
1484 // equal to the ending index of the to-be-removed first group.
1485 if (BitGroups[0].StartIdx == 0 &&
1486 BitGroups[BitGroups.size()-1].EndIdx == Bits.size()-1 &&
1487 BitGroups[0].V == BitGroups[BitGroups.size()-1].V &&
1488 BitGroups[0].RLAmt == BitGroups[BitGroups.size()-1].RLAmt) {
1489 LLVM_DEBUG(dbgs() << "\tcombining final bit group with initial one\n");
1490 BitGroups[BitGroups.size()-1].EndIdx = BitGroups[0].EndIdx;
1491 BitGroups.erase(BitGroups.begin());
1496 // Take all (SDValue, RLAmt) pairs and sort them by the number of groups
1497 // associated with each. If the number of groups are same, we prefer a group
1498 // which does not require rotate, i.e. RLAmt is 0, to avoid the first rotate
1499 // instruction. If there is a degeneracy, pick the one that occurs
1500 // first (in the final value).
1501 void collectValueRotInfo() {
1504 for (auto &BG : BitGroups) {
1505 unsigned RLAmtKey = BG.RLAmt + (BG.Repl32 ? 64 : 0);
1506 ValueRotInfo &VRI = ValueRots[std::make_pair(BG.V, RLAmtKey)];
1508 VRI.RLAmt = BG.RLAmt;
1509 VRI.Repl32 = BG.Repl32;
1511 VRI.FirstGroupStartIdx = std::min(VRI.FirstGroupStartIdx, BG.StartIdx);
1514 // Now that we've collected the various ValueRotInfo instances, we need to
1516 ValueRotsVec.clear();
1517 for (auto &I : ValueRots) {
1518 ValueRotsVec.push_back(I.second);
1520 llvm::sort(ValueRotsVec);
1523 // In 64-bit mode, rlwinm and friends have a rotation operator that
1524 // replicates the low-order 32 bits into the high-order 32-bits. The mask
1525 // indices of these instructions can only be in the lower 32 bits, so they
1526 // can only represent some 64-bit bit groups. However, when they can be used,
1527 // the 32-bit replication can be used to represent, as a single bit group,
1528 // otherwise separate bit groups. We'll convert to replicated-32-bit bit
1529 // groups when possible. Returns true if any of the bit groups were
1531 void assignRepl32BitGroups() {
1532 // If we have bits like this:
1534 // Indices: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1535 // V bits: ... 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24
1536 // Groups: | RLAmt = 8 | RLAmt = 40 |
1538 // But, making use of a 32-bit operation that replicates the low-order 32
1539 // bits into the high-order 32 bits, this can be one bit group with a RLAmt
1542 auto IsAllLow32 = [this](BitGroup & BG) {
1543 if (BG.StartIdx <= BG.EndIdx) {
1544 for (unsigned i = BG.StartIdx; i <= BG.EndIdx; ++i) {
1545 if (!Bits[i].hasValue())
1547 if (Bits[i].getValueBitIndex() >= 32)
1551 for (unsigned i = BG.StartIdx; i < Bits.size(); ++i) {
1552 if (!Bits[i].hasValue())
1554 if (Bits[i].getValueBitIndex() >= 32)
1557 for (unsigned i = 0; i <= BG.EndIdx; ++i) {
1558 if (!Bits[i].hasValue())
1560 if (Bits[i].getValueBitIndex() >= 32)
1568 for (auto &BG : BitGroups) {
1569 // If this bit group has RLAmt of 0 and will not be merged with
1570 // another bit group, we don't benefit from Repl32. We don't mark
1571 // such group to give more freedom for later instruction selection.
1572 if (BG.RLAmt == 0) {
1573 auto PotentiallyMerged = [this](BitGroup & BG) {
1574 for (auto &BG2 : BitGroups)
1575 if (&BG != &BG2 && BG.V == BG2.V &&
1576 (BG2.RLAmt == 0 || BG2.RLAmt == 32))
1580 if (!PotentiallyMerged(BG))
1583 if (BG.StartIdx < 32 && BG.EndIdx < 32) {
1584 if (IsAllLow32(BG)) {
1585 if (BG.RLAmt >= 32) {
1592 LLVM_DEBUG(dbgs() << "\t32-bit replicated bit group for "
1593 << BG.V.getNode() << " RLAmt = " << BG.RLAmt << " ["
1594 << BG.StartIdx << ", " << BG.EndIdx << "]\n");
1599 // Now walk through the bit groups, consolidating where possible.
1600 for (auto I = BitGroups.begin(); I != BitGroups.end();) {
1601 // We might want to remove this bit group by merging it with the previous
1602 // group (which might be the ending group).
1603 auto IP = (I == BitGroups.begin()) ?
1604 std::prev(BitGroups.end()) : std::prev(I);
1605 if (I->Repl32 && IP->Repl32 && I->V == IP->V && I->RLAmt == IP->RLAmt &&
1606 I->StartIdx == (IP->EndIdx + 1) % 64 && I != IP) {
1608 LLVM_DEBUG(dbgs() << "\tcombining 32-bit replicated bit group for "
1609 << I->V.getNode() << " RLAmt = " << I->RLAmt << " ["
1610 << I->StartIdx << ", " << I->EndIdx
1611 << "] with group with range [" << IP->StartIdx << ", "
1612 << IP->EndIdx << "]\n");
1614 IP->EndIdx = I->EndIdx;
1615 IP->Repl32CR = IP->Repl32CR || I->Repl32CR;
1616 IP->Repl32Coalesced = true;
1617 I = BitGroups.erase(I);
1620 // There is a special case worth handling: If there is a single group
1621 // covering the entire upper 32 bits, and it can be merged with both
1622 // the next and previous groups (which might be the same group), then
1623 // do so. If it is the same group (so there will be only one group in
1624 // total), then we need to reverse the order of the range so that it
1625 // covers the entire 64 bits.
1626 if (I->StartIdx == 32 && I->EndIdx == 63) {
1627 assert(std::next(I) == BitGroups.end() &&
1628 "bit group ends at index 63 but there is another?");
1629 auto IN = BitGroups.begin();
1631 if (IP->Repl32 && IN->Repl32 && I->V == IP->V && I->V == IN->V &&
1632 (I->RLAmt % 32) == IP->RLAmt && (I->RLAmt % 32) == IN->RLAmt &&
1633 IP->EndIdx == 31 && IN->StartIdx == 0 && I != IP &&
1636 LLVM_DEBUG(dbgs() << "\tcombining bit group for " << I->V.getNode()
1637 << " RLAmt = " << I->RLAmt << " [" << I->StartIdx
1638 << ", " << I->EndIdx
1639 << "] with 32-bit replicated groups with ranges ["
1640 << IP->StartIdx << ", " << IP->EndIdx << "] and ["
1641 << IN->StartIdx << ", " << IN->EndIdx << "]\n");
1644 // There is only one other group; change it to cover the whole
1645 // range (backward, so that it can still be Repl32 but cover the
1646 // whole 64-bit range).
1649 IP->Repl32CR = IP->Repl32CR || I->RLAmt >= 32;
1650 IP->Repl32Coalesced = true;
1651 I = BitGroups.erase(I);
1653 // There are two separate groups, one before this group and one
1654 // after us (at the beginning). We're going to remove this group,
1655 // but also the group at the very beginning.
1656 IP->EndIdx = IN->EndIdx;
1657 IP->Repl32CR = IP->Repl32CR || IN->Repl32CR || I->RLAmt >= 32;
1658 IP->Repl32Coalesced = true;
1659 I = BitGroups.erase(I);
1660 BitGroups.erase(BitGroups.begin());
1663 // This must be the last group in the vector (and we might have
1664 // just invalidated the iterator above), so break here.
1674 SDValue getI32Imm(unsigned Imm, const SDLoc &dl) {
1675 return CurDAG->getTargetConstant(Imm, dl, MVT::i32);
1678 uint64_t getZerosMask() {
1680 for (unsigned i = 0; i < Bits.size(); ++i) {
1681 if (Bits[i].hasValue())
1683 Mask |= (UINT64_C(1) << i);
1689 // This method extends an input value to 64 bit if input is 32-bit integer.
1690 // While selecting instructions in BitPermutationSelector in 64-bit mode,
1691 // an input value can be a 32-bit integer if a ZERO_EXTEND node is included.
1692 // In such case, we extend it to 64 bit to be consistent with other values.
1693 SDValue ExtendToInt64(SDValue V, const SDLoc &dl) {
1694 if (V.getValueSizeInBits() == 64)
1697 assert(V.getValueSizeInBits() == 32);
1698 SDValue SubRegIdx = CurDAG->getTargetConstant(PPC::sub_32, dl, MVT::i32);
1699 SDValue ImDef = SDValue(CurDAG->getMachineNode(PPC::IMPLICIT_DEF, dl,
1701 SDValue ExtVal = SDValue(CurDAG->getMachineNode(PPC::INSERT_SUBREG, dl,
1707 SDValue TruncateToInt32(SDValue V, const SDLoc &dl) {
1708 if (V.getValueSizeInBits() == 32)
1711 assert(V.getValueSizeInBits() == 64);
1712 SDValue SubRegIdx = CurDAG->getTargetConstant(PPC::sub_32, dl, MVT::i32);
1713 SDValue SubVal = SDValue(CurDAG->getMachineNode(PPC::EXTRACT_SUBREG, dl,
1714 MVT::i32, V, SubRegIdx), 0);
1718 // Depending on the number of groups for a particular value, it might be
1719 // better to rotate, mask explicitly (using andi/andis), and then or the
1720 // result. Select this part of the result first.
1721 void SelectAndParts32(const SDLoc &dl, SDValue &Res, unsigned *InstCnt) {
1722 if (BPermRewriterNoMasking)
1725 for (ValueRotInfo &VRI : ValueRotsVec) {
1727 for (unsigned i = 0; i < Bits.size(); ++i) {
1728 if (!Bits[i].hasValue() || Bits[i].getValue() != VRI.V)
1730 if (RLAmt[i] != VRI.RLAmt)
1735 // Compute the masks for andi/andis that would be necessary.
1736 unsigned ANDIMask = (Mask & UINT16_MAX), ANDISMask = Mask >> 16;
1737 assert((ANDIMask != 0 || ANDISMask != 0) &&
1738 "No set bits in mask for value bit groups");
1739 bool NeedsRotate = VRI.RLAmt != 0;
1741 // We're trying to minimize the number of instructions. If we have one
1742 // group, using one of andi/andis can break even. If we have three
1743 // groups, we can use both andi and andis and break even (to use both
1744 // andi and andis we also need to or the results together). We need four
1745 // groups if we also need to rotate. To use andi/andis we need to do more
1746 // than break even because rotate-and-mask instructions tend to be easier
1749 // FIXME: We've biased here against using andi/andis, which is right for
1750 // POWER cores, but not optimal everywhere. For example, on the A2,
1751 // andi/andis have single-cycle latency whereas the rotate-and-mask
1752 // instructions take two cycles, and it would be better to bias toward
1753 // andi/andis in break-even cases.
1755 unsigned NumAndInsts = (unsigned) NeedsRotate +
1756 (unsigned) (ANDIMask != 0) +
1757 (unsigned) (ANDISMask != 0) +
1758 (unsigned) (ANDIMask != 0 && ANDISMask != 0) +
1759 (unsigned) (bool) Res;
1761 LLVM_DEBUG(dbgs() << "\t\trotation groups for " << VRI.V.getNode()
1762 << " RL: " << VRI.RLAmt << ":"
1763 << "\n\t\t\tisel using masking: " << NumAndInsts
1764 << " using rotates: " << VRI.NumGroups << "\n");
1766 if (NumAndInsts >= VRI.NumGroups)
1769 LLVM_DEBUG(dbgs() << "\t\t\t\tusing masking\n");
1771 if (InstCnt) *InstCnt += NumAndInsts;
1776 { TruncateToInt32(VRI.V, dl), getI32Imm(VRI.RLAmt, dl),
1777 getI32Imm(0, dl), getI32Imm(31, dl) };
1778 VRot = SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32,
1781 VRot = TruncateToInt32(VRI.V, dl);
1784 SDValue ANDIVal, ANDISVal;
1786 ANDIVal = SDValue(CurDAG->getMachineNode(PPC::ANDIo, dl, MVT::i32,
1787 VRot, getI32Imm(ANDIMask, dl)), 0);
1789 ANDISVal = SDValue(CurDAG->getMachineNode(PPC::ANDISo, dl, MVT::i32,
1790 VRot, getI32Imm(ANDISMask, dl)), 0);
1794 TotalVal = ANDISVal;
1798 TotalVal = SDValue(CurDAG->getMachineNode(PPC::OR, dl, MVT::i32,
1799 ANDIVal, ANDISVal), 0);
1804 Res = SDValue(CurDAG->getMachineNode(PPC::OR, dl, MVT::i32,
1807 // Now, remove all groups with this underlying value and rotation
1809 eraseMatchingBitGroups([VRI](const BitGroup &BG) {
1810 return BG.V == VRI.V && BG.RLAmt == VRI.RLAmt;
1815 // Instruction selection for the 32-bit case.
1816 SDNode *Select32(SDNode *N, bool LateMask, unsigned *InstCnt) {
1820 if (InstCnt) *InstCnt = 0;
1822 // Take care of cases that should use andi/andis first.
1823 SelectAndParts32(dl, Res, InstCnt);
1825 // If we've not yet selected a 'starting' instruction, and we have no zeros
1826 // to fill in, select the (Value, RLAmt) with the highest priority (largest
1827 // number of groups), and start with this rotated value.
1828 if ((!NeedMask || LateMask) && !Res) {
1829 ValueRotInfo &VRI = ValueRotsVec[0];
1831 if (InstCnt) *InstCnt += 1;
1833 { TruncateToInt32(VRI.V, dl), getI32Imm(VRI.RLAmt, dl),
1834 getI32Imm(0, dl), getI32Imm(31, dl) };
1835 Res = SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops),
1838 Res = TruncateToInt32(VRI.V, dl);
1841 // Now, remove all groups with this underlying value and rotation factor.
1842 eraseMatchingBitGroups([VRI](const BitGroup &BG) {
1843 return BG.V == VRI.V && BG.RLAmt == VRI.RLAmt;
1847 if (InstCnt) *InstCnt += BitGroups.size();
1849 // Insert the other groups (one at a time).
1850 for (auto &BG : BitGroups) {
1853 { TruncateToInt32(BG.V, dl), getI32Imm(BG.RLAmt, dl),
1854 getI32Imm(Bits.size() - BG.EndIdx - 1, dl),
1855 getI32Imm(Bits.size() - BG.StartIdx - 1, dl) };
1856 Res = SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops), 0);
1859 { Res, TruncateToInt32(BG.V, dl), getI32Imm(BG.RLAmt, dl),
1860 getI32Imm(Bits.size() - BG.EndIdx - 1, dl),
1861 getI32Imm(Bits.size() - BG.StartIdx - 1, dl) };
1862 Res = SDValue(CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops), 0);
1867 unsigned Mask = (unsigned) getZerosMask();
1869 unsigned ANDIMask = (Mask & UINT16_MAX), ANDISMask = Mask >> 16;
1870 assert((ANDIMask != 0 || ANDISMask != 0) &&
1871 "No set bits in zeros mask?");
1873 if (InstCnt) *InstCnt += (unsigned) (ANDIMask != 0) +
1874 (unsigned) (ANDISMask != 0) +
1875 (unsigned) (ANDIMask != 0 && ANDISMask != 0);
1877 SDValue ANDIVal, ANDISVal;
1879 ANDIVal = SDValue(CurDAG->getMachineNode(PPC::ANDIo, dl, MVT::i32,
1880 Res, getI32Imm(ANDIMask, dl)), 0);
1882 ANDISVal = SDValue(CurDAG->getMachineNode(PPC::ANDISo, dl, MVT::i32,
1883 Res, getI32Imm(ANDISMask, dl)), 0);
1890 Res = SDValue(CurDAG->getMachineNode(PPC::OR, dl, MVT::i32,
1891 ANDIVal, ANDISVal), 0);
1894 return Res.getNode();
1897 unsigned SelectRotMask64Count(unsigned RLAmt, bool Repl32,
1898 unsigned MaskStart, unsigned MaskEnd,
1900 // In the notation used by the instructions, 'start' and 'end' are reversed
1901 // because bits are counted from high to low order.
1902 unsigned InstMaskStart = 64 - MaskEnd - 1,
1903 InstMaskEnd = 64 - MaskStart - 1;
1908 if ((!IsIns && (InstMaskEnd == 63 || InstMaskStart == 0)) ||
1909 InstMaskEnd == 63 - RLAmt)
1915 // For 64-bit values, not all combinations of rotates and masks are
1916 // available. Produce one if it is available.
1917 SDValue SelectRotMask64(SDValue V, const SDLoc &dl, unsigned RLAmt,
1918 bool Repl32, unsigned MaskStart, unsigned MaskEnd,
1919 unsigned *InstCnt = nullptr) {
1920 // In the notation used by the instructions, 'start' and 'end' are reversed
1921 // because bits are counted from high to low order.
1922 unsigned InstMaskStart = 64 - MaskEnd - 1,
1923 InstMaskEnd = 64 - MaskStart - 1;
1925 if (InstCnt) *InstCnt += 1;
1928 // This rotation amount assumes that the lower 32 bits of the quantity
1929 // are replicated in the high 32 bits by the rotation operator (which is
1930 // done by rlwinm and friends).
1931 assert(InstMaskStart >= 32 && "Mask cannot start out of range");
1932 assert(InstMaskEnd >= 32 && "Mask cannot end out of range");
1934 { ExtendToInt64(V, dl), getI32Imm(RLAmt, dl),
1935 getI32Imm(InstMaskStart - 32, dl), getI32Imm(InstMaskEnd - 32, dl) };
1936 return SDValue(CurDAG->getMachineNode(PPC::RLWINM8, dl, MVT::i64,
1940 if (InstMaskEnd == 63) {
1942 { ExtendToInt64(V, dl), getI32Imm(RLAmt, dl),
1943 getI32Imm(InstMaskStart, dl) };
1944 return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, Ops), 0);
1947 if (InstMaskStart == 0) {
1949 { ExtendToInt64(V, dl), getI32Imm(RLAmt, dl),
1950 getI32Imm(InstMaskEnd, dl) };
1951 return SDValue(CurDAG->getMachineNode(PPC::RLDICR, dl, MVT::i64, Ops), 0);
1954 if (InstMaskEnd == 63 - RLAmt) {
1956 { ExtendToInt64(V, dl), getI32Imm(RLAmt, dl),
1957 getI32Imm(InstMaskStart, dl) };
1958 return SDValue(CurDAG->getMachineNode(PPC::RLDIC, dl, MVT::i64, Ops), 0);
1961 // We cannot do this with a single instruction, so we'll use two. The
1962 // problem is that we're not free to choose both a rotation amount and mask
1963 // start and end independently. We can choose an arbitrary mask start and
1964 // end, but then the rotation amount is fixed. Rotation, however, can be
1965 // inverted, and so by applying an "inverse" rotation first, we can get the
1967 if (InstCnt) *InstCnt += 1;
1969 // The rotation mask for the second instruction must be MaskStart.
1970 unsigned RLAmt2 = MaskStart;
1971 // The first instruction must rotate V so that the overall rotation amount
1973 unsigned RLAmt1 = (64 + RLAmt - RLAmt2) % 64;
1975 V = SelectRotMask64(V, dl, RLAmt1, false, 0, 63);
1976 return SelectRotMask64(V, dl, RLAmt2, false, MaskStart, MaskEnd);
1979 // For 64-bit values, not all combinations of rotates and masks are
1980 // available. Produce a rotate-mask-and-insert if one is available.
1981 SDValue SelectRotMaskIns64(SDValue Base, SDValue V, const SDLoc &dl,
1982 unsigned RLAmt, bool Repl32, unsigned MaskStart,
1983 unsigned MaskEnd, unsigned *InstCnt = nullptr) {
1984 // In the notation used by the instructions, 'start' and 'end' are reversed
1985 // because bits are counted from high to low order.
1986 unsigned InstMaskStart = 64 - MaskEnd - 1,
1987 InstMaskEnd = 64 - MaskStart - 1;
1989 if (InstCnt) *InstCnt += 1;
1992 // This rotation amount assumes that the lower 32 bits of the quantity
1993 // are replicated in the high 32 bits by the rotation operator (which is
1994 // done by rlwinm and friends).
1995 assert(InstMaskStart >= 32 && "Mask cannot start out of range");
1996 assert(InstMaskEnd >= 32 && "Mask cannot end out of range");
1998 { ExtendToInt64(Base, dl), ExtendToInt64(V, dl), getI32Imm(RLAmt, dl),
1999 getI32Imm(InstMaskStart - 32, dl), getI32Imm(InstMaskEnd - 32, dl) };
2000 return SDValue(CurDAG->getMachineNode(PPC::RLWIMI8, dl, MVT::i64,
2004 if (InstMaskEnd == 63 - RLAmt) {
2006 { ExtendToInt64(Base, dl), ExtendToInt64(V, dl), getI32Imm(RLAmt, dl),
2007 getI32Imm(InstMaskStart, dl) };
2008 return SDValue(CurDAG->getMachineNode(PPC::RLDIMI, dl, MVT::i64, Ops), 0);
2011 // We cannot do this with a single instruction, so we'll use two. The
2012 // problem is that we're not free to choose both a rotation amount and mask
2013 // start and end independently. We can choose an arbitrary mask start and
2014 // end, but then the rotation amount is fixed. Rotation, however, can be
2015 // inverted, and so by applying an "inverse" rotation first, we can get the
2017 if (InstCnt) *InstCnt += 1;
2019 // The rotation mask for the second instruction must be MaskStart.
2020 unsigned RLAmt2 = MaskStart;
2021 // The first instruction must rotate V so that the overall rotation amount
2023 unsigned RLAmt1 = (64 + RLAmt - RLAmt2) % 64;
2025 V = SelectRotMask64(V, dl, RLAmt1, false, 0, 63);
2026 return SelectRotMaskIns64(Base, V, dl, RLAmt2, false, MaskStart, MaskEnd);
2029 void SelectAndParts64(const SDLoc &dl, SDValue &Res, unsigned *InstCnt) {
2030 if (BPermRewriterNoMasking)
2033 // The idea here is the same as in the 32-bit version, but with additional
2034 // complications from the fact that Repl32 might be true. Because we
2035 // aggressively convert bit groups to Repl32 form (which, for small
2036 // rotation factors, involves no other change), and then coalesce, it might
2037 // be the case that a single 64-bit masking operation could handle both
2038 // some Repl32 groups and some non-Repl32 groups. If converting to Repl32
2039 // form allowed coalescing, then we must use a 32-bit rotaton in order to
2040 // completely capture the new combined bit group.
2042 for (ValueRotInfo &VRI : ValueRotsVec) {
2045 // We need to add to the mask all bits from the associated bit groups.
2046 // If Repl32 is false, we need to add bits from bit groups that have
2047 // Repl32 true, but are trivially convertable to Repl32 false. Such a
2048 // group is trivially convertable if it overlaps only with the lower 32
2049 // bits, and the group has not been coalesced.
2050 auto MatchingBG = [VRI](const BitGroup &BG) {
2054 unsigned EffRLAmt = BG.RLAmt;
2055 if (!VRI.Repl32 && BG.Repl32) {
2056 if (BG.StartIdx < 32 && BG.EndIdx < 32 && BG.StartIdx <= BG.EndIdx &&
2057 !BG.Repl32Coalesced) {
2063 } else if (VRI.Repl32 != BG.Repl32) {
2067 return VRI.RLAmt == EffRLAmt;
2070 for (auto &BG : BitGroups) {
2071 if (!MatchingBG(BG))
2074 if (BG.StartIdx <= BG.EndIdx) {
2075 for (unsigned i = BG.StartIdx; i <= BG.EndIdx; ++i)
2076 Mask |= (UINT64_C(1) << i);
2078 for (unsigned i = BG.StartIdx; i < Bits.size(); ++i)
2079 Mask |= (UINT64_C(1) << i);
2080 for (unsigned i = 0; i <= BG.EndIdx; ++i)
2081 Mask |= (UINT64_C(1) << i);
2085 // We can use the 32-bit andi/andis technique if the mask does not
2086 // require any higher-order bits. This can save an instruction compared
2087 // to always using the general 64-bit technique.
2088 bool Use32BitInsts = isUInt<32>(Mask);
2089 // Compute the masks for andi/andis that would be necessary.
2090 unsigned ANDIMask = (Mask & UINT16_MAX),
2091 ANDISMask = (Mask >> 16) & UINT16_MAX;
2093 bool NeedsRotate = VRI.RLAmt || (VRI.Repl32 && !isUInt<32>(Mask));
2095 unsigned NumAndInsts = (unsigned) NeedsRotate +
2096 (unsigned) (bool) Res;
2098 NumAndInsts += (unsigned) (ANDIMask != 0) + (unsigned) (ANDISMask != 0) +
2099 (unsigned) (ANDIMask != 0 && ANDISMask != 0);
2101 NumAndInsts += selectI64ImmInstrCount(Mask) + /* and */ 1;
2103 unsigned NumRLInsts = 0;
2104 bool FirstBG = true;
2105 bool MoreBG = false;
2106 for (auto &BG : BitGroups) {
2107 if (!MatchingBG(BG)) {
2112 SelectRotMask64Count(BG.RLAmt, BG.Repl32, BG.StartIdx, BG.EndIdx,
2117 LLVM_DEBUG(dbgs() << "\t\trotation groups for " << VRI.V.getNode()
2118 << " RL: " << VRI.RLAmt << (VRI.Repl32 ? " (32):" : ":")
2119 << "\n\t\t\tisel using masking: " << NumAndInsts
2120 << " using rotates: " << NumRLInsts << "\n");
2122 // When we'd use andi/andis, we bias toward using the rotates (andi only
2123 // has a record form, and is cracked on POWER cores). However, when using
2124 // general 64-bit constant formation, bias toward the constant form,
2125 // because that exposes more opportunities for CSE.
2126 if (NumAndInsts > NumRLInsts)
2128 // When merging multiple bit groups, instruction or is used.
2129 // But when rotate is used, rldimi can inert the rotated value into any
2130 // register, so instruction or can be avoided.
2131 if ((Use32BitInsts || MoreBG) && NumAndInsts == NumRLInsts)
2134 LLVM_DEBUG(dbgs() << "\t\t\t\tusing masking\n");
2136 if (InstCnt) *InstCnt += NumAndInsts;
2139 // We actually need to generate a rotation if we have a non-zero rotation
2140 // factor or, in the Repl32 case, if we care about any of the
2141 // higher-order replicated bits. In the latter case, we generate a mask
2142 // backward so that it actually includes the entire 64 bits.
2143 if (VRI.RLAmt || (VRI.Repl32 && !isUInt<32>(Mask)))
2144 VRot = SelectRotMask64(VRI.V, dl, VRI.RLAmt, VRI.Repl32,
2145 VRI.Repl32 ? 31 : 0, VRI.Repl32 ? 30 : 63);
2150 if (Use32BitInsts) {
2151 assert((ANDIMask != 0 || ANDISMask != 0) &&
2152 "No set bits in mask when using 32-bit ands for 64-bit value");
2154 SDValue ANDIVal, ANDISVal;
2156 ANDIVal = SDValue(CurDAG->getMachineNode(PPC::ANDIo8, dl, MVT::i64,
2157 ExtendToInt64(VRot, dl),
2158 getI32Imm(ANDIMask, dl)),
2161 ANDISVal = SDValue(CurDAG->getMachineNode(PPC::ANDISo8, dl, MVT::i64,
2162 ExtendToInt64(VRot, dl),
2163 getI32Imm(ANDISMask, dl)),
2167 TotalVal = ANDISVal;
2171 TotalVal = SDValue(CurDAG->getMachineNode(PPC::OR8, dl, MVT::i64,
2172 ExtendToInt64(ANDIVal, dl), ANDISVal), 0);
2174 TotalVal = SDValue(selectI64Imm(CurDAG, dl, Mask), 0);
2176 SDValue(CurDAG->getMachineNode(PPC::AND8, dl, MVT::i64,
2177 ExtendToInt64(VRot, dl), TotalVal),
2184 Res = SDValue(CurDAG->getMachineNode(PPC::OR8, dl, MVT::i64,
2185 ExtendToInt64(Res, dl), TotalVal),
2188 // Now, remove all groups with this underlying value and rotation
2190 eraseMatchingBitGroups(MatchingBG);
2194 // Instruction selection for the 64-bit case.
2195 SDNode *Select64(SDNode *N, bool LateMask, unsigned *InstCnt) {
2199 if (InstCnt) *InstCnt = 0;
2201 // Take care of cases that should use andi/andis first.
2202 SelectAndParts64(dl, Res, InstCnt);
2204 // If we've not yet selected a 'starting' instruction, and we have no zeros
2205 // to fill in, select the (Value, RLAmt) with the highest priority (largest
2206 // number of groups), and start with this rotated value.
2207 if ((!NeedMask || LateMask) && !Res) {
2208 // If we have both Repl32 groups and non-Repl32 groups, the non-Repl32
2209 // groups will come first, and so the VRI representing the largest number
2210 // of groups might not be first (it might be the first Repl32 groups).
2211 unsigned MaxGroupsIdx = 0;
2212 if (!ValueRotsVec[0].Repl32) {
2213 for (unsigned i = 0, ie = ValueRotsVec.size(); i < ie; ++i)
2214 if (ValueRotsVec[i].Repl32) {
2215 if (ValueRotsVec[i].NumGroups > ValueRotsVec[0].NumGroups)
2221 ValueRotInfo &VRI = ValueRotsVec[MaxGroupsIdx];
2222 bool NeedsRotate = false;
2225 } else if (VRI.Repl32) {
2226 for (auto &BG : BitGroups) {
2227 if (BG.V != VRI.V || BG.RLAmt != VRI.RLAmt ||
2228 BG.Repl32 != VRI.Repl32)
2231 // We don't need a rotate if the bit group is confined to the lower
2233 if (BG.StartIdx < 32 && BG.EndIdx < 32 && BG.StartIdx < BG.EndIdx)
2242 Res = SelectRotMask64(VRI.V, dl, VRI.RLAmt, VRI.Repl32,
2243 VRI.Repl32 ? 31 : 0, VRI.Repl32 ? 30 : 63,
2248 // Now, remove all groups with this underlying value and rotation factor.
2250 eraseMatchingBitGroups([VRI](const BitGroup &BG) {
2251 return BG.V == VRI.V && BG.RLAmt == VRI.RLAmt &&
2252 BG.Repl32 == VRI.Repl32;
2256 // Because 64-bit rotates are more flexible than inserts, we might have a
2257 // preference regarding which one we do first (to save one instruction).
2259 for (auto I = BitGroups.begin(), IE = BitGroups.end(); I != IE; ++I) {
2260 if (SelectRotMask64Count(I->RLAmt, I->Repl32, I->StartIdx, I->EndIdx,
2262 SelectRotMask64Count(I->RLAmt, I->Repl32, I->StartIdx, I->EndIdx,
2264 if (I != BitGroups.begin()) {
2267 BitGroups.insert(BitGroups.begin(), BG);
2274 // Insert the other groups (one at a time).
2275 for (auto &BG : BitGroups) {
2277 Res = SelectRotMask64(BG.V, dl, BG.RLAmt, BG.Repl32, BG.StartIdx,
2278 BG.EndIdx, InstCnt);
2280 Res = SelectRotMaskIns64(Res, BG.V, dl, BG.RLAmt, BG.Repl32,
2281 BG.StartIdx, BG.EndIdx, InstCnt);
2285 uint64_t Mask = getZerosMask();
2287 // We can use the 32-bit andi/andis technique if the mask does not
2288 // require any higher-order bits. This can save an instruction compared
2289 // to always using the general 64-bit technique.
2290 bool Use32BitInsts = isUInt<32>(Mask);
2291 // Compute the masks for andi/andis that would be necessary.
2292 unsigned ANDIMask = (Mask & UINT16_MAX),
2293 ANDISMask = (Mask >> 16) & UINT16_MAX;
2295 if (Use32BitInsts) {
2296 assert((ANDIMask != 0 || ANDISMask != 0) &&
2297 "No set bits in mask when using 32-bit ands for 64-bit value");
2299 if (InstCnt) *InstCnt += (unsigned) (ANDIMask != 0) +
2300 (unsigned) (ANDISMask != 0) +
2301 (unsigned) (ANDIMask != 0 && ANDISMask != 0);
2303 SDValue ANDIVal, ANDISVal;
2305 ANDIVal = SDValue(CurDAG->getMachineNode(PPC::ANDIo8, dl, MVT::i64,
2306 ExtendToInt64(Res, dl), getI32Imm(ANDIMask, dl)), 0);
2308 ANDISVal = SDValue(CurDAG->getMachineNode(PPC::ANDISo8, dl, MVT::i64,
2309 ExtendToInt64(Res, dl), getI32Imm(ANDISMask, dl)), 0);
2316 Res = SDValue(CurDAG->getMachineNode(PPC::OR8, dl, MVT::i64,
2317 ExtendToInt64(ANDIVal, dl), ANDISVal), 0);
2319 if (InstCnt) *InstCnt += selectI64ImmInstrCount(Mask) + /* and */ 1;
2321 SDValue MaskVal = SDValue(selectI64Imm(CurDAG, dl, Mask), 0);
2323 SDValue(CurDAG->getMachineNode(PPC::AND8, dl, MVT::i64,
2324 ExtendToInt64(Res, dl), MaskVal), 0);
2328 return Res.getNode();
2331 SDNode *Select(SDNode *N, bool LateMask, unsigned *InstCnt = nullptr) {
2332 // Fill in BitGroups.
2333 collectBitGroups(LateMask);
2334 if (BitGroups.empty())
2337 // For 64-bit values, figure out when we can use 32-bit instructions.
2338 if (Bits.size() == 64)
2339 assignRepl32BitGroups();
2341 // Fill in ValueRotsVec.
2342 collectValueRotInfo();
2344 if (Bits.size() == 32) {
2345 return Select32(N, LateMask, InstCnt);
2347 assert(Bits.size() == 64 && "Not 64 bits here?");
2348 return Select64(N, LateMask, InstCnt);
2354 void eraseMatchingBitGroups(function_ref<bool(const BitGroup &)> F) {
2355 BitGroups.erase(remove_if(BitGroups, F), BitGroups.end());
2358 SmallVector<ValueBit, 64> Bits;
2361 SmallVector<unsigned, 64> RLAmt;
2363 SmallVector<BitGroup, 16> BitGroups;
2365 DenseMap<std::pair<SDValue, unsigned>, ValueRotInfo> ValueRots;
2366 SmallVector<ValueRotInfo, 16> ValueRotsVec;
2368 SelectionDAG *CurDAG;
2371 BitPermutationSelector(SelectionDAG *DAG)
2374 // Here we try to match complex bit permutations into a set of
2375 // rotate-and-shift/shift/and/or instructions, using a set of heuristics
2376 // known to produce optimial code for common cases (like i32 byte swapping).
2377 SDNode *Select(SDNode *N) {
2380 getValueBits(SDValue(N, 0), N->getValueType(0).getSizeInBits());
2383 Bits = std::move(*Result.second);
2385 LLVM_DEBUG(dbgs() << "Considering bit-permutation-based instruction"
2386 " selection for: ");
2387 LLVM_DEBUG(N->dump(CurDAG));
2389 // Fill it RLAmt and set NeedMask.
2390 computeRotationAmounts();
2393 return Select(N, false);
2395 // We currently have two techniques for handling results with zeros: early
2396 // masking (the default) and late masking. Late masking is sometimes more
2397 // efficient, but because the structure of the bit groups is different, it
2398 // is hard to tell without generating both and comparing the results. With
2399 // late masking, we ignore zeros in the resulting value when inserting each
2400 // set of bit groups, and then mask in the zeros at the end. With early
2401 // masking, we only insert the non-zero parts of the result at every step.
2403 unsigned InstCnt = 0, InstCntLateMask = 0;
2404 LLVM_DEBUG(dbgs() << "\tEarly masking:\n");
2405 SDNode *RN = Select(N, false, &InstCnt);
2406 LLVM_DEBUG(dbgs() << "\t\tisel would use " << InstCnt << " instructions\n");
2408 LLVM_DEBUG(dbgs() << "\tLate masking:\n");
2409 SDNode *RNLM = Select(N, true, &InstCntLateMask);
2410 LLVM_DEBUG(dbgs() << "\t\tisel would use " << InstCntLateMask
2411 << " instructions\n");
2413 if (InstCnt <= InstCntLateMask) {
2414 LLVM_DEBUG(dbgs() << "\tUsing early-masking for isel\n");
2418 LLVM_DEBUG(dbgs() << "\tUsing late-masking for isel\n");
2423 class IntegerCompareEliminator {
2424 SelectionDAG *CurDAG;
2426 // Conversion type for interpreting results of a 32-bit instruction as
2427 // a 64-bit value or vice versa.
2428 enum ExtOrTruncConversion { Ext, Trunc };
2430 // Modifiers to guide how an ISD::SETCC node's result is to be computed
2432 // ZExtOrig - use the original condition code, zero-extend value
2433 // ZExtInvert - invert the condition code, zero-extend value
2434 // SExtOrig - use the original condition code, sign-extend value
2435 // SExtInvert - invert the condition code, sign-extend value
2436 enum SetccInGPROpts { ZExtOrig, ZExtInvert, SExtOrig, SExtInvert };
2438 // Comparisons against zero to emit GPR code sequences for. Each of these
2439 // sequences may need to be emitted for two or more equivalent patterns.
2440 // For example (a >= 0) == (a > -1). The direction of the comparison (</>)
2441 // matters as well as the extension type: sext (-1/0), zext (1/0).
2442 // GEZExt - (zext (LHS >= 0))
2443 // GESExt - (sext (LHS >= 0))
2444 // LEZExt - (zext (LHS <= 0))
2445 // LESExt - (sext (LHS <= 0))
2446 enum ZeroCompare { GEZExt, GESExt, LEZExt, LESExt };
2448 SDNode *tryEXTEND(SDNode *N);
2449 SDNode *tryLogicOpOfCompares(SDNode *N);
2450 SDValue computeLogicOpInGPR(SDValue LogicOp);
2451 SDValue signExtendInputIfNeeded(SDValue Input);
2452 SDValue zeroExtendInputIfNeeded(SDValue Input);
2453 SDValue addExtOrTrunc(SDValue NatWidthRes, ExtOrTruncConversion Conv);
2454 SDValue getCompoundZeroComparisonInGPR(SDValue LHS, SDLoc dl,
2456 SDValue get32BitZExtCompare(SDValue LHS, SDValue RHS, ISD::CondCode CC,
2457 int64_t RHSValue, SDLoc dl);
2458 SDValue get32BitSExtCompare(SDValue LHS, SDValue RHS, ISD::CondCode CC,
2459 int64_t RHSValue, SDLoc dl);
2460 SDValue get64BitZExtCompare(SDValue LHS, SDValue RHS, ISD::CondCode CC,
2461 int64_t RHSValue, SDLoc dl);
2462 SDValue get64BitSExtCompare(SDValue LHS, SDValue RHS, ISD::CondCode CC,
2463 int64_t RHSValue, SDLoc dl);
2464 SDValue getSETCCInGPR(SDValue Compare, SetccInGPROpts ConvOpts);
2467 IntegerCompareEliminator(SelectionDAG *DAG,
2468 PPCDAGToDAGISel *Sel) : CurDAG(DAG), S(Sel) {
2469 assert(CurDAG->getTargetLoweringInfo()
2470 .getPointerTy(CurDAG->getDataLayout()).getSizeInBits() == 64 &&
2471 "Only expecting to use this on 64 bit targets.");
2473 SDNode *Select(SDNode *N) {
2474 if (CmpInGPR == ICGPR_None)
2476 switch (N->getOpcode()) {
2478 case ISD::ZERO_EXTEND:
2479 if (CmpInGPR == ICGPR_Sext || CmpInGPR == ICGPR_SextI32 ||
2480 CmpInGPR == ICGPR_SextI64)
2483 case ISD::SIGN_EXTEND:
2484 if (CmpInGPR == ICGPR_Zext || CmpInGPR == ICGPR_ZextI32 ||
2485 CmpInGPR == ICGPR_ZextI64)
2487 return tryEXTEND(N);
2491 return tryLogicOpOfCompares(N);
2497 static bool isLogicOp(unsigned Opc) {
2498 return Opc == ISD::AND || Opc == ISD::OR || Opc == ISD::XOR;
2500 // The obvious case for wanting to keep the value in a GPR. Namely, the
2501 // result of the comparison is actually needed in a GPR.
2502 SDNode *IntegerCompareEliminator::tryEXTEND(SDNode *N) {
2503 assert((N->getOpcode() == ISD::ZERO_EXTEND ||
2504 N->getOpcode() == ISD::SIGN_EXTEND) &&
2505 "Expecting a zero/sign extend node!");
2507 // If we are zero-extending the result of a logical operation on i1
2508 // values, we can keep the values in GPRs.
2509 if (isLogicOp(N->getOperand(0).getOpcode()) &&
2510 N->getOperand(0).getValueType() == MVT::i1 &&
2511 N->getOpcode() == ISD::ZERO_EXTEND)
2512 WideRes = computeLogicOpInGPR(N->getOperand(0));
2513 else if (N->getOperand(0).getOpcode() != ISD::SETCC)
2517 getSETCCInGPR(N->getOperand(0),
2518 N->getOpcode() == ISD::SIGN_EXTEND ?
2519 SetccInGPROpts::SExtOrig : SetccInGPROpts::ZExtOrig);
2525 bool Input32Bit = WideRes.getValueType() == MVT::i32;
2526 bool Output32Bit = N->getValueType(0) == MVT::i32;
2528 NumSextSetcc += N->getOpcode() == ISD::SIGN_EXTEND ? 1 : 0;
2529 NumZextSetcc += N->getOpcode() == ISD::SIGN_EXTEND ? 0 : 1;
2531 SDValue ConvOp = WideRes;
2532 if (Input32Bit != Output32Bit)
2533 ConvOp = addExtOrTrunc(WideRes, Input32Bit ? ExtOrTruncConversion::Ext :
2534 ExtOrTruncConversion::Trunc);
2535 return ConvOp.getNode();
2538 // Attempt to perform logical operations on the results of comparisons while
2539 // keeping the values in GPRs. Without doing so, these would end up being
2540 // lowered to CR-logical operations which suffer from significant latency and
2542 SDNode *IntegerCompareEliminator::tryLogicOpOfCompares(SDNode *N) {
2543 if (N->getValueType(0) != MVT::i1)
2545 assert(isLogicOp(N->getOpcode()) &&
2546 "Expected a logic operation on setcc results.");
2547 SDValue LoweredLogical = computeLogicOpInGPR(SDValue(N, 0));
2548 if (!LoweredLogical)
2552 bool IsBitwiseNegate = LoweredLogical.getMachineOpcode() == PPC::XORI8;
2553 unsigned SubRegToExtract = IsBitwiseNegate ? PPC::sub_eq : PPC::sub_gt;
2554 SDValue CR0Reg = CurDAG->getRegister(PPC::CR0, MVT::i32);
2555 SDValue LHS = LoweredLogical.getOperand(0);
2556 SDValue RHS = LoweredLogical.getOperand(1);
2558 SDValue OpToConvToRecForm;
2560 // Look through any 32-bit to 64-bit implicit extend nodes to find the
2561 // opcode that is input to the XORI.
2562 if (IsBitwiseNegate &&
2563 LoweredLogical.getOperand(0).getMachineOpcode() == PPC::INSERT_SUBREG)
2564 OpToConvToRecForm = LoweredLogical.getOperand(0).getOperand(1);
2565 else if (IsBitwiseNegate)
2566 // If the input to the XORI isn't an extension, that's what we're after.
2567 OpToConvToRecForm = LoweredLogical.getOperand(0);
2569 // If this is not an XORI, it is a reg-reg logical op and we can convert
2570 // it to record-form.
2571 OpToConvToRecForm = LoweredLogical;
2573 // Get the record-form version of the node we're looking to use to get the
2575 uint16_t NonRecOpc = OpToConvToRecForm.getMachineOpcode();
2576 int NewOpc = PPCInstrInfo::getRecordFormOpcode(NonRecOpc);
2578 // Convert the right node to record-form. This is either the logical we're
2579 // looking at or it is the input node to the negation (if we're looking at
2580 // a bitwise negation).
2581 if (NewOpc != -1 && IsBitwiseNegate) {
2582 // The input to the XORI has a record-form. Use it.
2583 assert(LoweredLogical.getConstantOperandVal(1) == 1 &&
2584 "Expected a PPC::XORI8 only for bitwise negation.");
2585 // Emit the record-form instruction.
2586 std::vector<SDValue> Ops;
2587 for (int i = 0, e = OpToConvToRecForm.getNumOperands(); i < e; i++)
2588 Ops.push_back(OpToConvToRecForm.getOperand(i));
2591 SDValue(CurDAG->getMachineNode(NewOpc, dl,
2592 OpToConvToRecForm.getValueType(),
2593 MVT::Glue, Ops), 0);
2595 assert((NewOpc != -1 || !IsBitwiseNegate) &&
2596 "No record form available for AND8/OR8/XOR8?");
2598 SDValue(CurDAG->getMachineNode(NewOpc == -1 ? PPC::ANDIo8 : NewOpc, dl,
2599 MVT::i64, MVT::Glue, LHS, RHS), 0);
2602 // Select this node to a single bit from CR0 set by the record-form node
2603 // just created. For bitwise negation, use the EQ bit which is the equivalent
2604 // of negating the result (i.e. it is a bit set when the result of the
2605 // operation is zero).
2607 CurDAG->getTargetConstant(SubRegToExtract, dl, MVT::i32);
2609 SDValue(CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG, dl,
2610 MVT::i1, CR0Reg, SRIdxVal,
2611 WideOp.getValue(1)), 0);
2612 return CRBit.getNode();
2615 // Lower a logical operation on i1 values into a GPR sequence if possible.
2616 // The result can be kept in a GPR if requested.
2617 // Three types of inputs can be handled:
2620 // - Logical operation (AND/OR/XOR)
2621 // There is also a special case that is handled (namely a complement operation
2622 // achieved with xor %a, -1).
2623 SDValue IntegerCompareEliminator::computeLogicOpInGPR(SDValue LogicOp) {
2624 assert(isLogicOp(LogicOp.getOpcode()) &&
2625 "Can only handle logic operations here.");
2626 assert(LogicOp.getValueType() == MVT::i1 &&
2627 "Can only handle logic operations on i1 values here.");
2631 // Special case: xor %a, -1
2632 bool IsBitwiseNegation = isBitwiseNot(LogicOp);
2634 // Produces a GPR sequence for each operand of the binary logic operation.
2635 // For SETCC, it produces the respective comparison, for TRUNCATE it truncates
2636 // the value in a GPR and for logic operations, it will recursively produce
2637 // a GPR sequence for the operation.
2638 auto getLogicOperand = [&] (SDValue Operand) -> SDValue {
2639 unsigned OperandOpcode = Operand.getOpcode();
2640 if (OperandOpcode == ISD::SETCC)
2641 return getSETCCInGPR(Operand, SetccInGPROpts::ZExtOrig);
2642 else if (OperandOpcode == ISD::TRUNCATE) {
2643 SDValue InputOp = Operand.getOperand(0);
2644 EVT InVT = InputOp.getValueType();
2645 return SDValue(CurDAG->getMachineNode(InVT == MVT::i32 ? PPC::RLDICL_32 :
2646 PPC::RLDICL, dl, InVT, InputOp,
2647 S->getI64Imm(0, dl),
2648 S->getI64Imm(63, dl)), 0);
2649 } else if (isLogicOp(OperandOpcode))
2650 return computeLogicOpInGPR(Operand);
2653 LHS = getLogicOperand(LogicOp.getOperand(0));
2654 RHS = getLogicOperand(LogicOp.getOperand(1));
2656 // If a GPR sequence can't be produced for the LHS we can't proceed.
2657 // Not producing a GPR sequence for the RHS is only a problem if this isn't
2658 // a bitwise negation operation.
2659 if (!LHS || (!RHS && !IsBitwiseNegation))
2662 NumLogicOpsOnComparison++;
2664 // We will use the inputs as 64-bit values.
2665 if (LHS.getValueType() == MVT::i32)
2666 LHS = addExtOrTrunc(LHS, ExtOrTruncConversion::Ext);
2667 if (!IsBitwiseNegation && RHS.getValueType() == MVT::i32)
2668 RHS = addExtOrTrunc(RHS, ExtOrTruncConversion::Ext);
2671 switch (LogicOp.getOpcode()) {
2672 default: llvm_unreachable("Unknown logic operation.");
2673 case ISD::AND: NewOpc = PPC::AND8; break;
2674 case ISD::OR: NewOpc = PPC::OR8; break;
2675 case ISD::XOR: NewOpc = PPC::XOR8; break;
2678 if (IsBitwiseNegation) {
2679 RHS = S->getI64Imm(1, dl);
2680 NewOpc = PPC::XORI8;
2683 return SDValue(CurDAG->getMachineNode(NewOpc, dl, MVT::i64, LHS, RHS), 0);
2687 /// If the value isn't guaranteed to be sign-extended to 64-bits, extend it.
2688 /// Otherwise just reinterpret it as a 64-bit value.
2689 /// Useful when emitting comparison code for 32-bit values without using
2690 /// the compare instruction (which only considers the lower 32-bits).
2691 SDValue IntegerCompareEliminator::signExtendInputIfNeeded(SDValue Input) {
2692 assert(Input.getValueType() == MVT::i32 &&
2693 "Can only sign-extend 32-bit values here.");
2694 unsigned Opc = Input.getOpcode();
2696 // The value was sign extended and then truncated to 32-bits. No need to
2697 // sign extend it again.
2698 if (Opc == ISD::TRUNCATE &&
2699 (Input.getOperand(0).getOpcode() == ISD::AssertSext ||
2700 Input.getOperand(0).getOpcode() == ISD::SIGN_EXTEND))
2701 return addExtOrTrunc(Input, ExtOrTruncConversion::Ext);
2703 LoadSDNode *InputLoad = dyn_cast<LoadSDNode>(Input);
2704 // The input is a sign-extending load. All ppc sign-extending loads
2705 // sign-extend to the full 64-bits.
2706 if (InputLoad && InputLoad->getExtensionType() == ISD::SEXTLOAD)
2707 return addExtOrTrunc(Input, ExtOrTruncConversion::Ext);
2709 ConstantSDNode *InputConst = dyn_cast<ConstantSDNode>(Input);
2710 // We don't sign-extend constants.
2712 return addExtOrTrunc(Input, ExtOrTruncConversion::Ext);
2715 SignExtensionsAdded++;
2716 return SDValue(CurDAG->getMachineNode(PPC::EXTSW_32_64, dl,
2717 MVT::i64, Input), 0);
2720 /// If the value isn't guaranteed to be zero-extended to 64-bits, extend it.
2721 /// Otherwise just reinterpret it as a 64-bit value.
2722 /// Useful when emitting comparison code for 32-bit values without using
2723 /// the compare instruction (which only considers the lower 32-bits).
2724 SDValue IntegerCompareEliminator::zeroExtendInputIfNeeded(SDValue Input) {
2725 assert(Input.getValueType() == MVT::i32 &&
2726 "Can only zero-extend 32-bit values here.");
2727 unsigned Opc = Input.getOpcode();
2729 // The only condition under which we can omit the actual extend instruction:
2730 // - The value is a positive constant
2731 // - The value comes from a load that isn't a sign-extending load
2732 // An ISD::TRUNCATE needs to be zero-extended unless it is fed by a zext.
2733 bool IsTruncateOfZExt = Opc == ISD::TRUNCATE &&
2734 (Input.getOperand(0).getOpcode() == ISD::AssertZext ||
2735 Input.getOperand(0).getOpcode() == ISD::ZERO_EXTEND);
2736 if (IsTruncateOfZExt)
2737 return addExtOrTrunc(Input, ExtOrTruncConversion::Ext);
2739 ConstantSDNode *InputConst = dyn_cast<ConstantSDNode>(Input);
2740 if (InputConst && InputConst->getSExtValue() >= 0)
2741 return addExtOrTrunc(Input, ExtOrTruncConversion::Ext);
2743 LoadSDNode *InputLoad = dyn_cast<LoadSDNode>(Input);
2744 // The input is a load that doesn't sign-extend (it will be zero-extended).
2745 if (InputLoad && InputLoad->getExtensionType() != ISD::SEXTLOAD)
2746 return addExtOrTrunc(Input, ExtOrTruncConversion::Ext);
2748 // None of the above, need to zero-extend.
2750 ZeroExtensionsAdded++;
2751 return SDValue(CurDAG->getMachineNode(PPC::RLDICL_32_64, dl, MVT::i64, Input,
2752 S->getI64Imm(0, dl),
2753 S->getI64Imm(32, dl)), 0);
2756 // Handle a 32-bit value in a 64-bit register and vice-versa. These are of
2757 // course not actual zero/sign extensions that will generate machine code,
2758 // they're just a way to reinterpret a 32 bit value in a register as a
2759 // 64 bit value and vice-versa.
2760 SDValue IntegerCompareEliminator::addExtOrTrunc(SDValue NatWidthRes,
2761 ExtOrTruncConversion Conv) {
2762 SDLoc dl(NatWidthRes);
2764 // For reinterpreting 32-bit values as 64 bit values, we generate
2765 // INSERT_SUBREG IMPLICIT_DEF:i64, <input>, TargetConstant:i32<1>
2766 if (Conv == ExtOrTruncConversion::Ext) {
2767 SDValue ImDef(CurDAG->getMachineNode(PPC::IMPLICIT_DEF, dl, MVT::i64), 0);
2769 CurDAG->getTargetConstant(PPC::sub_32, dl, MVT::i32);
2770 return SDValue(CurDAG->getMachineNode(PPC::INSERT_SUBREG, dl, MVT::i64,
2771 ImDef, NatWidthRes, SubRegIdx), 0);
2774 assert(Conv == ExtOrTruncConversion::Trunc &&
2775 "Unknown convertion between 32 and 64 bit values.");
2776 // For reinterpreting 64-bit values as 32-bit values, we just need to
2777 // EXTRACT_SUBREG (i.e. extract the low word).
2779 CurDAG->getTargetConstant(PPC::sub_32, dl, MVT::i32);
2780 return SDValue(CurDAG->getMachineNode(PPC::EXTRACT_SUBREG, dl, MVT::i32,
2781 NatWidthRes, SubRegIdx), 0);
2784 // Produce a GPR sequence for compound comparisons (<=, >=) against zero.
2785 // Handle both zero-extensions and sign-extensions.
2787 IntegerCompareEliminator::getCompoundZeroComparisonInGPR(SDValue LHS, SDLoc dl,
2788 ZeroCompare CmpTy) {
2789 EVT InVT = LHS.getValueType();
2790 bool Is32Bit = InVT == MVT::i32;
2793 // Produce the value that needs to be either zero or sign extended.
2795 case ZeroCompare::GEZExt:
2796 case ZeroCompare::GESExt:
2797 ToExtend = SDValue(CurDAG->getMachineNode(Is32Bit ? PPC::NOR : PPC::NOR8,
2798 dl, InVT, LHS, LHS), 0);
2800 case ZeroCompare::LEZExt:
2801 case ZeroCompare::LESExt: {
2803 // Upper 32 bits cannot be undefined for this sequence.
2804 LHS = signExtendInputIfNeeded(LHS);
2806 SDValue(CurDAG->getMachineNode(PPC::NEG8, dl, MVT::i64, LHS), 0);
2808 SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64,
2809 Neg, S->getI64Imm(1, dl),
2810 S->getI64Imm(63, dl)), 0);
2813 SDValue(CurDAG->getMachineNode(PPC::ADDI8, dl, MVT::i64, LHS,
2814 S->getI64Imm(~0ULL, dl)), 0);
2815 ToExtend = SDValue(CurDAG->getMachineNode(PPC::OR8, dl, MVT::i64,
2822 // For 64-bit sequences, the extensions are the same for the GE/LE cases.
2824 (CmpTy == ZeroCompare::GEZExt || CmpTy == ZeroCompare::LEZExt))
2825 return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64,
2826 ToExtend, S->getI64Imm(1, dl),
2827 S->getI64Imm(63, dl)), 0);
2829 (CmpTy == ZeroCompare::GESExt || CmpTy == ZeroCompare::LESExt))
2830 return SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, ToExtend,
2831 S->getI64Imm(63, dl)), 0);
2833 assert(Is32Bit && "Should have handled the 32-bit sequences above.");
2834 // For 32-bit sequences, the extensions differ between GE/LE cases.
2836 case ZeroCompare::GEZExt: {
2837 SDValue ShiftOps[] = { ToExtend, S->getI32Imm(1, dl), S->getI32Imm(31, dl),
2838 S->getI32Imm(31, dl) };
2839 return SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32,
2842 case ZeroCompare::GESExt:
2843 return SDValue(CurDAG->getMachineNode(PPC::SRAWI, dl, MVT::i32, ToExtend,
2844 S->getI32Imm(31, dl)), 0);
2845 case ZeroCompare::LEZExt:
2846 return SDValue(CurDAG->getMachineNode(PPC::XORI8, dl, MVT::i64, ToExtend,
2847 S->getI32Imm(1, dl)), 0);
2848 case ZeroCompare::LESExt:
2849 return SDValue(CurDAG->getMachineNode(PPC::ADDI8, dl, MVT::i64, ToExtend,
2850 S->getI32Imm(-1, dl)), 0);
2853 // The above case covers all the enumerators so it can't have a default clause
2854 // to avoid compiler warnings.
2855 llvm_unreachable("Unknown zero-comparison type.");
2858 /// Produces a zero-extended result of comparing two 32-bit values according to
2859 /// the passed condition code.
2861 IntegerCompareEliminator::get32BitZExtCompare(SDValue LHS, SDValue RHS,
2863 int64_t RHSValue, SDLoc dl) {
2864 if (CmpInGPR == ICGPR_I64 || CmpInGPR == ICGPR_SextI64 ||
2865 CmpInGPR == ICGPR_ZextI64 || CmpInGPR == ICGPR_Sext)
2867 bool IsRHSZero = RHSValue == 0;
2868 bool IsRHSOne = RHSValue == 1;
2869 bool IsRHSNegOne = RHSValue == -1LL;
2871 default: return SDValue();
2873 // (zext (setcc %a, %b, seteq)) -> (lshr (cntlzw (xor %a, %b)), 5)
2874 // (zext (setcc %a, 0, seteq)) -> (lshr (cntlzw %a), 5)
2875 SDValue Xor = IsRHSZero ? LHS :
2876 SDValue(CurDAG->getMachineNode(PPC::XOR, dl, MVT::i32, LHS, RHS), 0);
2878 SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, Xor), 0);
2879 SDValue ShiftOps[] = { Clz, S->getI32Imm(27, dl), S->getI32Imm(5, dl),
2880 S->getI32Imm(31, dl) };
2881 return SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32,
2885 // (zext (setcc %a, %b, setne)) -> (xor (lshr (cntlzw (xor %a, %b)), 5), 1)
2886 // (zext (setcc %a, 0, setne)) -> (xor (lshr (cntlzw %a), 5), 1)
2887 SDValue Xor = IsRHSZero ? LHS :
2888 SDValue(CurDAG->getMachineNode(PPC::XOR, dl, MVT::i32, LHS, RHS), 0);
2890 SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, Xor), 0);
2891 SDValue ShiftOps[] = { Clz, S->getI32Imm(27, dl), S->getI32Imm(5, dl),
2892 S->getI32Imm(31, dl) };
2894 SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, ShiftOps), 0);
2895 return SDValue(CurDAG->getMachineNode(PPC::XORI, dl, MVT::i32, Shift,
2896 S->getI32Imm(1, dl)), 0);
2899 // (zext (setcc %a, %b, setge)) -> (xor (lshr (sub %a, %b), 63), 1)
2900 // (zext (setcc %a, 0, setge)) -> (lshr (~ %a), 31)
2902 return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::GEZExt);
2904 // Not a special case (i.e. RHS == 0). Handle (%a >= %b) as (%b <= %a)
2905 // by swapping inputs and falling through.
2906 std::swap(LHS, RHS);
2907 ConstantSDNode *RHSConst = dyn_cast<ConstantSDNode>(RHS);
2908 IsRHSZero = RHSConst && RHSConst->isNullValue();
2912 if (CmpInGPR == ICGPR_NonExtIn)
2914 // (zext (setcc %a, %b, setle)) -> (xor (lshr (sub %b, %a), 63), 1)
2915 // (zext (setcc %a, 0, setle)) -> (xor (lshr (- %a), 63), 1)
2917 if (CmpInGPR == ICGPR_NonExtIn)
2919 return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::LEZExt);
2922 // The upper 32-bits of the register can't be undefined for this sequence.
2923 LHS = signExtendInputIfNeeded(LHS);
2924 RHS = signExtendInputIfNeeded(RHS);
2926 SDValue(CurDAG->getMachineNode(PPC::SUBF8, dl, MVT::i64, LHS, RHS), 0);
2928 SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, Sub,
2929 S->getI64Imm(1, dl), S->getI64Imm(63, dl)),
2932 SDValue(CurDAG->getMachineNode(PPC::XORI8, dl,
2933 MVT::i64, Shift, S->getI32Imm(1, dl)), 0);
2936 // (zext (setcc %a, %b, setgt)) -> (lshr (sub %b, %a), 63)
2937 // (zext (setcc %a, -1, setgt)) -> (lshr (~ %a), 31)
2938 // (zext (setcc %a, 0, setgt)) -> (lshr (- %a), 63)
2939 // Handle SETLT -1 (which is equivalent to SETGE 0).
2941 return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::GEZExt);
2944 if (CmpInGPR == ICGPR_NonExtIn)
2946 // The upper 32-bits of the register can't be undefined for this sequence.
2947 LHS = signExtendInputIfNeeded(LHS);
2948 RHS = signExtendInputIfNeeded(RHS);
2950 SDValue(CurDAG->getMachineNode(PPC::NEG8, dl, MVT::i64, LHS), 0);
2951 return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64,
2952 Neg, S->getI32Imm(1, dl), S->getI32Imm(63, dl)), 0);
2954 // Not a special case (i.e. RHS == 0 or RHS == -1). Handle (%a > %b) as
2955 // (%b < %a) by swapping inputs and falling through.
2956 std::swap(LHS, RHS);
2957 ConstantSDNode *RHSConst = dyn_cast<ConstantSDNode>(RHS);
2958 IsRHSZero = RHSConst && RHSConst->isNullValue();
2959 IsRHSOne = RHSConst && RHSConst->getSExtValue() == 1;
2963 // (zext (setcc %a, %b, setlt)) -> (lshr (sub %a, %b), 63)
2964 // (zext (setcc %a, 1, setlt)) -> (xor (lshr (- %a), 63), 1)
2965 // (zext (setcc %a, 0, setlt)) -> (lshr %a, 31)
2966 // Handle SETLT 1 (which is equivalent to SETLE 0).
2968 if (CmpInGPR == ICGPR_NonExtIn)
2970 return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::LEZExt);
2974 SDValue ShiftOps[] = { LHS, S->getI32Imm(1, dl), S->getI32Imm(31, dl),
2975 S->getI32Imm(31, dl) };
2976 return SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32,
2980 if (CmpInGPR == ICGPR_NonExtIn)
2982 // The upper 32-bits of the register can't be undefined for this sequence.
2983 LHS = signExtendInputIfNeeded(LHS);
2984 RHS = signExtendInputIfNeeded(RHS);
2986 SDValue(CurDAG->getMachineNode(PPC::SUBF8, dl, MVT::i64, RHS, LHS), 0);
2987 return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64,
2988 SUBFNode, S->getI64Imm(1, dl),
2989 S->getI64Imm(63, dl)), 0);
2992 // (zext (setcc %a, %b, setuge)) -> (xor (lshr (sub %b, %a), 63), 1)
2993 // (zext (setcc %a, %b, setule)) -> (xor (lshr (sub %a, %b), 63), 1)
2994 std::swap(LHS, RHS);
2997 if (CmpInGPR == ICGPR_NonExtIn)
2999 // The upper 32-bits of the register can't be undefined for this sequence.
3000 LHS = zeroExtendInputIfNeeded(LHS);
3001 RHS = zeroExtendInputIfNeeded(RHS);
3003 SDValue(CurDAG->getMachineNode(PPC::SUBF8, dl, MVT::i64, LHS, RHS), 0);
3005 SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64,
3006 Subtract, S->getI64Imm(1, dl),
3007 S->getI64Imm(63, dl)), 0);
3008 return SDValue(CurDAG->getMachineNode(PPC::XORI8, dl, MVT::i64, SrdiNode,
3009 S->getI32Imm(1, dl)), 0);
3012 // (zext (setcc %a, %b, setugt)) -> (lshr (sub %b, %a), 63)
3013 // (zext (setcc %a, %b, setult)) -> (lshr (sub %a, %b), 63)
3014 std::swap(LHS, RHS);
3017 if (CmpInGPR == ICGPR_NonExtIn)
3019 // The upper 32-bits of the register can't be undefined for this sequence.
3020 LHS = zeroExtendInputIfNeeded(LHS);
3021 RHS = zeroExtendInputIfNeeded(RHS);
3023 SDValue(CurDAG->getMachineNode(PPC::SUBF8, dl, MVT::i64, RHS, LHS), 0);
3024 return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64,
3025 Subtract, S->getI64Imm(1, dl),
3026 S->getI64Imm(63, dl)), 0);
3031 /// Produces a sign-extended result of comparing two 32-bit values according to
3032 /// the passed condition code.
3034 IntegerCompareEliminator::get32BitSExtCompare(SDValue LHS, SDValue RHS,
3036 int64_t RHSValue, SDLoc dl) {
3037 if (CmpInGPR == ICGPR_I64 || CmpInGPR == ICGPR_SextI64 ||
3038 CmpInGPR == ICGPR_ZextI64 || CmpInGPR == ICGPR_Zext)
3040 bool IsRHSZero = RHSValue == 0;
3041 bool IsRHSOne = RHSValue == 1;
3042 bool IsRHSNegOne = RHSValue == -1LL;
3045 default: return SDValue();
3047 // (sext (setcc %a, %b, seteq)) ->
3048 // (ashr (shl (ctlz (xor %a, %b)), 58), 63)
3049 // (sext (setcc %a, 0, seteq)) ->
3050 // (ashr (shl (ctlz %a), 58), 63)
3051 SDValue CountInput = IsRHSZero ? LHS :
3052 SDValue(CurDAG->getMachineNode(PPC::XOR, dl, MVT::i32, LHS, RHS), 0);
3054 SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, CountInput), 0);
3055 SDValue SHLOps[] = { Cntlzw, S->getI32Imm(27, dl),
3056 S->getI32Imm(5, dl), S->getI32Imm(31, dl) };
3058 SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, SHLOps), 0);
3059 return SDValue(CurDAG->getMachineNode(PPC::NEG, dl, MVT::i32, Slwi), 0);
3062 // Bitwise xor the operands, count leading zeros, shift right by 5 bits and
3063 // flip the bit, finally take 2's complement.
3064 // (sext (setcc %a, %b, setne)) ->
3065 // (neg (xor (lshr (ctlz (xor %a, %b)), 5), 1))
3066 // Same as above, but the first xor is not needed.
3067 // (sext (setcc %a, 0, setne)) ->
3068 // (neg (xor (lshr (ctlz %a), 5), 1))
3069 SDValue Xor = IsRHSZero ? LHS :
3070 SDValue(CurDAG->getMachineNode(PPC::XOR, dl, MVT::i32, LHS, RHS), 0);
3072 SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, Xor), 0);
3073 SDValue ShiftOps[] =
3074 { Clz, S->getI32Imm(27, dl), S->getI32Imm(5, dl), S->getI32Imm(31, dl) };
3076 SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, ShiftOps), 0);
3078 SDValue(CurDAG->getMachineNode(PPC::XORI, dl, MVT::i32, Shift,
3079 S->getI32Imm(1, dl)), 0);
3080 return SDValue(CurDAG->getMachineNode(PPC::NEG, dl, MVT::i32, Xori), 0);
3083 // (sext (setcc %a, %b, setge)) -> (add (lshr (sub %a, %b), 63), -1)
3084 // (sext (setcc %a, 0, setge)) -> (ashr (~ %a), 31)
3086 return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::GESExt);
3088 // Not a special case (i.e. RHS == 0). Handle (%a >= %b) as (%b <= %a)
3089 // by swapping inputs and falling through.
3090 std::swap(LHS, RHS);
3091 ConstantSDNode *RHSConst = dyn_cast<ConstantSDNode>(RHS);
3092 IsRHSZero = RHSConst && RHSConst->isNullValue();
3096 if (CmpInGPR == ICGPR_NonExtIn)
3098 // (sext (setcc %a, %b, setge)) -> (add (lshr (sub %b, %a), 63), -1)
3099 // (sext (setcc %a, 0, setle)) -> (add (lshr (- %a), 63), -1)
3101 return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::LESExt);
3103 // The upper 32-bits of the register can't be undefined for this sequence.
3104 LHS = signExtendInputIfNeeded(LHS);
3105 RHS = signExtendInputIfNeeded(RHS);
3107 SDValue(CurDAG->getMachineNode(PPC::SUBF8, dl, MVT::i64, MVT::Glue,
3110 SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64,
3111 SUBFNode, S->getI64Imm(1, dl),
3112 S->getI64Imm(63, dl)), 0);
3113 return SDValue(CurDAG->getMachineNode(PPC::ADDI8, dl, MVT::i64, Srdi,
3114 S->getI32Imm(-1, dl)), 0);
3117 // (sext (setcc %a, %b, setgt)) -> (ashr (sub %b, %a), 63)
3118 // (sext (setcc %a, -1, setgt)) -> (ashr (~ %a), 31)
3119 // (sext (setcc %a, 0, setgt)) -> (ashr (- %a), 63)
3121 return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::GESExt);
3123 if (CmpInGPR == ICGPR_NonExtIn)
3125 // The upper 32-bits of the register can't be undefined for this sequence.
3126 LHS = signExtendInputIfNeeded(LHS);
3127 RHS = signExtendInputIfNeeded(RHS);
3129 SDValue(CurDAG->getMachineNode(PPC::NEG8, dl, MVT::i64, LHS), 0);
3130 return SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, Neg,
3131 S->getI64Imm(63, dl)), 0);
3133 // Not a special case (i.e. RHS == 0 or RHS == -1). Handle (%a > %b) as
3134 // (%b < %a) by swapping inputs and falling through.
3135 std::swap(LHS, RHS);
3136 ConstantSDNode *RHSConst = dyn_cast<ConstantSDNode>(RHS);
3137 IsRHSZero = RHSConst && RHSConst->isNullValue();
3138 IsRHSOne = RHSConst && RHSConst->getSExtValue() == 1;
3142 // (sext (setcc %a, %b, setgt)) -> (ashr (sub %a, %b), 63)
3143 // (sext (setcc %a, 1, setgt)) -> (add (lshr (- %a), 63), -1)
3144 // (sext (setcc %a, 0, setgt)) -> (ashr %a, 31)
3146 if (CmpInGPR == ICGPR_NonExtIn)
3148 return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::LESExt);
3151 return SDValue(CurDAG->getMachineNode(PPC::SRAWI, dl, MVT::i32, LHS,
3152 S->getI32Imm(31, dl)), 0);
3154 if (CmpInGPR == ICGPR_NonExtIn)
3156 // The upper 32-bits of the register can't be undefined for this sequence.
3157 LHS = signExtendInputIfNeeded(LHS);
3158 RHS = signExtendInputIfNeeded(RHS);
3160 SDValue(CurDAG->getMachineNode(PPC::SUBF8, dl, MVT::i64, RHS, LHS), 0);
3161 return SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64,
3162 SUBFNode, S->getI64Imm(63, dl)), 0);
3165 // (sext (setcc %a, %b, setuge)) -> (add (lshr (sub %a, %b), 63), -1)
3166 // (sext (setcc %a, %b, setule)) -> (add (lshr (sub %b, %a), 63), -1)
3167 std::swap(LHS, RHS);
3170 if (CmpInGPR == ICGPR_NonExtIn)
3172 // The upper 32-bits of the register can't be undefined for this sequence.
3173 LHS = zeroExtendInputIfNeeded(LHS);
3174 RHS = zeroExtendInputIfNeeded(RHS);
3176 SDValue(CurDAG->getMachineNode(PPC::SUBF8, dl, MVT::i64, LHS, RHS), 0);
3178 SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, Subtract,
3179 S->getI32Imm(1, dl), S->getI32Imm(63,dl)),
3181 return SDValue(CurDAG->getMachineNode(PPC::ADDI8, dl, MVT::i64, Shift,
3182 S->getI32Imm(-1, dl)), 0);
3185 // (sext (setcc %a, %b, setugt)) -> (ashr (sub %b, %a), 63)
3186 // (sext (setcc %a, %b, setugt)) -> (ashr (sub %a, %b), 63)
3187 std::swap(LHS, RHS);
3190 if (CmpInGPR == ICGPR_NonExtIn)
3192 // The upper 32-bits of the register can't be undefined for this sequence.
3193 LHS = zeroExtendInputIfNeeded(LHS);
3194 RHS = zeroExtendInputIfNeeded(RHS);
3196 SDValue(CurDAG->getMachineNode(PPC::SUBF8, dl, MVT::i64, RHS, LHS), 0);
3197 return SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64,
3198 Subtract, S->getI64Imm(63, dl)), 0);
3203 /// Produces a zero-extended result of comparing two 64-bit values according to
3204 /// the passed condition code.
3206 IntegerCompareEliminator::get64BitZExtCompare(SDValue LHS, SDValue RHS,
3208 int64_t RHSValue, SDLoc dl) {
3209 if (CmpInGPR == ICGPR_I32 || CmpInGPR == ICGPR_SextI32 ||
3210 CmpInGPR == ICGPR_ZextI32 || CmpInGPR == ICGPR_Sext)
3212 bool IsRHSZero = RHSValue == 0;
3213 bool IsRHSOne = RHSValue == 1;
3214 bool IsRHSNegOne = RHSValue == -1LL;
3216 default: return SDValue();
3218 // (zext (setcc %a, %b, seteq)) -> (lshr (ctlz (xor %a, %b)), 6)
3219 // (zext (setcc %a, 0, seteq)) -> (lshr (ctlz %a), 6)
3220 SDValue Xor = IsRHSZero ? LHS :
3221 SDValue(CurDAG->getMachineNode(PPC::XOR8, dl, MVT::i64, LHS, RHS), 0);
3223 SDValue(CurDAG->getMachineNode(PPC::CNTLZD, dl, MVT::i64, Xor), 0);
3224 return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, Clz,
3225 S->getI64Imm(58, dl),
3226 S->getI64Imm(63, dl)), 0);
3229 // {addc.reg, addc.CA} = (addcarry (xor %a, %b), -1)
3230 // (zext (setcc %a, %b, setne)) -> (sube addc.reg, addc.reg, addc.CA)
3231 // {addcz.reg, addcz.CA} = (addcarry %a, -1)
3232 // (zext (setcc %a, 0, setne)) -> (sube addcz.reg, addcz.reg, addcz.CA)
3233 SDValue Xor = IsRHSZero ? LHS :
3234 SDValue(CurDAG->getMachineNode(PPC::XOR8, dl, MVT::i64, LHS, RHS), 0);
3236 SDValue(CurDAG->getMachineNode(PPC::ADDIC8, dl, MVT::i64, MVT::Glue,
3237 Xor, S->getI32Imm(~0U, dl)), 0);
3238 return SDValue(CurDAG->getMachineNode(PPC::SUBFE8, dl, MVT::i64, AC,
3239 Xor, AC.getValue(1)), 0);
3242 // {subc.reg, subc.CA} = (subcarry %a, %b)
3243 // (zext (setcc %a, %b, setge)) ->
3244 // (adde (lshr %b, 63), (ashr %a, 63), subc.CA)
3245 // (zext (setcc %a, 0, setge)) -> (lshr (~ %a), 63)
3247 return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::GEZExt);
3248 std::swap(LHS, RHS);
3249 ConstantSDNode *RHSConst = dyn_cast<ConstantSDNode>(RHS);
3250 IsRHSZero = RHSConst && RHSConst->isNullValue();
3254 // {subc.reg, subc.CA} = (subcarry %b, %a)
3255 // (zext (setcc %a, %b, setge)) ->
3256 // (adde (lshr %a, 63), (ashr %b, 63), subc.CA)
3257 // (zext (setcc %a, 0, setge)) -> (lshr (or %a, (add %a, -1)), 63)
3259 return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::LEZExt);
3261 SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, LHS,
3262 S->getI64Imm(1, dl),
3263 S->getI64Imm(63, dl)), 0);
3265 SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, RHS,
3266 S->getI64Imm(63, dl)), 0);
3267 SDValue SubtractCarry =
3268 SDValue(CurDAG->getMachineNode(PPC::SUBFC8, dl, MVT::i64, MVT::Glue,
3270 return SDValue(CurDAG->getMachineNode(PPC::ADDE8, dl, MVT::i64, MVT::Glue,
3271 ShiftR, ShiftL, SubtractCarry), 0);
3274 // {subc.reg, subc.CA} = (subcarry %b, %a)
3275 // (zext (setcc %a, %b, setgt)) ->
3276 // (xor (adde (lshr %a, 63), (ashr %b, 63), subc.CA), 1)
3277 // (zext (setcc %a, 0, setgt)) -> (lshr (nor (add %a, -1), %a), 63)
3279 return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::GEZExt);
3282 SDValue(CurDAG->getMachineNode(PPC::ADDI8, dl, MVT::i64, LHS,
3283 S->getI64Imm(~0ULL, dl)), 0);
3285 SDValue(CurDAG->getMachineNode(PPC::NOR8, dl, MVT::i64, Addi, LHS), 0);
3286 return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, Nor,
3287 S->getI64Imm(1, dl),
3288 S->getI64Imm(63, dl)), 0);
3290 std::swap(LHS, RHS);
3291 ConstantSDNode *RHSConst = dyn_cast<ConstantSDNode>(RHS);
3292 IsRHSZero = RHSConst && RHSConst->isNullValue();
3293 IsRHSOne = RHSConst && RHSConst->getSExtValue() == 1;
3297 // {subc.reg, subc.CA} = (subcarry %a, %b)
3298 // (zext (setcc %a, %b, setlt)) ->
3299 // (xor (adde (lshr %b, 63), (ashr %a, 63), subc.CA), 1)
3300 // (zext (setcc %a, 0, setlt)) -> (lshr %a, 63)
3302 return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::LEZExt);
3304 return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, LHS,
3305 S->getI64Imm(1, dl),
3306 S->getI64Imm(63, dl)), 0);
3308 SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64,
3309 LHS, S->getI64Imm(63, dl)), 0);
3311 SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64,
3312 RHS, S->getI64Imm(1, dl),
3313 S->getI64Imm(63, dl)), 0);
3314 SDValue SUBFC8Carry =
3315 SDValue(CurDAG->getMachineNode(PPC::SUBFC8, dl, MVT::i64, MVT::Glue,
3318 SDValue(CurDAG->getMachineNode(PPC::ADDE8, dl, MVT::i64, MVT::Glue,
3319 SRDINode, SRADINode, SUBFC8Carry), 0);
3320 return SDValue(CurDAG->getMachineNode(PPC::XORI8, dl, MVT::i64,
3321 ADDE8Node, S->getI64Imm(1, dl)), 0);
3324 // {subc.reg, subc.CA} = (subcarry %a, %b)
3325 // (zext (setcc %a, %b, setuge)) -> (add (sube %b, %b, subc.CA), 1)
3326 std::swap(LHS, RHS);
3329 // {subc.reg, subc.CA} = (subcarry %b, %a)
3330 // (zext (setcc %a, %b, setule)) -> (add (sube %a, %a, subc.CA), 1)
3331 SDValue SUBFC8Carry =
3332 SDValue(CurDAG->getMachineNode(PPC::SUBFC8, dl, MVT::i64, MVT::Glue,
3334 SDValue SUBFE8Node =
3335 SDValue(CurDAG->getMachineNode(PPC::SUBFE8, dl, MVT::i64, MVT::Glue,
3336 LHS, LHS, SUBFC8Carry), 0);
3337 return SDValue(CurDAG->getMachineNode(PPC::ADDI8, dl, MVT::i64,
3338 SUBFE8Node, S->getI64Imm(1, dl)), 0);
3341 // {subc.reg, subc.CA} = (subcarry %b, %a)
3342 // (zext (setcc %a, %b, setugt)) -> -(sube %b, %b, subc.CA)
3343 std::swap(LHS, RHS);
3346 // {subc.reg, subc.CA} = (subcarry %a, %b)
3347 // (zext (setcc %a, %b, setult)) -> -(sube %a, %a, subc.CA)
3348 SDValue SubtractCarry =
3349 SDValue(CurDAG->getMachineNode(PPC::SUBFC8, dl, MVT::i64, MVT::Glue,
3352 SDValue(CurDAG->getMachineNode(PPC::SUBFE8, dl, MVT::i64,
3353 LHS, LHS, SubtractCarry), 0);
3354 return SDValue(CurDAG->getMachineNode(PPC::NEG8, dl, MVT::i64,
3360 /// Produces a sign-extended result of comparing two 64-bit values according to
3361 /// the passed condition code.
3363 IntegerCompareEliminator::get64BitSExtCompare(SDValue LHS, SDValue RHS,
3365 int64_t RHSValue, SDLoc dl) {
3366 if (CmpInGPR == ICGPR_I32 || CmpInGPR == ICGPR_SextI32 ||
3367 CmpInGPR == ICGPR_ZextI32 || CmpInGPR == ICGPR_Zext)
3369 bool IsRHSZero = RHSValue == 0;
3370 bool IsRHSOne = RHSValue == 1;
3371 bool IsRHSNegOne = RHSValue == -1LL;
3373 default: return SDValue();
3375 // {addc.reg, addc.CA} = (addcarry (xor %a, %b), -1)
3376 // (sext (setcc %a, %b, seteq)) -> (sube addc.reg, addc.reg, addc.CA)
3377 // {addcz.reg, addcz.CA} = (addcarry %a, -1)
3378 // (sext (setcc %a, 0, seteq)) -> (sube addcz.reg, addcz.reg, addcz.CA)
3379 SDValue AddInput = IsRHSZero ? LHS :
3380 SDValue(CurDAG->getMachineNode(PPC::XOR8, dl, MVT::i64, LHS, RHS), 0);
3382 SDValue(CurDAG->getMachineNode(PPC::ADDIC8, dl, MVT::i64, MVT::Glue,
3383 AddInput, S->getI32Imm(~0U, dl)), 0);
3384 return SDValue(CurDAG->getMachineNode(PPC::SUBFE8, dl, MVT::i64, Addic,
3385 Addic, Addic.getValue(1)), 0);
3388 // {subfc.reg, subfc.CA} = (subcarry 0, (xor %a, %b))
3389 // (sext (setcc %a, %b, setne)) -> (sube subfc.reg, subfc.reg, subfc.CA)
3390 // {subfcz.reg, subfcz.CA} = (subcarry 0, %a)
3391 // (sext (setcc %a, 0, setne)) -> (sube subfcz.reg, subfcz.reg, subfcz.CA)
3392 SDValue Xor = IsRHSZero ? LHS :
3393 SDValue(CurDAG->getMachineNode(PPC::XOR8, dl, MVT::i64, LHS, RHS), 0);
3395 SDValue(CurDAG->getMachineNode(PPC::SUBFIC8, dl, MVT::i64, MVT::Glue,
3396 Xor, S->getI32Imm(0, dl)), 0);
3397 return SDValue(CurDAG->getMachineNode(PPC::SUBFE8, dl, MVT::i64, SC,
3398 SC, SC.getValue(1)), 0);
3401 // {subc.reg, subc.CA} = (subcarry %a, %b)
3402 // (zext (setcc %a, %b, setge)) ->
3403 // (- (adde (lshr %b, 63), (ashr %a, 63), subc.CA))
3404 // (zext (setcc %a, 0, setge)) -> (~ (ashr %a, 63))
3406 return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::GESExt);
3407 std::swap(LHS, RHS);
3408 ConstantSDNode *RHSConst = dyn_cast<ConstantSDNode>(RHS);
3409 IsRHSZero = RHSConst && RHSConst->isNullValue();
3413 // {subc.reg, subc.CA} = (subcarry %b, %a)
3414 // (zext (setcc %a, %b, setge)) ->
3415 // (- (adde (lshr %a, 63), (ashr %b, 63), subc.CA))
3416 // (zext (setcc %a, 0, setge)) -> (ashr (or %a, (add %a, -1)), 63)
3418 return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::LESExt);
3420 SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, RHS,
3421 S->getI64Imm(63, dl)), 0);
3423 SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, LHS,
3424 S->getI64Imm(1, dl),
3425 S->getI64Imm(63, dl)), 0);
3426 SDValue SubtractCarry =
3427 SDValue(CurDAG->getMachineNode(PPC::SUBFC8, dl, MVT::i64, MVT::Glue,
3430 SDValue(CurDAG->getMachineNode(PPC::ADDE8, dl, MVT::i64, MVT::Glue,
3431 ShiftR, ShiftL, SubtractCarry), 0);
3432 return SDValue(CurDAG->getMachineNode(PPC::NEG8, dl, MVT::i64, Adde), 0);
3435 // {subc.reg, subc.CA} = (subcarry %b, %a)
3436 // (zext (setcc %a, %b, setgt)) ->
3437 // -(xor (adde (lshr %a, 63), (ashr %b, 63), subc.CA), 1)
3438 // (zext (setcc %a, 0, setgt)) -> (ashr (nor (add %a, -1), %a), 63)
3440 return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::GESExt);
3443 SDValue(CurDAG->getMachineNode(PPC::ADDI8, dl, MVT::i64, LHS,
3444 S->getI64Imm(-1, dl)), 0);
3446 SDValue(CurDAG->getMachineNode(PPC::NOR8, dl, MVT::i64, Add, LHS), 0);
3447 return SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, Nor,
3448 S->getI64Imm(63, dl)), 0);
3450 std::swap(LHS, RHS);
3451 ConstantSDNode *RHSConst = dyn_cast<ConstantSDNode>(RHS);
3452 IsRHSZero = RHSConst && RHSConst->isNullValue();
3453 IsRHSOne = RHSConst && RHSConst->getSExtValue() == 1;
3457 // {subc.reg, subc.CA} = (subcarry %a, %b)
3458 // (zext (setcc %a, %b, setlt)) ->
3459 // -(xor (adde (lshr %b, 63), (ashr %a, 63), subc.CA), 1)
3460 // (zext (setcc %a, 0, setlt)) -> (ashr %a, 63)
3462 return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::LESExt);
3464 return SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, LHS,
3465 S->getI64Imm(63, dl)), 0);
3468 SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64,
3469 LHS, S->getI64Imm(63, dl)), 0);
3471 SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64,
3472 RHS, S->getI64Imm(1, dl),
3473 S->getI64Imm(63, dl)), 0);
3474 SDValue SUBFC8Carry =
3475 SDValue(CurDAG->getMachineNode(PPC::SUBFC8, dl, MVT::i64, MVT::Glue,
3478 SDValue(CurDAG->getMachineNode(PPC::ADDE8, dl, MVT::i64,
3479 SRDINode, SRADINode, SUBFC8Carry), 0);
3481 SDValue(CurDAG->getMachineNode(PPC::XORI8, dl, MVT::i64,
3482 ADDE8Node, S->getI64Imm(1, dl)), 0);
3483 return SDValue(CurDAG->getMachineNode(PPC::NEG8, dl, MVT::i64,
3487 // {subc.reg, subc.CA} = (subcarry %a, %b)
3488 // (sext (setcc %a, %b, setuge)) -> ~(sube %b, %b, subc.CA)
3489 std::swap(LHS, RHS);
3492 // {subc.reg, subc.CA} = (subcarry %b, %a)
3493 // (sext (setcc %a, %b, setule)) -> ~(sube %a, %a, subc.CA)
3494 SDValue SubtractCarry =
3495 SDValue(CurDAG->getMachineNode(PPC::SUBFC8, dl, MVT::i64, MVT::Glue,
3498 SDValue(CurDAG->getMachineNode(PPC::SUBFE8, dl, MVT::i64, MVT::Glue, LHS,
3499 LHS, SubtractCarry), 0);
3500 return SDValue(CurDAG->getMachineNode(PPC::NOR8, dl, MVT::i64,
3501 ExtSub, ExtSub), 0);
3504 // {subc.reg, subc.CA} = (subcarry %b, %a)
3505 // (sext (setcc %a, %b, setugt)) -> (sube %b, %b, subc.CA)
3506 std::swap(LHS, RHS);
3509 // {subc.reg, subc.CA} = (subcarry %a, %b)
3510 // (sext (setcc %a, %b, setult)) -> (sube %a, %a, subc.CA)
3512 SDValue(CurDAG->getMachineNode(PPC::SUBFC8, dl, MVT::i64, MVT::Glue,
3514 return SDValue(CurDAG->getMachineNode(PPC::SUBFE8, dl, MVT::i64,
3515 LHS, LHS, SubCarry), 0);
3520 /// Do all uses of this SDValue need the result in a GPR?
3521 /// This is meant to be used on values that have type i1 since
3522 /// it is somewhat meaningless to ask if values of other types
3523 /// should be kept in GPR's.
3524 static bool allUsesExtend(SDValue Compare, SelectionDAG *CurDAG) {
3525 assert(Compare.getOpcode() == ISD::SETCC &&
3526 "An ISD::SETCC node required here.");
3528 // For values that have a single use, the caller should obviously already have
3529 // checked if that use is an extending use. We check the other uses here.
3530 if (Compare.hasOneUse())
3532 // We want the value in a GPR if it is being extended, used for a select, or
3533 // used in logical operations.
3534 for (auto CompareUse : Compare.getNode()->uses())
3535 if (CompareUse->getOpcode() != ISD::SIGN_EXTEND &&
3536 CompareUse->getOpcode() != ISD::ZERO_EXTEND &&
3537 CompareUse->getOpcode() != ISD::SELECT &&
3538 !isLogicOp(CompareUse->getOpcode())) {
3539 OmittedForNonExtendUses++;
3545 /// Returns an equivalent of a SETCC node but with the result the same width as
3546 /// the inputs. This can also be used for SELECT_CC if either the true or false
3547 /// values is a power of two while the other is zero.
3548 SDValue IntegerCompareEliminator::getSETCCInGPR(SDValue Compare,
3549 SetccInGPROpts ConvOpts) {
3550 assert((Compare.getOpcode() == ISD::SETCC ||
3551 Compare.getOpcode() == ISD::SELECT_CC) &&
3552 "An ISD::SETCC node required here.");
3554 // Don't convert this comparison to a GPR sequence because there are uses
3555 // of the i1 result (i.e. uses that require the result in the CR).
3556 if ((Compare.getOpcode() == ISD::SETCC) && !allUsesExtend(Compare, CurDAG))
3559 SDValue LHS = Compare.getOperand(0);
3560 SDValue RHS = Compare.getOperand(1);
3562 // The condition code is operand 2 for SETCC and operand 4 for SELECT_CC.
3563 int CCOpNum = Compare.getOpcode() == ISD::SELECT_CC ? 4 : 2;
3565 cast<CondCodeSDNode>(Compare.getOperand(CCOpNum))->get();
3566 EVT InputVT = LHS.getValueType();
3567 if (InputVT != MVT::i32 && InputVT != MVT::i64)
3570 if (ConvOpts == SetccInGPROpts::ZExtInvert ||
3571 ConvOpts == SetccInGPROpts::SExtInvert)
3572 CC = ISD::getSetCCInverse(CC, true);
3574 bool Inputs32Bit = InputVT == MVT::i32;
3577 ConstantSDNode *RHSConst = dyn_cast<ConstantSDNode>(RHS);
3578 int64_t RHSValue = RHSConst ? RHSConst->getSExtValue() : INT64_MAX;
3579 bool IsSext = ConvOpts == SetccInGPROpts::SExtOrig ||
3580 ConvOpts == SetccInGPROpts::SExtInvert;
3582 if (IsSext && Inputs32Bit)
3583 return get32BitSExtCompare(LHS, RHS, CC, RHSValue, dl);
3584 else if (Inputs32Bit)
3585 return get32BitZExtCompare(LHS, RHS, CC, RHSValue, dl);
3587 return get64BitSExtCompare(LHS, RHS, CC, RHSValue, dl);
3588 return get64BitZExtCompare(LHS, RHS, CC, RHSValue, dl);
3591 } // end anonymous namespace
3593 bool PPCDAGToDAGISel::tryIntCompareInGPR(SDNode *N) {
3594 if (N->getValueType(0) != MVT::i32 &&
3595 N->getValueType(0) != MVT::i64)
3598 // This optimization will emit code that assumes 64-bit registers
3599 // so we don't want to run it in 32-bit mode. Also don't run it
3600 // on functions that are not to be optimized.
3601 if (TM.getOptLevel() == CodeGenOpt::None || !TM.isPPC64())
3604 switch (N->getOpcode()) {
3606 case ISD::ZERO_EXTEND:
3607 case ISD::SIGN_EXTEND:
3611 IntegerCompareEliminator ICmpElim(CurDAG, this);
3612 if (SDNode *New = ICmpElim.Select(N)) {
3613 ReplaceNode(N, New);
3621 bool PPCDAGToDAGISel::tryBitPermutation(SDNode *N) {
3622 if (N->getValueType(0) != MVT::i32 &&
3623 N->getValueType(0) != MVT::i64)
3626 if (!UseBitPermRewriter)
3629 switch (N->getOpcode()) {
3636 BitPermutationSelector BPS(CurDAG);
3637 if (SDNode *New = BPS.Select(N)) {
3638 ReplaceNode(N, New);
3648 /// SelectCC - Select a comparison of the specified values with the specified
3649 /// condition code, returning the CR# of the expression.
3650 SDValue PPCDAGToDAGISel::SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC,
3652 // Always select the LHS.
3655 if (LHS.getValueType() == MVT::i32) {
3657 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
3658 if (isInt32Immediate(RHS, Imm)) {
3659 // SETEQ/SETNE comparison with 16-bit immediate, fold it.
3660 if (isUInt<16>(Imm))
3661 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, LHS,
3662 getI32Imm(Imm & 0xFFFF, dl)),
3664 // If this is a 16-bit signed immediate, fold it.
3665 if (isInt<16>((int)Imm))
3666 return SDValue(CurDAG->getMachineNode(PPC::CMPWI, dl, MVT::i32, LHS,
3667 getI32Imm(Imm & 0xFFFF, dl)),
3670 // For non-equality comparisons, the default code would materialize the
3671 // constant, then compare against it, like this:
3673 // ori r2, r2, 22136
3675 // Since we are just comparing for equality, we can emit this instead:
3676 // xoris r0,r3,0x1234
3677 // cmplwi cr0,r0,0x5678
3679 SDValue Xor(CurDAG->getMachineNode(PPC::XORIS, dl, MVT::i32, LHS,
3680 getI32Imm(Imm >> 16, dl)), 0);
3681 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, Xor,
3682 getI32Imm(Imm & 0xFFFF, dl)), 0);
3685 } else if (ISD::isUnsignedIntSetCC(CC)) {
3686 if (isInt32Immediate(RHS, Imm) && isUInt<16>(Imm))
3687 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, LHS,
3688 getI32Imm(Imm & 0xFFFF, dl)), 0);
3692 if (isIntS16Immediate(RHS, SImm))
3693 return SDValue(CurDAG->getMachineNode(PPC::CMPWI, dl, MVT::i32, LHS,
3694 getI32Imm((int)SImm & 0xFFFF,
3699 } else if (LHS.getValueType() == MVT::i64) {
3701 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
3702 if (isInt64Immediate(RHS.getNode(), Imm)) {
3703 // SETEQ/SETNE comparison with 16-bit immediate, fold it.
3704 if (isUInt<16>(Imm))
3705 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, LHS,
3706 getI32Imm(Imm & 0xFFFF, dl)),
3708 // If this is a 16-bit signed immediate, fold it.
3710 return SDValue(CurDAG->getMachineNode(PPC::CMPDI, dl, MVT::i64, LHS,
3711 getI32Imm(Imm & 0xFFFF, dl)),
3714 // For non-equality comparisons, the default code would materialize the
3715 // constant, then compare against it, like this:
3717 // ori r2, r2, 22136
3719 // Since we are just comparing for equality, we can emit this instead:
3720 // xoris r0,r3,0x1234
3721 // cmpldi cr0,r0,0x5678
3723 if (isUInt<32>(Imm)) {
3724 SDValue Xor(CurDAG->getMachineNode(PPC::XORIS8, dl, MVT::i64, LHS,
3725 getI64Imm(Imm >> 16, dl)), 0);
3726 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, Xor,
3727 getI64Imm(Imm & 0xFFFF, dl)),
3732 } else if (ISD::isUnsignedIntSetCC(CC)) {
3733 if (isInt64Immediate(RHS.getNode(), Imm) && isUInt<16>(Imm))
3734 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, LHS,
3735 getI64Imm(Imm & 0xFFFF, dl)), 0);
3739 if (isIntS16Immediate(RHS, SImm))
3740 return SDValue(CurDAG->getMachineNode(PPC::CMPDI, dl, MVT::i64, LHS,
3741 getI64Imm(SImm & 0xFFFF, dl)),
3745 } else if (LHS.getValueType() == MVT::f32) {
3746 if (PPCSubTarget->hasSPE()) {
3751 Opc = PPC::EFSCMPEQ;
3759 Opc = PPC::EFSCMPLT;
3767 Opc = PPC::EFSCMPGT;
3772 } else if (LHS.getValueType() == MVT::f64) {
3773 if (PPCSubTarget->hasSPE()) {
3778 Opc = PPC::EFDCMPEQ;
3786 Opc = PPC::EFDCMPLT;
3794 Opc = PPC::EFDCMPGT;
3798 Opc = PPCSubTarget->hasVSX() ? PPC::XSCMPUDP : PPC::FCMPUD;
3800 assert(LHS.getValueType() == MVT::f128 && "Unknown vt!");
3801 assert(PPCSubTarget->hasVSX() && "__float128 requires VSX");
3802 Opc = PPC::XSCMPUQP;
3804 return SDValue(CurDAG->getMachineNode(Opc, dl, MVT::i32, LHS, RHS), 0);
3807 static PPC::Predicate getPredicateForSetCC(ISD::CondCode CC) {
3813 llvm_unreachable("Should be lowered by legalize!");
3814 default: llvm_unreachable("Unknown condition!");
3816 case ISD::SETEQ: return PPC::PRED_EQ;
3818 case ISD::SETNE: return PPC::PRED_NE;
3820 case ISD::SETLT: return PPC::PRED_LT;
3822 case ISD::SETLE: return PPC::PRED_LE;
3824 case ISD::SETGT: return PPC::PRED_GT;
3826 case ISD::SETGE: return PPC::PRED_GE;
3827 case ISD::SETO: return PPC::PRED_NU;
3828 case ISD::SETUO: return PPC::PRED_UN;
3829 // These two are invalid for floating point. Assume we have int.
3830 case ISD::SETULT: return PPC::PRED_LT;
3831 case ISD::SETUGT: return PPC::PRED_GT;
3835 /// getCRIdxForSetCC - Return the index of the condition register field
3836 /// associated with the SetCC condition, and whether or not the field is
3837 /// treated as inverted. That is, lt = 0; ge = 0 inverted.
3838 static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool &Invert) {
3841 default: llvm_unreachable("Unknown condition!");
3843 case ISD::SETLT: return 0; // Bit #0 = SETOLT
3845 case ISD::SETGT: return 1; // Bit #1 = SETOGT
3847 case ISD::SETEQ: return 2; // Bit #2 = SETOEQ
3848 case ISD::SETUO: return 3; // Bit #3 = SETUO
3850 case ISD::SETGE: Invert = true; return 0; // !Bit #0 = SETUGE
3852 case ISD::SETLE: Invert = true; return 1; // !Bit #1 = SETULE
3854 case ISD::SETNE: Invert = true; return 2; // !Bit #2 = SETUNE
3855 case ISD::SETO: Invert = true; return 3; // !Bit #3 = SETO
3860 llvm_unreachable("Invalid branch code: should be expanded by legalize");
3861 // These are invalid for floating point. Assume integer.
3862 case ISD::SETULT: return 0;
3863 case ISD::SETUGT: return 1;
3867 // getVCmpInst: return the vector compare instruction for the specified
3868 // vector type and condition code. Since this is for altivec specific code,
3869 // only support the altivec types (v16i8, v8i16, v4i32, v2i64, and v4f32).
3870 static unsigned int getVCmpInst(MVT VecVT, ISD::CondCode CC,
3871 bool HasVSX, bool &Swap, bool &Negate) {
3875 if (VecVT.isFloatingPoint()) {
3876 /* Handle some cases by swapping input operands. */
3878 case ISD::SETLE: CC = ISD::SETGE; Swap = true; break;
3879 case ISD::SETLT: CC = ISD::SETGT; Swap = true; break;
3880 case ISD::SETOLE: CC = ISD::SETOGE; Swap = true; break;
3881 case ISD::SETOLT: CC = ISD::SETOGT; Swap = true; break;
3882 case ISD::SETUGE: CC = ISD::SETULE; Swap = true; break;
3883 case ISD::SETUGT: CC = ISD::SETULT; Swap = true; break;
3886 /* Handle some cases by negating the result. */
3888 case ISD::SETNE: CC = ISD::SETEQ; Negate = true; break;
3889 case ISD::SETUNE: CC = ISD::SETOEQ; Negate = true; break;
3890 case ISD::SETULE: CC = ISD::SETOGT; Negate = true; break;
3891 case ISD::SETULT: CC = ISD::SETOGE; Negate = true; break;
3894 /* We have instructions implementing the remaining cases. */
3898 if (VecVT == MVT::v4f32)
3899 return HasVSX ? PPC::XVCMPEQSP : PPC::VCMPEQFP;
3900 else if (VecVT == MVT::v2f64)
3901 return PPC::XVCMPEQDP;
3905 if (VecVT == MVT::v4f32)
3906 return HasVSX ? PPC::XVCMPGTSP : PPC::VCMPGTFP;
3907 else if (VecVT == MVT::v2f64)
3908 return PPC::XVCMPGTDP;
3912 if (VecVT == MVT::v4f32)
3913 return HasVSX ? PPC::XVCMPGESP : PPC::VCMPGEFP;
3914 else if (VecVT == MVT::v2f64)
3915 return PPC::XVCMPGEDP;
3920 llvm_unreachable("Invalid floating-point vector compare condition");
3922 /* Handle some cases by swapping input operands. */
3924 case ISD::SETGE: CC = ISD::SETLE; Swap = true; break;
3925 case ISD::SETLT: CC = ISD::SETGT; Swap = true; break;
3926 case ISD::SETUGE: CC = ISD::SETULE; Swap = true; break;
3927 case ISD::SETULT: CC = ISD::SETUGT; Swap = true; break;
3930 /* Handle some cases by negating the result. */
3932 case ISD::SETNE: CC = ISD::SETEQ; Negate = true; break;
3933 case ISD::SETUNE: CC = ISD::SETUEQ; Negate = true; break;
3934 case ISD::SETLE: CC = ISD::SETGT; Negate = true; break;
3935 case ISD::SETULE: CC = ISD::SETUGT; Negate = true; break;
3938 /* We have instructions implementing the remaining cases. */
3942 if (VecVT == MVT::v16i8)
3943 return PPC::VCMPEQUB;
3944 else if (VecVT == MVT::v8i16)
3945 return PPC::VCMPEQUH;
3946 else if (VecVT == MVT::v4i32)
3947 return PPC::VCMPEQUW;
3948 else if (VecVT == MVT::v2i64)
3949 return PPC::VCMPEQUD;
3952 if (VecVT == MVT::v16i8)
3953 return PPC::VCMPGTSB;
3954 else if (VecVT == MVT::v8i16)
3955 return PPC::VCMPGTSH;
3956 else if (VecVT == MVT::v4i32)
3957 return PPC::VCMPGTSW;
3958 else if (VecVT == MVT::v2i64)
3959 return PPC::VCMPGTSD;
3962 if (VecVT == MVT::v16i8)
3963 return PPC::VCMPGTUB;
3964 else if (VecVT == MVT::v8i16)
3965 return PPC::VCMPGTUH;
3966 else if (VecVT == MVT::v4i32)
3967 return PPC::VCMPGTUW;
3968 else if (VecVT == MVT::v2i64)
3969 return PPC::VCMPGTUD;
3974 llvm_unreachable("Invalid integer vector compare condition");
3978 bool PPCDAGToDAGISel::trySETCC(SDNode *N) {
3981 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
3983 CurDAG->getTargetLoweringInfo().getPointerTy(CurDAG->getDataLayout());
3984 bool isPPC64 = (PtrVT == MVT::i64);
3986 if (!PPCSubTarget->useCRBits() &&
3987 isInt32Immediate(N->getOperand(1), Imm)) {
3988 // We can codegen setcc op, imm very efficiently compared to a brcond.
3989 // Check for those cases here.
3992 SDValue Op = N->getOperand(0);
3996 Op = SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, Op), 0);
3997 SDValue Ops[] = { Op, getI32Imm(27, dl), getI32Imm(5, dl),
3998 getI32Imm(31, dl) };
3999 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
4005 SDValue(CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
4006 Op, getI32Imm(~0U, dl)), 0);
4007 CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op, AD.getValue(1));
4011 SDValue Ops[] = { Op, getI32Imm(1, dl), getI32Imm(31, dl),
4012 getI32Imm(31, dl) };
4013 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
4018 SDValue(CurDAG->getMachineNode(PPC::NEG, dl, MVT::i32, Op), 0);
4019 T = SDValue(CurDAG->getMachineNode(PPC::ANDC, dl, MVT::i32, T, Op), 0);
4020 SDValue Ops[] = { T, getI32Imm(1, dl), getI32Imm(31, dl),
4021 getI32Imm(31, dl) };
4022 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
4026 } else if (Imm == ~0U) { // setcc op, -1
4027 SDValue Op = N->getOperand(0);
4032 Op = SDValue(CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
4033 Op, getI32Imm(1, dl)), 0);
4034 CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
4035 SDValue(CurDAG->getMachineNode(PPC::LI, dl,
4038 0), Op.getValue(1));
4042 Op = SDValue(CurDAG->getMachineNode(PPC::NOR, dl, MVT::i32, Op, Op), 0);
4043 SDNode *AD = CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
4044 Op, getI32Imm(~0U, dl));
4045 CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDValue(AD, 0), Op,
4050 SDValue AD = SDValue(CurDAG->getMachineNode(PPC::ADDI, dl, MVT::i32, Op,
4051 getI32Imm(1, dl)), 0);
4052 SDValue AN = SDValue(CurDAG->getMachineNode(PPC::AND, dl, MVT::i32, AD,
4054 SDValue Ops[] = { AN, getI32Imm(1, dl), getI32Imm(31, dl),
4055 getI32Imm(31, dl) };
4056 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
4060 SDValue Ops[] = { Op, getI32Imm(1, dl), getI32Imm(31, dl),
4061 getI32Imm(31, dl) };
4062 Op = SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops), 0);
4063 CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op, getI32Imm(1, dl));
4070 SDValue LHS = N->getOperand(0);
4071 SDValue RHS = N->getOperand(1);
4073 // Altivec Vector compare instructions do not set any CR register by default and
4074 // vector compare operations return the same type as the operands.
4075 if (LHS.getValueType().isVector()) {
4076 if (PPCSubTarget->hasQPX() || PPCSubTarget->hasSPE())
4079 EVT VecVT = LHS.getValueType();
4081 unsigned int VCmpInst = getVCmpInst(VecVT.getSimpleVT(), CC,
4082 PPCSubTarget->hasVSX(), Swap, Negate);
4084 std::swap(LHS, RHS);
4086 EVT ResVT = VecVT.changeVectorElementTypeToInteger();
4088 SDValue VCmp(CurDAG->getMachineNode(VCmpInst, dl, ResVT, LHS, RHS), 0);
4089 CurDAG->SelectNodeTo(N, PPCSubTarget->hasVSX() ? PPC::XXLNOR : PPC::VNOR,
4094 CurDAG->SelectNodeTo(N, VCmpInst, ResVT, LHS, RHS);
4098 if (PPCSubTarget->useCRBits())
4102 unsigned Idx = getCRIdxForSetCC(CC, Inv);
4103 SDValue CCReg = SelectCC(LHS, RHS, CC, dl);
4106 // SPE e*cmp* instructions only set the 'gt' bit, so hard-code that
4107 // The correct compare instruction is already set by SelectCC()
4108 if (PPCSubTarget->hasSPE() && LHS.getValueType().isFloatingPoint()) {
4112 // Force the ccreg into CR7.
4113 SDValue CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32);
4115 SDValue InFlag(nullptr, 0); // Null incoming flag value.
4116 CCReg = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, CR7Reg, CCReg,
4117 InFlag).getValue(1);
4119 IntCR = SDValue(CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32, CR7Reg,
4122 SDValue Ops[] = { IntCR, getI32Imm((32 - (3 - Idx)) & 31, dl),
4123 getI32Imm(31, dl), getI32Imm(31, dl) };
4125 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
4129 // Get the specified bit.
4131 SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops), 0);
4132 CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1, dl));
4136 /// Does this node represent a load/store node whose address can be represented
4137 /// with a register plus an immediate that's a multiple of \p Val:
4138 bool PPCDAGToDAGISel::isOffsetMultipleOf(SDNode *N, unsigned Val) const {
4139 LoadSDNode *LDN = dyn_cast<LoadSDNode>(N);
4140 StoreSDNode *STN = dyn_cast<StoreSDNode>(N);
4143 AddrOp = LDN->getOperand(1);
4145 AddrOp = STN->getOperand(2);
4147 // If the address points a frame object or a frame object with an offset,
4148 // we need to check the object alignment.
4150 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(
4151 AddrOp.getOpcode() == ISD::ADD ? AddrOp.getOperand(0) :
4153 // If op0 is a frame index that is under aligned, we can't do it either,
4154 // because it is translated to r31 or r1 + slot + offset. We won't know the
4155 // slot number until the stack frame is finalized.
4156 const MachineFrameInfo &MFI = CurDAG->getMachineFunction().getFrameInfo();
4157 unsigned SlotAlign = MFI.getObjectAlignment(FI->getIndex());
4158 if ((SlotAlign % Val) != 0)
4161 // If we have an offset, we need further check on the offset.
4162 if (AddrOp.getOpcode() != ISD::ADD)
4166 if (AddrOp.getOpcode() == ISD::ADD)
4167 return isIntS16Immediate(AddrOp.getOperand(1), Imm) && !(Imm % Val);
4169 // If the address comes from the outside, the offset will be zero.
4170 return AddrOp.getOpcode() == ISD::CopyFromReg;
4173 void PPCDAGToDAGISel::transferMemOperands(SDNode *N, SDNode *Result) {
4174 // Transfer memoperands.
4175 MachineMemOperand *MemOp = cast<MemSDNode>(N)->getMemOperand();
4176 CurDAG->setNodeMemRefs(cast<MachineSDNode>(Result), {MemOp});
4179 static bool mayUseP9Setb(SDNode *N, const ISD::CondCode &CC, SelectionDAG *DAG,
4180 bool &NeedSwapOps, bool &IsUnCmp) {
4182 assert(N->getOpcode() == ISD::SELECT_CC && "Expecting a SELECT_CC here.");
4184 SDValue LHS = N->getOperand(0);
4185 SDValue RHS = N->getOperand(1);
4186 SDValue TrueRes = N->getOperand(2);
4187 SDValue FalseRes = N->getOperand(3);
4188 ConstantSDNode *TrueConst = dyn_cast<ConstantSDNode>(TrueRes);
4192 assert((N->getSimpleValueType(0) == MVT::i64 ||
4193 N->getSimpleValueType(0) == MVT::i32) &&
4194 "Expecting either i64 or i32 here.");
4196 // We are looking for any of:
4197 // (select_cc lhs, rhs, 1, (sext (setcc [lr]hs, [lr]hs, cc2)), cc1)
4198 // (select_cc lhs, rhs, -1, (zext (setcc [lr]hs, [lr]hs, cc2)), cc1)
4199 // (select_cc lhs, rhs, 0, (select_cc [lr]hs, [lr]hs, 1, -1, cc2), seteq)
4200 // (select_cc lhs, rhs, 0, (select_cc [lr]hs, [lr]hs, -1, 1, cc2), seteq)
4201 int64_t TrueResVal = TrueConst->getSExtValue();
4202 if ((TrueResVal < -1 || TrueResVal > 1) ||
4203 (TrueResVal == -1 && FalseRes.getOpcode() != ISD::ZERO_EXTEND) ||
4204 (TrueResVal == 1 && FalseRes.getOpcode() != ISD::SIGN_EXTEND) ||
4206 (FalseRes.getOpcode() != ISD::SELECT_CC || CC != ISD::SETEQ)))
4209 bool InnerIsSel = FalseRes.getOpcode() == ISD::SELECT_CC;
4210 SDValue SetOrSelCC = InnerIsSel ? FalseRes : FalseRes.getOperand(0);
4211 if (SetOrSelCC.getOpcode() != ISD::SETCC &&
4212 SetOrSelCC.getOpcode() != ISD::SELECT_CC)
4215 // Without this setb optimization, the outer SELECT_CC will be manually
4216 // selected to SELECT_CC_I4/SELECT_CC_I8 Pseudo, then expand-isel-pseudos pass
4217 // transforms pseduo instruction to isel instruction. When there are more than
4218 // one use for result like zext/sext, with current optimization we only see
4219 // isel is replaced by setb but can't see any significant gain. Since
4220 // setb has longer latency than original isel, we should avoid this. Another
4221 // point is that setb requires comparison always kept, it can break the
4222 // oppotunity to get the comparison away if we have in future.
4223 if (!SetOrSelCC.hasOneUse() || (!InnerIsSel && !FalseRes.hasOneUse()))
4226 SDValue InnerLHS = SetOrSelCC.getOperand(0);
4227 SDValue InnerRHS = SetOrSelCC.getOperand(1);
4228 ISD::CondCode InnerCC =
4229 cast<CondCodeSDNode>(SetOrSelCC.getOperand(InnerIsSel ? 4 : 2))->get();
4230 // If the inner comparison is a select_cc, make sure the true/false values are
4231 // 1/-1 and canonicalize it if needed.
4233 ConstantSDNode *SelCCTrueConst =
4234 dyn_cast<ConstantSDNode>(SetOrSelCC.getOperand(2));
4235 ConstantSDNode *SelCCFalseConst =
4236 dyn_cast<ConstantSDNode>(SetOrSelCC.getOperand(3));
4237 if (!SelCCTrueConst || !SelCCFalseConst)
4239 int64_t SelCCTVal = SelCCTrueConst->getSExtValue();
4240 int64_t SelCCFVal = SelCCFalseConst->getSExtValue();
4241 // The values must be -1/1 (requiring a swap) or 1/-1.
4242 if (SelCCTVal == -1 && SelCCFVal == 1) {
4243 std::swap(InnerLHS, InnerRHS);
4244 } else if (SelCCTVal != 1 || SelCCFVal != -1)
4248 // Canonicalize unsigned case
4249 if (InnerCC == ISD::SETULT || InnerCC == ISD::SETUGT) {
4251 InnerCC = (InnerCC == ISD::SETULT) ? ISD::SETLT : ISD::SETGT;
4254 bool InnerSwapped = false;
4255 if (LHS == InnerRHS && RHS == InnerLHS)
4256 InnerSwapped = true;
4257 else if (LHS != InnerLHS || RHS != InnerRHS)
4261 // (select_cc lhs, rhs, 0, \
4262 // (select_cc [lr]hs, [lr]hs, 1, -1, setlt/setgt), seteq)
4266 if (InnerCC != ISD::SETLT && InnerCC != ISD::SETGT)
4268 NeedSwapOps = (InnerCC == ISD::SETGT) ? InnerSwapped : !InnerSwapped;
4271 // (select_cc lhs, rhs, -1, (zext (setcc [lr]hs, [lr]hs, setne)), setu?lt)
4272 // (select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setgt)), setu?lt)
4273 // (select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setlt)), setu?lt)
4274 // (select_cc lhs, rhs, 1, (sext (setcc [lr]hs, [lr]hs, setne)), setu?lt)
4275 // (select_cc lhs, rhs, 1, (sext (setcc lhs, rhs, setgt)), setu?lt)
4276 // (select_cc lhs, rhs, 1, (sext (setcc rhs, lhs, setlt)), setu?lt)
4278 if (!IsUnCmp && InnerCC != ISD::SETNE)
4283 if (InnerCC == ISD::SETNE || (InnerCC == ISD::SETGT && !InnerSwapped) ||
4284 (InnerCC == ISD::SETLT && InnerSwapped))
4285 NeedSwapOps = (TrueResVal == 1);
4290 // (select_cc lhs, rhs, 1, (sext (setcc [lr]hs, [lr]hs, setne)), setu?gt)
4291 // (select_cc lhs, rhs, 1, (sext (setcc lhs, rhs, setlt)), setu?gt)
4292 // (select_cc lhs, rhs, 1, (sext (setcc rhs, lhs, setgt)), setu?gt)
4293 // (select_cc lhs, rhs, -1, (zext (setcc [lr]hs, [lr]hs, setne)), setu?gt)
4294 // (select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setlt)), setu?gt)
4295 // (select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setgt)), setu?gt)
4297 if (!IsUnCmp && InnerCC != ISD::SETNE)
4302 if (InnerCC == ISD::SETNE || (InnerCC == ISD::SETLT && !InnerSwapped) ||
4303 (InnerCC == ISD::SETGT && InnerSwapped))
4304 NeedSwapOps = (TrueResVal == -1);
4313 LLVM_DEBUG(dbgs() << "Found a node that can be lowered to a SETB: ");
4314 LLVM_DEBUG(N->dump());
4319 // Select - Convert the specified operand from a target-independent to a
4320 // target-specific node if it hasn't already been changed.
4321 void PPCDAGToDAGISel::Select(SDNode *N) {
4323 if (N->isMachineOpcode()) {
4325 return; // Already selected.
4328 // In case any misguided DAG-level optimizations form an ADD with a
4329 // TargetConstant operand, crash here instead of miscompiling (by selecting
4330 // an r+r add instead of some kind of r+i add).
4331 if (N->getOpcode() == ISD::ADD &&
4332 N->getOperand(1).getOpcode() == ISD::TargetConstant)
4333 llvm_unreachable("Invalid ADD with TargetConstant operand");
4335 // Try matching complex bit permutations before doing anything else.
4336 if (tryBitPermutation(N))
4339 // Try to emit integer compares as GPR-only sequences (i.e. no use of CR).
4340 if (tryIntCompareInGPR(N))
4343 switch (N->getOpcode()) {
4347 if (N->getValueType(0) == MVT::i64) {
4348 ReplaceNode(N, selectI64Imm(CurDAG, N));
4358 case PPCISD::CALL: {
4359 const Module *M = MF->getFunction().getParent();
4361 if (PPCLowering->getPointerTy(CurDAG->getDataLayout()) != MVT::i32 ||
4362 !PPCSubTarget->isSecurePlt() || !PPCSubTarget->isTargetELF() ||
4363 M->getPICLevel() == PICLevel::SmallPIC)
4366 SDValue Op = N->getOperand(1);
4368 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op)) {
4369 if (GA->getTargetFlags() == PPCII::MO_PLT)
4372 else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) {
4373 if (ES->getTargetFlags() == PPCII::MO_PLT)
4379 case PPCISD::GlobalBaseReg:
4380 ReplaceNode(N, getGlobalBaseReg());
4383 case ISD::FrameIndex:
4384 selectFrameIndex(N, N);
4387 case PPCISD::MFOCRF: {
4388 SDValue InFlag = N->getOperand(1);
4389 ReplaceNode(N, CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32,
4390 N->getOperand(0), InFlag));
4394 case PPCISD::READ_TIME_BASE:
4395 ReplaceNode(N, CurDAG->getMachineNode(PPC::ReadTB, dl, MVT::i32, MVT::i32,
4396 MVT::Other, N->getOperand(0)));
4399 case PPCISD::SRA_ADDZE: {
4400 SDValue N0 = N->getOperand(0);
4402 CurDAG->getTargetConstant(*cast<ConstantSDNode>(N->getOperand(1))->
4403 getConstantIntValue(), dl,
4404 N->getValueType(0));
4405 if (N->getValueType(0) == MVT::i64) {
4407 CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, MVT::Glue,
4409 CurDAG->SelectNodeTo(N, PPC::ADDZE8, MVT::i64, SDValue(Op, 0),
4413 assert(N->getValueType(0) == MVT::i32 &&
4414 "Expecting i64 or i32 in PPCISD::SRA_ADDZE");
4416 CurDAG->getMachineNode(PPC::SRAWI, dl, MVT::i32, MVT::Glue,
4418 CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32, SDValue(Op, 0),
4425 // Change TLS initial-exec D-form stores to X-form stores.
4426 StoreSDNode *ST = cast<StoreSDNode>(N);
4427 if (EnableTLSOpt && PPCSubTarget->isELFv2ABI() &&
4428 ST->getAddressingMode() != ISD::PRE_INC)
4429 if (tryTLSXFormStore(ST))
4434 // Handle preincrement loads.
4435 LoadSDNode *LD = cast<LoadSDNode>(N);
4436 EVT LoadedVT = LD->getMemoryVT();
4438 // Normal loads are handled by code generated from the .td file.
4439 if (LD->getAddressingMode() != ISD::PRE_INC) {
4440 // Change TLS initial-exec D-form loads to X-form loads.
4441 if (EnableTLSOpt && PPCSubTarget->isELFv2ABI())
4442 if (tryTLSXFormLoad(LD))
4447 SDValue Offset = LD->getOffset();
4448 if (Offset.getOpcode() == ISD::TargetConstant ||
4449 Offset.getOpcode() == ISD::TargetGlobalAddress) {
4452 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD;
4453 if (LD->getValueType(0) != MVT::i64) {
4454 // Handle PPC32 integer and normal FP loads.
4455 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
4456 switch (LoadedVT.getSimpleVT().SimpleTy) {
4457 default: llvm_unreachable("Invalid PPC load type!");
4458 case MVT::f64: Opcode = PPC::LFDU; break;
4459 case MVT::f32: Opcode = PPC::LFSU; break;
4460 case MVT::i32: Opcode = PPC::LWZU; break;
4461 case MVT::i16: Opcode = isSExt ? PPC::LHAU : PPC::LHZU; break;
4463 case MVT::i8: Opcode = PPC::LBZU; break;
4466 assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!");
4467 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
4468 switch (LoadedVT.getSimpleVT().SimpleTy) {
4469 default: llvm_unreachable("Invalid PPC load type!");
4470 case MVT::i64: Opcode = PPC::LDU; break;
4471 case MVT::i32: Opcode = PPC::LWZU8; break;
4472 case MVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; break;
4474 case MVT::i8: Opcode = PPC::LBZU8; break;
4478 SDValue Chain = LD->getChain();
4479 SDValue Base = LD->getBasePtr();
4480 SDValue Ops[] = { Offset, Base, Chain };
4481 SDNode *MN = CurDAG->getMachineNode(
4482 Opcode, dl, LD->getValueType(0),
4483 PPCLowering->getPointerTy(CurDAG->getDataLayout()), MVT::Other, Ops);
4484 transferMemOperands(N, MN);
4489 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD;
4490 if (LD->getValueType(0) != MVT::i64) {
4491 // Handle PPC32 integer and normal FP loads.
4492 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
4493 switch (LoadedVT.getSimpleVT().SimpleTy) {
4494 default: llvm_unreachable("Invalid PPC load type!");
4495 case MVT::v4f64: Opcode = PPC::QVLFDUX; break; // QPX
4496 case MVT::v4f32: Opcode = PPC::QVLFSUX; break; // QPX
4497 case MVT::f64: Opcode = PPC::LFDUX; break;
4498 case MVT::f32: Opcode = PPC::LFSUX; break;
4499 case MVT::i32: Opcode = PPC::LWZUX; break;
4500 case MVT::i16: Opcode = isSExt ? PPC::LHAUX : PPC::LHZUX; break;
4502 case MVT::i8: Opcode = PPC::LBZUX; break;
4505 assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!");
4506 assert((!isSExt || LoadedVT == MVT::i16 || LoadedVT == MVT::i32) &&
4507 "Invalid sext update load");
4508 switch (LoadedVT.getSimpleVT().SimpleTy) {
4509 default: llvm_unreachable("Invalid PPC load type!");
4510 case MVT::i64: Opcode = PPC::LDUX; break;
4511 case MVT::i32: Opcode = isSExt ? PPC::LWAUX : PPC::LWZUX8; break;
4512 case MVT::i16: Opcode = isSExt ? PPC::LHAUX8 : PPC::LHZUX8; break;
4514 case MVT::i8: Opcode = PPC::LBZUX8; break;
4518 SDValue Chain = LD->getChain();
4519 SDValue Base = LD->getBasePtr();
4520 SDValue Ops[] = { Base, Offset, Chain };
4521 SDNode *MN = CurDAG->getMachineNode(
4522 Opcode, dl, LD->getValueType(0),
4523 PPCLowering->getPointerTy(CurDAG->getDataLayout()), MVT::Other, Ops);
4524 transferMemOperands(N, MN);
4531 unsigned Imm, Imm2, SH, MB, ME;
4534 // If this is an and of a value rotated between 0 and 31 bits and then and'd
4535 // with a mask, emit rlwinm
4536 if (isInt32Immediate(N->getOperand(1), Imm) &&
4537 isRotateAndMask(N->getOperand(0).getNode(), Imm, false, SH, MB, ME)) {
4538 SDValue Val = N->getOperand(0).getOperand(0);
4539 SDValue Ops[] = { Val, getI32Imm(SH, dl), getI32Imm(MB, dl),
4540 getI32Imm(ME, dl) };
4541 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
4544 // If this is just a masked value where the input is not handled above, and
4545 // is not a rotate-left (handled by a pattern in the .td file), emit rlwinm
4546 if (isInt32Immediate(N->getOperand(1), Imm) &&
4547 isRunOfOnes(Imm, MB, ME) &&
4548 N->getOperand(0).getOpcode() != ISD::ROTL) {
4549 SDValue Val = N->getOperand(0);
4550 SDValue Ops[] = { Val, getI32Imm(0, dl), getI32Imm(MB, dl),
4551 getI32Imm(ME, dl) };
4552 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
4555 // If this is a 64-bit zero-extension mask, emit rldicl.
4556 if (isInt64Immediate(N->getOperand(1).getNode(), Imm64) &&
4558 SDValue Val = N->getOperand(0);
4559 MB = 64 - countTrailingOnes(Imm64);
4562 if (Val.getOpcode() == ISD::ANY_EXTEND) {
4563 auto Op0 = Val.getOperand(0);
4564 if ( Op0.getOpcode() == ISD::SRL &&
4565 isInt32Immediate(Op0.getOperand(1).getNode(), Imm) && Imm <= MB) {
4567 auto ResultType = Val.getNode()->getValueType(0);
4568 auto ImDef = CurDAG->getMachineNode(PPC::IMPLICIT_DEF, dl,
4570 SDValue IDVal (ImDef, 0);
4572 Val = SDValue(CurDAG->getMachineNode(PPC::INSERT_SUBREG, dl,
4573 ResultType, IDVal, Op0.getOperand(0),
4574 getI32Imm(1, dl)), 0);
4579 // If the operand is a logical right shift, we can fold it into this
4580 // instruction: rldicl(rldicl(x, 64-n, n), 0, mb) -> rldicl(x, 64-n, mb)
4581 // for n <= mb. The right shift is really a left rotate followed by a
4582 // mask, and this mask is a more-restrictive sub-mask of the mask implied
4584 if (Val.getOpcode() == ISD::SRL &&
4585 isInt32Immediate(Val.getOperand(1).getNode(), Imm) && Imm <= MB) {
4586 assert(Imm < 64 && "Illegal shift amount");
4587 Val = Val.getOperand(0);
4591 SDValue Ops[] = { Val, getI32Imm(SH, dl), getI32Imm(MB, dl) };
4592 CurDAG->SelectNodeTo(N, PPC::RLDICL, MVT::i64, Ops);
4595 // If this is a negated 64-bit zero-extension mask,
4596 // i.e. the immediate is a sequence of ones from most significant side
4597 // and all zero for reminder, we should use rldicr.
4598 if (isInt64Immediate(N->getOperand(1).getNode(), Imm64) &&
4599 isMask_64(~Imm64)) {
4600 SDValue Val = N->getOperand(0);
4601 MB = 63 - countTrailingOnes(~Imm64);
4603 SDValue Ops[] = { Val, getI32Imm(SH, dl), getI32Imm(MB, dl) };
4604 CurDAG->SelectNodeTo(N, PPC::RLDICR, MVT::i64, Ops);
4608 // AND X, 0 -> 0, not "rlwinm 32".
4609 if (isInt32Immediate(N->getOperand(1), Imm) && (Imm == 0)) {
4610 ReplaceUses(SDValue(N, 0), N->getOperand(1));
4613 // ISD::OR doesn't get all the bitfield insertion fun.
4614 // (and (or x, c1), c2) where isRunOfOnes(~(c1^c2)) might be a
4616 if (isInt32Immediate(N->getOperand(1), Imm) &&
4617 N->getOperand(0).getOpcode() == ISD::OR &&
4618 isInt32Immediate(N->getOperand(0).getOperand(1), Imm2)) {
4619 // The idea here is to check whether this is equivalent to:
4620 // (c1 & m) | (x & ~m)
4621 // where m is a run-of-ones mask. The logic here is that, for each bit in
4623 // - if both are 1, then the output will be 1.
4624 // - if both are 0, then the output will be 0.
4625 // - if the bit in c1 is 0, and the bit in c2 is 1, then the output will
4627 // - if the bit in c1 is 1, and the bit in c2 is 0, then the output will
4629 // If that last condition is never the case, then we can form m from the
4630 // bits that are the same between c1 and c2.
4632 if (isRunOfOnes(~(Imm^Imm2), MB, ME) && !(~Imm & Imm2)) {
4633 SDValue Ops[] = { N->getOperand(0).getOperand(0),
4634 N->getOperand(0).getOperand(1),
4635 getI32Imm(0, dl), getI32Imm(MB, dl),
4636 getI32Imm(ME, dl) };
4637 ReplaceNode(N, CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops));
4642 // Other cases are autogenerated.
4646 if (N->getValueType(0) == MVT::i32)
4647 if (tryBitfieldInsert(N))
4651 if (N->getOperand(0)->getOpcode() == ISD::FrameIndex &&
4652 isIntS16Immediate(N->getOperand(1), Imm)) {
4653 KnownBits LHSKnown = CurDAG->computeKnownBits(N->getOperand(0));
4655 // If this is equivalent to an add, then we can fold it with the
4656 // FrameIndex calculation.
4657 if ((LHSKnown.Zero.getZExtValue()|~(uint64_t)Imm) == ~0ULL) {
4658 selectFrameIndex(N, N->getOperand(0).getNode(), (int)Imm);
4663 // OR with a 32-bit immediate can be handled by ori + oris
4664 // without creating an immediate in a GPR.
4666 bool IsPPC64 = PPCSubTarget->isPPC64();
4667 if (IsPPC64 && isInt64Immediate(N->getOperand(1), Imm64) &&
4668 (Imm64 & ~0xFFFFFFFFuLL) == 0) {
4669 // If ImmHi (ImmHi) is zero, only one ori (oris) is generated later.
4670 uint64_t ImmHi = Imm64 >> 16;
4671 uint64_t ImmLo = Imm64 & 0xFFFF;
4672 if (ImmHi != 0 && ImmLo != 0) {
4673 SDNode *Lo = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64,
4675 getI16Imm(ImmLo, dl));
4676 SDValue Ops1[] = { SDValue(Lo, 0), getI16Imm(ImmHi, dl)};
4677 CurDAG->SelectNodeTo(N, PPC::ORIS8, MVT::i64, Ops1);
4682 // Other cases are autogenerated.
4686 // XOR with a 32-bit immediate can be handled by xori + xoris
4687 // without creating an immediate in a GPR.
4689 bool IsPPC64 = PPCSubTarget->isPPC64();
4690 if (IsPPC64 && isInt64Immediate(N->getOperand(1), Imm64) &&
4691 (Imm64 & ~0xFFFFFFFFuLL) == 0) {
4692 // If ImmHi (ImmHi) is zero, only one xori (xoris) is generated later.
4693 uint64_t ImmHi = Imm64 >> 16;
4694 uint64_t ImmLo = Imm64 & 0xFFFF;
4695 if (ImmHi != 0 && ImmLo != 0) {
4696 SDNode *Lo = CurDAG->getMachineNode(PPC::XORI8, dl, MVT::i64,
4698 getI16Imm(ImmLo, dl));
4699 SDValue Ops1[] = { SDValue(Lo, 0), getI16Imm(ImmHi, dl)};
4700 CurDAG->SelectNodeTo(N, PPC::XORIS8, MVT::i64, Ops1);
4709 if (N->getOperand(0)->getOpcode() == ISD::FrameIndex &&
4710 isIntS16Immediate(N->getOperand(1), Imm)) {
4711 selectFrameIndex(N, N->getOperand(0).getNode(), (int)Imm);
4718 unsigned Imm, SH, MB, ME;
4719 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) &&
4720 isRotateAndMask(N, Imm, true, SH, MB, ME)) {
4721 SDValue Ops[] = { N->getOperand(0).getOperand(0),
4722 getI32Imm(SH, dl), getI32Imm(MB, dl),
4723 getI32Imm(ME, dl) };
4724 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
4728 // Other cases are autogenerated.
4732 unsigned Imm, SH, MB, ME;
4733 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) &&
4734 isRotateAndMask(N, Imm, true, SH, MB, ME)) {
4735 SDValue Ops[] = { N->getOperand(0).getOperand(0),
4736 getI32Imm(SH, dl), getI32Imm(MB, dl),
4737 getI32Imm(ME, dl) };
4738 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
4742 // Other cases are autogenerated.
4745 // FIXME: Remove this once the ANDI glue bug is fixed:
4746 case PPCISD::ANDIo_1_EQ_BIT:
4747 case PPCISD::ANDIo_1_GT_BIT: {
4751 EVT InVT = N->getOperand(0).getValueType();
4752 assert((InVT == MVT::i64 || InVT == MVT::i32) &&
4753 "Invalid input type for ANDIo_1_EQ_BIT");
4755 unsigned Opcode = (InVT == MVT::i64) ? PPC::ANDIo8 : PPC::ANDIo;
4756 SDValue AndI(CurDAG->getMachineNode(Opcode, dl, InVT, MVT::Glue,
4758 CurDAG->getTargetConstant(1, dl, InVT)),
4760 SDValue CR0Reg = CurDAG->getRegister(PPC::CR0, MVT::i32);
4762 CurDAG->getTargetConstant(N->getOpcode() == PPCISD::ANDIo_1_EQ_BIT ?
4763 PPC::sub_eq : PPC::sub_gt, dl, MVT::i32);
4765 CurDAG->SelectNodeTo(N, TargetOpcode::EXTRACT_SUBREG, MVT::i1, CR0Reg,
4766 SRIdxVal, SDValue(AndI.getNode(), 1) /* glue */);
4769 case ISD::SELECT_CC: {
4770 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
4772 CurDAG->getTargetLoweringInfo().getPointerTy(CurDAG->getDataLayout());
4773 bool isPPC64 = (PtrVT == MVT::i64);
4775 // If this is a select of i1 operands, we'll pattern match it.
4776 if (PPCSubTarget->useCRBits() &&
4777 N->getOperand(0).getValueType() == MVT::i1)
4780 if (PPCSubTarget->isISA3_0() && PPCSubTarget->isPPC64()) {
4781 bool NeedSwapOps = false;
4782 bool IsUnCmp = false;
4783 if (mayUseP9Setb(N, CC, CurDAG, NeedSwapOps, IsUnCmp)) {
4784 SDValue LHS = N->getOperand(0);
4785 SDValue RHS = N->getOperand(1);
4787 std::swap(LHS, RHS);
4789 // Make use of SelectCC to generate the comparison to set CR bits, for
4790 // equality comparisons having one literal operand, SelectCC probably
4791 // doesn't need to materialize the whole literal and just use xoris to
4792 // check it first, it leads the following comparison result can't
4793 // exactly represent GT/LT relationship. So to avoid this we specify
4794 // SETGT/SETUGT here instead of SETEQ.
4796 SelectCC(LHS, RHS, IsUnCmp ? ISD::SETUGT : ISD::SETGT, dl);
4797 CurDAG->SelectNodeTo(
4798 N, N->getSimpleValueType(0) == MVT::i64 ? PPC::SETB8 : PPC::SETB,
4799 N->getValueType(0), GenCC);
4805 // Handle the setcc cases here. select_cc lhs, 0, 1, 0, cc
4807 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
4808 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N->getOperand(2)))
4809 if (ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N->getOperand(3)))
4810 if (N1C->isNullValue() && N3C->isNullValue() &&
4811 N2C->getZExtValue() == 1ULL && CC == ISD::SETNE &&
4812 // FIXME: Implement this optzn for PPC64.
4813 N->getValueType(0) == MVT::i32) {
4815 CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
4816 N->getOperand(0), getI32Imm(~0U, dl));
4817 CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDValue(Tmp, 0),
4818 N->getOperand(0), SDValue(Tmp, 1));
4822 SDValue CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC, dl);
4824 if (N->getValueType(0) == MVT::i1) {
4825 // An i1 select is: (c & t) | (!c & f).
4827 unsigned Idx = getCRIdxForSetCC(CC, Inv);
4831 default: llvm_unreachable("Invalid CC index");
4832 case 0: SRI = PPC::sub_lt; break;
4833 case 1: SRI = PPC::sub_gt; break;
4834 case 2: SRI = PPC::sub_eq; break;
4835 case 3: SRI = PPC::sub_un; break;
4838 SDValue CCBit = CurDAG->getTargetExtractSubreg(SRI, dl, MVT::i1, CCReg);
4840 SDValue NotCCBit(CurDAG->getMachineNode(PPC::CRNOR, dl, MVT::i1,
4842 SDValue C = Inv ? NotCCBit : CCBit,
4843 NotC = Inv ? CCBit : NotCCBit;
4845 SDValue CAndT(CurDAG->getMachineNode(PPC::CRAND, dl, MVT::i1,
4846 C, N->getOperand(2)), 0);
4847 SDValue NotCAndF(CurDAG->getMachineNode(PPC::CRAND, dl, MVT::i1,
4848 NotC, N->getOperand(3)), 0);
4850 CurDAG->SelectNodeTo(N, PPC::CROR, MVT::i1, CAndT, NotCAndF);
4854 unsigned BROpc = getPredicateForSetCC(CC);
4856 unsigned SelectCCOp;
4857 if (N->getValueType(0) == MVT::i32)
4858 SelectCCOp = PPC::SELECT_CC_I4;
4859 else if (N->getValueType(0) == MVT::i64)
4860 SelectCCOp = PPC::SELECT_CC_I8;
4861 else if (N->getValueType(0) == MVT::f32) {
4862 if (PPCSubTarget->hasP8Vector())
4863 SelectCCOp = PPC::SELECT_CC_VSSRC;
4864 else if (PPCSubTarget->hasSPE())
4865 SelectCCOp = PPC::SELECT_CC_SPE4;
4867 SelectCCOp = PPC::SELECT_CC_F4;
4868 } else if (N->getValueType(0) == MVT::f64) {
4869 if (PPCSubTarget->hasVSX())
4870 SelectCCOp = PPC::SELECT_CC_VSFRC;
4871 else if (PPCSubTarget->hasSPE())
4872 SelectCCOp = PPC::SELECT_CC_SPE;
4874 SelectCCOp = PPC::SELECT_CC_F8;
4875 } else if (N->getValueType(0) == MVT::f128)
4876 SelectCCOp = PPC::SELECT_CC_F16;
4877 else if (PPCSubTarget->hasSPE())
4878 SelectCCOp = PPC::SELECT_CC_SPE;
4879 else if (PPCSubTarget->hasQPX() && N->getValueType(0) == MVT::v4f64)
4880 SelectCCOp = PPC::SELECT_CC_QFRC;
4881 else if (PPCSubTarget->hasQPX() && N->getValueType(0) == MVT::v4f32)
4882 SelectCCOp = PPC::SELECT_CC_QSRC;
4883 else if (PPCSubTarget->hasQPX() && N->getValueType(0) == MVT::v4i1)
4884 SelectCCOp = PPC::SELECT_CC_QBRC;
4885 else if (N->getValueType(0) == MVT::v2f64 ||
4886 N->getValueType(0) == MVT::v2i64)
4887 SelectCCOp = PPC::SELECT_CC_VSRC;
4889 SelectCCOp = PPC::SELECT_CC_VRRC;
4891 SDValue Ops[] = { CCReg, N->getOperand(2), N->getOperand(3),
4892 getI32Imm(BROpc, dl) };
4893 CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), Ops);
4896 case ISD::VECTOR_SHUFFLE:
4897 if (PPCSubTarget->hasVSX() && (N->getValueType(0) == MVT::v2f64 ||
4898 N->getValueType(0) == MVT::v2i64)) {
4899 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
4901 SDValue Op1 = N->getOperand(SVN->getMaskElt(0) < 2 ? 0 : 1),
4902 Op2 = N->getOperand(SVN->getMaskElt(1) < 2 ? 0 : 1);
4905 for (int i = 0; i < 2; ++i)
4906 if (SVN->getMaskElt(i) <= 0 || SVN->getMaskElt(i) == 2)
4911 if (Op1 == Op2 && DM[0] == 0 && DM[1] == 0 &&
4912 Op1.getOpcode() == ISD::SCALAR_TO_VECTOR &&
4913 isa<LoadSDNode>(Op1.getOperand(0))) {
4914 LoadSDNode *LD = cast<LoadSDNode>(Op1.getOperand(0));
4915 SDValue Base, Offset;
4917 if (LD->isUnindexed() && LD->hasOneUse() && Op1.hasOneUse() &&
4918 (LD->getMemoryVT() == MVT::f64 ||
4919 LD->getMemoryVT() == MVT::i64) &&
4920 SelectAddrIdxOnly(LD->getBasePtr(), Base, Offset)) {
4921 SDValue Chain = LD->getChain();
4922 SDValue Ops[] = { Base, Offset, Chain };
4923 MachineMemOperand *MemOp = LD->getMemOperand();
4924 SDNode *NewN = CurDAG->SelectNodeTo(N, PPC::LXVDSX,
4925 N->getValueType(0), Ops);
4926 CurDAG->setNodeMemRefs(cast<MachineSDNode>(NewN), {MemOp});
4931 // For little endian, we must swap the input operands and adjust
4932 // the mask elements (reverse and invert them).
4933 if (PPCSubTarget->isLittleEndian()) {
4934 std::swap(Op1, Op2);
4935 unsigned tmp = DM[0];
4940 SDValue DMV = CurDAG->getTargetConstant(DM[1] | (DM[0] << 1), dl,
4942 SDValue Ops[] = { Op1, Op2, DMV };
4943 CurDAG->SelectNodeTo(N, PPC::XXPERMDI, N->getValueType(0), Ops);
4950 bool IsPPC64 = PPCSubTarget->isPPC64();
4951 SDValue Ops[] = { N->getOperand(1), N->getOperand(0) };
4952 CurDAG->SelectNodeTo(N, N->getOpcode() == PPCISD::BDNZ
4953 ? (IsPPC64 ? PPC::BDNZ8 : PPC::BDNZ)
4954 : (IsPPC64 ? PPC::BDZ8 : PPC::BDZ),
4958 case PPCISD::COND_BRANCH: {
4959 // Op #0 is the Chain.
4960 // Op #1 is the PPC::PRED_* number.
4962 // Op #3 is the Dest MBB
4963 // Op #4 is the Flag.
4964 // Prevent PPC::PRED_* from being selected into LI.
4965 unsigned PCC = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
4966 if (EnableBranchHint)
4967 PCC |= getBranchHint(PCC, FuncInfo, N->getOperand(3));
4969 SDValue Pred = getI32Imm(PCC, dl);
4970 SDValue Ops[] = { Pred, N->getOperand(2), N->getOperand(3),
4971 N->getOperand(0), N->getOperand(4) };
4972 CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops);
4976 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
4977 unsigned PCC = getPredicateForSetCC(CC);
4979 if (N->getOperand(2).getValueType() == MVT::i1) {
4983 default: llvm_unreachable("Unexpected Boolean-operand predicate");
4984 case PPC::PRED_LT: Opc = PPC::CRANDC; Swap = true; break;
4985 case PPC::PRED_LE: Opc = PPC::CRORC; Swap = true; break;
4986 case PPC::PRED_EQ: Opc = PPC::CREQV; Swap = false; break;
4987 case PPC::PRED_GE: Opc = PPC::CRORC; Swap = false; break;
4988 case PPC::PRED_GT: Opc = PPC::CRANDC; Swap = false; break;
4989 case PPC::PRED_NE: Opc = PPC::CRXOR; Swap = false; break;
4992 // A signed comparison of i1 values produces the opposite result to an
4993 // unsigned one if the condition code includes less-than or greater-than.
4994 // This is because 1 is the most negative signed i1 number and the most
4995 // positive unsigned i1 number. The CR-logical operations used for such
4996 // comparisons are non-commutative so for signed comparisons vs. unsigned
4997 // ones, the input operands just need to be swapped.
4998 if (ISD::isSignedIntSetCC(CC))
5001 SDValue BitComp(CurDAG->getMachineNode(Opc, dl, MVT::i1,
5002 N->getOperand(Swap ? 3 : 2),
5003 N->getOperand(Swap ? 2 : 3)), 0);
5004 CurDAG->SelectNodeTo(N, PPC::BC, MVT::Other, BitComp, N->getOperand(4),
5009 if (EnableBranchHint)
5010 PCC |= getBranchHint(PCC, FuncInfo, N->getOperand(4));
5012 SDValue CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC, dl);
5013 SDValue Ops[] = { getI32Imm(PCC, dl), CondCode,
5014 N->getOperand(4), N->getOperand(0) };
5015 CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops);
5019 // FIXME: Should custom lower this.
5020 SDValue Chain = N->getOperand(0);
5021 SDValue Target = N->getOperand(1);
5022 unsigned Opc = Target.getValueType() == MVT::i32 ? PPC::MTCTR : PPC::MTCTR8;
5023 unsigned Reg = Target.getValueType() == MVT::i32 ? PPC::BCTR : PPC::BCTR8;
5024 Chain = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Glue, Target,
5026 CurDAG->SelectNodeTo(N, Reg, MVT::Other, Chain);
5029 case PPCISD::TOC_ENTRY: {
5030 assert ((PPCSubTarget->isPPC64() || PPCSubTarget->isSVR4ABI()) &&
5031 "Only supported for 64-bit ABI and 32-bit SVR4");
5032 if (PPCSubTarget->isSVR4ABI() && !PPCSubTarget->isPPC64()) {
5033 SDValue GA = N->getOperand(0);
5034 SDNode *MN = CurDAG->getMachineNode(PPC::LWZtoc, dl, MVT::i32, GA,
5036 transferMemOperands(N, MN);
5041 // For medium and large code model, we generate two instructions as
5042 // described below. Otherwise we allow SelectCodeCommon to handle this,
5043 // selecting one of LDtoc, LDtocJTI, LDtocCPT, and LDtocBA.
5044 CodeModel::Model CModel = TM.getCodeModel();
5045 if (CModel != CodeModel::Medium && CModel != CodeModel::Large)
5048 // The first source operand is a TargetGlobalAddress or a TargetJumpTable.
5049 // If it must be toc-referenced according to PPCSubTarget, we generate:
5050 // LDtocL(@sym, ADDIStocHA(%x2, @sym))
5051 // Otherwise we generate:
5052 // ADDItocL(ADDIStocHA(%x2, @sym), @sym)
5053 SDValue GA = N->getOperand(0);
5054 SDValue TOCbase = N->getOperand(1);
5055 SDNode *Tmp = CurDAG->getMachineNode(PPC::ADDIStocHA, dl, MVT::i64,
5057 if (PPCLowering->isAccessedAsGotIndirect(GA)) {
5058 // If it is access as got-indirect, we need an extra LD to load
5060 SDNode *MN = CurDAG->getMachineNode(PPC::LDtocL, dl, MVT::i64, GA,
5062 transferMemOperands(N, MN);
5067 // Build the address relative to the TOC-pointer..
5068 ReplaceNode(N, CurDAG->getMachineNode(PPC::ADDItocL, dl, MVT::i64,
5069 SDValue(Tmp, 0), GA));
5072 case PPCISD::PPC32_PICGOT:
5073 // Generate a PIC-safe GOT reference.
5074 assert(!PPCSubTarget->isPPC64() && PPCSubTarget->isSVR4ABI() &&
5075 "PPCISD::PPC32_PICGOT is only supported for 32-bit SVR4");
5076 CurDAG->SelectNodeTo(N, PPC::PPC32PICGOT,
5077 PPCLowering->getPointerTy(CurDAG->getDataLayout()),
5081 case PPCISD::VADD_SPLAT: {
5082 // This expands into one of three sequences, depending on whether
5083 // the first operand is odd or even, positive or negative.
5084 assert(isa<ConstantSDNode>(N->getOperand(0)) &&
5085 isa<ConstantSDNode>(N->getOperand(1)) &&
5086 "Invalid operand on VADD_SPLAT!");
5088 int Elt = N->getConstantOperandVal(0);
5089 int EltSize = N->getConstantOperandVal(1);
5090 unsigned Opc1, Opc2, Opc3;
5094 Opc1 = PPC::VSPLTISB;
5095 Opc2 = PPC::VADDUBM;
5096 Opc3 = PPC::VSUBUBM;
5098 } else if (EltSize == 2) {
5099 Opc1 = PPC::VSPLTISH;
5100 Opc2 = PPC::VADDUHM;
5101 Opc3 = PPC::VSUBUHM;
5104 assert(EltSize == 4 && "Invalid element size on VADD_SPLAT!");
5105 Opc1 = PPC::VSPLTISW;
5106 Opc2 = PPC::VADDUWM;
5107 Opc3 = PPC::VSUBUWM;
5111 if ((Elt & 1) == 0) {
5112 // Elt is even, in the range [-32,-18] + [16,30].
5114 // Convert: VADD_SPLAT elt, size
5115 // Into: tmp = VSPLTIS[BHW] elt
5116 // VADDU[BHW]M tmp, tmp
5117 // Where: [BHW] = B for size = 1, H for size = 2, W for size = 4
5118 SDValue EltVal = getI32Imm(Elt >> 1, dl);
5119 SDNode *Tmp = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
5120 SDValue TmpVal = SDValue(Tmp, 0);
5121 ReplaceNode(N, CurDAG->getMachineNode(Opc2, dl, VT, TmpVal, TmpVal));
5123 } else if (Elt > 0) {
5124 // Elt is odd and positive, in the range [17,31].
5126 // Convert: VADD_SPLAT elt, size
5127 // Into: tmp1 = VSPLTIS[BHW] elt-16
5128 // tmp2 = VSPLTIS[BHW] -16
5129 // VSUBU[BHW]M tmp1, tmp2
5130 SDValue EltVal = getI32Imm(Elt - 16, dl);
5131 SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
5132 EltVal = getI32Imm(-16, dl);
5133 SDNode *Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
5134 ReplaceNode(N, CurDAG->getMachineNode(Opc3, dl, VT, SDValue(Tmp1, 0),
5138 // Elt is odd and negative, in the range [-31,-17].
5140 // Convert: VADD_SPLAT elt, size
5141 // Into: tmp1 = VSPLTIS[BHW] elt+16
5142 // tmp2 = VSPLTIS[BHW] -16
5143 // VADDU[BHW]M tmp1, tmp2
5144 SDValue EltVal = getI32Imm(Elt + 16, dl);
5145 SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
5146 EltVal = getI32Imm(-16, dl);
5147 SDNode *Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
5148 ReplaceNode(N, CurDAG->getMachineNode(Opc2, dl, VT, SDValue(Tmp1, 0),
5158 // If the target supports the cmpb instruction, do the idiom recognition here.
5159 // We don't do this as a DAG combine because we don't want to do it as nodes
5160 // are being combined (because we might miss part of the eventual idiom). We
5161 // don't want to do it during instruction selection because we want to reuse
5162 // the logic for lowering the masking operations already part of the
5163 // instruction selector.
5164 SDValue PPCDAGToDAGISel::combineToCMPB(SDNode *N) {
5167 assert(N->getOpcode() == ISD::OR &&
5168 "Only OR nodes are supported for CMPB");
5171 if (!PPCSubTarget->hasCMPB())
5174 if (N->getValueType(0) != MVT::i32 &&
5175 N->getValueType(0) != MVT::i64)
5178 EVT VT = N->getValueType(0);
5181 bool BytesFound[8] = {false, false, false, false, false, false, false, false};
5182 uint64_t Mask = 0, Alt = 0;
5184 auto IsByteSelectCC = [this](SDValue O, unsigned &b,
5185 uint64_t &Mask, uint64_t &Alt,
5186 SDValue &LHS, SDValue &RHS) {
5187 if (O.getOpcode() != ISD::SELECT_CC)
5189 ISD::CondCode CC = cast<CondCodeSDNode>(O.getOperand(4))->get();
5191 if (!isa<ConstantSDNode>(O.getOperand(2)) ||
5192 !isa<ConstantSDNode>(O.getOperand(3)))
5195 uint64_t PM = O.getConstantOperandVal(2);
5196 uint64_t PAlt = O.getConstantOperandVal(3);
5197 for (b = 0; b < 8; ++b) {
5198 uint64_t Mask = UINT64_C(0xFF) << (8*b);
5199 if (PM && (PM & Mask) == PM && (PAlt & Mask) == PAlt)
5208 if (!isa<ConstantSDNode>(O.getOperand(1)) ||
5209 O.getConstantOperandVal(1) != 0) {
5210 SDValue Op0 = O.getOperand(0), Op1 = O.getOperand(1);
5211 if (Op0.getOpcode() == ISD::TRUNCATE)
5212 Op0 = Op0.getOperand(0);
5213 if (Op1.getOpcode() == ISD::TRUNCATE)
5214 Op1 = Op1.getOperand(0);
5216 if (Op0.getOpcode() == ISD::SRL && Op1.getOpcode() == ISD::SRL &&
5217 Op0.getOperand(1) == Op1.getOperand(1) && CC == ISD::SETEQ &&
5218 isa<ConstantSDNode>(Op0.getOperand(1))) {
5220 unsigned Bits = Op0.getValueSizeInBits();
5223 if (Op0.getConstantOperandVal(1) != Bits-8)
5226 LHS = Op0.getOperand(0);
5227 RHS = Op1.getOperand(0);
5231 // When we have small integers (i16 to be specific), the form present
5232 // post-legalization uses SETULT in the SELECT_CC for the
5233 // higher-order byte, depending on the fact that the
5234 // even-higher-order bytes are known to all be zero, for example:
5235 // select_cc (xor $lhs, $rhs), 256, 65280, 0, setult
5236 // (so when the second byte is the same, because all higher-order
5237 // bits from bytes 3 and 4 are known to be zero, the result of the
5238 // xor can be at most 255)
5239 if (Op0.getOpcode() == ISD::XOR && CC == ISD::SETULT &&
5240 isa<ConstantSDNode>(O.getOperand(1))) {
5242 uint64_t ULim = O.getConstantOperandVal(1);
5243 if (ULim != (UINT64_C(1) << b*8))
5246 // Now we need to make sure that the upper bytes are known to be
5248 unsigned Bits = Op0.getValueSizeInBits();
5249 if (!CurDAG->MaskedValueIsZero(
5250 Op0, APInt::getHighBitsSet(Bits, Bits - (b + 1) * 8)))
5253 LHS = Op0.getOperand(0);
5254 RHS = Op0.getOperand(1);
5261 if (CC != ISD::SETEQ)
5264 SDValue Op = O.getOperand(0);
5265 if (Op.getOpcode() == ISD::AND) {
5266 if (!isa<ConstantSDNode>(Op.getOperand(1)))
5268 if (Op.getConstantOperandVal(1) != (UINT64_C(0xFF) << (8*b)))
5271 SDValue XOR = Op.getOperand(0);
5272 if (XOR.getOpcode() == ISD::TRUNCATE)
5273 XOR = XOR.getOperand(0);
5274 if (XOR.getOpcode() != ISD::XOR)
5277 LHS = XOR.getOperand(0);
5278 RHS = XOR.getOperand(1);
5280 } else if (Op.getOpcode() == ISD::SRL) {
5281 if (!isa<ConstantSDNode>(Op.getOperand(1)))
5283 unsigned Bits = Op.getValueSizeInBits();
5286 if (Op.getConstantOperandVal(1) != Bits-8)
5289 SDValue XOR = Op.getOperand(0);
5290 if (XOR.getOpcode() == ISD::TRUNCATE)
5291 XOR = XOR.getOperand(0);
5292 if (XOR.getOpcode() != ISD::XOR)
5295 LHS = XOR.getOperand(0);
5296 RHS = XOR.getOperand(1);
5303 SmallVector<SDValue, 8> Queue(1, SDValue(N, 0));
5304 while (!Queue.empty()) {
5305 SDValue V = Queue.pop_back_val();
5307 for (const SDValue &O : V.getNode()->ops()) {
5309 uint64_t M = 0, A = 0;
5311 if (O.getOpcode() == ISD::OR) {
5313 } else if (IsByteSelectCC(O, b, M, A, OLHS, ORHS)) {
5317 BytesFound[b] = true;
5320 } else if ((LHS == ORHS && RHS == OLHS) ||
5321 (RHS == ORHS && LHS == OLHS)) {
5322 BytesFound[b] = true;
5334 unsigned LastB = 0, BCnt = 0;
5335 for (unsigned i = 0; i < 8; ++i)
5336 if (BytesFound[LastB]) {
5341 if (!LastB || BCnt < 2)
5344 // Because we'll be zero-extending the output anyway if don't have a specific
5345 // value for each input byte (via the Mask), we can 'anyext' the inputs.
5346 if (LHS.getValueType() != VT) {
5347 LHS = CurDAG->getAnyExtOrTrunc(LHS, dl, VT);
5348 RHS = CurDAG->getAnyExtOrTrunc(RHS, dl, VT);
5351 Res = CurDAG->getNode(PPCISD::CMPB, dl, VT, LHS, RHS);
5353 bool NonTrivialMask = ((int64_t) Mask) != INT64_C(-1);
5354 if (NonTrivialMask && !Alt) {
5355 // Res = Mask & CMPB
5356 Res = CurDAG->getNode(ISD::AND, dl, VT, Res,
5357 CurDAG->getConstant(Mask, dl, VT));
5359 // Res = (CMPB & Mask) | (~CMPB & Alt)
5360 // Which, as suggested here:
5361 // https://graphics.stanford.edu/~seander/bithacks.html#MaskedMerge
5362 // can be written as:
5363 // Res = Alt ^ ((Alt ^ Mask) & CMPB)
5364 // useful because the (Alt ^ Mask) can be pre-computed.
5365 Res = CurDAG->getNode(ISD::AND, dl, VT, Res,
5366 CurDAG->getConstant(Mask ^ Alt, dl, VT));
5367 Res = CurDAG->getNode(ISD::XOR, dl, VT, Res,
5368 CurDAG->getConstant(Alt, dl, VT));
5374 // When CR bit registers are enabled, an extension of an i1 variable to a i32
5375 // or i64 value is lowered in terms of a SELECT_I[48] operation, and thus
5376 // involves constant materialization of a 0 or a 1 or both. If the result of
5377 // the extension is then operated upon by some operator that can be constant
5378 // folded with a constant 0 or 1, and that constant can be materialized using
5379 // only one instruction (like a zero or one), then we should fold in those
5380 // operations with the select.
5381 void PPCDAGToDAGISel::foldBoolExts(SDValue &Res, SDNode *&N) {
5382 if (!PPCSubTarget->useCRBits())
5385 if (N->getOpcode() != ISD::ZERO_EXTEND &&
5386 N->getOpcode() != ISD::SIGN_EXTEND &&
5387 N->getOpcode() != ISD::ANY_EXTEND)
5390 if (N->getOperand(0).getValueType() != MVT::i1)
5393 if (!N->hasOneUse())
5397 EVT VT = N->getValueType(0);
5398 SDValue Cond = N->getOperand(0);
5400 CurDAG->getConstant(N->getOpcode() == ISD::SIGN_EXTEND ? -1 : 1, dl, VT);
5401 SDValue ConstFalse = CurDAG->getConstant(0, dl, VT);
5404 SDNode *User = *N->use_begin();
5405 if (User->getNumOperands() != 2)
5408 auto TryFold = [this, N, User, dl](SDValue Val) {
5409 SDValue UserO0 = User->getOperand(0), UserO1 = User->getOperand(1);
5410 SDValue O0 = UserO0.getNode() == N ? Val : UserO0;
5411 SDValue O1 = UserO1.getNode() == N ? Val : UserO1;
5413 return CurDAG->FoldConstantArithmetic(User->getOpcode(), dl,
5414 User->getValueType(0),
5415 O0.getNode(), O1.getNode());
5418 // FIXME: When the semantics of the interaction between select and undef
5419 // are clearly defined, it may turn out to be unnecessary to break here.
5420 SDValue TrueRes = TryFold(ConstTrue);
5421 if (!TrueRes || TrueRes.isUndef())
5423 SDValue FalseRes = TryFold(ConstFalse);
5424 if (!FalseRes || FalseRes.isUndef())
5427 // For us to materialize these using one instruction, we must be able to
5428 // represent them as signed 16-bit integers.
5429 uint64_t True = cast<ConstantSDNode>(TrueRes)->getZExtValue(),
5430 False = cast<ConstantSDNode>(FalseRes)->getZExtValue();
5431 if (!isInt<16>(True) || !isInt<16>(False))
5434 // We can replace User with a new SELECT node, and try again to see if we
5435 // can fold the select with its user.
5436 Res = CurDAG->getSelect(dl, User->getValueType(0), Cond, TrueRes, FalseRes);
5438 ConstTrue = TrueRes;
5439 ConstFalse = FalseRes;
5440 } while (N->hasOneUse());
5443 void PPCDAGToDAGISel::PreprocessISelDAG() {
5444 SelectionDAG::allnodes_iterator Position = CurDAG->allnodes_end();
5446 bool MadeChange = false;
5447 while (Position != CurDAG->allnodes_begin()) {
5448 SDNode *N = &*--Position;
5453 switch (N->getOpcode()) {
5456 Res = combineToCMPB(N);
5461 foldBoolExts(Res, N);
5464 LLVM_DEBUG(dbgs() << "PPC DAG preprocessing replacing:\nOld: ");
5465 LLVM_DEBUG(N->dump(CurDAG));
5466 LLVM_DEBUG(dbgs() << "\nNew: ");
5467 LLVM_DEBUG(Res.getNode()->dump(CurDAG));
5468 LLVM_DEBUG(dbgs() << "\n");
5470 CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), Res);
5476 CurDAG->RemoveDeadNodes();
5479 /// PostprocessISelDAG - Perform some late peephole optimizations
5480 /// on the DAG representation.
5481 void PPCDAGToDAGISel::PostprocessISelDAG() {
5482 // Skip peepholes at -O0.
5483 if (TM.getOptLevel() == CodeGenOpt::None)
5488 PeepholePPC64ZExt();
5491 // Check if all users of this node will become isel where the second operand
5492 // is the constant zero. If this is so, and if we can negate the condition,
5493 // then we can flip the true and false operands. This will allow the zero to
5494 // be folded with the isel so that we don't need to materialize a register
5496 bool PPCDAGToDAGISel::AllUsersSelectZero(SDNode *N) {
5497 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
5500 if (!User->isMachineOpcode())
5502 if (User->getMachineOpcode() != PPC::SELECT_I4 &&
5503 User->getMachineOpcode() != PPC::SELECT_I8)
5506 SDNode *Op2 = User->getOperand(2).getNode();
5507 if (!Op2->isMachineOpcode())
5510 if (Op2->getMachineOpcode() != PPC::LI &&
5511 Op2->getMachineOpcode() != PPC::LI8)
5514 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op2->getOperand(0));
5518 if (!C->isNullValue())
5525 void PPCDAGToDAGISel::SwapAllSelectUsers(SDNode *N) {
5526 SmallVector<SDNode *, 4> ToReplace;
5527 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
5530 assert((User->getMachineOpcode() == PPC::SELECT_I4 ||
5531 User->getMachineOpcode() == PPC::SELECT_I8) &&
5532 "Must have all select users");
5533 ToReplace.push_back(User);
5536 for (SmallVector<SDNode *, 4>::iterator UI = ToReplace.begin(),
5537 UE = ToReplace.end(); UI != UE; ++UI) {
5540 CurDAG->getMachineNode(User->getMachineOpcode(), SDLoc(User),
5541 User->getValueType(0), User->getOperand(0),
5542 User->getOperand(2),
5543 User->getOperand(1));
5545 LLVM_DEBUG(dbgs() << "CR Peephole replacing:\nOld: ");
5546 LLVM_DEBUG(User->dump(CurDAG));
5547 LLVM_DEBUG(dbgs() << "\nNew: ");
5548 LLVM_DEBUG(ResNode->dump(CurDAG));
5549 LLVM_DEBUG(dbgs() << "\n");
5551 ReplaceUses(User, ResNode);
5555 void PPCDAGToDAGISel::PeepholeCROps() {
5559 for (SDNode &Node : CurDAG->allnodes()) {
5560 MachineSDNode *MachineNode = dyn_cast<MachineSDNode>(&Node);
5561 if (!MachineNode || MachineNode->use_empty())
5563 SDNode *ResNode = MachineNode;
5565 bool Op1Set = false, Op1Unset = false,
5567 Op2Set = false, Op2Unset = false,
5570 unsigned Opcode = MachineNode->getMachineOpcode();
5581 SDValue Op = MachineNode->getOperand(1);
5582 if (Op.isMachineOpcode()) {
5583 if (Op.getMachineOpcode() == PPC::CRSET)
5585 else if (Op.getMachineOpcode() == PPC::CRUNSET)
5587 else if (Op.getMachineOpcode() == PPC::CRNOR &&
5588 Op.getOperand(0) == Op.getOperand(1))
5595 case PPC::SELECT_I4:
5596 case PPC::SELECT_I8:
5597 case PPC::SELECT_F4:
5598 case PPC::SELECT_F8:
5599 case PPC::SELECT_QFRC:
5600 case PPC::SELECT_QSRC:
5601 case PPC::SELECT_QBRC:
5602 case PPC::SELECT_SPE:
5603 case PPC::SELECT_SPE4:
5604 case PPC::SELECT_VRRC:
5605 case PPC::SELECT_VSFRC:
5606 case PPC::SELECT_VSSRC:
5607 case PPC::SELECT_VSRC: {
5608 SDValue Op = MachineNode->getOperand(0);
5609 if (Op.isMachineOpcode()) {
5610 if (Op.getMachineOpcode() == PPC::CRSET)
5612 else if (Op.getMachineOpcode() == PPC::CRUNSET)
5614 else if (Op.getMachineOpcode() == PPC::CRNOR &&
5615 Op.getOperand(0) == Op.getOperand(1))
5622 bool SelectSwap = false;
5626 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
5628 ResNode = MachineNode->getOperand(0).getNode();
5631 ResNode = MachineNode->getOperand(1).getNode();
5634 ResNode = MachineNode->getOperand(0).getNode();
5635 else if (Op1Unset || Op2Unset)
5636 // x & 0 = 0 & y = 0
5637 ResNode = CurDAG->getMachineNode(PPC::CRUNSET, SDLoc(MachineNode),
5640 // ~x & y = andc(y, x)
5641 ResNode = CurDAG->getMachineNode(PPC::CRANDC, SDLoc(MachineNode),
5642 MVT::i1, MachineNode->getOperand(1),
5643 MachineNode->getOperand(0).
5646 // x & ~y = andc(x, y)
5647 ResNode = CurDAG->getMachineNode(PPC::CRANDC, SDLoc(MachineNode),
5648 MVT::i1, MachineNode->getOperand(0),
5649 MachineNode->getOperand(1).
5651 else if (AllUsersSelectZero(MachineNode)) {
5652 ResNode = CurDAG->getMachineNode(PPC::CRNAND, SDLoc(MachineNode),
5653 MVT::i1, MachineNode->getOperand(0),
5654 MachineNode->getOperand(1));
5659 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
5660 // nand(x, x) -> nor(x, x)
5661 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
5662 MVT::i1, MachineNode->getOperand(0),
5663 MachineNode->getOperand(0));
5665 // nand(1, y) -> nor(y, y)
5666 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
5667 MVT::i1, MachineNode->getOperand(1),
5668 MachineNode->getOperand(1));
5670 // nand(x, 1) -> nor(x, x)
5671 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
5672 MVT::i1, MachineNode->getOperand(0),
5673 MachineNode->getOperand(0));
5674 else if (Op1Unset || Op2Unset)
5675 // nand(x, 0) = nand(0, y) = 1
5676 ResNode = CurDAG->getMachineNode(PPC::CRSET, SDLoc(MachineNode),
5679 // nand(~x, y) = ~(~x & y) = x | ~y = orc(x, y)
5680 ResNode = CurDAG->getMachineNode(PPC::CRORC, SDLoc(MachineNode),
5681 MVT::i1, MachineNode->getOperand(0).
5683 MachineNode->getOperand(1));
5685 // nand(x, ~y) = ~x | y = orc(y, x)
5686 ResNode = CurDAG->getMachineNode(PPC::CRORC, SDLoc(MachineNode),
5687 MVT::i1, MachineNode->getOperand(1).
5689 MachineNode->getOperand(0));
5690 else if (AllUsersSelectZero(MachineNode)) {
5691 ResNode = CurDAG->getMachineNode(PPC::CRAND, SDLoc(MachineNode),
5692 MVT::i1, MachineNode->getOperand(0),
5693 MachineNode->getOperand(1));
5698 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
5700 ResNode = MachineNode->getOperand(0).getNode();
5701 else if (Op1Set || Op2Set)
5702 // x | 1 = 1 | y = 1
5703 ResNode = CurDAG->getMachineNode(PPC::CRSET, SDLoc(MachineNode),
5707 ResNode = MachineNode->getOperand(1).getNode();
5710 ResNode = MachineNode->getOperand(0).getNode();
5712 // ~x | y = orc(y, x)
5713 ResNode = CurDAG->getMachineNode(PPC::CRORC, SDLoc(MachineNode),
5714 MVT::i1, MachineNode->getOperand(1),
5715 MachineNode->getOperand(0).
5718 // x | ~y = orc(x, y)
5719 ResNode = CurDAG->getMachineNode(PPC::CRORC, SDLoc(MachineNode),
5720 MVT::i1, MachineNode->getOperand(0),
5721 MachineNode->getOperand(1).
5723 else if (AllUsersSelectZero(MachineNode)) {
5724 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
5725 MVT::i1, MachineNode->getOperand(0),
5726 MachineNode->getOperand(1));
5731 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
5733 ResNode = CurDAG->getMachineNode(PPC::CRUNSET, SDLoc(MachineNode),
5736 // xor(1, y) -> nor(y, y)
5737 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
5738 MVT::i1, MachineNode->getOperand(1),
5739 MachineNode->getOperand(1));
5741 // xor(x, 1) -> nor(x, x)
5742 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
5743 MVT::i1, MachineNode->getOperand(0),
5744 MachineNode->getOperand(0));
5747 ResNode = MachineNode->getOperand(1).getNode();
5750 ResNode = MachineNode->getOperand(0).getNode();
5752 // xor(~x, y) = eqv(x, y)
5753 ResNode = CurDAG->getMachineNode(PPC::CREQV, SDLoc(MachineNode),
5754 MVT::i1, MachineNode->getOperand(0).
5756 MachineNode->getOperand(1));
5758 // xor(x, ~y) = eqv(x, y)
5759 ResNode = CurDAG->getMachineNode(PPC::CREQV, SDLoc(MachineNode),
5760 MVT::i1, MachineNode->getOperand(0),
5761 MachineNode->getOperand(1).
5763 else if (AllUsersSelectZero(MachineNode)) {
5764 ResNode = CurDAG->getMachineNode(PPC::CREQV, SDLoc(MachineNode),
5765 MVT::i1, MachineNode->getOperand(0),
5766 MachineNode->getOperand(1));
5771 if (Op1Set || Op2Set)
5773 ResNode = CurDAG->getMachineNode(PPC::CRUNSET, SDLoc(MachineNode),
5776 // nor(0, y) = ~y -> nor(y, y)
5777 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
5778 MVT::i1, MachineNode->getOperand(1),
5779 MachineNode->getOperand(1));
5782 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
5783 MVT::i1, MachineNode->getOperand(0),
5784 MachineNode->getOperand(0));
5786 // nor(~x, y) = andc(x, y)
5787 ResNode = CurDAG->getMachineNode(PPC::CRANDC, SDLoc(MachineNode),
5788 MVT::i1, MachineNode->getOperand(0).
5790 MachineNode->getOperand(1));
5792 // nor(x, ~y) = andc(y, x)
5793 ResNode = CurDAG->getMachineNode(PPC::CRANDC, SDLoc(MachineNode),
5794 MVT::i1, MachineNode->getOperand(1).
5796 MachineNode->getOperand(0));
5797 else if (AllUsersSelectZero(MachineNode)) {
5798 ResNode = CurDAG->getMachineNode(PPC::CROR, SDLoc(MachineNode),
5799 MVT::i1, MachineNode->getOperand(0),
5800 MachineNode->getOperand(1));
5805 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
5807 ResNode = CurDAG->getMachineNode(PPC::CRSET, SDLoc(MachineNode),
5811 ResNode = MachineNode->getOperand(1).getNode();
5814 ResNode = MachineNode->getOperand(0).getNode();
5816 // eqv(0, y) = ~y -> nor(y, y)
5817 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
5818 MVT::i1, MachineNode->getOperand(1),
5819 MachineNode->getOperand(1));
5822 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
5823 MVT::i1, MachineNode->getOperand(0),
5824 MachineNode->getOperand(0));
5826 // eqv(~x, y) = xor(x, y)
5827 ResNode = CurDAG->getMachineNode(PPC::CRXOR, SDLoc(MachineNode),
5828 MVT::i1, MachineNode->getOperand(0).
5830 MachineNode->getOperand(1));
5832 // eqv(x, ~y) = xor(x, y)
5833 ResNode = CurDAG->getMachineNode(PPC::CRXOR, SDLoc(MachineNode),
5834 MVT::i1, MachineNode->getOperand(0),
5835 MachineNode->getOperand(1).
5837 else if (AllUsersSelectZero(MachineNode)) {
5838 ResNode = CurDAG->getMachineNode(PPC::CRXOR, SDLoc(MachineNode),
5839 MVT::i1, MachineNode->getOperand(0),
5840 MachineNode->getOperand(1));
5845 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
5847 ResNode = CurDAG->getMachineNode(PPC::CRUNSET, SDLoc(MachineNode),
5851 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
5852 MVT::i1, MachineNode->getOperand(1),
5853 MachineNode->getOperand(1));
5854 else if (Op1Unset || Op2Set)
5855 // andc(0, y) = andc(x, 1) = 0
5856 ResNode = CurDAG->getMachineNode(PPC::CRUNSET, SDLoc(MachineNode),
5860 ResNode = MachineNode->getOperand(0).getNode();
5862 // andc(~x, y) = ~(x | y) = nor(x, y)
5863 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
5864 MVT::i1, MachineNode->getOperand(0).
5866 MachineNode->getOperand(1));
5868 // andc(x, ~y) = x & y
5869 ResNode = CurDAG->getMachineNode(PPC::CRAND, SDLoc(MachineNode),
5870 MVT::i1, MachineNode->getOperand(0),
5871 MachineNode->getOperand(1).
5873 else if (AllUsersSelectZero(MachineNode)) {
5874 ResNode = CurDAG->getMachineNode(PPC::CRORC, SDLoc(MachineNode),
5875 MVT::i1, MachineNode->getOperand(1),
5876 MachineNode->getOperand(0));
5881 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
5883 ResNode = CurDAG->getMachineNode(PPC::CRSET, SDLoc(MachineNode),
5885 else if (Op1Set || Op2Unset)
5886 // orc(1, y) = orc(x, 0) = 1
5887 ResNode = CurDAG->getMachineNode(PPC::CRSET, SDLoc(MachineNode),
5891 ResNode = MachineNode->getOperand(0).getNode();
5894 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
5895 MVT::i1, MachineNode->getOperand(1),
5896 MachineNode->getOperand(1));
5898 // orc(~x, y) = ~(x & y) = nand(x, y)
5899 ResNode = CurDAG->getMachineNode(PPC::CRNAND, SDLoc(MachineNode),
5900 MVT::i1, MachineNode->getOperand(0).
5902 MachineNode->getOperand(1));
5904 // orc(x, ~y) = x | y
5905 ResNode = CurDAG->getMachineNode(PPC::CROR, SDLoc(MachineNode),
5906 MVT::i1, MachineNode->getOperand(0),
5907 MachineNode->getOperand(1).
5909 else if (AllUsersSelectZero(MachineNode)) {
5910 ResNode = CurDAG->getMachineNode(PPC::CRANDC, SDLoc(MachineNode),
5911 MVT::i1, MachineNode->getOperand(1),
5912 MachineNode->getOperand(0));
5916 case PPC::SELECT_I4:
5917 case PPC::SELECT_I8:
5918 case PPC::SELECT_F4:
5919 case PPC::SELECT_F8:
5920 case PPC::SELECT_QFRC:
5921 case PPC::SELECT_QSRC:
5922 case PPC::SELECT_QBRC:
5923 case PPC::SELECT_SPE:
5924 case PPC::SELECT_SPE4:
5925 case PPC::SELECT_VRRC:
5926 case PPC::SELECT_VSFRC:
5927 case PPC::SELECT_VSSRC:
5928 case PPC::SELECT_VSRC:
5930 ResNode = MachineNode->getOperand(1).getNode();
5932 ResNode = MachineNode->getOperand(2).getNode();
5934 ResNode = CurDAG->getMachineNode(MachineNode->getMachineOpcode(),
5936 MachineNode->getValueType(0),
5937 MachineNode->getOperand(0).
5939 MachineNode->getOperand(2),
5940 MachineNode->getOperand(1));
5945 ResNode = CurDAG->getMachineNode(Opcode == PPC::BC ? PPC::BCn :
5949 MachineNode->getOperand(0).
5951 MachineNode->getOperand(1),
5952 MachineNode->getOperand(2));
5953 // FIXME: Handle Op1Set, Op1Unset here too.
5957 // If we're inverting this node because it is used only by selects that
5958 // we'd like to swap, then swap the selects before the node replacement.
5960 SwapAllSelectUsers(MachineNode);
5962 if (ResNode != MachineNode) {
5963 LLVM_DEBUG(dbgs() << "CR Peephole replacing:\nOld: ");
5964 LLVM_DEBUG(MachineNode->dump(CurDAG));
5965 LLVM_DEBUG(dbgs() << "\nNew: ");
5966 LLVM_DEBUG(ResNode->dump(CurDAG));
5967 LLVM_DEBUG(dbgs() << "\n");
5969 ReplaceUses(MachineNode, ResNode);
5974 CurDAG->RemoveDeadNodes();
5975 } while (IsModified);
5978 // Gather the set of 32-bit operations that are known to have their
5979 // higher-order 32 bits zero, where ToPromote contains all such operations.
5980 static bool PeepholePPC64ZExtGather(SDValue Op32,
5981 SmallPtrSetImpl<SDNode *> &ToPromote) {
5982 if (!Op32.isMachineOpcode())
5985 // First, check for the "frontier" instructions (those that will clear the
5986 // higher-order 32 bits.
5988 // For RLWINM and RLWNM, we need to make sure that the mask does not wrap
5989 // around. If it does not, then these instructions will clear the
5990 // higher-order bits.
5991 if ((Op32.getMachineOpcode() == PPC::RLWINM ||
5992 Op32.getMachineOpcode() == PPC::RLWNM) &&
5993 Op32.getConstantOperandVal(2) <= Op32.getConstantOperandVal(3)) {
5994 ToPromote.insert(Op32.getNode());
5998 // SLW and SRW always clear the higher-order bits.
5999 if (Op32.getMachineOpcode() == PPC::SLW ||
6000 Op32.getMachineOpcode() == PPC::SRW) {
6001 ToPromote.insert(Op32.getNode());
6005 // For LI and LIS, we need the immediate to be positive (so that it is not
6007 if (Op32.getMachineOpcode() == PPC::LI ||
6008 Op32.getMachineOpcode() == PPC::LIS) {
6009 if (!isUInt<15>(Op32.getConstantOperandVal(0)))
6012 ToPromote.insert(Op32.getNode());
6016 // LHBRX and LWBRX always clear the higher-order bits.
6017 if (Op32.getMachineOpcode() == PPC::LHBRX ||
6018 Op32.getMachineOpcode() == PPC::LWBRX) {
6019 ToPromote.insert(Op32.getNode());
6023 // CNT[LT]ZW always produce a 64-bit value in [0,32], and so is zero extended.
6024 if (Op32.getMachineOpcode() == PPC::CNTLZW ||
6025 Op32.getMachineOpcode() == PPC::CNTTZW) {
6026 ToPromote.insert(Op32.getNode());
6030 // Next, check for those instructions we can look through.
6032 // Assuming the mask does not wrap around, then the higher-order bits are
6033 // taken directly from the first operand.
6034 if (Op32.getMachineOpcode() == PPC::RLWIMI &&
6035 Op32.getConstantOperandVal(3) <= Op32.getConstantOperandVal(4)) {
6036 SmallPtrSet<SDNode *, 16> ToPromote1;
6037 if (!PeepholePPC64ZExtGather(Op32.getOperand(0), ToPromote1))
6040 ToPromote.insert(Op32.getNode());
6041 ToPromote.insert(ToPromote1.begin(), ToPromote1.end());
6045 // For OR, the higher-order bits are zero if that is true for both operands.
6046 // For SELECT_I4, the same is true (but the relevant operand numbers are
6048 if (Op32.getMachineOpcode() == PPC::OR ||
6049 Op32.getMachineOpcode() == PPC::SELECT_I4) {
6050 unsigned B = Op32.getMachineOpcode() == PPC::SELECT_I4 ? 1 : 0;
6051 SmallPtrSet<SDNode *, 16> ToPromote1;
6052 if (!PeepholePPC64ZExtGather(Op32.getOperand(B+0), ToPromote1))
6054 if (!PeepholePPC64ZExtGather(Op32.getOperand(B+1), ToPromote1))
6057 ToPromote.insert(Op32.getNode());
6058 ToPromote.insert(ToPromote1.begin(), ToPromote1.end());
6062 // For ORI and ORIS, we need the higher-order bits of the first operand to be
6063 // zero, and also for the constant to be positive (so that it is not sign
6065 if (Op32.getMachineOpcode() == PPC::ORI ||
6066 Op32.getMachineOpcode() == PPC::ORIS) {
6067 SmallPtrSet<SDNode *, 16> ToPromote1;
6068 if (!PeepholePPC64ZExtGather(Op32.getOperand(0), ToPromote1))
6070 if (!isUInt<15>(Op32.getConstantOperandVal(1)))
6073 ToPromote.insert(Op32.getNode());
6074 ToPromote.insert(ToPromote1.begin(), ToPromote1.end());
6078 // The higher-order bits of AND are zero if that is true for at least one of
6080 if (Op32.getMachineOpcode() == PPC::AND) {
6081 SmallPtrSet<SDNode *, 16> ToPromote1, ToPromote2;
6083 PeepholePPC64ZExtGather(Op32.getOperand(0), ToPromote1);
6085 PeepholePPC64ZExtGather(Op32.getOperand(1), ToPromote2);
6086 if (!Op0OK && !Op1OK)
6089 ToPromote.insert(Op32.getNode());
6092 ToPromote.insert(ToPromote1.begin(), ToPromote1.end());
6095 ToPromote.insert(ToPromote2.begin(), ToPromote2.end());
6100 // For ANDI and ANDIS, the higher-order bits are zero if either that is true
6101 // of the first operand, or if the second operand is positive (so that it is
6102 // not sign extended).
6103 if (Op32.getMachineOpcode() == PPC::ANDIo ||
6104 Op32.getMachineOpcode() == PPC::ANDISo) {
6105 SmallPtrSet<SDNode *, 16> ToPromote1;
6107 PeepholePPC64ZExtGather(Op32.getOperand(0), ToPromote1);
6108 bool Op1OK = isUInt<15>(Op32.getConstantOperandVal(1));
6109 if (!Op0OK && !Op1OK)
6112 ToPromote.insert(Op32.getNode());
6115 ToPromote.insert(ToPromote1.begin(), ToPromote1.end());
6123 void PPCDAGToDAGISel::PeepholePPC64ZExt() {
6124 if (!PPCSubTarget->isPPC64())
6127 // When we zero-extend from i32 to i64, we use a pattern like this:
6128 // def : Pat<(i64 (zext i32:$in)),
6129 // (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32),
6131 // There are several 32-bit shift/rotate instructions, however, that will
6132 // clear the higher-order bits of their output, rendering the RLDICL
6133 // unnecessary. When that happens, we remove it here, and redefine the
6134 // relevant 32-bit operation to be a 64-bit operation.
6136 SelectionDAG::allnodes_iterator Position = CurDAG->allnodes_end();
6138 bool MadeChange = false;
6139 while (Position != CurDAG->allnodes_begin()) {
6140 SDNode *N = &*--Position;
6141 // Skip dead nodes and any non-machine opcodes.
6142 if (N->use_empty() || !N->isMachineOpcode())
6145 if (N->getMachineOpcode() != PPC::RLDICL)
6148 if (N->getConstantOperandVal(1) != 0 ||
6149 N->getConstantOperandVal(2) != 32)
6152 SDValue ISR = N->getOperand(0);
6153 if (!ISR.isMachineOpcode() ||
6154 ISR.getMachineOpcode() != TargetOpcode::INSERT_SUBREG)
6157 if (!ISR.hasOneUse())
6160 if (ISR.getConstantOperandVal(2) != PPC::sub_32)
6163 SDValue IDef = ISR.getOperand(0);
6164 if (!IDef.isMachineOpcode() ||
6165 IDef.getMachineOpcode() != TargetOpcode::IMPLICIT_DEF)
6168 // We now know that we're looking at a canonical i32 -> i64 zext. See if we
6169 // can get rid of it.
6171 SDValue Op32 = ISR->getOperand(1);
6172 if (!Op32.isMachineOpcode())
6175 // There are some 32-bit instructions that always clear the high-order 32
6176 // bits, there are also some instructions (like AND) that we can look
6178 SmallPtrSet<SDNode *, 16> ToPromote;
6179 if (!PeepholePPC64ZExtGather(Op32, ToPromote))
6182 // If the ToPromote set contains nodes that have uses outside of the set
6183 // (except for the original INSERT_SUBREG), then abort the transformation.
6184 bool OutsideUse = false;
6185 for (SDNode *PN : ToPromote) {
6186 for (SDNode *UN : PN->uses()) {
6187 if (!ToPromote.count(UN) && UN != ISR.getNode()) {
6201 // We now know that this zero extension can be removed by promoting to
6202 // nodes in ToPromote to 64-bit operations, where for operations in the
6203 // frontier of the set, we need to insert INSERT_SUBREGs for their
6205 for (SDNode *PN : ToPromote) {
6207 switch (PN->getMachineOpcode()) {
6209 llvm_unreachable("Don't know the 64-bit variant of this instruction");
6210 case PPC::RLWINM: NewOpcode = PPC::RLWINM8; break;
6211 case PPC::RLWNM: NewOpcode = PPC::RLWNM8; break;
6212 case PPC::SLW: NewOpcode = PPC::SLW8; break;
6213 case PPC::SRW: NewOpcode = PPC::SRW8; break;
6214 case PPC::LI: NewOpcode = PPC::LI8; break;
6215 case PPC::LIS: NewOpcode = PPC::LIS8; break;
6216 case PPC::LHBRX: NewOpcode = PPC::LHBRX8; break;
6217 case PPC::LWBRX: NewOpcode = PPC::LWBRX8; break;
6218 case PPC::CNTLZW: NewOpcode = PPC::CNTLZW8; break;
6219 case PPC::CNTTZW: NewOpcode = PPC::CNTTZW8; break;
6220 case PPC::RLWIMI: NewOpcode = PPC::RLWIMI8; break;
6221 case PPC::OR: NewOpcode = PPC::OR8; break;
6222 case PPC::SELECT_I4: NewOpcode = PPC::SELECT_I8; break;
6223 case PPC::ORI: NewOpcode = PPC::ORI8; break;
6224 case PPC::ORIS: NewOpcode = PPC::ORIS8; break;
6225 case PPC::AND: NewOpcode = PPC::AND8; break;
6226 case PPC::ANDIo: NewOpcode = PPC::ANDIo8; break;
6227 case PPC::ANDISo: NewOpcode = PPC::ANDISo8; break;
6230 // Note: During the replacement process, the nodes will be in an
6231 // inconsistent state (some instructions will have operands with values
6232 // of the wrong type). Once done, however, everything should be right
6235 SmallVector<SDValue, 4> Ops;
6236 for (const SDValue &V : PN->ops()) {
6237 if (!ToPromote.count(V.getNode()) && V.getValueType() == MVT::i32 &&
6238 !isa<ConstantSDNode>(V)) {
6239 SDValue ReplOpOps[] = { ISR.getOperand(0), V, ISR.getOperand(2) };
6241 CurDAG->getMachineNode(TargetOpcode::INSERT_SUBREG, SDLoc(V),
6242 ISR.getNode()->getVTList(), ReplOpOps);
6243 Ops.push_back(SDValue(ReplOp, 0));
6249 // Because all to-be-promoted nodes only have users that are other
6250 // promoted nodes (or the original INSERT_SUBREG), we can safely replace
6251 // the i32 result value type with i64.
6253 SmallVector<EVT, 2> NewVTs;
6254 SDVTList VTs = PN->getVTList();
6255 for (unsigned i = 0, ie = VTs.NumVTs; i != ie; ++i)
6256 if (VTs.VTs[i] == MVT::i32)
6257 NewVTs.push_back(MVT::i64);
6259 NewVTs.push_back(VTs.VTs[i]);
6261 LLVM_DEBUG(dbgs() << "PPC64 ZExt Peephole morphing:\nOld: ");
6262 LLVM_DEBUG(PN->dump(CurDAG));
6264 CurDAG->SelectNodeTo(PN, NewOpcode, CurDAG->getVTList(NewVTs), Ops);
6266 LLVM_DEBUG(dbgs() << "\nNew: ");
6267 LLVM_DEBUG(PN->dump(CurDAG));
6268 LLVM_DEBUG(dbgs() << "\n");
6271 // Now we replace the original zero extend and its associated INSERT_SUBREG
6272 // with the value feeding the INSERT_SUBREG (which has now been promoted to
6275 LLVM_DEBUG(dbgs() << "PPC64 ZExt Peephole replacing:\nOld: ");
6276 LLVM_DEBUG(N->dump(CurDAG));
6277 LLVM_DEBUG(dbgs() << "\nNew: ");
6278 LLVM_DEBUG(Op32.getNode()->dump(CurDAG));
6279 LLVM_DEBUG(dbgs() << "\n");
6281 ReplaceUses(N, Op32.getNode());
6285 CurDAG->RemoveDeadNodes();
6288 void PPCDAGToDAGISel::PeepholePPC64() {
6289 // These optimizations are currently supported only for 64-bit SVR4.
6290 if (PPCSubTarget->isDarwin() || !PPCSubTarget->isPPC64())
6293 SelectionDAG::allnodes_iterator Position = CurDAG->allnodes_end();
6295 while (Position != CurDAG->allnodes_begin()) {
6296 SDNode *N = &*--Position;
6297 // Skip dead nodes and any non-machine opcodes.
6298 if (N->use_empty() || !N->isMachineOpcode())
6302 unsigned StorageOpcode = N->getMachineOpcode();
6303 bool RequiresMod4Offset = false;
6305 switch (StorageOpcode) {
6310 case PPC::DFLOADf64:
6311 case PPC::DFLOADf32:
6312 RequiresMod4Offset = true;
6328 case PPC::DFSTOREf64:
6329 case PPC::DFSTOREf32:
6330 RequiresMod4Offset = true;
6344 // If this is a load or store with a zero offset, or within the alignment,
6345 // we may be able to fold an add-immediate into the memory operation.
6346 // The check against alignment is below, as it can't occur until we check
6347 // the arguments to N
6348 if (!isa<ConstantSDNode>(N->getOperand(FirstOp)))
6351 SDValue Base = N->getOperand(FirstOp + 1);
6352 if (!Base.isMachineOpcode())
6356 bool ReplaceFlags = true;
6358 // When the feeding operation is an add-immediate of some sort,
6359 // determine whether we need to add relocation information to the
6360 // target flags on the immediate operand when we fold it into the
6361 // load instruction.
6363 // For something like ADDItocL, the relocation information is
6364 // inferred from the opcode; when we process it in the AsmPrinter,
6365 // we add the necessary relocation there. A load, though, can receive
6366 // relocation from various flavors of ADDIxxx, so we need to carry
6367 // the relocation information in the target flags.
6368 switch (Base.getMachineOpcode()) {
6373 // In some cases (such as TLS) the relocation information
6374 // is already in place on the operand, so copying the operand
6376 ReplaceFlags = false;
6377 // For these cases, the immediate may not be divisible by 4, in
6378 // which case the fold is illegal for DS-form instructions. (The
6379 // other cases provide aligned addresses and are always safe.)
6380 if (RequiresMod4Offset &&
6381 (!isa<ConstantSDNode>(Base.getOperand(1)) ||
6382 Base.getConstantOperandVal(1) % 4 != 0))
6385 case PPC::ADDIdtprelL:
6386 Flags = PPCII::MO_DTPREL_LO;
6388 case PPC::ADDItlsldL:
6389 Flags = PPCII::MO_TLSLD_LO;
6392 Flags = PPCII::MO_TOC_LO;
6396 SDValue ImmOpnd = Base.getOperand(1);
6398 // On PPC64, the TOC base pointer is guaranteed by the ABI only to have
6399 // 8-byte alignment, and so we can only use offsets less than 8 (otherwise,
6400 // we might have needed different @ha relocation values for the offset
6402 int MaxDisplacement = 7;
6403 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(ImmOpnd)) {
6404 const GlobalValue *GV = GA->getGlobal();
6405 MaxDisplacement = std::min((int) GV->getAlignment() - 1, MaxDisplacement);
6408 bool UpdateHBase = false;
6409 SDValue HBase = Base.getOperand(0);
6411 int Offset = N->getConstantOperandVal(FirstOp);
6413 if (Offset < 0 || Offset > MaxDisplacement) {
6414 // If we have a addi(toc@l)/addis(toc@ha) pair, and the addis has only
6415 // one use, then we can do this for any offset, we just need to also
6416 // update the offset (i.e. the symbol addend) on the addis also.
6417 if (Base.getMachineOpcode() != PPC::ADDItocL)
6420 if (!HBase.isMachineOpcode() ||
6421 HBase.getMachineOpcode() != PPC::ADDIStocHA)
6424 if (!Base.hasOneUse() || !HBase.hasOneUse())
6427 SDValue HImmOpnd = HBase.getOperand(1);
6428 if (HImmOpnd != ImmOpnd)
6434 // If we're directly folding the addend from an addi instruction, then:
6435 // 1. In general, the offset on the memory access must be zero.
6436 // 2. If the addend is a constant, then it can be combined with a
6437 // non-zero offset, but only if the result meets the encoding
6439 if (auto *C = dyn_cast<ConstantSDNode>(ImmOpnd)) {
6440 Offset += C->getSExtValue();
6442 if (RequiresMod4Offset && (Offset % 4) != 0)
6445 if (!isInt<16>(Offset))
6448 ImmOpnd = CurDAG->getTargetConstant(Offset, SDLoc(ImmOpnd),
6449 ImmOpnd.getValueType());
6450 } else if (Offset != 0) {
6455 // We found an opportunity. Reverse the operands from the add
6456 // immediate and substitute them into the load or store. If
6457 // needed, update the target flags for the immediate operand to
6458 // reflect the necessary relocation information.
6459 LLVM_DEBUG(dbgs() << "Folding add-immediate into mem-op:\nBase: ");
6460 LLVM_DEBUG(Base->dump(CurDAG));
6461 LLVM_DEBUG(dbgs() << "\nN: ");
6462 LLVM_DEBUG(N->dump(CurDAG));
6463 LLVM_DEBUG(dbgs() << "\n");
6465 // If the relocation information isn't already present on the
6466 // immediate operand, add it now.
6468 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(ImmOpnd)) {
6470 const GlobalValue *GV = GA->getGlobal();
6471 // We can't perform this optimization for data whose alignment
6472 // is insufficient for the instruction encoding.
6473 if (GV->getAlignment() < 4 &&
6474 (RequiresMod4Offset || (Offset % 4) != 0)) {
6475 LLVM_DEBUG(dbgs() << "Rejected this candidate for alignment.\n\n");
6478 ImmOpnd = CurDAG->getTargetGlobalAddress(GV, dl, MVT::i64, Offset, Flags);
6479 } else if (ConstantPoolSDNode *CP =
6480 dyn_cast<ConstantPoolSDNode>(ImmOpnd)) {
6481 const Constant *C = CP->getConstVal();
6482 ImmOpnd = CurDAG->getTargetConstantPool(C, MVT::i64,
6488 if (FirstOp == 1) // Store
6489 (void)CurDAG->UpdateNodeOperands(N, N->getOperand(0), ImmOpnd,
6490 Base.getOperand(0), N->getOperand(3));
6492 (void)CurDAG->UpdateNodeOperands(N, ImmOpnd, Base.getOperand(0),
6496 (void)CurDAG->UpdateNodeOperands(HBase.getNode(), HBase.getOperand(0),
6499 // The add-immediate may now be dead, in which case remove it.
6500 if (Base.getNode()->use_empty())
6501 CurDAG->RemoveDeadNode(Base.getNode());
6505 /// createPPCISelDag - This pass converts a legalized DAG into a
6506 /// PowerPC-specific DAG, ready for instruction scheduling.
6508 FunctionPass *llvm::createPPCISelDag(PPCTargetMachine &TM,
6509 CodeGenOpt::Level OptLevel) {
6510 return new PPCDAGToDAGISel(TM, OptLevel);