1 //===-- PPCISelDAGToDAG.cpp - PPC --pattern matching inst selector --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for PowerPC,
11 // converting from a legalized dag to a PPC dag.
13 //===----------------------------------------------------------------------===//
15 #include "MCTargetDesc/PPCMCTargetDesc.h"
16 #include "MCTargetDesc/PPCPredicates.h"
18 #include "PPCISelLowering.h"
19 #include "PPCMachineFunctionInfo.h"
20 #include "PPCSubtarget.h"
21 #include "PPCTargetMachine.h"
22 #include "llvm/ADT/APInt.h"
23 #include "llvm/ADT/DenseMap.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/ADT/SmallPtrSet.h"
26 #include "llvm/ADT/SmallVector.h"
27 #include "llvm/ADT/Statistic.h"
28 #include "llvm/Analysis/BranchProbabilityInfo.h"
29 #include "llvm/CodeGen/FunctionLoweringInfo.h"
30 #include "llvm/CodeGen/ISDOpcodes.h"
31 #include "llvm/CodeGen/MachineBasicBlock.h"
32 #include "llvm/CodeGen/MachineFunction.h"
33 #include "llvm/CodeGen/MachineInstrBuilder.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/SelectionDAG.h"
36 #include "llvm/CodeGen/SelectionDAGISel.h"
37 #include "llvm/CodeGen/SelectionDAGNodes.h"
38 #include "llvm/CodeGen/TargetInstrInfo.h"
39 #include "llvm/CodeGen/TargetRegisterInfo.h"
40 #include "llvm/CodeGen/ValueTypes.h"
41 #include "llvm/IR/BasicBlock.h"
42 #include "llvm/IR/DebugLoc.h"
43 #include "llvm/IR/Function.h"
44 #include "llvm/IR/GlobalValue.h"
45 #include "llvm/IR/InlineAsm.h"
46 #include "llvm/IR/InstrTypes.h"
47 #include "llvm/IR/Module.h"
48 #include "llvm/Support/Casting.h"
49 #include "llvm/Support/CodeGen.h"
50 #include "llvm/Support/CommandLine.h"
51 #include "llvm/Support/Compiler.h"
52 #include "llvm/Support/Debug.h"
53 #include "llvm/Support/ErrorHandling.h"
54 #include "llvm/Support/KnownBits.h"
55 #include "llvm/Support/MachineValueType.h"
56 #include "llvm/Support/MathExtras.h"
57 #include "llvm/Support/raw_ostream.h"
70 #define DEBUG_TYPE "ppc-codegen"
72 STATISTIC(NumSextSetcc,
73 "Number of (sext(setcc)) nodes expanded into GPR sequence.");
74 STATISTIC(NumZextSetcc,
75 "Number of (zext(setcc)) nodes expanded into GPR sequence.");
76 STATISTIC(SignExtensionsAdded,
77 "Number of sign extensions for compare inputs added.");
78 STATISTIC(ZeroExtensionsAdded,
79 "Number of zero extensions for compare inputs added.");
80 STATISTIC(NumLogicOpsOnComparison,
81 "Number of logical ops on i1 values calculated in GPR.");
82 STATISTIC(OmittedForNonExtendUses,
83 "Number of compares not eliminated as they have non-extending uses.");
85 // FIXME: Remove this once the bug has been fixed!
86 cl::opt<bool> ANDIGlueBug("expose-ppc-andi-glue-bug",
87 cl::desc("expose the ANDI glue bug on PPC"), cl::Hidden);
90 UseBitPermRewriter("ppc-use-bit-perm-rewriter", cl::init(true),
91 cl::desc("use aggressive ppc isel for bit permutations"),
93 static cl::opt<bool> BPermRewriterNoMasking(
94 "ppc-bit-perm-rewriter-stress-rotates",
95 cl::desc("stress rotate selection in aggressive ppc isel for "
99 static cl::opt<bool> EnableBranchHint(
100 "ppc-use-branch-hint", cl::init(true),
101 cl::desc("Enable static hinting of branches on ppc"),
104 static cl::opt<bool> EnableTLSOpt(
105 "ppc-tls-opt", cl::init(true),
106 cl::desc("Enable tls optimization peephole"),
109 enum ICmpInGPRType { ICGPR_All, ICGPR_None, ICGPR_I32, ICGPR_I64,
110 ICGPR_NonExtIn, ICGPR_Zext, ICGPR_Sext, ICGPR_ZextI32,
111 ICGPR_SextI32, ICGPR_ZextI64, ICGPR_SextI64 };
113 static cl::opt<ICmpInGPRType> CmpInGPR(
114 "ppc-gpr-icmps", cl::Hidden, cl::init(ICGPR_All),
115 cl::desc("Specify the types of comparisons to emit GPR-only code for."),
116 cl::values(clEnumValN(ICGPR_None, "none", "Do not modify integer comparisons."),
117 clEnumValN(ICGPR_All, "all", "All possible int comparisons in GPRs."),
118 clEnumValN(ICGPR_I32, "i32", "Only i32 comparisons in GPRs."),
119 clEnumValN(ICGPR_I64, "i64", "Only i64 comparisons in GPRs."),
120 clEnumValN(ICGPR_NonExtIn, "nonextin",
121 "Only comparisons where inputs don't need [sz]ext."),
122 clEnumValN(ICGPR_Zext, "zext", "Only comparisons with zext result."),
123 clEnumValN(ICGPR_ZextI32, "zexti32",
124 "Only i32 comparisons with zext result."),
125 clEnumValN(ICGPR_ZextI64, "zexti64",
126 "Only i64 comparisons with zext result."),
127 clEnumValN(ICGPR_Sext, "sext", "Only comparisons with sext result."),
128 clEnumValN(ICGPR_SextI32, "sexti32",
129 "Only i32 comparisons with sext result."),
130 clEnumValN(ICGPR_SextI64, "sexti64",
131 "Only i64 comparisons with sext result.")));
134 //===--------------------------------------------------------------------===//
135 /// PPCDAGToDAGISel - PPC specific code to select PPC machine
136 /// instructions for SelectionDAG operations.
138 class PPCDAGToDAGISel : public SelectionDAGISel {
139 const PPCTargetMachine &TM;
140 const PPCSubtarget *PPCSubTarget;
141 const PPCTargetLowering *PPCLowering;
142 unsigned GlobalBaseReg;
145 explicit PPCDAGToDAGISel(PPCTargetMachine &tm, CodeGenOpt::Level OptLevel)
146 : SelectionDAGISel(tm, OptLevel), TM(tm) {}
148 bool runOnMachineFunction(MachineFunction &MF) override {
149 // Make sure we re-emit a set of the global base reg if necessary
151 PPCSubTarget = &MF.getSubtarget<PPCSubtarget>();
152 PPCLowering = PPCSubTarget->getTargetLowering();
153 SelectionDAGISel::runOnMachineFunction(MF);
155 if (!PPCSubTarget->isSVR4ABI())
156 InsertVRSaveCode(MF);
161 void PreprocessISelDAG() override;
162 void PostprocessISelDAG() override;
164 /// getI16Imm - Return a target constant with the specified value, of type
166 inline SDValue getI16Imm(unsigned Imm, const SDLoc &dl) {
167 return CurDAG->getTargetConstant(Imm, dl, MVT::i16);
170 /// getI32Imm - Return a target constant with the specified value, of type
172 inline SDValue getI32Imm(unsigned Imm, const SDLoc &dl) {
173 return CurDAG->getTargetConstant(Imm, dl, MVT::i32);
176 /// getI64Imm - Return a target constant with the specified value, of type
178 inline SDValue getI64Imm(uint64_t Imm, const SDLoc &dl) {
179 return CurDAG->getTargetConstant(Imm, dl, MVT::i64);
182 /// getSmallIPtrImm - Return a target constant of pointer type.
183 inline SDValue getSmallIPtrImm(unsigned Imm, const SDLoc &dl) {
184 return CurDAG->getTargetConstant(
185 Imm, dl, PPCLowering->getPointerTy(CurDAG->getDataLayout()));
188 /// isRotateAndMask - Returns true if Mask and Shift can be folded into a
189 /// rotate and mask opcode and mask operation.
190 static bool isRotateAndMask(SDNode *N, unsigned Mask, bool isShiftMask,
191 unsigned &SH, unsigned &MB, unsigned &ME);
193 /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
194 /// base register. Return the virtual register that holds this value.
195 SDNode *getGlobalBaseReg();
197 void selectFrameIndex(SDNode *SN, SDNode *N, unsigned Offset = 0);
199 // Select - Convert the specified operand from a target-independent to a
200 // target-specific node if it hasn't already been changed.
201 void Select(SDNode *N) override;
203 bool tryBitfieldInsert(SDNode *N);
204 bool tryBitPermutation(SDNode *N);
205 bool tryIntCompareInGPR(SDNode *N);
207 // tryTLSXFormLoad - Convert an ISD::LOAD fed by a PPCISD::ADD_TLS into
208 // an X-Form load instruction with the offset being a relocation coming from
209 // the PPCISD::ADD_TLS.
210 bool tryTLSXFormLoad(LoadSDNode *N);
211 // tryTLSXFormStore - Convert an ISD::STORE fed by a PPCISD::ADD_TLS into
212 // an X-Form store instruction with the offset being a relocation coming from
213 // the PPCISD::ADD_TLS.
214 bool tryTLSXFormStore(StoreSDNode *N);
215 /// SelectCC - Select a comparison of the specified values with the
216 /// specified condition code, returning the CR# of the expression.
217 SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC,
220 /// SelectAddrImm - Returns true if the address N can be represented by
221 /// a base register plus a signed 16-bit displacement [r+imm].
222 bool SelectAddrImm(SDValue N, SDValue &Disp,
224 return PPCLowering->SelectAddressRegImm(N, Disp, Base, *CurDAG, 0);
227 /// SelectAddrImmOffs - Return true if the operand is valid for a preinc
228 /// immediate field. Note that the operand at this point is already the
229 /// result of a prior SelectAddressRegImm call.
230 bool SelectAddrImmOffs(SDValue N, SDValue &Out) const {
231 if (N.getOpcode() == ISD::TargetConstant ||
232 N.getOpcode() == ISD::TargetGlobalAddress) {
240 /// SelectAddrIdx - Given the specified addressed, check to see if it can be
241 /// represented as an indexed [r+r] operation. Returns false if it can
242 /// be represented by [r+imm], which are preferred.
243 bool SelectAddrIdx(SDValue N, SDValue &Base, SDValue &Index) {
244 return PPCLowering->SelectAddressRegReg(N, Base, Index, *CurDAG);
247 /// SelectAddrIdxOnly - Given the specified addressed, force it to be
248 /// represented as an indexed [r+r] operation.
249 bool SelectAddrIdxOnly(SDValue N, SDValue &Base, SDValue &Index) {
250 return PPCLowering->SelectAddressRegRegOnly(N, Base, Index, *CurDAG);
253 /// SelectAddrImmX4 - Returns true if the address N can be represented by
254 /// a base register plus a signed 16-bit displacement that is a multiple of 4.
255 /// Suitable for use by STD and friends.
256 bool SelectAddrImmX4(SDValue N, SDValue &Disp, SDValue &Base) {
257 return PPCLowering->SelectAddressRegImm(N, Disp, Base, *CurDAG, 4);
260 bool SelectAddrImmX16(SDValue N, SDValue &Disp, SDValue &Base) {
261 return PPCLowering->SelectAddressRegImm(N, Disp, Base, *CurDAG, 16);
264 // Select an address into a single register.
265 bool SelectAddr(SDValue N, SDValue &Base) {
270 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
271 /// inline asm expressions. It is always correct to compute the value into
272 /// a register. The case of adding a (possibly relocatable) constant to a
273 /// register can be improved, but it is wrong to substitute Reg+Reg for
274 /// Reg in an asm, because the load or store opcode would have to change.
275 bool SelectInlineAsmMemoryOperand(const SDValue &Op,
276 unsigned ConstraintID,
277 std::vector<SDValue> &OutOps) override {
278 switch(ConstraintID) {
280 errs() << "ConstraintID: " << ConstraintID << "\n";
281 llvm_unreachable("Unexpected asm memory constraint");
282 case InlineAsm::Constraint_es:
283 case InlineAsm::Constraint_i:
284 case InlineAsm::Constraint_m:
285 case InlineAsm::Constraint_o:
286 case InlineAsm::Constraint_Q:
287 case InlineAsm::Constraint_Z:
288 case InlineAsm::Constraint_Zy:
289 // We need to make sure that this one operand does not end up in r0
290 // (because we might end up lowering this as 0(%op)).
291 const TargetRegisterInfo *TRI = PPCSubTarget->getRegisterInfo();
292 const TargetRegisterClass *TRC = TRI->getPointerRegClass(*MF, /*Kind=*/1);
294 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), dl, MVT::i32);
296 SDValue(CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS,
297 dl, Op.getValueType(),
300 OutOps.push_back(NewOp);
306 void InsertVRSaveCode(MachineFunction &MF);
308 StringRef getPassName() const override {
309 return "PowerPC DAG->DAG Pattern Instruction Selection";
312 // Include the pieces autogenerated from the target description.
313 #include "PPCGenDAGISel.inc"
316 bool trySETCC(SDNode *N);
318 void PeepholePPC64();
319 void PeepholePPC64ZExt();
320 void PeepholeCROps();
322 SDValue combineToCMPB(SDNode *N);
323 void foldBoolExts(SDValue &Res, SDNode *&N);
325 bool AllUsersSelectZero(SDNode *N);
326 void SwapAllSelectUsers(SDNode *N);
328 bool isOffsetMultipleOf(SDNode *N, unsigned Val) const;
329 void transferMemOperands(SDNode *N, SDNode *Result);
330 MachineSDNode *flipSignBit(const SDValue &N, SDNode **SignBit = nullptr);
333 } // end anonymous namespace
335 /// InsertVRSaveCode - Once the entire function has been instruction selected,
336 /// all virtual registers are created and all machine instructions are built,
337 /// check to see if we need to save/restore VRSAVE. If so, do it.
338 void PPCDAGToDAGISel::InsertVRSaveCode(MachineFunction &Fn) {
339 // Check to see if this function uses vector registers, which means we have to
340 // save and restore the VRSAVE register and update it with the regs we use.
342 // In this case, there will be virtual registers of vector type created
343 // by the scheduler. Detect them now.
344 bool HasVectorVReg = false;
345 for (unsigned i = 0, e = RegInfo->getNumVirtRegs(); i != e; ++i) {
346 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
347 if (RegInfo->getRegClass(Reg) == &PPC::VRRCRegClass) {
348 HasVectorVReg = true;
352 if (!HasVectorVReg) return; // nothing to do.
354 // If we have a vector register, we want to emit code into the entry and exit
355 // blocks to save and restore the VRSAVE register. We do this here (instead
356 // of marking all vector instructions as clobbering VRSAVE) for two reasons:
358 // 1. This (trivially) reduces the load on the register allocator, by not
359 // having to represent the live range of the VRSAVE register.
360 // 2. This (more significantly) allows us to create a temporary virtual
361 // register to hold the saved VRSAVE value, allowing this temporary to be
362 // register allocated, instead of forcing it to be spilled to the stack.
364 // Create two vregs - one to hold the VRSAVE register that is live-in to the
365 // function and one for the value after having bits or'd into it.
366 unsigned InVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
367 unsigned UpdatedVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
369 const TargetInstrInfo &TII = *PPCSubTarget->getInstrInfo();
370 MachineBasicBlock &EntryBB = *Fn.begin();
372 // Emit the following code into the entry block:
373 // InVRSAVE = MFVRSAVE
374 // UpdatedVRSAVE = UPDATE_VRSAVE InVRSAVE
375 // MTVRSAVE UpdatedVRSAVE
376 MachineBasicBlock::iterator IP = EntryBB.begin(); // Insert Point
377 BuildMI(EntryBB, IP, dl, TII.get(PPC::MFVRSAVE), InVRSAVE);
378 BuildMI(EntryBB, IP, dl, TII.get(PPC::UPDATE_VRSAVE),
379 UpdatedVRSAVE).addReg(InVRSAVE);
380 BuildMI(EntryBB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(UpdatedVRSAVE);
382 // Find all return blocks, outputting a restore in each epilog.
383 for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
384 if (BB->isReturnBlock()) {
385 IP = BB->end(); --IP;
387 // Skip over all terminator instructions, which are part of the return
389 MachineBasicBlock::iterator I2 = IP;
390 while (I2 != BB->begin() && (--I2)->isTerminator())
393 // Emit: MTVRSAVE InVRSave
394 BuildMI(*BB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(InVRSAVE);
399 /// getGlobalBaseReg - Output the instructions required to put the
400 /// base address to use for accessing globals into a register.
402 SDNode *PPCDAGToDAGISel::getGlobalBaseReg() {
403 if (!GlobalBaseReg) {
404 const TargetInstrInfo &TII = *PPCSubTarget->getInstrInfo();
405 // Insert the set of GlobalBaseReg into the first MBB of the function
406 MachineBasicBlock &FirstMBB = MF->front();
407 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
408 const Module *M = MF->getFunction().getParent();
411 if (PPCLowering->getPointerTy(CurDAG->getDataLayout()) == MVT::i32) {
412 if (PPCSubTarget->isTargetELF()) {
413 GlobalBaseReg = PPC::R30;
414 if (M->getPICLevel() == PICLevel::SmallPIC) {
415 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MoveGOTtoLR));
416 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg);
417 MF->getInfo<PPCFunctionInfo>()->setUsesPICBase(true);
419 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR));
420 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg);
421 unsigned TempReg = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
422 BuildMI(FirstMBB, MBBI, dl,
423 TII.get(PPC::UpdateGBR), GlobalBaseReg)
424 .addReg(TempReg, RegState::Define).addReg(GlobalBaseReg);
425 MF->getInfo<PPCFunctionInfo>()->setUsesPICBase(true);
429 RegInfo->createVirtualRegister(&PPC::GPRC_and_GPRC_NOR0RegClass);
430 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR));
431 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg);
434 // We must ensure that this sequence is dominated by the prologue.
435 // FIXME: This is a bit of a big hammer since we don't get the benefits
436 // of shrink-wrapping whenever we emit this instruction. Considering
437 // this is used in any function where we emit a jump table, this may be
438 // a significant limitation. We should consider inserting this in the
439 // block where it is used and then commoning this sequence up if it
440 // appears in multiple places.
441 // Note: on ISA 3.0 cores, we can use lnia (addpcis) instead of
443 MF->getInfo<PPCFunctionInfo>()->setShrinkWrapDisabled(true);
444 GlobalBaseReg = RegInfo->createVirtualRegister(&PPC::G8RC_and_G8RC_NOX0RegClass);
445 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR8));
446 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR8), GlobalBaseReg);
449 return CurDAG->getRegister(GlobalBaseReg,
450 PPCLowering->getPointerTy(CurDAG->getDataLayout()))
454 /// isInt32Immediate - This method tests to see if the node is a 32-bit constant
455 /// operand. If so Imm will receive the 32-bit value.
456 static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
457 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
458 Imm = cast<ConstantSDNode>(N)->getZExtValue();
464 /// isInt64Immediate - This method tests to see if the node is a 64-bit constant
465 /// operand. If so Imm will receive the 64-bit value.
466 static bool isInt64Immediate(SDNode *N, uint64_t &Imm) {
467 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i64) {
468 Imm = cast<ConstantSDNode>(N)->getZExtValue();
474 // isInt32Immediate - This method tests to see if a constant operand.
475 // If so Imm will receive the 32 bit value.
476 static bool isInt32Immediate(SDValue N, unsigned &Imm) {
477 return isInt32Immediate(N.getNode(), Imm);
480 /// isInt64Immediate - This method tests to see if the value is a 64-bit
481 /// constant operand. If so Imm will receive the 64-bit value.
482 static bool isInt64Immediate(SDValue N, uint64_t &Imm) {
483 return isInt64Immediate(N.getNode(), Imm);
486 static unsigned getBranchHint(unsigned PCC, FunctionLoweringInfo *FuncInfo,
487 const SDValue &DestMBB) {
488 assert(isa<BasicBlockSDNode>(DestMBB));
490 if (!FuncInfo->BPI) return PPC::BR_NO_HINT;
492 const BasicBlock *BB = FuncInfo->MBB->getBasicBlock();
493 const TerminatorInst *BBTerm = BB->getTerminator();
495 if (BBTerm->getNumSuccessors() != 2) return PPC::BR_NO_HINT;
497 const BasicBlock *TBB = BBTerm->getSuccessor(0);
498 const BasicBlock *FBB = BBTerm->getSuccessor(1);
500 auto TProb = FuncInfo->BPI->getEdgeProbability(BB, TBB);
501 auto FProb = FuncInfo->BPI->getEdgeProbability(BB, FBB);
503 // We only want to handle cases which are easy to predict at static time, e.g.
504 // C++ throw statement, that is very likely not taken, or calling never
505 // returned function, e.g. stdlib exit(). So we set Threshold to filter
508 // Below is LLVM branch weight table, we only want to handle case 1, 2
510 // Case Taken:Nontaken Example
511 // 1. Unreachable 1048575:1 C++ throw, stdlib exit(),
512 // 2. Invoke-terminating 1:1048575
513 // 3. Coldblock 4:64 __builtin_expect
514 // 4. Loop Branch 124:4 For loop
515 // 5. PH/ZH/FPH 20:12
516 const uint32_t Threshold = 10000;
518 if (std::max(TProb, FProb) / Threshold < std::min(TProb, FProb))
519 return PPC::BR_NO_HINT;
521 LLVM_DEBUG(dbgs() << "Use branch hint for '" << FuncInfo->Fn->getName()
522 << "::" << BB->getName() << "'\n"
523 << " -> " << TBB->getName() << ": " << TProb << "\n"
524 << " -> " << FBB->getName() << ": " << FProb << "\n");
526 const BasicBlockSDNode *BBDN = cast<BasicBlockSDNode>(DestMBB);
528 // If Dest BasicBlock is False-BasicBlock (FBB), swap branch probabilities,
529 // because we want 'TProb' stands for 'branch probability' to Dest BasicBlock
530 if (BBDN->getBasicBlock()->getBasicBlock() != TBB)
531 std::swap(TProb, FProb);
533 return (TProb > FProb) ? PPC::BR_TAKEN_HINT : PPC::BR_NONTAKEN_HINT;
536 // isOpcWithIntImmediate - This method tests to see if the node is a specific
537 // opcode and that it has a immediate integer right operand.
538 // If so Imm will receive the 32 bit value.
539 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
540 return N->getOpcode() == Opc
541 && isInt32Immediate(N->getOperand(1).getNode(), Imm);
544 void PPCDAGToDAGISel::selectFrameIndex(SDNode *SN, SDNode *N, unsigned Offset) {
546 int FI = cast<FrameIndexSDNode>(N)->getIndex();
547 SDValue TFI = CurDAG->getTargetFrameIndex(FI, N->getValueType(0));
548 unsigned Opc = N->getValueType(0) == MVT::i32 ? PPC::ADDI : PPC::ADDI8;
550 CurDAG->SelectNodeTo(SN, Opc, N->getValueType(0), TFI,
551 getSmallIPtrImm(Offset, dl));
553 ReplaceNode(SN, CurDAG->getMachineNode(Opc, dl, N->getValueType(0), TFI,
554 getSmallIPtrImm(Offset, dl)));
557 bool PPCDAGToDAGISel::isRotateAndMask(SDNode *N, unsigned Mask,
558 bool isShiftMask, unsigned &SH,
559 unsigned &MB, unsigned &ME) {
560 // Don't even go down this path for i64, since different logic will be
561 // necessary for rldicl/rldicr/rldimi.
562 if (N->getValueType(0) != MVT::i32)
566 unsigned Indeterminant = ~0; // bit mask marking indeterminant results
567 unsigned Opcode = N->getOpcode();
568 if (N->getNumOperands() != 2 ||
569 !isInt32Immediate(N->getOperand(1).getNode(), Shift) || (Shift > 31))
572 if (Opcode == ISD::SHL) {
573 // apply shift left to mask if it comes first
574 if (isShiftMask) Mask = Mask << Shift;
575 // determine which bits are made indeterminant by shift
576 Indeterminant = ~(0xFFFFFFFFu << Shift);
577 } else if (Opcode == ISD::SRL) {
578 // apply shift right to mask if it comes first
579 if (isShiftMask) Mask = Mask >> Shift;
580 // determine which bits are made indeterminant by shift
581 Indeterminant = ~(0xFFFFFFFFu >> Shift);
582 // adjust for the left rotate
584 } else if (Opcode == ISD::ROTL) {
590 // if the mask doesn't intersect any Indeterminant bits
591 if (Mask && !(Mask & Indeterminant)) {
593 // make sure the mask is still a mask (wrap arounds may not be)
594 return isRunOfOnes(Mask, MB, ME);
599 bool PPCDAGToDAGISel::tryTLSXFormStore(StoreSDNode *ST) {
600 SDValue Base = ST->getBasePtr();
601 if (Base.getOpcode() != PPCISD::ADD_TLS)
603 SDValue Offset = ST->getOffset();
604 if (!Offset.isUndef())
608 EVT MemVT = ST->getMemoryVT();
609 EVT RegVT = ST->getValue().getValueType();
612 switch (MemVT.getSimpleVT().SimpleTy) {
616 Opcode = (RegVT == MVT::i32) ? PPC::STBXTLS_32 : PPC::STBXTLS;
620 Opcode = (RegVT == MVT::i32) ? PPC::STHXTLS_32 : PPC::STHXTLS;
624 Opcode = (RegVT == MVT::i32) ? PPC::STWXTLS_32 : PPC::STWXTLS;
628 Opcode = PPC::STDXTLS;
632 SDValue Chain = ST->getChain();
633 SDVTList VTs = ST->getVTList();
634 SDValue Ops[] = {ST->getValue(), Base.getOperand(0), Base.getOperand(1),
636 SDNode *MN = CurDAG->getMachineNode(Opcode, dl, VTs, Ops);
637 transferMemOperands(ST, MN);
642 bool PPCDAGToDAGISel::tryTLSXFormLoad(LoadSDNode *LD) {
643 SDValue Base = LD->getBasePtr();
644 if (Base.getOpcode() != PPCISD::ADD_TLS)
646 SDValue Offset = LD->getOffset();
647 if (!Offset.isUndef())
651 EVT MemVT = LD->getMemoryVT();
652 EVT RegVT = LD->getValueType(0);
654 switch (MemVT.getSimpleVT().SimpleTy) {
658 Opcode = (RegVT == MVT::i32) ? PPC::LBZXTLS_32 : PPC::LBZXTLS;
662 Opcode = (RegVT == MVT::i32) ? PPC::LHZXTLS_32 : PPC::LHZXTLS;
666 Opcode = (RegVT == MVT::i32) ? PPC::LWZXTLS_32 : PPC::LWZXTLS;
670 Opcode = PPC::LDXTLS;
674 SDValue Chain = LD->getChain();
675 SDVTList VTs = LD->getVTList();
676 SDValue Ops[] = {Base.getOperand(0), Base.getOperand(1), Chain};
677 SDNode *MN = CurDAG->getMachineNode(Opcode, dl, VTs, Ops);
678 transferMemOperands(LD, MN);
683 /// Turn an or of two masked values into the rotate left word immediate then
684 /// mask insert (rlwimi) instruction.
685 bool PPCDAGToDAGISel::tryBitfieldInsert(SDNode *N) {
686 SDValue Op0 = N->getOperand(0);
687 SDValue Op1 = N->getOperand(1);
690 KnownBits LKnown, RKnown;
691 CurDAG->computeKnownBits(Op0, LKnown);
692 CurDAG->computeKnownBits(Op1, RKnown);
694 unsigned TargetMask = LKnown.Zero.getZExtValue();
695 unsigned InsertMask = RKnown.Zero.getZExtValue();
697 if ((TargetMask | InsertMask) == 0xFFFFFFFF) {
698 unsigned Op0Opc = Op0.getOpcode();
699 unsigned Op1Opc = Op1.getOpcode();
700 unsigned Value, SH = 0;
701 TargetMask = ~TargetMask;
702 InsertMask = ~InsertMask;
704 // If the LHS has a foldable shift and the RHS does not, then swap it to the
705 // RHS so that we can fold the shift into the insert.
706 if (Op0Opc == ISD::AND && Op1Opc == ISD::AND) {
707 if (Op0.getOperand(0).getOpcode() == ISD::SHL ||
708 Op0.getOperand(0).getOpcode() == ISD::SRL) {
709 if (Op1.getOperand(0).getOpcode() != ISD::SHL &&
710 Op1.getOperand(0).getOpcode() != ISD::SRL) {
712 std::swap(Op0Opc, Op1Opc);
713 std::swap(TargetMask, InsertMask);
716 } else if (Op0Opc == ISD::SHL || Op0Opc == ISD::SRL) {
717 if (Op1Opc == ISD::AND && Op1.getOperand(0).getOpcode() != ISD::SHL &&
718 Op1.getOperand(0).getOpcode() != ISD::SRL) {
720 std::swap(Op0Opc, Op1Opc);
721 std::swap(TargetMask, InsertMask);
726 if (isRunOfOnes(InsertMask, MB, ME)) {
727 if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) &&
728 isInt32Immediate(Op1.getOperand(1), Value)) {
729 Op1 = Op1.getOperand(0);
730 SH = (Op1Opc == ISD::SHL) ? Value : 32 - Value;
732 if (Op1Opc == ISD::AND) {
733 // The AND mask might not be a constant, and we need to make sure that
734 // if we're going to fold the masking with the insert, all bits not
735 // know to be zero in the mask are known to be one.
737 CurDAG->computeKnownBits(Op1.getOperand(1), MKnown);
738 bool CanFoldMask = InsertMask == MKnown.One.getZExtValue();
740 unsigned SHOpc = Op1.getOperand(0).getOpcode();
741 if ((SHOpc == ISD::SHL || SHOpc == ISD::SRL) && CanFoldMask &&
742 isInt32Immediate(Op1.getOperand(0).getOperand(1), Value)) {
743 // Note that Value must be in range here (less than 32) because
744 // otherwise there would not be any bits set in InsertMask.
745 Op1 = Op1.getOperand(0).getOperand(0);
746 SH = (SHOpc == ISD::SHL) ? Value : 32 - Value;
751 SDValue Ops[] = { Op0, Op1, getI32Imm(SH, dl), getI32Imm(MB, dl),
753 ReplaceNode(N, CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops));
760 // Predict the number of instructions that would be generated by calling
762 static unsigned selectI64ImmInstrCountDirect(int64_t Imm) {
763 // Assume no remaining bits.
764 unsigned Remainder = 0;
765 // Assume no shift required.
768 // If it can't be represented as a 32 bit value.
769 if (!isInt<32>(Imm)) {
770 Shift = countTrailingZeros<uint64_t>(Imm);
771 int64_t ImmSh = static_cast<uint64_t>(Imm) >> Shift;
773 // If the shifted value fits 32 bits.
774 if (isInt<32>(ImmSh)) {
775 // Go with the shifted value.
778 // Still stuck with a 64 bit value.
785 // Intermediate operand.
788 // Handle first 32 bits.
789 unsigned Lo = Imm & 0xFFFF;
792 if (isInt<16>(Imm)) {
796 // Handle the Hi bits and Lo bits.
803 // If no shift, we're done.
804 if (!Shift) return Result;
806 // If Hi word == Lo word,
807 // we can use rldimi to insert the Lo word into Hi word.
808 if ((unsigned)(Imm & 0xFFFFFFFF) == Remainder) {
813 // Shift for next step if the upper 32-bits were not zero.
817 // Add in the last bits as required.
818 if ((Remainder >> 16) & 0xFFFF)
820 if (Remainder & 0xFFFF)
826 static uint64_t Rot64(uint64_t Imm, unsigned R) {
827 return (Imm << R) | (Imm >> (64 - R));
830 static unsigned selectI64ImmInstrCount(int64_t Imm) {
831 unsigned Count = selectI64ImmInstrCountDirect(Imm);
833 // If the instruction count is 1 or 2, we do not need further analysis
834 // since rotate + load constant requires at least 2 instructions.
838 for (unsigned r = 1; r < 63; ++r) {
839 uint64_t RImm = Rot64(Imm, r);
840 unsigned RCount = selectI64ImmInstrCountDirect(RImm) + 1;
841 Count = std::min(Count, RCount);
843 // See comments in selectI64Imm for an explanation of the logic below.
844 unsigned LS = findLastSet(RImm);
848 uint64_t OnesMask = -(int64_t) (UINT64_C(1) << (LS+1));
849 uint64_t RImmWithOnes = RImm | OnesMask;
851 RCount = selectI64ImmInstrCountDirect(RImmWithOnes) + 1;
852 Count = std::min(Count, RCount);
858 // Select a 64-bit constant. For cost-modeling purposes, selectI64ImmInstrCount
859 // (above) needs to be kept in sync with this function.
860 static SDNode *selectI64ImmDirect(SelectionDAG *CurDAG, const SDLoc &dl,
862 // Assume no remaining bits.
863 unsigned Remainder = 0;
864 // Assume no shift required.
867 // If it can't be represented as a 32 bit value.
868 if (!isInt<32>(Imm)) {
869 Shift = countTrailingZeros<uint64_t>(Imm);
870 int64_t ImmSh = static_cast<uint64_t>(Imm) >> Shift;
872 // If the shifted value fits 32 bits.
873 if (isInt<32>(ImmSh)) {
874 // Go with the shifted value.
877 // Still stuck with a 64 bit value.
884 // Intermediate operand.
887 // Handle first 32 bits.
888 unsigned Lo = Imm & 0xFFFF;
889 unsigned Hi = (Imm >> 16) & 0xFFFF;
891 auto getI32Imm = [CurDAG, dl](unsigned Imm) {
892 return CurDAG->getTargetConstant(Imm, dl, MVT::i32);
896 if (isInt<16>(Imm)) {
897 uint64_t SextImm = SignExtend64(Lo, 16);
898 SDValue SDImm = CurDAG->getTargetConstant(SextImm, dl, MVT::i64);
900 Result = CurDAG->getMachineNode(PPC::LI8, dl, MVT::i64, SDImm);
902 // Handle the Hi bits.
903 unsigned OpC = Hi ? PPC::LIS8 : PPC::LI8;
904 Result = CurDAG->getMachineNode(OpC, dl, MVT::i64, getI32Imm(Hi));
906 Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64,
907 SDValue(Result, 0), getI32Imm(Lo));
910 Result = CurDAG->getMachineNode(PPC::LIS8, dl, MVT::i64, getI32Imm(Hi));
913 // If no shift, we're done.
914 if (!Shift) return Result;
916 // If Hi word == Lo word,
917 // we can use rldimi to insert the Lo word into Hi word.
918 if ((unsigned)(Imm & 0xFFFFFFFF) == Remainder) {
920 { SDValue(Result, 0), SDValue(Result, 0), getI32Imm(Shift), getI32Imm(0)};
921 return CurDAG->getMachineNode(PPC::RLDIMI, dl, MVT::i64, Ops);
924 // Shift for next step if the upper 32-bits were not zero.
926 Result = CurDAG->getMachineNode(PPC::RLDICR, dl, MVT::i64,
929 getI32Imm(63 - Shift));
932 // Add in the last bits as required.
933 if ((Hi = (Remainder >> 16) & 0xFFFF)) {
934 Result = CurDAG->getMachineNode(PPC::ORIS8, dl, MVT::i64,
935 SDValue(Result, 0), getI32Imm(Hi));
937 if ((Lo = Remainder & 0xFFFF)) {
938 Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64,
939 SDValue(Result, 0), getI32Imm(Lo));
945 static SDNode *selectI64Imm(SelectionDAG *CurDAG, const SDLoc &dl,
947 unsigned Count = selectI64ImmInstrCountDirect(Imm);
949 // If the instruction count is 1 or 2, we do not need further analysis
950 // since rotate + load constant requires at least 2 instructions.
952 return selectI64ImmDirect(CurDAG, dl, Imm);
959 for (unsigned r = 1; r < 63; ++r) {
960 uint64_t RImm = Rot64(Imm, r);
961 unsigned RCount = selectI64ImmInstrCountDirect(RImm) + 1;
962 if (RCount < Count) {
969 // If the immediate to generate has many trailing zeros, it might be
970 // worthwhile to generate a rotated value with too many leading ones
971 // (because that's free with li/lis's sign-extension semantics), and then
972 // mask them off after rotation.
974 unsigned LS = findLastSet(RImm);
975 // We're adding (63-LS) higher-order ones, and we expect to mask them off
976 // after performing the inverse rotation by (64-r). So we need that:
977 // 63-LS == 64-r => LS == r-1
981 uint64_t OnesMask = -(int64_t) (UINT64_C(1) << (LS+1));
982 uint64_t RImmWithOnes = RImm | OnesMask;
984 RCount = selectI64ImmInstrCountDirect(RImmWithOnes) + 1;
985 if (RCount < Count) {
988 MatImm = RImmWithOnes;
994 return selectI64ImmDirect(CurDAG, dl, Imm);
996 auto getI32Imm = [CurDAG, dl](unsigned Imm) {
997 return CurDAG->getTargetConstant(Imm, dl, MVT::i32);
1000 SDValue Val = SDValue(selectI64ImmDirect(CurDAG, dl, MatImm), 0);
1001 return CurDAG->getMachineNode(PPC::RLDICR, dl, MVT::i64, Val,
1002 getI32Imm(64 - RMin), getI32Imm(MaskEnd));
1005 static unsigned allUsesTruncate(SelectionDAG *CurDAG, SDNode *N) {
1006 unsigned MaxTruncation = 0;
1007 // Cannot use range-based for loop here as we need the actual use (i.e. we
1008 // need the operand number corresponding to the use). A range-based for
1009 // will unbox the use and provide an SDNode*.
1010 for (SDNode::use_iterator Use = N->use_begin(), UseEnd = N->use_end();
1011 Use != UseEnd; ++Use) {
1013 Use->isMachineOpcode() ? Use->getMachineOpcode() : Use->getOpcode();
1017 if (Use->isMachineOpcode())
1020 std::max(MaxTruncation, Use->getValueType(0).getSizeInBits());
1023 if (Use->isMachineOpcode())
1025 StoreSDNode *STN = cast<StoreSDNode>(*Use);
1026 unsigned MemVTSize = STN->getMemoryVT().getSizeInBits();
1027 if (MemVTSize == 64 || Use.getOperandNo() != 0)
1029 MaxTruncation = std::max(MaxTruncation, MemVTSize);
1036 if (Use.getOperandNo() != 0)
1038 MaxTruncation = std::max(MaxTruncation, 32u);
1044 if (Use.getOperandNo() != 0)
1046 MaxTruncation = std::max(MaxTruncation, 16u);
1052 if (Use.getOperandNo() != 0)
1054 MaxTruncation = std::max(MaxTruncation, 8u);
1058 return MaxTruncation;
1061 // Select a 64-bit constant.
1062 static SDNode *selectI64Imm(SelectionDAG *CurDAG, SDNode *N) {
1065 // Get 64 bit value.
1066 int64_t Imm = cast<ConstantSDNode>(N)->getZExtValue();
1067 if (unsigned MinSize = allUsesTruncate(CurDAG, N)) {
1068 uint64_t SextImm = SignExtend64(Imm, MinSize);
1069 SDValue SDImm = CurDAG->getTargetConstant(SextImm, dl, MVT::i64);
1070 if (isInt<16>(SextImm))
1071 return CurDAG->getMachineNode(PPC::LI8, dl, MVT::i64, SDImm);
1073 return selectI64Imm(CurDAG, dl, Imm);
1078 class BitPermutationSelector {
1082 // The bit number in the value, using a convention where bit 0 is the
1083 // lowest-order bit.
1091 ValueBit(SDValue V, unsigned I, Kind K = Variable)
1092 : V(V), Idx(I), K(K) {}
1093 ValueBit(Kind K = Variable)
1094 : V(SDValue(nullptr, 0)), Idx(UINT32_MAX), K(K) {}
1096 bool isZero() const {
1097 return K == ConstZero;
1100 bool hasValue() const {
1101 return K == Variable;
1104 SDValue getValue() const {
1105 assert(hasValue() && "Cannot get the value of a constant bit");
1109 unsigned getValueBitIndex() const {
1110 assert(hasValue() && "Cannot get the value bit index of a constant bit");
1115 // A bit group has the same underlying value and the same rotate factor.
1119 unsigned StartIdx, EndIdx;
1121 // This rotation amount assumes that the lower 32 bits of the quantity are
1122 // replicated in the high 32 bits by the rotation operator (which is done
1123 // by rlwinm and friends in 64-bit mode).
1125 // Did converting to Repl32 == true change the rotation factor? If it did,
1126 // it decreased it by 32.
1128 // Was this group coalesced after setting Repl32 to true?
1129 bool Repl32Coalesced;
1131 BitGroup(SDValue V, unsigned R, unsigned S, unsigned E)
1132 : V(V), RLAmt(R), StartIdx(S), EndIdx(E), Repl32(false), Repl32CR(false),
1133 Repl32Coalesced(false) {
1134 LLVM_DEBUG(dbgs() << "\tbit group for " << V.getNode() << " RLAmt = " << R
1135 << " [" << S << ", " << E << "]\n");
1139 // Information on each (Value, RLAmt) pair (like the number of groups
1140 // associated with each) used to choose the lowering method.
1141 struct ValueRotInfo {
1143 unsigned RLAmt = std::numeric_limits<unsigned>::max();
1144 unsigned NumGroups = 0;
1145 unsigned FirstGroupStartIdx = std::numeric_limits<unsigned>::max();
1146 bool Repl32 = false;
1148 ValueRotInfo() = default;
1150 // For sorting (in reverse order) by NumGroups, and then by
1151 // FirstGroupStartIdx.
1152 bool operator < (const ValueRotInfo &Other) const {
1153 // We need to sort so that the non-Repl32 come first because, when we're
1154 // doing masking, the Repl32 bit groups might be subsumed into the 64-bit
1155 // masking operation.
1156 if (Repl32 < Other.Repl32)
1158 else if (Repl32 > Other.Repl32)
1160 else if (NumGroups > Other.NumGroups)
1162 else if (NumGroups < Other.NumGroups)
1164 else if (RLAmt == 0 && Other.RLAmt != 0)
1166 else if (RLAmt != 0 && Other.RLAmt == 0)
1168 else if (FirstGroupStartIdx < Other.FirstGroupStartIdx)
1174 using ValueBitsMemoizedValue = std::pair<bool, SmallVector<ValueBit, 64>>;
1175 using ValueBitsMemoizer =
1176 DenseMap<SDValue, std::unique_ptr<ValueBitsMemoizedValue>>;
1177 ValueBitsMemoizer Memoizer;
1179 // Return a pair of bool and a SmallVector pointer to a memoization entry.
1180 // The bool is true if something interesting was deduced, otherwise if we're
1181 // providing only a generic representation of V (or something else likewise
1182 // uninteresting for instruction selection) through the SmallVector.
1183 std::pair<bool, SmallVector<ValueBit, 64> *> getValueBits(SDValue V,
1185 auto &ValueEntry = Memoizer[V];
1187 return std::make_pair(ValueEntry->first, &ValueEntry->second);
1188 ValueEntry.reset(new ValueBitsMemoizedValue());
1189 bool &Interesting = ValueEntry->first;
1190 SmallVector<ValueBit, 64> &Bits = ValueEntry->second;
1191 Bits.resize(NumBits);
1193 switch (V.getOpcode()) {
1196 if (isa<ConstantSDNode>(V.getOperand(1))) {
1197 unsigned RotAmt = V.getConstantOperandVal(1);
1199 const auto &LHSBits = *getValueBits(V.getOperand(0), NumBits).second;
1201 for (unsigned i = 0; i < NumBits; ++i)
1202 Bits[i] = LHSBits[i < RotAmt ? i + (NumBits - RotAmt) : i - RotAmt];
1204 return std::make_pair(Interesting = true, &Bits);
1208 if (isa<ConstantSDNode>(V.getOperand(1))) {
1209 unsigned ShiftAmt = V.getConstantOperandVal(1);
1211 const auto &LHSBits = *getValueBits(V.getOperand(0), NumBits).second;
1213 for (unsigned i = ShiftAmt; i < NumBits; ++i)
1214 Bits[i] = LHSBits[i - ShiftAmt];
1216 for (unsigned i = 0; i < ShiftAmt; ++i)
1217 Bits[i] = ValueBit(ValueBit::ConstZero);
1219 return std::make_pair(Interesting = true, &Bits);
1223 if (isa<ConstantSDNode>(V.getOperand(1))) {
1224 unsigned ShiftAmt = V.getConstantOperandVal(1);
1226 const auto &LHSBits = *getValueBits(V.getOperand(0), NumBits).second;
1228 for (unsigned i = 0; i < NumBits - ShiftAmt; ++i)
1229 Bits[i] = LHSBits[i + ShiftAmt];
1231 for (unsigned i = NumBits - ShiftAmt; i < NumBits; ++i)
1232 Bits[i] = ValueBit(ValueBit::ConstZero);
1234 return std::make_pair(Interesting = true, &Bits);
1238 if (isa<ConstantSDNode>(V.getOperand(1))) {
1239 uint64_t Mask = V.getConstantOperandVal(1);
1241 const SmallVector<ValueBit, 64> *LHSBits;
1242 // Mark this as interesting, only if the LHS was also interesting. This
1243 // prevents the overall procedure from matching a single immediate 'and'
1244 // (which is non-optimal because such an and might be folded with other
1245 // things if we don't select it here).
1246 std::tie(Interesting, LHSBits) = getValueBits(V.getOperand(0), NumBits);
1248 for (unsigned i = 0; i < NumBits; ++i)
1249 if (((Mask >> i) & 1) == 1)
1250 Bits[i] = (*LHSBits)[i];
1252 Bits[i] = ValueBit(ValueBit::ConstZero);
1254 return std::make_pair(Interesting, &Bits);
1258 const auto &LHSBits = *getValueBits(V.getOperand(0), NumBits).second;
1259 const auto &RHSBits = *getValueBits(V.getOperand(1), NumBits).second;
1261 bool AllDisjoint = true;
1262 for (unsigned i = 0; i < NumBits; ++i)
1263 if (LHSBits[i].isZero())
1264 Bits[i] = RHSBits[i];
1265 else if (RHSBits[i].isZero())
1266 Bits[i] = LHSBits[i];
1268 AllDisjoint = false;
1275 return std::make_pair(Interesting = true, &Bits);
1277 case ISD::ZERO_EXTEND: {
1278 // We support only the case with zero extension from i32 to i64 so far.
1279 if (V.getValueType() != MVT::i64 ||
1280 V.getOperand(0).getValueType() != MVT::i32)
1283 const SmallVector<ValueBit, 64> *LHSBits;
1284 const unsigned NumOperandBits = 32;
1285 std::tie(Interesting, LHSBits) = getValueBits(V.getOperand(0),
1288 for (unsigned i = 0; i < NumOperandBits; ++i)
1289 Bits[i] = (*LHSBits)[i];
1291 for (unsigned i = NumOperandBits; i < NumBits; ++i)
1292 Bits[i] = ValueBit(ValueBit::ConstZero);
1294 return std::make_pair(Interesting, &Bits);
1298 for (unsigned i = 0; i < NumBits; ++i)
1299 Bits[i] = ValueBit(V, i);
1301 return std::make_pair(Interesting = false, &Bits);
1304 // For each value (except the constant ones), compute the left-rotate amount
1305 // to get it from its original to final position.
1306 void computeRotationAmounts() {
1308 RLAmt.resize(Bits.size());
1309 for (unsigned i = 0; i < Bits.size(); ++i)
1310 if (Bits[i].hasValue()) {
1311 unsigned VBI = Bits[i].getValueBitIndex();
1315 RLAmt[i] = Bits.size() - (VBI - i);
1316 } else if (Bits[i].isZero()) {
1318 RLAmt[i] = UINT32_MAX;
1320 llvm_unreachable("Unknown value bit type");
1324 // Collect groups of consecutive bits with the same underlying value and
1325 // rotation factor. If we're doing late masking, we ignore zeros, otherwise
1326 // they break up groups.
1327 void collectBitGroups(bool LateMask) {
1330 unsigned LastRLAmt = RLAmt[0];
1331 SDValue LastValue = Bits[0].hasValue() ? Bits[0].getValue() : SDValue();
1332 unsigned LastGroupStartIdx = 0;
1333 for (unsigned i = 1; i < Bits.size(); ++i) {
1334 unsigned ThisRLAmt = RLAmt[i];
1335 SDValue ThisValue = Bits[i].hasValue() ? Bits[i].getValue() : SDValue();
1336 if (LateMask && !ThisValue) {
1337 ThisValue = LastValue;
1338 ThisRLAmt = LastRLAmt;
1339 // If we're doing late masking, then the first bit group always starts
1340 // at zero (even if the first bits were zero).
1341 if (BitGroups.empty())
1342 LastGroupStartIdx = 0;
1345 // If this bit has the same underlying value and the same rotate factor as
1346 // the last one, then they're part of the same group.
1347 if (ThisRLAmt == LastRLAmt && ThisValue == LastValue)
1350 if (LastValue.getNode())
1351 BitGroups.push_back(BitGroup(LastValue, LastRLAmt, LastGroupStartIdx,
1353 LastRLAmt = ThisRLAmt;
1354 LastValue = ThisValue;
1355 LastGroupStartIdx = i;
1357 if (LastValue.getNode())
1358 BitGroups.push_back(BitGroup(LastValue, LastRLAmt, LastGroupStartIdx,
1361 if (BitGroups.empty())
1364 // We might be able to combine the first and last groups.
1365 if (BitGroups.size() > 1) {
1366 // If the first and last groups are the same, then remove the first group
1367 // in favor of the last group, making the ending index of the last group
1368 // equal to the ending index of the to-be-removed first group.
1369 if (BitGroups[0].StartIdx == 0 &&
1370 BitGroups[BitGroups.size()-1].EndIdx == Bits.size()-1 &&
1371 BitGroups[0].V == BitGroups[BitGroups.size()-1].V &&
1372 BitGroups[0].RLAmt == BitGroups[BitGroups.size()-1].RLAmt) {
1373 LLVM_DEBUG(dbgs() << "\tcombining final bit group with initial one\n");
1374 BitGroups[BitGroups.size()-1].EndIdx = BitGroups[0].EndIdx;
1375 BitGroups.erase(BitGroups.begin());
1380 // Take all (SDValue, RLAmt) pairs and sort them by the number of groups
1381 // associated with each. If the number of groups are same, we prefer a group
1382 // which does not require rotate, i.e. RLAmt is 0, to avoid the first rotate
1383 // instruction. If there is a degeneracy, pick the one that occurs
1384 // first (in the final value).
1385 void collectValueRotInfo() {
1388 for (auto &BG : BitGroups) {
1389 unsigned RLAmtKey = BG.RLAmt + (BG.Repl32 ? 64 : 0);
1390 ValueRotInfo &VRI = ValueRots[std::make_pair(BG.V, RLAmtKey)];
1392 VRI.RLAmt = BG.RLAmt;
1393 VRI.Repl32 = BG.Repl32;
1395 VRI.FirstGroupStartIdx = std::min(VRI.FirstGroupStartIdx, BG.StartIdx);
1398 // Now that we've collected the various ValueRotInfo instances, we need to
1400 ValueRotsVec.clear();
1401 for (auto &I : ValueRots) {
1402 ValueRotsVec.push_back(I.second);
1404 llvm::sort(ValueRotsVec.begin(), ValueRotsVec.end());
1407 // In 64-bit mode, rlwinm and friends have a rotation operator that
1408 // replicates the low-order 32 bits into the high-order 32-bits. The mask
1409 // indices of these instructions can only be in the lower 32 bits, so they
1410 // can only represent some 64-bit bit groups. However, when they can be used,
1411 // the 32-bit replication can be used to represent, as a single bit group,
1412 // otherwise separate bit groups. We'll convert to replicated-32-bit bit
1413 // groups when possible. Returns true if any of the bit groups were
1415 void assignRepl32BitGroups() {
1416 // If we have bits like this:
1418 // Indices: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1419 // V bits: ... 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24
1420 // Groups: | RLAmt = 8 | RLAmt = 40 |
1422 // But, making use of a 32-bit operation that replicates the low-order 32
1423 // bits into the high-order 32 bits, this can be one bit group with a RLAmt
1426 auto IsAllLow32 = [this](BitGroup & BG) {
1427 if (BG.StartIdx <= BG.EndIdx) {
1428 for (unsigned i = BG.StartIdx; i <= BG.EndIdx; ++i) {
1429 if (!Bits[i].hasValue())
1431 if (Bits[i].getValueBitIndex() >= 32)
1435 for (unsigned i = BG.StartIdx; i < Bits.size(); ++i) {
1436 if (!Bits[i].hasValue())
1438 if (Bits[i].getValueBitIndex() >= 32)
1441 for (unsigned i = 0; i <= BG.EndIdx; ++i) {
1442 if (!Bits[i].hasValue())
1444 if (Bits[i].getValueBitIndex() >= 32)
1452 for (auto &BG : BitGroups) {
1453 // If this bit group has RLAmt of 0 and will not be merged with
1454 // another bit group, we don't benefit from Repl32. We don't mark
1455 // such group to give more freedom for later instruction selection.
1456 if (BG.RLAmt == 0) {
1457 auto PotentiallyMerged = [this](BitGroup & BG) {
1458 for (auto &BG2 : BitGroups)
1459 if (&BG != &BG2 && BG.V == BG2.V &&
1460 (BG2.RLAmt == 0 || BG2.RLAmt == 32))
1464 if (!PotentiallyMerged(BG))
1467 if (BG.StartIdx < 32 && BG.EndIdx < 32) {
1468 if (IsAllLow32(BG)) {
1469 if (BG.RLAmt >= 32) {
1476 LLVM_DEBUG(dbgs() << "\t32-bit replicated bit group for "
1477 << BG.V.getNode() << " RLAmt = " << BG.RLAmt << " ["
1478 << BG.StartIdx << ", " << BG.EndIdx << "]\n");
1483 // Now walk through the bit groups, consolidating where possible.
1484 for (auto I = BitGroups.begin(); I != BitGroups.end();) {
1485 // We might want to remove this bit group by merging it with the previous
1486 // group (which might be the ending group).
1487 auto IP = (I == BitGroups.begin()) ?
1488 std::prev(BitGroups.end()) : std::prev(I);
1489 if (I->Repl32 && IP->Repl32 && I->V == IP->V && I->RLAmt == IP->RLAmt &&
1490 I->StartIdx == (IP->EndIdx + 1) % 64 && I != IP) {
1492 LLVM_DEBUG(dbgs() << "\tcombining 32-bit replicated bit group for "
1493 << I->V.getNode() << " RLAmt = " << I->RLAmt << " ["
1494 << I->StartIdx << ", " << I->EndIdx
1495 << "] with group with range [" << IP->StartIdx << ", "
1496 << IP->EndIdx << "]\n");
1498 IP->EndIdx = I->EndIdx;
1499 IP->Repl32CR = IP->Repl32CR || I->Repl32CR;
1500 IP->Repl32Coalesced = true;
1501 I = BitGroups.erase(I);
1504 // There is a special case worth handling: If there is a single group
1505 // covering the entire upper 32 bits, and it can be merged with both
1506 // the next and previous groups (which might be the same group), then
1507 // do so. If it is the same group (so there will be only one group in
1508 // total), then we need to reverse the order of the range so that it
1509 // covers the entire 64 bits.
1510 if (I->StartIdx == 32 && I->EndIdx == 63) {
1511 assert(std::next(I) == BitGroups.end() &&
1512 "bit group ends at index 63 but there is another?");
1513 auto IN = BitGroups.begin();
1515 if (IP->Repl32 && IN->Repl32 && I->V == IP->V && I->V == IN->V &&
1516 (I->RLAmt % 32) == IP->RLAmt && (I->RLAmt % 32) == IN->RLAmt &&
1517 IP->EndIdx == 31 && IN->StartIdx == 0 && I != IP &&
1520 LLVM_DEBUG(dbgs() << "\tcombining bit group for " << I->V.getNode()
1521 << " RLAmt = " << I->RLAmt << " [" << I->StartIdx
1522 << ", " << I->EndIdx
1523 << "] with 32-bit replicated groups with ranges ["
1524 << IP->StartIdx << ", " << IP->EndIdx << "] and ["
1525 << IN->StartIdx << ", " << IN->EndIdx << "]\n");
1528 // There is only one other group; change it to cover the whole
1529 // range (backward, so that it can still be Repl32 but cover the
1530 // whole 64-bit range).
1533 IP->Repl32CR = IP->Repl32CR || I->RLAmt >= 32;
1534 IP->Repl32Coalesced = true;
1535 I = BitGroups.erase(I);
1537 // There are two separate groups, one before this group and one
1538 // after us (at the beginning). We're going to remove this group,
1539 // but also the group at the very beginning.
1540 IP->EndIdx = IN->EndIdx;
1541 IP->Repl32CR = IP->Repl32CR || IN->Repl32CR || I->RLAmt >= 32;
1542 IP->Repl32Coalesced = true;
1543 I = BitGroups.erase(I);
1544 BitGroups.erase(BitGroups.begin());
1547 // This must be the last group in the vector (and we might have
1548 // just invalidated the iterator above), so break here.
1558 SDValue getI32Imm(unsigned Imm, const SDLoc &dl) {
1559 return CurDAG->getTargetConstant(Imm, dl, MVT::i32);
1562 uint64_t getZerosMask() {
1564 for (unsigned i = 0; i < Bits.size(); ++i) {
1565 if (Bits[i].hasValue())
1567 Mask |= (UINT64_C(1) << i);
1573 // This method extends an input value to 64 bit if input is 32-bit integer.
1574 // While selecting instructions in BitPermutationSelector in 64-bit mode,
1575 // an input value can be a 32-bit integer if a ZERO_EXTEND node is included.
1576 // In such case, we extend it to 64 bit to be consistent with other values.
1577 SDValue ExtendToInt64(SDValue V, const SDLoc &dl) {
1578 if (V.getValueSizeInBits() == 64)
1581 assert(V.getValueSizeInBits() == 32);
1582 SDValue SubRegIdx = CurDAG->getTargetConstant(PPC::sub_32, dl, MVT::i32);
1583 SDValue ImDef = SDValue(CurDAG->getMachineNode(PPC::IMPLICIT_DEF, dl,
1585 SDValue ExtVal = SDValue(CurDAG->getMachineNode(PPC::INSERT_SUBREG, dl,
1591 // Depending on the number of groups for a particular value, it might be
1592 // better to rotate, mask explicitly (using andi/andis), and then or the
1593 // result. Select this part of the result first.
1594 void SelectAndParts32(const SDLoc &dl, SDValue &Res, unsigned *InstCnt) {
1595 if (BPermRewriterNoMasking)
1598 for (ValueRotInfo &VRI : ValueRotsVec) {
1600 for (unsigned i = 0; i < Bits.size(); ++i) {
1601 if (!Bits[i].hasValue() || Bits[i].getValue() != VRI.V)
1603 if (RLAmt[i] != VRI.RLAmt)
1608 // Compute the masks for andi/andis that would be necessary.
1609 unsigned ANDIMask = (Mask & UINT16_MAX), ANDISMask = Mask >> 16;
1610 assert((ANDIMask != 0 || ANDISMask != 0) &&
1611 "No set bits in mask for value bit groups");
1612 bool NeedsRotate = VRI.RLAmt != 0;
1614 // We're trying to minimize the number of instructions. If we have one
1615 // group, using one of andi/andis can break even. If we have three
1616 // groups, we can use both andi and andis and break even (to use both
1617 // andi and andis we also need to or the results together). We need four
1618 // groups if we also need to rotate. To use andi/andis we need to do more
1619 // than break even because rotate-and-mask instructions tend to be easier
1622 // FIXME: We've biased here against using andi/andis, which is right for
1623 // POWER cores, but not optimal everywhere. For example, on the A2,
1624 // andi/andis have single-cycle latency whereas the rotate-and-mask
1625 // instructions take two cycles, and it would be better to bias toward
1626 // andi/andis in break-even cases.
1628 unsigned NumAndInsts = (unsigned) NeedsRotate +
1629 (unsigned) (ANDIMask != 0) +
1630 (unsigned) (ANDISMask != 0) +
1631 (unsigned) (ANDIMask != 0 && ANDISMask != 0) +
1632 (unsigned) (bool) Res;
1634 LLVM_DEBUG(dbgs() << "\t\trotation groups for " << VRI.V.getNode()
1635 << " RL: " << VRI.RLAmt << ":"
1636 << "\n\t\t\tisel using masking: " << NumAndInsts
1637 << " using rotates: " << VRI.NumGroups << "\n");
1639 if (NumAndInsts >= VRI.NumGroups)
1642 LLVM_DEBUG(dbgs() << "\t\t\t\tusing masking\n");
1644 if (InstCnt) *InstCnt += NumAndInsts;
1649 { VRI.V, getI32Imm(VRI.RLAmt, dl), getI32Imm(0, dl),
1650 getI32Imm(31, dl) };
1651 VRot = SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32,
1657 SDValue ANDIVal, ANDISVal;
1659 ANDIVal = SDValue(CurDAG->getMachineNode(PPC::ANDIo, dl, MVT::i32,
1660 VRot, getI32Imm(ANDIMask, dl)), 0);
1662 ANDISVal = SDValue(CurDAG->getMachineNode(PPC::ANDISo, dl, MVT::i32,
1663 VRot, getI32Imm(ANDISMask, dl)), 0);
1667 TotalVal = ANDISVal;
1671 TotalVal = SDValue(CurDAG->getMachineNode(PPC::OR, dl, MVT::i32,
1672 ANDIVal, ANDISVal), 0);
1677 Res = SDValue(CurDAG->getMachineNode(PPC::OR, dl, MVT::i32,
1680 // Now, remove all groups with this underlying value and rotation
1682 eraseMatchingBitGroups([VRI](const BitGroup &BG) {
1683 return BG.V == VRI.V && BG.RLAmt == VRI.RLAmt;
1688 // Instruction selection for the 32-bit case.
1689 SDNode *Select32(SDNode *N, bool LateMask, unsigned *InstCnt) {
1693 if (InstCnt) *InstCnt = 0;
1695 // Take care of cases that should use andi/andis first.
1696 SelectAndParts32(dl, Res, InstCnt);
1698 // If we've not yet selected a 'starting' instruction, and we have no zeros
1699 // to fill in, select the (Value, RLAmt) with the highest priority (largest
1700 // number of groups), and start with this rotated value.
1701 if ((!HasZeros || LateMask) && !Res) {
1702 ValueRotInfo &VRI = ValueRotsVec[0];
1704 if (InstCnt) *InstCnt += 1;
1706 { VRI.V, getI32Imm(VRI.RLAmt, dl), getI32Imm(0, dl),
1707 getI32Imm(31, dl) };
1708 Res = SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops),
1714 // Now, remove all groups with this underlying value and rotation factor.
1715 eraseMatchingBitGroups([VRI](const BitGroup &BG) {
1716 return BG.V == VRI.V && BG.RLAmt == VRI.RLAmt;
1720 if (InstCnt) *InstCnt += BitGroups.size();
1722 // Insert the other groups (one at a time).
1723 for (auto &BG : BitGroups) {
1726 { BG.V, getI32Imm(BG.RLAmt, dl),
1727 getI32Imm(Bits.size() - BG.EndIdx - 1, dl),
1728 getI32Imm(Bits.size() - BG.StartIdx - 1, dl) };
1729 Res = SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops), 0);
1732 { Res, BG.V, getI32Imm(BG.RLAmt, dl),
1733 getI32Imm(Bits.size() - BG.EndIdx - 1, dl),
1734 getI32Imm(Bits.size() - BG.StartIdx - 1, dl) };
1735 Res = SDValue(CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops), 0);
1740 unsigned Mask = (unsigned) getZerosMask();
1742 unsigned ANDIMask = (Mask & UINT16_MAX), ANDISMask = Mask >> 16;
1743 assert((ANDIMask != 0 || ANDISMask != 0) &&
1744 "No set bits in zeros mask?");
1746 if (InstCnt) *InstCnt += (unsigned) (ANDIMask != 0) +
1747 (unsigned) (ANDISMask != 0) +
1748 (unsigned) (ANDIMask != 0 && ANDISMask != 0);
1750 SDValue ANDIVal, ANDISVal;
1752 ANDIVal = SDValue(CurDAG->getMachineNode(PPC::ANDIo, dl, MVT::i32,
1753 Res, getI32Imm(ANDIMask, dl)), 0);
1755 ANDISVal = SDValue(CurDAG->getMachineNode(PPC::ANDISo, dl, MVT::i32,
1756 Res, getI32Imm(ANDISMask, dl)), 0);
1763 Res = SDValue(CurDAG->getMachineNode(PPC::OR, dl, MVT::i32,
1764 ANDIVal, ANDISVal), 0);
1767 return Res.getNode();
1770 unsigned SelectRotMask64Count(unsigned RLAmt, bool Repl32,
1771 unsigned MaskStart, unsigned MaskEnd,
1773 // In the notation used by the instructions, 'start' and 'end' are reversed
1774 // because bits are counted from high to low order.
1775 unsigned InstMaskStart = 64 - MaskEnd - 1,
1776 InstMaskEnd = 64 - MaskStart - 1;
1781 if ((!IsIns && (InstMaskEnd == 63 || InstMaskStart == 0)) ||
1782 InstMaskEnd == 63 - RLAmt)
1788 // For 64-bit values, not all combinations of rotates and masks are
1789 // available. Produce one if it is available.
1790 SDValue SelectRotMask64(SDValue V, const SDLoc &dl, unsigned RLAmt,
1791 bool Repl32, unsigned MaskStart, unsigned MaskEnd,
1792 unsigned *InstCnt = nullptr) {
1793 // In the notation used by the instructions, 'start' and 'end' are reversed
1794 // because bits are counted from high to low order.
1795 unsigned InstMaskStart = 64 - MaskEnd - 1,
1796 InstMaskEnd = 64 - MaskStart - 1;
1798 if (InstCnt) *InstCnt += 1;
1801 // This rotation amount assumes that the lower 32 bits of the quantity
1802 // are replicated in the high 32 bits by the rotation operator (which is
1803 // done by rlwinm and friends).
1804 assert(InstMaskStart >= 32 && "Mask cannot start out of range");
1805 assert(InstMaskEnd >= 32 && "Mask cannot end out of range");
1807 { ExtendToInt64(V, dl), getI32Imm(RLAmt, dl),
1808 getI32Imm(InstMaskStart - 32, dl), getI32Imm(InstMaskEnd - 32, dl) };
1809 return SDValue(CurDAG->getMachineNode(PPC::RLWINM8, dl, MVT::i64,
1813 if (InstMaskEnd == 63) {
1815 { ExtendToInt64(V, dl), getI32Imm(RLAmt, dl),
1816 getI32Imm(InstMaskStart, dl) };
1817 return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, Ops), 0);
1820 if (InstMaskStart == 0) {
1822 { ExtendToInt64(V, dl), getI32Imm(RLAmt, dl),
1823 getI32Imm(InstMaskEnd, dl) };
1824 return SDValue(CurDAG->getMachineNode(PPC::RLDICR, dl, MVT::i64, Ops), 0);
1827 if (InstMaskEnd == 63 - RLAmt) {
1829 { ExtendToInt64(V, dl), getI32Imm(RLAmt, dl),
1830 getI32Imm(InstMaskStart, dl) };
1831 return SDValue(CurDAG->getMachineNode(PPC::RLDIC, dl, MVT::i64, Ops), 0);
1834 // We cannot do this with a single instruction, so we'll use two. The
1835 // problem is that we're not free to choose both a rotation amount and mask
1836 // start and end independently. We can choose an arbitrary mask start and
1837 // end, but then the rotation amount is fixed. Rotation, however, can be
1838 // inverted, and so by applying an "inverse" rotation first, we can get the
1840 if (InstCnt) *InstCnt += 1;
1842 // The rotation mask for the second instruction must be MaskStart.
1843 unsigned RLAmt2 = MaskStart;
1844 // The first instruction must rotate V so that the overall rotation amount
1846 unsigned RLAmt1 = (64 + RLAmt - RLAmt2) % 64;
1848 V = SelectRotMask64(V, dl, RLAmt1, false, 0, 63);
1849 return SelectRotMask64(V, dl, RLAmt2, false, MaskStart, MaskEnd);
1852 // For 64-bit values, not all combinations of rotates and masks are
1853 // available. Produce a rotate-mask-and-insert if one is available.
1854 SDValue SelectRotMaskIns64(SDValue Base, SDValue V, const SDLoc &dl,
1855 unsigned RLAmt, bool Repl32, unsigned MaskStart,
1856 unsigned MaskEnd, unsigned *InstCnt = nullptr) {
1857 // In the notation used by the instructions, 'start' and 'end' are reversed
1858 // because bits are counted from high to low order.
1859 unsigned InstMaskStart = 64 - MaskEnd - 1,
1860 InstMaskEnd = 64 - MaskStart - 1;
1862 if (InstCnt) *InstCnt += 1;
1865 // This rotation amount assumes that the lower 32 bits of the quantity
1866 // are replicated in the high 32 bits by the rotation operator (which is
1867 // done by rlwinm and friends).
1868 assert(InstMaskStart >= 32 && "Mask cannot start out of range");
1869 assert(InstMaskEnd >= 32 && "Mask cannot end out of range");
1871 { ExtendToInt64(Base, dl), ExtendToInt64(V, dl), getI32Imm(RLAmt, dl),
1872 getI32Imm(InstMaskStart - 32, dl), getI32Imm(InstMaskEnd - 32, dl) };
1873 return SDValue(CurDAG->getMachineNode(PPC::RLWIMI8, dl, MVT::i64,
1877 if (InstMaskEnd == 63 - RLAmt) {
1879 { ExtendToInt64(Base, dl), ExtendToInt64(V, dl), getI32Imm(RLAmt, dl),
1880 getI32Imm(InstMaskStart, dl) };
1881 return SDValue(CurDAG->getMachineNode(PPC::RLDIMI, dl, MVT::i64, Ops), 0);
1884 // We cannot do this with a single instruction, so we'll use two. The
1885 // problem is that we're not free to choose both a rotation amount and mask
1886 // start and end independently. We can choose an arbitrary mask start and
1887 // end, but then the rotation amount is fixed. Rotation, however, can be
1888 // inverted, and so by applying an "inverse" rotation first, we can get the
1890 if (InstCnt) *InstCnt += 1;
1892 // The rotation mask for the second instruction must be MaskStart.
1893 unsigned RLAmt2 = MaskStart;
1894 // The first instruction must rotate V so that the overall rotation amount
1896 unsigned RLAmt1 = (64 + RLAmt - RLAmt2) % 64;
1898 V = SelectRotMask64(V, dl, RLAmt1, false, 0, 63);
1899 return SelectRotMaskIns64(Base, V, dl, RLAmt2, false, MaskStart, MaskEnd);
1902 void SelectAndParts64(const SDLoc &dl, SDValue &Res, unsigned *InstCnt) {
1903 if (BPermRewriterNoMasking)
1906 // The idea here is the same as in the 32-bit version, but with additional
1907 // complications from the fact that Repl32 might be true. Because we
1908 // aggressively convert bit groups to Repl32 form (which, for small
1909 // rotation factors, involves no other change), and then coalesce, it might
1910 // be the case that a single 64-bit masking operation could handle both
1911 // some Repl32 groups and some non-Repl32 groups. If converting to Repl32
1912 // form allowed coalescing, then we must use a 32-bit rotaton in order to
1913 // completely capture the new combined bit group.
1915 for (ValueRotInfo &VRI : ValueRotsVec) {
1918 // We need to add to the mask all bits from the associated bit groups.
1919 // If Repl32 is false, we need to add bits from bit groups that have
1920 // Repl32 true, but are trivially convertable to Repl32 false. Such a
1921 // group is trivially convertable if it overlaps only with the lower 32
1922 // bits, and the group has not been coalesced.
1923 auto MatchingBG = [VRI](const BitGroup &BG) {
1927 unsigned EffRLAmt = BG.RLAmt;
1928 if (!VRI.Repl32 && BG.Repl32) {
1929 if (BG.StartIdx < 32 && BG.EndIdx < 32 && BG.StartIdx <= BG.EndIdx &&
1930 !BG.Repl32Coalesced) {
1936 } else if (VRI.Repl32 != BG.Repl32) {
1940 return VRI.RLAmt == EffRLAmt;
1943 for (auto &BG : BitGroups) {
1944 if (!MatchingBG(BG))
1947 if (BG.StartIdx <= BG.EndIdx) {
1948 for (unsigned i = BG.StartIdx; i <= BG.EndIdx; ++i)
1949 Mask |= (UINT64_C(1) << i);
1951 for (unsigned i = BG.StartIdx; i < Bits.size(); ++i)
1952 Mask |= (UINT64_C(1) << i);
1953 for (unsigned i = 0; i <= BG.EndIdx; ++i)
1954 Mask |= (UINT64_C(1) << i);
1958 // We can use the 32-bit andi/andis technique if the mask does not
1959 // require any higher-order bits. This can save an instruction compared
1960 // to always using the general 64-bit technique.
1961 bool Use32BitInsts = isUInt<32>(Mask);
1962 // Compute the masks for andi/andis that would be necessary.
1963 unsigned ANDIMask = (Mask & UINT16_MAX),
1964 ANDISMask = (Mask >> 16) & UINT16_MAX;
1966 bool NeedsRotate = VRI.RLAmt || (VRI.Repl32 && !isUInt<32>(Mask));
1968 unsigned NumAndInsts = (unsigned) NeedsRotate +
1969 (unsigned) (bool) Res;
1971 NumAndInsts += (unsigned) (ANDIMask != 0) + (unsigned) (ANDISMask != 0) +
1972 (unsigned) (ANDIMask != 0 && ANDISMask != 0);
1974 NumAndInsts += selectI64ImmInstrCount(Mask) + /* and */ 1;
1976 unsigned NumRLInsts = 0;
1977 bool FirstBG = true;
1978 bool MoreBG = false;
1979 for (auto &BG : BitGroups) {
1980 if (!MatchingBG(BG)) {
1985 SelectRotMask64Count(BG.RLAmt, BG.Repl32, BG.StartIdx, BG.EndIdx,
1990 LLVM_DEBUG(dbgs() << "\t\trotation groups for " << VRI.V.getNode()
1991 << " RL: " << VRI.RLAmt << (VRI.Repl32 ? " (32):" : ":")
1992 << "\n\t\t\tisel using masking: " << NumAndInsts
1993 << " using rotates: " << NumRLInsts << "\n");
1995 // When we'd use andi/andis, we bias toward using the rotates (andi only
1996 // has a record form, and is cracked on POWER cores). However, when using
1997 // general 64-bit constant formation, bias toward the constant form,
1998 // because that exposes more opportunities for CSE.
1999 if (NumAndInsts > NumRLInsts)
2001 // When merging multiple bit groups, instruction or is used.
2002 // But when rotate is used, rldimi can inert the rotated value into any
2003 // register, so instruction or can be avoided.
2004 if ((Use32BitInsts || MoreBG) && NumAndInsts == NumRLInsts)
2007 LLVM_DEBUG(dbgs() << "\t\t\t\tusing masking\n");
2009 if (InstCnt) *InstCnt += NumAndInsts;
2012 // We actually need to generate a rotation if we have a non-zero rotation
2013 // factor or, in the Repl32 case, if we care about any of the
2014 // higher-order replicated bits. In the latter case, we generate a mask
2015 // backward so that it actually includes the entire 64 bits.
2016 if (VRI.RLAmt || (VRI.Repl32 && !isUInt<32>(Mask)))
2017 VRot = SelectRotMask64(VRI.V, dl, VRI.RLAmt, VRI.Repl32,
2018 VRI.Repl32 ? 31 : 0, VRI.Repl32 ? 30 : 63);
2023 if (Use32BitInsts) {
2024 assert((ANDIMask != 0 || ANDISMask != 0) &&
2025 "No set bits in mask when using 32-bit ands for 64-bit value");
2027 SDValue ANDIVal, ANDISVal;
2029 ANDIVal = SDValue(CurDAG->getMachineNode(PPC::ANDIo8, dl, MVT::i64,
2030 ExtendToInt64(VRot, dl),
2031 getI32Imm(ANDIMask, dl)),
2034 ANDISVal = SDValue(CurDAG->getMachineNode(PPC::ANDISo8, dl, MVT::i64,
2035 ExtendToInt64(VRot, dl),
2036 getI32Imm(ANDISMask, dl)),
2040 TotalVal = ANDISVal;
2044 TotalVal = SDValue(CurDAG->getMachineNode(PPC::OR8, dl, MVT::i64,
2045 ExtendToInt64(ANDIVal, dl), ANDISVal), 0);
2047 TotalVal = SDValue(selectI64Imm(CurDAG, dl, Mask), 0);
2049 SDValue(CurDAG->getMachineNode(PPC::AND8, dl, MVT::i64,
2050 ExtendToInt64(VRot, dl), TotalVal),
2057 Res = SDValue(CurDAG->getMachineNode(PPC::OR8, dl, MVT::i64,
2058 ExtendToInt64(Res, dl), TotalVal),
2061 // Now, remove all groups with this underlying value and rotation
2063 eraseMatchingBitGroups(MatchingBG);
2067 // Instruction selection for the 64-bit case.
2068 SDNode *Select64(SDNode *N, bool LateMask, unsigned *InstCnt) {
2072 if (InstCnt) *InstCnt = 0;
2074 // Take care of cases that should use andi/andis first.
2075 SelectAndParts64(dl, Res, InstCnt);
2077 // If we've not yet selected a 'starting' instruction, and we have no zeros
2078 // to fill in, select the (Value, RLAmt) with the highest priority (largest
2079 // number of groups), and start with this rotated value.
2080 if ((!HasZeros || LateMask) && !Res) {
2081 // If we have both Repl32 groups and non-Repl32 groups, the non-Repl32
2082 // groups will come first, and so the VRI representing the largest number
2083 // of groups might not be first (it might be the first Repl32 groups).
2084 unsigned MaxGroupsIdx = 0;
2085 if (!ValueRotsVec[0].Repl32) {
2086 for (unsigned i = 0, ie = ValueRotsVec.size(); i < ie; ++i)
2087 if (ValueRotsVec[i].Repl32) {
2088 if (ValueRotsVec[i].NumGroups > ValueRotsVec[0].NumGroups)
2094 ValueRotInfo &VRI = ValueRotsVec[MaxGroupsIdx];
2095 bool NeedsRotate = false;
2098 } else if (VRI.Repl32) {
2099 for (auto &BG : BitGroups) {
2100 if (BG.V != VRI.V || BG.RLAmt != VRI.RLAmt ||
2101 BG.Repl32 != VRI.Repl32)
2104 // We don't need a rotate if the bit group is confined to the lower
2106 if (BG.StartIdx < 32 && BG.EndIdx < 32 && BG.StartIdx < BG.EndIdx)
2115 Res = SelectRotMask64(VRI.V, dl, VRI.RLAmt, VRI.Repl32,
2116 VRI.Repl32 ? 31 : 0, VRI.Repl32 ? 30 : 63,
2121 // Now, remove all groups with this underlying value and rotation factor.
2123 eraseMatchingBitGroups([VRI](const BitGroup &BG) {
2124 return BG.V == VRI.V && BG.RLAmt == VRI.RLAmt &&
2125 BG.Repl32 == VRI.Repl32;
2129 // Because 64-bit rotates are more flexible than inserts, we might have a
2130 // preference regarding which one we do first (to save one instruction).
2132 for (auto I = BitGroups.begin(), IE = BitGroups.end(); I != IE; ++I) {
2133 if (SelectRotMask64Count(I->RLAmt, I->Repl32, I->StartIdx, I->EndIdx,
2135 SelectRotMask64Count(I->RLAmt, I->Repl32, I->StartIdx, I->EndIdx,
2137 if (I != BitGroups.begin()) {
2140 BitGroups.insert(BitGroups.begin(), BG);
2147 // Insert the other groups (one at a time).
2148 for (auto &BG : BitGroups) {
2150 Res = SelectRotMask64(BG.V, dl, BG.RLAmt, BG.Repl32, BG.StartIdx,
2151 BG.EndIdx, InstCnt);
2153 Res = SelectRotMaskIns64(Res, BG.V, dl, BG.RLAmt, BG.Repl32,
2154 BG.StartIdx, BG.EndIdx, InstCnt);
2158 uint64_t Mask = getZerosMask();
2160 // We can use the 32-bit andi/andis technique if the mask does not
2161 // require any higher-order bits. This can save an instruction compared
2162 // to always using the general 64-bit technique.
2163 bool Use32BitInsts = isUInt<32>(Mask);
2164 // Compute the masks for andi/andis that would be necessary.
2165 unsigned ANDIMask = (Mask & UINT16_MAX),
2166 ANDISMask = (Mask >> 16) & UINT16_MAX;
2168 if (Use32BitInsts) {
2169 assert((ANDIMask != 0 || ANDISMask != 0) &&
2170 "No set bits in mask when using 32-bit ands for 64-bit value");
2172 if (InstCnt) *InstCnt += (unsigned) (ANDIMask != 0) +
2173 (unsigned) (ANDISMask != 0) +
2174 (unsigned) (ANDIMask != 0 && ANDISMask != 0);
2176 SDValue ANDIVal, ANDISVal;
2178 ANDIVal = SDValue(CurDAG->getMachineNode(PPC::ANDIo8, dl, MVT::i64,
2179 ExtendToInt64(Res, dl), getI32Imm(ANDIMask, dl)), 0);
2181 ANDISVal = SDValue(CurDAG->getMachineNode(PPC::ANDISo8, dl, MVT::i64,
2182 ExtendToInt64(Res, dl), getI32Imm(ANDISMask, dl)), 0);
2189 Res = SDValue(CurDAG->getMachineNode(PPC::OR8, dl, MVT::i64,
2190 ExtendToInt64(ANDIVal, dl), ANDISVal), 0);
2192 if (InstCnt) *InstCnt += selectI64ImmInstrCount(Mask) + /* and */ 1;
2194 SDValue MaskVal = SDValue(selectI64Imm(CurDAG, dl, Mask), 0);
2196 SDValue(CurDAG->getMachineNode(PPC::AND8, dl, MVT::i64,
2197 ExtendToInt64(Res, dl), MaskVal), 0);
2201 return Res.getNode();
2204 SDNode *Select(SDNode *N, bool LateMask, unsigned *InstCnt = nullptr) {
2205 // Fill in BitGroups.
2206 collectBitGroups(LateMask);
2207 if (BitGroups.empty())
2210 // For 64-bit values, figure out when we can use 32-bit instructions.
2211 if (Bits.size() == 64)
2212 assignRepl32BitGroups();
2214 // Fill in ValueRotsVec.
2215 collectValueRotInfo();
2217 if (Bits.size() == 32) {
2218 return Select32(N, LateMask, InstCnt);
2220 assert(Bits.size() == 64 && "Not 64 bits here?");
2221 return Select64(N, LateMask, InstCnt);
2227 void eraseMatchingBitGroups(function_ref<bool(const BitGroup &)> F) {
2228 BitGroups.erase(remove_if(BitGroups, F), BitGroups.end());
2231 SmallVector<ValueBit, 64> Bits;
2234 SmallVector<unsigned, 64> RLAmt;
2236 SmallVector<BitGroup, 16> BitGroups;
2238 DenseMap<std::pair<SDValue, unsigned>, ValueRotInfo> ValueRots;
2239 SmallVector<ValueRotInfo, 16> ValueRotsVec;
2241 SelectionDAG *CurDAG;
2244 BitPermutationSelector(SelectionDAG *DAG)
2247 // Here we try to match complex bit permutations into a set of
2248 // rotate-and-shift/shift/and/or instructions, using a set of heuristics
2249 // known to produce optimial code for common cases (like i32 byte swapping).
2250 SDNode *Select(SDNode *N) {
2253 getValueBits(SDValue(N, 0), N->getValueType(0).getSizeInBits());
2256 Bits = std::move(*Result.second);
2258 LLVM_DEBUG(dbgs() << "Considering bit-permutation-based instruction"
2259 " selection for: ");
2260 LLVM_DEBUG(N->dump(CurDAG));
2262 // Fill it RLAmt and set HasZeros.
2263 computeRotationAmounts();
2266 return Select(N, false);
2268 // We currently have two techniques for handling results with zeros: early
2269 // masking (the default) and late masking. Late masking is sometimes more
2270 // efficient, but because the structure of the bit groups is different, it
2271 // is hard to tell without generating both and comparing the results. With
2272 // late masking, we ignore zeros in the resulting value when inserting each
2273 // set of bit groups, and then mask in the zeros at the end. With early
2274 // masking, we only insert the non-zero parts of the result at every step.
2276 unsigned InstCnt = 0, InstCntLateMask = 0;
2277 LLVM_DEBUG(dbgs() << "\tEarly masking:\n");
2278 SDNode *RN = Select(N, false, &InstCnt);
2279 LLVM_DEBUG(dbgs() << "\t\tisel would use " << InstCnt << " instructions\n");
2281 LLVM_DEBUG(dbgs() << "\tLate masking:\n");
2282 SDNode *RNLM = Select(N, true, &InstCntLateMask);
2283 LLVM_DEBUG(dbgs() << "\t\tisel would use " << InstCntLateMask
2284 << " instructions\n");
2286 if (InstCnt <= InstCntLateMask) {
2287 LLVM_DEBUG(dbgs() << "\tUsing early-masking for isel\n");
2291 LLVM_DEBUG(dbgs() << "\tUsing late-masking for isel\n");
2296 class IntegerCompareEliminator {
2297 SelectionDAG *CurDAG;
2299 // Conversion type for interpreting results of a 32-bit instruction as
2300 // a 64-bit value or vice versa.
2301 enum ExtOrTruncConversion { Ext, Trunc };
2303 // Modifiers to guide how an ISD::SETCC node's result is to be computed
2305 // ZExtOrig - use the original condition code, zero-extend value
2306 // ZExtInvert - invert the condition code, zero-extend value
2307 // SExtOrig - use the original condition code, sign-extend value
2308 // SExtInvert - invert the condition code, sign-extend value
2309 enum SetccInGPROpts { ZExtOrig, ZExtInvert, SExtOrig, SExtInvert };
2311 // Comparisons against zero to emit GPR code sequences for. Each of these
2312 // sequences may need to be emitted for two or more equivalent patterns.
2313 // For example (a >= 0) == (a > -1). The direction of the comparison (</>)
2314 // matters as well as the extension type: sext (-1/0), zext (1/0).
2315 // GEZExt - (zext (LHS >= 0))
2316 // GESExt - (sext (LHS >= 0))
2317 // LEZExt - (zext (LHS <= 0))
2318 // LESExt - (sext (LHS <= 0))
2319 enum ZeroCompare { GEZExt, GESExt, LEZExt, LESExt };
2321 SDNode *tryEXTEND(SDNode *N);
2322 SDNode *tryLogicOpOfCompares(SDNode *N);
2323 SDValue computeLogicOpInGPR(SDValue LogicOp);
2324 SDValue signExtendInputIfNeeded(SDValue Input);
2325 SDValue zeroExtendInputIfNeeded(SDValue Input);
2326 SDValue addExtOrTrunc(SDValue NatWidthRes, ExtOrTruncConversion Conv);
2327 SDValue getCompoundZeroComparisonInGPR(SDValue LHS, SDLoc dl,
2329 SDValue get32BitZExtCompare(SDValue LHS, SDValue RHS, ISD::CondCode CC,
2330 int64_t RHSValue, SDLoc dl);
2331 SDValue get32BitSExtCompare(SDValue LHS, SDValue RHS, ISD::CondCode CC,
2332 int64_t RHSValue, SDLoc dl);
2333 SDValue get64BitZExtCompare(SDValue LHS, SDValue RHS, ISD::CondCode CC,
2334 int64_t RHSValue, SDLoc dl);
2335 SDValue get64BitSExtCompare(SDValue LHS, SDValue RHS, ISD::CondCode CC,
2336 int64_t RHSValue, SDLoc dl);
2337 SDValue getSETCCInGPR(SDValue Compare, SetccInGPROpts ConvOpts);
2340 IntegerCompareEliminator(SelectionDAG *DAG,
2341 PPCDAGToDAGISel *Sel) : CurDAG(DAG), S(Sel) {
2342 assert(CurDAG->getTargetLoweringInfo()
2343 .getPointerTy(CurDAG->getDataLayout()).getSizeInBits() == 64 &&
2344 "Only expecting to use this on 64 bit targets.");
2346 SDNode *Select(SDNode *N) {
2347 if (CmpInGPR == ICGPR_None)
2349 switch (N->getOpcode()) {
2351 case ISD::ZERO_EXTEND:
2352 if (CmpInGPR == ICGPR_Sext || CmpInGPR == ICGPR_SextI32 ||
2353 CmpInGPR == ICGPR_SextI64)
2356 case ISD::SIGN_EXTEND:
2357 if (CmpInGPR == ICGPR_Zext || CmpInGPR == ICGPR_ZextI32 ||
2358 CmpInGPR == ICGPR_ZextI64)
2360 return tryEXTEND(N);
2364 return tryLogicOpOfCompares(N);
2370 static bool isLogicOp(unsigned Opc) {
2371 return Opc == ISD::AND || Opc == ISD::OR || Opc == ISD::XOR;
2373 // The obvious case for wanting to keep the value in a GPR. Namely, the
2374 // result of the comparison is actually needed in a GPR.
2375 SDNode *IntegerCompareEliminator::tryEXTEND(SDNode *N) {
2376 assert((N->getOpcode() == ISD::ZERO_EXTEND ||
2377 N->getOpcode() == ISD::SIGN_EXTEND) &&
2378 "Expecting a zero/sign extend node!");
2380 // If we are zero-extending the result of a logical operation on i1
2381 // values, we can keep the values in GPRs.
2382 if (isLogicOp(N->getOperand(0).getOpcode()) &&
2383 N->getOperand(0).getValueType() == MVT::i1 &&
2384 N->getOpcode() == ISD::ZERO_EXTEND)
2385 WideRes = computeLogicOpInGPR(N->getOperand(0));
2386 else if (N->getOperand(0).getOpcode() != ISD::SETCC)
2390 getSETCCInGPR(N->getOperand(0),
2391 N->getOpcode() == ISD::SIGN_EXTEND ?
2392 SetccInGPROpts::SExtOrig : SetccInGPROpts::ZExtOrig);
2398 bool Input32Bit = WideRes.getValueType() == MVT::i32;
2399 bool Output32Bit = N->getValueType(0) == MVT::i32;
2401 NumSextSetcc += N->getOpcode() == ISD::SIGN_EXTEND ? 1 : 0;
2402 NumZextSetcc += N->getOpcode() == ISD::SIGN_EXTEND ? 0 : 1;
2404 SDValue ConvOp = WideRes;
2405 if (Input32Bit != Output32Bit)
2406 ConvOp = addExtOrTrunc(WideRes, Input32Bit ? ExtOrTruncConversion::Ext :
2407 ExtOrTruncConversion::Trunc);
2408 return ConvOp.getNode();
2411 // Attempt to perform logical operations on the results of comparisons while
2412 // keeping the values in GPRs. Without doing so, these would end up being
2413 // lowered to CR-logical operations which suffer from significant latency and
2415 SDNode *IntegerCompareEliminator::tryLogicOpOfCompares(SDNode *N) {
2416 if (N->getValueType(0) != MVT::i1)
2418 assert(isLogicOp(N->getOpcode()) &&
2419 "Expected a logic operation on setcc results.");
2420 SDValue LoweredLogical = computeLogicOpInGPR(SDValue(N, 0));
2421 if (!LoweredLogical)
2425 bool IsBitwiseNegate = LoweredLogical.getMachineOpcode() == PPC::XORI8;
2426 unsigned SubRegToExtract = IsBitwiseNegate ? PPC::sub_eq : PPC::sub_gt;
2427 SDValue CR0Reg = CurDAG->getRegister(PPC::CR0, MVT::i32);
2428 SDValue LHS = LoweredLogical.getOperand(0);
2429 SDValue RHS = LoweredLogical.getOperand(1);
2431 SDValue OpToConvToRecForm;
2433 // Look through any 32-bit to 64-bit implicit extend nodes to find the
2434 // opcode that is input to the XORI.
2435 if (IsBitwiseNegate &&
2436 LoweredLogical.getOperand(0).getMachineOpcode() == PPC::INSERT_SUBREG)
2437 OpToConvToRecForm = LoweredLogical.getOperand(0).getOperand(1);
2438 else if (IsBitwiseNegate)
2439 // If the input to the XORI isn't an extension, that's what we're after.
2440 OpToConvToRecForm = LoweredLogical.getOperand(0);
2442 // If this is not an XORI, it is a reg-reg logical op and we can convert
2443 // it to record-form.
2444 OpToConvToRecForm = LoweredLogical;
2446 // Get the record-form version of the node we're looking to use to get the
2448 uint16_t NonRecOpc = OpToConvToRecForm.getMachineOpcode();
2449 int NewOpc = PPCInstrInfo::getRecordFormOpcode(NonRecOpc);
2451 // Convert the right node to record-form. This is either the logical we're
2452 // looking at or it is the input node to the negation (if we're looking at
2453 // a bitwise negation).
2454 if (NewOpc != -1 && IsBitwiseNegate) {
2455 // The input to the XORI has a record-form. Use it.
2456 assert(LoweredLogical.getConstantOperandVal(1) == 1 &&
2457 "Expected a PPC::XORI8 only for bitwise negation.");
2458 // Emit the record-form instruction.
2459 std::vector<SDValue> Ops;
2460 for (int i = 0, e = OpToConvToRecForm.getNumOperands(); i < e; i++)
2461 Ops.push_back(OpToConvToRecForm.getOperand(i));
2464 SDValue(CurDAG->getMachineNode(NewOpc, dl,
2465 OpToConvToRecForm.getValueType(),
2466 MVT::Glue, Ops), 0);
2468 assert((NewOpc != -1 || !IsBitwiseNegate) &&
2469 "No record form available for AND8/OR8/XOR8?");
2471 SDValue(CurDAG->getMachineNode(NewOpc == -1 ? PPC::ANDIo8 : NewOpc, dl,
2472 MVT::i64, MVT::Glue, LHS, RHS), 0);
2475 // Select this node to a single bit from CR0 set by the record-form node
2476 // just created. For bitwise negation, use the EQ bit which is the equivalent
2477 // of negating the result (i.e. it is a bit set when the result of the
2478 // operation is zero).
2480 CurDAG->getTargetConstant(SubRegToExtract, dl, MVT::i32);
2482 SDValue(CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG, dl,
2483 MVT::i1, CR0Reg, SRIdxVal,
2484 WideOp.getValue(1)), 0);
2485 return CRBit.getNode();
2488 // Lower a logical operation on i1 values into a GPR sequence if possible.
2489 // The result can be kept in a GPR if requested.
2490 // Three types of inputs can be handled:
2493 // - Logical operation (AND/OR/XOR)
2494 // There is also a special case that is handled (namely a complement operation
2495 // achieved with xor %a, -1).
2496 SDValue IntegerCompareEliminator::computeLogicOpInGPR(SDValue LogicOp) {
2497 assert(isLogicOp(LogicOp.getOpcode()) &&
2498 "Can only handle logic operations here.");
2499 assert(LogicOp.getValueType() == MVT::i1 &&
2500 "Can only handle logic operations on i1 values here.");
2504 // Special case: xor %a, -1
2505 bool IsBitwiseNegation = isBitwiseNot(LogicOp);
2507 // Produces a GPR sequence for each operand of the binary logic operation.
2508 // For SETCC, it produces the respective comparison, for TRUNCATE it truncates
2509 // the value in a GPR and for logic operations, it will recursively produce
2510 // a GPR sequence for the operation.
2511 auto getLogicOperand = [&] (SDValue Operand) -> SDValue {
2512 unsigned OperandOpcode = Operand.getOpcode();
2513 if (OperandOpcode == ISD::SETCC)
2514 return getSETCCInGPR(Operand, SetccInGPROpts::ZExtOrig);
2515 else if (OperandOpcode == ISD::TRUNCATE) {
2516 SDValue InputOp = Operand.getOperand(0);
2517 EVT InVT = InputOp.getValueType();
2518 return SDValue(CurDAG->getMachineNode(InVT == MVT::i32 ? PPC::RLDICL_32 :
2519 PPC::RLDICL, dl, InVT, InputOp,
2520 S->getI64Imm(0, dl),
2521 S->getI64Imm(63, dl)), 0);
2522 } else if (isLogicOp(OperandOpcode))
2523 return computeLogicOpInGPR(Operand);
2526 LHS = getLogicOperand(LogicOp.getOperand(0));
2527 RHS = getLogicOperand(LogicOp.getOperand(1));
2529 // If a GPR sequence can't be produced for the LHS we can't proceed.
2530 // Not producing a GPR sequence for the RHS is only a problem if this isn't
2531 // a bitwise negation operation.
2532 if (!LHS || (!RHS && !IsBitwiseNegation))
2535 NumLogicOpsOnComparison++;
2537 // We will use the inputs as 64-bit values.
2538 if (LHS.getValueType() == MVT::i32)
2539 LHS = addExtOrTrunc(LHS, ExtOrTruncConversion::Ext);
2540 if (!IsBitwiseNegation && RHS.getValueType() == MVT::i32)
2541 RHS = addExtOrTrunc(RHS, ExtOrTruncConversion::Ext);
2544 switch (LogicOp.getOpcode()) {
2545 default: llvm_unreachable("Unknown logic operation.");
2546 case ISD::AND: NewOpc = PPC::AND8; break;
2547 case ISD::OR: NewOpc = PPC::OR8; break;
2548 case ISD::XOR: NewOpc = PPC::XOR8; break;
2551 if (IsBitwiseNegation) {
2552 RHS = S->getI64Imm(1, dl);
2553 NewOpc = PPC::XORI8;
2556 return SDValue(CurDAG->getMachineNode(NewOpc, dl, MVT::i64, LHS, RHS), 0);
2560 /// If the value isn't guaranteed to be sign-extended to 64-bits, extend it.
2561 /// Otherwise just reinterpret it as a 64-bit value.
2562 /// Useful when emitting comparison code for 32-bit values without using
2563 /// the compare instruction (which only considers the lower 32-bits).
2564 SDValue IntegerCompareEliminator::signExtendInputIfNeeded(SDValue Input) {
2565 assert(Input.getValueType() == MVT::i32 &&
2566 "Can only sign-extend 32-bit values here.");
2567 unsigned Opc = Input.getOpcode();
2569 // The value was sign extended and then truncated to 32-bits. No need to
2570 // sign extend it again.
2571 if (Opc == ISD::TRUNCATE &&
2572 (Input.getOperand(0).getOpcode() == ISD::AssertSext ||
2573 Input.getOperand(0).getOpcode() == ISD::SIGN_EXTEND))
2574 return addExtOrTrunc(Input, ExtOrTruncConversion::Ext);
2576 LoadSDNode *InputLoad = dyn_cast<LoadSDNode>(Input);
2577 // The input is a sign-extending load. All ppc sign-extending loads
2578 // sign-extend to the full 64-bits.
2579 if (InputLoad && InputLoad->getExtensionType() == ISD::SEXTLOAD)
2580 return addExtOrTrunc(Input, ExtOrTruncConversion::Ext);
2582 ConstantSDNode *InputConst = dyn_cast<ConstantSDNode>(Input);
2583 // We don't sign-extend constants.
2585 return addExtOrTrunc(Input, ExtOrTruncConversion::Ext);
2588 SignExtensionsAdded++;
2589 return SDValue(CurDAG->getMachineNode(PPC::EXTSW_32_64, dl,
2590 MVT::i64, Input), 0);
2593 /// If the value isn't guaranteed to be zero-extended to 64-bits, extend it.
2594 /// Otherwise just reinterpret it as a 64-bit value.
2595 /// Useful when emitting comparison code for 32-bit values without using
2596 /// the compare instruction (which only considers the lower 32-bits).
2597 SDValue IntegerCompareEliminator::zeroExtendInputIfNeeded(SDValue Input) {
2598 assert(Input.getValueType() == MVT::i32 &&
2599 "Can only zero-extend 32-bit values here.");
2600 unsigned Opc = Input.getOpcode();
2602 // The only condition under which we can omit the actual extend instruction:
2603 // - The value is a positive constant
2604 // - The value comes from a load that isn't a sign-extending load
2605 // An ISD::TRUNCATE needs to be zero-extended unless it is fed by a zext.
2606 bool IsTruncateOfZExt = Opc == ISD::TRUNCATE &&
2607 (Input.getOperand(0).getOpcode() == ISD::AssertZext ||
2608 Input.getOperand(0).getOpcode() == ISD::ZERO_EXTEND);
2609 if (IsTruncateOfZExt)
2610 return addExtOrTrunc(Input, ExtOrTruncConversion::Ext);
2612 ConstantSDNode *InputConst = dyn_cast<ConstantSDNode>(Input);
2613 if (InputConst && InputConst->getSExtValue() >= 0)
2614 return addExtOrTrunc(Input, ExtOrTruncConversion::Ext);
2616 LoadSDNode *InputLoad = dyn_cast<LoadSDNode>(Input);
2617 // The input is a load that doesn't sign-extend (it will be zero-extended).
2618 if (InputLoad && InputLoad->getExtensionType() != ISD::SEXTLOAD)
2619 return addExtOrTrunc(Input, ExtOrTruncConversion::Ext);
2621 // None of the above, need to zero-extend.
2623 ZeroExtensionsAdded++;
2624 return SDValue(CurDAG->getMachineNode(PPC::RLDICL_32_64, dl, MVT::i64, Input,
2625 S->getI64Imm(0, dl),
2626 S->getI64Imm(32, dl)), 0);
2629 // Handle a 32-bit value in a 64-bit register and vice-versa. These are of
2630 // course not actual zero/sign extensions that will generate machine code,
2631 // they're just a way to reinterpret a 32 bit value in a register as a
2632 // 64 bit value and vice-versa.
2633 SDValue IntegerCompareEliminator::addExtOrTrunc(SDValue NatWidthRes,
2634 ExtOrTruncConversion Conv) {
2635 SDLoc dl(NatWidthRes);
2637 // For reinterpreting 32-bit values as 64 bit values, we generate
2638 // INSERT_SUBREG IMPLICIT_DEF:i64, <input>, TargetConstant:i32<1>
2639 if (Conv == ExtOrTruncConversion::Ext) {
2640 SDValue ImDef(CurDAG->getMachineNode(PPC::IMPLICIT_DEF, dl, MVT::i64), 0);
2642 CurDAG->getTargetConstant(PPC::sub_32, dl, MVT::i32);
2643 return SDValue(CurDAG->getMachineNode(PPC::INSERT_SUBREG, dl, MVT::i64,
2644 ImDef, NatWidthRes, SubRegIdx), 0);
2647 assert(Conv == ExtOrTruncConversion::Trunc &&
2648 "Unknown convertion between 32 and 64 bit values.");
2649 // For reinterpreting 64-bit values as 32-bit values, we just need to
2650 // EXTRACT_SUBREG (i.e. extract the low word).
2652 CurDAG->getTargetConstant(PPC::sub_32, dl, MVT::i32);
2653 return SDValue(CurDAG->getMachineNode(PPC::EXTRACT_SUBREG, dl, MVT::i32,
2654 NatWidthRes, SubRegIdx), 0);
2657 // Produce a GPR sequence for compound comparisons (<=, >=) against zero.
2658 // Handle both zero-extensions and sign-extensions.
2660 IntegerCompareEliminator::getCompoundZeroComparisonInGPR(SDValue LHS, SDLoc dl,
2661 ZeroCompare CmpTy) {
2662 EVT InVT = LHS.getValueType();
2663 bool Is32Bit = InVT == MVT::i32;
2666 // Produce the value that needs to be either zero or sign extended.
2668 case ZeroCompare::GEZExt:
2669 case ZeroCompare::GESExt:
2670 ToExtend = SDValue(CurDAG->getMachineNode(Is32Bit ? PPC::NOR : PPC::NOR8,
2671 dl, InVT, LHS, LHS), 0);
2673 case ZeroCompare::LEZExt:
2674 case ZeroCompare::LESExt: {
2676 // Upper 32 bits cannot be undefined for this sequence.
2677 LHS = signExtendInputIfNeeded(LHS);
2679 SDValue(CurDAG->getMachineNode(PPC::NEG8, dl, MVT::i64, LHS), 0);
2681 SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64,
2682 Neg, S->getI64Imm(1, dl),
2683 S->getI64Imm(63, dl)), 0);
2686 SDValue(CurDAG->getMachineNode(PPC::ADDI8, dl, MVT::i64, LHS,
2687 S->getI64Imm(~0ULL, dl)), 0);
2688 ToExtend = SDValue(CurDAG->getMachineNode(PPC::OR8, dl, MVT::i64,
2695 // For 64-bit sequences, the extensions are the same for the GE/LE cases.
2697 (CmpTy == ZeroCompare::GEZExt || CmpTy == ZeroCompare::LEZExt))
2698 return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64,
2699 ToExtend, S->getI64Imm(1, dl),
2700 S->getI64Imm(63, dl)), 0);
2702 (CmpTy == ZeroCompare::GESExt || CmpTy == ZeroCompare::LESExt))
2703 return SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, ToExtend,
2704 S->getI64Imm(63, dl)), 0);
2706 assert(Is32Bit && "Should have handled the 32-bit sequences above.");
2707 // For 32-bit sequences, the extensions differ between GE/LE cases.
2709 case ZeroCompare::GEZExt: {
2710 SDValue ShiftOps[] = { ToExtend, S->getI32Imm(1, dl), S->getI32Imm(31, dl),
2711 S->getI32Imm(31, dl) };
2712 return SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32,
2715 case ZeroCompare::GESExt:
2716 return SDValue(CurDAG->getMachineNode(PPC::SRAWI, dl, MVT::i32, ToExtend,
2717 S->getI32Imm(31, dl)), 0);
2718 case ZeroCompare::LEZExt:
2719 return SDValue(CurDAG->getMachineNode(PPC::XORI8, dl, MVT::i64, ToExtend,
2720 S->getI32Imm(1, dl)), 0);
2721 case ZeroCompare::LESExt:
2722 return SDValue(CurDAG->getMachineNode(PPC::ADDI8, dl, MVT::i64, ToExtend,
2723 S->getI32Imm(-1, dl)), 0);
2726 // The above case covers all the enumerators so it can't have a default clause
2727 // to avoid compiler warnings.
2728 llvm_unreachable("Unknown zero-comparison type.");
2731 /// Produces a zero-extended result of comparing two 32-bit values according to
2732 /// the passed condition code.
2734 IntegerCompareEliminator::get32BitZExtCompare(SDValue LHS, SDValue RHS,
2736 int64_t RHSValue, SDLoc dl) {
2737 if (CmpInGPR == ICGPR_I64 || CmpInGPR == ICGPR_SextI64 ||
2738 CmpInGPR == ICGPR_ZextI64 || CmpInGPR == ICGPR_Sext)
2740 bool IsRHSZero = RHSValue == 0;
2741 bool IsRHSOne = RHSValue == 1;
2742 bool IsRHSNegOne = RHSValue == -1LL;
2744 default: return SDValue();
2746 // (zext (setcc %a, %b, seteq)) -> (lshr (cntlzw (xor %a, %b)), 5)
2747 // (zext (setcc %a, 0, seteq)) -> (lshr (cntlzw %a), 5)
2748 SDValue Xor = IsRHSZero ? LHS :
2749 SDValue(CurDAG->getMachineNode(PPC::XOR, dl, MVT::i32, LHS, RHS), 0);
2751 SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, Xor), 0);
2752 SDValue ShiftOps[] = { Clz, S->getI32Imm(27, dl), S->getI32Imm(5, dl),
2753 S->getI32Imm(31, dl) };
2754 return SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32,
2758 // (zext (setcc %a, %b, setne)) -> (xor (lshr (cntlzw (xor %a, %b)), 5), 1)
2759 // (zext (setcc %a, 0, setne)) -> (xor (lshr (cntlzw %a), 5), 1)
2760 SDValue Xor = IsRHSZero ? LHS :
2761 SDValue(CurDAG->getMachineNode(PPC::XOR, dl, MVT::i32, LHS, RHS), 0);
2763 SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, Xor), 0);
2764 SDValue ShiftOps[] = { Clz, S->getI32Imm(27, dl), S->getI32Imm(5, dl),
2765 S->getI32Imm(31, dl) };
2767 SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, ShiftOps), 0);
2768 return SDValue(CurDAG->getMachineNode(PPC::XORI, dl, MVT::i32, Shift,
2769 S->getI32Imm(1, dl)), 0);
2772 // (zext (setcc %a, %b, setge)) -> (xor (lshr (sub %a, %b), 63), 1)
2773 // (zext (setcc %a, 0, setge)) -> (lshr (~ %a), 31)
2775 return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::GEZExt);
2777 // Not a special case (i.e. RHS == 0). Handle (%a >= %b) as (%b <= %a)
2778 // by swapping inputs and falling through.
2779 std::swap(LHS, RHS);
2780 ConstantSDNode *RHSConst = dyn_cast<ConstantSDNode>(RHS);
2781 IsRHSZero = RHSConst && RHSConst->isNullValue();
2785 if (CmpInGPR == ICGPR_NonExtIn)
2787 // (zext (setcc %a, %b, setle)) -> (xor (lshr (sub %b, %a), 63), 1)
2788 // (zext (setcc %a, 0, setle)) -> (xor (lshr (- %a), 63), 1)
2790 if (CmpInGPR == ICGPR_NonExtIn)
2792 return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::LEZExt);
2795 // The upper 32-bits of the register can't be undefined for this sequence.
2796 LHS = signExtendInputIfNeeded(LHS);
2797 RHS = signExtendInputIfNeeded(RHS);
2799 SDValue(CurDAG->getMachineNode(PPC::SUBF8, dl, MVT::i64, LHS, RHS), 0);
2801 SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, Sub,
2802 S->getI64Imm(1, dl), S->getI64Imm(63, dl)),
2805 SDValue(CurDAG->getMachineNode(PPC::XORI8, dl,
2806 MVT::i64, Shift, S->getI32Imm(1, dl)), 0);
2809 // (zext (setcc %a, %b, setgt)) -> (lshr (sub %b, %a), 63)
2810 // (zext (setcc %a, -1, setgt)) -> (lshr (~ %a), 31)
2811 // (zext (setcc %a, 0, setgt)) -> (lshr (- %a), 63)
2812 // Handle SETLT -1 (which is equivalent to SETGE 0).
2814 return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::GEZExt);
2817 if (CmpInGPR == ICGPR_NonExtIn)
2819 // The upper 32-bits of the register can't be undefined for this sequence.
2820 LHS = signExtendInputIfNeeded(LHS);
2821 RHS = signExtendInputIfNeeded(RHS);
2823 SDValue(CurDAG->getMachineNode(PPC::NEG8, dl, MVT::i64, LHS), 0);
2824 return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64,
2825 Neg, S->getI32Imm(1, dl), S->getI32Imm(63, dl)), 0);
2827 // Not a special case (i.e. RHS == 0 or RHS == -1). Handle (%a > %b) as
2828 // (%b < %a) by swapping inputs and falling through.
2829 std::swap(LHS, RHS);
2830 ConstantSDNode *RHSConst = dyn_cast<ConstantSDNode>(RHS);
2831 IsRHSZero = RHSConst && RHSConst->isNullValue();
2832 IsRHSOne = RHSConst && RHSConst->getSExtValue() == 1;
2836 // (zext (setcc %a, %b, setlt)) -> (lshr (sub %a, %b), 63)
2837 // (zext (setcc %a, 1, setlt)) -> (xor (lshr (- %a), 63), 1)
2838 // (zext (setcc %a, 0, setlt)) -> (lshr %a, 31)
2839 // Handle SETLT 1 (which is equivalent to SETLE 0).
2841 if (CmpInGPR == ICGPR_NonExtIn)
2843 return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::LEZExt);
2847 SDValue ShiftOps[] = { LHS, S->getI32Imm(1, dl), S->getI32Imm(31, dl),
2848 S->getI32Imm(31, dl) };
2849 return SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32,
2853 if (CmpInGPR == ICGPR_NonExtIn)
2855 // The upper 32-bits of the register can't be undefined for this sequence.
2856 LHS = signExtendInputIfNeeded(LHS);
2857 RHS = signExtendInputIfNeeded(RHS);
2859 SDValue(CurDAG->getMachineNode(PPC::SUBF8, dl, MVT::i64, RHS, LHS), 0);
2860 return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64,
2861 SUBFNode, S->getI64Imm(1, dl),
2862 S->getI64Imm(63, dl)), 0);
2865 // (zext (setcc %a, %b, setuge)) -> (xor (lshr (sub %b, %a), 63), 1)
2866 // (zext (setcc %a, %b, setule)) -> (xor (lshr (sub %a, %b), 63), 1)
2867 std::swap(LHS, RHS);
2870 if (CmpInGPR == ICGPR_NonExtIn)
2872 // The upper 32-bits of the register can't be undefined for this sequence.
2873 LHS = zeroExtendInputIfNeeded(LHS);
2874 RHS = zeroExtendInputIfNeeded(RHS);
2876 SDValue(CurDAG->getMachineNode(PPC::SUBF8, dl, MVT::i64, LHS, RHS), 0);
2878 SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64,
2879 Subtract, S->getI64Imm(1, dl),
2880 S->getI64Imm(63, dl)), 0);
2881 return SDValue(CurDAG->getMachineNode(PPC::XORI8, dl, MVT::i64, SrdiNode,
2882 S->getI32Imm(1, dl)), 0);
2885 // (zext (setcc %a, %b, setugt)) -> (lshr (sub %b, %a), 63)
2886 // (zext (setcc %a, %b, setult)) -> (lshr (sub %a, %b), 63)
2887 std::swap(LHS, RHS);
2890 if (CmpInGPR == ICGPR_NonExtIn)
2892 // The upper 32-bits of the register can't be undefined for this sequence.
2893 LHS = zeroExtendInputIfNeeded(LHS);
2894 RHS = zeroExtendInputIfNeeded(RHS);
2896 SDValue(CurDAG->getMachineNode(PPC::SUBF8, dl, MVT::i64, RHS, LHS), 0);
2897 return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64,
2898 Subtract, S->getI64Imm(1, dl),
2899 S->getI64Imm(63, dl)), 0);
2904 /// Produces a sign-extended result of comparing two 32-bit values according to
2905 /// the passed condition code.
2907 IntegerCompareEliminator::get32BitSExtCompare(SDValue LHS, SDValue RHS,
2909 int64_t RHSValue, SDLoc dl) {
2910 if (CmpInGPR == ICGPR_I64 || CmpInGPR == ICGPR_SextI64 ||
2911 CmpInGPR == ICGPR_ZextI64 || CmpInGPR == ICGPR_Zext)
2913 bool IsRHSZero = RHSValue == 0;
2914 bool IsRHSOne = RHSValue == 1;
2915 bool IsRHSNegOne = RHSValue == -1LL;
2918 default: return SDValue();
2920 // (sext (setcc %a, %b, seteq)) ->
2921 // (ashr (shl (ctlz (xor %a, %b)), 58), 63)
2922 // (sext (setcc %a, 0, seteq)) ->
2923 // (ashr (shl (ctlz %a), 58), 63)
2924 SDValue CountInput = IsRHSZero ? LHS :
2925 SDValue(CurDAG->getMachineNode(PPC::XOR, dl, MVT::i32, LHS, RHS), 0);
2927 SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, CountInput), 0);
2928 SDValue SHLOps[] = { Cntlzw, S->getI32Imm(27, dl),
2929 S->getI32Imm(5, dl), S->getI32Imm(31, dl) };
2931 SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, SHLOps), 0);
2932 return SDValue(CurDAG->getMachineNode(PPC::NEG, dl, MVT::i32, Slwi), 0);
2935 // Bitwise xor the operands, count leading zeros, shift right by 5 bits and
2936 // flip the bit, finally take 2's complement.
2937 // (sext (setcc %a, %b, setne)) ->
2938 // (neg (xor (lshr (ctlz (xor %a, %b)), 5), 1))
2939 // Same as above, but the first xor is not needed.
2940 // (sext (setcc %a, 0, setne)) ->
2941 // (neg (xor (lshr (ctlz %a), 5), 1))
2942 SDValue Xor = IsRHSZero ? LHS :
2943 SDValue(CurDAG->getMachineNode(PPC::XOR, dl, MVT::i32, LHS, RHS), 0);
2945 SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, Xor), 0);
2946 SDValue ShiftOps[] =
2947 { Clz, S->getI32Imm(27, dl), S->getI32Imm(5, dl), S->getI32Imm(31, dl) };
2949 SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, ShiftOps), 0);
2951 SDValue(CurDAG->getMachineNode(PPC::XORI, dl, MVT::i32, Shift,
2952 S->getI32Imm(1, dl)), 0);
2953 return SDValue(CurDAG->getMachineNode(PPC::NEG, dl, MVT::i32, Xori), 0);
2956 // (sext (setcc %a, %b, setge)) -> (add (lshr (sub %a, %b), 63), -1)
2957 // (sext (setcc %a, 0, setge)) -> (ashr (~ %a), 31)
2959 return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::GESExt);
2961 // Not a special case (i.e. RHS == 0). Handle (%a >= %b) as (%b <= %a)
2962 // by swapping inputs and falling through.
2963 std::swap(LHS, RHS);
2964 ConstantSDNode *RHSConst = dyn_cast<ConstantSDNode>(RHS);
2965 IsRHSZero = RHSConst && RHSConst->isNullValue();
2969 if (CmpInGPR == ICGPR_NonExtIn)
2971 // (sext (setcc %a, %b, setge)) -> (add (lshr (sub %b, %a), 63), -1)
2972 // (sext (setcc %a, 0, setle)) -> (add (lshr (- %a), 63), -1)
2974 return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::LESExt);
2976 // The upper 32-bits of the register can't be undefined for this sequence.
2977 LHS = signExtendInputIfNeeded(LHS);
2978 RHS = signExtendInputIfNeeded(RHS);
2980 SDValue(CurDAG->getMachineNode(PPC::SUBF8, dl, MVT::i64, MVT::Glue,
2983 SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64,
2984 SUBFNode, S->getI64Imm(1, dl),
2985 S->getI64Imm(63, dl)), 0);
2986 return SDValue(CurDAG->getMachineNode(PPC::ADDI8, dl, MVT::i64, Srdi,
2987 S->getI32Imm(-1, dl)), 0);
2990 // (sext (setcc %a, %b, setgt)) -> (ashr (sub %b, %a), 63)
2991 // (sext (setcc %a, -1, setgt)) -> (ashr (~ %a), 31)
2992 // (sext (setcc %a, 0, setgt)) -> (ashr (- %a), 63)
2994 return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::GESExt);
2996 if (CmpInGPR == ICGPR_NonExtIn)
2998 // The upper 32-bits of the register can't be undefined for this sequence.
2999 LHS = signExtendInputIfNeeded(LHS);
3000 RHS = signExtendInputIfNeeded(RHS);
3002 SDValue(CurDAG->getMachineNode(PPC::NEG8, dl, MVT::i64, LHS), 0);
3003 return SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, Neg,
3004 S->getI64Imm(63, dl)), 0);
3006 // Not a special case (i.e. RHS == 0 or RHS == -1). Handle (%a > %b) as
3007 // (%b < %a) by swapping inputs and falling through.
3008 std::swap(LHS, RHS);
3009 ConstantSDNode *RHSConst = dyn_cast<ConstantSDNode>(RHS);
3010 IsRHSZero = RHSConst && RHSConst->isNullValue();
3011 IsRHSOne = RHSConst && RHSConst->getSExtValue() == 1;
3015 // (sext (setcc %a, %b, setgt)) -> (ashr (sub %a, %b), 63)
3016 // (sext (setcc %a, 1, setgt)) -> (add (lshr (- %a), 63), -1)
3017 // (sext (setcc %a, 0, setgt)) -> (ashr %a, 31)
3019 if (CmpInGPR == ICGPR_NonExtIn)
3021 return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::LESExt);
3024 return SDValue(CurDAG->getMachineNode(PPC::SRAWI, dl, MVT::i32, LHS,
3025 S->getI32Imm(31, dl)), 0);
3027 if (CmpInGPR == ICGPR_NonExtIn)
3029 // The upper 32-bits of the register can't be undefined for this sequence.
3030 LHS = signExtendInputIfNeeded(LHS);
3031 RHS = signExtendInputIfNeeded(RHS);
3033 SDValue(CurDAG->getMachineNode(PPC::SUBF8, dl, MVT::i64, RHS, LHS), 0);
3034 return SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64,
3035 SUBFNode, S->getI64Imm(63, dl)), 0);
3038 // (sext (setcc %a, %b, setuge)) -> (add (lshr (sub %a, %b), 63), -1)
3039 // (sext (setcc %a, %b, setule)) -> (add (lshr (sub %b, %a), 63), -1)
3040 std::swap(LHS, RHS);
3043 if (CmpInGPR == ICGPR_NonExtIn)
3045 // The upper 32-bits of the register can't be undefined for this sequence.
3046 LHS = zeroExtendInputIfNeeded(LHS);
3047 RHS = zeroExtendInputIfNeeded(RHS);
3049 SDValue(CurDAG->getMachineNode(PPC::SUBF8, dl, MVT::i64, LHS, RHS), 0);
3051 SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, Subtract,
3052 S->getI32Imm(1, dl), S->getI32Imm(63,dl)),
3054 return SDValue(CurDAG->getMachineNode(PPC::ADDI8, dl, MVT::i64, Shift,
3055 S->getI32Imm(-1, dl)), 0);
3058 // (sext (setcc %a, %b, setugt)) -> (ashr (sub %b, %a), 63)
3059 // (sext (setcc %a, %b, setugt)) -> (ashr (sub %a, %b), 63)
3060 std::swap(LHS, RHS);
3063 if (CmpInGPR == ICGPR_NonExtIn)
3065 // The upper 32-bits of the register can't be undefined for this sequence.
3066 LHS = zeroExtendInputIfNeeded(LHS);
3067 RHS = zeroExtendInputIfNeeded(RHS);
3069 SDValue(CurDAG->getMachineNode(PPC::SUBF8, dl, MVT::i64, RHS, LHS), 0);
3070 return SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64,
3071 Subtract, S->getI64Imm(63, dl)), 0);
3076 /// Produces a zero-extended result of comparing two 64-bit values according to
3077 /// the passed condition code.
3079 IntegerCompareEliminator::get64BitZExtCompare(SDValue LHS, SDValue RHS,
3081 int64_t RHSValue, SDLoc dl) {
3082 if (CmpInGPR == ICGPR_I32 || CmpInGPR == ICGPR_SextI32 ||
3083 CmpInGPR == ICGPR_ZextI32 || CmpInGPR == ICGPR_Sext)
3085 bool IsRHSZero = RHSValue == 0;
3086 bool IsRHSOne = RHSValue == 1;
3087 bool IsRHSNegOne = RHSValue == -1LL;
3089 default: return SDValue();
3091 // (zext (setcc %a, %b, seteq)) -> (lshr (ctlz (xor %a, %b)), 6)
3092 // (zext (setcc %a, 0, seteq)) -> (lshr (ctlz %a), 6)
3093 SDValue Xor = IsRHSZero ? LHS :
3094 SDValue(CurDAG->getMachineNode(PPC::XOR8, dl, MVT::i64, LHS, RHS), 0);
3096 SDValue(CurDAG->getMachineNode(PPC::CNTLZD, dl, MVT::i64, Xor), 0);
3097 return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, Clz,
3098 S->getI64Imm(58, dl),
3099 S->getI64Imm(63, dl)), 0);
3102 // {addc.reg, addc.CA} = (addcarry (xor %a, %b), -1)
3103 // (zext (setcc %a, %b, setne)) -> (sube addc.reg, addc.reg, addc.CA)
3104 // {addcz.reg, addcz.CA} = (addcarry %a, -1)
3105 // (zext (setcc %a, 0, setne)) -> (sube addcz.reg, addcz.reg, addcz.CA)
3106 SDValue Xor = IsRHSZero ? LHS :
3107 SDValue(CurDAG->getMachineNode(PPC::XOR8, dl, MVT::i64, LHS, RHS), 0);
3109 SDValue(CurDAG->getMachineNode(PPC::ADDIC8, dl, MVT::i64, MVT::Glue,
3110 Xor, S->getI32Imm(~0U, dl)), 0);
3111 return SDValue(CurDAG->getMachineNode(PPC::SUBFE8, dl, MVT::i64, AC,
3112 Xor, AC.getValue(1)), 0);
3115 // {subc.reg, subc.CA} = (subcarry %a, %b)
3116 // (zext (setcc %a, %b, setge)) ->
3117 // (adde (lshr %b, 63), (ashr %a, 63), subc.CA)
3118 // (zext (setcc %a, 0, setge)) -> (lshr (~ %a), 63)
3120 return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::GEZExt);
3121 std::swap(LHS, RHS);
3122 ConstantSDNode *RHSConst = dyn_cast<ConstantSDNode>(RHS);
3123 IsRHSZero = RHSConst && RHSConst->isNullValue();
3127 // {subc.reg, subc.CA} = (subcarry %b, %a)
3128 // (zext (setcc %a, %b, setge)) ->
3129 // (adde (lshr %a, 63), (ashr %b, 63), subc.CA)
3130 // (zext (setcc %a, 0, setge)) -> (lshr (or %a, (add %a, -1)), 63)
3132 return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::LEZExt);
3134 SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, LHS,
3135 S->getI64Imm(1, dl),
3136 S->getI64Imm(63, dl)), 0);
3138 SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, RHS,
3139 S->getI64Imm(63, dl)), 0);
3140 SDValue SubtractCarry =
3141 SDValue(CurDAG->getMachineNode(PPC::SUBFC8, dl, MVT::i64, MVT::Glue,
3143 return SDValue(CurDAG->getMachineNode(PPC::ADDE8, dl, MVT::i64, MVT::Glue,
3144 ShiftR, ShiftL, SubtractCarry), 0);
3147 // {subc.reg, subc.CA} = (subcarry %b, %a)
3148 // (zext (setcc %a, %b, setgt)) ->
3149 // (xor (adde (lshr %a, 63), (ashr %b, 63), subc.CA), 1)
3150 // (zext (setcc %a, 0, setgt)) -> (lshr (nor (add %a, -1), %a), 63)
3152 return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::GEZExt);
3155 SDValue(CurDAG->getMachineNode(PPC::ADDI8, dl, MVT::i64, LHS,
3156 S->getI64Imm(~0ULL, dl)), 0);
3158 SDValue(CurDAG->getMachineNode(PPC::NOR8, dl, MVT::i64, Addi, LHS), 0);
3159 return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, Nor,
3160 S->getI64Imm(1, dl),
3161 S->getI64Imm(63, dl)), 0);
3163 std::swap(LHS, RHS);
3164 ConstantSDNode *RHSConst = dyn_cast<ConstantSDNode>(RHS);
3165 IsRHSZero = RHSConst && RHSConst->isNullValue();
3166 IsRHSOne = RHSConst && RHSConst->getSExtValue() == 1;
3170 // {subc.reg, subc.CA} = (subcarry %a, %b)
3171 // (zext (setcc %a, %b, setlt)) ->
3172 // (xor (adde (lshr %b, 63), (ashr %a, 63), subc.CA), 1)
3173 // (zext (setcc %a, 0, setlt)) -> (lshr %a, 63)
3175 return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::LEZExt);
3177 return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, LHS,
3178 S->getI64Imm(1, dl),
3179 S->getI64Imm(63, dl)), 0);
3181 SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64,
3182 LHS, S->getI64Imm(63, dl)), 0);
3184 SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64,
3185 RHS, S->getI64Imm(1, dl),
3186 S->getI64Imm(63, dl)), 0);
3187 SDValue SUBFC8Carry =
3188 SDValue(CurDAG->getMachineNode(PPC::SUBFC8, dl, MVT::i64, MVT::Glue,
3191 SDValue(CurDAG->getMachineNode(PPC::ADDE8, dl, MVT::i64, MVT::Glue,
3192 SRDINode, SRADINode, SUBFC8Carry), 0);
3193 return SDValue(CurDAG->getMachineNode(PPC::XORI8, dl, MVT::i64,
3194 ADDE8Node, S->getI64Imm(1, dl)), 0);
3197 // {subc.reg, subc.CA} = (subcarry %a, %b)
3198 // (zext (setcc %a, %b, setuge)) -> (add (sube %b, %b, subc.CA), 1)
3199 std::swap(LHS, RHS);
3202 // {subc.reg, subc.CA} = (subcarry %b, %a)
3203 // (zext (setcc %a, %b, setule)) -> (add (sube %a, %a, subc.CA), 1)
3204 SDValue SUBFC8Carry =
3205 SDValue(CurDAG->getMachineNode(PPC::SUBFC8, dl, MVT::i64, MVT::Glue,
3207 SDValue SUBFE8Node =
3208 SDValue(CurDAG->getMachineNode(PPC::SUBFE8, dl, MVT::i64, MVT::Glue,
3209 LHS, LHS, SUBFC8Carry), 0);
3210 return SDValue(CurDAG->getMachineNode(PPC::ADDI8, dl, MVT::i64,
3211 SUBFE8Node, S->getI64Imm(1, dl)), 0);
3214 // {subc.reg, subc.CA} = (subcarry %b, %a)
3215 // (zext (setcc %a, %b, setugt)) -> -(sube %b, %b, subc.CA)
3216 std::swap(LHS, RHS);
3219 // {subc.reg, subc.CA} = (subcarry %a, %b)
3220 // (zext (setcc %a, %b, setult)) -> -(sube %a, %a, subc.CA)
3221 SDValue SubtractCarry =
3222 SDValue(CurDAG->getMachineNode(PPC::SUBFC8, dl, MVT::i64, MVT::Glue,
3225 SDValue(CurDAG->getMachineNode(PPC::SUBFE8, dl, MVT::i64,
3226 LHS, LHS, SubtractCarry), 0);
3227 return SDValue(CurDAG->getMachineNode(PPC::NEG8, dl, MVT::i64,
3233 /// Produces a sign-extended result of comparing two 64-bit values according to
3234 /// the passed condition code.
3236 IntegerCompareEliminator::get64BitSExtCompare(SDValue LHS, SDValue RHS,
3238 int64_t RHSValue, SDLoc dl) {
3239 if (CmpInGPR == ICGPR_I32 || CmpInGPR == ICGPR_SextI32 ||
3240 CmpInGPR == ICGPR_ZextI32 || CmpInGPR == ICGPR_Zext)
3242 bool IsRHSZero = RHSValue == 0;
3243 bool IsRHSOne = RHSValue == 1;
3244 bool IsRHSNegOne = RHSValue == -1LL;
3246 default: return SDValue();
3248 // {addc.reg, addc.CA} = (addcarry (xor %a, %b), -1)
3249 // (sext (setcc %a, %b, seteq)) -> (sube addc.reg, addc.reg, addc.CA)
3250 // {addcz.reg, addcz.CA} = (addcarry %a, -1)
3251 // (sext (setcc %a, 0, seteq)) -> (sube addcz.reg, addcz.reg, addcz.CA)
3252 SDValue AddInput = IsRHSZero ? LHS :
3253 SDValue(CurDAG->getMachineNode(PPC::XOR8, dl, MVT::i64, LHS, RHS), 0);
3255 SDValue(CurDAG->getMachineNode(PPC::ADDIC8, dl, MVT::i64, MVT::Glue,
3256 AddInput, S->getI32Imm(~0U, dl)), 0);
3257 return SDValue(CurDAG->getMachineNode(PPC::SUBFE8, dl, MVT::i64, Addic,
3258 Addic, Addic.getValue(1)), 0);
3261 // {subfc.reg, subfc.CA} = (subcarry 0, (xor %a, %b))
3262 // (sext (setcc %a, %b, setne)) -> (sube subfc.reg, subfc.reg, subfc.CA)
3263 // {subfcz.reg, subfcz.CA} = (subcarry 0, %a)
3264 // (sext (setcc %a, 0, setne)) -> (sube subfcz.reg, subfcz.reg, subfcz.CA)
3265 SDValue Xor = IsRHSZero ? LHS :
3266 SDValue(CurDAG->getMachineNode(PPC::XOR8, dl, MVT::i64, LHS, RHS), 0);
3268 SDValue(CurDAG->getMachineNode(PPC::SUBFIC8, dl, MVT::i64, MVT::Glue,
3269 Xor, S->getI32Imm(0, dl)), 0);
3270 return SDValue(CurDAG->getMachineNode(PPC::SUBFE8, dl, MVT::i64, SC,
3271 SC, SC.getValue(1)), 0);
3274 // {subc.reg, subc.CA} = (subcarry %a, %b)
3275 // (zext (setcc %a, %b, setge)) ->
3276 // (- (adde (lshr %b, 63), (ashr %a, 63), subc.CA))
3277 // (zext (setcc %a, 0, setge)) -> (~ (ashr %a, 63))
3279 return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::GESExt);
3280 std::swap(LHS, RHS);
3281 ConstantSDNode *RHSConst = dyn_cast<ConstantSDNode>(RHS);
3282 IsRHSZero = RHSConst && RHSConst->isNullValue();
3286 // {subc.reg, subc.CA} = (subcarry %b, %a)
3287 // (zext (setcc %a, %b, setge)) ->
3288 // (- (adde (lshr %a, 63), (ashr %b, 63), subc.CA))
3289 // (zext (setcc %a, 0, setge)) -> (ashr (or %a, (add %a, -1)), 63)
3291 return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::LESExt);
3293 SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, RHS,
3294 S->getI64Imm(63, dl)), 0);
3296 SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, LHS,
3297 S->getI64Imm(1, dl),
3298 S->getI64Imm(63, dl)), 0);
3299 SDValue SubtractCarry =
3300 SDValue(CurDAG->getMachineNode(PPC::SUBFC8, dl, MVT::i64, MVT::Glue,
3303 SDValue(CurDAG->getMachineNode(PPC::ADDE8, dl, MVT::i64, MVT::Glue,
3304 ShiftR, ShiftL, SubtractCarry), 0);
3305 return SDValue(CurDAG->getMachineNode(PPC::NEG8, dl, MVT::i64, Adde), 0);
3308 // {subc.reg, subc.CA} = (subcarry %b, %a)
3309 // (zext (setcc %a, %b, setgt)) ->
3310 // -(xor (adde (lshr %a, 63), (ashr %b, 63), subc.CA), 1)
3311 // (zext (setcc %a, 0, setgt)) -> (ashr (nor (add %a, -1), %a), 63)
3313 return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::GESExt);
3316 SDValue(CurDAG->getMachineNode(PPC::ADDI8, dl, MVT::i64, LHS,
3317 S->getI64Imm(-1, dl)), 0);
3319 SDValue(CurDAG->getMachineNode(PPC::NOR8, dl, MVT::i64, Add, LHS), 0);
3320 return SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, Nor,
3321 S->getI64Imm(63, dl)), 0);
3323 std::swap(LHS, RHS);
3324 ConstantSDNode *RHSConst = dyn_cast<ConstantSDNode>(RHS);
3325 IsRHSZero = RHSConst && RHSConst->isNullValue();
3326 IsRHSOne = RHSConst && RHSConst->getSExtValue() == 1;
3330 // {subc.reg, subc.CA} = (subcarry %a, %b)
3331 // (zext (setcc %a, %b, setlt)) ->
3332 // -(xor (adde (lshr %b, 63), (ashr %a, 63), subc.CA), 1)
3333 // (zext (setcc %a, 0, setlt)) -> (ashr %a, 63)
3335 return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::LESExt);
3337 return SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, LHS,
3338 S->getI64Imm(63, dl)), 0);
3341 SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64,
3342 LHS, S->getI64Imm(63, dl)), 0);
3344 SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64,
3345 RHS, S->getI64Imm(1, dl),
3346 S->getI64Imm(63, dl)), 0);
3347 SDValue SUBFC8Carry =
3348 SDValue(CurDAG->getMachineNode(PPC::SUBFC8, dl, MVT::i64, MVT::Glue,
3351 SDValue(CurDAG->getMachineNode(PPC::ADDE8, dl, MVT::i64,
3352 SRDINode, SRADINode, SUBFC8Carry), 0);
3354 SDValue(CurDAG->getMachineNode(PPC::XORI8, dl, MVT::i64,
3355 ADDE8Node, S->getI64Imm(1, dl)), 0);
3356 return SDValue(CurDAG->getMachineNode(PPC::NEG8, dl, MVT::i64,
3360 // {subc.reg, subc.CA} = (subcarry %a, %b)
3361 // (sext (setcc %a, %b, setuge)) -> ~(sube %b, %b, subc.CA)
3362 std::swap(LHS, RHS);
3365 // {subc.reg, subc.CA} = (subcarry %b, %a)
3366 // (sext (setcc %a, %b, setule)) -> ~(sube %a, %a, subc.CA)
3367 SDValue SubtractCarry =
3368 SDValue(CurDAG->getMachineNode(PPC::SUBFC8, dl, MVT::i64, MVT::Glue,
3371 SDValue(CurDAG->getMachineNode(PPC::SUBFE8, dl, MVT::i64, MVT::Glue, LHS,
3372 LHS, SubtractCarry), 0);
3373 return SDValue(CurDAG->getMachineNode(PPC::NOR8, dl, MVT::i64,
3374 ExtSub, ExtSub), 0);
3377 // {subc.reg, subc.CA} = (subcarry %b, %a)
3378 // (sext (setcc %a, %b, setugt)) -> (sube %b, %b, subc.CA)
3379 std::swap(LHS, RHS);
3382 // {subc.reg, subc.CA} = (subcarry %a, %b)
3383 // (sext (setcc %a, %b, setult)) -> (sube %a, %a, subc.CA)
3385 SDValue(CurDAG->getMachineNode(PPC::SUBFC8, dl, MVT::i64, MVT::Glue,
3387 return SDValue(CurDAG->getMachineNode(PPC::SUBFE8, dl, MVT::i64,
3388 LHS, LHS, SubCarry), 0);
3393 /// Do all uses of this SDValue need the result in a GPR?
3394 /// This is meant to be used on values that have type i1 since
3395 /// it is somewhat meaningless to ask if values of other types
3396 /// should be kept in GPR's.
3397 static bool allUsesExtend(SDValue Compare, SelectionDAG *CurDAG) {
3398 assert(Compare.getOpcode() == ISD::SETCC &&
3399 "An ISD::SETCC node required here.");
3401 // For values that have a single use, the caller should obviously already have
3402 // checked if that use is an extending use. We check the other uses here.
3403 if (Compare.hasOneUse())
3405 // We want the value in a GPR if it is being extended, used for a select, or
3406 // used in logical operations.
3407 for (auto CompareUse : Compare.getNode()->uses())
3408 if (CompareUse->getOpcode() != ISD::SIGN_EXTEND &&
3409 CompareUse->getOpcode() != ISD::ZERO_EXTEND &&
3410 CompareUse->getOpcode() != ISD::SELECT &&
3411 !isLogicOp(CompareUse->getOpcode())) {
3412 OmittedForNonExtendUses++;
3418 /// Returns an equivalent of a SETCC node but with the result the same width as
3419 /// the inputs. This can also be used for SELECT_CC if either the true or false
3420 /// values is a power of two while the other is zero.
3421 SDValue IntegerCompareEliminator::getSETCCInGPR(SDValue Compare,
3422 SetccInGPROpts ConvOpts) {
3423 assert((Compare.getOpcode() == ISD::SETCC ||
3424 Compare.getOpcode() == ISD::SELECT_CC) &&
3425 "An ISD::SETCC node required here.");
3427 // Don't convert this comparison to a GPR sequence because there are uses
3428 // of the i1 result (i.e. uses that require the result in the CR).
3429 if ((Compare.getOpcode() == ISD::SETCC) && !allUsesExtend(Compare, CurDAG))
3432 SDValue LHS = Compare.getOperand(0);
3433 SDValue RHS = Compare.getOperand(1);
3435 // The condition code is operand 2 for SETCC and operand 4 for SELECT_CC.
3436 int CCOpNum = Compare.getOpcode() == ISD::SELECT_CC ? 4 : 2;
3438 cast<CondCodeSDNode>(Compare.getOperand(CCOpNum))->get();
3439 EVT InputVT = LHS.getValueType();
3440 if (InputVT != MVT::i32 && InputVT != MVT::i64)
3443 if (ConvOpts == SetccInGPROpts::ZExtInvert ||
3444 ConvOpts == SetccInGPROpts::SExtInvert)
3445 CC = ISD::getSetCCInverse(CC, true);
3447 bool Inputs32Bit = InputVT == MVT::i32;
3450 ConstantSDNode *RHSConst = dyn_cast<ConstantSDNode>(RHS);
3451 int64_t RHSValue = RHSConst ? RHSConst->getSExtValue() : INT64_MAX;
3452 bool IsSext = ConvOpts == SetccInGPROpts::SExtOrig ||
3453 ConvOpts == SetccInGPROpts::SExtInvert;
3455 if (IsSext && Inputs32Bit)
3456 return get32BitSExtCompare(LHS, RHS, CC, RHSValue, dl);
3457 else if (Inputs32Bit)
3458 return get32BitZExtCompare(LHS, RHS, CC, RHSValue, dl);
3460 return get64BitSExtCompare(LHS, RHS, CC, RHSValue, dl);
3461 return get64BitZExtCompare(LHS, RHS, CC, RHSValue, dl);
3464 } // end anonymous namespace
3466 bool PPCDAGToDAGISel::tryIntCompareInGPR(SDNode *N) {
3467 if (N->getValueType(0) != MVT::i32 &&
3468 N->getValueType(0) != MVT::i64)
3471 // This optimization will emit code that assumes 64-bit registers
3472 // so we don't want to run it in 32-bit mode. Also don't run it
3473 // on functions that are not to be optimized.
3474 if (TM.getOptLevel() == CodeGenOpt::None || !TM.isPPC64())
3477 switch (N->getOpcode()) {
3479 case ISD::ZERO_EXTEND:
3480 case ISD::SIGN_EXTEND:
3484 IntegerCompareEliminator ICmpElim(CurDAG, this);
3485 if (SDNode *New = ICmpElim.Select(N)) {
3486 ReplaceNode(N, New);
3494 bool PPCDAGToDAGISel::tryBitPermutation(SDNode *N) {
3495 if (N->getValueType(0) != MVT::i32 &&
3496 N->getValueType(0) != MVT::i64)
3499 if (!UseBitPermRewriter)
3502 switch (N->getOpcode()) {
3509 BitPermutationSelector BPS(CurDAG);
3510 if (SDNode *New = BPS.Select(N)) {
3511 ReplaceNode(N, New);
3521 /// SelectCC - Select a comparison of the specified values with the specified
3522 /// condition code, returning the CR# of the expression.
3523 SDValue PPCDAGToDAGISel::SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC,
3525 // Always select the LHS.
3528 if (LHS.getValueType() == MVT::i32) {
3530 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
3531 if (isInt32Immediate(RHS, Imm)) {
3532 // SETEQ/SETNE comparison with 16-bit immediate, fold it.
3533 if (isUInt<16>(Imm))
3534 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, LHS,
3535 getI32Imm(Imm & 0xFFFF, dl)),
3537 // If this is a 16-bit signed immediate, fold it.
3538 if (isInt<16>((int)Imm))
3539 return SDValue(CurDAG->getMachineNode(PPC::CMPWI, dl, MVT::i32, LHS,
3540 getI32Imm(Imm & 0xFFFF, dl)),
3543 // For non-equality comparisons, the default code would materialize the
3544 // constant, then compare against it, like this:
3546 // ori r2, r2, 22136
3548 // Since we are just comparing for equality, we can emit this instead:
3549 // xoris r0,r3,0x1234
3550 // cmplwi cr0,r0,0x5678
3552 SDValue Xor(CurDAG->getMachineNode(PPC::XORIS, dl, MVT::i32, LHS,
3553 getI32Imm(Imm >> 16, dl)), 0);
3554 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, Xor,
3555 getI32Imm(Imm & 0xFFFF, dl)), 0);
3558 } else if (ISD::isUnsignedIntSetCC(CC)) {
3559 if (isInt32Immediate(RHS, Imm) && isUInt<16>(Imm))
3560 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, LHS,
3561 getI32Imm(Imm & 0xFFFF, dl)), 0);
3565 if (isIntS16Immediate(RHS, SImm))
3566 return SDValue(CurDAG->getMachineNode(PPC::CMPWI, dl, MVT::i32, LHS,
3567 getI32Imm((int)SImm & 0xFFFF,
3572 } else if (LHS.getValueType() == MVT::i64) {
3574 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
3575 if (isInt64Immediate(RHS.getNode(), Imm)) {
3576 // SETEQ/SETNE comparison with 16-bit immediate, fold it.
3577 if (isUInt<16>(Imm))
3578 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, LHS,
3579 getI32Imm(Imm & 0xFFFF, dl)),
3581 // If this is a 16-bit signed immediate, fold it.
3583 return SDValue(CurDAG->getMachineNode(PPC::CMPDI, dl, MVT::i64, LHS,
3584 getI32Imm(Imm & 0xFFFF, dl)),
3587 // For non-equality comparisons, the default code would materialize the
3588 // constant, then compare against it, like this:
3590 // ori r2, r2, 22136
3592 // Since we are just comparing for equality, we can emit this instead:
3593 // xoris r0,r3,0x1234
3594 // cmpldi cr0,r0,0x5678
3596 if (isUInt<32>(Imm)) {
3597 SDValue Xor(CurDAG->getMachineNode(PPC::XORIS8, dl, MVT::i64, LHS,
3598 getI64Imm(Imm >> 16, dl)), 0);
3599 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, Xor,
3600 getI64Imm(Imm & 0xFFFF, dl)),
3605 } else if (ISD::isUnsignedIntSetCC(CC)) {
3606 if (isInt64Immediate(RHS.getNode(), Imm) && isUInt<16>(Imm))
3607 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, LHS,
3608 getI64Imm(Imm & 0xFFFF, dl)), 0);
3612 if (isIntS16Immediate(RHS, SImm))
3613 return SDValue(CurDAG->getMachineNode(PPC::CMPDI, dl, MVT::i64, LHS,
3614 getI64Imm(SImm & 0xFFFF, dl)),
3618 } else if (LHS.getValueType() == MVT::f32) {
3619 if (PPCSubTarget->hasSPE()) {
3624 Opc = PPC::EFSCMPEQ;
3632 Opc = PPC::EFSCMPLT;
3640 Opc = PPC::EFSCMPGT;
3645 } else if (LHS.getValueType() == MVT::f64) {
3646 if (PPCSubTarget->hasSPE()) {
3651 Opc = PPC::EFDCMPEQ;
3659 Opc = PPC::EFDCMPLT;
3667 Opc = PPC::EFDCMPGT;
3671 Opc = PPCSubTarget->hasVSX() ? PPC::XSCMPUDP : PPC::FCMPUD;
3673 assert(LHS.getValueType() == MVT::f128 && "Unknown vt!");
3674 assert(PPCSubTarget->hasVSX() && "__float128 requires VSX");
3675 Opc = PPC::XSCMPUQP;
3677 return SDValue(CurDAG->getMachineNode(Opc, dl, MVT::i32, LHS, RHS), 0);
3680 static PPC::Predicate getPredicateForSetCC(ISD::CondCode CC) {
3686 llvm_unreachable("Should be lowered by legalize!");
3687 default: llvm_unreachable("Unknown condition!");
3689 case ISD::SETEQ: return PPC::PRED_EQ;
3691 case ISD::SETNE: return PPC::PRED_NE;
3693 case ISD::SETLT: return PPC::PRED_LT;
3695 case ISD::SETLE: return PPC::PRED_LE;
3697 case ISD::SETGT: return PPC::PRED_GT;
3699 case ISD::SETGE: return PPC::PRED_GE;
3700 case ISD::SETO: return PPC::PRED_NU;
3701 case ISD::SETUO: return PPC::PRED_UN;
3702 // These two are invalid for floating point. Assume we have int.
3703 case ISD::SETULT: return PPC::PRED_LT;
3704 case ISD::SETUGT: return PPC::PRED_GT;
3708 /// getCRIdxForSetCC - Return the index of the condition register field
3709 /// associated with the SetCC condition, and whether or not the field is
3710 /// treated as inverted. That is, lt = 0; ge = 0 inverted.
3711 static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool &Invert) {
3714 default: llvm_unreachable("Unknown condition!");
3716 case ISD::SETLT: return 0; // Bit #0 = SETOLT
3718 case ISD::SETGT: return 1; // Bit #1 = SETOGT
3720 case ISD::SETEQ: return 2; // Bit #2 = SETOEQ
3721 case ISD::SETUO: return 3; // Bit #3 = SETUO
3723 case ISD::SETGE: Invert = true; return 0; // !Bit #0 = SETUGE
3725 case ISD::SETLE: Invert = true; return 1; // !Bit #1 = SETULE
3727 case ISD::SETNE: Invert = true; return 2; // !Bit #2 = SETUNE
3728 case ISD::SETO: Invert = true; return 3; // !Bit #3 = SETO
3733 llvm_unreachable("Invalid branch code: should be expanded by legalize");
3734 // These are invalid for floating point. Assume integer.
3735 case ISD::SETULT: return 0;
3736 case ISD::SETUGT: return 1;
3740 // getVCmpInst: return the vector compare instruction for the specified
3741 // vector type and condition code. Since this is for altivec specific code,
3742 // only support the altivec types (v16i8, v8i16, v4i32, v2i64, and v4f32).
3743 static unsigned int getVCmpInst(MVT VecVT, ISD::CondCode CC,
3744 bool HasVSX, bool &Swap, bool &Negate) {
3748 if (VecVT.isFloatingPoint()) {
3749 /* Handle some cases by swapping input operands. */
3751 case ISD::SETLE: CC = ISD::SETGE; Swap = true; break;
3752 case ISD::SETLT: CC = ISD::SETGT; Swap = true; break;
3753 case ISD::SETOLE: CC = ISD::SETOGE; Swap = true; break;
3754 case ISD::SETOLT: CC = ISD::SETOGT; Swap = true; break;
3755 case ISD::SETUGE: CC = ISD::SETULE; Swap = true; break;
3756 case ISD::SETUGT: CC = ISD::SETULT; Swap = true; break;
3759 /* Handle some cases by negating the result. */
3761 case ISD::SETNE: CC = ISD::SETEQ; Negate = true; break;
3762 case ISD::SETUNE: CC = ISD::SETOEQ; Negate = true; break;
3763 case ISD::SETULE: CC = ISD::SETOGT; Negate = true; break;
3764 case ISD::SETULT: CC = ISD::SETOGE; Negate = true; break;
3767 /* We have instructions implementing the remaining cases. */
3771 if (VecVT == MVT::v4f32)
3772 return HasVSX ? PPC::XVCMPEQSP : PPC::VCMPEQFP;
3773 else if (VecVT == MVT::v2f64)
3774 return PPC::XVCMPEQDP;
3778 if (VecVT == MVT::v4f32)
3779 return HasVSX ? PPC::XVCMPGTSP : PPC::VCMPGTFP;
3780 else if (VecVT == MVT::v2f64)
3781 return PPC::XVCMPGTDP;
3785 if (VecVT == MVT::v4f32)
3786 return HasVSX ? PPC::XVCMPGESP : PPC::VCMPGEFP;
3787 else if (VecVT == MVT::v2f64)
3788 return PPC::XVCMPGEDP;
3793 llvm_unreachable("Invalid floating-point vector compare condition");
3795 /* Handle some cases by swapping input operands. */
3797 case ISD::SETGE: CC = ISD::SETLE; Swap = true; break;
3798 case ISD::SETLT: CC = ISD::SETGT; Swap = true; break;
3799 case ISD::SETUGE: CC = ISD::SETULE; Swap = true; break;
3800 case ISD::SETULT: CC = ISD::SETUGT; Swap = true; break;
3803 /* Handle some cases by negating the result. */
3805 case ISD::SETNE: CC = ISD::SETEQ; Negate = true; break;
3806 case ISD::SETUNE: CC = ISD::SETUEQ; Negate = true; break;
3807 case ISD::SETLE: CC = ISD::SETGT; Negate = true; break;
3808 case ISD::SETULE: CC = ISD::SETUGT; Negate = true; break;
3811 /* We have instructions implementing the remaining cases. */
3815 if (VecVT == MVT::v16i8)
3816 return PPC::VCMPEQUB;
3817 else if (VecVT == MVT::v8i16)
3818 return PPC::VCMPEQUH;
3819 else if (VecVT == MVT::v4i32)
3820 return PPC::VCMPEQUW;
3821 else if (VecVT == MVT::v2i64)
3822 return PPC::VCMPEQUD;
3825 if (VecVT == MVT::v16i8)
3826 return PPC::VCMPGTSB;
3827 else if (VecVT == MVT::v8i16)
3828 return PPC::VCMPGTSH;
3829 else if (VecVT == MVT::v4i32)
3830 return PPC::VCMPGTSW;
3831 else if (VecVT == MVT::v2i64)
3832 return PPC::VCMPGTSD;
3835 if (VecVT == MVT::v16i8)
3836 return PPC::VCMPGTUB;
3837 else if (VecVT == MVT::v8i16)
3838 return PPC::VCMPGTUH;
3839 else if (VecVT == MVT::v4i32)
3840 return PPC::VCMPGTUW;
3841 else if (VecVT == MVT::v2i64)
3842 return PPC::VCMPGTUD;
3847 llvm_unreachable("Invalid integer vector compare condition");
3851 bool PPCDAGToDAGISel::trySETCC(SDNode *N) {
3854 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
3856 CurDAG->getTargetLoweringInfo().getPointerTy(CurDAG->getDataLayout());
3857 bool isPPC64 = (PtrVT == MVT::i64);
3859 if (!PPCSubTarget->useCRBits() &&
3860 isInt32Immediate(N->getOperand(1), Imm)) {
3861 // We can codegen setcc op, imm very efficiently compared to a brcond.
3862 // Check for those cases here.
3865 SDValue Op = N->getOperand(0);
3869 Op = SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, Op), 0);
3870 SDValue Ops[] = { Op, getI32Imm(27, dl), getI32Imm(5, dl),
3871 getI32Imm(31, dl) };
3872 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
3878 SDValue(CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
3879 Op, getI32Imm(~0U, dl)), 0);
3880 CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op, AD.getValue(1));
3884 SDValue Ops[] = { Op, getI32Imm(1, dl), getI32Imm(31, dl),
3885 getI32Imm(31, dl) };
3886 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
3891 SDValue(CurDAG->getMachineNode(PPC::NEG, dl, MVT::i32, Op), 0);
3892 T = SDValue(CurDAG->getMachineNode(PPC::ANDC, dl, MVT::i32, T, Op), 0);
3893 SDValue Ops[] = { T, getI32Imm(1, dl), getI32Imm(31, dl),
3894 getI32Imm(31, dl) };
3895 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
3899 } else if (Imm == ~0U) { // setcc op, -1
3900 SDValue Op = N->getOperand(0);
3905 Op = SDValue(CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
3906 Op, getI32Imm(1, dl)), 0);
3907 CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
3908 SDValue(CurDAG->getMachineNode(PPC::LI, dl,
3911 0), Op.getValue(1));
3915 Op = SDValue(CurDAG->getMachineNode(PPC::NOR, dl, MVT::i32, Op, Op), 0);
3916 SDNode *AD = CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
3917 Op, getI32Imm(~0U, dl));
3918 CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDValue(AD, 0), Op,
3923 SDValue AD = SDValue(CurDAG->getMachineNode(PPC::ADDI, dl, MVT::i32, Op,
3924 getI32Imm(1, dl)), 0);
3925 SDValue AN = SDValue(CurDAG->getMachineNode(PPC::AND, dl, MVT::i32, AD,
3927 SDValue Ops[] = { AN, getI32Imm(1, dl), getI32Imm(31, dl),
3928 getI32Imm(31, dl) };
3929 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
3933 SDValue Ops[] = { Op, getI32Imm(1, dl), getI32Imm(31, dl),
3934 getI32Imm(31, dl) };
3935 Op = SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops), 0);
3936 CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op, getI32Imm(1, dl));
3943 SDValue LHS = N->getOperand(0);
3944 SDValue RHS = N->getOperand(1);
3946 // Altivec Vector compare instructions do not set any CR register by default and
3947 // vector compare operations return the same type as the operands.
3948 if (LHS.getValueType().isVector()) {
3949 if (PPCSubTarget->hasQPX() || PPCSubTarget->hasSPE())
3952 EVT VecVT = LHS.getValueType();
3954 unsigned int VCmpInst = getVCmpInst(VecVT.getSimpleVT(), CC,
3955 PPCSubTarget->hasVSX(), Swap, Negate);
3957 std::swap(LHS, RHS);
3959 EVT ResVT = VecVT.changeVectorElementTypeToInteger();
3961 SDValue VCmp(CurDAG->getMachineNode(VCmpInst, dl, ResVT, LHS, RHS), 0);
3962 CurDAG->SelectNodeTo(N, PPCSubTarget->hasVSX() ? PPC::XXLNOR : PPC::VNOR,
3967 CurDAG->SelectNodeTo(N, VCmpInst, ResVT, LHS, RHS);
3971 if (PPCSubTarget->useCRBits())
3975 unsigned Idx = getCRIdxForSetCC(CC, Inv);
3976 SDValue CCReg = SelectCC(LHS, RHS, CC, dl);
3979 // SPE e*cmp* instructions only set the 'gt' bit, so hard-code that
3980 // The correct compare instruction is already set by SelectCC()
3981 if (PPCSubTarget->hasSPE() && LHS.getValueType().isFloatingPoint()) {
3985 // Force the ccreg into CR7.
3986 SDValue CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32);
3988 SDValue InFlag(nullptr, 0); // Null incoming flag value.
3989 CCReg = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, CR7Reg, CCReg,
3990 InFlag).getValue(1);
3992 IntCR = SDValue(CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32, CR7Reg,
3995 SDValue Ops[] = { IntCR, getI32Imm((32 - (3 - Idx)) & 31, dl),
3996 getI32Imm(31, dl), getI32Imm(31, dl) };
3998 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
4002 // Get the specified bit.
4004 SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops), 0);
4005 CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1, dl));
4009 /// Does this node represent a load/store node whose address can be represented
4010 /// with a register plus an immediate that's a multiple of \p Val:
4011 bool PPCDAGToDAGISel::isOffsetMultipleOf(SDNode *N, unsigned Val) const {
4012 LoadSDNode *LDN = dyn_cast<LoadSDNode>(N);
4013 StoreSDNode *STN = dyn_cast<StoreSDNode>(N);
4016 AddrOp = LDN->getOperand(1);
4018 AddrOp = STN->getOperand(2);
4020 // If the address points a frame object or a frame object with an offset,
4021 // we need to check the object alignment.
4023 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(
4024 AddrOp.getOpcode() == ISD::ADD ? AddrOp.getOperand(0) :
4026 // If op0 is a frame index that is under aligned, we can't do it either,
4027 // because it is translated to r31 or r1 + slot + offset. We won't know the
4028 // slot number until the stack frame is finalized.
4029 const MachineFrameInfo &MFI = CurDAG->getMachineFunction().getFrameInfo();
4030 unsigned SlotAlign = MFI.getObjectAlignment(FI->getIndex());
4031 if ((SlotAlign % Val) != 0)
4034 // If we have an offset, we need further check on the offset.
4035 if (AddrOp.getOpcode() != ISD::ADD)
4039 if (AddrOp.getOpcode() == ISD::ADD)
4040 return isIntS16Immediate(AddrOp.getOperand(1), Imm) && !(Imm % Val);
4042 // If the address comes from the outside, the offset will be zero.
4043 return AddrOp.getOpcode() == ISD::CopyFromReg;
4046 void PPCDAGToDAGISel::transferMemOperands(SDNode *N, SDNode *Result) {
4047 // Transfer memoperands.
4048 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
4049 MemOp[0] = cast<MemSDNode>(N)->getMemOperand();
4050 cast<MachineSDNode>(Result)->setMemRefs(MemOp, MemOp + 1);
4053 /// This method returns a node after flipping the MSB of each element
4054 /// of vector integer type. Additionally, if SignBitVec is non-null,
4055 /// this method sets a node with one at MSB of all elements
4056 /// and zero at other bits in SignBitVec.
4058 PPCDAGToDAGISel::flipSignBit(const SDValue &N, SDNode **SignBitVec) {
4060 EVT VecVT = N.getValueType();
4061 if (VecVT == MVT::v4i32) {
4063 SDNode *ZV = CurDAG->getMachineNode(PPC::V_SET0, dl, MVT::v4i32);
4064 *SignBitVec = CurDAG->getMachineNode(PPC::XVNEGSP, dl, VecVT,
4067 return CurDAG->getMachineNode(PPC::XVNEGSP, dl, VecVT, N);
4069 else if (VecVT == MVT::v8i16) {
4070 SDNode *Hi = CurDAG->getMachineNode(PPC::LIS, dl, MVT::i32,
4071 getI32Imm(0x8000, dl));
4072 SDNode *ScaImm = CurDAG->getMachineNode(PPC::ORI, dl, MVT::i32,
4074 getI32Imm(0x8000, dl));
4075 SDNode *VecImm = CurDAG->getMachineNode(PPC::MTVSRWS, dl, VecVT,
4076 SDValue(ScaImm, 0));
4078 Alternatively, we can do this as follow to use VRF instead of GPR.
4083 if (SignBitVec) *SignBitVec = VecImm;
4084 return CurDAG->getMachineNode(PPC::VADDUHM, dl, VecVT, N,
4085 SDValue(VecImm, 0));
4087 else if (VecVT == MVT::v16i8) {
4088 SDNode *VecImm = CurDAG->getMachineNode(PPC::XXSPLTIB, dl, MVT::i32,
4089 getI32Imm(0x80, dl));
4090 if (SignBitVec) *SignBitVec = VecImm;
4091 return CurDAG->getMachineNode(PPC::VADDUBM, dl, VecVT, N,
4092 SDValue(VecImm, 0));
4095 llvm_unreachable("Unsupported vector data type for flipSignBit");
4098 // Select - Convert the specified operand from a target-independent to a
4099 // target-specific node if it hasn't already been changed.
4100 void PPCDAGToDAGISel::Select(SDNode *N) {
4102 if (N->isMachineOpcode()) {
4104 return; // Already selected.
4107 // In case any misguided DAG-level optimizations form an ADD with a
4108 // TargetConstant operand, crash here instead of miscompiling (by selecting
4109 // an r+r add instead of some kind of r+i add).
4110 if (N->getOpcode() == ISD::ADD &&
4111 N->getOperand(1).getOpcode() == ISD::TargetConstant)
4112 llvm_unreachable("Invalid ADD with TargetConstant operand");
4114 // Try matching complex bit permutations before doing anything else.
4115 if (tryBitPermutation(N))
4118 // Try to emit integer compares as GPR-only sequences (i.e. no use of CR).
4119 if (tryIntCompareInGPR(N))
4122 switch (N->getOpcode()) {
4126 if (N->getValueType(0) == MVT::i64) {
4127 ReplaceNode(N, selectI64Imm(CurDAG, N));
4137 case PPCISD::CALL: {
4138 const Module *M = MF->getFunction().getParent();
4140 if (PPCLowering->getPointerTy(CurDAG->getDataLayout()) != MVT::i32 ||
4141 !PPCSubTarget->isSecurePlt() || !PPCSubTarget->isTargetELF() ||
4142 M->getPICLevel() == PICLevel::SmallPIC)
4145 SDValue Op = N->getOperand(1);
4147 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op)) {
4148 if (GA->getTargetFlags() == PPCII::MO_PLT)
4151 else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) {
4152 if (ES->getTargetFlags() == PPCII::MO_PLT)
4158 case PPCISD::GlobalBaseReg:
4159 ReplaceNode(N, getGlobalBaseReg());
4162 case ISD::FrameIndex:
4163 selectFrameIndex(N, N);
4166 case PPCISD::MFOCRF: {
4167 SDValue InFlag = N->getOperand(1);
4168 ReplaceNode(N, CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32,
4169 N->getOperand(0), InFlag));
4173 case PPCISD::READ_TIME_BASE:
4174 ReplaceNode(N, CurDAG->getMachineNode(PPC::ReadTB, dl, MVT::i32, MVT::i32,
4175 MVT::Other, N->getOperand(0)));
4178 case PPCISD::SRA_ADDZE: {
4179 SDValue N0 = N->getOperand(0);
4181 CurDAG->getTargetConstant(*cast<ConstantSDNode>(N->getOperand(1))->
4182 getConstantIntValue(), dl,
4183 N->getValueType(0));
4184 if (N->getValueType(0) == MVT::i64) {
4186 CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, MVT::Glue,
4188 CurDAG->SelectNodeTo(N, PPC::ADDZE8, MVT::i64, SDValue(Op, 0),
4192 assert(N->getValueType(0) == MVT::i32 &&
4193 "Expecting i64 or i32 in PPCISD::SRA_ADDZE");
4195 CurDAG->getMachineNode(PPC::SRAWI, dl, MVT::i32, MVT::Glue,
4197 CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32, SDValue(Op, 0),
4204 // Change TLS initial-exec D-form stores to X-form stores.
4205 StoreSDNode *ST = cast<StoreSDNode>(N);
4206 if (EnableTLSOpt && PPCSubTarget->isELFv2ABI() &&
4207 ST->getAddressingMode() != ISD::PRE_INC)
4208 if (tryTLSXFormStore(ST))
4213 // Handle preincrement loads.
4214 LoadSDNode *LD = cast<LoadSDNode>(N);
4215 EVT LoadedVT = LD->getMemoryVT();
4217 // Normal loads are handled by code generated from the .td file.
4218 if (LD->getAddressingMode() != ISD::PRE_INC) {
4219 // Change TLS initial-exec D-form loads to X-form loads.
4220 if (EnableTLSOpt && PPCSubTarget->isELFv2ABI())
4221 if (tryTLSXFormLoad(LD))
4226 SDValue Offset = LD->getOffset();
4227 if (Offset.getOpcode() == ISD::TargetConstant ||
4228 Offset.getOpcode() == ISD::TargetGlobalAddress) {
4231 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD;
4232 if (LD->getValueType(0) != MVT::i64) {
4233 // Handle PPC32 integer and normal FP loads.
4234 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
4235 switch (LoadedVT.getSimpleVT().SimpleTy) {
4236 default: llvm_unreachable("Invalid PPC load type!");
4237 case MVT::f64: Opcode = PPC::LFDU; break;
4238 case MVT::f32: Opcode = PPC::LFSU; break;
4239 case MVT::i32: Opcode = PPC::LWZU; break;
4240 case MVT::i16: Opcode = isSExt ? PPC::LHAU : PPC::LHZU; break;
4242 case MVT::i8: Opcode = PPC::LBZU; break;
4245 assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!");
4246 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
4247 switch (LoadedVT.getSimpleVT().SimpleTy) {
4248 default: llvm_unreachable("Invalid PPC load type!");
4249 case MVT::i64: Opcode = PPC::LDU; break;
4250 case MVT::i32: Opcode = PPC::LWZU8; break;
4251 case MVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; break;
4253 case MVT::i8: Opcode = PPC::LBZU8; break;
4257 SDValue Chain = LD->getChain();
4258 SDValue Base = LD->getBasePtr();
4259 SDValue Ops[] = { Offset, Base, Chain };
4260 SDNode *MN = CurDAG->getMachineNode(
4261 Opcode, dl, LD->getValueType(0),
4262 PPCLowering->getPointerTy(CurDAG->getDataLayout()), MVT::Other, Ops);
4263 transferMemOperands(N, MN);
4268 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD;
4269 if (LD->getValueType(0) != MVT::i64) {
4270 // Handle PPC32 integer and normal FP loads.
4271 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
4272 switch (LoadedVT.getSimpleVT().SimpleTy) {
4273 default: llvm_unreachable("Invalid PPC load type!");
4274 case MVT::v4f64: Opcode = PPC::QVLFDUX; break; // QPX
4275 case MVT::v4f32: Opcode = PPC::QVLFSUX; break; // QPX
4276 case MVT::f64: Opcode = PPC::LFDUX; break;
4277 case MVT::f32: Opcode = PPC::LFSUX; break;
4278 case MVT::i32: Opcode = PPC::LWZUX; break;
4279 case MVT::i16: Opcode = isSExt ? PPC::LHAUX : PPC::LHZUX; break;
4281 case MVT::i8: Opcode = PPC::LBZUX; break;
4284 assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!");
4285 assert((!isSExt || LoadedVT == MVT::i16 || LoadedVT == MVT::i32) &&
4286 "Invalid sext update load");
4287 switch (LoadedVT.getSimpleVT().SimpleTy) {
4288 default: llvm_unreachable("Invalid PPC load type!");
4289 case MVT::i64: Opcode = PPC::LDUX; break;
4290 case MVT::i32: Opcode = isSExt ? PPC::LWAUX : PPC::LWZUX8; break;
4291 case MVT::i16: Opcode = isSExt ? PPC::LHAUX8 : PPC::LHZUX8; break;
4293 case MVT::i8: Opcode = PPC::LBZUX8; break;
4297 SDValue Chain = LD->getChain();
4298 SDValue Base = LD->getBasePtr();
4299 SDValue Ops[] = { Base, Offset, Chain };
4300 SDNode *MN = CurDAG->getMachineNode(
4301 Opcode, dl, LD->getValueType(0),
4302 PPCLowering->getPointerTy(CurDAG->getDataLayout()), MVT::Other, Ops);
4303 transferMemOperands(N, MN);
4310 unsigned Imm, Imm2, SH, MB, ME;
4313 // If this is an and of a value rotated between 0 and 31 bits and then and'd
4314 // with a mask, emit rlwinm
4315 if (isInt32Immediate(N->getOperand(1), Imm) &&
4316 isRotateAndMask(N->getOperand(0).getNode(), Imm, false, SH, MB, ME)) {
4317 SDValue Val = N->getOperand(0).getOperand(0);
4318 SDValue Ops[] = { Val, getI32Imm(SH, dl), getI32Imm(MB, dl),
4319 getI32Imm(ME, dl) };
4320 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
4323 // If this is just a masked value where the input is not handled above, and
4324 // is not a rotate-left (handled by a pattern in the .td file), emit rlwinm
4325 if (isInt32Immediate(N->getOperand(1), Imm) &&
4326 isRunOfOnes(Imm, MB, ME) &&
4327 N->getOperand(0).getOpcode() != ISD::ROTL) {
4328 SDValue Val = N->getOperand(0);
4329 SDValue Ops[] = { Val, getI32Imm(0, dl), getI32Imm(MB, dl),
4330 getI32Imm(ME, dl) };
4331 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
4334 // If this is a 64-bit zero-extension mask, emit rldicl.
4335 if (isInt64Immediate(N->getOperand(1).getNode(), Imm64) &&
4337 SDValue Val = N->getOperand(0);
4338 MB = 64 - countTrailingOnes(Imm64);
4341 if (Val.getOpcode() == ISD::ANY_EXTEND) {
4342 auto Op0 = Val.getOperand(0);
4343 if ( Op0.getOpcode() == ISD::SRL &&
4344 isInt32Immediate(Op0.getOperand(1).getNode(), Imm) && Imm <= MB) {
4346 auto ResultType = Val.getNode()->getValueType(0);
4347 auto ImDef = CurDAG->getMachineNode(PPC::IMPLICIT_DEF, dl,
4349 SDValue IDVal (ImDef, 0);
4351 Val = SDValue(CurDAG->getMachineNode(PPC::INSERT_SUBREG, dl,
4352 ResultType, IDVal, Op0.getOperand(0),
4353 getI32Imm(1, dl)), 0);
4358 // If the operand is a logical right shift, we can fold it into this
4359 // instruction: rldicl(rldicl(x, 64-n, n), 0, mb) -> rldicl(x, 64-n, mb)
4360 // for n <= mb. The right shift is really a left rotate followed by a
4361 // mask, and this mask is a more-restrictive sub-mask of the mask implied
4363 if (Val.getOpcode() == ISD::SRL &&
4364 isInt32Immediate(Val.getOperand(1).getNode(), Imm) && Imm <= MB) {
4365 assert(Imm < 64 && "Illegal shift amount");
4366 Val = Val.getOperand(0);
4370 SDValue Ops[] = { Val, getI32Imm(SH, dl), getI32Imm(MB, dl) };
4371 CurDAG->SelectNodeTo(N, PPC::RLDICL, MVT::i64, Ops);
4374 // If this is a negated 64-bit zero-extension mask,
4375 // i.e. the immediate is a sequence of ones from most significant side
4376 // and all zero for reminder, we should use rldicr.
4377 if (isInt64Immediate(N->getOperand(1).getNode(), Imm64) &&
4378 isMask_64(~Imm64)) {
4379 SDValue Val = N->getOperand(0);
4380 MB = 63 - countTrailingOnes(~Imm64);
4382 SDValue Ops[] = { Val, getI32Imm(SH, dl), getI32Imm(MB, dl) };
4383 CurDAG->SelectNodeTo(N, PPC::RLDICR, MVT::i64, Ops);
4387 // AND X, 0 -> 0, not "rlwinm 32".
4388 if (isInt32Immediate(N->getOperand(1), Imm) && (Imm == 0)) {
4389 ReplaceUses(SDValue(N, 0), N->getOperand(1));
4392 // ISD::OR doesn't get all the bitfield insertion fun.
4393 // (and (or x, c1), c2) where isRunOfOnes(~(c1^c2)) might be a
4395 if (isInt32Immediate(N->getOperand(1), Imm) &&
4396 N->getOperand(0).getOpcode() == ISD::OR &&
4397 isInt32Immediate(N->getOperand(0).getOperand(1), Imm2)) {
4398 // The idea here is to check whether this is equivalent to:
4399 // (c1 & m) | (x & ~m)
4400 // where m is a run-of-ones mask. The logic here is that, for each bit in
4402 // - if both are 1, then the output will be 1.
4403 // - if both are 0, then the output will be 0.
4404 // - if the bit in c1 is 0, and the bit in c2 is 1, then the output will
4406 // - if the bit in c1 is 1, and the bit in c2 is 0, then the output will
4408 // If that last condition is never the case, then we can form m from the
4409 // bits that are the same between c1 and c2.
4411 if (isRunOfOnes(~(Imm^Imm2), MB, ME) && !(~Imm & Imm2)) {
4412 SDValue Ops[] = { N->getOperand(0).getOperand(0),
4413 N->getOperand(0).getOperand(1),
4414 getI32Imm(0, dl), getI32Imm(MB, dl),
4415 getI32Imm(ME, dl) };
4416 ReplaceNode(N, CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops));
4421 // Other cases are autogenerated.
4425 if (N->getValueType(0) == MVT::i32)
4426 if (tryBitfieldInsert(N))
4430 if (N->getOperand(0)->getOpcode() == ISD::FrameIndex &&
4431 isIntS16Immediate(N->getOperand(1), Imm)) {
4433 CurDAG->computeKnownBits(N->getOperand(0), LHSKnown);
4435 // If this is equivalent to an add, then we can fold it with the
4436 // FrameIndex calculation.
4437 if ((LHSKnown.Zero.getZExtValue()|~(uint64_t)Imm) == ~0ULL) {
4438 selectFrameIndex(N, N->getOperand(0).getNode(), (int)Imm);
4443 // OR with a 32-bit immediate can be handled by ori + oris
4444 // without creating an immediate in a GPR.
4446 bool IsPPC64 = PPCSubTarget->isPPC64();
4447 if (IsPPC64 && isInt64Immediate(N->getOperand(1), Imm64) &&
4448 (Imm64 & ~0xFFFFFFFFuLL) == 0) {
4449 // If ImmHi (ImmHi) is zero, only one ori (oris) is generated later.
4450 uint64_t ImmHi = Imm64 >> 16;
4451 uint64_t ImmLo = Imm64 & 0xFFFF;
4452 if (ImmHi != 0 && ImmLo != 0) {
4453 SDNode *Lo = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64,
4455 getI16Imm(ImmLo, dl));
4456 SDValue Ops1[] = { SDValue(Lo, 0), getI16Imm(ImmHi, dl)};
4457 CurDAG->SelectNodeTo(N, PPC::ORIS8, MVT::i64, Ops1);
4462 // Other cases are autogenerated.
4466 // XOR with a 32-bit immediate can be handled by xori + xoris
4467 // without creating an immediate in a GPR.
4469 bool IsPPC64 = PPCSubTarget->isPPC64();
4470 if (IsPPC64 && isInt64Immediate(N->getOperand(1), Imm64) &&
4471 (Imm64 & ~0xFFFFFFFFuLL) == 0) {
4472 // If ImmHi (ImmHi) is zero, only one xori (xoris) is generated later.
4473 uint64_t ImmHi = Imm64 >> 16;
4474 uint64_t ImmLo = Imm64 & 0xFFFF;
4475 if (ImmHi != 0 && ImmLo != 0) {
4476 SDNode *Lo = CurDAG->getMachineNode(PPC::XORI8, dl, MVT::i64,
4478 getI16Imm(ImmLo, dl));
4479 SDValue Ops1[] = { SDValue(Lo, 0), getI16Imm(ImmHi, dl)};
4480 CurDAG->SelectNodeTo(N, PPC::XORIS8, MVT::i64, Ops1);
4489 if (N->getOperand(0)->getOpcode() == ISD::FrameIndex &&
4490 isIntS16Immediate(N->getOperand(1), Imm)) {
4491 selectFrameIndex(N, N->getOperand(0).getNode(), (int)Imm);
4498 unsigned Imm, SH, MB, ME;
4499 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) &&
4500 isRotateAndMask(N, Imm, true, SH, MB, ME)) {
4501 SDValue Ops[] = { N->getOperand(0).getOperand(0),
4502 getI32Imm(SH, dl), getI32Imm(MB, dl),
4503 getI32Imm(ME, dl) };
4504 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
4508 // Other cases are autogenerated.
4512 unsigned Imm, SH, MB, ME;
4513 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) &&
4514 isRotateAndMask(N, Imm, true, SH, MB, ME)) {
4515 SDValue Ops[] = { N->getOperand(0).getOperand(0),
4516 getI32Imm(SH, dl), getI32Imm(MB, dl),
4517 getI32Imm(ME, dl) };
4518 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
4522 // Other cases are autogenerated.
4525 // FIXME: Remove this once the ANDI glue bug is fixed:
4526 case PPCISD::ANDIo_1_EQ_BIT:
4527 case PPCISD::ANDIo_1_GT_BIT: {
4531 EVT InVT = N->getOperand(0).getValueType();
4532 assert((InVT == MVT::i64 || InVT == MVT::i32) &&
4533 "Invalid input type for ANDIo_1_EQ_BIT");
4535 unsigned Opcode = (InVT == MVT::i64) ? PPC::ANDIo8 : PPC::ANDIo;
4536 SDValue AndI(CurDAG->getMachineNode(Opcode, dl, InVT, MVT::Glue,
4538 CurDAG->getTargetConstant(1, dl, InVT)),
4540 SDValue CR0Reg = CurDAG->getRegister(PPC::CR0, MVT::i32);
4542 CurDAG->getTargetConstant(N->getOpcode() == PPCISD::ANDIo_1_EQ_BIT ?
4543 PPC::sub_eq : PPC::sub_gt, dl, MVT::i32);
4545 CurDAG->SelectNodeTo(N, TargetOpcode::EXTRACT_SUBREG, MVT::i1, CR0Reg,
4546 SRIdxVal, SDValue(AndI.getNode(), 1) /* glue */);
4549 case ISD::SELECT_CC: {
4550 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
4552 CurDAG->getTargetLoweringInfo().getPointerTy(CurDAG->getDataLayout());
4553 bool isPPC64 = (PtrVT == MVT::i64);
4555 // If this is a select of i1 operands, we'll pattern match it.
4556 if (PPCSubTarget->useCRBits() &&
4557 N->getOperand(0).getValueType() == MVT::i1)
4560 // Handle the setcc cases here. select_cc lhs, 0, 1, 0, cc
4562 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
4563 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N->getOperand(2)))
4564 if (ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N->getOperand(3)))
4565 if (N1C->isNullValue() && N3C->isNullValue() &&
4566 N2C->getZExtValue() == 1ULL && CC == ISD::SETNE &&
4567 // FIXME: Implement this optzn for PPC64.
4568 N->getValueType(0) == MVT::i32) {
4570 CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
4571 N->getOperand(0), getI32Imm(~0U, dl));
4572 CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDValue(Tmp, 0),
4573 N->getOperand(0), SDValue(Tmp, 1));
4577 SDValue CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC, dl);
4579 if (N->getValueType(0) == MVT::i1) {
4580 // An i1 select is: (c & t) | (!c & f).
4582 unsigned Idx = getCRIdxForSetCC(CC, Inv);
4586 default: llvm_unreachable("Invalid CC index");
4587 case 0: SRI = PPC::sub_lt; break;
4588 case 1: SRI = PPC::sub_gt; break;
4589 case 2: SRI = PPC::sub_eq; break;
4590 case 3: SRI = PPC::sub_un; break;
4593 SDValue CCBit = CurDAG->getTargetExtractSubreg(SRI, dl, MVT::i1, CCReg);
4595 SDValue NotCCBit(CurDAG->getMachineNode(PPC::CRNOR, dl, MVT::i1,
4597 SDValue C = Inv ? NotCCBit : CCBit,
4598 NotC = Inv ? CCBit : NotCCBit;
4600 SDValue CAndT(CurDAG->getMachineNode(PPC::CRAND, dl, MVT::i1,
4601 C, N->getOperand(2)), 0);
4602 SDValue NotCAndF(CurDAG->getMachineNode(PPC::CRAND, dl, MVT::i1,
4603 NotC, N->getOperand(3)), 0);
4605 CurDAG->SelectNodeTo(N, PPC::CROR, MVT::i1, CAndT, NotCAndF);
4609 unsigned BROpc = getPredicateForSetCC(CC);
4611 unsigned SelectCCOp;
4612 if (N->getValueType(0) == MVT::i32)
4613 SelectCCOp = PPC::SELECT_CC_I4;
4614 else if (N->getValueType(0) == MVT::i64)
4615 SelectCCOp = PPC::SELECT_CC_I8;
4616 else if (N->getValueType(0) == MVT::f32) {
4617 if (PPCSubTarget->hasP8Vector())
4618 SelectCCOp = PPC::SELECT_CC_VSSRC;
4619 else if (PPCSubTarget->hasSPE())
4620 SelectCCOp = PPC::SELECT_CC_SPE4;
4622 SelectCCOp = PPC::SELECT_CC_F4;
4623 } else if (N->getValueType(0) == MVT::f64) {
4624 if (PPCSubTarget->hasVSX())
4625 SelectCCOp = PPC::SELECT_CC_VSFRC;
4626 else if (PPCSubTarget->hasSPE())
4627 SelectCCOp = PPC::SELECT_CC_SPE;
4629 SelectCCOp = PPC::SELECT_CC_F8;
4630 } else if (N->getValueType(0) == MVT::f128)
4631 SelectCCOp = PPC::SELECT_CC_F16;
4632 else if (PPCSubTarget->hasSPE())
4633 SelectCCOp = PPC::SELECT_CC_SPE;
4634 else if (PPCSubTarget->hasQPX() && N->getValueType(0) == MVT::v4f64)
4635 SelectCCOp = PPC::SELECT_CC_QFRC;
4636 else if (PPCSubTarget->hasQPX() && N->getValueType(0) == MVT::v4f32)
4637 SelectCCOp = PPC::SELECT_CC_QSRC;
4638 else if (PPCSubTarget->hasQPX() && N->getValueType(0) == MVT::v4i1)
4639 SelectCCOp = PPC::SELECT_CC_QBRC;
4640 else if (N->getValueType(0) == MVT::v2f64 ||
4641 N->getValueType(0) == MVT::v2i64)
4642 SelectCCOp = PPC::SELECT_CC_VSRC;
4644 SelectCCOp = PPC::SELECT_CC_VRRC;
4646 SDValue Ops[] = { CCReg, N->getOperand(2), N->getOperand(3),
4647 getI32Imm(BROpc, dl) };
4648 CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), Ops);
4652 if (PPCSubTarget->hasVSX()) {
4653 SDValue Ops[] = { N->getOperand(2), N->getOperand(1), N->getOperand(0) };
4654 CurDAG->SelectNodeTo(N, PPC::XXSEL, N->getValueType(0), Ops);
4659 case ISD::VECTOR_SHUFFLE:
4660 if (PPCSubTarget->hasVSX() && (N->getValueType(0) == MVT::v2f64 ||
4661 N->getValueType(0) == MVT::v2i64)) {
4662 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
4664 SDValue Op1 = N->getOperand(SVN->getMaskElt(0) < 2 ? 0 : 1),
4665 Op2 = N->getOperand(SVN->getMaskElt(1) < 2 ? 0 : 1);
4668 for (int i = 0; i < 2; ++i)
4669 if (SVN->getMaskElt(i) <= 0 || SVN->getMaskElt(i) == 2)
4674 if (Op1 == Op2 && DM[0] == 0 && DM[1] == 0 &&
4675 Op1.getOpcode() == ISD::SCALAR_TO_VECTOR &&
4676 isa<LoadSDNode>(Op1.getOperand(0))) {
4677 LoadSDNode *LD = cast<LoadSDNode>(Op1.getOperand(0));
4678 SDValue Base, Offset;
4680 if (LD->isUnindexed() && LD->hasOneUse() && Op1.hasOneUse() &&
4681 (LD->getMemoryVT() == MVT::f64 ||
4682 LD->getMemoryVT() == MVT::i64) &&
4683 SelectAddrIdxOnly(LD->getBasePtr(), Base, Offset)) {
4684 SDValue Chain = LD->getChain();
4685 SDValue Ops[] = { Base, Offset, Chain };
4686 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
4687 MemOp[0] = LD->getMemOperand();
4688 SDNode *NewN = CurDAG->SelectNodeTo(N, PPC::LXVDSX,
4689 N->getValueType(0), Ops);
4690 cast<MachineSDNode>(NewN)->setMemRefs(MemOp, MemOp + 1);
4695 // For little endian, we must swap the input operands and adjust
4696 // the mask elements (reverse and invert them).
4697 if (PPCSubTarget->isLittleEndian()) {
4698 std::swap(Op1, Op2);
4699 unsigned tmp = DM[0];
4704 SDValue DMV = CurDAG->getTargetConstant(DM[1] | (DM[0] << 1), dl,
4706 SDValue Ops[] = { Op1, Op2, DMV };
4707 CurDAG->SelectNodeTo(N, PPC::XXPERMDI, N->getValueType(0), Ops);
4714 bool IsPPC64 = PPCSubTarget->isPPC64();
4715 SDValue Ops[] = { N->getOperand(1), N->getOperand(0) };
4716 CurDAG->SelectNodeTo(N, N->getOpcode() == PPCISD::BDNZ
4717 ? (IsPPC64 ? PPC::BDNZ8 : PPC::BDNZ)
4718 : (IsPPC64 ? PPC::BDZ8 : PPC::BDZ),
4722 case PPCISD::COND_BRANCH: {
4723 // Op #0 is the Chain.
4724 // Op #1 is the PPC::PRED_* number.
4726 // Op #3 is the Dest MBB
4727 // Op #4 is the Flag.
4728 // Prevent PPC::PRED_* from being selected into LI.
4729 unsigned PCC = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
4730 if (EnableBranchHint)
4731 PCC |= getBranchHint(PCC, FuncInfo, N->getOperand(3));
4733 SDValue Pred = getI32Imm(PCC, dl);
4734 SDValue Ops[] = { Pred, N->getOperand(2), N->getOperand(3),
4735 N->getOperand(0), N->getOperand(4) };
4736 CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops);
4740 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
4741 unsigned PCC = getPredicateForSetCC(CC);
4743 if (N->getOperand(2).getValueType() == MVT::i1) {
4747 default: llvm_unreachable("Unexpected Boolean-operand predicate");
4748 case PPC::PRED_LT: Opc = PPC::CRANDC; Swap = true; break;
4749 case PPC::PRED_LE: Opc = PPC::CRORC; Swap = true; break;
4750 case PPC::PRED_EQ: Opc = PPC::CREQV; Swap = false; break;
4751 case PPC::PRED_GE: Opc = PPC::CRORC; Swap = false; break;
4752 case PPC::PRED_GT: Opc = PPC::CRANDC; Swap = false; break;
4753 case PPC::PRED_NE: Opc = PPC::CRXOR; Swap = false; break;
4756 SDValue BitComp(CurDAG->getMachineNode(Opc, dl, MVT::i1,
4757 N->getOperand(Swap ? 3 : 2),
4758 N->getOperand(Swap ? 2 : 3)), 0);
4759 CurDAG->SelectNodeTo(N, PPC::BC, MVT::Other, BitComp, N->getOperand(4),
4764 if (EnableBranchHint)
4765 PCC |= getBranchHint(PCC, FuncInfo, N->getOperand(4));
4767 SDValue CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC, dl);
4768 SDValue Ops[] = { getI32Imm(PCC, dl), CondCode,
4769 N->getOperand(4), N->getOperand(0) };
4770 CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops);
4774 // FIXME: Should custom lower this.
4775 SDValue Chain = N->getOperand(0);
4776 SDValue Target = N->getOperand(1);
4777 unsigned Opc = Target.getValueType() == MVT::i32 ? PPC::MTCTR : PPC::MTCTR8;
4778 unsigned Reg = Target.getValueType() == MVT::i32 ? PPC::BCTR : PPC::BCTR8;
4779 Chain = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Glue, Target,
4781 CurDAG->SelectNodeTo(N, Reg, MVT::Other, Chain);
4784 case PPCISD::TOC_ENTRY: {
4785 assert ((PPCSubTarget->isPPC64() || PPCSubTarget->isSVR4ABI()) &&
4786 "Only supported for 64-bit ABI and 32-bit SVR4");
4787 if (PPCSubTarget->isSVR4ABI() && !PPCSubTarget->isPPC64()) {
4788 SDValue GA = N->getOperand(0);
4789 SDNode *MN = CurDAG->getMachineNode(PPC::LWZtoc, dl, MVT::i32, GA,
4791 transferMemOperands(N, MN);
4796 // For medium and large code model, we generate two instructions as
4797 // described below. Otherwise we allow SelectCodeCommon to handle this,
4798 // selecting one of LDtoc, LDtocJTI, LDtocCPT, and LDtocBA.
4799 CodeModel::Model CModel = TM.getCodeModel();
4800 if (CModel != CodeModel::Medium && CModel != CodeModel::Large)
4803 // The first source operand is a TargetGlobalAddress or a TargetJumpTable.
4804 // If it must be toc-referenced according to PPCSubTarget, we generate:
4805 // LDtocL(@sym, ADDIStocHA(%x2, @sym))
4806 // Otherwise we generate:
4807 // ADDItocL(ADDIStocHA(%x2, @sym), @sym)
4808 SDValue GA = N->getOperand(0);
4809 SDValue TOCbase = N->getOperand(1);
4810 SDNode *Tmp = CurDAG->getMachineNode(PPC::ADDIStocHA, dl, MVT::i64,
4813 if (isa<JumpTableSDNode>(GA) || isa<BlockAddressSDNode>(GA) ||
4814 CModel == CodeModel::Large) {
4815 SDNode *MN = CurDAG->getMachineNode(PPC::LDtocL, dl, MVT::i64, GA,
4817 transferMemOperands(N, MN);
4822 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(GA)) {
4823 const GlobalValue *GV = G->getGlobal();
4824 unsigned char GVFlags = PPCSubTarget->classifyGlobalReference(GV);
4825 if (GVFlags & PPCII::MO_NLP_FLAG) {
4826 SDNode *MN = CurDAG->getMachineNode(PPC::LDtocL, dl, MVT::i64, GA,
4828 transferMemOperands(N, MN);
4834 ReplaceNode(N, CurDAG->getMachineNode(PPC::ADDItocL, dl, MVT::i64,
4835 SDValue(Tmp, 0), GA));
4838 case PPCISD::PPC32_PICGOT:
4839 // Generate a PIC-safe GOT reference.
4840 assert(!PPCSubTarget->isPPC64() && PPCSubTarget->isSVR4ABI() &&
4841 "PPCISD::PPC32_PICGOT is only supported for 32-bit SVR4");
4842 CurDAG->SelectNodeTo(N, PPC::PPC32PICGOT,
4843 PPCLowering->getPointerTy(CurDAG->getDataLayout()),
4847 case PPCISD::VADD_SPLAT: {
4848 // This expands into one of three sequences, depending on whether
4849 // the first operand is odd or even, positive or negative.
4850 assert(isa<ConstantSDNode>(N->getOperand(0)) &&
4851 isa<ConstantSDNode>(N->getOperand(1)) &&
4852 "Invalid operand on VADD_SPLAT!");
4854 int Elt = N->getConstantOperandVal(0);
4855 int EltSize = N->getConstantOperandVal(1);
4856 unsigned Opc1, Opc2, Opc3;
4860 Opc1 = PPC::VSPLTISB;
4861 Opc2 = PPC::VADDUBM;
4862 Opc3 = PPC::VSUBUBM;
4864 } else if (EltSize == 2) {
4865 Opc1 = PPC::VSPLTISH;
4866 Opc2 = PPC::VADDUHM;
4867 Opc3 = PPC::VSUBUHM;
4870 assert(EltSize == 4 && "Invalid element size on VADD_SPLAT!");
4871 Opc1 = PPC::VSPLTISW;
4872 Opc2 = PPC::VADDUWM;
4873 Opc3 = PPC::VSUBUWM;
4877 if ((Elt & 1) == 0) {
4878 // Elt is even, in the range [-32,-18] + [16,30].
4880 // Convert: VADD_SPLAT elt, size
4881 // Into: tmp = VSPLTIS[BHW] elt
4882 // VADDU[BHW]M tmp, tmp
4883 // Where: [BHW] = B for size = 1, H for size = 2, W for size = 4
4884 SDValue EltVal = getI32Imm(Elt >> 1, dl);
4885 SDNode *Tmp = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
4886 SDValue TmpVal = SDValue(Tmp, 0);
4887 ReplaceNode(N, CurDAG->getMachineNode(Opc2, dl, VT, TmpVal, TmpVal));
4889 } else if (Elt > 0) {
4890 // Elt is odd and positive, in the range [17,31].
4892 // Convert: VADD_SPLAT elt, size
4893 // Into: tmp1 = VSPLTIS[BHW] elt-16
4894 // tmp2 = VSPLTIS[BHW] -16
4895 // VSUBU[BHW]M tmp1, tmp2
4896 SDValue EltVal = getI32Imm(Elt - 16, dl);
4897 SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
4898 EltVal = getI32Imm(-16, dl);
4899 SDNode *Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
4900 ReplaceNode(N, CurDAG->getMachineNode(Opc3, dl, VT, SDValue(Tmp1, 0),
4904 // Elt is odd and negative, in the range [-31,-17].
4906 // Convert: VADD_SPLAT elt, size
4907 // Into: tmp1 = VSPLTIS[BHW] elt+16
4908 // tmp2 = VSPLTIS[BHW] -16
4909 // VADDU[BHW]M tmp1, tmp2
4910 SDValue EltVal = getI32Imm(Elt + 16, dl);
4911 SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
4912 EltVal = getI32Imm(-16, dl);
4913 SDNode *Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
4914 ReplaceNode(N, CurDAG->getMachineNode(Opc2, dl, VT, SDValue(Tmp1, 0),
4920 assert(PPCSubTarget->hasP9Vector() && "ABS is supported with P9 Vector");
4922 // For vector absolute difference, we use VABSDUW instruction of POWER9.
4923 // Since VABSDU instructions are for unsigned integers, we need adjustment
4924 // for signed integers.
4925 // For abs(sub(a, b)), we generate VABSDUW(a+0x80000000, b+0x80000000).
4926 // Otherwise, abs(sub(-1, 0)) returns 0xFFFFFFFF(=-1) instead of 1.
4927 // For abs(a), we generate VABSDUW(a+0x80000000, 0x80000000).
4928 EVT VecVT = N->getOperand(0).getValueType();
4929 SDNode *AbsOp = nullptr;
4932 if (VecVT == MVT::v4i32)
4933 AbsOpcode = PPC::VABSDUW;
4934 else if (VecVT == MVT::v8i16)
4935 AbsOpcode = PPC::VABSDUH;
4936 else if (VecVT == MVT::v16i8)
4937 AbsOpcode = PPC::VABSDUB;
4939 llvm_unreachable("Unsupported vector data type for ISD::ABS");
4941 // Even for signed integers, we can skip adjustment if all values are
4942 // known to be positive (as signed integer) due to zero-extended inputs.
4943 if (N->getOperand(0).getOpcode() == ISD::SUB &&
4944 N->getOperand(0)->getOperand(0).getOpcode() == ISD::ZERO_EXTEND &&
4945 N->getOperand(0)->getOperand(1).getOpcode() == ISD::ZERO_EXTEND) {
4946 AbsOp = CurDAG->getMachineNode(AbsOpcode, dl, VecVT,
4947 SDValue(N->getOperand(0)->getOperand(0)),
4948 SDValue(N->getOperand(0)->getOperand(1)));
4949 ReplaceNode(N, AbsOp);
4952 if (N->getOperand(0).getOpcode() == ISD::SUB) {
4953 SDValue SubVal = N->getOperand(0);
4954 SDNode *Op0 = flipSignBit(SubVal->getOperand(0));
4955 SDNode *Op1 = flipSignBit(SubVal->getOperand(1));
4956 AbsOp = CurDAG->getMachineNode(AbsOpcode, dl, VecVT,
4957 SDValue(Op0, 0), SDValue(Op1, 0));
4960 SDNode *Op1 = nullptr;
4961 SDNode *Op0 = flipSignBit(N->getOperand(0), &Op1);
4962 AbsOp = CurDAG->getMachineNode(AbsOpcode, dl, VecVT, SDValue(Op0, 0),
4965 ReplaceNode(N, AbsOp);
4973 // If the target supports the cmpb instruction, do the idiom recognition here.
4974 // We don't do this as a DAG combine because we don't want to do it as nodes
4975 // are being combined (because we might miss part of the eventual idiom). We
4976 // don't want to do it during instruction selection because we want to reuse
4977 // the logic for lowering the masking operations already part of the
4978 // instruction selector.
4979 SDValue PPCDAGToDAGISel::combineToCMPB(SDNode *N) {
4982 assert(N->getOpcode() == ISD::OR &&
4983 "Only OR nodes are supported for CMPB");
4986 if (!PPCSubTarget->hasCMPB())
4989 if (N->getValueType(0) != MVT::i32 &&
4990 N->getValueType(0) != MVT::i64)
4993 EVT VT = N->getValueType(0);
4996 bool BytesFound[8] = {false, false, false, false, false, false, false, false};
4997 uint64_t Mask = 0, Alt = 0;
4999 auto IsByteSelectCC = [this](SDValue O, unsigned &b,
5000 uint64_t &Mask, uint64_t &Alt,
5001 SDValue &LHS, SDValue &RHS) {
5002 if (O.getOpcode() != ISD::SELECT_CC)
5004 ISD::CondCode CC = cast<CondCodeSDNode>(O.getOperand(4))->get();
5006 if (!isa<ConstantSDNode>(O.getOperand(2)) ||
5007 !isa<ConstantSDNode>(O.getOperand(3)))
5010 uint64_t PM = O.getConstantOperandVal(2);
5011 uint64_t PAlt = O.getConstantOperandVal(3);
5012 for (b = 0; b < 8; ++b) {
5013 uint64_t Mask = UINT64_C(0xFF) << (8*b);
5014 if (PM && (PM & Mask) == PM && (PAlt & Mask) == PAlt)
5023 if (!isa<ConstantSDNode>(O.getOperand(1)) ||
5024 O.getConstantOperandVal(1) != 0) {
5025 SDValue Op0 = O.getOperand(0), Op1 = O.getOperand(1);
5026 if (Op0.getOpcode() == ISD::TRUNCATE)
5027 Op0 = Op0.getOperand(0);
5028 if (Op1.getOpcode() == ISD::TRUNCATE)
5029 Op1 = Op1.getOperand(0);
5031 if (Op0.getOpcode() == ISD::SRL && Op1.getOpcode() == ISD::SRL &&
5032 Op0.getOperand(1) == Op1.getOperand(1) && CC == ISD::SETEQ &&
5033 isa<ConstantSDNode>(Op0.getOperand(1))) {
5035 unsigned Bits = Op0.getValueSizeInBits();
5038 if (Op0.getConstantOperandVal(1) != Bits-8)
5041 LHS = Op0.getOperand(0);
5042 RHS = Op1.getOperand(0);
5046 // When we have small integers (i16 to be specific), the form present
5047 // post-legalization uses SETULT in the SELECT_CC for the
5048 // higher-order byte, depending on the fact that the
5049 // even-higher-order bytes are known to all be zero, for example:
5050 // select_cc (xor $lhs, $rhs), 256, 65280, 0, setult
5051 // (so when the second byte is the same, because all higher-order
5052 // bits from bytes 3 and 4 are known to be zero, the result of the
5053 // xor can be at most 255)
5054 if (Op0.getOpcode() == ISD::XOR && CC == ISD::SETULT &&
5055 isa<ConstantSDNode>(O.getOperand(1))) {
5057 uint64_t ULim = O.getConstantOperandVal(1);
5058 if (ULim != (UINT64_C(1) << b*8))
5061 // Now we need to make sure that the upper bytes are known to be
5063 unsigned Bits = Op0.getValueSizeInBits();
5064 if (!CurDAG->MaskedValueIsZero(
5065 Op0, APInt::getHighBitsSet(Bits, Bits - (b + 1) * 8)))
5068 LHS = Op0.getOperand(0);
5069 RHS = Op0.getOperand(1);
5076 if (CC != ISD::SETEQ)
5079 SDValue Op = O.getOperand(0);
5080 if (Op.getOpcode() == ISD::AND) {
5081 if (!isa<ConstantSDNode>(Op.getOperand(1)))
5083 if (Op.getConstantOperandVal(1) != (UINT64_C(0xFF) << (8*b)))
5086 SDValue XOR = Op.getOperand(0);
5087 if (XOR.getOpcode() == ISD::TRUNCATE)
5088 XOR = XOR.getOperand(0);
5089 if (XOR.getOpcode() != ISD::XOR)
5092 LHS = XOR.getOperand(0);
5093 RHS = XOR.getOperand(1);
5095 } else if (Op.getOpcode() == ISD::SRL) {
5096 if (!isa<ConstantSDNode>(Op.getOperand(1)))
5098 unsigned Bits = Op.getValueSizeInBits();
5101 if (Op.getConstantOperandVal(1) != Bits-8)
5104 SDValue XOR = Op.getOperand(0);
5105 if (XOR.getOpcode() == ISD::TRUNCATE)
5106 XOR = XOR.getOperand(0);
5107 if (XOR.getOpcode() != ISD::XOR)
5110 LHS = XOR.getOperand(0);
5111 RHS = XOR.getOperand(1);
5118 SmallVector<SDValue, 8> Queue(1, SDValue(N, 0));
5119 while (!Queue.empty()) {
5120 SDValue V = Queue.pop_back_val();
5122 for (const SDValue &O : V.getNode()->ops()) {
5124 uint64_t M = 0, A = 0;
5126 if (O.getOpcode() == ISD::OR) {
5128 } else if (IsByteSelectCC(O, b, M, A, OLHS, ORHS)) {
5132 BytesFound[b] = true;
5135 } else if ((LHS == ORHS && RHS == OLHS) ||
5136 (RHS == ORHS && LHS == OLHS)) {
5137 BytesFound[b] = true;
5149 unsigned LastB = 0, BCnt = 0;
5150 for (unsigned i = 0; i < 8; ++i)
5151 if (BytesFound[LastB]) {
5156 if (!LastB || BCnt < 2)
5159 // Because we'll be zero-extending the output anyway if don't have a specific
5160 // value for each input byte (via the Mask), we can 'anyext' the inputs.
5161 if (LHS.getValueType() != VT) {
5162 LHS = CurDAG->getAnyExtOrTrunc(LHS, dl, VT);
5163 RHS = CurDAG->getAnyExtOrTrunc(RHS, dl, VT);
5166 Res = CurDAG->getNode(PPCISD::CMPB, dl, VT, LHS, RHS);
5168 bool NonTrivialMask = ((int64_t) Mask) != INT64_C(-1);
5169 if (NonTrivialMask && !Alt) {
5170 // Res = Mask & CMPB
5171 Res = CurDAG->getNode(ISD::AND, dl, VT, Res,
5172 CurDAG->getConstant(Mask, dl, VT));
5174 // Res = (CMPB & Mask) | (~CMPB & Alt)
5175 // Which, as suggested here:
5176 // https://graphics.stanford.edu/~seander/bithacks.html#MaskedMerge
5177 // can be written as:
5178 // Res = Alt ^ ((Alt ^ Mask) & CMPB)
5179 // useful because the (Alt ^ Mask) can be pre-computed.
5180 Res = CurDAG->getNode(ISD::AND, dl, VT, Res,
5181 CurDAG->getConstant(Mask ^ Alt, dl, VT));
5182 Res = CurDAG->getNode(ISD::XOR, dl, VT, Res,
5183 CurDAG->getConstant(Alt, dl, VT));
5189 // When CR bit registers are enabled, an extension of an i1 variable to a i32
5190 // or i64 value is lowered in terms of a SELECT_I[48] operation, and thus
5191 // involves constant materialization of a 0 or a 1 or both. If the result of
5192 // the extension is then operated upon by some operator that can be constant
5193 // folded with a constant 0 or 1, and that constant can be materialized using
5194 // only one instruction (like a zero or one), then we should fold in those
5195 // operations with the select.
5196 void PPCDAGToDAGISel::foldBoolExts(SDValue &Res, SDNode *&N) {
5197 if (!PPCSubTarget->useCRBits())
5200 if (N->getOpcode() != ISD::ZERO_EXTEND &&
5201 N->getOpcode() != ISD::SIGN_EXTEND &&
5202 N->getOpcode() != ISD::ANY_EXTEND)
5205 if (N->getOperand(0).getValueType() != MVT::i1)
5208 if (!N->hasOneUse())
5212 EVT VT = N->getValueType(0);
5213 SDValue Cond = N->getOperand(0);
5215 CurDAG->getConstant(N->getOpcode() == ISD::SIGN_EXTEND ? -1 : 1, dl, VT);
5216 SDValue ConstFalse = CurDAG->getConstant(0, dl, VT);
5219 SDNode *User = *N->use_begin();
5220 if (User->getNumOperands() != 2)
5223 auto TryFold = [this, N, User, dl](SDValue Val) {
5224 SDValue UserO0 = User->getOperand(0), UserO1 = User->getOperand(1);
5225 SDValue O0 = UserO0.getNode() == N ? Val : UserO0;
5226 SDValue O1 = UserO1.getNode() == N ? Val : UserO1;
5228 return CurDAG->FoldConstantArithmetic(User->getOpcode(), dl,
5229 User->getValueType(0),
5230 O0.getNode(), O1.getNode());
5233 // FIXME: When the semantics of the interaction between select and undef
5234 // are clearly defined, it may turn out to be unnecessary to break here.
5235 SDValue TrueRes = TryFold(ConstTrue);
5236 if (!TrueRes || TrueRes.isUndef())
5238 SDValue FalseRes = TryFold(ConstFalse);
5239 if (!FalseRes || FalseRes.isUndef())
5242 // For us to materialize these using one instruction, we must be able to
5243 // represent them as signed 16-bit integers.
5244 uint64_t True = cast<ConstantSDNode>(TrueRes)->getZExtValue(),
5245 False = cast<ConstantSDNode>(FalseRes)->getZExtValue();
5246 if (!isInt<16>(True) || !isInt<16>(False))
5249 // We can replace User with a new SELECT node, and try again to see if we
5250 // can fold the select with its user.
5251 Res = CurDAG->getSelect(dl, User->getValueType(0), Cond, TrueRes, FalseRes);
5253 ConstTrue = TrueRes;
5254 ConstFalse = FalseRes;
5255 } while (N->hasOneUse());
5258 void PPCDAGToDAGISel::PreprocessISelDAG() {
5259 SelectionDAG::allnodes_iterator Position = CurDAG->allnodes_end();
5261 bool MadeChange = false;
5262 while (Position != CurDAG->allnodes_begin()) {
5263 SDNode *N = &*--Position;
5268 switch (N->getOpcode()) {
5271 Res = combineToCMPB(N);
5276 foldBoolExts(Res, N);
5279 LLVM_DEBUG(dbgs() << "PPC DAG preprocessing replacing:\nOld: ");
5280 LLVM_DEBUG(N->dump(CurDAG));
5281 LLVM_DEBUG(dbgs() << "\nNew: ");
5282 LLVM_DEBUG(Res.getNode()->dump(CurDAG));
5283 LLVM_DEBUG(dbgs() << "\n");
5285 CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), Res);
5291 CurDAG->RemoveDeadNodes();
5294 /// PostprocessISelDAG - Perform some late peephole optimizations
5295 /// on the DAG representation.
5296 void PPCDAGToDAGISel::PostprocessISelDAG() {
5297 // Skip peepholes at -O0.
5298 if (TM.getOptLevel() == CodeGenOpt::None)
5303 PeepholePPC64ZExt();
5306 // Check if all users of this node will become isel where the second operand
5307 // is the constant zero. If this is so, and if we can negate the condition,
5308 // then we can flip the true and false operands. This will allow the zero to
5309 // be folded with the isel so that we don't need to materialize a register
5311 bool PPCDAGToDAGISel::AllUsersSelectZero(SDNode *N) {
5312 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
5315 if (!User->isMachineOpcode())
5317 if (User->getMachineOpcode() != PPC::SELECT_I4 &&
5318 User->getMachineOpcode() != PPC::SELECT_I8)
5321 SDNode *Op2 = User->getOperand(2).getNode();
5322 if (!Op2->isMachineOpcode())
5325 if (Op2->getMachineOpcode() != PPC::LI &&
5326 Op2->getMachineOpcode() != PPC::LI8)
5329 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op2->getOperand(0));
5333 if (!C->isNullValue())
5340 void PPCDAGToDAGISel::SwapAllSelectUsers(SDNode *N) {
5341 SmallVector<SDNode *, 4> ToReplace;
5342 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
5345 assert((User->getMachineOpcode() == PPC::SELECT_I4 ||
5346 User->getMachineOpcode() == PPC::SELECT_I8) &&
5347 "Must have all select users");
5348 ToReplace.push_back(User);
5351 for (SmallVector<SDNode *, 4>::iterator UI = ToReplace.begin(),
5352 UE = ToReplace.end(); UI != UE; ++UI) {
5355 CurDAG->getMachineNode(User->getMachineOpcode(), SDLoc(User),
5356 User->getValueType(0), User->getOperand(0),
5357 User->getOperand(2),
5358 User->getOperand(1));
5360 LLVM_DEBUG(dbgs() << "CR Peephole replacing:\nOld: ");
5361 LLVM_DEBUG(User->dump(CurDAG));
5362 LLVM_DEBUG(dbgs() << "\nNew: ");
5363 LLVM_DEBUG(ResNode->dump(CurDAG));
5364 LLVM_DEBUG(dbgs() << "\n");
5366 ReplaceUses(User, ResNode);
5370 void PPCDAGToDAGISel::PeepholeCROps() {
5374 for (SDNode &Node : CurDAG->allnodes()) {
5375 MachineSDNode *MachineNode = dyn_cast<MachineSDNode>(&Node);
5376 if (!MachineNode || MachineNode->use_empty())
5378 SDNode *ResNode = MachineNode;
5380 bool Op1Set = false, Op1Unset = false,
5382 Op2Set = false, Op2Unset = false,
5385 unsigned Opcode = MachineNode->getMachineOpcode();
5396 SDValue Op = MachineNode->getOperand(1);
5397 if (Op.isMachineOpcode()) {
5398 if (Op.getMachineOpcode() == PPC::CRSET)
5400 else if (Op.getMachineOpcode() == PPC::CRUNSET)
5402 else if (Op.getMachineOpcode() == PPC::CRNOR &&
5403 Op.getOperand(0) == Op.getOperand(1))
5410 case PPC::SELECT_I4:
5411 case PPC::SELECT_I8:
5412 case PPC::SELECT_F4:
5413 case PPC::SELECT_F8:
5414 case PPC::SELECT_QFRC:
5415 case PPC::SELECT_QSRC:
5416 case PPC::SELECT_QBRC:
5417 case PPC::SELECT_SPE:
5418 case PPC::SELECT_SPE4:
5419 case PPC::SELECT_VRRC:
5420 case PPC::SELECT_VSFRC:
5421 case PPC::SELECT_VSSRC:
5422 case PPC::SELECT_VSRC: {
5423 SDValue Op = MachineNode->getOperand(0);
5424 if (Op.isMachineOpcode()) {
5425 if (Op.getMachineOpcode() == PPC::CRSET)
5427 else if (Op.getMachineOpcode() == PPC::CRUNSET)
5429 else if (Op.getMachineOpcode() == PPC::CRNOR &&
5430 Op.getOperand(0) == Op.getOperand(1))
5437 bool SelectSwap = false;
5441 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
5443 ResNode = MachineNode->getOperand(0).getNode();
5446 ResNode = MachineNode->getOperand(1).getNode();
5449 ResNode = MachineNode->getOperand(0).getNode();
5450 else if (Op1Unset || Op2Unset)
5451 // x & 0 = 0 & y = 0
5452 ResNode = CurDAG->getMachineNode(PPC::CRUNSET, SDLoc(MachineNode),
5455 // ~x & y = andc(y, x)
5456 ResNode = CurDAG->getMachineNode(PPC::CRANDC, SDLoc(MachineNode),
5457 MVT::i1, MachineNode->getOperand(1),
5458 MachineNode->getOperand(0).
5461 // x & ~y = andc(x, y)
5462 ResNode = CurDAG->getMachineNode(PPC::CRANDC, SDLoc(MachineNode),
5463 MVT::i1, MachineNode->getOperand(0),
5464 MachineNode->getOperand(1).
5466 else if (AllUsersSelectZero(MachineNode)) {
5467 ResNode = CurDAG->getMachineNode(PPC::CRNAND, SDLoc(MachineNode),
5468 MVT::i1, MachineNode->getOperand(0),
5469 MachineNode->getOperand(1));
5474 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
5475 // nand(x, x) -> nor(x, x)
5476 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
5477 MVT::i1, MachineNode->getOperand(0),
5478 MachineNode->getOperand(0));
5480 // nand(1, y) -> nor(y, y)
5481 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
5482 MVT::i1, MachineNode->getOperand(1),
5483 MachineNode->getOperand(1));
5485 // nand(x, 1) -> nor(x, x)
5486 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
5487 MVT::i1, MachineNode->getOperand(0),
5488 MachineNode->getOperand(0));
5489 else if (Op1Unset || Op2Unset)
5490 // nand(x, 0) = nand(0, y) = 1
5491 ResNode = CurDAG->getMachineNode(PPC::CRSET, SDLoc(MachineNode),
5494 // nand(~x, y) = ~(~x & y) = x | ~y = orc(x, y)
5495 ResNode = CurDAG->getMachineNode(PPC::CRORC, SDLoc(MachineNode),
5496 MVT::i1, MachineNode->getOperand(0).
5498 MachineNode->getOperand(1));
5500 // nand(x, ~y) = ~x | y = orc(y, x)
5501 ResNode = CurDAG->getMachineNode(PPC::CRORC, SDLoc(MachineNode),
5502 MVT::i1, MachineNode->getOperand(1).
5504 MachineNode->getOperand(0));
5505 else if (AllUsersSelectZero(MachineNode)) {
5506 ResNode = CurDAG->getMachineNode(PPC::CRAND, SDLoc(MachineNode),
5507 MVT::i1, MachineNode->getOperand(0),
5508 MachineNode->getOperand(1));
5513 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
5515 ResNode = MachineNode->getOperand(0).getNode();
5516 else if (Op1Set || Op2Set)
5517 // x | 1 = 1 | y = 1
5518 ResNode = CurDAG->getMachineNode(PPC::CRSET, SDLoc(MachineNode),
5522 ResNode = MachineNode->getOperand(1).getNode();
5525 ResNode = MachineNode->getOperand(0).getNode();
5527 // ~x | y = orc(y, x)
5528 ResNode = CurDAG->getMachineNode(PPC::CRORC, SDLoc(MachineNode),
5529 MVT::i1, MachineNode->getOperand(1),
5530 MachineNode->getOperand(0).
5533 // x | ~y = orc(x, y)
5534 ResNode = CurDAG->getMachineNode(PPC::CRORC, SDLoc(MachineNode),
5535 MVT::i1, MachineNode->getOperand(0),
5536 MachineNode->getOperand(1).
5538 else if (AllUsersSelectZero(MachineNode)) {
5539 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
5540 MVT::i1, MachineNode->getOperand(0),
5541 MachineNode->getOperand(1));
5546 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
5548 ResNode = CurDAG->getMachineNode(PPC::CRUNSET, SDLoc(MachineNode),
5551 // xor(1, y) -> nor(y, y)
5552 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
5553 MVT::i1, MachineNode->getOperand(1),
5554 MachineNode->getOperand(1));
5556 // xor(x, 1) -> nor(x, x)
5557 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
5558 MVT::i1, MachineNode->getOperand(0),
5559 MachineNode->getOperand(0));
5562 ResNode = MachineNode->getOperand(1).getNode();
5565 ResNode = MachineNode->getOperand(0).getNode();
5567 // xor(~x, y) = eqv(x, y)
5568 ResNode = CurDAG->getMachineNode(PPC::CREQV, SDLoc(MachineNode),
5569 MVT::i1, MachineNode->getOperand(0).
5571 MachineNode->getOperand(1));
5573 // xor(x, ~y) = eqv(x, y)
5574 ResNode = CurDAG->getMachineNode(PPC::CREQV, SDLoc(MachineNode),
5575 MVT::i1, MachineNode->getOperand(0),
5576 MachineNode->getOperand(1).
5578 else if (AllUsersSelectZero(MachineNode)) {
5579 ResNode = CurDAG->getMachineNode(PPC::CREQV, SDLoc(MachineNode),
5580 MVT::i1, MachineNode->getOperand(0),
5581 MachineNode->getOperand(1));
5586 if (Op1Set || Op2Set)
5588 ResNode = CurDAG->getMachineNode(PPC::CRUNSET, SDLoc(MachineNode),
5591 // nor(0, y) = ~y -> nor(y, y)
5592 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
5593 MVT::i1, MachineNode->getOperand(1),
5594 MachineNode->getOperand(1));
5597 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
5598 MVT::i1, MachineNode->getOperand(0),
5599 MachineNode->getOperand(0));
5601 // nor(~x, y) = andc(x, y)
5602 ResNode = CurDAG->getMachineNode(PPC::CRANDC, SDLoc(MachineNode),
5603 MVT::i1, MachineNode->getOperand(0).
5605 MachineNode->getOperand(1));
5607 // nor(x, ~y) = andc(y, x)
5608 ResNode = CurDAG->getMachineNode(PPC::CRANDC, SDLoc(MachineNode),
5609 MVT::i1, MachineNode->getOperand(1).
5611 MachineNode->getOperand(0));
5612 else if (AllUsersSelectZero(MachineNode)) {
5613 ResNode = CurDAG->getMachineNode(PPC::CROR, SDLoc(MachineNode),
5614 MVT::i1, MachineNode->getOperand(0),
5615 MachineNode->getOperand(1));
5620 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
5622 ResNode = CurDAG->getMachineNode(PPC::CRSET, SDLoc(MachineNode),
5626 ResNode = MachineNode->getOperand(1).getNode();
5629 ResNode = MachineNode->getOperand(0).getNode();
5631 // eqv(0, y) = ~y -> nor(y, y)
5632 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
5633 MVT::i1, MachineNode->getOperand(1),
5634 MachineNode->getOperand(1));
5637 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
5638 MVT::i1, MachineNode->getOperand(0),
5639 MachineNode->getOperand(0));
5641 // eqv(~x, y) = xor(x, y)
5642 ResNode = CurDAG->getMachineNode(PPC::CRXOR, SDLoc(MachineNode),
5643 MVT::i1, MachineNode->getOperand(0).
5645 MachineNode->getOperand(1));
5647 // eqv(x, ~y) = xor(x, y)
5648 ResNode = CurDAG->getMachineNode(PPC::CRXOR, SDLoc(MachineNode),
5649 MVT::i1, MachineNode->getOperand(0),
5650 MachineNode->getOperand(1).
5652 else if (AllUsersSelectZero(MachineNode)) {
5653 ResNode = CurDAG->getMachineNode(PPC::CRXOR, SDLoc(MachineNode),
5654 MVT::i1, MachineNode->getOperand(0),
5655 MachineNode->getOperand(1));
5660 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
5662 ResNode = CurDAG->getMachineNode(PPC::CRUNSET, SDLoc(MachineNode),
5666 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
5667 MVT::i1, MachineNode->getOperand(1),
5668 MachineNode->getOperand(1));
5669 else if (Op1Unset || Op2Set)
5670 // andc(0, y) = andc(x, 1) = 0
5671 ResNode = CurDAG->getMachineNode(PPC::CRUNSET, SDLoc(MachineNode),
5675 ResNode = MachineNode->getOperand(0).getNode();
5677 // andc(~x, y) = ~(x | y) = nor(x, y)
5678 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
5679 MVT::i1, MachineNode->getOperand(0).
5681 MachineNode->getOperand(1));
5683 // andc(x, ~y) = x & y
5684 ResNode = CurDAG->getMachineNode(PPC::CRAND, SDLoc(MachineNode),
5685 MVT::i1, MachineNode->getOperand(0),
5686 MachineNode->getOperand(1).
5688 else if (AllUsersSelectZero(MachineNode)) {
5689 ResNode = CurDAG->getMachineNode(PPC::CRORC, SDLoc(MachineNode),
5690 MVT::i1, MachineNode->getOperand(1),
5691 MachineNode->getOperand(0));
5696 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
5698 ResNode = CurDAG->getMachineNode(PPC::CRSET, SDLoc(MachineNode),
5700 else if (Op1Set || Op2Unset)
5701 // orc(1, y) = orc(x, 0) = 1
5702 ResNode = CurDAG->getMachineNode(PPC::CRSET, SDLoc(MachineNode),
5706 ResNode = MachineNode->getOperand(0).getNode();
5709 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
5710 MVT::i1, MachineNode->getOperand(1),
5711 MachineNode->getOperand(1));
5713 // orc(~x, y) = ~(x & y) = nand(x, y)
5714 ResNode = CurDAG->getMachineNode(PPC::CRNAND, SDLoc(MachineNode),
5715 MVT::i1, MachineNode->getOperand(0).
5717 MachineNode->getOperand(1));
5719 // orc(x, ~y) = x | y
5720 ResNode = CurDAG->getMachineNode(PPC::CROR, SDLoc(MachineNode),
5721 MVT::i1, MachineNode->getOperand(0),
5722 MachineNode->getOperand(1).
5724 else if (AllUsersSelectZero(MachineNode)) {
5725 ResNode = CurDAG->getMachineNode(PPC::CRANDC, SDLoc(MachineNode),
5726 MVT::i1, MachineNode->getOperand(1),
5727 MachineNode->getOperand(0));
5731 case PPC::SELECT_I4:
5732 case PPC::SELECT_I8:
5733 case PPC::SELECT_F4:
5734 case PPC::SELECT_F8:
5735 case PPC::SELECT_QFRC:
5736 case PPC::SELECT_QSRC:
5737 case PPC::SELECT_QBRC:
5738 case PPC::SELECT_SPE:
5739 case PPC::SELECT_SPE4:
5740 case PPC::SELECT_VRRC:
5741 case PPC::SELECT_VSFRC:
5742 case PPC::SELECT_VSSRC:
5743 case PPC::SELECT_VSRC:
5745 ResNode = MachineNode->getOperand(1).getNode();
5747 ResNode = MachineNode->getOperand(2).getNode();
5749 ResNode = CurDAG->getMachineNode(MachineNode->getMachineOpcode(),
5751 MachineNode->getValueType(0),
5752 MachineNode->getOperand(0).
5754 MachineNode->getOperand(2),
5755 MachineNode->getOperand(1));
5760 ResNode = CurDAG->getMachineNode(Opcode == PPC::BC ? PPC::BCn :
5764 MachineNode->getOperand(0).
5766 MachineNode->getOperand(1),
5767 MachineNode->getOperand(2));
5768 // FIXME: Handle Op1Set, Op1Unset here too.
5772 // If we're inverting this node because it is used only by selects that
5773 // we'd like to swap, then swap the selects before the node replacement.
5775 SwapAllSelectUsers(MachineNode);
5777 if (ResNode != MachineNode) {
5778 LLVM_DEBUG(dbgs() << "CR Peephole replacing:\nOld: ");
5779 LLVM_DEBUG(MachineNode->dump(CurDAG));
5780 LLVM_DEBUG(dbgs() << "\nNew: ");
5781 LLVM_DEBUG(ResNode->dump(CurDAG));
5782 LLVM_DEBUG(dbgs() << "\n");
5784 ReplaceUses(MachineNode, ResNode);
5789 CurDAG->RemoveDeadNodes();
5790 } while (IsModified);
5793 // Gather the set of 32-bit operations that are known to have their
5794 // higher-order 32 bits zero, where ToPromote contains all such operations.
5795 static bool PeepholePPC64ZExtGather(SDValue Op32,
5796 SmallPtrSetImpl<SDNode *> &ToPromote) {
5797 if (!Op32.isMachineOpcode())
5800 // First, check for the "frontier" instructions (those that will clear the
5801 // higher-order 32 bits.
5803 // For RLWINM and RLWNM, we need to make sure that the mask does not wrap
5804 // around. If it does not, then these instructions will clear the
5805 // higher-order bits.
5806 if ((Op32.getMachineOpcode() == PPC::RLWINM ||
5807 Op32.getMachineOpcode() == PPC::RLWNM) &&
5808 Op32.getConstantOperandVal(2) <= Op32.getConstantOperandVal(3)) {
5809 ToPromote.insert(Op32.getNode());
5813 // SLW and SRW always clear the higher-order bits.
5814 if (Op32.getMachineOpcode() == PPC::SLW ||
5815 Op32.getMachineOpcode() == PPC::SRW) {
5816 ToPromote.insert(Op32.getNode());
5820 // For LI and LIS, we need the immediate to be positive (so that it is not
5822 if (Op32.getMachineOpcode() == PPC::LI ||
5823 Op32.getMachineOpcode() == PPC::LIS) {
5824 if (!isUInt<15>(Op32.getConstantOperandVal(0)))
5827 ToPromote.insert(Op32.getNode());
5831 // LHBRX and LWBRX always clear the higher-order bits.
5832 if (Op32.getMachineOpcode() == PPC::LHBRX ||
5833 Op32.getMachineOpcode() == PPC::LWBRX) {
5834 ToPromote.insert(Op32.getNode());
5838 // CNT[LT]ZW always produce a 64-bit value in [0,32], and so is zero extended.
5839 if (Op32.getMachineOpcode() == PPC::CNTLZW ||
5840 Op32.getMachineOpcode() == PPC::CNTTZW) {
5841 ToPromote.insert(Op32.getNode());
5845 // Next, check for those instructions we can look through.
5847 // Assuming the mask does not wrap around, then the higher-order bits are
5848 // taken directly from the first operand.
5849 if (Op32.getMachineOpcode() == PPC::RLWIMI &&
5850 Op32.getConstantOperandVal(3) <= Op32.getConstantOperandVal(4)) {
5851 SmallPtrSet<SDNode *, 16> ToPromote1;
5852 if (!PeepholePPC64ZExtGather(Op32.getOperand(0), ToPromote1))
5855 ToPromote.insert(Op32.getNode());
5856 ToPromote.insert(ToPromote1.begin(), ToPromote1.end());
5860 // For OR, the higher-order bits are zero if that is true for both operands.
5861 // For SELECT_I4, the same is true (but the relevant operand numbers are
5863 if (Op32.getMachineOpcode() == PPC::OR ||
5864 Op32.getMachineOpcode() == PPC::SELECT_I4) {
5865 unsigned B = Op32.getMachineOpcode() == PPC::SELECT_I4 ? 1 : 0;
5866 SmallPtrSet<SDNode *, 16> ToPromote1;
5867 if (!PeepholePPC64ZExtGather(Op32.getOperand(B+0), ToPromote1))
5869 if (!PeepholePPC64ZExtGather(Op32.getOperand(B+1), ToPromote1))
5872 ToPromote.insert(Op32.getNode());
5873 ToPromote.insert(ToPromote1.begin(), ToPromote1.end());
5877 // For ORI and ORIS, we need the higher-order bits of the first operand to be
5878 // zero, and also for the constant to be positive (so that it is not sign
5880 if (Op32.getMachineOpcode() == PPC::ORI ||
5881 Op32.getMachineOpcode() == PPC::ORIS) {
5882 SmallPtrSet<SDNode *, 16> ToPromote1;
5883 if (!PeepholePPC64ZExtGather(Op32.getOperand(0), ToPromote1))
5885 if (!isUInt<15>(Op32.getConstantOperandVal(1)))
5888 ToPromote.insert(Op32.getNode());
5889 ToPromote.insert(ToPromote1.begin(), ToPromote1.end());
5893 // The higher-order bits of AND are zero if that is true for at least one of
5895 if (Op32.getMachineOpcode() == PPC::AND) {
5896 SmallPtrSet<SDNode *, 16> ToPromote1, ToPromote2;
5898 PeepholePPC64ZExtGather(Op32.getOperand(0), ToPromote1);
5900 PeepholePPC64ZExtGather(Op32.getOperand(1), ToPromote2);
5901 if (!Op0OK && !Op1OK)
5904 ToPromote.insert(Op32.getNode());
5907 ToPromote.insert(ToPromote1.begin(), ToPromote1.end());
5910 ToPromote.insert(ToPromote2.begin(), ToPromote2.end());
5915 // For ANDI and ANDIS, the higher-order bits are zero if either that is true
5916 // of the first operand, or if the second operand is positive (so that it is
5917 // not sign extended).
5918 if (Op32.getMachineOpcode() == PPC::ANDIo ||
5919 Op32.getMachineOpcode() == PPC::ANDISo) {
5920 SmallPtrSet<SDNode *, 16> ToPromote1;
5922 PeepholePPC64ZExtGather(Op32.getOperand(0), ToPromote1);
5923 bool Op1OK = isUInt<15>(Op32.getConstantOperandVal(1));
5924 if (!Op0OK && !Op1OK)
5927 ToPromote.insert(Op32.getNode());
5930 ToPromote.insert(ToPromote1.begin(), ToPromote1.end());
5938 void PPCDAGToDAGISel::PeepholePPC64ZExt() {
5939 if (!PPCSubTarget->isPPC64())
5942 // When we zero-extend from i32 to i64, we use a pattern like this:
5943 // def : Pat<(i64 (zext i32:$in)),
5944 // (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32),
5946 // There are several 32-bit shift/rotate instructions, however, that will
5947 // clear the higher-order bits of their output, rendering the RLDICL
5948 // unnecessary. When that happens, we remove it here, and redefine the
5949 // relevant 32-bit operation to be a 64-bit operation.
5951 SelectionDAG::allnodes_iterator Position = CurDAG->allnodes_end();
5953 bool MadeChange = false;
5954 while (Position != CurDAG->allnodes_begin()) {
5955 SDNode *N = &*--Position;
5956 // Skip dead nodes and any non-machine opcodes.
5957 if (N->use_empty() || !N->isMachineOpcode())
5960 if (N->getMachineOpcode() != PPC::RLDICL)
5963 if (N->getConstantOperandVal(1) != 0 ||
5964 N->getConstantOperandVal(2) != 32)
5967 SDValue ISR = N->getOperand(0);
5968 if (!ISR.isMachineOpcode() ||
5969 ISR.getMachineOpcode() != TargetOpcode::INSERT_SUBREG)
5972 if (!ISR.hasOneUse())
5975 if (ISR.getConstantOperandVal(2) != PPC::sub_32)
5978 SDValue IDef = ISR.getOperand(0);
5979 if (!IDef.isMachineOpcode() ||
5980 IDef.getMachineOpcode() != TargetOpcode::IMPLICIT_DEF)
5983 // We now know that we're looking at a canonical i32 -> i64 zext. See if we
5984 // can get rid of it.
5986 SDValue Op32 = ISR->getOperand(1);
5987 if (!Op32.isMachineOpcode())
5990 // There are some 32-bit instructions that always clear the high-order 32
5991 // bits, there are also some instructions (like AND) that we can look
5993 SmallPtrSet<SDNode *, 16> ToPromote;
5994 if (!PeepholePPC64ZExtGather(Op32, ToPromote))
5997 // If the ToPromote set contains nodes that have uses outside of the set
5998 // (except for the original INSERT_SUBREG), then abort the transformation.
5999 bool OutsideUse = false;
6000 for (SDNode *PN : ToPromote) {
6001 for (SDNode *UN : PN->uses()) {
6002 if (!ToPromote.count(UN) && UN != ISR.getNode()) {
6016 // We now know that this zero extension can be removed by promoting to
6017 // nodes in ToPromote to 64-bit operations, where for operations in the
6018 // frontier of the set, we need to insert INSERT_SUBREGs for their
6020 for (SDNode *PN : ToPromote) {
6022 switch (PN->getMachineOpcode()) {
6024 llvm_unreachable("Don't know the 64-bit variant of this instruction");
6025 case PPC::RLWINM: NewOpcode = PPC::RLWINM8; break;
6026 case PPC::RLWNM: NewOpcode = PPC::RLWNM8; break;
6027 case PPC::SLW: NewOpcode = PPC::SLW8; break;
6028 case PPC::SRW: NewOpcode = PPC::SRW8; break;
6029 case PPC::LI: NewOpcode = PPC::LI8; break;
6030 case PPC::LIS: NewOpcode = PPC::LIS8; break;
6031 case PPC::LHBRX: NewOpcode = PPC::LHBRX8; break;
6032 case PPC::LWBRX: NewOpcode = PPC::LWBRX8; break;
6033 case PPC::CNTLZW: NewOpcode = PPC::CNTLZW8; break;
6034 case PPC::CNTTZW: NewOpcode = PPC::CNTTZW8; break;
6035 case PPC::RLWIMI: NewOpcode = PPC::RLWIMI8; break;
6036 case PPC::OR: NewOpcode = PPC::OR8; break;
6037 case PPC::SELECT_I4: NewOpcode = PPC::SELECT_I8; break;
6038 case PPC::ORI: NewOpcode = PPC::ORI8; break;
6039 case PPC::ORIS: NewOpcode = PPC::ORIS8; break;
6040 case PPC::AND: NewOpcode = PPC::AND8; break;
6041 case PPC::ANDIo: NewOpcode = PPC::ANDIo8; break;
6042 case PPC::ANDISo: NewOpcode = PPC::ANDISo8; break;
6045 // Note: During the replacement process, the nodes will be in an
6046 // inconsistent state (some instructions will have operands with values
6047 // of the wrong type). Once done, however, everything should be right
6050 SmallVector<SDValue, 4> Ops;
6051 for (const SDValue &V : PN->ops()) {
6052 if (!ToPromote.count(V.getNode()) && V.getValueType() == MVT::i32 &&
6053 !isa<ConstantSDNode>(V)) {
6054 SDValue ReplOpOps[] = { ISR.getOperand(0), V, ISR.getOperand(2) };
6056 CurDAG->getMachineNode(TargetOpcode::INSERT_SUBREG, SDLoc(V),
6057 ISR.getNode()->getVTList(), ReplOpOps);
6058 Ops.push_back(SDValue(ReplOp, 0));
6064 // Because all to-be-promoted nodes only have users that are other
6065 // promoted nodes (or the original INSERT_SUBREG), we can safely replace
6066 // the i32 result value type with i64.
6068 SmallVector<EVT, 2> NewVTs;
6069 SDVTList VTs = PN->getVTList();
6070 for (unsigned i = 0, ie = VTs.NumVTs; i != ie; ++i)
6071 if (VTs.VTs[i] == MVT::i32)
6072 NewVTs.push_back(MVT::i64);
6074 NewVTs.push_back(VTs.VTs[i]);
6076 LLVM_DEBUG(dbgs() << "PPC64 ZExt Peephole morphing:\nOld: ");
6077 LLVM_DEBUG(PN->dump(CurDAG));
6079 CurDAG->SelectNodeTo(PN, NewOpcode, CurDAG->getVTList(NewVTs), Ops);
6081 LLVM_DEBUG(dbgs() << "\nNew: ");
6082 LLVM_DEBUG(PN->dump(CurDAG));
6083 LLVM_DEBUG(dbgs() << "\n");
6086 // Now we replace the original zero extend and its associated INSERT_SUBREG
6087 // with the value feeding the INSERT_SUBREG (which has now been promoted to
6090 LLVM_DEBUG(dbgs() << "PPC64 ZExt Peephole replacing:\nOld: ");
6091 LLVM_DEBUG(N->dump(CurDAG));
6092 LLVM_DEBUG(dbgs() << "\nNew: ");
6093 LLVM_DEBUG(Op32.getNode()->dump(CurDAG));
6094 LLVM_DEBUG(dbgs() << "\n");
6096 ReplaceUses(N, Op32.getNode());
6100 CurDAG->RemoveDeadNodes();
6103 void PPCDAGToDAGISel::PeepholePPC64() {
6104 // These optimizations are currently supported only for 64-bit SVR4.
6105 if (PPCSubTarget->isDarwin() || !PPCSubTarget->isPPC64())
6108 SelectionDAG::allnodes_iterator Position = CurDAG->allnodes_end();
6110 while (Position != CurDAG->allnodes_begin()) {
6111 SDNode *N = &*--Position;
6112 // Skip dead nodes and any non-machine opcodes.
6113 if (N->use_empty() || !N->isMachineOpcode())
6117 unsigned StorageOpcode = N->getMachineOpcode();
6118 bool RequiresMod4Offset = false;
6120 switch (StorageOpcode) {
6125 case PPC::DFLOADf64:
6126 case PPC::DFLOADf32:
6127 RequiresMod4Offset = true;
6143 case PPC::DFSTOREf64:
6144 case PPC::DFSTOREf32:
6145 RequiresMod4Offset = true;
6159 // If this is a load or store with a zero offset, or within the alignment,
6160 // we may be able to fold an add-immediate into the memory operation.
6161 // The check against alignment is below, as it can't occur until we check
6162 // the arguments to N
6163 if (!isa<ConstantSDNode>(N->getOperand(FirstOp)))
6166 SDValue Base = N->getOperand(FirstOp + 1);
6167 if (!Base.isMachineOpcode())
6171 bool ReplaceFlags = true;
6173 // When the feeding operation is an add-immediate of some sort,
6174 // determine whether we need to add relocation information to the
6175 // target flags on the immediate operand when we fold it into the
6176 // load instruction.
6178 // For something like ADDItocL, the relocation information is
6179 // inferred from the opcode; when we process it in the AsmPrinter,
6180 // we add the necessary relocation there. A load, though, can receive
6181 // relocation from various flavors of ADDIxxx, so we need to carry
6182 // the relocation information in the target flags.
6183 switch (Base.getMachineOpcode()) {
6188 // In some cases (such as TLS) the relocation information
6189 // is already in place on the operand, so copying the operand
6191 ReplaceFlags = false;
6192 // For these cases, the immediate may not be divisible by 4, in
6193 // which case the fold is illegal for DS-form instructions. (The
6194 // other cases provide aligned addresses and are always safe.)
6195 if (RequiresMod4Offset &&
6196 (!isa<ConstantSDNode>(Base.getOperand(1)) ||
6197 Base.getConstantOperandVal(1) % 4 != 0))
6200 case PPC::ADDIdtprelL:
6201 Flags = PPCII::MO_DTPREL_LO;
6203 case PPC::ADDItlsldL:
6204 Flags = PPCII::MO_TLSLD_LO;
6207 Flags = PPCII::MO_TOC_LO;
6211 SDValue ImmOpnd = Base.getOperand(1);
6213 // On PPC64, the TOC base pointer is guaranteed by the ABI only to have
6214 // 8-byte alignment, and so we can only use offsets less than 8 (otherwise,
6215 // we might have needed different @ha relocation values for the offset
6217 int MaxDisplacement = 7;
6218 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(ImmOpnd)) {
6219 const GlobalValue *GV = GA->getGlobal();
6220 MaxDisplacement = std::min((int) GV->getAlignment() - 1, MaxDisplacement);
6223 bool UpdateHBase = false;
6224 SDValue HBase = Base.getOperand(0);
6226 int Offset = N->getConstantOperandVal(FirstOp);
6228 if (Offset < 0 || Offset > MaxDisplacement) {
6229 // If we have a addi(toc@l)/addis(toc@ha) pair, and the addis has only
6230 // one use, then we can do this for any offset, we just need to also
6231 // update the offset (i.e. the symbol addend) on the addis also.
6232 if (Base.getMachineOpcode() != PPC::ADDItocL)
6235 if (!HBase.isMachineOpcode() ||
6236 HBase.getMachineOpcode() != PPC::ADDIStocHA)
6239 if (!Base.hasOneUse() || !HBase.hasOneUse())
6242 SDValue HImmOpnd = HBase.getOperand(1);
6243 if (HImmOpnd != ImmOpnd)
6249 // If we're directly folding the addend from an addi instruction, then:
6250 // 1. In general, the offset on the memory access must be zero.
6251 // 2. If the addend is a constant, then it can be combined with a
6252 // non-zero offset, but only if the result meets the encoding
6254 if (auto *C = dyn_cast<ConstantSDNode>(ImmOpnd)) {
6255 Offset += C->getSExtValue();
6257 if (RequiresMod4Offset && (Offset % 4) != 0)
6260 if (!isInt<16>(Offset))
6263 ImmOpnd = CurDAG->getTargetConstant(Offset, SDLoc(ImmOpnd),
6264 ImmOpnd.getValueType());
6265 } else if (Offset != 0) {
6270 // We found an opportunity. Reverse the operands from the add
6271 // immediate and substitute them into the load or store. If
6272 // needed, update the target flags for the immediate operand to
6273 // reflect the necessary relocation information.
6274 LLVM_DEBUG(dbgs() << "Folding add-immediate into mem-op:\nBase: ");
6275 LLVM_DEBUG(Base->dump(CurDAG));
6276 LLVM_DEBUG(dbgs() << "\nN: ");
6277 LLVM_DEBUG(N->dump(CurDAG));
6278 LLVM_DEBUG(dbgs() << "\n");
6280 // If the relocation information isn't already present on the
6281 // immediate operand, add it now.
6283 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(ImmOpnd)) {
6285 const GlobalValue *GV = GA->getGlobal();
6286 // We can't perform this optimization for data whose alignment
6287 // is insufficient for the instruction encoding.
6288 if (GV->getAlignment() < 4 &&
6289 (RequiresMod4Offset || (Offset % 4) != 0)) {
6290 LLVM_DEBUG(dbgs() << "Rejected this candidate for alignment.\n\n");
6293 ImmOpnd = CurDAG->getTargetGlobalAddress(GV, dl, MVT::i64, Offset, Flags);
6294 } else if (ConstantPoolSDNode *CP =
6295 dyn_cast<ConstantPoolSDNode>(ImmOpnd)) {
6296 const Constant *C = CP->getConstVal();
6297 ImmOpnd = CurDAG->getTargetConstantPool(C, MVT::i64,
6303 if (FirstOp == 1) // Store
6304 (void)CurDAG->UpdateNodeOperands(N, N->getOperand(0), ImmOpnd,
6305 Base.getOperand(0), N->getOperand(3));
6307 (void)CurDAG->UpdateNodeOperands(N, ImmOpnd, Base.getOperand(0),
6311 (void)CurDAG->UpdateNodeOperands(HBase.getNode(), HBase.getOperand(0),
6314 // The add-immediate may now be dead, in which case remove it.
6315 if (Base.getNode()->use_empty())
6316 CurDAG->RemoveDeadNode(Base.getNode());
6320 /// createPPCISelDag - This pass converts a legalized DAG into a
6321 /// PowerPC-specific DAG, ready for instruction scheduling.
6323 FunctionPass *llvm::createPPCISelDag(PPCTargetMachine &TM,
6324 CodeGenOpt::Level OptLevel) {
6325 return new PPCDAGToDAGISel(TM, OptLevel);