1 //===-- PPCISelDAGToDAG.cpp - PPC --pattern matching inst selector --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for PowerPC,
11 // converting from a legalized dag to a PPC dag.
13 //===----------------------------------------------------------------------===//
15 #include "MCTargetDesc/PPCMCTargetDesc.h"
16 #include "MCTargetDesc/PPCPredicates.h"
18 #include "PPCISelLowering.h"
19 #include "PPCMachineFunctionInfo.h"
20 #include "PPCSubtarget.h"
21 #include "PPCTargetMachine.h"
22 #include "llvm/ADT/APInt.h"
23 #include "llvm/ADT/DenseMap.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/ADT/SmallPtrSet.h"
26 #include "llvm/ADT/SmallVector.h"
27 #include "llvm/ADT/Statistic.h"
28 #include "llvm/Analysis/BranchProbabilityInfo.h"
29 #include "llvm/CodeGen/FunctionLoweringInfo.h"
30 #include "llvm/CodeGen/ISDOpcodes.h"
31 #include "llvm/CodeGen/MachineBasicBlock.h"
32 #include "llvm/CodeGen/MachineFunction.h"
33 #include "llvm/CodeGen/MachineInstrBuilder.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/MachineValueType.h"
36 #include "llvm/CodeGen/SelectionDAG.h"
37 #include "llvm/CodeGen/SelectionDAGISel.h"
38 #include "llvm/CodeGen/SelectionDAGNodes.h"
39 #include "llvm/CodeGen/ValueTypes.h"
40 #include "llvm/IR/BasicBlock.h"
41 #include "llvm/IR/DebugLoc.h"
42 #include "llvm/IR/Function.h"
43 #include "llvm/IR/GlobalValue.h"
44 #include "llvm/IR/InlineAsm.h"
45 #include "llvm/IR/InstrTypes.h"
46 #include "llvm/IR/Module.h"
47 #include "llvm/Support/Casting.h"
48 #include "llvm/Support/CodeGen.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/Compiler.h"
51 #include "llvm/Support/Debug.h"
52 #include "llvm/Support/ErrorHandling.h"
53 #include "llvm/Support/KnownBits.h"
54 #include "llvm/Support/MathExtras.h"
55 #include "llvm/Support/raw_ostream.h"
56 #include "llvm/Target/TargetInstrInfo.h"
57 #include "llvm/Target/TargetRegisterInfo.h"
70 #define DEBUG_TYPE "ppc-codegen"
72 STATISTIC(NumSextSetcc,
73 "Number of (sext(setcc)) nodes expanded into GPR sequence.");
74 STATISTIC(NumZextSetcc,
75 "Number of (zext(setcc)) nodes expanded into GPR sequence.");
76 STATISTIC(SignExtensionsAdded,
77 "Number of sign extensions for compare inputs added.");
78 STATISTIC(ZeroExtensionsAdded,
79 "Number of zero extensions for compare inputs added.");
80 STATISTIC(NumLogicOpsOnComparison,
81 "Number of logical ops on i1 values calculated in GPR.");
82 STATISTIC(OmittedForNonExtendUses,
83 "Number of compares not eliminated as they have non-extending uses.");
85 // FIXME: Remove this once the bug has been fixed!
86 cl::opt<bool> ANDIGlueBug("expose-ppc-andi-glue-bug",
87 cl::desc("expose the ANDI glue bug on PPC"), cl::Hidden);
90 UseBitPermRewriter("ppc-use-bit-perm-rewriter", cl::init(true),
91 cl::desc("use aggressive ppc isel for bit permutations"),
93 static cl::opt<bool> BPermRewriterNoMasking(
94 "ppc-bit-perm-rewriter-stress-rotates",
95 cl::desc("stress rotate selection in aggressive ppc isel for "
99 static cl::opt<bool> EnableBranchHint(
100 "ppc-use-branch-hint", cl::init(true),
101 cl::desc("Enable static hinting of branches on ppc"),
106 //===--------------------------------------------------------------------===//
107 /// PPCDAGToDAGISel - PPC specific code to select PPC machine
108 /// instructions for SelectionDAG operations.
110 class PPCDAGToDAGISel : public SelectionDAGISel {
111 const PPCTargetMachine &TM;
112 const PPCSubtarget *PPCSubTarget;
113 const PPCTargetLowering *PPCLowering;
114 unsigned GlobalBaseReg;
117 explicit PPCDAGToDAGISel(PPCTargetMachine &tm, CodeGenOpt::Level OptLevel)
118 : SelectionDAGISel(tm, OptLevel), TM(tm) {}
120 bool runOnMachineFunction(MachineFunction &MF) override {
121 // Make sure we re-emit a set of the global base reg if necessary
123 PPCSubTarget = &MF.getSubtarget<PPCSubtarget>();
124 PPCLowering = PPCSubTarget->getTargetLowering();
125 SelectionDAGISel::runOnMachineFunction(MF);
127 if (!PPCSubTarget->isSVR4ABI())
128 InsertVRSaveCode(MF);
133 void PreprocessISelDAG() override;
134 void PostprocessISelDAG() override;
136 /// getI32Imm - Return a target constant with the specified value, of type
138 inline SDValue getI32Imm(unsigned Imm, const SDLoc &dl) {
139 return CurDAG->getTargetConstant(Imm, dl, MVT::i32);
142 /// getI64Imm - Return a target constant with the specified value, of type
144 inline SDValue getI64Imm(uint64_t Imm, const SDLoc &dl) {
145 return CurDAG->getTargetConstant(Imm, dl, MVT::i64);
148 /// getSmallIPtrImm - Return a target constant of pointer type.
149 inline SDValue getSmallIPtrImm(unsigned Imm, const SDLoc &dl) {
150 return CurDAG->getTargetConstant(
151 Imm, dl, PPCLowering->getPointerTy(CurDAG->getDataLayout()));
154 /// isRotateAndMask - Returns true if Mask and Shift can be folded into a
155 /// rotate and mask opcode and mask operation.
156 static bool isRotateAndMask(SDNode *N, unsigned Mask, bool isShiftMask,
157 unsigned &SH, unsigned &MB, unsigned &ME);
159 /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
160 /// base register. Return the virtual register that holds this value.
161 SDNode *getGlobalBaseReg();
163 void selectFrameIndex(SDNode *SN, SDNode *N, unsigned Offset = 0);
165 // Select - Convert the specified operand from a target-independent to a
166 // target-specific node if it hasn't already been changed.
167 void Select(SDNode *N) override;
169 bool tryBitfieldInsert(SDNode *N);
170 bool tryBitPermutation(SDNode *N);
172 /// SelectCC - Select a comparison of the specified values with the
173 /// specified condition code, returning the CR# of the expression.
174 SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC,
177 /// SelectAddrImm - Returns true if the address N can be represented by
178 /// a base register plus a signed 16-bit displacement [r+imm].
179 bool SelectAddrImm(SDValue N, SDValue &Disp,
181 return PPCLowering->SelectAddressRegImm(N, Disp, Base, *CurDAG, false);
184 /// SelectAddrImmOffs - Return true if the operand is valid for a preinc
185 /// immediate field. Note that the operand at this point is already the
186 /// result of a prior SelectAddressRegImm call.
187 bool SelectAddrImmOffs(SDValue N, SDValue &Out) const {
188 if (N.getOpcode() == ISD::TargetConstant ||
189 N.getOpcode() == ISD::TargetGlobalAddress) {
197 /// SelectAddrIdx - Given the specified addressed, check to see if it can be
198 /// represented as an indexed [r+r] operation. Returns false if it can
199 /// be represented by [r+imm], which are preferred.
200 bool SelectAddrIdx(SDValue N, SDValue &Base, SDValue &Index) {
201 return PPCLowering->SelectAddressRegReg(N, Base, Index, *CurDAG);
204 /// SelectAddrIdxOnly - Given the specified addressed, force it to be
205 /// represented as an indexed [r+r] operation.
206 bool SelectAddrIdxOnly(SDValue N, SDValue &Base, SDValue &Index) {
207 return PPCLowering->SelectAddressRegRegOnly(N, Base, Index, *CurDAG);
210 /// SelectAddrImmX4 - Returns true if the address N can be represented by
211 /// a base register plus a signed 16-bit displacement that is a multiple of 4.
212 /// Suitable for use by STD and friends.
213 bool SelectAddrImmX4(SDValue N, SDValue &Disp, SDValue &Base) {
214 return PPCLowering->SelectAddressRegImm(N, Disp, Base, *CurDAG, true);
217 // Select an address into a single register.
218 bool SelectAddr(SDValue N, SDValue &Base) {
223 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
224 /// inline asm expressions. It is always correct to compute the value into
225 /// a register. The case of adding a (possibly relocatable) constant to a
226 /// register can be improved, but it is wrong to substitute Reg+Reg for
227 /// Reg in an asm, because the load or store opcode would have to change.
228 bool SelectInlineAsmMemoryOperand(const SDValue &Op,
229 unsigned ConstraintID,
230 std::vector<SDValue> &OutOps) override {
231 switch(ConstraintID) {
233 errs() << "ConstraintID: " << ConstraintID << "\n";
234 llvm_unreachable("Unexpected asm memory constraint");
235 case InlineAsm::Constraint_es:
236 case InlineAsm::Constraint_i:
237 case InlineAsm::Constraint_m:
238 case InlineAsm::Constraint_o:
239 case InlineAsm::Constraint_Q:
240 case InlineAsm::Constraint_Z:
241 case InlineAsm::Constraint_Zy:
242 // We need to make sure that this one operand does not end up in r0
243 // (because we might end up lowering this as 0(%op)).
244 const TargetRegisterInfo *TRI = PPCSubTarget->getRegisterInfo();
245 const TargetRegisterClass *TRC = TRI->getPointerRegClass(*MF, /*Kind=*/1);
247 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), dl, MVT::i32);
249 SDValue(CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS,
250 dl, Op.getValueType(),
253 OutOps.push_back(NewOp);
259 void InsertVRSaveCode(MachineFunction &MF);
261 StringRef getPassName() const override {
262 return "PowerPC DAG->DAG Pattern Instruction Selection";
265 // Include the pieces autogenerated from the target description.
266 #include "PPCGenDAGISel.inc"
269 // Conversion type for interpreting results of a 32-bit instruction as
270 // a 64-bit value or vice versa.
271 enum ExtOrTruncConversion { Ext, Trunc };
273 // Modifiers to guide how an ISD::SETCC node's result is to be computed
275 // ZExtOrig - use the original condition code, zero-extend value
276 // ZExtInvert - invert the condition code, zero-extend value
277 // SExtOrig - use the original condition code, sign-extend value
278 // SExtInvert - invert the condition code, sign-extend value
279 enum SetccInGPROpts { ZExtOrig, ZExtInvert, SExtOrig, SExtInvert };
281 bool trySETCC(SDNode *N);
282 bool tryEXTEND(SDNode *N);
283 bool tryLogicOpOfCompares(SDNode *N);
284 SDValue computeLogicOpInGPR(SDValue LogicOp);
285 SDValue signExtendInputIfNeeded(SDValue Input);
286 SDValue zeroExtendInputIfNeeded(SDValue Input);
287 SDValue addExtOrTrunc(SDValue NatWidthRes, ExtOrTruncConversion Conv);
288 SDValue get32BitZExtCompare(SDValue LHS, SDValue RHS, ISD::CondCode CC,
289 int64_t RHSValue, SDLoc dl);
290 SDValue get32BitSExtCompare(SDValue LHS, SDValue RHS, ISD::CondCode CC,
291 int64_t RHSValue, SDLoc dl);
292 SDValue get64BitZExtCompare(SDValue LHS, SDValue RHS, ISD::CondCode CC,
293 int64_t RHSValue, SDLoc dl);
294 SDValue get64BitSExtCompare(SDValue LHS, SDValue RHS, ISD::CondCode CC,
295 int64_t RHSValue, SDLoc dl);
296 SDValue getSETCCInGPR(SDValue Compare, SetccInGPROpts ConvOpts);
298 void PeepholePPC64();
299 void PeepholePPC64ZExt();
300 void PeepholeCROps();
302 SDValue combineToCMPB(SDNode *N);
303 void foldBoolExts(SDValue &Res, SDNode *&N);
305 bool AllUsersSelectZero(SDNode *N);
306 void SwapAllSelectUsers(SDNode *N);
308 void transferMemOperands(SDNode *N, SDNode *Result);
311 } // end anonymous namespace
313 /// InsertVRSaveCode - Once the entire function has been instruction selected,
314 /// all virtual registers are created and all machine instructions are built,
315 /// check to see if we need to save/restore VRSAVE. If so, do it.
316 void PPCDAGToDAGISel::InsertVRSaveCode(MachineFunction &Fn) {
317 // Check to see if this function uses vector registers, which means we have to
318 // save and restore the VRSAVE register and update it with the regs we use.
320 // In this case, there will be virtual registers of vector type created
321 // by the scheduler. Detect them now.
322 bool HasVectorVReg = false;
323 for (unsigned i = 0, e = RegInfo->getNumVirtRegs(); i != e; ++i) {
324 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
325 if (RegInfo->getRegClass(Reg) == &PPC::VRRCRegClass) {
326 HasVectorVReg = true;
330 if (!HasVectorVReg) return; // nothing to do.
332 // If we have a vector register, we want to emit code into the entry and exit
333 // blocks to save and restore the VRSAVE register. We do this here (instead
334 // of marking all vector instructions as clobbering VRSAVE) for two reasons:
336 // 1. This (trivially) reduces the load on the register allocator, by not
337 // having to represent the live range of the VRSAVE register.
338 // 2. This (more significantly) allows us to create a temporary virtual
339 // register to hold the saved VRSAVE value, allowing this temporary to be
340 // register allocated, instead of forcing it to be spilled to the stack.
342 // Create two vregs - one to hold the VRSAVE register that is live-in to the
343 // function and one for the value after having bits or'd into it.
344 unsigned InVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
345 unsigned UpdatedVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
347 const TargetInstrInfo &TII = *PPCSubTarget->getInstrInfo();
348 MachineBasicBlock &EntryBB = *Fn.begin();
350 // Emit the following code into the entry block:
351 // InVRSAVE = MFVRSAVE
352 // UpdatedVRSAVE = UPDATE_VRSAVE InVRSAVE
353 // MTVRSAVE UpdatedVRSAVE
354 MachineBasicBlock::iterator IP = EntryBB.begin(); // Insert Point
355 BuildMI(EntryBB, IP, dl, TII.get(PPC::MFVRSAVE), InVRSAVE);
356 BuildMI(EntryBB, IP, dl, TII.get(PPC::UPDATE_VRSAVE),
357 UpdatedVRSAVE).addReg(InVRSAVE);
358 BuildMI(EntryBB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(UpdatedVRSAVE);
360 // Find all return blocks, outputting a restore in each epilog.
361 for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
362 if (BB->isReturnBlock()) {
363 IP = BB->end(); --IP;
365 // Skip over all terminator instructions, which are part of the return
367 MachineBasicBlock::iterator I2 = IP;
368 while (I2 != BB->begin() && (--I2)->isTerminator())
371 // Emit: MTVRSAVE InVRSave
372 BuildMI(*BB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(InVRSAVE);
377 /// getGlobalBaseReg - Output the instructions required to put the
378 /// base address to use for accessing globals into a register.
380 SDNode *PPCDAGToDAGISel::getGlobalBaseReg() {
381 if (!GlobalBaseReg) {
382 const TargetInstrInfo &TII = *PPCSubTarget->getInstrInfo();
383 // Insert the set of GlobalBaseReg into the first MBB of the function
384 MachineBasicBlock &FirstMBB = MF->front();
385 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
386 const Module *M = MF->getFunction()->getParent();
389 if (PPCLowering->getPointerTy(CurDAG->getDataLayout()) == MVT::i32) {
390 if (PPCSubTarget->isTargetELF()) {
391 GlobalBaseReg = PPC::R30;
392 if (M->getPICLevel() == PICLevel::SmallPIC) {
393 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MoveGOTtoLR));
394 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg);
395 MF->getInfo<PPCFunctionInfo>()->setUsesPICBase(true);
397 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR));
398 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg);
399 unsigned TempReg = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
400 BuildMI(FirstMBB, MBBI, dl,
401 TII.get(PPC::UpdateGBR), GlobalBaseReg)
402 .addReg(TempReg, RegState::Define).addReg(GlobalBaseReg);
403 MF->getInfo<PPCFunctionInfo>()->setUsesPICBase(true);
407 RegInfo->createVirtualRegister(&PPC::GPRC_and_GPRC_NOR0RegClass);
408 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR));
409 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg);
412 GlobalBaseReg = RegInfo->createVirtualRegister(&PPC::G8RC_and_G8RC_NOX0RegClass);
413 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR8));
414 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR8), GlobalBaseReg);
417 return CurDAG->getRegister(GlobalBaseReg,
418 PPCLowering->getPointerTy(CurDAG->getDataLayout()))
422 /// isInt32Immediate - This method tests to see if the node is a 32-bit constant
423 /// operand. If so Imm will receive the 32-bit value.
424 static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
425 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
426 Imm = cast<ConstantSDNode>(N)->getZExtValue();
432 /// isInt64Immediate - This method tests to see if the node is a 64-bit constant
433 /// operand. If so Imm will receive the 64-bit value.
434 static bool isInt64Immediate(SDNode *N, uint64_t &Imm) {
435 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i64) {
436 Imm = cast<ConstantSDNode>(N)->getZExtValue();
442 // isInt32Immediate - This method tests to see if a constant operand.
443 // If so Imm will receive the 32 bit value.
444 static bool isInt32Immediate(SDValue N, unsigned &Imm) {
445 return isInt32Immediate(N.getNode(), Imm);
448 static unsigned getBranchHint(unsigned PCC, FunctionLoweringInfo *FuncInfo,
449 const SDValue &DestMBB) {
450 assert(isa<BasicBlockSDNode>(DestMBB));
452 if (!FuncInfo->BPI) return PPC::BR_NO_HINT;
454 const BasicBlock *BB = FuncInfo->MBB->getBasicBlock();
455 const TerminatorInst *BBTerm = BB->getTerminator();
457 if (BBTerm->getNumSuccessors() != 2) return PPC::BR_NO_HINT;
459 const BasicBlock *TBB = BBTerm->getSuccessor(0);
460 const BasicBlock *FBB = BBTerm->getSuccessor(1);
462 auto TProb = FuncInfo->BPI->getEdgeProbability(BB, TBB);
463 auto FProb = FuncInfo->BPI->getEdgeProbability(BB, FBB);
465 // We only want to handle cases which are easy to predict at static time, e.g.
466 // C++ throw statement, that is very likely not taken, or calling never
467 // returned function, e.g. stdlib exit(). So we set Threshold to filter
470 // Below is LLVM branch weight table, we only want to handle case 1, 2
472 // Case Taken:Nontaken Example
473 // 1. Unreachable 1048575:1 C++ throw, stdlib exit(),
474 // 2. Invoke-terminating 1:1048575
475 // 3. Coldblock 4:64 __builtin_expect
476 // 4. Loop Branch 124:4 For loop
477 // 5. PH/ZH/FPH 20:12
478 const uint32_t Threshold = 10000;
480 if (std::max(TProb, FProb) / Threshold < std::min(TProb, FProb))
481 return PPC::BR_NO_HINT;
483 DEBUG(dbgs() << "Use branch hint for '" << FuncInfo->Fn->getName() << "::"
484 << BB->getName() << "'\n"
485 << " -> " << TBB->getName() << ": " << TProb << "\n"
486 << " -> " << FBB->getName() << ": " << FProb << "\n");
488 const BasicBlockSDNode *BBDN = cast<BasicBlockSDNode>(DestMBB);
490 // If Dest BasicBlock is False-BasicBlock (FBB), swap branch probabilities,
491 // because we want 'TProb' stands for 'branch probability' to Dest BasicBlock
492 if (BBDN->getBasicBlock()->getBasicBlock() != TBB)
493 std::swap(TProb, FProb);
495 return (TProb > FProb) ? PPC::BR_TAKEN_HINT : PPC::BR_NONTAKEN_HINT;
498 // isOpcWithIntImmediate - This method tests to see if the node is a specific
499 // opcode and that it has a immediate integer right operand.
500 // If so Imm will receive the 32 bit value.
501 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
502 return N->getOpcode() == Opc
503 && isInt32Immediate(N->getOperand(1).getNode(), Imm);
506 void PPCDAGToDAGISel::selectFrameIndex(SDNode *SN, SDNode *N, unsigned Offset) {
508 int FI = cast<FrameIndexSDNode>(N)->getIndex();
509 SDValue TFI = CurDAG->getTargetFrameIndex(FI, N->getValueType(0));
510 unsigned Opc = N->getValueType(0) == MVT::i32 ? PPC::ADDI : PPC::ADDI8;
512 CurDAG->SelectNodeTo(SN, Opc, N->getValueType(0), TFI,
513 getSmallIPtrImm(Offset, dl));
515 ReplaceNode(SN, CurDAG->getMachineNode(Opc, dl, N->getValueType(0), TFI,
516 getSmallIPtrImm(Offset, dl)));
519 bool PPCDAGToDAGISel::isRotateAndMask(SDNode *N, unsigned Mask,
520 bool isShiftMask, unsigned &SH,
521 unsigned &MB, unsigned &ME) {
522 // Don't even go down this path for i64, since different logic will be
523 // necessary for rldicl/rldicr/rldimi.
524 if (N->getValueType(0) != MVT::i32)
528 unsigned Indeterminant = ~0; // bit mask marking indeterminant results
529 unsigned Opcode = N->getOpcode();
530 if (N->getNumOperands() != 2 ||
531 !isInt32Immediate(N->getOperand(1).getNode(), Shift) || (Shift > 31))
534 if (Opcode == ISD::SHL) {
535 // apply shift left to mask if it comes first
536 if (isShiftMask) Mask = Mask << Shift;
537 // determine which bits are made indeterminant by shift
538 Indeterminant = ~(0xFFFFFFFFu << Shift);
539 } else if (Opcode == ISD::SRL) {
540 // apply shift right to mask if it comes first
541 if (isShiftMask) Mask = Mask >> Shift;
542 // determine which bits are made indeterminant by shift
543 Indeterminant = ~(0xFFFFFFFFu >> Shift);
544 // adjust for the left rotate
546 } else if (Opcode == ISD::ROTL) {
552 // if the mask doesn't intersect any Indeterminant bits
553 if (Mask && !(Mask & Indeterminant)) {
555 // make sure the mask is still a mask (wrap arounds may not be)
556 return isRunOfOnes(Mask, MB, ME);
561 /// Turn an or of two masked values into the rotate left word immediate then
562 /// mask insert (rlwimi) instruction.
563 bool PPCDAGToDAGISel::tryBitfieldInsert(SDNode *N) {
564 SDValue Op0 = N->getOperand(0);
565 SDValue Op1 = N->getOperand(1);
568 KnownBits LKnown, RKnown;
569 CurDAG->computeKnownBits(Op0, LKnown);
570 CurDAG->computeKnownBits(Op1, RKnown);
572 unsigned TargetMask = LKnown.Zero.getZExtValue();
573 unsigned InsertMask = RKnown.Zero.getZExtValue();
575 if ((TargetMask | InsertMask) == 0xFFFFFFFF) {
576 unsigned Op0Opc = Op0.getOpcode();
577 unsigned Op1Opc = Op1.getOpcode();
578 unsigned Value, SH = 0;
579 TargetMask = ~TargetMask;
580 InsertMask = ~InsertMask;
582 // If the LHS has a foldable shift and the RHS does not, then swap it to the
583 // RHS so that we can fold the shift into the insert.
584 if (Op0Opc == ISD::AND && Op1Opc == ISD::AND) {
585 if (Op0.getOperand(0).getOpcode() == ISD::SHL ||
586 Op0.getOperand(0).getOpcode() == ISD::SRL) {
587 if (Op1.getOperand(0).getOpcode() != ISD::SHL &&
588 Op1.getOperand(0).getOpcode() != ISD::SRL) {
590 std::swap(Op0Opc, Op1Opc);
591 std::swap(TargetMask, InsertMask);
594 } else if (Op0Opc == ISD::SHL || Op0Opc == ISD::SRL) {
595 if (Op1Opc == ISD::AND && Op1.getOperand(0).getOpcode() != ISD::SHL &&
596 Op1.getOperand(0).getOpcode() != ISD::SRL) {
598 std::swap(Op0Opc, Op1Opc);
599 std::swap(TargetMask, InsertMask);
604 if (isRunOfOnes(InsertMask, MB, ME)) {
607 if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) &&
608 isInt32Immediate(Op1.getOperand(1), Value)) {
609 Op1 = Op1.getOperand(0);
610 SH = (Op1Opc == ISD::SHL) ? Value : 32 - Value;
612 if (Op1Opc == ISD::AND) {
613 // The AND mask might not be a constant, and we need to make sure that
614 // if we're going to fold the masking with the insert, all bits not
615 // know to be zero in the mask are known to be one.
617 CurDAG->computeKnownBits(Op1.getOperand(1), MKnown);
618 bool CanFoldMask = InsertMask == MKnown.One.getZExtValue();
620 unsigned SHOpc = Op1.getOperand(0).getOpcode();
621 if ((SHOpc == ISD::SHL || SHOpc == ISD::SRL) && CanFoldMask &&
622 isInt32Immediate(Op1.getOperand(0).getOperand(1), Value)) {
623 // Note that Value must be in range here (less than 32) because
624 // otherwise there would not be any bits set in InsertMask.
625 Op1 = Op1.getOperand(0).getOperand(0);
626 SH = (SHOpc == ISD::SHL) ? Value : 32 - Value;
631 SDValue Ops[] = { Op0, Op1, getI32Imm(SH, dl), getI32Imm(MB, dl),
633 ReplaceNode(N, CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops));
640 // Predict the number of instructions that would be generated by calling
642 static unsigned getInt64CountDirect(int64_t Imm) {
643 // Assume no remaining bits.
644 unsigned Remainder = 0;
645 // Assume no shift required.
648 // If it can't be represented as a 32 bit value.
649 if (!isInt<32>(Imm)) {
650 Shift = countTrailingZeros<uint64_t>(Imm);
651 int64_t ImmSh = static_cast<uint64_t>(Imm) >> Shift;
653 // If the shifted value fits 32 bits.
654 if (isInt<32>(ImmSh)) {
655 // Go with the shifted value.
658 // Still stuck with a 64 bit value.
665 // Intermediate operand.
668 // Handle first 32 bits.
669 unsigned Lo = Imm & 0xFFFF;
672 if (isInt<16>(Imm)) {
676 // Handle the Hi bits and Lo bits.
683 // If no shift, we're done.
684 if (!Shift) return Result;
686 // If Hi word == Lo word,
687 // we can use rldimi to insert the Lo word into Hi word.
688 if ((unsigned)(Imm & 0xFFFFFFFF) == Remainder) {
693 // Shift for next step if the upper 32-bits were not zero.
697 // Add in the last bits as required.
698 if ((Remainder >> 16) & 0xFFFF)
700 if (Remainder & 0xFFFF)
706 static uint64_t Rot64(uint64_t Imm, unsigned R) {
707 return (Imm << R) | (Imm >> (64 - R));
710 static unsigned getInt64Count(int64_t Imm) {
711 unsigned Count = getInt64CountDirect(Imm);
713 // If the instruction count is 1 or 2, we do not need further analysis
714 // since rotate + load constant requires at least 2 instructions.
718 for (unsigned r = 1; r < 63; ++r) {
719 uint64_t RImm = Rot64(Imm, r);
720 unsigned RCount = getInt64CountDirect(RImm) + 1;
721 Count = std::min(Count, RCount);
723 // See comments in getInt64 for an explanation of the logic below.
724 unsigned LS = findLastSet(RImm);
728 uint64_t OnesMask = -(int64_t) (UINT64_C(1) << (LS+1));
729 uint64_t RImmWithOnes = RImm | OnesMask;
731 RCount = getInt64CountDirect(RImmWithOnes) + 1;
732 Count = std::min(Count, RCount);
738 // Select a 64-bit constant. For cost-modeling purposes, getInt64Count
739 // (above) needs to be kept in sync with this function.
740 static SDNode *getInt64Direct(SelectionDAG *CurDAG, const SDLoc &dl,
742 // Assume no remaining bits.
743 unsigned Remainder = 0;
744 // Assume no shift required.
747 // If it can't be represented as a 32 bit value.
748 if (!isInt<32>(Imm)) {
749 Shift = countTrailingZeros<uint64_t>(Imm);
750 int64_t ImmSh = static_cast<uint64_t>(Imm) >> Shift;
752 // If the shifted value fits 32 bits.
753 if (isInt<32>(ImmSh)) {
754 // Go with the shifted value.
757 // Still stuck with a 64 bit value.
764 // Intermediate operand.
767 // Handle first 32 bits.
768 unsigned Lo = Imm & 0xFFFF;
769 unsigned Hi = (Imm >> 16) & 0xFFFF;
771 auto getI32Imm = [CurDAG, dl](unsigned Imm) {
772 return CurDAG->getTargetConstant(Imm, dl, MVT::i32);
776 if (isInt<16>(Imm)) {
778 Result = CurDAG->getMachineNode(PPC::LI8, dl, MVT::i64, getI32Imm(Lo));
780 // Handle the Hi bits.
781 unsigned OpC = Hi ? PPC::LIS8 : PPC::LI8;
782 Result = CurDAG->getMachineNode(OpC, dl, MVT::i64, getI32Imm(Hi));
784 Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64,
785 SDValue(Result, 0), getI32Imm(Lo));
788 Result = CurDAG->getMachineNode(PPC::LIS8, dl, MVT::i64, getI32Imm(Hi));
791 // If no shift, we're done.
792 if (!Shift) return Result;
794 // If Hi word == Lo word,
795 // we can use rldimi to insert the Lo word into Hi word.
796 if ((unsigned)(Imm & 0xFFFFFFFF) == Remainder) {
798 { SDValue(Result, 0), SDValue(Result, 0), getI32Imm(Shift), getI32Imm(0)};
799 return CurDAG->getMachineNode(PPC::RLDIMI, dl, MVT::i64, Ops);
802 // Shift for next step if the upper 32-bits were not zero.
804 Result = CurDAG->getMachineNode(PPC::RLDICR, dl, MVT::i64,
807 getI32Imm(63 - Shift));
810 // Add in the last bits as required.
811 if ((Hi = (Remainder >> 16) & 0xFFFF)) {
812 Result = CurDAG->getMachineNode(PPC::ORIS8, dl, MVT::i64,
813 SDValue(Result, 0), getI32Imm(Hi));
815 if ((Lo = Remainder & 0xFFFF)) {
816 Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64,
817 SDValue(Result, 0), getI32Imm(Lo));
823 static SDNode *getInt64(SelectionDAG *CurDAG, const SDLoc &dl, int64_t Imm) {
824 unsigned Count = getInt64CountDirect(Imm);
826 // If the instruction count is 1 or 2, we do not need further analysis
827 // since rotate + load constant requires at least 2 instructions.
829 return getInt64Direct(CurDAG, dl, Imm);
836 for (unsigned r = 1; r < 63; ++r) {
837 uint64_t RImm = Rot64(Imm, r);
838 unsigned RCount = getInt64CountDirect(RImm) + 1;
839 if (RCount < Count) {
846 // If the immediate to generate has many trailing zeros, it might be
847 // worthwhile to generate a rotated value with too many leading ones
848 // (because that's free with li/lis's sign-extension semantics), and then
849 // mask them off after rotation.
851 unsigned LS = findLastSet(RImm);
852 // We're adding (63-LS) higher-order ones, and we expect to mask them off
853 // after performing the inverse rotation by (64-r). So we need that:
854 // 63-LS == 64-r => LS == r-1
858 uint64_t OnesMask = -(int64_t) (UINT64_C(1) << (LS+1));
859 uint64_t RImmWithOnes = RImm | OnesMask;
861 RCount = getInt64CountDirect(RImmWithOnes) + 1;
862 if (RCount < Count) {
865 MatImm = RImmWithOnes;
871 return getInt64Direct(CurDAG, dl, Imm);
873 auto getI32Imm = [CurDAG, dl](unsigned Imm) {
874 return CurDAG->getTargetConstant(Imm, dl, MVT::i32);
877 SDValue Val = SDValue(getInt64Direct(CurDAG, dl, MatImm), 0);
878 return CurDAG->getMachineNode(PPC::RLDICR, dl, MVT::i64, Val,
879 getI32Imm(64 - RMin), getI32Imm(MaskEnd));
882 // Select a 64-bit constant.
883 static SDNode *getInt64(SelectionDAG *CurDAG, SDNode *N) {
887 int64_t Imm = cast<ConstantSDNode>(N)->getZExtValue();
888 return getInt64(CurDAG, dl, Imm);
893 class BitPermutationSelector {
897 // The bit number in the value, using a convention where bit 0 is the
906 ValueBit(SDValue V, unsigned I, Kind K = Variable)
907 : V(V), Idx(I), K(K) {}
908 ValueBit(Kind K = Variable)
909 : V(SDValue(nullptr, 0)), Idx(UINT32_MAX), K(K) {}
911 bool isZero() const {
912 return K == ConstZero;
915 bool hasValue() const {
916 return K == Variable;
919 SDValue getValue() const {
920 assert(hasValue() && "Cannot get the value of a constant bit");
924 unsigned getValueBitIndex() const {
925 assert(hasValue() && "Cannot get the value bit index of a constant bit");
930 // A bit group has the same underlying value and the same rotate factor.
934 unsigned StartIdx, EndIdx;
936 // This rotation amount assumes that the lower 32 bits of the quantity are
937 // replicated in the high 32 bits by the rotation operator (which is done
938 // by rlwinm and friends in 64-bit mode).
940 // Did converting to Repl32 == true change the rotation factor? If it did,
941 // it decreased it by 32.
943 // Was this group coalesced after setting Repl32 to true?
944 bool Repl32Coalesced;
946 BitGroup(SDValue V, unsigned R, unsigned S, unsigned E)
947 : V(V), RLAmt(R), StartIdx(S), EndIdx(E), Repl32(false), Repl32CR(false),
948 Repl32Coalesced(false) {
949 DEBUG(dbgs() << "\tbit group for " << V.getNode() << " RLAmt = " << R <<
950 " [" << S << ", " << E << "]\n");
954 // Information on each (Value, RLAmt) pair (like the number of groups
955 // associated with each) used to choose the lowering method.
956 struct ValueRotInfo {
958 unsigned RLAmt = std::numeric_limits<unsigned>::max();
959 unsigned NumGroups = 0;
960 unsigned FirstGroupStartIdx = std::numeric_limits<unsigned>::max();
963 ValueRotInfo() = default;
965 // For sorting (in reverse order) by NumGroups, and then by
966 // FirstGroupStartIdx.
967 bool operator < (const ValueRotInfo &Other) const {
968 // We need to sort so that the non-Repl32 come first because, when we're
969 // doing masking, the Repl32 bit groups might be subsumed into the 64-bit
970 // masking operation.
971 if (Repl32 < Other.Repl32)
973 else if (Repl32 > Other.Repl32)
975 else if (NumGroups > Other.NumGroups)
977 else if (NumGroups < Other.NumGroups)
979 else if (FirstGroupStartIdx < Other.FirstGroupStartIdx)
985 using ValueBitsMemoizedValue = std::pair<bool, SmallVector<ValueBit, 64>>;
986 using ValueBitsMemoizer =
987 DenseMap<SDValue, std::unique_ptr<ValueBitsMemoizedValue>>;
988 ValueBitsMemoizer Memoizer;
990 // Return a pair of bool and a SmallVector pointer to a memoization entry.
991 // The bool is true if something interesting was deduced, otherwise if we're
992 // providing only a generic representation of V (or something else likewise
993 // uninteresting for instruction selection) through the SmallVector.
994 std::pair<bool, SmallVector<ValueBit, 64> *> getValueBits(SDValue V,
996 auto &ValueEntry = Memoizer[V];
998 return std::make_pair(ValueEntry->first, &ValueEntry->second);
999 ValueEntry.reset(new ValueBitsMemoizedValue());
1000 bool &Interesting = ValueEntry->first;
1001 SmallVector<ValueBit, 64> &Bits = ValueEntry->second;
1002 Bits.resize(NumBits);
1004 switch (V.getOpcode()) {
1007 if (isa<ConstantSDNode>(V.getOperand(1))) {
1008 unsigned RotAmt = V.getConstantOperandVal(1);
1010 const auto &LHSBits = *getValueBits(V.getOperand(0), NumBits).second;
1012 for (unsigned i = 0; i < NumBits; ++i)
1013 Bits[i] = LHSBits[i < RotAmt ? i + (NumBits - RotAmt) : i - RotAmt];
1015 return std::make_pair(Interesting = true, &Bits);
1019 if (isa<ConstantSDNode>(V.getOperand(1))) {
1020 unsigned ShiftAmt = V.getConstantOperandVal(1);
1022 const auto &LHSBits = *getValueBits(V.getOperand(0), NumBits).second;
1024 for (unsigned i = ShiftAmt; i < NumBits; ++i)
1025 Bits[i] = LHSBits[i - ShiftAmt];
1027 for (unsigned i = 0; i < ShiftAmt; ++i)
1028 Bits[i] = ValueBit(ValueBit::ConstZero);
1030 return std::make_pair(Interesting = true, &Bits);
1034 if (isa<ConstantSDNode>(V.getOperand(1))) {
1035 unsigned ShiftAmt = V.getConstantOperandVal(1);
1037 const auto &LHSBits = *getValueBits(V.getOperand(0), NumBits).second;
1039 for (unsigned i = 0; i < NumBits - ShiftAmt; ++i)
1040 Bits[i] = LHSBits[i + ShiftAmt];
1042 for (unsigned i = NumBits - ShiftAmt; i < NumBits; ++i)
1043 Bits[i] = ValueBit(ValueBit::ConstZero);
1045 return std::make_pair(Interesting = true, &Bits);
1049 if (isa<ConstantSDNode>(V.getOperand(1))) {
1050 uint64_t Mask = V.getConstantOperandVal(1);
1052 const SmallVector<ValueBit, 64> *LHSBits;
1053 // Mark this as interesting, only if the LHS was also interesting. This
1054 // prevents the overall procedure from matching a single immediate 'and'
1055 // (which is non-optimal because such an and might be folded with other
1056 // things if we don't select it here).
1057 std::tie(Interesting, LHSBits) = getValueBits(V.getOperand(0), NumBits);
1059 for (unsigned i = 0; i < NumBits; ++i)
1060 if (((Mask >> i) & 1) == 1)
1061 Bits[i] = (*LHSBits)[i];
1063 Bits[i] = ValueBit(ValueBit::ConstZero);
1065 return std::make_pair(Interesting, &Bits);
1069 const auto &LHSBits = *getValueBits(V.getOperand(0), NumBits).second;
1070 const auto &RHSBits = *getValueBits(V.getOperand(1), NumBits).second;
1072 bool AllDisjoint = true;
1073 for (unsigned i = 0; i < NumBits; ++i)
1074 if (LHSBits[i].isZero())
1075 Bits[i] = RHSBits[i];
1076 else if (RHSBits[i].isZero())
1077 Bits[i] = LHSBits[i];
1079 AllDisjoint = false;
1086 return std::make_pair(Interesting = true, &Bits);
1090 for (unsigned i = 0; i < NumBits; ++i)
1091 Bits[i] = ValueBit(V, i);
1093 return std::make_pair(Interesting = false, &Bits);
1096 // For each value (except the constant ones), compute the left-rotate amount
1097 // to get it from its original to final position.
1098 void computeRotationAmounts() {
1100 RLAmt.resize(Bits.size());
1101 for (unsigned i = 0; i < Bits.size(); ++i)
1102 if (Bits[i].hasValue()) {
1103 unsigned VBI = Bits[i].getValueBitIndex();
1107 RLAmt[i] = Bits.size() - (VBI - i);
1108 } else if (Bits[i].isZero()) {
1110 RLAmt[i] = UINT32_MAX;
1112 llvm_unreachable("Unknown value bit type");
1116 // Collect groups of consecutive bits with the same underlying value and
1117 // rotation factor. If we're doing late masking, we ignore zeros, otherwise
1118 // they break up groups.
1119 void collectBitGroups(bool LateMask) {
1122 unsigned LastRLAmt = RLAmt[0];
1123 SDValue LastValue = Bits[0].hasValue() ? Bits[0].getValue() : SDValue();
1124 unsigned LastGroupStartIdx = 0;
1125 for (unsigned i = 1; i < Bits.size(); ++i) {
1126 unsigned ThisRLAmt = RLAmt[i];
1127 SDValue ThisValue = Bits[i].hasValue() ? Bits[i].getValue() : SDValue();
1128 if (LateMask && !ThisValue) {
1129 ThisValue = LastValue;
1130 ThisRLAmt = LastRLAmt;
1131 // If we're doing late masking, then the first bit group always starts
1132 // at zero (even if the first bits were zero).
1133 if (BitGroups.empty())
1134 LastGroupStartIdx = 0;
1137 // If this bit has the same underlying value and the same rotate factor as
1138 // the last one, then they're part of the same group.
1139 if (ThisRLAmt == LastRLAmt && ThisValue == LastValue)
1142 if (LastValue.getNode())
1143 BitGroups.push_back(BitGroup(LastValue, LastRLAmt, LastGroupStartIdx,
1145 LastRLAmt = ThisRLAmt;
1146 LastValue = ThisValue;
1147 LastGroupStartIdx = i;
1149 if (LastValue.getNode())
1150 BitGroups.push_back(BitGroup(LastValue, LastRLAmt, LastGroupStartIdx,
1153 if (BitGroups.empty())
1156 // We might be able to combine the first and last groups.
1157 if (BitGroups.size() > 1) {
1158 // If the first and last groups are the same, then remove the first group
1159 // in favor of the last group, making the ending index of the last group
1160 // equal to the ending index of the to-be-removed first group.
1161 if (BitGroups[0].StartIdx == 0 &&
1162 BitGroups[BitGroups.size()-1].EndIdx == Bits.size()-1 &&
1163 BitGroups[0].V == BitGroups[BitGroups.size()-1].V &&
1164 BitGroups[0].RLAmt == BitGroups[BitGroups.size()-1].RLAmt) {
1165 DEBUG(dbgs() << "\tcombining final bit group with initial one\n");
1166 BitGroups[BitGroups.size()-1].EndIdx = BitGroups[0].EndIdx;
1167 BitGroups.erase(BitGroups.begin());
1172 // Take all (SDValue, RLAmt) pairs and sort them by the number of groups
1173 // associated with each. If there is a degeneracy, pick the one that occurs
1174 // first (in the final value).
1175 void collectValueRotInfo() {
1178 for (auto &BG : BitGroups) {
1179 unsigned RLAmtKey = BG.RLAmt + (BG.Repl32 ? 64 : 0);
1180 ValueRotInfo &VRI = ValueRots[std::make_pair(BG.V, RLAmtKey)];
1182 VRI.RLAmt = BG.RLAmt;
1183 VRI.Repl32 = BG.Repl32;
1185 VRI.FirstGroupStartIdx = std::min(VRI.FirstGroupStartIdx, BG.StartIdx);
1188 // Now that we've collected the various ValueRotInfo instances, we need to
1190 ValueRotsVec.clear();
1191 for (auto &I : ValueRots) {
1192 ValueRotsVec.push_back(I.second);
1194 std::sort(ValueRotsVec.begin(), ValueRotsVec.end());
1197 // In 64-bit mode, rlwinm and friends have a rotation operator that
1198 // replicates the low-order 32 bits into the high-order 32-bits. The mask
1199 // indices of these instructions can only be in the lower 32 bits, so they
1200 // can only represent some 64-bit bit groups. However, when they can be used,
1201 // the 32-bit replication can be used to represent, as a single bit group,
1202 // otherwise separate bit groups. We'll convert to replicated-32-bit bit
1203 // groups when possible. Returns true if any of the bit groups were
1205 void assignRepl32BitGroups() {
1206 // If we have bits like this:
1208 // Indices: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1209 // V bits: ... 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24
1210 // Groups: | RLAmt = 8 | RLAmt = 40 |
1212 // But, making use of a 32-bit operation that replicates the low-order 32
1213 // bits into the high-order 32 bits, this can be one bit group with a RLAmt
1216 auto IsAllLow32 = [this](BitGroup & BG) {
1217 if (BG.StartIdx <= BG.EndIdx) {
1218 for (unsigned i = BG.StartIdx; i <= BG.EndIdx; ++i) {
1219 if (!Bits[i].hasValue())
1221 if (Bits[i].getValueBitIndex() >= 32)
1225 for (unsigned i = BG.StartIdx; i < Bits.size(); ++i) {
1226 if (!Bits[i].hasValue())
1228 if (Bits[i].getValueBitIndex() >= 32)
1231 for (unsigned i = 0; i <= BG.EndIdx; ++i) {
1232 if (!Bits[i].hasValue())
1234 if (Bits[i].getValueBitIndex() >= 32)
1242 for (auto &BG : BitGroups) {
1243 if (BG.StartIdx < 32 && BG.EndIdx < 32) {
1244 if (IsAllLow32(BG)) {
1245 if (BG.RLAmt >= 32) {
1252 DEBUG(dbgs() << "\t32-bit replicated bit group for " <<
1253 BG.V.getNode() << " RLAmt = " << BG.RLAmt <<
1254 " [" << BG.StartIdx << ", " << BG.EndIdx << "]\n");
1259 // Now walk through the bit groups, consolidating where possible.
1260 for (auto I = BitGroups.begin(); I != BitGroups.end();) {
1261 // We might want to remove this bit group by merging it with the previous
1262 // group (which might be the ending group).
1263 auto IP = (I == BitGroups.begin()) ?
1264 std::prev(BitGroups.end()) : std::prev(I);
1265 if (I->Repl32 && IP->Repl32 && I->V == IP->V && I->RLAmt == IP->RLAmt &&
1266 I->StartIdx == (IP->EndIdx + 1) % 64 && I != IP) {
1268 DEBUG(dbgs() << "\tcombining 32-bit replicated bit group for " <<
1269 I->V.getNode() << " RLAmt = " << I->RLAmt <<
1270 " [" << I->StartIdx << ", " << I->EndIdx <<
1271 "] with group with range [" <<
1272 IP->StartIdx << ", " << IP->EndIdx << "]\n");
1274 IP->EndIdx = I->EndIdx;
1275 IP->Repl32CR = IP->Repl32CR || I->Repl32CR;
1276 IP->Repl32Coalesced = true;
1277 I = BitGroups.erase(I);
1280 // There is a special case worth handling: If there is a single group
1281 // covering the entire upper 32 bits, and it can be merged with both
1282 // the next and previous groups (which might be the same group), then
1283 // do so. If it is the same group (so there will be only one group in
1284 // total), then we need to reverse the order of the range so that it
1285 // covers the entire 64 bits.
1286 if (I->StartIdx == 32 && I->EndIdx == 63) {
1287 assert(std::next(I) == BitGroups.end() &&
1288 "bit group ends at index 63 but there is another?");
1289 auto IN = BitGroups.begin();
1291 if (IP->Repl32 && IN->Repl32 && I->V == IP->V && I->V == IN->V &&
1292 (I->RLAmt % 32) == IP->RLAmt && (I->RLAmt % 32) == IN->RLAmt &&
1293 IP->EndIdx == 31 && IN->StartIdx == 0 && I != IP &&
1296 DEBUG(dbgs() << "\tcombining bit group for " <<
1297 I->V.getNode() << " RLAmt = " << I->RLAmt <<
1298 " [" << I->StartIdx << ", " << I->EndIdx <<
1299 "] with 32-bit replicated groups with ranges [" <<
1300 IP->StartIdx << ", " << IP->EndIdx << "] and [" <<
1301 IN->StartIdx << ", " << IN->EndIdx << "]\n");
1304 // There is only one other group; change it to cover the whole
1305 // range (backward, so that it can still be Repl32 but cover the
1306 // whole 64-bit range).
1309 IP->Repl32CR = IP->Repl32CR || I->RLAmt >= 32;
1310 IP->Repl32Coalesced = true;
1311 I = BitGroups.erase(I);
1313 // There are two separate groups, one before this group and one
1314 // after us (at the beginning). We're going to remove this group,
1315 // but also the group at the very beginning.
1316 IP->EndIdx = IN->EndIdx;
1317 IP->Repl32CR = IP->Repl32CR || IN->Repl32CR || I->RLAmt >= 32;
1318 IP->Repl32Coalesced = true;
1319 I = BitGroups.erase(I);
1320 BitGroups.erase(BitGroups.begin());
1323 // This must be the last group in the vector (and we might have
1324 // just invalidated the iterator above), so break here.
1334 SDValue getI32Imm(unsigned Imm, const SDLoc &dl) {
1335 return CurDAG->getTargetConstant(Imm, dl, MVT::i32);
1338 uint64_t getZerosMask() {
1340 for (unsigned i = 0; i < Bits.size(); ++i) {
1341 if (Bits[i].hasValue())
1343 Mask |= (UINT64_C(1) << i);
1349 // Depending on the number of groups for a particular value, it might be
1350 // better to rotate, mask explicitly (using andi/andis), and then or the
1351 // result. Select this part of the result first.
1352 void SelectAndParts32(const SDLoc &dl, SDValue &Res, unsigned *InstCnt) {
1353 if (BPermRewriterNoMasking)
1356 for (ValueRotInfo &VRI : ValueRotsVec) {
1358 for (unsigned i = 0; i < Bits.size(); ++i) {
1359 if (!Bits[i].hasValue() || Bits[i].getValue() != VRI.V)
1361 if (RLAmt[i] != VRI.RLAmt)
1366 // Compute the masks for andi/andis that would be necessary.
1367 unsigned ANDIMask = (Mask & UINT16_MAX), ANDISMask = Mask >> 16;
1368 assert((ANDIMask != 0 || ANDISMask != 0) &&
1369 "No set bits in mask for value bit groups");
1370 bool NeedsRotate = VRI.RLAmt != 0;
1372 // We're trying to minimize the number of instructions. If we have one
1373 // group, using one of andi/andis can break even. If we have three
1374 // groups, we can use both andi and andis and break even (to use both
1375 // andi and andis we also need to or the results together). We need four
1376 // groups if we also need to rotate. To use andi/andis we need to do more
1377 // than break even because rotate-and-mask instructions tend to be easier
1380 // FIXME: We've biased here against using andi/andis, which is right for
1381 // POWER cores, but not optimal everywhere. For example, on the A2,
1382 // andi/andis have single-cycle latency whereas the rotate-and-mask
1383 // instructions take two cycles, and it would be better to bias toward
1384 // andi/andis in break-even cases.
1386 unsigned NumAndInsts = (unsigned) NeedsRotate +
1387 (unsigned) (ANDIMask != 0) +
1388 (unsigned) (ANDISMask != 0) +
1389 (unsigned) (ANDIMask != 0 && ANDISMask != 0) +
1390 (unsigned) (bool) Res;
1392 DEBUG(dbgs() << "\t\trotation groups for " << VRI.V.getNode() <<
1393 " RL: " << VRI.RLAmt << ":" <<
1394 "\n\t\t\tisel using masking: " << NumAndInsts <<
1395 " using rotates: " << VRI.NumGroups << "\n");
1397 if (NumAndInsts >= VRI.NumGroups)
1400 DEBUG(dbgs() << "\t\t\t\tusing masking\n");
1402 if (InstCnt) *InstCnt += NumAndInsts;
1407 { VRI.V, getI32Imm(VRI.RLAmt, dl), getI32Imm(0, dl),
1408 getI32Imm(31, dl) };
1409 VRot = SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32,
1415 SDValue ANDIVal, ANDISVal;
1417 ANDIVal = SDValue(CurDAG->getMachineNode(PPC::ANDIo, dl, MVT::i32,
1418 VRot, getI32Imm(ANDIMask, dl)), 0);
1420 ANDISVal = SDValue(CurDAG->getMachineNode(PPC::ANDISo, dl, MVT::i32,
1421 VRot, getI32Imm(ANDISMask, dl)), 0);
1425 TotalVal = ANDISVal;
1429 TotalVal = SDValue(CurDAG->getMachineNode(PPC::OR, dl, MVT::i32,
1430 ANDIVal, ANDISVal), 0);
1435 Res = SDValue(CurDAG->getMachineNode(PPC::OR, dl, MVT::i32,
1438 // Now, remove all groups with this underlying value and rotation
1440 eraseMatchingBitGroups([VRI](const BitGroup &BG) {
1441 return BG.V == VRI.V && BG.RLAmt == VRI.RLAmt;
1446 // Instruction selection for the 32-bit case.
1447 SDNode *Select32(SDNode *N, bool LateMask, unsigned *InstCnt) {
1451 if (InstCnt) *InstCnt = 0;
1453 // Take care of cases that should use andi/andis first.
1454 SelectAndParts32(dl, Res, InstCnt);
1456 // If we've not yet selected a 'starting' instruction, and we have no zeros
1457 // to fill in, select the (Value, RLAmt) with the highest priority (largest
1458 // number of groups), and start with this rotated value.
1459 if ((!HasZeros || LateMask) && !Res) {
1460 ValueRotInfo &VRI = ValueRotsVec[0];
1462 if (InstCnt) *InstCnt += 1;
1464 { VRI.V, getI32Imm(VRI.RLAmt, dl), getI32Imm(0, dl),
1465 getI32Imm(31, dl) };
1466 Res = SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops),
1472 // Now, remove all groups with this underlying value and rotation factor.
1473 eraseMatchingBitGroups([VRI](const BitGroup &BG) {
1474 return BG.V == VRI.V && BG.RLAmt == VRI.RLAmt;
1478 if (InstCnt) *InstCnt += BitGroups.size();
1480 // Insert the other groups (one at a time).
1481 for (auto &BG : BitGroups) {
1484 { BG.V, getI32Imm(BG.RLAmt, dl),
1485 getI32Imm(Bits.size() - BG.EndIdx - 1, dl),
1486 getI32Imm(Bits.size() - BG.StartIdx - 1, dl) };
1487 Res = SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops), 0);
1490 { Res, BG.V, getI32Imm(BG.RLAmt, dl),
1491 getI32Imm(Bits.size() - BG.EndIdx - 1, dl),
1492 getI32Imm(Bits.size() - BG.StartIdx - 1, dl) };
1493 Res = SDValue(CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops), 0);
1498 unsigned Mask = (unsigned) getZerosMask();
1500 unsigned ANDIMask = (Mask & UINT16_MAX), ANDISMask = Mask >> 16;
1501 assert((ANDIMask != 0 || ANDISMask != 0) &&
1502 "No set bits in zeros mask?");
1504 if (InstCnt) *InstCnt += (unsigned) (ANDIMask != 0) +
1505 (unsigned) (ANDISMask != 0) +
1506 (unsigned) (ANDIMask != 0 && ANDISMask != 0);
1508 SDValue ANDIVal, ANDISVal;
1510 ANDIVal = SDValue(CurDAG->getMachineNode(PPC::ANDIo, dl, MVT::i32,
1511 Res, getI32Imm(ANDIMask, dl)), 0);
1513 ANDISVal = SDValue(CurDAG->getMachineNode(PPC::ANDISo, dl, MVT::i32,
1514 Res, getI32Imm(ANDISMask, dl)), 0);
1521 Res = SDValue(CurDAG->getMachineNode(PPC::OR, dl, MVT::i32,
1522 ANDIVal, ANDISVal), 0);
1525 return Res.getNode();
1528 unsigned SelectRotMask64Count(unsigned RLAmt, bool Repl32,
1529 unsigned MaskStart, unsigned MaskEnd,
1531 // In the notation used by the instructions, 'start' and 'end' are reversed
1532 // because bits are counted from high to low order.
1533 unsigned InstMaskStart = 64 - MaskEnd - 1,
1534 InstMaskEnd = 64 - MaskStart - 1;
1539 if ((!IsIns && (InstMaskEnd == 63 || InstMaskStart == 0)) ||
1540 InstMaskEnd == 63 - RLAmt)
1546 // For 64-bit values, not all combinations of rotates and masks are
1547 // available. Produce one if it is available.
1548 SDValue SelectRotMask64(SDValue V, const SDLoc &dl, unsigned RLAmt,
1549 bool Repl32, unsigned MaskStart, unsigned MaskEnd,
1550 unsigned *InstCnt = nullptr) {
1551 // In the notation used by the instructions, 'start' and 'end' are reversed
1552 // because bits are counted from high to low order.
1553 unsigned InstMaskStart = 64 - MaskEnd - 1,
1554 InstMaskEnd = 64 - MaskStart - 1;
1556 if (InstCnt) *InstCnt += 1;
1559 // This rotation amount assumes that the lower 32 bits of the quantity
1560 // are replicated in the high 32 bits by the rotation operator (which is
1561 // done by rlwinm and friends).
1562 assert(InstMaskStart >= 32 && "Mask cannot start out of range");
1563 assert(InstMaskEnd >= 32 && "Mask cannot end out of range");
1565 { V, getI32Imm(RLAmt, dl), getI32Imm(InstMaskStart - 32, dl),
1566 getI32Imm(InstMaskEnd - 32, dl) };
1567 return SDValue(CurDAG->getMachineNode(PPC::RLWINM8, dl, MVT::i64,
1571 if (InstMaskEnd == 63) {
1573 { V, getI32Imm(RLAmt, dl), getI32Imm(InstMaskStart, dl) };
1574 return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, Ops), 0);
1577 if (InstMaskStart == 0) {
1579 { V, getI32Imm(RLAmt, dl), getI32Imm(InstMaskEnd, dl) };
1580 return SDValue(CurDAG->getMachineNode(PPC::RLDICR, dl, MVT::i64, Ops), 0);
1583 if (InstMaskEnd == 63 - RLAmt) {
1585 { V, getI32Imm(RLAmt, dl), getI32Imm(InstMaskStart, dl) };
1586 return SDValue(CurDAG->getMachineNode(PPC::RLDIC, dl, MVT::i64, Ops), 0);
1589 // We cannot do this with a single instruction, so we'll use two. The
1590 // problem is that we're not free to choose both a rotation amount and mask
1591 // start and end independently. We can choose an arbitrary mask start and
1592 // end, but then the rotation amount is fixed. Rotation, however, can be
1593 // inverted, and so by applying an "inverse" rotation first, we can get the
1595 if (InstCnt) *InstCnt += 1;
1597 // The rotation mask for the second instruction must be MaskStart.
1598 unsigned RLAmt2 = MaskStart;
1599 // The first instruction must rotate V so that the overall rotation amount
1601 unsigned RLAmt1 = (64 + RLAmt - RLAmt2) % 64;
1603 V = SelectRotMask64(V, dl, RLAmt1, false, 0, 63);
1604 return SelectRotMask64(V, dl, RLAmt2, false, MaskStart, MaskEnd);
1607 // For 64-bit values, not all combinations of rotates and masks are
1608 // available. Produce a rotate-mask-and-insert if one is available.
1609 SDValue SelectRotMaskIns64(SDValue Base, SDValue V, const SDLoc &dl,
1610 unsigned RLAmt, bool Repl32, unsigned MaskStart,
1611 unsigned MaskEnd, unsigned *InstCnt = nullptr) {
1612 // In the notation used by the instructions, 'start' and 'end' are reversed
1613 // because bits are counted from high to low order.
1614 unsigned InstMaskStart = 64 - MaskEnd - 1,
1615 InstMaskEnd = 64 - MaskStart - 1;
1617 if (InstCnt) *InstCnt += 1;
1620 // This rotation amount assumes that the lower 32 bits of the quantity
1621 // are replicated in the high 32 bits by the rotation operator (which is
1622 // done by rlwinm and friends).
1623 assert(InstMaskStart >= 32 && "Mask cannot start out of range");
1624 assert(InstMaskEnd >= 32 && "Mask cannot end out of range");
1626 { Base, V, getI32Imm(RLAmt, dl), getI32Imm(InstMaskStart - 32, dl),
1627 getI32Imm(InstMaskEnd - 32, dl) };
1628 return SDValue(CurDAG->getMachineNode(PPC::RLWIMI8, dl, MVT::i64,
1632 if (InstMaskEnd == 63 - RLAmt) {
1634 { Base, V, getI32Imm(RLAmt, dl), getI32Imm(InstMaskStart, dl) };
1635 return SDValue(CurDAG->getMachineNode(PPC::RLDIMI, dl, MVT::i64, Ops), 0);
1638 // We cannot do this with a single instruction, so we'll use two. The
1639 // problem is that we're not free to choose both a rotation amount and mask
1640 // start and end independently. We can choose an arbitrary mask start and
1641 // end, but then the rotation amount is fixed. Rotation, however, can be
1642 // inverted, and so by applying an "inverse" rotation first, we can get the
1644 if (InstCnt) *InstCnt += 1;
1646 // The rotation mask for the second instruction must be MaskStart.
1647 unsigned RLAmt2 = MaskStart;
1648 // The first instruction must rotate V so that the overall rotation amount
1650 unsigned RLAmt1 = (64 + RLAmt - RLAmt2) % 64;
1652 V = SelectRotMask64(V, dl, RLAmt1, false, 0, 63);
1653 return SelectRotMaskIns64(Base, V, dl, RLAmt2, false, MaskStart, MaskEnd);
1656 void SelectAndParts64(const SDLoc &dl, SDValue &Res, unsigned *InstCnt) {
1657 if (BPermRewriterNoMasking)
1660 // The idea here is the same as in the 32-bit version, but with additional
1661 // complications from the fact that Repl32 might be true. Because we
1662 // aggressively convert bit groups to Repl32 form (which, for small
1663 // rotation factors, involves no other change), and then coalesce, it might
1664 // be the case that a single 64-bit masking operation could handle both
1665 // some Repl32 groups and some non-Repl32 groups. If converting to Repl32
1666 // form allowed coalescing, then we must use a 32-bit rotaton in order to
1667 // completely capture the new combined bit group.
1669 for (ValueRotInfo &VRI : ValueRotsVec) {
1672 // We need to add to the mask all bits from the associated bit groups.
1673 // If Repl32 is false, we need to add bits from bit groups that have
1674 // Repl32 true, but are trivially convertable to Repl32 false. Such a
1675 // group is trivially convertable if it overlaps only with the lower 32
1676 // bits, and the group has not been coalesced.
1677 auto MatchingBG = [VRI](const BitGroup &BG) {
1681 unsigned EffRLAmt = BG.RLAmt;
1682 if (!VRI.Repl32 && BG.Repl32) {
1683 if (BG.StartIdx < 32 && BG.EndIdx < 32 && BG.StartIdx <= BG.EndIdx &&
1684 !BG.Repl32Coalesced) {
1690 } else if (VRI.Repl32 != BG.Repl32) {
1694 return VRI.RLAmt == EffRLAmt;
1697 for (auto &BG : BitGroups) {
1698 if (!MatchingBG(BG))
1701 if (BG.StartIdx <= BG.EndIdx) {
1702 for (unsigned i = BG.StartIdx; i <= BG.EndIdx; ++i)
1703 Mask |= (UINT64_C(1) << i);
1705 for (unsigned i = BG.StartIdx; i < Bits.size(); ++i)
1706 Mask |= (UINT64_C(1) << i);
1707 for (unsigned i = 0; i <= BG.EndIdx; ++i)
1708 Mask |= (UINT64_C(1) << i);
1712 // We can use the 32-bit andi/andis technique if the mask does not
1713 // require any higher-order bits. This can save an instruction compared
1714 // to always using the general 64-bit technique.
1715 bool Use32BitInsts = isUInt<32>(Mask);
1716 // Compute the masks for andi/andis that would be necessary.
1717 unsigned ANDIMask = (Mask & UINT16_MAX),
1718 ANDISMask = (Mask >> 16) & UINT16_MAX;
1720 bool NeedsRotate = VRI.RLAmt || (VRI.Repl32 && !isUInt<32>(Mask));
1722 unsigned NumAndInsts = (unsigned) NeedsRotate +
1723 (unsigned) (bool) Res;
1725 NumAndInsts += (unsigned) (ANDIMask != 0) + (unsigned) (ANDISMask != 0) +
1726 (unsigned) (ANDIMask != 0 && ANDISMask != 0);
1728 NumAndInsts += getInt64Count(Mask) + /* and */ 1;
1730 unsigned NumRLInsts = 0;
1731 bool FirstBG = true;
1732 bool MoreBG = false;
1733 for (auto &BG : BitGroups) {
1734 if (!MatchingBG(BG)) {
1739 SelectRotMask64Count(BG.RLAmt, BG.Repl32, BG.StartIdx, BG.EndIdx,
1744 DEBUG(dbgs() << "\t\trotation groups for " << VRI.V.getNode() <<
1745 " RL: " << VRI.RLAmt << (VRI.Repl32 ? " (32):" : ":") <<
1746 "\n\t\t\tisel using masking: " << NumAndInsts <<
1747 " using rotates: " << NumRLInsts << "\n");
1749 // When we'd use andi/andis, we bias toward using the rotates (andi only
1750 // has a record form, and is cracked on POWER cores). However, when using
1751 // general 64-bit constant formation, bias toward the constant form,
1752 // because that exposes more opportunities for CSE.
1753 if (NumAndInsts > NumRLInsts)
1755 // When merging multiple bit groups, instruction or is used.
1756 // But when rotate is used, rldimi can inert the rotated value into any
1757 // register, so instruction or can be avoided.
1758 if ((Use32BitInsts || MoreBG) && NumAndInsts == NumRLInsts)
1761 DEBUG(dbgs() << "\t\t\t\tusing masking\n");
1763 if (InstCnt) *InstCnt += NumAndInsts;
1766 // We actually need to generate a rotation if we have a non-zero rotation
1767 // factor or, in the Repl32 case, if we care about any of the
1768 // higher-order replicated bits. In the latter case, we generate a mask
1769 // backward so that it actually includes the entire 64 bits.
1770 if (VRI.RLAmt || (VRI.Repl32 && !isUInt<32>(Mask)))
1771 VRot = SelectRotMask64(VRI.V, dl, VRI.RLAmt, VRI.Repl32,
1772 VRI.Repl32 ? 31 : 0, VRI.Repl32 ? 30 : 63);
1777 if (Use32BitInsts) {
1778 assert((ANDIMask != 0 || ANDISMask != 0) &&
1779 "No set bits in mask when using 32-bit ands for 64-bit value");
1781 SDValue ANDIVal, ANDISVal;
1783 ANDIVal = SDValue(CurDAG->getMachineNode(PPC::ANDIo8, dl, MVT::i64,
1784 VRot, getI32Imm(ANDIMask, dl)), 0);
1786 ANDISVal = SDValue(CurDAG->getMachineNode(PPC::ANDISo8, dl, MVT::i64,
1787 VRot, getI32Imm(ANDISMask, dl)), 0);
1790 TotalVal = ANDISVal;
1794 TotalVal = SDValue(CurDAG->getMachineNode(PPC::OR8, dl, MVT::i64,
1795 ANDIVal, ANDISVal), 0);
1797 TotalVal = SDValue(getInt64(CurDAG, dl, Mask), 0);
1799 SDValue(CurDAG->getMachineNode(PPC::AND8, dl, MVT::i64,
1800 VRot, TotalVal), 0);
1806 Res = SDValue(CurDAG->getMachineNode(PPC::OR8, dl, MVT::i64,
1809 // Now, remove all groups with this underlying value and rotation
1811 eraseMatchingBitGroups(MatchingBG);
1815 // Instruction selection for the 64-bit case.
1816 SDNode *Select64(SDNode *N, bool LateMask, unsigned *InstCnt) {
1820 if (InstCnt) *InstCnt = 0;
1822 // Take care of cases that should use andi/andis first.
1823 SelectAndParts64(dl, Res, InstCnt);
1825 // If we've not yet selected a 'starting' instruction, and we have no zeros
1826 // to fill in, select the (Value, RLAmt) with the highest priority (largest
1827 // number of groups), and start with this rotated value.
1828 if ((!HasZeros || LateMask) && !Res) {
1829 // If we have both Repl32 groups and non-Repl32 groups, the non-Repl32
1830 // groups will come first, and so the VRI representing the largest number
1831 // of groups might not be first (it might be the first Repl32 groups).
1832 unsigned MaxGroupsIdx = 0;
1833 if (!ValueRotsVec[0].Repl32) {
1834 for (unsigned i = 0, ie = ValueRotsVec.size(); i < ie; ++i)
1835 if (ValueRotsVec[i].Repl32) {
1836 if (ValueRotsVec[i].NumGroups > ValueRotsVec[0].NumGroups)
1842 ValueRotInfo &VRI = ValueRotsVec[MaxGroupsIdx];
1843 bool NeedsRotate = false;
1846 } else if (VRI.Repl32) {
1847 for (auto &BG : BitGroups) {
1848 if (BG.V != VRI.V || BG.RLAmt != VRI.RLAmt ||
1849 BG.Repl32 != VRI.Repl32)
1852 // We don't need a rotate if the bit group is confined to the lower
1854 if (BG.StartIdx < 32 && BG.EndIdx < 32 && BG.StartIdx < BG.EndIdx)
1863 Res = SelectRotMask64(VRI.V, dl, VRI.RLAmt, VRI.Repl32,
1864 VRI.Repl32 ? 31 : 0, VRI.Repl32 ? 30 : 63,
1869 // Now, remove all groups with this underlying value and rotation factor.
1871 eraseMatchingBitGroups([VRI](const BitGroup &BG) {
1872 return BG.V == VRI.V && BG.RLAmt == VRI.RLAmt &&
1873 BG.Repl32 == VRI.Repl32;
1877 // Because 64-bit rotates are more flexible than inserts, we might have a
1878 // preference regarding which one we do first (to save one instruction).
1880 for (auto I = BitGroups.begin(), IE = BitGroups.end(); I != IE; ++I) {
1881 if (SelectRotMask64Count(I->RLAmt, I->Repl32, I->StartIdx, I->EndIdx,
1883 SelectRotMask64Count(I->RLAmt, I->Repl32, I->StartIdx, I->EndIdx,
1885 if (I != BitGroups.begin()) {
1888 BitGroups.insert(BitGroups.begin(), BG);
1895 // Insert the other groups (one at a time).
1896 for (auto &BG : BitGroups) {
1898 Res = SelectRotMask64(BG.V, dl, BG.RLAmt, BG.Repl32, BG.StartIdx,
1899 BG.EndIdx, InstCnt);
1901 Res = SelectRotMaskIns64(Res, BG.V, dl, BG.RLAmt, BG.Repl32,
1902 BG.StartIdx, BG.EndIdx, InstCnt);
1906 uint64_t Mask = getZerosMask();
1908 // We can use the 32-bit andi/andis technique if the mask does not
1909 // require any higher-order bits. This can save an instruction compared
1910 // to always using the general 64-bit technique.
1911 bool Use32BitInsts = isUInt<32>(Mask);
1912 // Compute the masks for andi/andis that would be necessary.
1913 unsigned ANDIMask = (Mask & UINT16_MAX),
1914 ANDISMask = (Mask >> 16) & UINT16_MAX;
1916 if (Use32BitInsts) {
1917 assert((ANDIMask != 0 || ANDISMask != 0) &&
1918 "No set bits in mask when using 32-bit ands for 64-bit value");
1920 if (InstCnt) *InstCnt += (unsigned) (ANDIMask != 0) +
1921 (unsigned) (ANDISMask != 0) +
1922 (unsigned) (ANDIMask != 0 && ANDISMask != 0);
1924 SDValue ANDIVal, ANDISVal;
1926 ANDIVal = SDValue(CurDAG->getMachineNode(PPC::ANDIo8, dl, MVT::i64,
1927 Res, getI32Imm(ANDIMask, dl)), 0);
1929 ANDISVal = SDValue(CurDAG->getMachineNode(PPC::ANDISo8, dl, MVT::i64,
1930 Res, getI32Imm(ANDISMask, dl)), 0);
1937 Res = SDValue(CurDAG->getMachineNode(PPC::OR8, dl, MVT::i64,
1938 ANDIVal, ANDISVal), 0);
1940 if (InstCnt) *InstCnt += getInt64Count(Mask) + /* and */ 1;
1942 SDValue MaskVal = SDValue(getInt64(CurDAG, dl, Mask), 0);
1944 SDValue(CurDAG->getMachineNode(PPC::AND8, dl, MVT::i64,
1949 return Res.getNode();
1952 SDNode *Select(SDNode *N, bool LateMask, unsigned *InstCnt = nullptr) {
1953 // Fill in BitGroups.
1954 collectBitGroups(LateMask);
1955 if (BitGroups.empty())
1958 // For 64-bit values, figure out when we can use 32-bit instructions.
1959 if (Bits.size() == 64)
1960 assignRepl32BitGroups();
1962 // Fill in ValueRotsVec.
1963 collectValueRotInfo();
1965 if (Bits.size() == 32) {
1966 return Select32(N, LateMask, InstCnt);
1968 assert(Bits.size() == 64 && "Not 64 bits here?");
1969 return Select64(N, LateMask, InstCnt);
1975 void eraseMatchingBitGroups(function_ref<bool(const BitGroup &)> F) {
1976 BitGroups.erase(remove_if(BitGroups, F), BitGroups.end());
1979 SmallVector<ValueBit, 64> Bits;
1982 SmallVector<unsigned, 64> RLAmt;
1984 SmallVector<BitGroup, 16> BitGroups;
1986 DenseMap<std::pair<SDValue, unsigned>, ValueRotInfo> ValueRots;
1987 SmallVector<ValueRotInfo, 16> ValueRotsVec;
1989 SelectionDAG *CurDAG;
1992 BitPermutationSelector(SelectionDAG *DAG)
1995 // Here we try to match complex bit permutations into a set of
1996 // rotate-and-shift/shift/and/or instructions, using a set of heuristics
1997 // known to produce optimial code for common cases (like i32 byte swapping).
1998 SDNode *Select(SDNode *N) {
2001 getValueBits(SDValue(N, 0), N->getValueType(0).getSizeInBits());
2004 Bits = std::move(*Result.second);
2006 DEBUG(dbgs() << "Considering bit-permutation-based instruction"
2007 " selection for: ");
2008 DEBUG(N->dump(CurDAG));
2010 // Fill it RLAmt and set HasZeros.
2011 computeRotationAmounts();
2014 return Select(N, false);
2016 // We currently have two techniques for handling results with zeros: early
2017 // masking (the default) and late masking. Late masking is sometimes more
2018 // efficient, but because the structure of the bit groups is different, it
2019 // is hard to tell without generating both and comparing the results. With
2020 // late masking, we ignore zeros in the resulting value when inserting each
2021 // set of bit groups, and then mask in the zeros at the end. With early
2022 // masking, we only insert the non-zero parts of the result at every step.
2024 unsigned InstCnt, InstCntLateMask;
2025 DEBUG(dbgs() << "\tEarly masking:\n");
2026 SDNode *RN = Select(N, false, &InstCnt);
2027 DEBUG(dbgs() << "\t\tisel would use " << InstCnt << " instructions\n");
2029 DEBUG(dbgs() << "\tLate masking:\n");
2030 SDNode *RNLM = Select(N, true, &InstCntLateMask);
2031 DEBUG(dbgs() << "\t\tisel would use " << InstCntLateMask <<
2034 if (InstCnt <= InstCntLateMask) {
2035 DEBUG(dbgs() << "\tUsing early-masking for isel\n");
2039 DEBUG(dbgs() << "\tUsing late-masking for isel\n");
2044 } // end anonymous namespace
2046 bool PPCDAGToDAGISel::tryBitPermutation(SDNode *N) {
2047 if (N->getValueType(0) != MVT::i32 &&
2048 N->getValueType(0) != MVT::i64)
2051 if (!UseBitPermRewriter)
2054 switch (N->getOpcode()) {
2061 BitPermutationSelector BPS(CurDAG);
2062 if (SDNode *New = BPS.Select(N)) {
2063 ReplaceNode(N, New);
2073 /// SelectCC - Select a comparison of the specified values with the specified
2074 /// condition code, returning the CR# of the expression.
2075 SDValue PPCDAGToDAGISel::SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC,
2077 // Always select the LHS.
2080 if (LHS.getValueType() == MVT::i32) {
2082 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
2083 if (isInt32Immediate(RHS, Imm)) {
2084 // SETEQ/SETNE comparison with 16-bit immediate, fold it.
2085 if (isUInt<16>(Imm))
2086 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, LHS,
2087 getI32Imm(Imm & 0xFFFF, dl)),
2089 // If this is a 16-bit signed immediate, fold it.
2090 if (isInt<16>((int)Imm))
2091 return SDValue(CurDAG->getMachineNode(PPC::CMPWI, dl, MVT::i32, LHS,
2092 getI32Imm(Imm & 0xFFFF, dl)),
2095 // For non-equality comparisons, the default code would materialize the
2096 // constant, then compare against it, like this:
2098 // ori r2, r2, 22136
2100 // Since we are just comparing for equality, we can emit this instead:
2101 // xoris r0,r3,0x1234
2102 // cmplwi cr0,r0,0x5678
2104 SDValue Xor(CurDAG->getMachineNode(PPC::XORIS, dl, MVT::i32, LHS,
2105 getI32Imm(Imm >> 16, dl)), 0);
2106 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, Xor,
2107 getI32Imm(Imm & 0xFFFF, dl)), 0);
2110 } else if (ISD::isUnsignedIntSetCC(CC)) {
2111 if (isInt32Immediate(RHS, Imm) && isUInt<16>(Imm))
2112 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, LHS,
2113 getI32Imm(Imm & 0xFFFF, dl)), 0);
2117 if (isIntS16Immediate(RHS, SImm))
2118 return SDValue(CurDAG->getMachineNode(PPC::CMPWI, dl, MVT::i32, LHS,
2119 getI32Imm((int)SImm & 0xFFFF,
2124 } else if (LHS.getValueType() == MVT::i64) {
2126 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
2127 if (isInt64Immediate(RHS.getNode(), Imm)) {
2128 // SETEQ/SETNE comparison with 16-bit immediate, fold it.
2129 if (isUInt<16>(Imm))
2130 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, LHS,
2131 getI32Imm(Imm & 0xFFFF, dl)),
2133 // If this is a 16-bit signed immediate, fold it.
2135 return SDValue(CurDAG->getMachineNode(PPC::CMPDI, dl, MVT::i64, LHS,
2136 getI32Imm(Imm & 0xFFFF, dl)),
2139 // For non-equality comparisons, the default code would materialize the
2140 // constant, then compare against it, like this:
2142 // ori r2, r2, 22136
2144 // Since we are just comparing for equality, we can emit this instead:
2145 // xoris r0,r3,0x1234
2146 // cmpldi cr0,r0,0x5678
2148 if (isUInt<32>(Imm)) {
2149 SDValue Xor(CurDAG->getMachineNode(PPC::XORIS8, dl, MVT::i64, LHS,
2150 getI64Imm(Imm >> 16, dl)), 0);
2151 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, Xor,
2152 getI64Imm(Imm & 0xFFFF, dl)),
2157 } else if (ISD::isUnsignedIntSetCC(CC)) {
2158 if (isInt64Immediate(RHS.getNode(), Imm) && isUInt<16>(Imm))
2159 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, LHS,
2160 getI64Imm(Imm & 0xFFFF, dl)), 0);
2164 if (isIntS16Immediate(RHS, SImm))
2165 return SDValue(CurDAG->getMachineNode(PPC::CMPDI, dl, MVT::i64, LHS,
2166 getI64Imm(SImm & 0xFFFF, dl)),
2170 } else if (LHS.getValueType() == MVT::f32) {
2173 assert(LHS.getValueType() == MVT::f64 && "Unknown vt!");
2174 Opc = PPCSubTarget->hasVSX() ? PPC::XSCMPUDP : PPC::FCMPUD;
2176 return SDValue(CurDAG->getMachineNode(Opc, dl, MVT::i32, LHS, RHS), 0);
2179 static PPC::Predicate getPredicateForSetCC(ISD::CondCode CC) {
2185 llvm_unreachable("Should be lowered by legalize!");
2186 default: llvm_unreachable("Unknown condition!");
2188 case ISD::SETEQ: return PPC::PRED_EQ;
2190 case ISD::SETNE: return PPC::PRED_NE;
2192 case ISD::SETLT: return PPC::PRED_LT;
2194 case ISD::SETLE: return PPC::PRED_LE;
2196 case ISD::SETGT: return PPC::PRED_GT;
2198 case ISD::SETGE: return PPC::PRED_GE;
2199 case ISD::SETO: return PPC::PRED_NU;
2200 case ISD::SETUO: return PPC::PRED_UN;
2201 // These two are invalid for floating point. Assume we have int.
2202 case ISD::SETULT: return PPC::PRED_LT;
2203 case ISD::SETUGT: return PPC::PRED_GT;
2207 /// getCRIdxForSetCC - Return the index of the condition register field
2208 /// associated with the SetCC condition, and whether or not the field is
2209 /// treated as inverted. That is, lt = 0; ge = 0 inverted.
2210 static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool &Invert) {
2213 default: llvm_unreachable("Unknown condition!");
2215 case ISD::SETLT: return 0; // Bit #0 = SETOLT
2217 case ISD::SETGT: return 1; // Bit #1 = SETOGT
2219 case ISD::SETEQ: return 2; // Bit #2 = SETOEQ
2220 case ISD::SETUO: return 3; // Bit #3 = SETUO
2222 case ISD::SETGE: Invert = true; return 0; // !Bit #0 = SETUGE
2224 case ISD::SETLE: Invert = true; return 1; // !Bit #1 = SETULE
2226 case ISD::SETNE: Invert = true; return 2; // !Bit #2 = SETUNE
2227 case ISD::SETO: Invert = true; return 3; // !Bit #3 = SETO
2232 llvm_unreachable("Invalid branch code: should be expanded by legalize");
2233 // These are invalid for floating point. Assume integer.
2234 case ISD::SETULT: return 0;
2235 case ISD::SETUGT: return 1;
2239 // getVCmpInst: return the vector compare instruction for the specified
2240 // vector type and condition code. Since this is for altivec specific code,
2241 // only support the altivec types (v16i8, v8i16, v4i32, v2i64, and v4f32).
2242 static unsigned int getVCmpInst(MVT VecVT, ISD::CondCode CC,
2243 bool HasVSX, bool &Swap, bool &Negate) {
2247 if (VecVT.isFloatingPoint()) {
2248 /* Handle some cases by swapping input operands. */
2250 case ISD::SETLE: CC = ISD::SETGE; Swap = true; break;
2251 case ISD::SETLT: CC = ISD::SETGT; Swap = true; break;
2252 case ISD::SETOLE: CC = ISD::SETOGE; Swap = true; break;
2253 case ISD::SETOLT: CC = ISD::SETOGT; Swap = true; break;
2254 case ISD::SETUGE: CC = ISD::SETULE; Swap = true; break;
2255 case ISD::SETUGT: CC = ISD::SETULT; Swap = true; break;
2258 /* Handle some cases by negating the result. */
2260 case ISD::SETNE: CC = ISD::SETEQ; Negate = true; break;
2261 case ISD::SETUNE: CC = ISD::SETOEQ; Negate = true; break;
2262 case ISD::SETULE: CC = ISD::SETOGT; Negate = true; break;
2263 case ISD::SETULT: CC = ISD::SETOGE; Negate = true; break;
2266 /* We have instructions implementing the remaining cases. */
2270 if (VecVT == MVT::v4f32)
2271 return HasVSX ? PPC::XVCMPEQSP : PPC::VCMPEQFP;
2272 else if (VecVT == MVT::v2f64)
2273 return PPC::XVCMPEQDP;
2277 if (VecVT == MVT::v4f32)
2278 return HasVSX ? PPC::XVCMPGTSP : PPC::VCMPGTFP;
2279 else if (VecVT == MVT::v2f64)
2280 return PPC::XVCMPGTDP;
2284 if (VecVT == MVT::v4f32)
2285 return HasVSX ? PPC::XVCMPGESP : PPC::VCMPGEFP;
2286 else if (VecVT == MVT::v2f64)
2287 return PPC::XVCMPGEDP;
2292 llvm_unreachable("Invalid floating-point vector compare condition");
2294 /* Handle some cases by swapping input operands. */
2296 case ISD::SETGE: CC = ISD::SETLE; Swap = true; break;
2297 case ISD::SETLT: CC = ISD::SETGT; Swap = true; break;
2298 case ISD::SETUGE: CC = ISD::SETULE; Swap = true; break;
2299 case ISD::SETULT: CC = ISD::SETUGT; Swap = true; break;
2302 /* Handle some cases by negating the result. */
2304 case ISD::SETNE: CC = ISD::SETEQ; Negate = true; break;
2305 case ISD::SETUNE: CC = ISD::SETUEQ; Negate = true; break;
2306 case ISD::SETLE: CC = ISD::SETGT; Negate = true; break;
2307 case ISD::SETULE: CC = ISD::SETUGT; Negate = true; break;
2310 /* We have instructions implementing the remaining cases. */
2314 if (VecVT == MVT::v16i8)
2315 return PPC::VCMPEQUB;
2316 else if (VecVT == MVT::v8i16)
2317 return PPC::VCMPEQUH;
2318 else if (VecVT == MVT::v4i32)
2319 return PPC::VCMPEQUW;
2320 else if (VecVT == MVT::v2i64)
2321 return PPC::VCMPEQUD;
2324 if (VecVT == MVT::v16i8)
2325 return PPC::VCMPGTSB;
2326 else if (VecVT == MVT::v8i16)
2327 return PPC::VCMPGTSH;
2328 else if (VecVT == MVT::v4i32)
2329 return PPC::VCMPGTSW;
2330 else if (VecVT == MVT::v2i64)
2331 return PPC::VCMPGTSD;
2334 if (VecVT == MVT::v16i8)
2335 return PPC::VCMPGTUB;
2336 else if (VecVT == MVT::v8i16)
2337 return PPC::VCMPGTUH;
2338 else if (VecVT == MVT::v4i32)
2339 return PPC::VCMPGTUW;
2340 else if (VecVT == MVT::v2i64)
2341 return PPC::VCMPGTUD;
2346 llvm_unreachable("Invalid integer vector compare condition");
2350 bool PPCDAGToDAGISel::trySETCC(SDNode *N) {
2353 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
2355 CurDAG->getTargetLoweringInfo().getPointerTy(CurDAG->getDataLayout());
2356 bool isPPC64 = (PtrVT == MVT::i64);
2358 if (!PPCSubTarget->useCRBits() &&
2359 isInt32Immediate(N->getOperand(1), Imm)) {
2360 // We can codegen setcc op, imm very efficiently compared to a brcond.
2361 // Check for those cases here.
2364 SDValue Op = N->getOperand(0);
2368 Op = SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, Op), 0);
2369 SDValue Ops[] = { Op, getI32Imm(27, dl), getI32Imm(5, dl),
2370 getI32Imm(31, dl) };
2371 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
2377 SDValue(CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
2378 Op, getI32Imm(~0U, dl)), 0);
2379 CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op, AD.getValue(1));
2383 SDValue Ops[] = { Op, getI32Imm(1, dl), getI32Imm(31, dl),
2384 getI32Imm(31, dl) };
2385 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
2390 SDValue(CurDAG->getMachineNode(PPC::NEG, dl, MVT::i32, Op), 0);
2391 T = SDValue(CurDAG->getMachineNode(PPC::ANDC, dl, MVT::i32, T, Op), 0);
2392 SDValue Ops[] = { T, getI32Imm(1, dl), getI32Imm(31, dl),
2393 getI32Imm(31, dl) };
2394 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
2398 } else if (Imm == ~0U) { // setcc op, -1
2399 SDValue Op = N->getOperand(0);
2404 Op = SDValue(CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
2405 Op, getI32Imm(1, dl)), 0);
2406 CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
2407 SDValue(CurDAG->getMachineNode(PPC::LI, dl,
2410 0), Op.getValue(1));
2414 Op = SDValue(CurDAG->getMachineNode(PPC::NOR, dl, MVT::i32, Op, Op), 0);
2415 SDNode *AD = CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
2416 Op, getI32Imm(~0U, dl));
2417 CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDValue(AD, 0), Op,
2422 SDValue AD = SDValue(CurDAG->getMachineNode(PPC::ADDI, dl, MVT::i32, Op,
2423 getI32Imm(1, dl)), 0);
2424 SDValue AN = SDValue(CurDAG->getMachineNode(PPC::AND, dl, MVT::i32, AD,
2426 SDValue Ops[] = { AN, getI32Imm(1, dl), getI32Imm(31, dl),
2427 getI32Imm(31, dl) };
2428 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
2432 SDValue Ops[] = { Op, getI32Imm(1, dl), getI32Imm(31, dl),
2433 getI32Imm(31, dl) };
2434 Op = SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops), 0);
2435 CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op, getI32Imm(1, dl));
2442 SDValue LHS = N->getOperand(0);
2443 SDValue RHS = N->getOperand(1);
2445 // Altivec Vector compare instructions do not set any CR register by default and
2446 // vector compare operations return the same type as the operands.
2447 if (LHS.getValueType().isVector()) {
2448 if (PPCSubTarget->hasQPX())
2451 EVT VecVT = LHS.getValueType();
2453 unsigned int VCmpInst = getVCmpInst(VecVT.getSimpleVT(), CC,
2454 PPCSubTarget->hasVSX(), Swap, Negate);
2456 std::swap(LHS, RHS);
2458 EVT ResVT = VecVT.changeVectorElementTypeToInteger();
2460 SDValue VCmp(CurDAG->getMachineNode(VCmpInst, dl, ResVT, LHS, RHS), 0);
2461 CurDAG->SelectNodeTo(N, PPCSubTarget->hasVSX() ? PPC::XXLNOR : PPC::VNOR,
2466 CurDAG->SelectNodeTo(N, VCmpInst, ResVT, LHS, RHS);
2470 if (PPCSubTarget->useCRBits())
2474 unsigned Idx = getCRIdxForSetCC(CC, Inv);
2475 SDValue CCReg = SelectCC(LHS, RHS, CC, dl);
2478 // Force the ccreg into CR7.
2479 SDValue CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32);
2481 SDValue InFlag(nullptr, 0); // Null incoming flag value.
2482 CCReg = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, CR7Reg, CCReg,
2483 InFlag).getValue(1);
2485 IntCR = SDValue(CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32, CR7Reg,
2488 SDValue Ops[] = { IntCR, getI32Imm((32 - (3 - Idx)) & 31, dl),
2489 getI32Imm(31, dl), getI32Imm(31, dl) };
2491 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
2495 // Get the specified bit.
2497 SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops), 0);
2498 CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1, dl));
2502 // Is this opcode a bitwise logical operation?
2503 static bool isLogicOp(unsigned Opc) {
2504 return Opc == ISD::AND || Opc == ISD::OR || Opc == ISD::XOR;
2507 /// If this node is a sign/zero extension of an integer comparison,
2508 /// it can usually be computed in GPR's rather than using comparison
2509 /// instructions and ISEL. We only do this on 64-bit targets for now
2510 /// as the code is specialized for 64-bit (it uses 64-bit instructions
2511 /// and assumes 64-bit registers).
2512 bool PPCDAGToDAGISel::tryEXTEND(SDNode *N) {
2513 if (TM.getOptLevel() == CodeGenOpt::None || !TM.isPPC64())
2515 assert((N->getOpcode() == ISD::ZERO_EXTEND ||
2516 N->getOpcode() == ISD::SIGN_EXTEND) &&
2517 "Expecting a zero/sign extend node!");
2520 // If we are zero-extending the result of a logical operation on i1
2521 // values, we can keep the values in GPRs.
2522 if (isLogicOp(N->getOperand(0).getOpcode()) &&
2523 N->getOperand(0).getValueType() == MVT::i1 &&
2524 N->getOpcode() == ISD::ZERO_EXTEND)
2525 WideRes = computeLogicOpInGPR(N->getOperand(0));
2526 else if (N->getOperand(0).getOpcode() != ISD::SETCC)
2530 getSETCCInGPR(N->getOperand(0),
2531 N->getOpcode() == ISD::SIGN_EXTEND ?
2532 SetccInGPROpts::SExtOrig : SetccInGPROpts::ZExtOrig);
2538 bool Inputs32Bit = N->getOperand(0).getOperand(0).getValueType() == MVT::i32;
2539 bool Output32Bit = N->getValueType(0) == MVT::i32;
2541 NumSextSetcc += N->getOpcode() == ISD::SIGN_EXTEND ? 1 : 0;
2542 NumZextSetcc += N->getOpcode() == ISD::SIGN_EXTEND ? 0 : 1;
2544 SDValue ConvOp = WideRes;
2545 if (Inputs32Bit != Output32Bit)
2546 ConvOp = addExtOrTrunc(WideRes, Inputs32Bit ? ExtOrTruncConversion::Ext :
2547 ExtOrTruncConversion::Trunc);
2548 ReplaceNode(N, ConvOp.getNode());
2553 // Lower a logical operation on i1 values into a GPR sequence if possible.
2554 // The result can be kept in a GPR if requested.
2555 // Three types of inputs can be handled:
2558 // - Logical operation (AND/OR/XOR)
2559 // There is also a special case that is handled (namely a complement operation
2560 // achieved with xor %a, -1).
2561 SDValue PPCDAGToDAGISel::computeLogicOpInGPR(SDValue LogicOp) {
2562 assert(isLogicOp(LogicOp.getOpcode()) &&
2563 "Can only handle logic operations here.");
2564 assert(LogicOp.getValueType() == MVT::i1 &&
2565 "Can only handle logic operations on i1 values here.");
2569 // Special case: xor %a, -1
2570 bool IsBitwiseNegation = isBitwiseNot(LogicOp);
2572 // Produces a GPR sequence for each operand of the binary logic operation.
2573 // For SETCC, it produces the respective comparison, for TRUNCATE it truncates
2574 // the value in a GPR and for logic operations, it will recursively produce
2575 // a GPR sequence for the operation.
2576 auto getLogicOperand = [&] (SDValue Operand) -> SDValue {
2577 unsigned OperandOpcode = Operand.getOpcode();
2578 if (OperandOpcode == ISD::SETCC)
2579 return getSETCCInGPR(Operand, SetccInGPROpts::ZExtOrig);
2580 else if (OperandOpcode == ISD::TRUNCATE) {
2581 SDValue InputOp = Operand.getOperand(0);
2582 EVT InVT = InputOp.getValueType();
2584 SDValue(CurDAG->getMachineNode(InVT == MVT::i32 ? PPC::RLDICL_32 :
2585 PPC::RLDICL, dl, InVT, InputOp,
2586 getI64Imm(0, dl), getI64Imm(63, dl)), 0);
2587 } else if (isLogicOp(OperandOpcode))
2588 return computeLogicOpInGPR(Operand);
2591 LHS = getLogicOperand(LogicOp.getOperand(0));
2592 RHS = getLogicOperand(LogicOp.getOperand(1));
2594 // If a GPR sequence can't be produced for the LHS we can't proceed.
2595 // Not producing a GPR sequence for the RHS is only a problem if this isn't
2596 // a bitwise negation operation.
2597 if (!LHS || (!RHS && !IsBitwiseNegation))
2600 NumLogicOpsOnComparison++;
2602 // We will use the inputs as 64-bit values.
2603 if (LHS.getValueType() == MVT::i32)
2604 LHS = addExtOrTrunc(LHS, ExtOrTruncConversion::Ext);
2605 if (!IsBitwiseNegation && RHS.getValueType() == MVT::i32)
2606 RHS = addExtOrTrunc(RHS, ExtOrTruncConversion::Ext);
2609 switch (LogicOp.getOpcode()) {
2610 default: llvm_unreachable("Unknown logic operation.");
2611 case ISD::AND: NewOpc = PPC::AND8; break;
2612 case ISD::OR: NewOpc = PPC::OR8; break;
2613 case ISD::XOR: NewOpc = PPC::XOR8; break;
2616 if (IsBitwiseNegation) {
2617 RHS = getI64Imm(1, dl);
2618 NewOpc = PPC::XORI8;
2621 return SDValue(CurDAG->getMachineNode(NewOpc, dl, MVT::i64, LHS, RHS), 0);
2625 /// Try performing logical operations on results of comparisons in GPRs.
2626 /// It is typically preferred from a performance perspective over performing
2627 /// the operations on individual bits in the CR. We only do this on 64-bit
2628 /// targets for now as the code is specialized for 64-bit (it uses 64-bit
2629 /// instructions and assumes 64-bit registers).
2630 bool PPCDAGToDAGISel::tryLogicOpOfCompares(SDNode *N) {
2631 if (TM.getOptLevel() == CodeGenOpt::None || !TM.isPPC64())
2633 if (N->getValueType(0) != MVT::i1)
2635 assert(isLogicOp(N->getOpcode()) &&
2636 "Expected a logic operation on setcc results.");
2637 SDValue LoweredLogical = computeLogicOpInGPR(SDValue(N, 0));
2638 if (!LoweredLogical)
2642 bool IsBitwiseNegate = LoweredLogical.getMachineOpcode() == PPC::XORI8;
2643 unsigned SubRegToExtract = IsBitwiseNegate ? PPC::sub_eq : PPC::sub_gt;
2644 SDValue CR0Reg = CurDAG->getRegister(PPC::CR0, MVT::i32);
2645 SDValue LHS = LoweredLogical.getOperand(0);
2646 SDValue RHS = LoweredLogical.getOperand(1);
2648 SDValue OpToConvToRecForm;
2650 // Look through any 32-bit to 64-bit implicit extend nodes to find the opcode
2651 // that is input to the XORI.
2652 if (IsBitwiseNegate &&
2653 LoweredLogical.getOperand(0).getMachineOpcode() == PPC::INSERT_SUBREG)
2654 OpToConvToRecForm = LoweredLogical.getOperand(0).getOperand(1);
2655 else if (IsBitwiseNegate)
2656 // If the input to the XORI isn't an extension, that's what we're after.
2657 OpToConvToRecForm = LoweredLogical.getOperand(0);
2659 // If this is not an XORI, it is a reg-reg logical op and we can convert it
2661 OpToConvToRecForm = LoweredLogical;
2663 // Get the record-form version of the node we're looking to use to get the
2665 uint16_t NonRecOpc = OpToConvToRecForm.getMachineOpcode();
2666 int NewOpc = PPCInstrInfo::getRecordFormOpcode(NonRecOpc);
2668 // Convert the right node to record-form. This is either the logical we're
2669 // looking at or it is the input node to the negation (if we're looking at
2670 // a bitwise negation).
2671 if (NewOpc != -1 && IsBitwiseNegate) {
2672 // The input to the XORI has a record-form. Use it.
2673 assert(LoweredLogical.getConstantOperandVal(1) == 1 &&
2674 "Expected a PPC::XORI8 only for bitwise negation.");
2675 // Emit the record-form instruction.
2676 std::vector<SDValue> Ops;
2677 for (int i = 0, e = OpToConvToRecForm.getNumOperands(); i < e; i++)
2678 Ops.push_back(OpToConvToRecForm.getOperand(i));
2681 SDValue(CurDAG->getMachineNode(NewOpc, dl,
2682 OpToConvToRecForm.getValueType(),
2683 MVT::Glue, Ops), 0);
2685 assert((NewOpc != -1 || !IsBitwiseNegate) &&
2686 "No record form available for AND8/OR8/XOR8?");
2688 SDValue(CurDAG->getMachineNode(NewOpc == -1 ? PPC::ANDIo8 : NewOpc, dl,
2689 MVT::i64, MVT::Glue, LHS, RHS), 0);
2692 // Select this node to a single bit from CR0 set by the record-form node
2693 // just created. For bitwise negation, use the EQ bit which is the equivalent
2694 // of negating the result (i.e. it is a bit set when the result of the
2695 // operation is zero).
2697 CurDAG->getTargetConstant(SubRegToExtract, dl, MVT::i32);
2699 SDValue(CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG, dl,
2700 MVT::i1, CR0Reg, SRIdxVal,
2701 WideOp.getValue(1)), 0);
2702 ReplaceNode(N, CRBit.getNode());
2706 /// If the value isn't guaranteed to be sign-extended to 64-bits, extend it.
2707 /// Useful when emitting comparison code for 32-bit values without using
2708 /// the compare instruction (which only considers the lower 32-bits).
2709 SDValue PPCDAGToDAGISel::signExtendInputIfNeeded(SDValue Input) {
2710 assert(Input.getValueType() == MVT::i32 &&
2711 "Can only sign-extend 32-bit values here.");
2712 unsigned Opc = Input.getOpcode();
2714 // The value was sign extended and then truncated to 32-bits. No need to
2715 // sign extend it again.
2716 if (Opc == ISD::TRUNCATE &&
2717 (Input.getOperand(0).getOpcode() == ISD::AssertSext ||
2718 Input.getOperand(0).getOpcode() == ISD::SIGN_EXTEND))
2721 LoadSDNode *InputLoad = dyn_cast<LoadSDNode>(Input);
2722 // The input is a sign-extending load. No reason to sign-extend.
2723 if (InputLoad && InputLoad->getExtensionType() == ISD::SEXTLOAD)
2726 ConstantSDNode *InputConst = dyn_cast<ConstantSDNode>(Input);
2727 // We don't sign-extend constants and already sign-extended values.
2728 if (InputConst || Opc == ISD::AssertSext || Opc == ISD::SIGN_EXTEND_INREG ||
2729 Opc == ISD::SIGN_EXTEND)
2733 SignExtensionsAdded++;
2734 return SDValue(CurDAG->getMachineNode(PPC::EXTSW_32, dl, MVT::i32, Input), 0);
2737 /// If the value isn't guaranteed to be zero-extended to 64-bits, extend it.
2738 /// Useful when emitting comparison code for 32-bit values without using
2739 /// the compare instruction (which only considers the lower 32-bits).
2740 SDValue PPCDAGToDAGISel::zeroExtendInputIfNeeded(SDValue Input) {
2741 assert(Input.getValueType() == MVT::i32 &&
2742 "Can only zero-extend 32-bit values here.");
2743 LoadSDNode *InputLoad = dyn_cast<LoadSDNode>(Input);
2744 unsigned Opc = Input.getOpcode();
2746 // No need to zero-extend loaded values (unless they're loaded with
2747 // a sign-extending load).
2748 if (InputLoad && InputLoad->getExtensionType() != ISD::SEXTLOAD)
2751 ConstantSDNode *InputConst = dyn_cast<ConstantSDNode>(Input);
2752 bool InputZExtConst = InputConst && InputConst->getSExtValue() >= 0;
2753 // An ISD::TRUNCATE will be lowered to an EXTRACT_SUBREG so we have
2754 // to conservatively actually clear the high bits. We also don't need to
2755 // zero-extend constants or values that are already zero-extended.
2756 if (InputZExtConst || Opc == ISD::AssertZext || Opc == ISD::ZERO_EXTEND)
2760 ZeroExtensionsAdded++;
2761 return SDValue(CurDAG->getMachineNode(PPC::RLDICL_32, dl, MVT::i32, Input,
2762 getI64Imm(0, dl), getI64Imm(32, dl)),
2766 // Handle a 32-bit value in a 64-bit register and vice-versa. These are of
2767 // course not actual zero/sign extensions that will generate machine code,
2768 // they're just a way to reinterpret a 32 bit value in a register as a
2769 // 64 bit value and vice-versa.
2770 SDValue PPCDAGToDAGISel::addExtOrTrunc(SDValue NatWidthRes,
2771 ExtOrTruncConversion Conv) {
2772 SDLoc dl(NatWidthRes);
2774 // For reinterpreting 32-bit values as 64 bit values, we generate
2775 // INSERT_SUBREG IMPLICIT_DEF:i64, <input>, TargetConstant:i32<1>
2776 if (Conv == ExtOrTruncConversion::Ext) {
2777 SDValue ImDef(CurDAG->getMachineNode(PPC::IMPLICIT_DEF, dl, MVT::i64), 0);
2779 CurDAG->getTargetConstant(PPC::sub_32, dl, MVT::i32);
2780 return SDValue(CurDAG->getMachineNode(PPC::INSERT_SUBREG, dl, MVT::i64,
2781 ImDef, NatWidthRes, SubRegIdx), 0);
2784 assert(Conv == ExtOrTruncConversion::Trunc &&
2785 "Unknown convertion between 32 and 64 bit values.");
2786 // For reinterpreting 64-bit values as 32-bit values, we just need to
2787 // EXTRACT_SUBREG (i.e. extract the low word).
2789 CurDAG->getTargetConstant(PPC::sub_32, dl, MVT::i32);
2790 return SDValue(CurDAG->getMachineNode(PPC::EXTRACT_SUBREG, dl, MVT::i32,
2791 NatWidthRes, SubRegIdx), 0);
2794 /// Produces a zero-extended result of comparing two 32-bit values according to
2795 /// the passed condition code.
2796 SDValue PPCDAGToDAGISel::get32BitZExtCompare(SDValue LHS, SDValue RHS,
2798 int64_t RHSValue, SDLoc dl) {
2799 bool IsRHSZero = RHSValue == 0;
2801 default: return SDValue();
2803 // (zext (setcc %a, %b, seteq)) -> (lshr (cntlzw (xor %a, %b)), 5)
2804 // (zext (setcc %a, 0, seteq)) -> (lshr (cntlzw %a), 5)
2805 SDValue Xor = IsRHSZero ? LHS :
2806 SDValue(CurDAG->getMachineNode(PPC::XOR, dl, MVT::i32, LHS, RHS), 0);
2808 SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, Xor), 0);
2809 SDValue ShiftOps[] = { Clz, getI32Imm(27, dl), getI32Imm(5, dl),
2810 getI32Imm(31, dl) };
2811 return SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32,
2815 // (zext (setcc %a, %b, setne)) -> (xor (lshr (cntlzw (xor %a, %b)), 5), 1)
2816 // (zext (setcc %a, 0, setne)) -> (xor (lshr (cntlzw %a), 5), 1)
2817 SDValue Xor = IsRHSZero ? LHS :
2818 SDValue(CurDAG->getMachineNode(PPC::XOR, dl, MVT::i32, LHS, RHS), 0);
2820 SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, Xor), 0);
2821 SDValue ShiftOps[] = { Clz, getI32Imm(27, dl), getI32Imm(5, dl),
2822 getI32Imm(31, dl) };
2824 SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, ShiftOps), 0);
2825 return SDValue(CurDAG->getMachineNode(PPC::XORI, dl, MVT::i32, Shift,
2826 getI32Imm(1, dl)), 0);
2831 /// Produces a sign-extended result of comparing two 32-bit values according to
2832 /// the passed condition code.
2833 SDValue PPCDAGToDAGISel::get32BitSExtCompare(SDValue LHS, SDValue RHS,
2835 int64_t RHSValue, SDLoc dl) {
2836 bool IsRHSZero = RHSValue == 0;
2838 default: return SDValue();
2840 // (sext (setcc %a, %b, seteq)) ->
2841 // (ashr (shl (ctlz (xor %a, %b)), 58), 63)
2842 // (sext (setcc %a, 0, seteq)) ->
2843 // (ashr (shl (ctlz %a), 58), 63)
2844 SDValue CountInput = IsRHSZero ? LHS :
2845 SDValue(CurDAG->getMachineNode(PPC::XOR, dl, MVT::i32, LHS, RHS), 0);
2847 SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, CountInput), 0);
2848 SDValue SHLOps[] = { Cntlzw, getI32Imm(58, dl), getI32Imm(0, dl) };
2850 SDValue(CurDAG->getMachineNode(PPC::RLDICR_32, dl, MVT::i32, SHLOps), 0);
2851 return SDValue(CurDAG->getMachineNode(PPC::SRADI_32, dl, MVT::i32, Sldi,
2852 getI32Imm(63, dl)), 0);
2855 // Bitwise xor the operands, count leading zeros, shift right by 5 bits and
2856 // flip the bit, finally take 2's complement.
2857 // (sext (setcc %a, %b, setne)) ->
2858 // (neg (xor (lshr (ctlz (xor %a, %b)), 5), 1))
2859 // Same as above, but the first xor is not needed.
2860 // (sext (setcc %a, 0, setne)) ->
2861 // (neg (xor (lshr (ctlz %a), 5), 1))
2862 SDValue Xor = IsRHSZero ? LHS :
2863 SDValue(CurDAG->getMachineNode(PPC::XOR, dl, MVT::i32, LHS, RHS), 0);
2865 SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, Xor), 0);
2866 SDValue ShiftOps[] =
2867 { Clz, getI32Imm(27, dl), getI32Imm(5, dl), getI32Imm(31, dl) };
2869 SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, ShiftOps), 0);
2871 SDValue(CurDAG->getMachineNode(PPC::XORI, dl, MVT::i32, Shift,
2872 getI32Imm(1, dl)), 0);
2873 return SDValue(CurDAG->getMachineNode(PPC::NEG, dl, MVT::i32, Xori), 0);
2878 /// Produces a zero-extended result of comparing two 64-bit values according to
2879 /// the passed condition code.
2880 SDValue PPCDAGToDAGISel::get64BitZExtCompare(SDValue LHS, SDValue RHS,
2882 int64_t RHSValue, SDLoc dl) {
2883 bool IsRHSZero = RHSValue == 0;
2885 default: return SDValue();
2887 // (zext (setcc %a, %b, seteq)) -> (lshr (ctlz (xor %a, %b)), 6)
2888 // (zext (setcc %a, 0, seteq)) -> (lshr (ctlz %a), 6)
2889 SDValue Xor = IsRHSZero ? LHS :
2890 SDValue(CurDAG->getMachineNode(PPC::XOR8, dl, MVT::i64, LHS, RHS), 0);
2892 SDValue(CurDAG->getMachineNode(PPC::CNTLZD, dl, MVT::i64, Xor), 0);
2893 return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, Clz,
2894 getI64Imm(58, dl), getI64Imm(63, dl)),
2900 /// Produces a sign-extended result of comparing two 64-bit values according to
2901 /// the passed condition code.
2902 SDValue PPCDAGToDAGISel::get64BitSExtCompare(SDValue LHS, SDValue RHS,
2904 int64_t RHSValue, SDLoc dl) {
2905 bool IsRHSZero = RHSValue == 0;
2907 default: return SDValue();
2909 // {addc.reg, addc.CA} = (addcarry (xor %a, %b), -1)
2910 // (sext (setcc %a, %b, seteq)) -> (sube addc.reg, addc.reg, addc.CA)
2911 // {addcz.reg, addcz.CA} = (addcarry %a, -1)
2912 // (sext (setcc %a, 0, seteq)) -> (sube addcz.reg, addcz.reg, addcz.CA)
2913 SDValue AddInput = IsRHSZero ? LHS :
2914 SDValue(CurDAG->getMachineNode(PPC::XOR8, dl, MVT::i64, LHS, RHS), 0);
2916 SDValue(CurDAG->getMachineNode(PPC::ADDIC8, dl, MVT::i64, MVT::Glue,
2917 AddInput, getI32Imm(~0U, dl)), 0);
2918 return SDValue(CurDAG->getMachineNode(PPC::SUBFE8, dl, MVT::i64, Addic,
2919 Addic, Addic.getValue(1)), 0);
2924 /// Does this SDValue have any uses for which keeping the value in a GPR is
2925 /// appropriate. This is meant to be used on values that have type i1 since
2926 /// it is somewhat meaningless to ask if values of other types can be kept in
2928 static bool allUsesExtend(SDValue Compare, SelectionDAG *CurDAG) {
2929 assert(Compare.getOpcode() == ISD::SETCC &&
2930 "An ISD::SETCC node required here.");
2932 // For values that have a single use, the caller should obviously already have
2933 // checked if that use is an extending use. We check the other uses here.
2934 if (Compare.hasOneUse())
2936 // We want the value in a GPR if it is being extended, used for a select, or
2937 // used in logical operations.
2938 for (auto CompareUse : Compare.getNode()->uses())
2939 if (CompareUse->getOpcode() != ISD::SIGN_EXTEND &&
2940 CompareUse->getOpcode() != ISD::ZERO_EXTEND &&
2941 CompareUse->getOpcode() != ISD::SELECT &&
2942 !isLogicOp(CompareUse->getOpcode())) {
2943 OmittedForNonExtendUses++;
2949 /// Returns an equivalent of a SETCC node but with the result the same width as
2950 /// the inputs. This can nalso be used for SELECT_CC if either the true or false
2951 /// values is a power of two while the other is zero.
2952 SDValue PPCDAGToDAGISel::getSETCCInGPR(SDValue Compare,
2953 SetccInGPROpts ConvOpts) {
2954 assert((Compare.getOpcode() == ISD::SETCC ||
2955 Compare.getOpcode() == ISD::SELECT_CC) &&
2956 "An ISD::SETCC node required here.");
2958 // Don't convert this comparison to a GPR sequence because there are uses
2959 // of the i1 result (i.e. uses that require the result in the CR).
2960 if ((Compare.getOpcode() == ISD::SETCC) && !allUsesExtend(Compare, CurDAG))
2963 SDValue LHS = Compare.getOperand(0);
2964 SDValue RHS = Compare.getOperand(1);
2966 // The condition code is operand 2 for SETCC and operand 4 for SELECT_CC.
2967 int CCOpNum = Compare.getOpcode() == ISD::SELECT_CC ? 4 : 2;
2969 cast<CondCodeSDNode>(Compare.getOperand(CCOpNum))->get();
2970 EVT InputVT = LHS.getValueType();
2971 if (InputVT != MVT::i32 && InputVT != MVT::i64)
2974 if (ConvOpts == SetccInGPROpts::ZExtInvert ||
2975 ConvOpts == SetccInGPROpts::SExtInvert)
2976 CC = ISD::getSetCCInverse(CC, true);
2978 bool Inputs32Bit = InputVT == MVT::i32;
2979 if (ISD::isSignedIntSetCC(CC) && Inputs32Bit) {
2980 LHS = signExtendInputIfNeeded(LHS);
2981 RHS = signExtendInputIfNeeded(RHS);
2982 } else if (ISD::isUnsignedIntSetCC(CC) && Inputs32Bit) {
2983 LHS = zeroExtendInputIfNeeded(LHS);
2984 RHS = zeroExtendInputIfNeeded(RHS);
2988 ConstantSDNode *RHSConst = dyn_cast<ConstantSDNode>(RHS);
2989 int64_t RHSValue = RHSConst ? RHSConst->getSExtValue() : INT64_MAX;
2990 bool IsSext = ConvOpts == SetccInGPROpts::SExtOrig ||
2991 ConvOpts == SetccInGPROpts::SExtInvert;
2993 if (IsSext && Inputs32Bit)
2994 return get32BitSExtCompare(LHS, RHS, CC, RHSValue, dl);
2995 else if (Inputs32Bit)
2996 return get32BitZExtCompare(LHS, RHS, CC, RHSValue, dl);
2998 return get64BitSExtCompare(LHS, RHS, CC, RHSValue, dl);
2999 return get64BitZExtCompare(LHS, RHS, CC, RHSValue, dl);
3002 void PPCDAGToDAGISel::transferMemOperands(SDNode *N, SDNode *Result) {
3003 // Transfer memoperands.
3004 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
3005 MemOp[0] = cast<MemSDNode>(N)->getMemOperand();
3006 cast<MachineSDNode>(Result)->setMemRefs(MemOp, MemOp + 1);
3009 // Select - Convert the specified operand from a target-independent to a
3010 // target-specific node if it hasn't already been changed.
3011 void PPCDAGToDAGISel::Select(SDNode *N) {
3013 if (N->isMachineOpcode()) {
3015 return; // Already selected.
3018 // In case any misguided DAG-level optimizations form an ADD with a
3019 // TargetConstant operand, crash here instead of miscompiling (by selecting
3020 // an r+r add instead of some kind of r+i add).
3021 if (N->getOpcode() == ISD::ADD &&
3022 N->getOperand(1).getOpcode() == ISD::TargetConstant)
3023 llvm_unreachable("Invalid ADD with TargetConstant operand");
3025 // Try matching complex bit permutations before doing anything else.
3026 if (tryBitPermutation(N))
3029 switch (N->getOpcode()) {
3033 if (N->getValueType(0) == MVT::i64) {
3034 ReplaceNode(N, getInt64(CurDAG, N));
3039 case ISD::ZERO_EXTEND:
3040 case ISD::SIGN_EXTEND:
3050 case PPCISD::GlobalBaseReg:
3051 ReplaceNode(N, getGlobalBaseReg());
3054 case ISD::FrameIndex:
3055 selectFrameIndex(N, N);
3058 case PPCISD::MFOCRF: {
3059 SDValue InFlag = N->getOperand(1);
3060 ReplaceNode(N, CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32,
3061 N->getOperand(0), InFlag));
3065 case PPCISD::READ_TIME_BASE:
3066 ReplaceNode(N, CurDAG->getMachineNode(PPC::ReadTB, dl, MVT::i32, MVT::i32,
3067 MVT::Other, N->getOperand(0)));
3070 case PPCISD::SRA_ADDZE: {
3071 SDValue N0 = N->getOperand(0);
3073 CurDAG->getTargetConstant(*cast<ConstantSDNode>(N->getOperand(1))->
3074 getConstantIntValue(), dl,
3075 N->getValueType(0));
3076 if (N->getValueType(0) == MVT::i64) {
3078 CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, MVT::Glue,
3080 CurDAG->SelectNodeTo(N, PPC::ADDZE8, MVT::i64, SDValue(Op, 0),
3084 assert(N->getValueType(0) == MVT::i32 &&
3085 "Expecting i64 or i32 in PPCISD::SRA_ADDZE");
3087 CurDAG->getMachineNode(PPC::SRAWI, dl, MVT::i32, MVT::Glue,
3089 CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32, SDValue(Op, 0),
3096 // Handle preincrement loads.
3097 LoadSDNode *LD = cast<LoadSDNode>(N);
3098 EVT LoadedVT = LD->getMemoryVT();
3100 // Normal loads are handled by code generated from the .td file.
3101 if (LD->getAddressingMode() != ISD::PRE_INC)
3104 SDValue Offset = LD->getOffset();
3105 if (Offset.getOpcode() == ISD::TargetConstant ||
3106 Offset.getOpcode() == ISD::TargetGlobalAddress) {
3109 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD;
3110 if (LD->getValueType(0) != MVT::i64) {
3111 // Handle PPC32 integer and normal FP loads.
3112 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
3113 switch (LoadedVT.getSimpleVT().SimpleTy) {
3114 default: llvm_unreachable("Invalid PPC load type!");
3115 case MVT::f64: Opcode = PPC::LFDU; break;
3116 case MVT::f32: Opcode = PPC::LFSU; break;
3117 case MVT::i32: Opcode = PPC::LWZU; break;
3118 case MVT::i16: Opcode = isSExt ? PPC::LHAU : PPC::LHZU; break;
3120 case MVT::i8: Opcode = PPC::LBZU; break;
3123 assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!");
3124 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
3125 switch (LoadedVT.getSimpleVT().SimpleTy) {
3126 default: llvm_unreachable("Invalid PPC load type!");
3127 case MVT::i64: Opcode = PPC::LDU; break;
3128 case MVT::i32: Opcode = PPC::LWZU8; break;
3129 case MVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; break;
3131 case MVT::i8: Opcode = PPC::LBZU8; break;
3135 SDValue Chain = LD->getChain();
3136 SDValue Base = LD->getBasePtr();
3137 SDValue Ops[] = { Offset, Base, Chain };
3138 SDNode *MN = CurDAG->getMachineNode(
3139 Opcode, dl, LD->getValueType(0),
3140 PPCLowering->getPointerTy(CurDAG->getDataLayout()), MVT::Other, Ops);
3141 transferMemOperands(N, MN);
3146 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD;
3147 if (LD->getValueType(0) != MVT::i64) {
3148 // Handle PPC32 integer and normal FP loads.
3149 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
3150 switch (LoadedVT.getSimpleVT().SimpleTy) {
3151 default: llvm_unreachable("Invalid PPC load type!");
3152 case MVT::v4f64: Opcode = PPC::QVLFDUX; break; // QPX
3153 case MVT::v4f32: Opcode = PPC::QVLFSUX; break; // QPX
3154 case MVT::f64: Opcode = PPC::LFDUX; break;
3155 case MVT::f32: Opcode = PPC::LFSUX; break;
3156 case MVT::i32: Opcode = PPC::LWZUX; break;
3157 case MVT::i16: Opcode = isSExt ? PPC::LHAUX : PPC::LHZUX; break;
3159 case MVT::i8: Opcode = PPC::LBZUX; break;
3162 assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!");
3163 assert((!isSExt || LoadedVT == MVT::i16 || LoadedVT == MVT::i32) &&
3164 "Invalid sext update load");
3165 switch (LoadedVT.getSimpleVT().SimpleTy) {
3166 default: llvm_unreachable("Invalid PPC load type!");
3167 case MVT::i64: Opcode = PPC::LDUX; break;
3168 case MVT::i32: Opcode = isSExt ? PPC::LWAUX : PPC::LWZUX8; break;
3169 case MVT::i16: Opcode = isSExt ? PPC::LHAUX8 : PPC::LHZUX8; break;
3171 case MVT::i8: Opcode = PPC::LBZUX8; break;
3175 SDValue Chain = LD->getChain();
3176 SDValue Base = LD->getBasePtr();
3177 SDValue Ops[] = { Base, Offset, Chain };
3178 SDNode *MN = CurDAG->getMachineNode(
3179 Opcode, dl, LD->getValueType(0),
3180 PPCLowering->getPointerTy(CurDAG->getDataLayout()), MVT::Other, Ops);
3181 transferMemOperands(N, MN);
3188 if (tryLogicOpOfCompares(N))
3191 unsigned Imm, Imm2, SH, MB, ME;
3194 // If this is an and of a value rotated between 0 and 31 bits and then and'd
3195 // with a mask, emit rlwinm
3196 if (isInt32Immediate(N->getOperand(1), Imm) &&
3197 isRotateAndMask(N->getOperand(0).getNode(), Imm, false, SH, MB, ME)) {
3198 SDValue Val = N->getOperand(0).getOperand(0);
3199 SDValue Ops[] = { Val, getI32Imm(SH, dl), getI32Imm(MB, dl),
3200 getI32Imm(ME, dl) };
3201 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
3204 // If this is just a masked value where the input is not handled above, and
3205 // is not a rotate-left (handled by a pattern in the .td file), emit rlwinm
3206 if (isInt32Immediate(N->getOperand(1), Imm) &&
3207 isRunOfOnes(Imm, MB, ME) &&
3208 N->getOperand(0).getOpcode() != ISD::ROTL) {
3209 SDValue Val = N->getOperand(0);
3210 SDValue Ops[] = { Val, getI32Imm(0, dl), getI32Imm(MB, dl),
3211 getI32Imm(ME, dl) };
3212 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
3215 // If this is a 64-bit zero-extension mask, emit rldicl.
3216 if (isInt64Immediate(N->getOperand(1).getNode(), Imm64) &&
3218 SDValue Val = N->getOperand(0);
3219 MB = 64 - countTrailingOnes(Imm64);
3222 if (Val.getOpcode() == ISD::ANY_EXTEND) {
3223 auto Op0 = Val.getOperand(0);
3224 if ( Op0.getOpcode() == ISD::SRL &&
3225 isInt32Immediate(Op0.getOperand(1).getNode(), Imm) && Imm <= MB) {
3227 auto ResultType = Val.getNode()->getValueType(0);
3228 auto ImDef = CurDAG->getMachineNode(PPC::IMPLICIT_DEF, dl,
3230 SDValue IDVal (ImDef, 0);
3232 Val = SDValue(CurDAG->getMachineNode(PPC::INSERT_SUBREG, dl,
3233 ResultType, IDVal, Op0.getOperand(0),
3234 getI32Imm(1, dl)), 0);
3239 // If the operand is a logical right shift, we can fold it into this
3240 // instruction: rldicl(rldicl(x, 64-n, n), 0, mb) -> rldicl(x, 64-n, mb)
3241 // for n <= mb. The right shift is really a left rotate followed by a
3242 // mask, and this mask is a more-restrictive sub-mask of the mask implied
3244 if (Val.getOpcode() == ISD::SRL &&
3245 isInt32Immediate(Val.getOperand(1).getNode(), Imm) && Imm <= MB) {
3246 assert(Imm < 64 && "Illegal shift amount");
3247 Val = Val.getOperand(0);
3251 SDValue Ops[] = { Val, getI32Imm(SH, dl), getI32Imm(MB, dl) };
3252 CurDAG->SelectNodeTo(N, PPC::RLDICL, MVT::i64, Ops);
3255 // If this is a negated 64-bit zero-extension mask,
3256 // i.e. the immediate is a sequence of ones from most significant side
3257 // and all zero for reminder, we should use rldicr.
3258 if (isInt64Immediate(N->getOperand(1).getNode(), Imm64) &&
3259 isMask_64(~Imm64)) {
3260 SDValue Val = N->getOperand(0);
3261 MB = 63 - countTrailingOnes(~Imm64);
3263 SDValue Ops[] = { Val, getI32Imm(SH, dl), getI32Imm(MB, dl) };
3264 CurDAG->SelectNodeTo(N, PPC::RLDICR, MVT::i64, Ops);
3268 // AND X, 0 -> 0, not "rlwinm 32".
3269 if (isInt32Immediate(N->getOperand(1), Imm) && (Imm == 0)) {
3270 ReplaceUses(SDValue(N, 0), N->getOperand(1));
3273 // ISD::OR doesn't get all the bitfield insertion fun.
3274 // (and (or x, c1), c2) where isRunOfOnes(~(c1^c2)) might be a
3276 if (isInt32Immediate(N->getOperand(1), Imm) &&
3277 N->getOperand(0).getOpcode() == ISD::OR &&
3278 isInt32Immediate(N->getOperand(0).getOperand(1), Imm2)) {
3279 // The idea here is to check whether this is equivalent to:
3280 // (c1 & m) | (x & ~m)
3281 // where m is a run-of-ones mask. The logic here is that, for each bit in
3283 // - if both are 1, then the output will be 1.
3284 // - if both are 0, then the output will be 0.
3285 // - if the bit in c1 is 0, and the bit in c2 is 1, then the output will
3287 // - if the bit in c1 is 1, and the bit in c2 is 0, then the output will
3289 // If that last condition is never the case, then we can form m from the
3290 // bits that are the same between c1 and c2.
3292 if (isRunOfOnes(~(Imm^Imm2), MB, ME) && !(~Imm & Imm2)) {
3293 SDValue Ops[] = { N->getOperand(0).getOperand(0),
3294 N->getOperand(0).getOperand(1),
3295 getI32Imm(0, dl), getI32Imm(MB, dl),
3296 getI32Imm(ME, dl) };
3297 ReplaceNode(N, CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops));
3302 // Other cases are autogenerated.
3306 if (N->getValueType(0) == MVT::i32)
3307 if (tryBitfieldInsert(N))
3310 if (tryLogicOpOfCompares(N))
3314 if (N->getOperand(0)->getOpcode() == ISD::FrameIndex &&
3315 isIntS16Immediate(N->getOperand(1), Imm)) {
3317 CurDAG->computeKnownBits(N->getOperand(0), LHSKnown);
3319 // If this is equivalent to an add, then we can fold it with the
3320 // FrameIndex calculation.
3321 if ((LHSKnown.Zero.getZExtValue()|~(uint64_t)Imm) == ~0ULL) {
3322 selectFrameIndex(N, N->getOperand(0).getNode(), (int)Imm);
3327 // Other cases are autogenerated.
3331 if (tryLogicOpOfCompares(N))
3337 if (N->getOperand(0)->getOpcode() == ISD::FrameIndex &&
3338 isIntS16Immediate(N->getOperand(1), Imm)) {
3339 selectFrameIndex(N, N->getOperand(0).getNode(), (int)Imm);
3346 unsigned Imm, SH, MB, ME;
3347 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) &&
3348 isRotateAndMask(N, Imm, true, SH, MB, ME)) {
3349 SDValue Ops[] = { N->getOperand(0).getOperand(0),
3350 getI32Imm(SH, dl), getI32Imm(MB, dl),
3351 getI32Imm(ME, dl) };
3352 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
3356 // Other cases are autogenerated.
3360 unsigned Imm, SH, MB, ME;
3361 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) &&
3362 isRotateAndMask(N, Imm, true, SH, MB, ME)) {
3363 SDValue Ops[] = { N->getOperand(0).getOperand(0),
3364 getI32Imm(SH, dl), getI32Imm(MB, dl),
3365 getI32Imm(ME, dl) };
3366 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
3370 // Other cases are autogenerated.
3373 // FIXME: Remove this once the ANDI glue bug is fixed:
3374 case PPCISD::ANDIo_1_EQ_BIT:
3375 case PPCISD::ANDIo_1_GT_BIT: {
3379 EVT InVT = N->getOperand(0).getValueType();
3380 assert((InVT == MVT::i64 || InVT == MVT::i32) &&
3381 "Invalid input type for ANDIo_1_EQ_BIT");
3383 unsigned Opcode = (InVT == MVT::i64) ? PPC::ANDIo8 : PPC::ANDIo;
3384 SDValue AndI(CurDAG->getMachineNode(Opcode, dl, InVT, MVT::Glue,
3386 CurDAG->getTargetConstant(1, dl, InVT)),
3388 SDValue CR0Reg = CurDAG->getRegister(PPC::CR0, MVT::i32);
3390 CurDAG->getTargetConstant(N->getOpcode() == PPCISD::ANDIo_1_EQ_BIT ?
3391 PPC::sub_eq : PPC::sub_gt, dl, MVT::i32);
3393 CurDAG->SelectNodeTo(N, TargetOpcode::EXTRACT_SUBREG, MVT::i1, CR0Reg,
3394 SRIdxVal, SDValue(AndI.getNode(), 1) /* glue */);
3397 case ISD::SELECT_CC: {
3398 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
3400 CurDAG->getTargetLoweringInfo().getPointerTy(CurDAG->getDataLayout());
3401 bool isPPC64 = (PtrVT == MVT::i64);
3403 // If this is a select of i1 operands, we'll pattern match it.
3404 if (PPCSubTarget->useCRBits() &&
3405 N->getOperand(0).getValueType() == MVT::i1)
3408 // Handle the setcc cases here. select_cc lhs, 0, 1, 0, cc
3410 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
3411 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N->getOperand(2)))
3412 if (ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N->getOperand(3)))
3413 if (N1C->isNullValue() && N3C->isNullValue() &&
3414 N2C->getZExtValue() == 1ULL && CC == ISD::SETNE &&
3415 // FIXME: Implement this optzn for PPC64.
3416 N->getValueType(0) == MVT::i32) {
3418 CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
3419 N->getOperand(0), getI32Imm(~0U, dl));
3420 CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDValue(Tmp, 0),
3421 N->getOperand(0), SDValue(Tmp, 1));
3425 SDValue CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC, dl);
3427 if (N->getValueType(0) == MVT::i1) {
3428 // An i1 select is: (c & t) | (!c & f).
3430 unsigned Idx = getCRIdxForSetCC(CC, Inv);
3434 default: llvm_unreachable("Invalid CC index");
3435 case 0: SRI = PPC::sub_lt; break;
3436 case 1: SRI = PPC::sub_gt; break;
3437 case 2: SRI = PPC::sub_eq; break;
3438 case 3: SRI = PPC::sub_un; break;
3441 SDValue CCBit = CurDAG->getTargetExtractSubreg(SRI, dl, MVT::i1, CCReg);
3443 SDValue NotCCBit(CurDAG->getMachineNode(PPC::CRNOR, dl, MVT::i1,
3445 SDValue C = Inv ? NotCCBit : CCBit,
3446 NotC = Inv ? CCBit : NotCCBit;
3448 SDValue CAndT(CurDAG->getMachineNode(PPC::CRAND, dl, MVT::i1,
3449 C, N->getOperand(2)), 0);
3450 SDValue NotCAndF(CurDAG->getMachineNode(PPC::CRAND, dl, MVT::i1,
3451 NotC, N->getOperand(3)), 0);
3453 CurDAG->SelectNodeTo(N, PPC::CROR, MVT::i1, CAndT, NotCAndF);
3457 unsigned BROpc = getPredicateForSetCC(CC);
3459 unsigned SelectCCOp;
3460 if (N->getValueType(0) == MVT::i32)
3461 SelectCCOp = PPC::SELECT_CC_I4;
3462 else if (N->getValueType(0) == MVT::i64)
3463 SelectCCOp = PPC::SELECT_CC_I8;
3464 else if (N->getValueType(0) == MVT::f32)
3465 if (PPCSubTarget->hasP8Vector())
3466 SelectCCOp = PPC::SELECT_CC_VSSRC;
3468 SelectCCOp = PPC::SELECT_CC_F4;
3469 else if (N->getValueType(0) == MVT::f64)
3470 if (PPCSubTarget->hasVSX())
3471 SelectCCOp = PPC::SELECT_CC_VSFRC;
3473 SelectCCOp = PPC::SELECT_CC_F8;
3474 else if (PPCSubTarget->hasQPX() && N->getValueType(0) == MVT::v4f64)
3475 SelectCCOp = PPC::SELECT_CC_QFRC;
3476 else if (PPCSubTarget->hasQPX() && N->getValueType(0) == MVT::v4f32)
3477 SelectCCOp = PPC::SELECT_CC_QSRC;
3478 else if (PPCSubTarget->hasQPX() && N->getValueType(0) == MVT::v4i1)
3479 SelectCCOp = PPC::SELECT_CC_QBRC;
3480 else if (N->getValueType(0) == MVT::v2f64 ||
3481 N->getValueType(0) == MVT::v2i64)
3482 SelectCCOp = PPC::SELECT_CC_VSRC;
3484 SelectCCOp = PPC::SELECT_CC_VRRC;
3486 SDValue Ops[] = { CCReg, N->getOperand(2), N->getOperand(3),
3487 getI32Imm(BROpc, dl) };
3488 CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), Ops);
3492 if (PPCSubTarget->hasVSX()) {
3493 SDValue Ops[] = { N->getOperand(2), N->getOperand(1), N->getOperand(0) };
3494 CurDAG->SelectNodeTo(N, PPC::XXSEL, N->getValueType(0), Ops);
3499 case ISD::VECTOR_SHUFFLE:
3500 if (PPCSubTarget->hasVSX() && (N->getValueType(0) == MVT::v2f64 ||
3501 N->getValueType(0) == MVT::v2i64)) {
3502 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
3504 SDValue Op1 = N->getOperand(SVN->getMaskElt(0) < 2 ? 0 : 1),
3505 Op2 = N->getOperand(SVN->getMaskElt(1) < 2 ? 0 : 1);
3508 for (int i = 0; i < 2; ++i)
3509 if (SVN->getMaskElt(i) <= 0 || SVN->getMaskElt(i) == 2)
3514 if (Op1 == Op2 && DM[0] == 0 && DM[1] == 0 &&
3515 Op1.getOpcode() == ISD::SCALAR_TO_VECTOR &&
3516 isa<LoadSDNode>(Op1.getOperand(0))) {
3517 LoadSDNode *LD = cast<LoadSDNode>(Op1.getOperand(0));
3518 SDValue Base, Offset;
3520 if (LD->isUnindexed() && LD->hasOneUse() && Op1.hasOneUse() &&
3521 (LD->getMemoryVT() == MVT::f64 ||
3522 LD->getMemoryVT() == MVT::i64) &&
3523 SelectAddrIdxOnly(LD->getBasePtr(), Base, Offset)) {
3524 SDValue Chain = LD->getChain();
3525 SDValue Ops[] = { Base, Offset, Chain };
3526 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
3527 MemOp[0] = LD->getMemOperand();
3528 SDNode *NewN = CurDAG->SelectNodeTo(N, PPC::LXVDSX,
3529 N->getValueType(0), Ops);
3530 cast<MachineSDNode>(NewN)->setMemRefs(MemOp, MemOp + 1);
3535 // For little endian, we must swap the input operands and adjust
3536 // the mask elements (reverse and invert them).
3537 if (PPCSubTarget->isLittleEndian()) {
3538 std::swap(Op1, Op2);
3539 unsigned tmp = DM[0];
3544 SDValue DMV = CurDAG->getTargetConstant(DM[1] | (DM[0] << 1), dl,
3546 SDValue Ops[] = { Op1, Op2, DMV };
3547 CurDAG->SelectNodeTo(N, PPC::XXPERMDI, N->getValueType(0), Ops);
3554 bool IsPPC64 = PPCSubTarget->isPPC64();
3555 SDValue Ops[] = { N->getOperand(1), N->getOperand(0) };
3556 CurDAG->SelectNodeTo(N, N->getOpcode() == PPCISD::BDNZ
3557 ? (IsPPC64 ? PPC::BDNZ8 : PPC::BDNZ)
3558 : (IsPPC64 ? PPC::BDZ8 : PPC::BDZ),
3562 case PPCISD::COND_BRANCH: {
3563 // Op #0 is the Chain.
3564 // Op #1 is the PPC::PRED_* number.
3566 // Op #3 is the Dest MBB
3567 // Op #4 is the Flag.
3568 // Prevent PPC::PRED_* from being selected into LI.
3569 unsigned PCC = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
3570 if (EnableBranchHint)
3571 PCC |= getBranchHint(PCC, FuncInfo, N->getOperand(3));
3573 SDValue Pred = getI32Imm(PCC, dl);
3574 SDValue Ops[] = { Pred, N->getOperand(2), N->getOperand(3),
3575 N->getOperand(0), N->getOperand(4) };
3576 CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops);
3580 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
3581 unsigned PCC = getPredicateForSetCC(CC);
3583 if (N->getOperand(2).getValueType() == MVT::i1) {
3587 default: llvm_unreachable("Unexpected Boolean-operand predicate");
3588 case PPC::PRED_LT: Opc = PPC::CRANDC; Swap = true; break;
3589 case PPC::PRED_LE: Opc = PPC::CRORC; Swap = true; break;
3590 case PPC::PRED_EQ: Opc = PPC::CREQV; Swap = false; break;
3591 case PPC::PRED_GE: Opc = PPC::CRORC; Swap = false; break;
3592 case PPC::PRED_GT: Opc = PPC::CRANDC; Swap = false; break;
3593 case PPC::PRED_NE: Opc = PPC::CRXOR; Swap = false; break;
3596 SDValue BitComp(CurDAG->getMachineNode(Opc, dl, MVT::i1,
3597 N->getOperand(Swap ? 3 : 2),
3598 N->getOperand(Swap ? 2 : 3)), 0);
3599 CurDAG->SelectNodeTo(N, PPC::BC, MVT::Other, BitComp, N->getOperand(4),
3604 if (EnableBranchHint)
3605 PCC |= getBranchHint(PCC, FuncInfo, N->getOperand(4));
3607 SDValue CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC, dl);
3608 SDValue Ops[] = { getI32Imm(PCC, dl), CondCode,
3609 N->getOperand(4), N->getOperand(0) };
3610 CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops);
3614 // FIXME: Should custom lower this.
3615 SDValue Chain = N->getOperand(0);
3616 SDValue Target = N->getOperand(1);
3617 unsigned Opc = Target.getValueType() == MVT::i32 ? PPC::MTCTR : PPC::MTCTR8;
3618 unsigned Reg = Target.getValueType() == MVT::i32 ? PPC::BCTR : PPC::BCTR8;
3619 Chain = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Glue, Target,
3621 CurDAG->SelectNodeTo(N, Reg, MVT::Other, Chain);
3624 case PPCISD::TOC_ENTRY: {
3625 assert ((PPCSubTarget->isPPC64() || PPCSubTarget->isSVR4ABI()) &&
3626 "Only supported for 64-bit ABI and 32-bit SVR4");
3627 if (PPCSubTarget->isSVR4ABI() && !PPCSubTarget->isPPC64()) {
3628 SDValue GA = N->getOperand(0);
3629 SDNode *MN = CurDAG->getMachineNode(PPC::LWZtoc, dl, MVT::i32, GA,
3631 transferMemOperands(N, MN);
3636 // For medium and large code model, we generate two instructions as
3637 // described below. Otherwise we allow SelectCodeCommon to handle this,
3638 // selecting one of LDtoc, LDtocJTI, LDtocCPT, and LDtocBA.
3639 CodeModel::Model CModel = TM.getCodeModel();
3640 if (CModel != CodeModel::Medium && CModel != CodeModel::Large)
3643 // The first source operand is a TargetGlobalAddress or a TargetJumpTable.
3644 // If it must be toc-referenced according to PPCSubTarget, we generate:
3645 // LDtocL(<ga:@sym>, ADDIStocHA(%X2, <ga:@sym>))
3646 // Otherwise we generate:
3647 // ADDItocL(ADDIStocHA(%X2, <ga:@sym>), <ga:@sym>)
3648 SDValue GA = N->getOperand(0);
3649 SDValue TOCbase = N->getOperand(1);
3650 SDNode *Tmp = CurDAG->getMachineNode(PPC::ADDIStocHA, dl, MVT::i64,
3653 if (isa<JumpTableSDNode>(GA) || isa<BlockAddressSDNode>(GA) ||
3654 CModel == CodeModel::Large) {
3655 SDNode *MN = CurDAG->getMachineNode(PPC::LDtocL, dl, MVT::i64, GA,
3657 transferMemOperands(N, MN);
3662 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(GA)) {
3663 const GlobalValue *GV = G->getGlobal();
3664 unsigned char GVFlags = PPCSubTarget->classifyGlobalReference(GV);
3665 if (GVFlags & PPCII::MO_NLP_FLAG) {
3666 SDNode *MN = CurDAG->getMachineNode(PPC::LDtocL, dl, MVT::i64, GA,
3668 transferMemOperands(N, MN);
3674 ReplaceNode(N, CurDAG->getMachineNode(PPC::ADDItocL, dl, MVT::i64,
3675 SDValue(Tmp, 0), GA));
3678 case PPCISD::PPC32_PICGOT:
3679 // Generate a PIC-safe GOT reference.
3680 assert(!PPCSubTarget->isPPC64() && PPCSubTarget->isSVR4ABI() &&
3681 "PPCISD::PPC32_PICGOT is only supported for 32-bit SVR4");
3682 CurDAG->SelectNodeTo(N, PPC::PPC32PICGOT,
3683 PPCLowering->getPointerTy(CurDAG->getDataLayout()),
3687 case PPCISD::VADD_SPLAT: {
3688 // This expands into one of three sequences, depending on whether
3689 // the first operand is odd or even, positive or negative.
3690 assert(isa<ConstantSDNode>(N->getOperand(0)) &&
3691 isa<ConstantSDNode>(N->getOperand(1)) &&
3692 "Invalid operand on VADD_SPLAT!");
3694 int Elt = N->getConstantOperandVal(0);
3695 int EltSize = N->getConstantOperandVal(1);
3696 unsigned Opc1, Opc2, Opc3;
3700 Opc1 = PPC::VSPLTISB;
3701 Opc2 = PPC::VADDUBM;
3702 Opc3 = PPC::VSUBUBM;
3704 } else if (EltSize == 2) {
3705 Opc1 = PPC::VSPLTISH;
3706 Opc2 = PPC::VADDUHM;
3707 Opc3 = PPC::VSUBUHM;
3710 assert(EltSize == 4 && "Invalid element size on VADD_SPLAT!");
3711 Opc1 = PPC::VSPLTISW;
3712 Opc2 = PPC::VADDUWM;
3713 Opc3 = PPC::VSUBUWM;
3717 if ((Elt & 1) == 0) {
3718 // Elt is even, in the range [-32,-18] + [16,30].
3720 // Convert: VADD_SPLAT elt, size
3721 // Into: tmp = VSPLTIS[BHW] elt
3722 // VADDU[BHW]M tmp, tmp
3723 // Where: [BHW] = B for size = 1, H for size = 2, W for size = 4
3724 SDValue EltVal = getI32Imm(Elt >> 1, dl);
3725 SDNode *Tmp = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
3726 SDValue TmpVal = SDValue(Tmp, 0);
3727 ReplaceNode(N, CurDAG->getMachineNode(Opc2, dl, VT, TmpVal, TmpVal));
3729 } else if (Elt > 0) {
3730 // Elt is odd and positive, in the range [17,31].
3732 // Convert: VADD_SPLAT elt, size
3733 // Into: tmp1 = VSPLTIS[BHW] elt-16
3734 // tmp2 = VSPLTIS[BHW] -16
3735 // VSUBU[BHW]M tmp1, tmp2
3736 SDValue EltVal = getI32Imm(Elt - 16, dl);
3737 SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
3738 EltVal = getI32Imm(-16, dl);
3739 SDNode *Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
3740 ReplaceNode(N, CurDAG->getMachineNode(Opc3, dl, VT, SDValue(Tmp1, 0),
3744 // Elt is odd and negative, in the range [-31,-17].
3746 // Convert: VADD_SPLAT elt, size
3747 // Into: tmp1 = VSPLTIS[BHW] elt+16
3748 // tmp2 = VSPLTIS[BHW] -16
3749 // VADDU[BHW]M tmp1, tmp2
3750 SDValue EltVal = getI32Imm(Elt + 16, dl);
3751 SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
3752 EltVal = getI32Imm(-16, dl);
3753 SDNode *Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
3754 ReplaceNode(N, CurDAG->getMachineNode(Opc2, dl, VT, SDValue(Tmp1, 0),
3764 // If the target supports the cmpb instruction, do the idiom recognition here.
3765 // We don't do this as a DAG combine because we don't want to do it as nodes
3766 // are being combined (because we might miss part of the eventual idiom). We
3767 // don't want to do it during instruction selection because we want to reuse
3768 // the logic for lowering the masking operations already part of the
3769 // instruction selector.
3770 SDValue PPCDAGToDAGISel::combineToCMPB(SDNode *N) {
3773 assert(N->getOpcode() == ISD::OR &&
3774 "Only OR nodes are supported for CMPB");
3777 if (!PPCSubTarget->hasCMPB())
3780 if (N->getValueType(0) != MVT::i32 &&
3781 N->getValueType(0) != MVT::i64)
3784 EVT VT = N->getValueType(0);
3787 bool BytesFound[8] = {false, false, false, false, false, false, false, false};
3788 uint64_t Mask = 0, Alt = 0;
3790 auto IsByteSelectCC = [this](SDValue O, unsigned &b,
3791 uint64_t &Mask, uint64_t &Alt,
3792 SDValue &LHS, SDValue &RHS) {
3793 if (O.getOpcode() != ISD::SELECT_CC)
3795 ISD::CondCode CC = cast<CondCodeSDNode>(O.getOperand(4))->get();
3797 if (!isa<ConstantSDNode>(O.getOperand(2)) ||
3798 !isa<ConstantSDNode>(O.getOperand(3)))
3801 uint64_t PM = O.getConstantOperandVal(2);
3802 uint64_t PAlt = O.getConstantOperandVal(3);
3803 for (b = 0; b < 8; ++b) {
3804 uint64_t Mask = UINT64_C(0xFF) << (8*b);
3805 if (PM && (PM & Mask) == PM && (PAlt & Mask) == PAlt)
3814 if (!isa<ConstantSDNode>(O.getOperand(1)) ||
3815 O.getConstantOperandVal(1) != 0) {
3816 SDValue Op0 = O.getOperand(0), Op1 = O.getOperand(1);
3817 if (Op0.getOpcode() == ISD::TRUNCATE)
3818 Op0 = Op0.getOperand(0);
3819 if (Op1.getOpcode() == ISD::TRUNCATE)
3820 Op1 = Op1.getOperand(0);
3822 if (Op0.getOpcode() == ISD::SRL && Op1.getOpcode() == ISD::SRL &&
3823 Op0.getOperand(1) == Op1.getOperand(1) && CC == ISD::SETEQ &&
3824 isa<ConstantSDNode>(Op0.getOperand(1))) {
3826 unsigned Bits = Op0.getValueSizeInBits();
3829 if (Op0.getConstantOperandVal(1) != Bits-8)
3832 LHS = Op0.getOperand(0);
3833 RHS = Op1.getOperand(0);
3837 // When we have small integers (i16 to be specific), the form present
3838 // post-legalization uses SETULT in the SELECT_CC for the
3839 // higher-order byte, depending on the fact that the
3840 // even-higher-order bytes are known to all be zero, for example:
3841 // select_cc (xor $lhs, $rhs), 256, 65280, 0, setult
3842 // (so when the second byte is the same, because all higher-order
3843 // bits from bytes 3 and 4 are known to be zero, the result of the
3844 // xor can be at most 255)
3845 if (Op0.getOpcode() == ISD::XOR && CC == ISD::SETULT &&
3846 isa<ConstantSDNode>(O.getOperand(1))) {
3848 uint64_t ULim = O.getConstantOperandVal(1);
3849 if (ULim != (UINT64_C(1) << b*8))
3852 // Now we need to make sure that the upper bytes are known to be
3854 unsigned Bits = Op0.getValueSizeInBits();
3855 if (!CurDAG->MaskedValueIsZero(
3856 Op0, APInt::getHighBitsSet(Bits, Bits - (b + 1) * 8)))
3859 LHS = Op0.getOperand(0);
3860 RHS = Op0.getOperand(1);
3867 if (CC != ISD::SETEQ)
3870 SDValue Op = O.getOperand(0);
3871 if (Op.getOpcode() == ISD::AND) {
3872 if (!isa<ConstantSDNode>(Op.getOperand(1)))
3874 if (Op.getConstantOperandVal(1) != (UINT64_C(0xFF) << (8*b)))
3877 SDValue XOR = Op.getOperand(0);
3878 if (XOR.getOpcode() == ISD::TRUNCATE)
3879 XOR = XOR.getOperand(0);
3880 if (XOR.getOpcode() != ISD::XOR)
3883 LHS = XOR.getOperand(0);
3884 RHS = XOR.getOperand(1);
3886 } else if (Op.getOpcode() == ISD::SRL) {
3887 if (!isa<ConstantSDNode>(Op.getOperand(1)))
3889 unsigned Bits = Op.getValueSizeInBits();
3892 if (Op.getConstantOperandVal(1) != Bits-8)
3895 SDValue XOR = Op.getOperand(0);
3896 if (XOR.getOpcode() == ISD::TRUNCATE)
3897 XOR = XOR.getOperand(0);
3898 if (XOR.getOpcode() != ISD::XOR)
3901 LHS = XOR.getOperand(0);
3902 RHS = XOR.getOperand(1);
3909 SmallVector<SDValue, 8> Queue(1, SDValue(N, 0));
3910 while (!Queue.empty()) {
3911 SDValue V = Queue.pop_back_val();
3913 for (const SDValue &O : V.getNode()->ops()) {
3915 uint64_t M = 0, A = 0;
3917 if (O.getOpcode() == ISD::OR) {
3919 } else if (IsByteSelectCC(O, b, M, A, OLHS, ORHS)) {
3923 BytesFound[b] = true;
3926 } else if ((LHS == ORHS && RHS == OLHS) ||
3927 (RHS == ORHS && LHS == OLHS)) {
3928 BytesFound[b] = true;
3940 unsigned LastB = 0, BCnt = 0;
3941 for (unsigned i = 0; i < 8; ++i)
3942 if (BytesFound[LastB]) {
3947 if (!LastB || BCnt < 2)
3950 // Because we'll be zero-extending the output anyway if don't have a specific
3951 // value for each input byte (via the Mask), we can 'anyext' the inputs.
3952 if (LHS.getValueType() != VT) {
3953 LHS = CurDAG->getAnyExtOrTrunc(LHS, dl, VT);
3954 RHS = CurDAG->getAnyExtOrTrunc(RHS, dl, VT);
3957 Res = CurDAG->getNode(PPCISD::CMPB, dl, VT, LHS, RHS);
3959 bool NonTrivialMask = ((int64_t) Mask) != INT64_C(-1);
3960 if (NonTrivialMask && !Alt) {
3961 // Res = Mask & CMPB
3962 Res = CurDAG->getNode(ISD::AND, dl, VT, Res,
3963 CurDAG->getConstant(Mask, dl, VT));
3965 // Res = (CMPB & Mask) | (~CMPB & Alt)
3966 // Which, as suggested here:
3967 // https://graphics.stanford.edu/~seander/bithacks.html#MaskedMerge
3968 // can be written as:
3969 // Res = Alt ^ ((Alt ^ Mask) & CMPB)
3970 // useful because the (Alt ^ Mask) can be pre-computed.
3971 Res = CurDAG->getNode(ISD::AND, dl, VT, Res,
3972 CurDAG->getConstant(Mask ^ Alt, dl, VT));
3973 Res = CurDAG->getNode(ISD::XOR, dl, VT, Res,
3974 CurDAG->getConstant(Alt, dl, VT));
3980 // When CR bit registers are enabled, an extension of an i1 variable to a i32
3981 // or i64 value is lowered in terms of a SELECT_I[48] operation, and thus
3982 // involves constant materialization of a 0 or a 1 or both. If the result of
3983 // the extension is then operated upon by some operator that can be constant
3984 // folded with a constant 0 or 1, and that constant can be materialized using
3985 // only one instruction (like a zero or one), then we should fold in those
3986 // operations with the select.
3987 void PPCDAGToDAGISel::foldBoolExts(SDValue &Res, SDNode *&N) {
3988 if (!PPCSubTarget->useCRBits())
3991 if (N->getOpcode() != ISD::ZERO_EXTEND &&
3992 N->getOpcode() != ISD::SIGN_EXTEND &&
3993 N->getOpcode() != ISD::ANY_EXTEND)
3996 if (N->getOperand(0).getValueType() != MVT::i1)
3999 if (!N->hasOneUse())
4003 EVT VT = N->getValueType(0);
4004 SDValue Cond = N->getOperand(0);
4006 CurDAG->getConstant(N->getOpcode() == ISD::SIGN_EXTEND ? -1 : 1, dl, VT);
4007 SDValue ConstFalse = CurDAG->getConstant(0, dl, VT);
4010 SDNode *User = *N->use_begin();
4011 if (User->getNumOperands() != 2)
4014 auto TryFold = [this, N, User, dl](SDValue Val) {
4015 SDValue UserO0 = User->getOperand(0), UserO1 = User->getOperand(1);
4016 SDValue O0 = UserO0.getNode() == N ? Val : UserO0;
4017 SDValue O1 = UserO1.getNode() == N ? Val : UserO1;
4019 return CurDAG->FoldConstantArithmetic(User->getOpcode(), dl,
4020 User->getValueType(0),
4021 O0.getNode(), O1.getNode());
4024 // FIXME: When the semantics of the interaction between select and undef
4025 // are clearly defined, it may turn out to be unnecessary to break here.
4026 SDValue TrueRes = TryFold(ConstTrue);
4027 if (!TrueRes || TrueRes.isUndef())
4029 SDValue FalseRes = TryFold(ConstFalse);
4030 if (!FalseRes || FalseRes.isUndef())
4033 // For us to materialize these using one instruction, we must be able to
4034 // represent them as signed 16-bit integers.
4035 uint64_t True = cast<ConstantSDNode>(TrueRes)->getZExtValue(),
4036 False = cast<ConstantSDNode>(FalseRes)->getZExtValue();
4037 if (!isInt<16>(True) || !isInt<16>(False))
4040 // We can replace User with a new SELECT node, and try again to see if we
4041 // can fold the select with its user.
4042 Res = CurDAG->getSelect(dl, User->getValueType(0), Cond, TrueRes, FalseRes);
4044 ConstTrue = TrueRes;
4045 ConstFalse = FalseRes;
4046 } while (N->hasOneUse());
4049 void PPCDAGToDAGISel::PreprocessISelDAG() {
4050 SelectionDAG::allnodes_iterator Position(CurDAG->getRoot().getNode());
4053 bool MadeChange = false;
4054 while (Position != CurDAG->allnodes_begin()) {
4055 SDNode *N = &*--Position;
4060 switch (N->getOpcode()) {
4063 Res = combineToCMPB(N);
4068 foldBoolExts(Res, N);
4071 DEBUG(dbgs() << "PPC DAG preprocessing replacing:\nOld: ");
4072 DEBUG(N->dump(CurDAG));
4073 DEBUG(dbgs() << "\nNew: ");
4074 DEBUG(Res.getNode()->dump(CurDAG));
4075 DEBUG(dbgs() << "\n");
4077 CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), Res);
4083 CurDAG->RemoveDeadNodes();
4086 /// PostprocessISelDAG - Perform some late peephole optimizations
4087 /// on the DAG representation.
4088 void PPCDAGToDAGISel::PostprocessISelDAG() {
4089 // Skip peepholes at -O0.
4090 if (TM.getOptLevel() == CodeGenOpt::None)
4095 PeepholePPC64ZExt();
4098 // Check if all users of this node will become isel where the second operand
4099 // is the constant zero. If this is so, and if we can negate the condition,
4100 // then we can flip the true and false operands. This will allow the zero to
4101 // be folded with the isel so that we don't need to materialize a register
4103 bool PPCDAGToDAGISel::AllUsersSelectZero(SDNode *N) {
4104 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
4107 if (!User->isMachineOpcode())
4109 if (User->getMachineOpcode() != PPC::SELECT_I4 &&
4110 User->getMachineOpcode() != PPC::SELECT_I8)
4113 SDNode *Op2 = User->getOperand(2).getNode();
4114 if (!Op2->isMachineOpcode())
4117 if (Op2->getMachineOpcode() != PPC::LI &&
4118 Op2->getMachineOpcode() != PPC::LI8)
4121 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op2->getOperand(0));
4125 if (!C->isNullValue())
4132 void PPCDAGToDAGISel::SwapAllSelectUsers(SDNode *N) {
4133 SmallVector<SDNode *, 4> ToReplace;
4134 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
4137 assert((User->getMachineOpcode() == PPC::SELECT_I4 ||
4138 User->getMachineOpcode() == PPC::SELECT_I8) &&
4139 "Must have all select users");
4140 ToReplace.push_back(User);
4143 for (SmallVector<SDNode *, 4>::iterator UI = ToReplace.begin(),
4144 UE = ToReplace.end(); UI != UE; ++UI) {
4147 CurDAG->getMachineNode(User->getMachineOpcode(), SDLoc(User),
4148 User->getValueType(0), User->getOperand(0),
4149 User->getOperand(2),
4150 User->getOperand(1));
4152 DEBUG(dbgs() << "CR Peephole replacing:\nOld: ");
4153 DEBUG(User->dump(CurDAG));
4154 DEBUG(dbgs() << "\nNew: ");
4155 DEBUG(ResNode->dump(CurDAG));
4156 DEBUG(dbgs() << "\n");
4158 ReplaceUses(User, ResNode);
4162 void PPCDAGToDAGISel::PeepholeCROps() {
4166 for (SDNode &Node : CurDAG->allnodes()) {
4167 MachineSDNode *MachineNode = dyn_cast<MachineSDNode>(&Node);
4168 if (!MachineNode || MachineNode->use_empty())
4170 SDNode *ResNode = MachineNode;
4172 bool Op1Set = false, Op1Unset = false,
4174 Op2Set = false, Op2Unset = false,
4177 unsigned Opcode = MachineNode->getMachineOpcode();
4188 SDValue Op = MachineNode->getOperand(1);
4189 if (Op.isMachineOpcode()) {
4190 if (Op.getMachineOpcode() == PPC::CRSET)
4192 else if (Op.getMachineOpcode() == PPC::CRUNSET)
4194 else if (Op.getMachineOpcode() == PPC::CRNOR &&
4195 Op.getOperand(0) == Op.getOperand(1))
4202 case PPC::SELECT_I4:
4203 case PPC::SELECT_I8:
4204 case PPC::SELECT_F4:
4205 case PPC::SELECT_F8:
4206 case PPC::SELECT_QFRC:
4207 case PPC::SELECT_QSRC:
4208 case PPC::SELECT_QBRC:
4209 case PPC::SELECT_VRRC:
4210 case PPC::SELECT_VSFRC:
4211 case PPC::SELECT_VSSRC:
4212 case PPC::SELECT_VSRC: {
4213 SDValue Op = MachineNode->getOperand(0);
4214 if (Op.isMachineOpcode()) {
4215 if (Op.getMachineOpcode() == PPC::CRSET)
4217 else if (Op.getMachineOpcode() == PPC::CRUNSET)
4219 else if (Op.getMachineOpcode() == PPC::CRNOR &&
4220 Op.getOperand(0) == Op.getOperand(1))
4227 bool SelectSwap = false;
4231 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
4233 ResNode = MachineNode->getOperand(0).getNode();
4236 ResNode = MachineNode->getOperand(1).getNode();
4239 ResNode = MachineNode->getOperand(0).getNode();
4240 else if (Op1Unset || Op2Unset)
4241 // x & 0 = 0 & y = 0
4242 ResNode = CurDAG->getMachineNode(PPC::CRUNSET, SDLoc(MachineNode),
4245 // ~x & y = andc(y, x)
4246 ResNode = CurDAG->getMachineNode(PPC::CRANDC, SDLoc(MachineNode),
4247 MVT::i1, MachineNode->getOperand(1),
4248 MachineNode->getOperand(0).
4251 // x & ~y = andc(x, y)
4252 ResNode = CurDAG->getMachineNode(PPC::CRANDC, SDLoc(MachineNode),
4253 MVT::i1, MachineNode->getOperand(0),
4254 MachineNode->getOperand(1).
4256 else if (AllUsersSelectZero(MachineNode)) {
4257 ResNode = CurDAG->getMachineNode(PPC::CRNAND, SDLoc(MachineNode),
4258 MVT::i1, MachineNode->getOperand(0),
4259 MachineNode->getOperand(1));
4264 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
4265 // nand(x, x) -> nor(x, x)
4266 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
4267 MVT::i1, MachineNode->getOperand(0),
4268 MachineNode->getOperand(0));
4270 // nand(1, y) -> nor(y, y)
4271 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
4272 MVT::i1, MachineNode->getOperand(1),
4273 MachineNode->getOperand(1));
4275 // nand(x, 1) -> nor(x, x)
4276 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
4277 MVT::i1, MachineNode->getOperand(0),
4278 MachineNode->getOperand(0));
4279 else if (Op1Unset || Op2Unset)
4280 // nand(x, 0) = nand(0, y) = 1
4281 ResNode = CurDAG->getMachineNode(PPC::CRSET, SDLoc(MachineNode),
4284 // nand(~x, y) = ~(~x & y) = x | ~y = orc(x, y)
4285 ResNode = CurDAG->getMachineNode(PPC::CRORC, SDLoc(MachineNode),
4286 MVT::i1, MachineNode->getOperand(0).
4288 MachineNode->getOperand(1));
4290 // nand(x, ~y) = ~x | y = orc(y, x)
4291 ResNode = CurDAG->getMachineNode(PPC::CRORC, SDLoc(MachineNode),
4292 MVT::i1, MachineNode->getOperand(1).
4294 MachineNode->getOperand(0));
4295 else if (AllUsersSelectZero(MachineNode)) {
4296 ResNode = CurDAG->getMachineNode(PPC::CRAND, SDLoc(MachineNode),
4297 MVT::i1, MachineNode->getOperand(0),
4298 MachineNode->getOperand(1));
4303 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
4305 ResNode = MachineNode->getOperand(0).getNode();
4306 else if (Op1Set || Op2Set)
4307 // x | 1 = 1 | y = 1
4308 ResNode = CurDAG->getMachineNode(PPC::CRSET, SDLoc(MachineNode),
4312 ResNode = MachineNode->getOperand(1).getNode();
4315 ResNode = MachineNode->getOperand(0).getNode();
4317 // ~x | y = orc(y, x)
4318 ResNode = CurDAG->getMachineNode(PPC::CRORC, SDLoc(MachineNode),
4319 MVT::i1, MachineNode->getOperand(1),
4320 MachineNode->getOperand(0).
4323 // x | ~y = orc(x, y)
4324 ResNode = CurDAG->getMachineNode(PPC::CRORC, SDLoc(MachineNode),
4325 MVT::i1, MachineNode->getOperand(0),
4326 MachineNode->getOperand(1).
4328 else if (AllUsersSelectZero(MachineNode)) {
4329 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
4330 MVT::i1, MachineNode->getOperand(0),
4331 MachineNode->getOperand(1));
4336 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
4338 ResNode = CurDAG->getMachineNode(PPC::CRUNSET, SDLoc(MachineNode),
4341 // xor(1, y) -> nor(y, y)
4342 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
4343 MVT::i1, MachineNode->getOperand(1),
4344 MachineNode->getOperand(1));
4346 // xor(x, 1) -> nor(x, x)
4347 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
4348 MVT::i1, MachineNode->getOperand(0),
4349 MachineNode->getOperand(0));
4352 ResNode = MachineNode->getOperand(1).getNode();
4355 ResNode = MachineNode->getOperand(0).getNode();
4357 // xor(~x, y) = eqv(x, y)
4358 ResNode = CurDAG->getMachineNode(PPC::CREQV, SDLoc(MachineNode),
4359 MVT::i1, MachineNode->getOperand(0).
4361 MachineNode->getOperand(1));
4363 // xor(x, ~y) = eqv(x, y)
4364 ResNode = CurDAG->getMachineNode(PPC::CREQV, SDLoc(MachineNode),
4365 MVT::i1, MachineNode->getOperand(0),
4366 MachineNode->getOperand(1).
4368 else if (AllUsersSelectZero(MachineNode)) {
4369 ResNode = CurDAG->getMachineNode(PPC::CREQV, SDLoc(MachineNode),
4370 MVT::i1, MachineNode->getOperand(0),
4371 MachineNode->getOperand(1));
4376 if (Op1Set || Op2Set)
4378 ResNode = CurDAG->getMachineNode(PPC::CRUNSET, SDLoc(MachineNode),
4381 // nor(0, y) = ~y -> nor(y, y)
4382 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
4383 MVT::i1, MachineNode->getOperand(1),
4384 MachineNode->getOperand(1));
4387 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
4388 MVT::i1, MachineNode->getOperand(0),
4389 MachineNode->getOperand(0));
4391 // nor(~x, y) = andc(x, y)
4392 ResNode = CurDAG->getMachineNode(PPC::CRANDC, SDLoc(MachineNode),
4393 MVT::i1, MachineNode->getOperand(0).
4395 MachineNode->getOperand(1));
4397 // nor(x, ~y) = andc(y, x)
4398 ResNode = CurDAG->getMachineNode(PPC::CRANDC, SDLoc(MachineNode),
4399 MVT::i1, MachineNode->getOperand(1).
4401 MachineNode->getOperand(0));
4402 else if (AllUsersSelectZero(MachineNode)) {
4403 ResNode = CurDAG->getMachineNode(PPC::CROR, SDLoc(MachineNode),
4404 MVT::i1, MachineNode->getOperand(0),
4405 MachineNode->getOperand(1));
4410 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
4412 ResNode = CurDAG->getMachineNode(PPC::CRSET, SDLoc(MachineNode),
4416 ResNode = MachineNode->getOperand(1).getNode();
4419 ResNode = MachineNode->getOperand(0).getNode();
4421 // eqv(0, y) = ~y -> nor(y, y)
4422 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
4423 MVT::i1, MachineNode->getOperand(1),
4424 MachineNode->getOperand(1));
4427 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
4428 MVT::i1, MachineNode->getOperand(0),
4429 MachineNode->getOperand(0));
4431 // eqv(~x, y) = xor(x, y)
4432 ResNode = CurDAG->getMachineNode(PPC::CRXOR, SDLoc(MachineNode),
4433 MVT::i1, MachineNode->getOperand(0).
4435 MachineNode->getOperand(1));
4437 // eqv(x, ~y) = xor(x, y)
4438 ResNode = CurDAG->getMachineNode(PPC::CRXOR, SDLoc(MachineNode),
4439 MVT::i1, MachineNode->getOperand(0),
4440 MachineNode->getOperand(1).
4442 else if (AllUsersSelectZero(MachineNode)) {
4443 ResNode = CurDAG->getMachineNode(PPC::CRXOR, SDLoc(MachineNode),
4444 MVT::i1, MachineNode->getOperand(0),
4445 MachineNode->getOperand(1));
4450 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
4452 ResNode = CurDAG->getMachineNode(PPC::CRUNSET, SDLoc(MachineNode),
4456 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
4457 MVT::i1, MachineNode->getOperand(1),
4458 MachineNode->getOperand(1));
4459 else if (Op1Unset || Op2Set)
4460 // andc(0, y) = andc(x, 1) = 0
4461 ResNode = CurDAG->getMachineNode(PPC::CRUNSET, SDLoc(MachineNode),
4465 ResNode = MachineNode->getOperand(0).getNode();
4467 // andc(~x, y) = ~(x | y) = nor(x, y)
4468 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
4469 MVT::i1, MachineNode->getOperand(0).
4471 MachineNode->getOperand(1));
4473 // andc(x, ~y) = x & y
4474 ResNode = CurDAG->getMachineNode(PPC::CRAND, SDLoc(MachineNode),
4475 MVT::i1, MachineNode->getOperand(0),
4476 MachineNode->getOperand(1).
4478 else if (AllUsersSelectZero(MachineNode)) {
4479 ResNode = CurDAG->getMachineNode(PPC::CRORC, SDLoc(MachineNode),
4480 MVT::i1, MachineNode->getOperand(1),
4481 MachineNode->getOperand(0));
4486 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
4488 ResNode = CurDAG->getMachineNode(PPC::CRSET, SDLoc(MachineNode),
4490 else if (Op1Set || Op2Unset)
4491 // orc(1, y) = orc(x, 0) = 1
4492 ResNode = CurDAG->getMachineNode(PPC::CRSET, SDLoc(MachineNode),
4496 ResNode = MachineNode->getOperand(0).getNode();
4499 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
4500 MVT::i1, MachineNode->getOperand(1),
4501 MachineNode->getOperand(1));
4503 // orc(~x, y) = ~(x & y) = nand(x, y)
4504 ResNode = CurDAG->getMachineNode(PPC::CRNAND, SDLoc(MachineNode),
4505 MVT::i1, MachineNode->getOperand(0).
4507 MachineNode->getOperand(1));
4509 // orc(x, ~y) = x | y
4510 ResNode = CurDAG->getMachineNode(PPC::CROR, SDLoc(MachineNode),
4511 MVT::i1, MachineNode->getOperand(0),
4512 MachineNode->getOperand(1).
4514 else if (AllUsersSelectZero(MachineNode)) {
4515 ResNode = CurDAG->getMachineNode(PPC::CRANDC, SDLoc(MachineNode),
4516 MVT::i1, MachineNode->getOperand(1),
4517 MachineNode->getOperand(0));
4521 case PPC::SELECT_I4:
4522 case PPC::SELECT_I8:
4523 case PPC::SELECT_F4:
4524 case PPC::SELECT_F8:
4525 case PPC::SELECT_QFRC:
4526 case PPC::SELECT_QSRC:
4527 case PPC::SELECT_QBRC:
4528 case PPC::SELECT_VRRC:
4529 case PPC::SELECT_VSFRC:
4530 case PPC::SELECT_VSSRC:
4531 case PPC::SELECT_VSRC:
4533 ResNode = MachineNode->getOperand(1).getNode();
4535 ResNode = MachineNode->getOperand(2).getNode();
4537 ResNode = CurDAG->getMachineNode(MachineNode->getMachineOpcode(),
4539 MachineNode->getValueType(0),
4540 MachineNode->getOperand(0).
4542 MachineNode->getOperand(2),
4543 MachineNode->getOperand(1));
4548 ResNode = CurDAG->getMachineNode(Opcode == PPC::BC ? PPC::BCn :
4552 MachineNode->getOperand(0).
4554 MachineNode->getOperand(1),
4555 MachineNode->getOperand(2));
4556 // FIXME: Handle Op1Set, Op1Unset here too.
4560 // If we're inverting this node because it is used only by selects that
4561 // we'd like to swap, then swap the selects before the node replacement.
4563 SwapAllSelectUsers(MachineNode);
4565 if (ResNode != MachineNode) {
4566 DEBUG(dbgs() << "CR Peephole replacing:\nOld: ");
4567 DEBUG(MachineNode->dump(CurDAG));
4568 DEBUG(dbgs() << "\nNew: ");
4569 DEBUG(ResNode->dump(CurDAG));
4570 DEBUG(dbgs() << "\n");
4572 ReplaceUses(MachineNode, ResNode);
4577 CurDAG->RemoveDeadNodes();
4578 } while (IsModified);
4581 // Gather the set of 32-bit operations that are known to have their
4582 // higher-order 32 bits zero, where ToPromote contains all such operations.
4583 static bool PeepholePPC64ZExtGather(SDValue Op32,
4584 SmallPtrSetImpl<SDNode *> &ToPromote) {
4585 if (!Op32.isMachineOpcode())
4588 // First, check for the "frontier" instructions (those that will clear the
4589 // higher-order 32 bits.
4591 // For RLWINM and RLWNM, we need to make sure that the mask does not wrap
4592 // around. If it does not, then these instructions will clear the
4593 // higher-order bits.
4594 if ((Op32.getMachineOpcode() == PPC::RLWINM ||
4595 Op32.getMachineOpcode() == PPC::RLWNM) &&
4596 Op32.getConstantOperandVal(2) <= Op32.getConstantOperandVal(3)) {
4597 ToPromote.insert(Op32.getNode());
4601 // SLW and SRW always clear the higher-order bits.
4602 if (Op32.getMachineOpcode() == PPC::SLW ||
4603 Op32.getMachineOpcode() == PPC::SRW) {
4604 ToPromote.insert(Op32.getNode());
4608 // For LI and LIS, we need the immediate to be positive (so that it is not
4610 if (Op32.getMachineOpcode() == PPC::LI ||
4611 Op32.getMachineOpcode() == PPC::LIS) {
4612 if (!isUInt<15>(Op32.getConstantOperandVal(0)))
4615 ToPromote.insert(Op32.getNode());
4619 // LHBRX and LWBRX always clear the higher-order bits.
4620 if (Op32.getMachineOpcode() == PPC::LHBRX ||
4621 Op32.getMachineOpcode() == PPC::LWBRX) {
4622 ToPromote.insert(Op32.getNode());
4626 // CNT[LT]ZW always produce a 64-bit value in [0,32], and so is zero extended.
4627 if (Op32.getMachineOpcode() == PPC::CNTLZW ||
4628 Op32.getMachineOpcode() == PPC::CNTTZW) {
4629 ToPromote.insert(Op32.getNode());
4633 // Next, check for those instructions we can look through.
4635 // Assuming the mask does not wrap around, then the higher-order bits are
4636 // taken directly from the first operand.
4637 if (Op32.getMachineOpcode() == PPC::RLWIMI &&
4638 Op32.getConstantOperandVal(3) <= Op32.getConstantOperandVal(4)) {
4639 SmallPtrSet<SDNode *, 16> ToPromote1;
4640 if (!PeepholePPC64ZExtGather(Op32.getOperand(0), ToPromote1))
4643 ToPromote.insert(Op32.getNode());
4644 ToPromote.insert(ToPromote1.begin(), ToPromote1.end());
4648 // For OR, the higher-order bits are zero if that is true for both operands.
4649 // For SELECT_I4, the same is true (but the relevant operand numbers are
4651 if (Op32.getMachineOpcode() == PPC::OR ||
4652 Op32.getMachineOpcode() == PPC::SELECT_I4) {
4653 unsigned B = Op32.getMachineOpcode() == PPC::SELECT_I4 ? 1 : 0;
4654 SmallPtrSet<SDNode *, 16> ToPromote1;
4655 if (!PeepholePPC64ZExtGather(Op32.getOperand(B+0), ToPromote1))
4657 if (!PeepholePPC64ZExtGather(Op32.getOperand(B+1), ToPromote1))
4660 ToPromote.insert(Op32.getNode());
4661 ToPromote.insert(ToPromote1.begin(), ToPromote1.end());
4665 // For ORI and ORIS, we need the higher-order bits of the first operand to be
4666 // zero, and also for the constant to be positive (so that it is not sign
4668 if (Op32.getMachineOpcode() == PPC::ORI ||
4669 Op32.getMachineOpcode() == PPC::ORIS) {
4670 SmallPtrSet<SDNode *, 16> ToPromote1;
4671 if (!PeepholePPC64ZExtGather(Op32.getOperand(0), ToPromote1))
4673 if (!isUInt<15>(Op32.getConstantOperandVal(1)))
4676 ToPromote.insert(Op32.getNode());
4677 ToPromote.insert(ToPromote1.begin(), ToPromote1.end());
4681 // The higher-order bits of AND are zero if that is true for at least one of
4683 if (Op32.getMachineOpcode() == PPC::AND) {
4684 SmallPtrSet<SDNode *, 16> ToPromote1, ToPromote2;
4686 PeepholePPC64ZExtGather(Op32.getOperand(0), ToPromote1);
4688 PeepholePPC64ZExtGather(Op32.getOperand(1), ToPromote2);
4689 if (!Op0OK && !Op1OK)
4692 ToPromote.insert(Op32.getNode());
4695 ToPromote.insert(ToPromote1.begin(), ToPromote1.end());
4698 ToPromote.insert(ToPromote2.begin(), ToPromote2.end());
4703 // For ANDI and ANDIS, the higher-order bits are zero if either that is true
4704 // of the first operand, or if the second operand is positive (so that it is
4705 // not sign extended).
4706 if (Op32.getMachineOpcode() == PPC::ANDIo ||
4707 Op32.getMachineOpcode() == PPC::ANDISo) {
4708 SmallPtrSet<SDNode *, 16> ToPromote1;
4710 PeepholePPC64ZExtGather(Op32.getOperand(0), ToPromote1);
4711 bool Op1OK = isUInt<15>(Op32.getConstantOperandVal(1));
4712 if (!Op0OK && !Op1OK)
4715 ToPromote.insert(Op32.getNode());
4718 ToPromote.insert(ToPromote1.begin(), ToPromote1.end());
4726 void PPCDAGToDAGISel::PeepholePPC64ZExt() {
4727 if (!PPCSubTarget->isPPC64())
4730 // When we zero-extend from i32 to i64, we use a pattern like this:
4731 // def : Pat<(i64 (zext i32:$in)),
4732 // (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32),
4734 // There are several 32-bit shift/rotate instructions, however, that will
4735 // clear the higher-order bits of their output, rendering the RLDICL
4736 // unnecessary. When that happens, we remove it here, and redefine the
4737 // relevant 32-bit operation to be a 64-bit operation.
4739 SelectionDAG::allnodes_iterator Position(CurDAG->getRoot().getNode());
4742 bool MadeChange = false;
4743 while (Position != CurDAG->allnodes_begin()) {
4744 SDNode *N = &*--Position;
4745 // Skip dead nodes and any non-machine opcodes.
4746 if (N->use_empty() || !N->isMachineOpcode())
4749 if (N->getMachineOpcode() != PPC::RLDICL)
4752 if (N->getConstantOperandVal(1) != 0 ||
4753 N->getConstantOperandVal(2) != 32)
4756 SDValue ISR = N->getOperand(0);
4757 if (!ISR.isMachineOpcode() ||
4758 ISR.getMachineOpcode() != TargetOpcode::INSERT_SUBREG)
4761 if (!ISR.hasOneUse())
4764 if (ISR.getConstantOperandVal(2) != PPC::sub_32)
4767 SDValue IDef = ISR.getOperand(0);
4768 if (!IDef.isMachineOpcode() ||
4769 IDef.getMachineOpcode() != TargetOpcode::IMPLICIT_DEF)
4772 // We now know that we're looking at a canonical i32 -> i64 zext. See if we
4773 // can get rid of it.
4775 SDValue Op32 = ISR->getOperand(1);
4776 if (!Op32.isMachineOpcode())
4779 // There are some 32-bit instructions that always clear the high-order 32
4780 // bits, there are also some instructions (like AND) that we can look
4782 SmallPtrSet<SDNode *, 16> ToPromote;
4783 if (!PeepholePPC64ZExtGather(Op32, ToPromote))
4786 // If the ToPromote set contains nodes that have uses outside of the set
4787 // (except for the original INSERT_SUBREG), then abort the transformation.
4788 bool OutsideUse = false;
4789 for (SDNode *PN : ToPromote) {
4790 for (SDNode *UN : PN->uses()) {
4791 if (!ToPromote.count(UN) && UN != ISR.getNode()) {
4805 // We now know that this zero extension can be removed by promoting to
4806 // nodes in ToPromote to 64-bit operations, where for operations in the
4807 // frontier of the set, we need to insert INSERT_SUBREGs for their
4809 for (SDNode *PN : ToPromote) {
4811 switch (PN->getMachineOpcode()) {
4813 llvm_unreachable("Don't know the 64-bit variant of this instruction");
4814 case PPC::RLWINM: NewOpcode = PPC::RLWINM8; break;
4815 case PPC::RLWNM: NewOpcode = PPC::RLWNM8; break;
4816 case PPC::SLW: NewOpcode = PPC::SLW8; break;
4817 case PPC::SRW: NewOpcode = PPC::SRW8; break;
4818 case PPC::LI: NewOpcode = PPC::LI8; break;
4819 case PPC::LIS: NewOpcode = PPC::LIS8; break;
4820 case PPC::LHBRX: NewOpcode = PPC::LHBRX8; break;
4821 case PPC::LWBRX: NewOpcode = PPC::LWBRX8; break;
4822 case PPC::CNTLZW: NewOpcode = PPC::CNTLZW8; break;
4823 case PPC::CNTTZW: NewOpcode = PPC::CNTTZW8; break;
4824 case PPC::RLWIMI: NewOpcode = PPC::RLWIMI8; break;
4825 case PPC::OR: NewOpcode = PPC::OR8; break;
4826 case PPC::SELECT_I4: NewOpcode = PPC::SELECT_I8; break;
4827 case PPC::ORI: NewOpcode = PPC::ORI8; break;
4828 case PPC::ORIS: NewOpcode = PPC::ORIS8; break;
4829 case PPC::AND: NewOpcode = PPC::AND8; break;
4830 case PPC::ANDIo: NewOpcode = PPC::ANDIo8; break;
4831 case PPC::ANDISo: NewOpcode = PPC::ANDISo8; break;
4834 // Note: During the replacement process, the nodes will be in an
4835 // inconsistent state (some instructions will have operands with values
4836 // of the wrong type). Once done, however, everything should be right
4839 SmallVector<SDValue, 4> Ops;
4840 for (const SDValue &V : PN->ops()) {
4841 if (!ToPromote.count(V.getNode()) && V.getValueType() == MVT::i32 &&
4842 !isa<ConstantSDNode>(V)) {
4843 SDValue ReplOpOps[] = { ISR.getOperand(0), V, ISR.getOperand(2) };
4845 CurDAG->getMachineNode(TargetOpcode::INSERT_SUBREG, SDLoc(V),
4846 ISR.getNode()->getVTList(), ReplOpOps);
4847 Ops.push_back(SDValue(ReplOp, 0));
4853 // Because all to-be-promoted nodes only have users that are other
4854 // promoted nodes (or the original INSERT_SUBREG), we can safely replace
4855 // the i32 result value type with i64.
4857 SmallVector<EVT, 2> NewVTs;
4858 SDVTList VTs = PN->getVTList();
4859 for (unsigned i = 0, ie = VTs.NumVTs; i != ie; ++i)
4860 if (VTs.VTs[i] == MVT::i32)
4861 NewVTs.push_back(MVT::i64);
4863 NewVTs.push_back(VTs.VTs[i]);
4865 DEBUG(dbgs() << "PPC64 ZExt Peephole morphing:\nOld: ");
4866 DEBUG(PN->dump(CurDAG));
4868 CurDAG->SelectNodeTo(PN, NewOpcode, CurDAG->getVTList(NewVTs), Ops);
4870 DEBUG(dbgs() << "\nNew: ");
4871 DEBUG(PN->dump(CurDAG));
4872 DEBUG(dbgs() << "\n");
4875 // Now we replace the original zero extend and its associated INSERT_SUBREG
4876 // with the value feeding the INSERT_SUBREG (which has now been promoted to
4879 DEBUG(dbgs() << "PPC64 ZExt Peephole replacing:\nOld: ");
4880 DEBUG(N->dump(CurDAG));
4881 DEBUG(dbgs() << "\nNew: ");
4882 DEBUG(Op32.getNode()->dump(CurDAG));
4883 DEBUG(dbgs() << "\n");
4885 ReplaceUses(N, Op32.getNode());
4889 CurDAG->RemoveDeadNodes();
4892 void PPCDAGToDAGISel::PeepholePPC64() {
4893 // These optimizations are currently supported only for 64-bit SVR4.
4894 if (PPCSubTarget->isDarwin() || !PPCSubTarget->isPPC64())
4897 SelectionDAG::allnodes_iterator Position(CurDAG->getRoot().getNode());
4900 while (Position != CurDAG->allnodes_begin()) {
4901 SDNode *N = &*--Position;
4902 // Skip dead nodes and any non-machine opcodes.
4903 if (N->use_empty() || !N->isMachineOpcode())
4907 unsigned StorageOpcode = N->getMachineOpcode();
4909 switch (StorageOpcode) {
4940 // If this is a load or store with a zero offset, or within the alignment,
4941 // we may be able to fold an add-immediate into the memory operation.
4942 // The check against alignment is below, as it can't occur until we check
4943 // the arguments to N
4944 if (!isa<ConstantSDNode>(N->getOperand(FirstOp)))
4947 SDValue Base = N->getOperand(FirstOp + 1);
4948 if (!Base.isMachineOpcode())
4952 bool ReplaceFlags = true;
4954 // When the feeding operation is an add-immediate of some sort,
4955 // determine whether we need to add relocation information to the
4956 // target flags on the immediate operand when we fold it into the
4957 // load instruction.
4959 // For something like ADDItocL, the relocation information is
4960 // inferred from the opcode; when we process it in the AsmPrinter,
4961 // we add the necessary relocation there. A load, though, can receive
4962 // relocation from various flavors of ADDIxxx, so we need to carry
4963 // the relocation information in the target flags.
4964 switch (Base.getMachineOpcode()) {
4969 // In some cases (such as TLS) the relocation information
4970 // is already in place on the operand, so copying the operand
4972 ReplaceFlags = false;
4973 // For these cases, the immediate may not be divisible by 4, in
4974 // which case the fold is illegal for DS-form instructions. (The
4975 // other cases provide aligned addresses and are always safe.)
4976 if ((StorageOpcode == PPC::LWA ||
4977 StorageOpcode == PPC::LD ||
4978 StorageOpcode == PPC::STD) &&
4979 (!isa<ConstantSDNode>(Base.getOperand(1)) ||
4980 Base.getConstantOperandVal(1) % 4 != 0))
4983 case PPC::ADDIdtprelL:
4984 Flags = PPCII::MO_DTPREL_LO;
4986 case PPC::ADDItlsldL:
4987 Flags = PPCII::MO_TLSLD_LO;
4990 Flags = PPCII::MO_TOC_LO;
4994 SDValue ImmOpnd = Base.getOperand(1);
4996 // On PPC64, the TOC base pointer is guaranteed by the ABI only to have
4997 // 8-byte alignment, and so we can only use offsets less than 8 (otherwise,
4998 // we might have needed different @ha relocation values for the offset
5000 int MaxDisplacement = 7;
5001 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(ImmOpnd)) {
5002 const GlobalValue *GV = GA->getGlobal();
5003 MaxDisplacement = std::min((int) GV->getAlignment() - 1, MaxDisplacement);
5006 bool UpdateHBase = false;
5007 SDValue HBase = Base.getOperand(0);
5009 int Offset = N->getConstantOperandVal(FirstOp);
5011 if (Offset < 0 || Offset > MaxDisplacement) {
5012 // If we have a addi(toc@l)/addis(toc@ha) pair, and the addis has only
5013 // one use, then we can do this for any offset, we just need to also
5014 // update the offset (i.e. the symbol addend) on the addis also.
5015 if (Base.getMachineOpcode() != PPC::ADDItocL)
5018 if (!HBase.isMachineOpcode() ||
5019 HBase.getMachineOpcode() != PPC::ADDIStocHA)
5022 if (!Base.hasOneUse() || !HBase.hasOneUse())
5025 SDValue HImmOpnd = HBase.getOperand(1);
5026 if (HImmOpnd != ImmOpnd)
5032 // If we're directly folding the addend from an addi instruction, then:
5033 // 1. In general, the offset on the memory access must be zero.
5034 // 2. If the addend is a constant, then it can be combined with a
5035 // non-zero offset, but only if the result meets the encoding
5037 if (auto *C = dyn_cast<ConstantSDNode>(ImmOpnd)) {
5038 Offset += C->getSExtValue();
5040 if ((StorageOpcode == PPC::LWA || StorageOpcode == PPC::LD ||
5041 StorageOpcode == PPC::STD) && (Offset % 4) != 0)
5044 if (!isInt<16>(Offset))
5047 ImmOpnd = CurDAG->getTargetConstant(Offset, SDLoc(ImmOpnd),
5048 ImmOpnd.getValueType());
5049 } else if (Offset != 0) {
5054 // We found an opportunity. Reverse the operands from the add
5055 // immediate and substitute them into the load or store. If
5056 // needed, update the target flags for the immediate operand to
5057 // reflect the necessary relocation information.
5058 DEBUG(dbgs() << "Folding add-immediate into mem-op:\nBase: ");
5059 DEBUG(Base->dump(CurDAG));
5060 DEBUG(dbgs() << "\nN: ");
5061 DEBUG(N->dump(CurDAG));
5062 DEBUG(dbgs() << "\n");
5064 // If the relocation information isn't already present on the
5065 // immediate operand, add it now.
5067 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(ImmOpnd)) {
5069 const GlobalValue *GV = GA->getGlobal();
5070 // We can't perform this optimization for data whose alignment
5071 // is insufficient for the instruction encoding.
5072 if (GV->getAlignment() < 4 &&
5073 (StorageOpcode == PPC::LD || StorageOpcode == PPC::STD ||
5074 StorageOpcode == PPC::LWA || (Offset % 4) != 0)) {
5075 DEBUG(dbgs() << "Rejected this candidate for alignment.\n\n");
5078 ImmOpnd = CurDAG->getTargetGlobalAddress(GV, dl, MVT::i64, Offset, Flags);
5079 } else if (ConstantPoolSDNode *CP =
5080 dyn_cast<ConstantPoolSDNode>(ImmOpnd)) {
5081 const Constant *C = CP->getConstVal();
5082 ImmOpnd = CurDAG->getTargetConstantPool(C, MVT::i64,
5088 if (FirstOp == 1) // Store
5089 (void)CurDAG->UpdateNodeOperands(N, N->getOperand(0), ImmOpnd,
5090 Base.getOperand(0), N->getOperand(3));
5092 (void)CurDAG->UpdateNodeOperands(N, ImmOpnd, Base.getOperand(0),
5096 (void)CurDAG->UpdateNodeOperands(HBase.getNode(), HBase.getOperand(0),
5099 // The add-immediate may now be dead, in which case remove it.
5100 if (Base.getNode()->use_empty())
5101 CurDAG->RemoveDeadNode(Base.getNode());
5105 /// createPPCISelDag - This pass converts a legalized DAG into a
5106 /// PowerPC-specific DAG, ready for instruction scheduling.
5108 FunctionPass *llvm::createPPCISelDag(PPCTargetMachine &TM,
5109 CodeGenOpt::Level OptLevel) {
5110 return new PPCDAGToDAGISel(TM, OptLevel);