1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "MCTargetDesc/PPCPredicates.h"
17 #include "PPCCCState.h"
18 #include "PPCCallingConv.h"
19 #include "PPCFrameLowering.h"
20 #include "PPCInstrInfo.h"
21 #include "PPCMachineFunctionInfo.h"
22 #include "PPCPerfectShuffle.h"
23 #include "PPCRegisterInfo.h"
24 #include "PPCSubtarget.h"
25 #include "PPCTargetMachine.h"
26 #include "llvm/ADT/APFloat.h"
27 #include "llvm/ADT/APInt.h"
28 #include "llvm/ADT/ArrayRef.h"
29 #include "llvm/ADT/DenseMap.h"
30 #include "llvm/ADT/None.h"
31 #include "llvm/ADT/STLExtras.h"
32 #include "llvm/ADT/SmallPtrSet.h"
33 #include "llvm/ADT/SmallSet.h"
34 #include "llvm/ADT/SmallVector.h"
35 #include "llvm/ADT/Statistic.h"
36 #include "llvm/ADT/StringRef.h"
37 #include "llvm/ADT/StringSwitch.h"
38 #include "llvm/CodeGen/CallingConvLower.h"
39 #include "llvm/CodeGen/ISDOpcodes.h"
40 #include "llvm/CodeGen/MachineBasicBlock.h"
41 #include "llvm/CodeGen/MachineFrameInfo.h"
42 #include "llvm/CodeGen/MachineFunction.h"
43 #include "llvm/CodeGen/MachineInstr.h"
44 #include "llvm/CodeGen/MachineInstrBuilder.h"
45 #include "llvm/CodeGen/MachineJumpTableInfo.h"
46 #include "llvm/CodeGen/MachineLoopInfo.h"
47 #include "llvm/CodeGen/MachineMemOperand.h"
48 #include "llvm/CodeGen/MachineOperand.h"
49 #include "llvm/CodeGen/MachineRegisterInfo.h"
50 #include "llvm/CodeGen/MachineValueType.h"
51 #include "llvm/CodeGen/RuntimeLibcalls.h"
52 #include "llvm/CodeGen/SelectionDAG.h"
53 #include "llvm/CodeGen/SelectionDAGNodes.h"
54 #include "llvm/CodeGen/TargetInstrInfo.h"
55 #include "llvm/CodeGen/TargetLowering.h"
56 #include "llvm/CodeGen/TargetRegisterInfo.h"
57 #include "llvm/CodeGen/ValueTypes.h"
58 #include "llvm/IR/CallSite.h"
59 #include "llvm/IR/CallingConv.h"
60 #include "llvm/IR/Constant.h"
61 #include "llvm/IR/Constants.h"
62 #include "llvm/IR/DataLayout.h"
63 #include "llvm/IR/DebugLoc.h"
64 #include "llvm/IR/DerivedTypes.h"
65 #include "llvm/IR/Function.h"
66 #include "llvm/IR/GlobalValue.h"
67 #include "llvm/IR/IRBuilder.h"
68 #include "llvm/IR/Instructions.h"
69 #include "llvm/IR/Intrinsics.h"
70 #include "llvm/IR/Module.h"
71 #include "llvm/IR/Type.h"
72 #include "llvm/IR/Use.h"
73 #include "llvm/IR/Value.h"
74 #include "llvm/MC/MCExpr.h"
75 #include "llvm/MC/MCRegisterInfo.h"
76 #include "llvm/Support/AtomicOrdering.h"
77 #include "llvm/Support/BranchProbability.h"
78 #include "llvm/Support/Casting.h"
79 #include "llvm/Support/CodeGen.h"
80 #include "llvm/Support/CommandLine.h"
81 #include "llvm/Support/Compiler.h"
82 #include "llvm/Support/Debug.h"
83 #include "llvm/Support/ErrorHandling.h"
84 #include "llvm/Support/Format.h"
85 #include "llvm/Support/KnownBits.h"
86 #include "llvm/Support/MathExtras.h"
87 #include "llvm/Support/raw_ostream.h"
88 #include "llvm/Target/TargetMachine.h"
89 #include "llvm/Target/TargetOptions.h"
100 #define DEBUG_TYPE "ppc-lowering"
102 static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
103 cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
105 static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
106 cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
108 static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
109 cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
111 static cl::opt<bool> DisableSCO("disable-ppc-sco",
112 cl::desc("disable sibling call optimization on ppc"), cl::Hidden);
114 STATISTIC(NumTailCalls, "Number of tail calls");
115 STATISTIC(NumSiblingCalls, "Number of sibling calls");
117 static bool isNByteElemShuffleMask(ShuffleVectorSDNode *, unsigned, int);
119 // FIXME: Remove this once the bug has been fixed!
120 extern cl::opt<bool> ANDIGlueBug;
122 PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
123 const PPCSubtarget &STI)
124 : TargetLowering(TM), Subtarget(STI) {
125 // Use _setjmp/_longjmp instead of setjmp/longjmp.
126 setUseUnderscoreSetJmp(true);
127 setUseUnderscoreLongJmp(true);
129 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
130 // arguments are at least 4/8 bytes aligned.
131 bool isPPC64 = Subtarget.isPPC64();
132 setMinStackArgumentAlignment(isPPC64 ? 8:4);
134 // Set up the register classes.
135 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
136 if (!useSoftFloat()) {
137 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
138 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
141 // Match BITREVERSE to customized fast code sequence in the td file.
142 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
143 setOperationAction(ISD::BITREVERSE, MVT::i64, Legal);
145 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD.
146 for (MVT VT : MVT::integer_valuetypes()) {
147 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
148 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand);
151 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
153 // PowerPC has pre-inc load and store's.
154 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
155 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
156 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
157 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
158 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
159 setIndexedLoadAction(ISD::PRE_INC, MVT::f32, Legal);
160 setIndexedLoadAction(ISD::PRE_INC, MVT::f64, Legal);
161 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
162 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
163 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
164 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
165 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
166 setIndexedStoreAction(ISD::PRE_INC, MVT::f32, Legal);
167 setIndexedStoreAction(ISD::PRE_INC, MVT::f64, Legal);
169 if (Subtarget.useCRBits()) {
170 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
172 if (isPPC64 || Subtarget.hasFPCVT()) {
173 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
174 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1,
175 isPPC64 ? MVT::i64 : MVT::i32);
176 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
177 AddPromotedToType(ISD::UINT_TO_FP, MVT::i1,
178 isPPC64 ? MVT::i64 : MVT::i32);
180 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom);
181 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Custom);
184 // PowerPC does not support direct load/store of condition registers.
185 setOperationAction(ISD::LOAD, MVT::i1, Custom);
186 setOperationAction(ISD::STORE, MVT::i1, Custom);
188 // FIXME: Remove this once the ANDI glue bug is fixed:
190 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
192 for (MVT VT : MVT::integer_valuetypes()) {
193 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
194 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
195 setTruncStoreAction(VT, MVT::i1, Expand);
198 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass);
201 // This is used in the ppcf128->int sequence. Note it has different semantics
202 // from FP_ROUND: that rounds to nearest, this rounds to zero.
203 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
205 // We do not currently implement these libm ops for PowerPC.
206 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
207 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
208 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
209 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
210 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
211 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
213 // PowerPC has no SREM/UREM instructions unless we are on P9
214 // On P9 we may use a hardware instruction to compute the remainder.
215 // The instructions are not legalized directly because in the cases where the
216 // result of both the remainder and the division is required it is more
217 // efficient to compute the remainder from the result of the division rather
218 // than use the remainder instruction.
219 if (Subtarget.isISA3_0()) {
220 setOperationAction(ISD::SREM, MVT::i32, Custom);
221 setOperationAction(ISD::UREM, MVT::i32, Custom);
222 setOperationAction(ISD::SREM, MVT::i64, Custom);
223 setOperationAction(ISD::UREM, MVT::i64, Custom);
225 setOperationAction(ISD::SREM, MVT::i32, Expand);
226 setOperationAction(ISD::UREM, MVT::i32, Expand);
227 setOperationAction(ISD::SREM, MVT::i64, Expand);
228 setOperationAction(ISD::UREM, MVT::i64, Expand);
231 if (Subtarget.hasP9Vector()) {
232 setOperationAction(ISD::ABS, MVT::v4i32, Legal);
233 setOperationAction(ISD::ABS, MVT::v8i16, Legal);
234 setOperationAction(ISD::ABS, MVT::v16i8, Legal);
237 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
238 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
239 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
240 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
241 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
242 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
243 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
244 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
245 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
247 // We don't support sin/cos/sqrt/fmod/pow
248 setOperationAction(ISD::FSIN , MVT::f64, Expand);
249 setOperationAction(ISD::FCOS , MVT::f64, Expand);
250 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
251 setOperationAction(ISD::FREM , MVT::f64, Expand);
252 setOperationAction(ISD::FPOW , MVT::f64, Expand);
253 setOperationAction(ISD::FMA , MVT::f64, Legal);
254 setOperationAction(ISD::FSIN , MVT::f32, Expand);
255 setOperationAction(ISD::FCOS , MVT::f32, Expand);
256 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
257 setOperationAction(ISD::FREM , MVT::f32, Expand);
258 setOperationAction(ISD::FPOW , MVT::f32, Expand);
259 setOperationAction(ISD::FMA , MVT::f32, Legal);
261 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
263 // If we're enabling GP optimizations, use hardware square root
264 if (!Subtarget.hasFSQRT() &&
265 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTE() &&
267 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
269 if (!Subtarget.hasFSQRT() &&
270 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTES() &&
271 Subtarget.hasFRES()))
272 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
274 if (Subtarget.hasFCPSGN()) {
275 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal);
276 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal);
278 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
279 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
282 if (Subtarget.hasFPRND()) {
283 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
284 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
285 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
286 setOperationAction(ISD::FROUND, MVT::f64, Legal);
288 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
289 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
290 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
291 setOperationAction(ISD::FROUND, MVT::f32, Legal);
294 // PowerPC does not have BSWAP, but we can use vector BSWAP instruction xxbrd
295 // to speed up scalar BSWAP64.
296 // CTPOP or CTTZ were introduced in P8/P9 respectivelly
297 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
298 if (Subtarget.isISA3_0()) {
299 setOperationAction(ISD::BSWAP, MVT::i64 , Custom);
300 setOperationAction(ISD::CTTZ , MVT::i32 , Legal);
301 setOperationAction(ISD::CTTZ , MVT::i64 , Legal);
303 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
304 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
305 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
308 if (Subtarget.hasPOPCNTD() == PPCSubtarget::POPCNTD_Fast) {
309 setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
310 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
312 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
313 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
316 // PowerPC does not have ROTR
317 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
318 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
320 if (!Subtarget.useCRBits()) {
321 // PowerPC does not have Select
322 setOperationAction(ISD::SELECT, MVT::i32, Expand);
323 setOperationAction(ISD::SELECT, MVT::i64, Expand);
324 setOperationAction(ISD::SELECT, MVT::f32, Expand);
325 setOperationAction(ISD::SELECT, MVT::f64, Expand);
328 // PowerPC wants to turn select_cc of FP into fsel when possible.
329 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
330 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
332 // PowerPC wants to optimize integer setcc a bit
333 if (!Subtarget.useCRBits())
334 setOperationAction(ISD::SETCC, MVT::i32, Custom);
336 // PowerPC does not have BRCOND which requires SetCC
337 if (!Subtarget.useCRBits())
338 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
340 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
342 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
343 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
345 // PowerPC does not have [U|S]INT_TO_FP
346 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
347 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
349 if (Subtarget.hasDirectMove() && isPPC64) {
350 setOperationAction(ISD::BITCAST, MVT::f32, Legal);
351 setOperationAction(ISD::BITCAST, MVT::i32, Legal);
352 setOperationAction(ISD::BITCAST, MVT::i64, Legal);
353 setOperationAction(ISD::BITCAST, MVT::f64, Legal);
355 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
356 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
357 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
358 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
361 // We cannot sextinreg(i1). Expand to shifts.
362 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
364 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
365 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
366 // support continuation, user-level threading, and etc.. As a result, no
367 // other SjLj exception interfaces are implemented and please don't build
368 // your own exception handling based on them.
369 // LLVM/Clang supports zero-cost DWARF exception handling.
370 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
371 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
373 // We want to legalize GlobalAddress and ConstantPool nodes into the
374 // appropriate instructions to materialize the address.
375 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
376 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
377 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
378 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
379 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
380 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
381 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
382 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
383 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
384 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
387 setOperationAction(ISD::TRAP, MVT::Other, Legal);
389 // TRAMPOLINE is custom lowered.
390 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
391 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
393 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
394 setOperationAction(ISD::VASTART , MVT::Other, Custom);
396 if (Subtarget.isSVR4ABI()) {
398 // VAARG always uses double-word chunks, so promote anything smaller.
399 setOperationAction(ISD::VAARG, MVT::i1, Promote);
400 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
401 setOperationAction(ISD::VAARG, MVT::i8, Promote);
402 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
403 setOperationAction(ISD::VAARG, MVT::i16, Promote);
404 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
405 setOperationAction(ISD::VAARG, MVT::i32, Promote);
406 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64);
407 setOperationAction(ISD::VAARG, MVT::Other, Expand);
409 // VAARG is custom lowered with the 32-bit SVR4 ABI.
410 setOperationAction(ISD::VAARG, MVT::Other, Custom);
411 setOperationAction(ISD::VAARG, MVT::i64, Custom);
414 setOperationAction(ISD::VAARG, MVT::Other, Expand);
416 if (Subtarget.isSVR4ABI() && !isPPC64)
417 // VACOPY is custom lowered with the 32-bit SVR4 ABI.
418 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
420 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
422 // Use the default implementation.
423 setOperationAction(ISD::VAEND , MVT::Other, Expand);
424 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
425 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
426 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
427 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
428 setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, MVT::i32, Custom);
429 setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, MVT::i64, Custom);
430 setOperationAction(ISD::EH_DWARF_CFA, MVT::i32, Custom);
431 setOperationAction(ISD::EH_DWARF_CFA, MVT::i64, Custom);
433 // We want to custom lower some of our intrinsics.
434 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
436 // To handle counter-based loop conditions.
437 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom);
439 setOperationAction(ISD::INTRINSIC_VOID, MVT::i8, Custom);
440 setOperationAction(ISD::INTRINSIC_VOID, MVT::i16, Custom);
441 setOperationAction(ISD::INTRINSIC_VOID, MVT::i32, Custom);
442 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
444 // Comparisons that require checking two conditions.
445 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
446 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
447 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
448 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
449 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
450 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
451 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
452 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
453 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
454 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
455 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
456 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
458 if (Subtarget.has64BitSupport()) {
459 // They also have instructions for converting between i64 and fp.
460 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
461 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
462 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
463 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
464 // This is just the low 32 bits of a (signed) fp->i64 conversion.
465 // We cannot do this with Promote because i64 is not a legal type.
466 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
468 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64())
469 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
471 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
472 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
475 // With the instructions enabled under FPCVT, we can do everything.
476 if (Subtarget.hasFPCVT()) {
477 if (Subtarget.has64BitSupport()) {
478 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
479 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
480 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
481 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
484 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
485 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
486 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
487 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
490 if (Subtarget.use64BitRegs()) {
491 // 64-bit PowerPC implementations can support i64 types directly
492 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
493 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
494 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
495 // 64-bit PowerPC wants to expand i128 shifts itself.
496 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
497 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
498 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
500 // 32-bit PowerPC wants to expand i64 shifts itself.
501 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
502 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
503 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
506 if (Subtarget.hasAltivec()) {
507 // First set operation action for all vector types to expand. Then we
508 // will selectively turn on ones that can be effectively codegen'd.
509 for (MVT VT : MVT::vector_valuetypes()) {
510 // add/sub are legal for all supported vector VT's.
511 setOperationAction(ISD::ADD, VT, Legal);
512 setOperationAction(ISD::SUB, VT, Legal);
514 // Vector instructions introduced in P8
515 if (Subtarget.hasP8Altivec() && (VT.SimpleTy != MVT::v1i128)) {
516 setOperationAction(ISD::CTPOP, VT, Legal);
517 setOperationAction(ISD::CTLZ, VT, Legal);
520 setOperationAction(ISD::CTPOP, VT, Expand);
521 setOperationAction(ISD::CTLZ, VT, Expand);
524 // Vector instructions introduced in P9
525 if (Subtarget.hasP9Altivec() && (VT.SimpleTy != MVT::v1i128))
526 setOperationAction(ISD::CTTZ, VT, Legal);
528 setOperationAction(ISD::CTTZ, VT, Expand);
530 // We promote all shuffles to v16i8.
531 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
532 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
534 // We promote all non-typed operations to v4i32.
535 setOperationAction(ISD::AND , VT, Promote);
536 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
537 setOperationAction(ISD::OR , VT, Promote);
538 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
539 setOperationAction(ISD::XOR , VT, Promote);
540 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
541 setOperationAction(ISD::LOAD , VT, Promote);
542 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
543 setOperationAction(ISD::SELECT, VT, Promote);
544 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
545 setOperationAction(ISD::SELECT_CC, VT, Promote);
546 AddPromotedToType (ISD::SELECT_CC, VT, MVT::v4i32);
547 setOperationAction(ISD::STORE, VT, Promote);
548 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
550 // No other operations are legal.
551 setOperationAction(ISD::MUL , VT, Expand);
552 setOperationAction(ISD::SDIV, VT, Expand);
553 setOperationAction(ISD::SREM, VT, Expand);
554 setOperationAction(ISD::UDIV, VT, Expand);
555 setOperationAction(ISD::UREM, VT, Expand);
556 setOperationAction(ISD::FDIV, VT, Expand);
557 setOperationAction(ISD::FREM, VT, Expand);
558 setOperationAction(ISD::FNEG, VT, Expand);
559 setOperationAction(ISD::FSQRT, VT, Expand);
560 setOperationAction(ISD::FLOG, VT, Expand);
561 setOperationAction(ISD::FLOG10, VT, Expand);
562 setOperationAction(ISD::FLOG2, VT, Expand);
563 setOperationAction(ISD::FEXP, VT, Expand);
564 setOperationAction(ISD::FEXP2, VT, Expand);
565 setOperationAction(ISD::FSIN, VT, Expand);
566 setOperationAction(ISD::FCOS, VT, Expand);
567 setOperationAction(ISD::FABS, VT, Expand);
568 setOperationAction(ISD::FFLOOR, VT, Expand);
569 setOperationAction(ISD::FCEIL, VT, Expand);
570 setOperationAction(ISD::FTRUNC, VT, Expand);
571 setOperationAction(ISD::FRINT, VT, Expand);
572 setOperationAction(ISD::FNEARBYINT, VT, Expand);
573 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
574 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
575 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
576 setOperationAction(ISD::MULHU, VT, Expand);
577 setOperationAction(ISD::MULHS, VT, Expand);
578 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
579 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
580 setOperationAction(ISD::UDIVREM, VT, Expand);
581 setOperationAction(ISD::SDIVREM, VT, Expand);
582 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
583 setOperationAction(ISD::FPOW, VT, Expand);
584 setOperationAction(ISD::BSWAP, VT, Expand);
585 setOperationAction(ISD::VSELECT, VT, Expand);
586 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
587 setOperationAction(ISD::ROTL, VT, Expand);
588 setOperationAction(ISD::ROTR, VT, Expand);
590 for (MVT InnerVT : MVT::vector_valuetypes()) {
591 setTruncStoreAction(VT, InnerVT, Expand);
592 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
593 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
594 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
598 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
599 // with merges, splats, etc.
600 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
602 setOperationAction(ISD::AND , MVT::v4i32, Legal);
603 setOperationAction(ISD::OR , MVT::v4i32, Legal);
604 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
605 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
606 setOperationAction(ISD::SELECT, MVT::v4i32,
607 Subtarget.useCRBits() ? Legal : Expand);
608 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
609 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
610 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
611 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
612 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
613 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
614 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
615 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
616 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
618 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
619 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
620 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
621 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
623 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
624 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
626 if (TM.Options.UnsafeFPMath || Subtarget.hasVSX()) {
627 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
628 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
631 if (Subtarget.hasP8Altivec())
632 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
634 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
636 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
637 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
639 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
640 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
642 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
643 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
644 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
645 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
647 // Altivec does not contain unordered floating-point compare instructions
648 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
649 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
650 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
651 setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
653 if (Subtarget.hasVSX()) {
654 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
655 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
656 if (Subtarget.hasP8Vector()) {
657 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal);
658 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Legal);
660 if (Subtarget.hasDirectMove() && isPPC64) {
661 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Legal);
662 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Legal);
663 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Legal);
664 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i64, Legal);
665 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Legal);
666 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Legal);
667 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Legal);
668 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
670 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
672 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
673 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
674 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
675 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
676 setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
678 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
680 setOperationAction(ISD::MUL, MVT::v2f64, Legal);
681 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
683 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
684 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
686 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
687 setOperationAction(ISD::VSELECT, MVT::v8i16, Legal);
688 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
689 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
690 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
692 // Share the Altivec comparison restrictions.
693 setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand);
694 setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand);
695 setCondCodeAction(ISD::SETO, MVT::v2f64, Expand);
696 setCondCodeAction(ISD::SETONE, MVT::v2f64, Expand);
698 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
699 setOperationAction(ISD::STORE, MVT::v2f64, Legal);
701 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Legal);
703 if (Subtarget.hasP8Vector())
704 addRegisterClass(MVT::f32, &PPC::VSSRCRegClass);
706 addRegisterClass(MVT::f64, &PPC::VSFRCRegClass);
708 addRegisterClass(MVT::v4i32, &PPC::VSRCRegClass);
709 addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass);
710 addRegisterClass(MVT::v2f64, &PPC::VSRCRegClass);
712 if (Subtarget.hasP8Altivec()) {
713 setOperationAction(ISD::SHL, MVT::v2i64, Legal);
714 setOperationAction(ISD::SRA, MVT::v2i64, Legal);
715 setOperationAction(ISD::SRL, MVT::v2i64, Legal);
717 // 128 bit shifts can be accomplished via 3 instructions for SHL and
718 // SRL, but not for SRA because of the instructions available:
719 // VS{RL} and VS{RL}O. However due to direct move costs, it's not worth
721 setOperationAction(ISD::SHL, MVT::v1i128, Expand);
722 setOperationAction(ISD::SRL, MVT::v1i128, Expand);
723 setOperationAction(ISD::SRA, MVT::v1i128, Expand);
725 setOperationAction(ISD::SETCC, MVT::v2i64, Legal);
728 setOperationAction(ISD::SHL, MVT::v2i64, Expand);
729 setOperationAction(ISD::SRA, MVT::v2i64, Expand);
730 setOperationAction(ISD::SRL, MVT::v2i64, Expand);
732 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
734 // VSX v2i64 only supports non-arithmetic operations.
735 setOperationAction(ISD::ADD, MVT::v2i64, Expand);
736 setOperationAction(ISD::SUB, MVT::v2i64, Expand);
739 setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
740 AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64);
741 setOperationAction(ISD::STORE, MVT::v2i64, Promote);
742 AddPromotedToType (ISD::STORE, MVT::v2i64, MVT::v2f64);
744 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Legal);
746 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
747 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
748 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
749 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
751 // Vector operation legalization checks the result type of
752 // SIGN_EXTEND_INREG, overall legalization checks the inner type.
753 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal);
754 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
755 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
756 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
758 setOperationAction(ISD::FNEG, MVT::v4f32, Legal);
759 setOperationAction(ISD::FNEG, MVT::v2f64, Legal);
760 setOperationAction(ISD::FABS, MVT::v4f32, Legal);
761 setOperationAction(ISD::FABS, MVT::v2f64, Legal);
763 if (Subtarget.hasDirectMove())
764 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
765 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
767 addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
770 if (Subtarget.hasP8Altivec()) {
771 addRegisterClass(MVT::v2i64, &PPC::VRRCRegClass);
772 addRegisterClass(MVT::v1i128, &PPC::VRRCRegClass);
775 if (Subtarget.hasP9Vector()) {
776 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
777 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
779 // 128 bit shifts can be accomplished via 3 instructions for SHL and
780 // SRL, but not for SRA because of the instructions available:
781 // VS{RL} and VS{RL}O.
782 setOperationAction(ISD::SHL, MVT::v1i128, Legal);
783 setOperationAction(ISD::SRL, MVT::v1i128, Legal);
784 setOperationAction(ISD::SRA, MVT::v1i128, Expand);
787 if (Subtarget.hasP9Altivec()) {
788 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
789 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
793 if (Subtarget.hasQPX()) {
794 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
795 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
796 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
797 setOperationAction(ISD::FREM, MVT::v4f64, Expand);
799 setOperationAction(ISD::FCOPYSIGN, MVT::v4f64, Legal);
800 setOperationAction(ISD::FGETSIGN, MVT::v4f64, Expand);
802 setOperationAction(ISD::LOAD , MVT::v4f64, Custom);
803 setOperationAction(ISD::STORE , MVT::v4f64, Custom);
805 setTruncStoreAction(MVT::v4f64, MVT::v4f32, Custom);
806 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f32, Custom);
808 if (!Subtarget.useCRBits())
809 setOperationAction(ISD::SELECT, MVT::v4f64, Expand);
810 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
812 setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4f64, Legal);
813 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4f64, Expand);
814 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4f64, Expand);
815 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4f64, Expand);
816 setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4f64, Custom);
817 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f64, Legal);
818 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom);
820 setOperationAction(ISD::FP_TO_SINT , MVT::v4f64, Legal);
821 setOperationAction(ISD::FP_TO_UINT , MVT::v4f64, Expand);
823 setOperationAction(ISD::FP_ROUND , MVT::v4f32, Legal);
824 setOperationAction(ISD::FP_ROUND_INREG , MVT::v4f32, Expand);
825 setOperationAction(ISD::FP_EXTEND, MVT::v4f64, Legal);
827 setOperationAction(ISD::FNEG , MVT::v4f64, Legal);
828 setOperationAction(ISD::FABS , MVT::v4f64, Legal);
829 setOperationAction(ISD::FSIN , MVT::v4f64, Expand);
830 setOperationAction(ISD::FCOS , MVT::v4f64, Expand);
831 setOperationAction(ISD::FPOW , MVT::v4f64, Expand);
832 setOperationAction(ISD::FLOG , MVT::v4f64, Expand);
833 setOperationAction(ISD::FLOG2 , MVT::v4f64, Expand);
834 setOperationAction(ISD::FLOG10 , MVT::v4f64, Expand);
835 setOperationAction(ISD::FEXP , MVT::v4f64, Expand);
836 setOperationAction(ISD::FEXP2 , MVT::v4f64, Expand);
838 setOperationAction(ISD::FMINNUM, MVT::v4f64, Legal);
839 setOperationAction(ISD::FMAXNUM, MVT::v4f64, Legal);
841 setIndexedLoadAction(ISD::PRE_INC, MVT::v4f64, Legal);
842 setIndexedStoreAction(ISD::PRE_INC, MVT::v4f64, Legal);
844 addRegisterClass(MVT::v4f64, &PPC::QFRCRegClass);
846 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
847 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
848 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
849 setOperationAction(ISD::FREM, MVT::v4f32, Expand);
851 setOperationAction(ISD::FCOPYSIGN, MVT::v4f32, Legal);
852 setOperationAction(ISD::FGETSIGN, MVT::v4f32, Expand);
854 setOperationAction(ISD::LOAD , MVT::v4f32, Custom);
855 setOperationAction(ISD::STORE , MVT::v4f32, Custom);
857 if (!Subtarget.useCRBits())
858 setOperationAction(ISD::SELECT, MVT::v4f32, Expand);
859 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
861 setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4f32, Legal);
862 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4f32, Expand);
863 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4f32, Expand);
864 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4f32, Expand);
865 setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4f32, Custom);
866 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal);
867 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
869 setOperationAction(ISD::FP_TO_SINT , MVT::v4f32, Legal);
870 setOperationAction(ISD::FP_TO_UINT , MVT::v4f32, Expand);
872 setOperationAction(ISD::FNEG , MVT::v4f32, Legal);
873 setOperationAction(ISD::FABS , MVT::v4f32, Legal);
874 setOperationAction(ISD::FSIN , MVT::v4f32, Expand);
875 setOperationAction(ISD::FCOS , MVT::v4f32, Expand);
876 setOperationAction(ISD::FPOW , MVT::v4f32, Expand);
877 setOperationAction(ISD::FLOG , MVT::v4f32, Expand);
878 setOperationAction(ISD::FLOG2 , MVT::v4f32, Expand);
879 setOperationAction(ISD::FLOG10 , MVT::v4f32, Expand);
880 setOperationAction(ISD::FEXP , MVT::v4f32, Expand);
881 setOperationAction(ISD::FEXP2 , MVT::v4f32, Expand);
883 setOperationAction(ISD::FMINNUM, MVT::v4f32, Legal);
884 setOperationAction(ISD::FMAXNUM, MVT::v4f32, Legal);
886 setIndexedLoadAction(ISD::PRE_INC, MVT::v4f32, Legal);
887 setIndexedStoreAction(ISD::PRE_INC, MVT::v4f32, Legal);
889 addRegisterClass(MVT::v4f32, &PPC::QSRCRegClass);
891 setOperationAction(ISD::AND , MVT::v4i1, Legal);
892 setOperationAction(ISD::OR , MVT::v4i1, Legal);
893 setOperationAction(ISD::XOR , MVT::v4i1, Legal);
895 if (!Subtarget.useCRBits())
896 setOperationAction(ISD::SELECT, MVT::v4i1, Expand);
897 setOperationAction(ISD::VSELECT, MVT::v4i1, Legal);
899 setOperationAction(ISD::LOAD , MVT::v4i1, Custom);
900 setOperationAction(ISD::STORE , MVT::v4i1, Custom);
902 setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4i1, Custom);
903 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4i1, Expand);
904 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4i1, Expand);
905 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4i1, Expand);
906 setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4i1, Custom);
907 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i1, Expand);
908 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i1, Custom);
910 setOperationAction(ISD::SINT_TO_FP, MVT::v4i1, Custom);
911 setOperationAction(ISD::UINT_TO_FP, MVT::v4i1, Custom);
913 addRegisterClass(MVT::v4i1, &PPC::QBRCRegClass);
915 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
916 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
917 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
918 setOperationAction(ISD::FROUND, MVT::v4f64, Legal);
920 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
921 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
922 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
923 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
925 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Expand);
926 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Expand);
928 // These need to set FE_INEXACT, and so cannot be vectorized here.
929 setOperationAction(ISD::FRINT, MVT::v4f64, Expand);
930 setOperationAction(ISD::FRINT, MVT::v4f32, Expand);
932 if (TM.Options.UnsafeFPMath) {
933 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
934 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
936 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
937 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
939 setOperationAction(ISD::FDIV, MVT::v4f64, Expand);
940 setOperationAction(ISD::FSQRT, MVT::v4f64, Expand);
942 setOperationAction(ISD::FDIV, MVT::v4f32, Expand);
943 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
947 if (Subtarget.has64BitSupport())
948 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
950 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, isPPC64 ? Legal : Custom);
953 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
954 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
957 setBooleanContents(ZeroOrOneBooleanContent);
959 if (Subtarget.hasAltivec()) {
960 // Altivec instructions set fields to all zeros or all ones.
961 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
965 // These libcalls are not available in 32-bit.
966 setLibcallName(RTLIB::SHL_I128, nullptr);
967 setLibcallName(RTLIB::SRL_I128, nullptr);
968 setLibcallName(RTLIB::SRA_I128, nullptr);
971 setStackPointerRegisterToSaveRestore(isPPC64 ? PPC::X1 : PPC::R1);
973 // We have target-specific dag combine patterns for the following nodes:
974 setTargetDAGCombine(ISD::SHL);
975 setTargetDAGCombine(ISD::SRA);
976 setTargetDAGCombine(ISD::SRL);
977 setTargetDAGCombine(ISD::SINT_TO_FP);
978 setTargetDAGCombine(ISD::BUILD_VECTOR);
979 if (Subtarget.hasFPCVT())
980 setTargetDAGCombine(ISD::UINT_TO_FP);
981 setTargetDAGCombine(ISD::LOAD);
982 setTargetDAGCombine(ISD::STORE);
983 setTargetDAGCombine(ISD::BR_CC);
984 if (Subtarget.useCRBits())
985 setTargetDAGCombine(ISD::BRCOND);
986 setTargetDAGCombine(ISD::BSWAP);
987 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
988 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
989 setTargetDAGCombine(ISD::INTRINSIC_VOID);
991 setTargetDAGCombine(ISD::SIGN_EXTEND);
992 setTargetDAGCombine(ISD::ZERO_EXTEND);
993 setTargetDAGCombine(ISD::ANY_EXTEND);
995 if (Subtarget.useCRBits()) {
996 setTargetDAGCombine(ISD::TRUNCATE);
997 setTargetDAGCombine(ISD::SETCC);
998 setTargetDAGCombine(ISD::SELECT_CC);
1001 // Use reciprocal estimates.
1002 if (TM.Options.UnsafeFPMath) {
1003 setTargetDAGCombine(ISD::FDIV);
1004 setTargetDAGCombine(ISD::FSQRT);
1007 // Darwin long double math library functions have $LDBL128 appended.
1008 if (Subtarget.isDarwin()) {
1009 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
1010 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
1011 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
1012 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
1013 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
1014 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
1015 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
1016 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
1017 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
1018 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
1021 // With 32 condition bits, we don't need to sink (and duplicate) compares
1022 // aggressively in CodeGenPrep.
1023 if (Subtarget.useCRBits()) {
1024 setHasMultipleConditionRegisters();
1025 setJumpIsExpensive();
1028 setMinFunctionAlignment(2);
1029 if (Subtarget.isDarwin())
1030 setPrefFunctionAlignment(4);
1032 switch (Subtarget.getDarwinDirective()) {
1036 case PPC::DIR_E500mc:
1037 case PPC::DIR_E5500:
1040 case PPC::DIR_PWR5X:
1042 case PPC::DIR_PWR6X:
1046 setPrefFunctionAlignment(4);
1047 setPrefLoopAlignment(4);
1051 if (Subtarget.enableMachineScheduler())
1052 setSchedulingPreference(Sched::Source);
1054 setSchedulingPreference(Sched::Hybrid);
1056 computeRegisterProperties(STI.getRegisterInfo());
1058 // The Freescale cores do better with aggressive inlining of memcpy and
1059 // friends. GCC uses same threshold of 128 bytes (= 32 word stores).
1060 if (Subtarget.getDarwinDirective() == PPC::DIR_E500mc ||
1061 Subtarget.getDarwinDirective() == PPC::DIR_E5500) {
1062 MaxStoresPerMemset = 32;
1063 MaxStoresPerMemsetOptSize = 16;
1064 MaxStoresPerMemcpy = 32;
1065 MaxStoresPerMemcpyOptSize = 8;
1066 MaxStoresPerMemmove = 32;
1067 MaxStoresPerMemmoveOptSize = 8;
1068 } else if (Subtarget.getDarwinDirective() == PPC::DIR_A2) {
1069 // The A2 also benefits from (very) aggressive inlining of memcpy and
1070 // friends. The overhead of a the function call, even when warm, can be
1071 // over one hundred cycles.
1072 MaxStoresPerMemset = 128;
1073 MaxStoresPerMemcpy = 128;
1074 MaxStoresPerMemmove = 128;
1075 MaxLoadsPerMemcmp = 128;
1077 MaxLoadsPerMemcmp = 8;
1078 MaxLoadsPerMemcmpOptSize = 4;
1082 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1083 /// the desired ByVal argument alignment.
1084 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign,
1085 unsigned MaxMaxAlign) {
1086 if (MaxAlign == MaxMaxAlign)
1088 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1089 if (MaxMaxAlign >= 32 && VTy->getBitWidth() >= 256)
1091 else if (VTy->getBitWidth() >= 128 && MaxAlign < 16)
1093 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1094 unsigned EltAlign = 0;
1095 getMaxByValAlign(ATy->getElementType(), EltAlign, MaxMaxAlign);
1096 if (EltAlign > MaxAlign)
1097 MaxAlign = EltAlign;
1098 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1099 for (auto *EltTy : STy->elements()) {
1100 unsigned EltAlign = 0;
1101 getMaxByValAlign(EltTy, EltAlign, MaxMaxAlign);
1102 if (EltAlign > MaxAlign)
1103 MaxAlign = EltAlign;
1104 if (MaxAlign == MaxMaxAlign)
1110 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1111 /// function arguments in the caller parameter area.
1112 unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty,
1113 const DataLayout &DL) const {
1114 // Darwin passes everything on 4 byte boundary.
1115 if (Subtarget.isDarwin())
1118 // 16byte and wider vectors are passed on 16byte boundary.
1119 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
1120 unsigned Align = Subtarget.isPPC64() ? 8 : 4;
1121 if (Subtarget.hasAltivec() || Subtarget.hasQPX())
1122 getMaxByValAlign(Ty, Align, Subtarget.hasQPX() ? 32 : 16);
1126 bool PPCTargetLowering::useSoftFloat() const {
1127 return Subtarget.useSoftFloat();
1130 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
1131 switch ((PPCISD::NodeType)Opcode) {
1132 case PPCISD::FIRST_NUMBER: break;
1133 case PPCISD::FSEL: return "PPCISD::FSEL";
1134 case PPCISD::FCFID: return "PPCISD::FCFID";
1135 case PPCISD::FCFIDU: return "PPCISD::FCFIDU";
1136 case PPCISD::FCFIDS: return "PPCISD::FCFIDS";
1137 case PPCISD::FCFIDUS: return "PPCISD::FCFIDUS";
1138 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
1139 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
1140 case PPCISD::FCTIDUZ: return "PPCISD::FCTIDUZ";
1141 case PPCISD::FCTIWUZ: return "PPCISD::FCTIWUZ";
1142 case PPCISD::FRE: return "PPCISD::FRE";
1143 case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
1144 case PPCISD::STFIWX: return "PPCISD::STFIWX";
1145 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
1146 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
1147 case PPCISD::VPERM: return "PPCISD::VPERM";
1148 case PPCISD::XXSPLT: return "PPCISD::XXSPLT";
1149 case PPCISD::VECINSERT: return "PPCISD::VECINSERT";
1150 case PPCISD::XXREVERSE: return "PPCISD::XXREVERSE";
1151 case PPCISD::XXPERMDI: return "PPCISD::XXPERMDI";
1152 case PPCISD::VECSHL: return "PPCISD::VECSHL";
1153 case PPCISD::CMPB: return "PPCISD::CMPB";
1154 case PPCISD::Hi: return "PPCISD::Hi";
1155 case PPCISD::Lo: return "PPCISD::Lo";
1156 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
1157 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
1158 case PPCISD::DYNAREAOFFSET: return "PPCISD::DYNAREAOFFSET";
1159 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
1160 case PPCISD::SRL: return "PPCISD::SRL";
1161 case PPCISD::SRA: return "PPCISD::SRA";
1162 case PPCISD::SHL: return "PPCISD::SHL";
1163 case PPCISD::SRA_ADDZE: return "PPCISD::SRA_ADDZE";
1164 case PPCISD::CALL: return "PPCISD::CALL";
1165 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
1166 case PPCISD::MTCTR: return "PPCISD::MTCTR";
1167 case PPCISD::BCTRL: return "PPCISD::BCTRL";
1168 case PPCISD::BCTRL_LOAD_TOC: return "PPCISD::BCTRL_LOAD_TOC";
1169 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
1170 case PPCISD::READ_TIME_BASE: return "PPCISD::READ_TIME_BASE";
1171 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
1172 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
1173 case PPCISD::MFOCRF: return "PPCISD::MFOCRF";
1174 case PPCISD::MFVSR: return "PPCISD::MFVSR";
1175 case PPCISD::MTVSRA: return "PPCISD::MTVSRA";
1176 case PPCISD::MTVSRZ: return "PPCISD::MTVSRZ";
1177 case PPCISD::SINT_VEC_TO_FP: return "PPCISD::SINT_VEC_TO_FP";
1178 case PPCISD::UINT_VEC_TO_FP: return "PPCISD::UINT_VEC_TO_FP";
1179 case PPCISD::ANDIo_1_EQ_BIT: return "PPCISD::ANDIo_1_EQ_BIT";
1180 case PPCISD::ANDIo_1_GT_BIT: return "PPCISD::ANDIo_1_GT_BIT";
1181 case PPCISD::VCMP: return "PPCISD::VCMP";
1182 case PPCISD::VCMPo: return "PPCISD::VCMPo";
1183 case PPCISD::LBRX: return "PPCISD::LBRX";
1184 case PPCISD::STBRX: return "PPCISD::STBRX";
1185 case PPCISD::LFIWAX: return "PPCISD::LFIWAX";
1186 case PPCISD::LFIWZX: return "PPCISD::LFIWZX";
1187 case PPCISD::LXSIZX: return "PPCISD::LXSIZX";
1188 case PPCISD::STXSIX: return "PPCISD::STXSIX";
1189 case PPCISD::VEXTS: return "PPCISD::VEXTS";
1190 case PPCISD::SExtVElems: return "PPCISD::SExtVElems";
1191 case PPCISD::LXVD2X: return "PPCISD::LXVD2X";
1192 case PPCISD::STXVD2X: return "PPCISD::STXVD2X";
1193 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
1194 case PPCISD::BDNZ: return "PPCISD::BDNZ";
1195 case PPCISD::BDZ: return "PPCISD::BDZ";
1196 case PPCISD::MFFS: return "PPCISD::MFFS";
1197 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
1198 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
1199 case PPCISD::CR6SET: return "PPCISD::CR6SET";
1200 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
1201 case PPCISD::PPC32_GOT: return "PPCISD::PPC32_GOT";
1202 case PPCISD::PPC32_PICGOT: return "PPCISD::PPC32_PICGOT";
1203 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
1204 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
1205 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
1206 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
1207 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
1208 case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR";
1209 case PPCISD::ADDI_TLSGD_L_ADDR: return "PPCISD::ADDI_TLSGD_L_ADDR";
1210 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
1211 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
1212 case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR";
1213 case PPCISD::ADDI_TLSLD_L_ADDR: return "PPCISD::ADDI_TLSLD_L_ADDR";
1214 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
1215 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
1216 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
1217 case PPCISD::SC: return "PPCISD::SC";
1218 case PPCISD::CLRBHRB: return "PPCISD::CLRBHRB";
1219 case PPCISD::MFBHRBE: return "PPCISD::MFBHRBE";
1220 case PPCISD::RFEBB: return "PPCISD::RFEBB";
1221 case PPCISD::XXSWAPD: return "PPCISD::XXSWAPD";
1222 case PPCISD::SWAP_NO_CHAIN: return "PPCISD::SWAP_NO_CHAIN";
1223 case PPCISD::QVFPERM: return "PPCISD::QVFPERM";
1224 case PPCISD::QVGPCI: return "PPCISD::QVGPCI";
1225 case PPCISD::QVALIGNI: return "PPCISD::QVALIGNI";
1226 case PPCISD::QVESPLATI: return "PPCISD::QVESPLATI";
1227 case PPCISD::QBFLT: return "PPCISD::QBFLT";
1228 case PPCISD::QVLFSb: return "PPCISD::QVLFSb";
1233 EVT PPCTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &C,
1236 return Subtarget.useCRBits() ? MVT::i1 : MVT::i32;
1238 if (Subtarget.hasQPX())
1239 return EVT::getVectorVT(C, MVT::i1, VT.getVectorNumElements());
1241 return VT.changeVectorElementTypeToInteger();
1244 bool PPCTargetLowering::enableAggressiveFMAFusion(EVT VT) const {
1245 assert(VT.isFloatingPoint() && "Non-floating-point FMA?");
1249 //===----------------------------------------------------------------------===//
1250 // Node matching predicates, for use by the tblgen matching code.
1251 //===----------------------------------------------------------------------===//
1253 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
1254 static bool isFloatingPointZero(SDValue Op) {
1255 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
1256 return CFP->getValueAPF().isZero();
1257 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
1258 // Maybe this has already been legalized into the constant pool?
1259 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
1260 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
1261 return CFP->getValueAPF().isZero();
1266 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
1267 /// true if Op is undef or if it matches the specified value.
1268 static bool isConstantOrUndef(int Op, int Val) {
1269 return Op < 0 || Op == Val;
1272 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
1273 /// VPKUHUM instruction.
1274 /// The ShuffleKind distinguishes between big-endian operations with
1275 /// two different inputs (0), either-endian operations with two identical
1276 /// inputs (1), and little-endian operations with two different inputs (2).
1277 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1278 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
1279 SelectionDAG &DAG) {
1280 bool IsLE = DAG.getDataLayout().isLittleEndian();
1281 if (ShuffleKind == 0) {
1284 for (unsigned i = 0; i != 16; ++i)
1285 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
1287 } else if (ShuffleKind == 2) {
1290 for (unsigned i = 0; i != 16; ++i)
1291 if (!isConstantOrUndef(N->getMaskElt(i), i*2))
1293 } else if (ShuffleKind == 1) {
1294 unsigned j = IsLE ? 0 : 1;
1295 for (unsigned i = 0; i != 8; ++i)
1296 if (!isConstantOrUndef(N->getMaskElt(i), i*2+j) ||
1297 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j))
1303 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
1304 /// VPKUWUM instruction.
1305 /// The ShuffleKind distinguishes between big-endian operations with
1306 /// two different inputs (0), either-endian operations with two identical
1307 /// inputs (1), and little-endian operations with two different inputs (2).
1308 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1309 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
1310 SelectionDAG &DAG) {
1311 bool IsLE = DAG.getDataLayout().isLittleEndian();
1312 if (ShuffleKind == 0) {
1315 for (unsigned i = 0; i != 16; i += 2)
1316 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
1317 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
1319 } else if (ShuffleKind == 2) {
1322 for (unsigned i = 0; i != 16; i += 2)
1323 if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
1324 !isConstantOrUndef(N->getMaskElt(i+1), i*2+1))
1326 } else if (ShuffleKind == 1) {
1327 unsigned j = IsLE ? 0 : 2;
1328 for (unsigned i = 0; i != 8; i += 2)
1329 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
1330 !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
1331 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
1332 !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1))
1338 /// isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a
1339 /// VPKUDUM instruction, AND the VPKUDUM instruction exists for the
1340 /// current subtarget.
1342 /// The ShuffleKind distinguishes between big-endian operations with
1343 /// two different inputs (0), either-endian operations with two identical
1344 /// inputs (1), and little-endian operations with two different inputs (2).
1345 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1346 bool PPC::isVPKUDUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
1347 SelectionDAG &DAG) {
1348 const PPCSubtarget& Subtarget =
1349 static_cast<const PPCSubtarget&>(DAG.getSubtarget());
1350 if (!Subtarget.hasP8Vector())
1353 bool IsLE = DAG.getDataLayout().isLittleEndian();
1354 if (ShuffleKind == 0) {
1357 for (unsigned i = 0; i != 16; i += 4)
1358 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+4) ||
1359 !isConstantOrUndef(N->getMaskElt(i+1), i*2+5) ||
1360 !isConstantOrUndef(N->getMaskElt(i+2), i*2+6) ||
1361 !isConstantOrUndef(N->getMaskElt(i+3), i*2+7))
1363 } else if (ShuffleKind == 2) {
1366 for (unsigned i = 0; i != 16; i += 4)
1367 if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
1368 !isConstantOrUndef(N->getMaskElt(i+1), i*2+1) ||
1369 !isConstantOrUndef(N->getMaskElt(i+2), i*2+2) ||
1370 !isConstantOrUndef(N->getMaskElt(i+3), i*2+3))
1372 } else if (ShuffleKind == 1) {
1373 unsigned j = IsLE ? 0 : 4;
1374 for (unsigned i = 0; i != 8; i += 4)
1375 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
1376 !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
1377 !isConstantOrUndef(N->getMaskElt(i+2), i*2+j+2) ||
1378 !isConstantOrUndef(N->getMaskElt(i+3), i*2+j+3) ||
1379 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
1380 !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1) ||
1381 !isConstantOrUndef(N->getMaskElt(i+10), i*2+j+2) ||
1382 !isConstantOrUndef(N->getMaskElt(i+11), i*2+j+3))
1388 /// isVMerge - Common function, used to match vmrg* shuffles.
1390 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
1391 unsigned LHSStart, unsigned RHSStart) {
1392 if (N->getValueType(0) != MVT::v16i8)
1394 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
1395 "Unsupported merge size!");
1397 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
1398 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
1399 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
1400 LHSStart+j+i*UnitSize) ||
1401 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
1402 RHSStart+j+i*UnitSize))
1408 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
1409 /// a VMRGL* instruction with the specified unit size (1,2 or 4 bytes).
1410 /// The ShuffleKind distinguishes between big-endian merges with two
1411 /// different inputs (0), either-endian merges with two identical inputs (1),
1412 /// and little-endian merges with two different inputs (2). For the latter,
1413 /// the input operands are swapped (see PPCInstrAltivec.td).
1414 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
1415 unsigned ShuffleKind, SelectionDAG &DAG) {
1416 if (DAG.getDataLayout().isLittleEndian()) {
1417 if (ShuffleKind == 1) // unary
1418 return isVMerge(N, UnitSize, 0, 0);
1419 else if (ShuffleKind == 2) // swapped
1420 return isVMerge(N, UnitSize, 0, 16);
1424 if (ShuffleKind == 1) // unary
1425 return isVMerge(N, UnitSize, 8, 8);
1426 else if (ShuffleKind == 0) // normal
1427 return isVMerge(N, UnitSize, 8, 24);
1433 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
1434 /// a VMRGH* instruction with the specified unit size (1,2 or 4 bytes).
1435 /// The ShuffleKind distinguishes between big-endian merges with two
1436 /// different inputs (0), either-endian merges with two identical inputs (1),
1437 /// and little-endian merges with two different inputs (2). For the latter,
1438 /// the input operands are swapped (see PPCInstrAltivec.td).
1439 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
1440 unsigned ShuffleKind, SelectionDAG &DAG) {
1441 if (DAG.getDataLayout().isLittleEndian()) {
1442 if (ShuffleKind == 1) // unary
1443 return isVMerge(N, UnitSize, 8, 8);
1444 else if (ShuffleKind == 2) // swapped
1445 return isVMerge(N, UnitSize, 8, 24);
1449 if (ShuffleKind == 1) // unary
1450 return isVMerge(N, UnitSize, 0, 0);
1451 else if (ShuffleKind == 0) // normal
1452 return isVMerge(N, UnitSize, 0, 16);
1459 * \brief Common function used to match vmrgew and vmrgow shuffles
1461 * The indexOffset determines whether to look for even or odd words in
1462 * the shuffle mask. This is based on the of the endianness of the target
1465 * - Use offset of 0 to check for odd elements
1466 * - Use offset of 4 to check for even elements
1468 * - Use offset of 0 to check for even elements
1469 * - Use offset of 4 to check for odd elements
1470 * A detailed description of the vector element ordering for little endian and
1471 * big endian can be found at
1472 * http://www.ibm.com/developerworks/library/l-ibm-xl-c-cpp-compiler/index.html
1473 * Targeting your applications - what little endian and big endian IBM XL C/C++
1474 * compiler differences mean to you
1476 * The mask to the shuffle vector instruction specifies the indices of the
1477 * elements from the two input vectors to place in the result. The elements are
1478 * numbered in array-access order, starting with the first vector. These vectors
1479 * are always of type v16i8, thus each vector will contain 16 elements of size
1480 * 8. More info on the shuffle vector can be found in the
1481 * http://llvm.org/docs/LangRef.html#shufflevector-instruction
1482 * Language Reference.
1484 * The RHSStartValue indicates whether the same input vectors are used (unary)
1485 * or two different input vectors are used, based on the following:
1486 * - If the instruction uses the same vector for both inputs, the range of the
1487 * indices will be 0 to 15. In this case, the RHSStart value passed should
1489 * - If the instruction has two different vectors then the range of the
1490 * indices will be 0 to 31. In this case, the RHSStart value passed should
1491 * be 16 (indices 0-15 specify elements in the first vector while indices 16
1492 * to 31 specify elements in the second vector).
1494 * \param[in] N The shuffle vector SD Node to analyze
1495 * \param[in] IndexOffset Specifies whether to look for even or odd elements
1496 * \param[in] RHSStartValue Specifies the starting index for the righthand input
1497 * vector to the shuffle_vector instruction
1498 * \return true iff this shuffle vector represents an even or odd word merge
1500 static bool isVMerge(ShuffleVectorSDNode *N, unsigned IndexOffset,
1501 unsigned RHSStartValue) {
1502 if (N->getValueType(0) != MVT::v16i8)
1505 for (unsigned i = 0; i < 2; ++i)
1506 for (unsigned j = 0; j < 4; ++j)
1507 if (!isConstantOrUndef(N->getMaskElt(i*4+j),
1508 i*RHSStartValue+j+IndexOffset) ||
1509 !isConstantOrUndef(N->getMaskElt(i*4+j+8),
1510 i*RHSStartValue+j+IndexOffset+8))
1516 * \brief Determine if the specified shuffle mask is suitable for the vmrgew or
1517 * vmrgow instructions.
1519 * \param[in] N The shuffle vector SD Node to analyze
1520 * \param[in] CheckEven Check for an even merge (true) or an odd merge (false)
1521 * \param[in] ShuffleKind Identify the type of merge:
1522 * - 0 = big-endian merge with two different inputs;
1523 * - 1 = either-endian merge with two identical inputs;
1524 * - 2 = little-endian merge with two different inputs (inputs are swapped for
1525 * little-endian merges).
1526 * \param[in] DAG The current SelectionDAG
1527 * \return true iff this shuffle mask
1529 bool PPC::isVMRGEOShuffleMask(ShuffleVectorSDNode *N, bool CheckEven,
1530 unsigned ShuffleKind, SelectionDAG &DAG) {
1531 if (DAG.getDataLayout().isLittleEndian()) {
1532 unsigned indexOffset = CheckEven ? 4 : 0;
1533 if (ShuffleKind == 1) // Unary
1534 return isVMerge(N, indexOffset, 0);
1535 else if (ShuffleKind == 2) // swapped
1536 return isVMerge(N, indexOffset, 16);
1541 unsigned indexOffset = CheckEven ? 0 : 4;
1542 if (ShuffleKind == 1) // Unary
1543 return isVMerge(N, indexOffset, 0);
1544 else if (ShuffleKind == 0) // Normal
1545 return isVMerge(N, indexOffset, 16);
1552 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
1553 /// amount, otherwise return -1.
1554 /// The ShuffleKind distinguishes between big-endian operations with two
1555 /// different inputs (0), either-endian operations with two identical inputs
1556 /// (1), and little-endian operations with two different inputs (2). For the
1557 /// latter, the input operands are swapped (see PPCInstrAltivec.td).
1558 int PPC::isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind,
1559 SelectionDAG &DAG) {
1560 if (N->getValueType(0) != MVT::v16i8)
1563 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1565 // Find the first non-undef value in the shuffle mask.
1567 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
1570 if (i == 16) return -1; // all undef.
1572 // Otherwise, check to see if the rest of the elements are consecutively
1573 // numbered from this value.
1574 unsigned ShiftAmt = SVOp->getMaskElt(i);
1575 if (ShiftAmt < i) return -1;
1578 bool isLE = DAG.getDataLayout().isLittleEndian();
1580 if ((ShuffleKind == 0 && !isLE) || (ShuffleKind == 2 && isLE)) {
1581 // Check the rest of the elements to see if they are consecutive.
1582 for (++i; i != 16; ++i)
1583 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
1585 } else if (ShuffleKind == 1) {
1586 // Check the rest of the elements to see if they are consecutive.
1587 for (++i; i != 16; ++i)
1588 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
1594 ShiftAmt = 16 - ShiftAmt;
1599 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
1600 /// specifies a splat of a single element that is suitable for input to
1601 /// VSPLTB/VSPLTH/VSPLTW.
1602 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
1603 assert(N->getValueType(0) == MVT::v16i8 &&
1604 (EltSize == 1 || EltSize == 2 || EltSize == 4));
1606 // The consecutive indices need to specify an element, not part of two
1607 // different elements. So abandon ship early if this isn't the case.
1608 if (N->getMaskElt(0) % EltSize != 0)
1611 // This is a splat operation if each element of the permute is the same, and
1612 // if the value doesn't reference the second vector.
1613 unsigned ElementBase = N->getMaskElt(0);
1615 // FIXME: Handle UNDEF elements too!
1616 if (ElementBase >= 16)
1619 // Check that the indices are consecutive, in the case of a multi-byte element
1620 // splatted with a v16i8 mask.
1621 for (unsigned i = 1; i != EltSize; ++i)
1622 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
1625 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
1626 if (N->getMaskElt(i) < 0) continue;
1627 for (unsigned j = 0; j != EltSize; ++j)
1628 if (N->getMaskElt(i+j) != N->getMaskElt(j))
1634 /// Check that the mask is shuffling N byte elements. Within each N byte
1635 /// element of the mask, the indices could be either in increasing or
1636 /// decreasing order as long as they are consecutive.
1637 /// \param[in] N the shuffle vector SD Node to analyze
1638 /// \param[in] Width the element width in bytes, could be 2/4/8/16 (HalfWord/
1639 /// Word/DoubleWord/QuadWord).
1640 /// \param[in] StepLen the delta indices number among the N byte element, if
1641 /// the mask is in increasing/decreasing order then it is 1/-1.
1642 /// \return true iff the mask is shuffling N byte elements.
1643 static bool isNByteElemShuffleMask(ShuffleVectorSDNode *N, unsigned Width,
1645 assert((Width == 2 || Width == 4 || Width == 8 || Width == 16) &&
1646 "Unexpected element width.");
1647 assert((StepLen == 1 || StepLen == -1) && "Unexpected element width.");
1649 unsigned NumOfElem = 16 / Width;
1650 unsigned MaskVal[16]; // Width is never greater than 16
1651 for (unsigned i = 0; i < NumOfElem; ++i) {
1652 MaskVal[0] = N->getMaskElt(i * Width);
1653 if ((StepLen == 1) && (MaskVal[0] % Width)) {
1655 } else if ((StepLen == -1) && ((MaskVal[0] + 1) % Width)) {
1659 for (unsigned int j = 1; j < Width; ++j) {
1660 MaskVal[j] = N->getMaskElt(i * Width + j);
1661 if (MaskVal[j] != MaskVal[j-1] + StepLen) {
1670 bool PPC::isXXINSERTWMask(ShuffleVectorSDNode *N, unsigned &ShiftElts,
1671 unsigned &InsertAtByte, bool &Swap, bool IsLE) {
1672 if (!isNByteElemShuffleMask(N, 4, 1))
1675 // Now we look at mask elements 0,4,8,12
1676 unsigned M0 = N->getMaskElt(0) / 4;
1677 unsigned M1 = N->getMaskElt(4) / 4;
1678 unsigned M2 = N->getMaskElt(8) / 4;
1679 unsigned M3 = N->getMaskElt(12) / 4;
1680 unsigned LittleEndianShifts[] = { 2, 1, 0, 3 };
1681 unsigned BigEndianShifts[] = { 3, 0, 1, 2 };
1683 // Below, let H and L be arbitrary elements of the shuffle mask
1684 // where H is in the range [4,7] and L is in the range [0,3].
1685 // H, 1, 2, 3 or L, 5, 6, 7
1686 if ((M0 > 3 && M1 == 1 && M2 == 2 && M3 == 3) ||
1687 (M0 < 4 && M1 == 5 && M2 == 6 && M3 == 7)) {
1688 ShiftElts = IsLE ? LittleEndianShifts[M0 & 0x3] : BigEndianShifts[M0 & 0x3];
1689 InsertAtByte = IsLE ? 12 : 0;
1693 // 0, H, 2, 3 or 4, L, 6, 7
1694 if ((M1 > 3 && M0 == 0 && M2 == 2 && M3 == 3) ||
1695 (M1 < 4 && M0 == 4 && M2 == 6 && M3 == 7)) {
1696 ShiftElts = IsLE ? LittleEndianShifts[M1 & 0x3] : BigEndianShifts[M1 & 0x3];
1697 InsertAtByte = IsLE ? 8 : 4;
1701 // 0, 1, H, 3 or 4, 5, L, 7
1702 if ((M2 > 3 && M0 == 0 && M1 == 1 && M3 == 3) ||
1703 (M2 < 4 && M0 == 4 && M1 == 5 && M3 == 7)) {
1704 ShiftElts = IsLE ? LittleEndianShifts[M2 & 0x3] : BigEndianShifts[M2 & 0x3];
1705 InsertAtByte = IsLE ? 4 : 8;
1709 // 0, 1, 2, H or 4, 5, 6, L
1710 if ((M3 > 3 && M0 == 0 && M1 == 1 && M2 == 2) ||
1711 (M3 < 4 && M0 == 4 && M1 == 5 && M2 == 6)) {
1712 ShiftElts = IsLE ? LittleEndianShifts[M3 & 0x3] : BigEndianShifts[M3 & 0x3];
1713 InsertAtByte = IsLE ? 0 : 12;
1718 // If both vector operands for the shuffle are the same vector, the mask will
1719 // contain only elements from the first one and the second one will be undef.
1720 if (N->getOperand(1).isUndef()) {
1723 unsigned XXINSERTWSrcElem = IsLE ? 2 : 1;
1724 if (M0 == XXINSERTWSrcElem && M1 == 1 && M2 == 2 && M3 == 3) {
1725 InsertAtByte = IsLE ? 12 : 0;
1728 if (M0 == 0 && M1 == XXINSERTWSrcElem && M2 == 2 && M3 == 3) {
1729 InsertAtByte = IsLE ? 8 : 4;
1732 if (M0 == 0 && M1 == 1 && M2 == XXINSERTWSrcElem && M3 == 3) {
1733 InsertAtByte = IsLE ? 4 : 8;
1736 if (M0 == 0 && M1 == 1 && M2 == 2 && M3 == XXINSERTWSrcElem) {
1737 InsertAtByte = IsLE ? 0 : 12;
1745 bool PPC::isXXSLDWIShuffleMask(ShuffleVectorSDNode *N, unsigned &ShiftElts,
1746 bool &Swap, bool IsLE) {
1747 assert(N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8");
1748 // Ensure each byte index of the word is consecutive.
1749 if (!isNByteElemShuffleMask(N, 4, 1))
1752 // Now we look at mask elements 0,4,8,12, which are the beginning of words.
1753 unsigned M0 = N->getMaskElt(0) / 4;
1754 unsigned M1 = N->getMaskElt(4) / 4;
1755 unsigned M2 = N->getMaskElt(8) / 4;
1756 unsigned M3 = N->getMaskElt(12) / 4;
1758 // If both vector operands for the shuffle are the same vector, the mask will
1759 // contain only elements from the first one and the second one will be undef.
1760 if (N->getOperand(1).isUndef()) {
1761 assert(M0 < 4 && "Indexing into an undef vector?");
1762 if (M1 != (M0 + 1) % 4 || M2 != (M1 + 1) % 4 || M3 != (M2 + 1) % 4)
1765 ShiftElts = IsLE ? (4 - M0) % 4 : M0;
1770 // Ensure each word index of the ShuffleVector Mask is consecutive.
1771 if (M1 != (M0 + 1) % 8 || M2 != (M1 + 1) % 8 || M3 != (M2 + 1) % 8)
1775 if (M0 == 0 || M0 == 7 || M0 == 6 || M0 == 5) {
1776 // Input vectors don't need to be swapped if the leading element
1777 // of the result is one of the 3 left elements of the second vector
1778 // (or if there is no shift to be done at all).
1780 ShiftElts = (8 - M0) % 8;
1781 } else if (M0 == 4 || M0 == 3 || M0 == 2 || M0 == 1) {
1782 // Input vectors need to be swapped if the leading element
1783 // of the result is one of the 3 left elements of the first vector
1784 // (or if we're shifting by 4 - thereby simply swapping the vectors).
1786 ShiftElts = (4 - M0) % 4;
1791 if (M0 == 0 || M0 == 1 || M0 == 2 || M0 == 3) {
1792 // Input vectors don't need to be swapped if the leading element
1793 // of the result is one of the 4 elements of the first vector.
1796 } else if (M0 == 4 || M0 == 5 || M0 == 6 || M0 == 7) {
1797 // Input vectors need to be swapped if the leading element
1798 // of the result is one of the 4 elements of the right vector.
1807 bool static isXXBRShuffleMaskHelper(ShuffleVectorSDNode *N, int Width) {
1808 assert(N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8");
1810 if (!isNByteElemShuffleMask(N, Width, -1))
1813 for (int i = 0; i < 16; i += Width)
1814 if (N->getMaskElt(i) != i + Width - 1)
1820 bool PPC::isXXBRHShuffleMask(ShuffleVectorSDNode *N) {
1821 return isXXBRShuffleMaskHelper(N, 2);
1824 bool PPC::isXXBRWShuffleMask(ShuffleVectorSDNode *N) {
1825 return isXXBRShuffleMaskHelper(N, 4);
1828 bool PPC::isXXBRDShuffleMask(ShuffleVectorSDNode *N) {
1829 return isXXBRShuffleMaskHelper(N, 8);
1832 bool PPC::isXXBRQShuffleMask(ShuffleVectorSDNode *N) {
1833 return isXXBRShuffleMaskHelper(N, 16);
1836 /// Can node \p N be lowered to an XXPERMDI instruction? If so, set \p Swap
1837 /// if the inputs to the instruction should be swapped and set \p DM to the
1838 /// value for the immediate.
1839 /// Specifically, set \p Swap to true only if \p N can be lowered to XXPERMDI
1840 /// AND element 0 of the result comes from the first input (LE) or second input
1841 /// (BE). Set \p DM to the calculated result (0-3) only if \p N can be lowered.
1842 /// \return true iff the given mask of shuffle node \p N is a XXPERMDI shuffle
1844 bool PPC::isXXPERMDIShuffleMask(ShuffleVectorSDNode *N, unsigned &DM,
1845 bool &Swap, bool IsLE) {
1846 assert(N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8");
1848 // Ensure each byte index of the double word is consecutive.
1849 if (!isNByteElemShuffleMask(N, 8, 1))
1852 unsigned M0 = N->getMaskElt(0) / 8;
1853 unsigned M1 = N->getMaskElt(8) / 8;
1854 assert(((M0 | M1) < 4) && "A mask element out of bounds?");
1856 // If both vector operands for the shuffle are the same vector, the mask will
1857 // contain only elements from the first one and the second one will be undef.
1858 if (N->getOperand(1).isUndef()) {
1859 if ((M0 | M1) < 2) {
1860 DM = IsLE ? (((~M1) & 1) << 1) + ((~M0) & 1) : (M0 << 1) + (M1 & 1);
1868 if (M0 > 1 && M1 < 2) {
1870 } else if (M0 < 2 && M1 > 1) {
1877 // Note: if control flow comes here that means Swap is already set above
1878 DM = (((~M1) & 1) << 1) + ((~M0) & 1);
1881 if (M0 < 2 && M1 > 1) {
1883 } else if (M0 > 1 && M1 < 2) {
1890 // Note: if control flow comes here that means Swap is already set above
1891 DM = (M0 << 1) + (M1 & 1);
1897 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
1898 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
1899 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize,
1900 SelectionDAG &DAG) {
1901 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1902 assert(isSplatShuffleMask(SVOp, EltSize));
1903 if (DAG.getDataLayout().isLittleEndian())
1904 return (16 / EltSize) - 1 - (SVOp->getMaskElt(0) / EltSize);
1906 return SVOp->getMaskElt(0) / EltSize;
1909 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
1910 /// by using a vspltis[bhw] instruction of the specified element size, return
1911 /// the constant being splatted. The ByteSize field indicates the number of
1912 /// bytes of each element [124] -> [bhw].
1913 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
1914 SDValue OpVal(nullptr, 0);
1916 // If ByteSize of the splat is bigger than the element size of the
1917 // build_vector, then we have a case where we are checking for a splat where
1918 // multiple elements of the buildvector are folded together into a single
1919 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
1920 unsigned EltSize = 16/N->getNumOperands();
1921 if (EltSize < ByteSize) {
1922 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
1923 SDValue UniquedVals[4];
1924 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
1926 // See if all of the elements in the buildvector agree across.
1927 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1928 if (N->getOperand(i).isUndef()) continue;
1929 // If the element isn't a constant, bail fully out.
1930 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
1932 if (!UniquedVals[i&(Multiple-1)].getNode())
1933 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
1934 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
1935 return SDValue(); // no match.
1938 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
1939 // either constant or undef values that are identical for each chunk. See
1940 // if these chunks can form into a larger vspltis*.
1942 // Check to see if all of the leading entries are either 0 or -1. If
1943 // neither, then this won't fit into the immediate field.
1944 bool LeadingZero = true;
1945 bool LeadingOnes = true;
1946 for (unsigned i = 0; i != Multiple-1; ++i) {
1947 if (!UniquedVals[i].getNode()) continue; // Must have been undefs.
1949 LeadingZero &= isNullConstant(UniquedVals[i]);
1950 LeadingOnes &= isAllOnesConstant(UniquedVals[i]);
1952 // Finally, check the least significant entry.
1954 if (!UniquedVals[Multiple-1].getNode())
1955 return DAG.getTargetConstant(0, SDLoc(N), MVT::i32); // 0,0,0,undef
1956 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
1957 if (Val < 16) // 0,0,0,4 -> vspltisw(4)
1958 return DAG.getTargetConstant(Val, SDLoc(N), MVT::i32);
1961 if (!UniquedVals[Multiple-1].getNode())
1962 return DAG.getTargetConstant(~0U, SDLoc(N), MVT::i32); // -1,-1,-1,undef
1963 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
1964 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
1965 return DAG.getTargetConstant(Val, SDLoc(N), MVT::i32);
1971 // Check to see if this buildvec has a single non-undef value in its elements.
1972 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1973 if (N->getOperand(i).isUndef()) continue;
1974 if (!OpVal.getNode())
1975 OpVal = N->getOperand(i);
1976 else if (OpVal != N->getOperand(i))
1980 if (!OpVal.getNode()) return SDValue(); // All UNDEF: use implicit def.
1982 unsigned ValSizeInBytes = EltSize;
1984 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
1985 Value = CN->getZExtValue();
1986 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
1987 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
1988 Value = FloatToBits(CN->getValueAPF().convertToFloat());
1991 // If the splat value is larger than the element value, then we can never do
1992 // this splat. The only case that we could fit the replicated bits into our
1993 // immediate field for would be zero, and we prefer to use vxor for it.
1994 if (ValSizeInBytes < ByteSize) return SDValue();
1996 // If the element value is larger than the splat value, check if it consists
1997 // of a repeated bit pattern of size ByteSize.
1998 if (!APInt(ValSizeInBytes * 8, Value).isSplat(ByteSize * 8))
2001 // Properly sign extend the value.
2002 int MaskVal = SignExtend32(Value, ByteSize * 8);
2004 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
2005 if (MaskVal == 0) return SDValue();
2007 // Finally, if this value fits in a 5 bit sext field, return it
2008 if (SignExtend32<5>(MaskVal) == MaskVal)
2009 return DAG.getTargetConstant(MaskVal, SDLoc(N), MVT::i32);
2013 /// isQVALIGNIShuffleMask - If this is a qvaligni shuffle mask, return the shift
2014 /// amount, otherwise return -1.
2015 int PPC::isQVALIGNIShuffleMask(SDNode *N) {
2016 EVT VT = N->getValueType(0);
2017 if (VT != MVT::v4f64 && VT != MVT::v4f32 && VT != MVT::v4i1)
2020 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2022 // Find the first non-undef value in the shuffle mask.
2024 for (i = 0; i != 4 && SVOp->getMaskElt(i) < 0; ++i)
2027 if (i == 4) return -1; // all undef.
2029 // Otherwise, check to see if the rest of the elements are consecutively
2030 // numbered from this value.
2031 unsigned ShiftAmt = SVOp->getMaskElt(i);
2032 if (ShiftAmt < i) return -1;
2035 // Check the rest of the elements to see if they are consecutive.
2036 for (++i; i != 4; ++i)
2037 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
2043 //===----------------------------------------------------------------------===//
2044 // Addressing Mode Selection
2045 //===----------------------------------------------------------------------===//
2047 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
2048 /// or 64-bit immediate, and if the value can be accurately represented as a
2049 /// sign extension from a 16-bit value. If so, this returns true and the
2051 bool llvm::isIntS16Immediate(SDNode *N, int16_t &Imm) {
2052 if (!isa<ConstantSDNode>(N))
2055 Imm = (int16_t)cast<ConstantSDNode>(N)->getZExtValue();
2056 if (N->getValueType(0) == MVT::i32)
2057 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
2059 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
2061 bool llvm::isIntS16Immediate(SDValue Op, int16_t &Imm) {
2062 return isIntS16Immediate(Op.getNode(), Imm);
2065 /// SelectAddressRegReg - Given the specified addressed, check to see if it
2066 /// can be represented as an indexed [r+r] operation. Returns false if it
2067 /// can be more efficiently represented with [r+imm].
2068 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
2070 SelectionDAG &DAG) const {
2072 if (N.getOpcode() == ISD::ADD) {
2073 if (isIntS16Immediate(N.getOperand(1), imm))
2074 return false; // r+i
2075 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
2076 return false; // r+i
2078 Base = N.getOperand(0);
2079 Index = N.getOperand(1);
2081 } else if (N.getOpcode() == ISD::OR) {
2082 if (isIntS16Immediate(N.getOperand(1), imm))
2083 return false; // r+i can fold it if we can.
2085 // If this is an or of disjoint bitfields, we can codegen this as an add
2086 // (for better address arithmetic) if the LHS and RHS of the OR are provably
2088 KnownBits LHSKnown, RHSKnown;
2089 DAG.computeKnownBits(N.getOperand(0), LHSKnown);
2091 if (LHSKnown.Zero.getBoolValue()) {
2092 DAG.computeKnownBits(N.getOperand(1), RHSKnown);
2093 // If all of the bits are known zero on the LHS or RHS, the add won't
2095 if (~(LHSKnown.Zero | RHSKnown.Zero) == 0) {
2096 Base = N.getOperand(0);
2097 Index = N.getOperand(1);
2106 // If we happen to be doing an i64 load or store into a stack slot that has
2107 // less than a 4-byte alignment, then the frame-index elimination may need to
2108 // use an indexed load or store instruction (because the offset may not be a
2109 // multiple of 4). The extra register needed to hold the offset comes from the
2110 // register scavenger, and it is possible that the scavenger will need to use
2111 // an emergency spill slot. As a result, we need to make sure that a spill slot
2112 // is allocated when doing an i64 load/store into a less-than-4-byte-aligned
2114 static void fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT) {
2115 // FIXME: This does not handle the LWA case.
2119 // NOTE: We'll exclude negative FIs here, which come from argument
2120 // lowering, because there are no known test cases triggering this problem
2121 // using packed structures (or similar). We can remove this exclusion if
2122 // we find such a test case. The reason why this is so test-case driven is
2123 // because this entire 'fixup' is only to prevent crashes (from the
2124 // register scavenger) on not-really-valid inputs. For example, if we have:
2126 // %b = bitcast i1* %a to i64*
2127 // store i64* a, i64 b
2128 // then the store should really be marked as 'align 1', but is not. If it
2129 // were marked as 'align 1' then the indexed form would have been
2130 // instruction-selected initially, and the problem this 'fixup' is preventing
2131 // won't happen regardless.
2135 MachineFunction &MF = DAG.getMachineFunction();
2136 MachineFrameInfo &MFI = MF.getFrameInfo();
2138 unsigned Align = MFI.getObjectAlignment(FrameIdx);
2142 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2143 FuncInfo->setHasNonRISpills();
2146 /// Returns true if the address N can be represented by a base register plus
2147 /// a signed 16-bit displacement [r+imm], and if it is not better
2148 /// represented as reg+reg. If \p Alignment is non-zero, only accept
2149 /// displacements that are multiples of that value.
2150 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
2153 unsigned Alignment) const {
2154 // FIXME dl should come from parent load or store, not from address
2156 // If this can be more profitably realized as r+r, fail.
2157 if (SelectAddressRegReg(N, Disp, Base, DAG))
2160 if (N.getOpcode() == ISD::ADD) {
2162 if (isIntS16Immediate(N.getOperand(1), imm) &&
2163 (!Alignment || (imm % Alignment) == 0)) {
2164 Disp = DAG.getTargetConstant(imm, dl, N.getValueType());
2165 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
2166 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
2167 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
2169 Base = N.getOperand(0);
2171 return true; // [r+i]
2172 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
2173 // Match LOAD (ADD (X, Lo(G))).
2174 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
2175 && "Cannot handle constant offsets yet!");
2176 Disp = N.getOperand(1).getOperand(0); // The global address.
2177 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
2178 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||
2179 Disp.getOpcode() == ISD::TargetConstantPool ||
2180 Disp.getOpcode() == ISD::TargetJumpTable);
2181 Base = N.getOperand(0);
2182 return true; // [&g+r]
2184 } else if (N.getOpcode() == ISD::OR) {
2186 if (isIntS16Immediate(N.getOperand(1), imm) &&
2187 (!Alignment || (imm % Alignment) == 0)) {
2188 // If this is an or of disjoint bitfields, we can codegen this as an add
2189 // (for better address arithmetic) if the LHS and RHS of the OR are
2190 // provably disjoint.
2192 DAG.computeKnownBits(N.getOperand(0), LHSKnown);
2194 if ((LHSKnown.Zero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
2195 // If all of the bits are known zero on the LHS or RHS, the add won't
2197 if (FrameIndexSDNode *FI =
2198 dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
2199 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
2200 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
2202 Base = N.getOperand(0);
2204 Disp = DAG.getTargetConstant(imm, dl, N.getValueType());
2208 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
2209 // Loading from a constant address.
2211 // If this address fits entirely in a 16-bit sext immediate field, codegen
2214 if (isIntS16Immediate(CN, Imm) && (!Alignment || (Imm % Alignment) == 0)) {
2215 Disp = DAG.getTargetConstant(Imm, dl, CN->getValueType(0));
2216 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
2217 CN->getValueType(0));
2221 // Handle 32-bit sext immediates with LIS + addr mode.
2222 if ((CN->getValueType(0) == MVT::i32 ||
2223 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) &&
2224 (!Alignment || (CN->getZExtValue() % Alignment) == 0)) {
2225 int Addr = (int)CN->getZExtValue();
2227 // Otherwise, break this down into an LIS + disp.
2228 Disp = DAG.getTargetConstant((short)Addr, dl, MVT::i32);
2230 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, dl,
2232 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
2233 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
2238 Disp = DAG.getTargetConstant(0, dl, getPointerTy(DAG.getDataLayout()));
2239 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
2240 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
2241 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
2244 return true; // [r+0]
2247 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
2248 /// represented as an indexed [r+r] operation.
2249 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
2251 SelectionDAG &DAG) const {
2252 // Check to see if we can easily represent this as an [r+r] address. This
2253 // will fail if it thinks that the address is more profitably represented as
2254 // reg+imm, e.g. where imm = 0.
2255 if (SelectAddressRegReg(N, Base, Index, DAG))
2258 // If the address is the result of an add, we will utilize the fact that the
2259 // address calculation includes an implicit add. However, we can reduce
2260 // register pressure if we do not materialize a constant just for use as the
2261 // index register. We only get rid of the add if it is not an add of a
2262 // value and a 16-bit signed constant and both have a single use.
2264 if (N.getOpcode() == ISD::ADD &&
2265 (!isIntS16Immediate(N.getOperand(1), imm) ||
2266 !N.getOperand(1).hasOneUse() || !N.getOperand(0).hasOneUse())) {
2267 Base = N.getOperand(0);
2268 Index = N.getOperand(1);
2272 // Otherwise, do it the hard way, using R0 as the base register.
2273 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
2279 /// getPreIndexedAddressParts - returns true by value, base pointer and
2280 /// offset pointer and addressing mode by reference if the node's address
2281 /// can be legally represented as pre-indexed load / store address.
2282 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
2284 ISD::MemIndexedMode &AM,
2285 SelectionDAG &DAG) const {
2286 if (DisablePPCPreinc) return false;
2292 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
2293 Ptr = LD->getBasePtr();
2294 VT = LD->getMemoryVT();
2295 Alignment = LD->getAlignment();
2296 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
2297 Ptr = ST->getBasePtr();
2298 VT = ST->getMemoryVT();
2299 Alignment = ST->getAlignment();
2304 // PowerPC doesn't have preinc load/store instructions for vectors (except
2305 // for QPX, which does have preinc r+r forms).
2306 if (VT.isVector()) {
2307 if (!Subtarget.hasQPX() || (VT != MVT::v4f64 && VT != MVT::v4f32)) {
2309 } else if (SelectAddressRegRegOnly(Ptr, Offset, Base, DAG)) {
2315 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
2316 // Common code will reject creating a pre-inc form if the base pointer
2317 // is a frame index, or if N is a store and the base pointer is either
2318 // the same as or a predecessor of the value being stored. Check for
2319 // those situations here, and try with swapped Base/Offset instead.
2322 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
2325 SDValue Val = cast<StoreSDNode>(N)->getValue();
2326 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
2331 std::swap(Base, Offset);
2337 // LDU/STU can only handle immediates that are a multiple of 4.
2338 if (VT != MVT::i64) {
2339 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, 0))
2342 // LDU/STU need an address with at least 4-byte alignment.
2346 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, 4))
2350 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
2351 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
2352 // sext i32 to i64 when addr mode is r+i.
2353 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
2354 LD->getExtensionType() == ISD::SEXTLOAD &&
2355 isa<ConstantSDNode>(Offset))
2363 //===----------------------------------------------------------------------===//
2364 // LowerOperation implementation
2365 //===----------------------------------------------------------------------===//
2367 /// Return true if we should reference labels using a PICBase, set the HiOpFlags
2368 /// and LoOpFlags to the target MO flags.
2369 static void getLabelAccessInfo(bool IsPIC, const PPCSubtarget &Subtarget,
2370 unsigned &HiOpFlags, unsigned &LoOpFlags,
2371 const GlobalValue *GV = nullptr) {
2372 HiOpFlags = PPCII::MO_HA;
2373 LoOpFlags = PPCII::MO_LO;
2375 // Don't use the pic base if not in PIC relocation model.
2377 HiOpFlags |= PPCII::MO_PIC_FLAG;
2378 LoOpFlags |= PPCII::MO_PIC_FLAG;
2381 // If this is a reference to a global value that requires a non-lazy-ptr, make
2382 // sure that instruction lowering adds it.
2383 if (GV && Subtarget.hasLazyResolverStub(GV)) {
2384 HiOpFlags |= PPCII::MO_NLP_FLAG;
2385 LoOpFlags |= PPCII::MO_NLP_FLAG;
2387 if (GV->hasHiddenVisibility()) {
2388 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
2389 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
2394 static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
2395 SelectionDAG &DAG) {
2397 EVT PtrVT = HiPart.getValueType();
2398 SDValue Zero = DAG.getConstant(0, DL, PtrVT);
2400 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
2401 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
2403 // With PIC, the first instruction is actually "GR+hi(&G)".
2405 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
2406 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
2408 // Generate non-pic code that has direct accesses to the constant pool.
2409 // The address of the global is just (hi(&g)+lo(&g)).
2410 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
2413 static void setUsesTOCBasePtr(MachineFunction &MF) {
2414 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2415 FuncInfo->setUsesTOCBasePtr();
2418 static void setUsesTOCBasePtr(SelectionDAG &DAG) {
2419 setUsesTOCBasePtr(DAG.getMachineFunction());
2422 static SDValue getTOCEntry(SelectionDAG &DAG, const SDLoc &dl, bool Is64Bit,
2424 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
2425 SDValue Reg = Is64Bit ? DAG.getRegister(PPC::X2, VT) :
2426 DAG.getNode(PPCISD::GlobalBaseReg, dl, VT);
2428 SDValue Ops[] = { GA, Reg };
2429 return DAG.getMemIntrinsicNode(
2430 PPCISD::TOC_ENTRY, dl, DAG.getVTList(VT, MVT::Other), Ops, VT,
2431 MachinePointerInfo::getGOT(DAG.getMachineFunction()), 0,
2432 MachineMemOperand::MOLoad);
2435 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
2436 SelectionDAG &DAG) const {
2437 EVT PtrVT = Op.getValueType();
2438 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
2439 const Constant *C = CP->getConstVal();
2441 // 64-bit SVR4 ABI code is always position-independent.
2442 // The actual address of the GlobalValue is stored in the TOC.
2443 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
2444 setUsesTOCBasePtr(DAG);
2445 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0);
2446 return getTOCEntry(DAG, SDLoc(CP), true, GA);
2449 unsigned MOHiFlag, MOLoFlag;
2450 bool IsPIC = isPositionIndependent();
2451 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag);
2453 if (IsPIC && Subtarget.isSVR4ABI()) {
2454 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(),
2455 PPCII::MO_PIC_FLAG);
2456 return getTOCEntry(DAG, SDLoc(CP), false, GA);
2460 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
2462 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
2463 return LowerLabelRef(CPIHi, CPILo, IsPIC, DAG);
2466 // For 64-bit PowerPC, prefer the more compact relative encodings.
2467 // This trades 32 bits per jump table entry for one or two instructions
2468 // on the jump site.
2469 unsigned PPCTargetLowering::getJumpTableEncoding() const {
2470 if (isJumpTableRelative())
2471 return MachineJumpTableInfo::EK_LabelDifference32;
2473 return TargetLowering::getJumpTableEncoding();
2476 bool PPCTargetLowering::isJumpTableRelative() const {
2477 if (Subtarget.isPPC64())
2479 return TargetLowering::isJumpTableRelative();
2482 SDValue PPCTargetLowering::getPICJumpTableRelocBase(SDValue Table,
2483 SelectionDAG &DAG) const {
2484 if (!Subtarget.isPPC64())
2485 return TargetLowering::getPICJumpTableRelocBase(Table, DAG);
2487 switch (getTargetMachine().getCodeModel()) {
2488 case CodeModel::Small:
2489 case CodeModel::Medium:
2490 return TargetLowering::getPICJumpTableRelocBase(Table, DAG);
2492 return DAG.getNode(PPCISD::GlobalBaseReg, SDLoc(),
2493 getPointerTy(DAG.getDataLayout()));
2498 PPCTargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
2500 MCContext &Ctx) const {
2501 if (!Subtarget.isPPC64())
2502 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
2504 switch (getTargetMachine().getCodeModel()) {
2505 case CodeModel::Small:
2506 case CodeModel::Medium:
2507 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
2509 return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
2513 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
2514 EVT PtrVT = Op.getValueType();
2515 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
2517 // 64-bit SVR4 ABI code is always position-independent.
2518 // The actual address of the GlobalValue is stored in the TOC.
2519 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
2520 setUsesTOCBasePtr(DAG);
2521 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
2522 return getTOCEntry(DAG, SDLoc(JT), true, GA);
2525 unsigned MOHiFlag, MOLoFlag;
2526 bool IsPIC = isPositionIndependent();
2527 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag);
2529 if (IsPIC && Subtarget.isSVR4ABI()) {
2530 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
2531 PPCII::MO_PIC_FLAG);
2532 return getTOCEntry(DAG, SDLoc(GA), false, GA);
2535 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
2536 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
2537 return LowerLabelRef(JTIHi, JTILo, IsPIC, DAG);
2540 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
2541 SelectionDAG &DAG) const {
2542 EVT PtrVT = Op.getValueType();
2543 BlockAddressSDNode *BASDN = cast<BlockAddressSDNode>(Op);
2544 const BlockAddress *BA = BASDN->getBlockAddress();
2546 // 64-bit SVR4 ABI code is always position-independent.
2547 // The actual BlockAddress is stored in the TOC.
2548 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
2549 setUsesTOCBasePtr(DAG);
2550 SDValue GA = DAG.getTargetBlockAddress(BA, PtrVT, BASDN->getOffset());
2551 return getTOCEntry(DAG, SDLoc(BASDN), true, GA);
2554 unsigned MOHiFlag, MOLoFlag;
2555 bool IsPIC = isPositionIndependent();
2556 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag);
2557 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
2558 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
2559 return LowerLabelRef(TgtBAHi, TgtBALo, IsPIC, DAG);
2562 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
2563 SelectionDAG &DAG) const {
2564 // FIXME: TLS addresses currently use medium model code sequences,
2565 // which is the most useful form. Eventually support for small and
2566 // large models could be added if users need it, at the cost of
2567 // additional complexity.
2568 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2569 if (DAG.getTarget().Options.EmulatedTLS)
2570 return LowerToTLSEmulatedModel(GA, DAG);
2573 const GlobalValue *GV = GA->getGlobal();
2574 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2575 bool is64bit = Subtarget.isPPC64();
2576 const Module *M = DAG.getMachineFunction().getFunction().getParent();
2577 PICLevel::Level picLevel = M->getPICLevel();
2579 TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
2581 if (Model == TLSModel::LocalExec) {
2582 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2583 PPCII::MO_TPREL_HA);
2584 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2585 PPCII::MO_TPREL_LO);
2586 SDValue TLSReg = is64bit ? DAG.getRegister(PPC::X13, MVT::i64)
2587 : DAG.getRegister(PPC::R2, MVT::i32);
2589 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
2590 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
2593 if (Model == TLSModel::InitialExec) {
2594 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
2595 SDValue TGATLS = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2599 setUsesTOCBasePtr(DAG);
2600 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
2601 GOTPtr = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl,
2602 PtrVT, GOTReg, TGA);
2604 GOTPtr = DAG.getNode(PPCISD::PPC32_GOT, dl, PtrVT);
2605 SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl,
2606 PtrVT, TGA, GOTPtr);
2607 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGATLS);
2610 if (Model == TLSModel::GeneralDynamic) {
2611 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
2614 setUsesTOCBasePtr(DAG);
2615 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
2616 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
2619 if (picLevel == PICLevel::SmallPIC)
2620 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
2622 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
2624 return DAG.getNode(PPCISD::ADDI_TLSGD_L_ADDR, dl, PtrVT,
2628 if (Model == TLSModel::LocalDynamic) {
2629 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
2632 setUsesTOCBasePtr(DAG);
2633 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
2634 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
2637 if (picLevel == PICLevel::SmallPIC)
2638 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
2640 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
2642 SDValue TLSAddr = DAG.getNode(PPCISD::ADDI_TLSLD_L_ADDR, dl,
2643 PtrVT, GOTPtr, TGA, TGA);
2644 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl,
2645 PtrVT, TLSAddr, TGA);
2646 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
2649 llvm_unreachable("Unknown TLS model!");
2652 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
2653 SelectionDAG &DAG) const {
2654 EVT PtrVT = Op.getValueType();
2655 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
2657 const GlobalValue *GV = GSDN->getGlobal();
2659 // 64-bit SVR4 ABI code is always position-independent.
2660 // The actual address of the GlobalValue is stored in the TOC.
2661 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
2662 setUsesTOCBasePtr(DAG);
2663 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
2664 return getTOCEntry(DAG, DL, true, GA);
2667 unsigned MOHiFlag, MOLoFlag;
2668 bool IsPIC = isPositionIndependent();
2669 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag, GV);
2671 if (IsPIC && Subtarget.isSVR4ABI()) {
2672 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT,
2674 PPCII::MO_PIC_FLAG);
2675 return getTOCEntry(DAG, DL, false, GA);
2679 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
2681 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
2683 SDValue Ptr = LowerLabelRef(GAHi, GALo, IsPIC, DAG);
2685 // If the global reference is actually to a non-lazy-pointer, we have to do an
2686 // extra load to get the address of the global.
2687 if (MOHiFlag & PPCII::MO_NLP_FLAG)
2688 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo());
2692 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
2693 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
2696 if (Op.getValueType() == MVT::v2i64) {
2697 // When the operands themselves are v2i64 values, we need to do something
2698 // special because VSX has no underlying comparison operations for these.
2699 if (Op.getOperand(0).getValueType() == MVT::v2i64) {
2700 // Equality can be handled by casting to the legal type for Altivec
2701 // comparisons, everything else needs to be expanded.
2702 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
2703 return DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
2704 DAG.getSetCC(dl, MVT::v4i32,
2705 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0)),
2706 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(1)),
2713 // We handle most of these in the usual way.
2717 // If we're comparing for equality to zero, expose the fact that this is
2718 // implemented as a ctlz/srl pair on ppc, so that the dag combiner can
2719 // fold the new nodes.
2720 if (SDValue V = lowerCmpEqZeroToCtlzSrl(Op, DAG))
2723 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
2724 // Leave comparisons against 0 and -1 alone for now, since they're usually
2725 // optimized. FIXME: revisit this when we can custom lower all setcc
2727 if (C->isAllOnesValue() || C->isNullValue())
2731 // If we have an integer seteq/setne, turn it into a compare against zero
2732 // by xor'ing the rhs with the lhs, which is faster than setting a
2733 // condition register, reading it back out, and masking the correct bit. The
2734 // normal approach here uses sub to do this instead of xor. Using xor exposes
2735 // the result to other bit-twiddling opportunities.
2736 EVT LHSVT = Op.getOperand(0).getValueType();
2737 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
2738 EVT VT = Op.getValueType();
2739 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
2741 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, dl, LHSVT), CC);
2746 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
2747 SDNode *Node = Op.getNode();
2748 EVT VT = Node->getValueType(0);
2749 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2750 SDValue InChain = Node->getOperand(0);
2751 SDValue VAListPtr = Node->getOperand(1);
2752 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2755 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only");
2758 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
2759 VAListPtr, MachinePointerInfo(SV), MVT::i8);
2760 InChain = GprIndex.getValue(1);
2762 if (VT == MVT::i64) {
2763 // Check if GprIndex is even
2764 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
2765 DAG.getConstant(1, dl, MVT::i32));
2766 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
2767 DAG.getConstant(0, dl, MVT::i32), ISD::SETNE);
2768 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
2769 DAG.getConstant(1, dl, MVT::i32));
2770 // Align GprIndex to be even if it isn't
2771 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
2775 // fpr index is 1 byte after gpr
2776 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
2777 DAG.getConstant(1, dl, MVT::i32));
2780 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
2781 FprPtr, MachinePointerInfo(SV), MVT::i8);
2782 InChain = FprIndex.getValue(1);
2784 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
2785 DAG.getConstant(8, dl, MVT::i32));
2787 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
2788 DAG.getConstant(4, dl, MVT::i32));
2791 SDValue OverflowArea =
2792 DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr, MachinePointerInfo());
2793 InChain = OverflowArea.getValue(1);
2795 SDValue RegSaveArea =
2796 DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr, MachinePointerInfo());
2797 InChain = RegSaveArea.getValue(1);
2799 // select overflow_area if index > 8
2800 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
2801 DAG.getConstant(8, dl, MVT::i32), ISD::SETLT);
2803 // adjustment constant gpr_index * 4/8
2804 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
2805 VT.isInteger() ? GprIndex : FprIndex,
2806 DAG.getConstant(VT.isInteger() ? 4 : 8, dl,
2809 // OurReg = RegSaveArea + RegConstant
2810 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
2813 // Floating types are 32 bytes into RegSaveArea
2814 if (VT.isFloatingPoint())
2815 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
2816 DAG.getConstant(32, dl, MVT::i32));
2818 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
2819 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
2820 VT.isInteger() ? GprIndex : FprIndex,
2821 DAG.getConstant(VT == MVT::i64 ? 2 : 1, dl,
2824 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
2825 VT.isInteger() ? VAListPtr : FprPtr,
2826 MachinePointerInfo(SV), MVT::i8);
2828 // determine if we should load from reg_save_area or overflow_area
2829 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
2831 // increase overflow_area by 4/8 if gpr/fpr > 8
2832 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
2833 DAG.getConstant(VT.isInteger() ? 4 : 8,
2836 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
2839 InChain = DAG.getTruncStore(InChain, dl, OverflowArea, OverflowAreaPtr,
2840 MachinePointerInfo(), MVT::i32);
2842 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo());
2845 SDValue PPCTargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
2846 assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only");
2848 // We have to copy the entire va_list struct:
2849 // 2*sizeof(char) + 2 Byte alignment + 2*sizeof(char*) = 12 Byte
2850 return DAG.getMemcpy(Op.getOperand(0), Op,
2851 Op.getOperand(1), Op.getOperand(2),
2852 DAG.getConstant(12, SDLoc(Op), MVT::i32), 8, false, true,
2853 false, MachinePointerInfo(), MachinePointerInfo());
2856 SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
2857 SelectionDAG &DAG) const {
2858 return Op.getOperand(0);
2861 SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
2862 SelectionDAG &DAG) const {
2863 SDValue Chain = Op.getOperand(0);
2864 SDValue Trmp = Op.getOperand(1); // trampoline
2865 SDValue FPtr = Op.getOperand(2); // nested function
2866 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
2869 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2870 bool isPPC64 = (PtrVT == MVT::i64);
2871 Type *IntPtrTy = DAG.getDataLayout().getIntPtrType(*DAG.getContext());
2873 TargetLowering::ArgListTy Args;
2874 TargetLowering::ArgListEntry Entry;
2876 Entry.Ty = IntPtrTy;
2877 Entry.Node = Trmp; Args.push_back(Entry);
2879 // TrampSize == (isPPC64 ? 48 : 40);
2880 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40, dl,
2881 isPPC64 ? MVT::i64 : MVT::i32);
2882 Args.push_back(Entry);
2884 Entry.Node = FPtr; Args.push_back(Entry);
2885 Entry.Node = Nest; Args.push_back(Entry);
2887 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
2888 TargetLowering::CallLoweringInfo CLI(DAG);
2889 CLI.setDebugLoc(dl).setChain(Chain).setLibCallee(
2890 CallingConv::C, Type::getVoidTy(*DAG.getContext()),
2891 DAG.getExternalSymbol("__trampoline_setup", PtrVT), std::move(Args));
2893 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2894 return CallResult.second;
2897 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
2898 MachineFunction &MF = DAG.getMachineFunction();
2899 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2900 EVT PtrVT = getPointerTy(MF.getDataLayout());
2904 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
2905 // vastart just stores the address of the VarArgsFrameIndex slot into the
2906 // memory location argument.
2907 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2908 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2909 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
2910 MachinePointerInfo(SV));
2913 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
2914 // We suppose the given va_list is already allocated.
2917 // char gpr; /* index into the array of 8 GPRs
2918 // * stored in the register save area
2919 // * gpr=0 corresponds to r3,
2920 // * gpr=1 to r4, etc.
2922 // char fpr; /* index into the array of 8 FPRs
2923 // * stored in the register save area
2924 // * fpr=0 corresponds to f1,
2925 // * fpr=1 to f2, etc.
2927 // char *overflow_arg_area;
2928 // /* location on stack that holds
2929 // * the next overflow argument
2931 // char *reg_save_area;
2932 // /* where r3:r10 and f1:f8 (if saved)
2937 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), dl, MVT::i32);
2938 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), dl, MVT::i32);
2939 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
2941 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
2944 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
2945 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, dl, PtrVT);
2947 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
2948 SDValue ConstStackOffset = DAG.getConstant(StackOffset, dl, PtrVT);
2950 uint64_t FPROffset = 1;
2951 SDValue ConstFPROffset = DAG.getConstant(FPROffset, dl, PtrVT);
2953 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2955 // Store first byte : number of int regs
2956 SDValue firstStore =
2957 DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR, Op.getOperand(1),
2958 MachinePointerInfo(SV), MVT::i8);
2959 uint64_t nextOffset = FPROffset;
2960 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
2963 // Store second byte : number of float regs
2964 SDValue secondStore =
2965 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
2966 MachinePointerInfo(SV, nextOffset), MVT::i8);
2967 nextOffset += StackOffset;
2968 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
2970 // Store second word : arguments given on stack
2971 SDValue thirdStore = DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
2972 MachinePointerInfo(SV, nextOffset));
2973 nextOffset += FrameOffset;
2974 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
2976 // Store third word : arguments given in registers
2977 return DAG.getStore(thirdStore, dl, FR, nextPtr,
2978 MachinePointerInfo(SV, nextOffset));
2981 #include "PPCGenCallingConv.inc"
2983 // Function whose sole purpose is to kill compiler warnings
2984 // stemming from unused functions included from PPCGenCallingConv.inc.
2985 CCAssignFn *PPCTargetLowering::useFastISelCCs(unsigned Flag) const {
2986 return Flag ? CC_PPC64_ELF_FIS : RetCC_PPC64_ELF_FIS;
2989 bool llvm::CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
2990 CCValAssign::LocInfo &LocInfo,
2991 ISD::ArgFlagsTy &ArgFlags,
2996 bool llvm::CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
2998 CCValAssign::LocInfo &LocInfo,
2999 ISD::ArgFlagsTy &ArgFlags,
3001 static const MCPhysReg ArgRegs[] = {
3002 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
3003 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
3005 const unsigned NumArgRegs = array_lengthof(ArgRegs);
3007 unsigned RegNum = State.getFirstUnallocated(ArgRegs);
3009 // Skip one register if the first unallocated register has an even register
3010 // number and there are still argument registers available which have not been
3011 // allocated yet. RegNum is actually an index into ArgRegs, which means we
3012 // need to skip a register if RegNum is odd.
3013 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
3014 State.AllocateReg(ArgRegs[RegNum]);
3017 // Always return false here, as this function only makes sure that the first
3018 // unallocated register has an odd register number and does not actually
3019 // allocate a register for the current argument.
3024 llvm::CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128(unsigned &ValNo, MVT &ValVT,
3026 CCValAssign::LocInfo &LocInfo,
3027 ISD::ArgFlagsTy &ArgFlags,
3029 static const MCPhysReg ArgRegs[] = {
3030 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
3031 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
3033 const unsigned NumArgRegs = array_lengthof(ArgRegs);
3035 unsigned RegNum = State.getFirstUnallocated(ArgRegs);
3036 int RegsLeft = NumArgRegs - RegNum;
3038 // Skip if there is not enough registers left for long double type (4 gpr regs
3039 // in soft float mode) and put long double argument on the stack.
3040 if (RegNum != NumArgRegs && RegsLeft < 4) {
3041 for (int i = 0; i < RegsLeft; i++) {
3042 State.AllocateReg(ArgRegs[RegNum + i]);
3049 bool llvm::CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
3051 CCValAssign::LocInfo &LocInfo,
3052 ISD::ArgFlagsTy &ArgFlags,
3054 static const MCPhysReg ArgRegs[] = {
3055 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
3059 const unsigned NumArgRegs = array_lengthof(ArgRegs);
3061 unsigned RegNum = State.getFirstUnallocated(ArgRegs);
3063 // If there is only one Floating-point register left we need to put both f64
3064 // values of a split ppc_fp128 value on the stack.
3065 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
3066 State.AllocateReg(ArgRegs[RegNum]);
3069 // Always return false here, as this function only makes sure that the two f64
3070 // values a ppc_fp128 value is split into are both passed in registers or both
3071 // passed on the stack and does not actually allocate a register for the
3072 // current argument.
3076 /// FPR - The set of FP registers that should be allocated for arguments,
3078 static const MCPhysReg FPR[] = {PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5,
3079 PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10,
3080 PPC::F11, PPC::F12, PPC::F13};
3082 /// QFPR - The set of QPX registers that should be allocated for arguments.
3083 static const MCPhysReg QFPR[] = {
3084 PPC::QF1, PPC::QF2, PPC::QF3, PPC::QF4, PPC::QF5, PPC::QF6, PPC::QF7,
3085 PPC::QF8, PPC::QF9, PPC::QF10, PPC::QF11, PPC::QF12, PPC::QF13};
3087 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
3089 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
3090 unsigned PtrByteSize) {
3091 unsigned ArgSize = ArgVT.getStoreSize();
3092 if (Flags.isByVal())
3093 ArgSize = Flags.getByValSize();
3095 // Round up to multiples of the pointer size, except for array members,
3096 // which are always packed.
3097 if (!Flags.isInConsecutiveRegs())
3098 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3103 /// CalculateStackSlotAlignment - Calculates the alignment of this argument
3105 static unsigned CalculateStackSlotAlignment(EVT ArgVT, EVT OrigVT,
3106 ISD::ArgFlagsTy Flags,
3107 unsigned PtrByteSize) {
3108 unsigned Align = PtrByteSize;
3110 // Altivec parameters are padded to a 16 byte boundary.
3111 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
3112 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
3113 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64 ||
3114 ArgVT == MVT::v1i128)
3116 // QPX vector types stored in double-precision are padded to a 32 byte
3118 else if (ArgVT == MVT::v4f64 || ArgVT == MVT::v4i1)
3121 // ByVal parameters are aligned as requested.
3122 if (Flags.isByVal()) {
3123 unsigned BVAlign = Flags.getByValAlign();
3124 if (BVAlign > PtrByteSize) {
3125 if (BVAlign % PtrByteSize != 0)
3127 "ByVal alignment is not a multiple of the pointer size");
3133 // Array members are always packed to their original alignment.
3134 if (Flags.isInConsecutiveRegs()) {
3135 // If the array member was split into multiple registers, the first
3136 // needs to be aligned to the size of the full type. (Except for
3137 // ppcf128, which is only aligned as its f64 components.)
3138 if (Flags.isSplit() && OrigVT != MVT::ppcf128)
3139 Align = OrigVT.getStoreSize();
3141 Align = ArgVT.getStoreSize();
3147 /// CalculateStackSlotUsed - Return whether this argument will use its
3148 /// stack slot (instead of being passed in registers). ArgOffset,
3149 /// AvailableFPRs, and AvailableVRs must hold the current argument
3150 /// position, and will be updated to account for this argument.
3151 static bool CalculateStackSlotUsed(EVT ArgVT, EVT OrigVT,
3152 ISD::ArgFlagsTy Flags,
3153 unsigned PtrByteSize,
3154 unsigned LinkageSize,
3155 unsigned ParamAreaSize,
3156 unsigned &ArgOffset,
3157 unsigned &AvailableFPRs,
3158 unsigned &AvailableVRs, bool HasQPX) {
3159 bool UseMemory = false;
3161 // Respect alignment of argument on the stack.
3163 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
3164 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
3165 // If there's no space left in the argument save area, we must
3166 // use memory (this check also catches zero-sized arguments).
3167 if (ArgOffset >= LinkageSize + ParamAreaSize)
3170 // Allocate argument on the stack.
3171 ArgOffset += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
3172 if (Flags.isInConsecutiveRegsLast())
3173 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3174 // If we overran the argument save area, we must use memory
3175 // (this check catches arguments passed partially in memory)
3176 if (ArgOffset > LinkageSize + ParamAreaSize)
3179 // However, if the argument is actually passed in an FPR or a VR,
3180 // we don't use memory after all.
3181 if (!Flags.isByVal()) {
3182 if (ArgVT == MVT::f32 || ArgVT == MVT::f64 ||
3183 // QPX registers overlap with the scalar FP registers.
3184 (HasQPX && (ArgVT == MVT::v4f32 ||
3185 ArgVT == MVT::v4f64 ||
3186 ArgVT == MVT::v4i1)))
3187 if (AvailableFPRs > 0) {
3191 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
3192 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
3193 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64 ||
3194 ArgVT == MVT::v1i128)
3195 if (AvailableVRs > 0) {
3204 /// EnsureStackAlignment - Round stack frame size up from NumBytes to
3205 /// ensure minimum alignment required for target.
3206 static unsigned EnsureStackAlignment(const PPCFrameLowering *Lowering,
3207 unsigned NumBytes) {
3208 unsigned TargetAlign = Lowering->getStackAlignment();
3209 unsigned AlignMask = TargetAlign - 1;
3210 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
3214 SDValue PPCTargetLowering::LowerFormalArguments(
3215 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
3216 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
3217 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
3218 if (Subtarget.isSVR4ABI()) {
3219 if (Subtarget.isPPC64())
3220 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins,
3223 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
3226 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
3231 SDValue PPCTargetLowering::LowerFormalArguments_32SVR4(
3232 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
3233 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
3234 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
3236 // 32-bit SVR4 ABI Stack Frame Layout:
3237 // +-----------------------------------+
3238 // +--> | Back chain |
3239 // | +-----------------------------------+
3240 // | | Floating-point register save area |
3241 // | +-----------------------------------+
3242 // | | General register save area |
3243 // | +-----------------------------------+
3244 // | | CR save word |
3245 // | +-----------------------------------+
3246 // | | VRSAVE save word |
3247 // | +-----------------------------------+
3248 // | | Alignment padding |
3249 // | +-----------------------------------+
3250 // | | Vector register save area |
3251 // | +-----------------------------------+
3252 // | | Local variable space |
3253 // | +-----------------------------------+
3254 // | | Parameter list area |
3255 // | +-----------------------------------+
3256 // | | LR save word |
3257 // | +-----------------------------------+
3258 // SP--> +--- | Back chain |
3259 // +-----------------------------------+
3262 // System V Application Binary Interface PowerPC Processor Supplement
3263 // AltiVec Technology Programming Interface Manual
3265 MachineFunction &MF = DAG.getMachineFunction();
3266 MachineFrameInfo &MFI = MF.getFrameInfo();
3267 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
3269 EVT PtrVT = getPointerTy(MF.getDataLayout());
3270 // Potential tail calls could cause overwriting of argument stack slots.
3271 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
3272 (CallConv == CallingConv::Fast));
3273 unsigned PtrByteSize = 4;
3275 // Assign locations to all of the incoming arguments.
3276 SmallVector<CCValAssign, 16> ArgLocs;
3277 PPCCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
3280 // Reserve space for the linkage area on the stack.
3281 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
3282 CCInfo.AllocateStack(LinkageSize, PtrByteSize);
3284 CCInfo.PreAnalyzeFormalArguments(Ins);
3286 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
3287 CCInfo.clearWasPPCF128();
3289 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3290 CCValAssign &VA = ArgLocs[i];
3292 // Arguments stored in registers.
3293 if (VA.isRegLoc()) {
3294 const TargetRegisterClass *RC;
3295 EVT ValVT = VA.getValVT();
3297 switch (ValVT.getSimpleVT().SimpleTy) {
3299 llvm_unreachable("ValVT not supported by formal arguments Lowering");
3302 RC = &PPC::GPRCRegClass;
3305 if (Subtarget.hasP8Vector())
3306 RC = &PPC::VSSRCRegClass;
3308 RC = &PPC::F4RCRegClass;
3311 if (Subtarget.hasVSX())
3312 RC = &PPC::VSFRCRegClass;
3314 RC = &PPC::F8RCRegClass;
3319 RC = &PPC::VRRCRegClass;
3322 RC = Subtarget.hasQPX() ? &PPC::QSRCRegClass : &PPC::VRRCRegClass;
3326 RC = &PPC::VRRCRegClass;
3329 RC = &PPC::QFRCRegClass;
3332 RC = &PPC::QBRCRegClass;
3336 // Transform the arguments stored in physical registers into virtual ones.
3337 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
3338 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg,
3339 ValVT == MVT::i1 ? MVT::i32 : ValVT);
3341 if (ValVT == MVT::i1)
3342 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgValue);
3344 InVals.push_back(ArgValue);
3346 // Argument stored in memory.
3347 assert(VA.isMemLoc());
3349 unsigned ArgSize = VA.getLocVT().getStoreSize();
3350 int FI = MFI.CreateFixedObject(ArgSize, VA.getLocMemOffset(),
3353 // Create load nodes to retrieve arguments from the stack.
3354 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3356 DAG.getLoad(VA.getValVT(), dl, Chain, FIN, MachinePointerInfo()));
3360 // Assign locations to all of the incoming aggregate by value arguments.
3361 // Aggregates passed by value are stored in the local variable space of the
3362 // caller's stack frame, right above the parameter list area.
3363 SmallVector<CCValAssign, 16> ByValArgLocs;
3364 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3365 ByValArgLocs, *DAG.getContext());
3367 // Reserve stack space for the allocations in CCInfo.
3368 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
3370 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
3372 // Area that is at least reserved in the caller of this function.
3373 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
3374 MinReservedArea = std::max(MinReservedArea, LinkageSize);
3376 // Set the size that is at least reserved in caller of this function. Tail
3377 // call optimized function's reserved stack space needs to be aligned so that
3378 // taking the difference between two stack areas will result in an aligned
3381 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
3382 FuncInfo->setMinReservedArea(MinReservedArea);
3384 SmallVector<SDValue, 8> MemOps;
3386 // If the function takes variable number of arguments, make a frame index for
3387 // the start of the first vararg value... for expansion of llvm.va_start.
3389 static const MCPhysReg GPArgRegs[] = {
3390 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
3391 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
3393 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
3395 static const MCPhysReg FPArgRegs[] = {
3396 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
3399 unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
3404 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs));
3405 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs));
3407 // Make room for NumGPArgRegs and NumFPArgRegs.
3408 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
3409 NumFPArgRegs * MVT(MVT::f64).getSizeInBits()/8;
3411 FuncInfo->setVarArgsStackOffset(
3412 MFI.CreateFixedObject(PtrVT.getSizeInBits()/8,
3413 CCInfo.getNextStackOffset(), true));
3415 FuncInfo->setVarArgsFrameIndex(MFI.CreateStackObject(Depth, 8, false));
3416 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3418 // The fixed integer arguments of a variadic function are stored to the
3419 // VarArgsFrameIndex on the stack so that they may be loaded by
3420 // dereferencing the result of va_next.
3421 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
3422 // Get an existing live-in vreg, or add a new one.
3423 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
3425 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
3427 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3429 DAG.getStore(Val.getValue(1), dl, Val, FIN, MachinePointerInfo());
3430 MemOps.push_back(Store);
3431 // Increment the address by four for the next argument to store
3432 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, dl, PtrVT);
3433 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3436 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
3438 // The double arguments are stored to the VarArgsFrameIndex
3440 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
3441 // Get an existing live-in vreg, or add a new one.
3442 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
3444 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
3446 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
3448 DAG.getStore(Val.getValue(1), dl, Val, FIN, MachinePointerInfo());
3449 MemOps.push_back(Store);
3450 // Increment the address by eight for the next argument to store
3451 SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8, dl,
3453 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3457 if (!MemOps.empty())
3458 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3463 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
3464 // value to MVT::i64 and then truncate to the correct register size.
3465 SDValue PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags,
3466 EVT ObjectVT, SelectionDAG &DAG,
3468 const SDLoc &dl) const {
3470 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
3471 DAG.getValueType(ObjectVT));
3472 else if (Flags.isZExt())
3473 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
3474 DAG.getValueType(ObjectVT));
3476 return DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, ArgVal);
3479 SDValue PPCTargetLowering::LowerFormalArguments_64SVR4(
3480 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
3481 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
3482 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
3483 // TODO: add description of PPC stack frame format, or at least some docs.
3485 bool isELFv2ABI = Subtarget.isELFv2ABI();
3486 bool isLittleEndian = Subtarget.isLittleEndian();
3487 MachineFunction &MF = DAG.getMachineFunction();
3488 MachineFrameInfo &MFI = MF.getFrameInfo();
3489 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
3491 assert(!(CallConv == CallingConv::Fast && isVarArg) &&
3492 "fastcc not supported on varargs functions");
3494 EVT PtrVT = getPointerTy(MF.getDataLayout());
3495 // Potential tail calls could cause overwriting of argument stack slots.
3496 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
3497 (CallConv == CallingConv::Fast));
3498 unsigned PtrByteSize = 8;
3499 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
3501 static const MCPhysReg GPR[] = {
3502 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
3503 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
3505 static const MCPhysReg VR[] = {
3506 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
3507 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
3510 const unsigned Num_GPR_Regs = array_lengthof(GPR);
3511 const unsigned Num_FPR_Regs = useSoftFloat() ? 0 : 13;
3512 const unsigned Num_VR_Regs = array_lengthof(VR);
3513 const unsigned Num_QFPR_Regs = Num_FPR_Regs;
3515 // Do a first pass over the arguments to determine whether the ABI
3516 // guarantees that our caller has allocated the parameter save area
3517 // on its stack frame. In the ELFv1 ABI, this is always the case;
3518 // in the ELFv2 ABI, it is true if this is a vararg function or if
3519 // any parameter is located in a stack slot.
3521 bool HasParameterArea = !isELFv2ABI || isVarArg;
3522 unsigned ParamAreaSize = Num_GPR_Regs * PtrByteSize;
3523 unsigned NumBytes = LinkageSize;
3524 unsigned AvailableFPRs = Num_FPR_Regs;
3525 unsigned AvailableVRs = Num_VR_Regs;
3526 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3527 if (Ins[i].Flags.isNest())
3530 if (CalculateStackSlotUsed(Ins[i].VT, Ins[i].ArgVT, Ins[i].Flags,
3531 PtrByteSize, LinkageSize, ParamAreaSize,
3532 NumBytes, AvailableFPRs, AvailableVRs,
3533 Subtarget.hasQPX()))
3534 HasParameterArea = true;
3537 // Add DAG nodes to load the arguments or copy them out of registers. On
3538 // entry to a function on PPC, the arguments start after the linkage area,
3539 // although the first ones are often in registers.
3541 unsigned ArgOffset = LinkageSize;
3542 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
3543 unsigned &QFPR_idx = FPR_idx;
3544 SmallVector<SDValue, 8> MemOps;
3545 Function::const_arg_iterator FuncArg = MF.getFunction().arg_begin();
3546 unsigned CurArgIdx = 0;
3547 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
3549 bool needsLoad = false;
3550 EVT ObjectVT = Ins[ArgNo].VT;
3551 EVT OrigVT = Ins[ArgNo].ArgVT;
3552 unsigned ObjSize = ObjectVT.getStoreSize();
3553 unsigned ArgSize = ObjSize;
3554 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3555 if (Ins[ArgNo].isOrigArg()) {
3556 std::advance(FuncArg, Ins[ArgNo].getOrigArgIndex() - CurArgIdx);
3557 CurArgIdx = Ins[ArgNo].getOrigArgIndex();
3559 // We re-align the argument offset for each argument, except when using the
3560 // fast calling convention, when we need to make sure we do that only when
3561 // we'll actually use a stack slot.
3562 unsigned CurArgOffset, Align;
3563 auto ComputeArgOffset = [&]() {
3564 /* Respect alignment of argument on the stack. */
3565 Align = CalculateStackSlotAlignment(ObjectVT, OrigVT, Flags, PtrByteSize);
3566 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
3567 CurArgOffset = ArgOffset;
3570 if (CallConv != CallingConv::Fast) {
3573 /* Compute GPR index associated with argument offset. */
3574 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
3575 GPR_idx = std::min(GPR_idx, Num_GPR_Regs);
3578 // FIXME the codegen can be much improved in some cases.
3579 // We do not have to keep everything in memory.
3580 if (Flags.isByVal()) {
3581 assert(Ins[ArgNo].isOrigArg() && "Byval arguments cannot be implicit");
3583 if (CallConv == CallingConv::Fast)
3586 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
3587 ObjSize = Flags.getByValSize();
3588 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3589 // Empty aggregate parameters do not take up registers. Examples:
3593 // etc. However, we have to provide a place-holder in InVals, so
3594 // pretend we have an 8-byte item at the current address for that
3597 int FI = MFI.CreateFixedObject(PtrByteSize, ArgOffset, true);
3598 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3599 InVals.push_back(FIN);
3603 // Create a stack object covering all stack doublewords occupied
3604 // by the argument. If the argument is (fully or partially) on
3605 // the stack, or if the argument is fully in registers but the
3606 // caller has allocated the parameter save anyway, we can refer
3607 // directly to the caller's stack frame. Otherwise, create a
3608 // local copy in our own frame.
3610 if (HasParameterArea ||
3611 ArgSize + ArgOffset > LinkageSize + Num_GPR_Regs * PtrByteSize)
3612 FI = MFI.CreateFixedObject(ArgSize, ArgOffset, false, true);
3614 FI = MFI.CreateStackObject(ArgSize, Align, false);
3615 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3617 // Handle aggregates smaller than 8 bytes.
3618 if (ObjSize < PtrByteSize) {
3619 // The value of the object is its address, which differs from the
3620 // address of the enclosing doubleword on big-endian systems.
3622 if (!isLittleEndian) {
3623 SDValue ArgOff = DAG.getConstant(PtrByteSize - ObjSize, dl, PtrVT);
3624 Arg = DAG.getNode(ISD::ADD, dl, ArgOff.getValueType(), Arg, ArgOff);
3626 InVals.push_back(Arg);
3628 if (GPR_idx != Num_GPR_Regs) {
3629 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
3630 FuncInfo->addLiveInAttr(VReg, Flags);
3631 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3634 if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
3635 EVT ObjType = (ObjSize == 1 ? MVT::i8 :
3636 (ObjSize == 2 ? MVT::i16 : MVT::i32));
3637 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, Arg,
3638 MachinePointerInfo(&*FuncArg), ObjType);
3640 // For sizes that don't fit a truncating store (3, 5, 6, 7),
3641 // store the whole register as-is to the parameter save area
3643 Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3644 MachinePointerInfo(&*FuncArg));
3647 MemOps.push_back(Store);
3649 // Whether we copied from a register or not, advance the offset
3650 // into the parameter save area by a full doubleword.
3651 ArgOffset += PtrByteSize;
3655 // The value of the object is its address, which is the address of
3656 // its first stack doubleword.
3657 InVals.push_back(FIN);
3659 // Store whatever pieces of the object are in registers to memory.
3660 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
3661 if (GPR_idx == Num_GPR_Regs)
3664 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3665 FuncInfo->addLiveInAttr(VReg, Flags);
3666 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3669 SDValue Off = DAG.getConstant(j, dl, PtrVT);
3670 Addr = DAG.getNode(ISD::ADD, dl, Off.getValueType(), Addr, Off);
3672 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, Addr,
3673 MachinePointerInfo(&*FuncArg, j));
3674 MemOps.push_back(Store);
3677 ArgOffset += ArgSize;
3681 switch (ObjectVT.getSimpleVT().SimpleTy) {
3682 default: llvm_unreachable("Unhandled argument type!");
3686 if (Flags.isNest()) {
3687 // The 'nest' parameter, if any, is passed in R11.
3688 unsigned VReg = MF.addLiveIn(PPC::X11, &PPC::G8RCRegClass);
3689 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3691 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
3692 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
3697 // These can be scalar arguments or elements of an integer array type
3698 // passed directly. Clang may use those instead of "byval" aggregate
3699 // types to avoid forcing arguments to memory unnecessarily.
3700 if (GPR_idx != Num_GPR_Regs) {
3701 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
3702 FuncInfo->addLiveInAttr(VReg, Flags);
3703 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3705 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
3706 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
3707 // value to MVT::i64 and then truncate to the correct register size.
3708 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
3710 if (CallConv == CallingConv::Fast)
3714 ArgSize = PtrByteSize;
3716 if (CallConv != CallingConv::Fast || needsLoad)
3722 // These can be scalar arguments or elements of a float array type
3723 // passed directly. The latter are used to implement ELFv2 homogenous
3724 // float aggregates.
3725 if (FPR_idx != Num_FPR_Regs) {
3728 if (ObjectVT == MVT::f32)
3729 VReg = MF.addLiveIn(FPR[FPR_idx],
3730 Subtarget.hasP8Vector()
3731 ? &PPC::VSSRCRegClass
3732 : &PPC::F4RCRegClass);
3734 VReg = MF.addLiveIn(FPR[FPR_idx], Subtarget.hasVSX()
3735 ? &PPC::VSFRCRegClass
3736 : &PPC::F8RCRegClass);
3738 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3740 } else if (GPR_idx != Num_GPR_Regs && CallConv != CallingConv::Fast) {
3741 // FIXME: We may want to re-enable this for CallingConv::Fast on the P8
3742 // once we support fp <-> gpr moves.
3744 // This can only ever happen in the presence of f32 array types,
3745 // since otherwise we never run out of FPRs before running out
3747 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
3748 FuncInfo->addLiveInAttr(VReg, Flags);
3749 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3751 if (ObjectVT == MVT::f32) {
3752 if ((ArgOffset % PtrByteSize) == (isLittleEndian ? 4 : 0))
3753 ArgVal = DAG.getNode(ISD::SRL, dl, MVT::i64, ArgVal,
3754 DAG.getConstant(32, dl, MVT::i32));
3755 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
3758 ArgVal = DAG.getNode(ISD::BITCAST, dl, ObjectVT, ArgVal);
3760 if (CallConv == CallingConv::Fast)
3766 // When passing an array of floats, the array occupies consecutive
3767 // space in the argument area; only round up to the next doubleword
3768 // at the end of the array. Otherwise, each float takes 8 bytes.
3769 if (CallConv != CallingConv::Fast || needsLoad) {
3770 ArgSize = Flags.isInConsecutiveRegs() ? ObjSize : PtrByteSize;
3771 ArgOffset += ArgSize;
3772 if (Flags.isInConsecutiveRegsLast())
3773 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3783 if (!Subtarget.hasQPX()) {
3784 // These can be scalar arguments or elements of a vector array type
3785 // passed directly. The latter are used to implement ELFv2 homogenous
3786 // vector aggregates.
3787 if (VR_idx != Num_VR_Regs) {
3788 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
3789 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3792 if (CallConv == CallingConv::Fast)
3797 if (CallConv != CallingConv::Fast || needsLoad)
3802 assert(ObjectVT.getSimpleVT().SimpleTy == MVT::v4f32 &&
3803 "Invalid QPX parameter type");
3808 // QPX vectors are treated like their scalar floating-point subregisters
3809 // (except that they're larger).
3810 unsigned Sz = ObjectVT.getSimpleVT().SimpleTy == MVT::v4f32 ? 16 : 32;
3811 if (QFPR_idx != Num_QFPR_Regs) {
3812 const TargetRegisterClass *RC;
3813 switch (ObjectVT.getSimpleVT().SimpleTy) {
3814 case MVT::v4f64: RC = &PPC::QFRCRegClass; break;
3815 case MVT::v4f32: RC = &PPC::QSRCRegClass; break;
3816 default: RC = &PPC::QBRCRegClass; break;
3819 unsigned VReg = MF.addLiveIn(QFPR[QFPR_idx], RC);
3820 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3823 if (CallConv == CallingConv::Fast)
3827 if (CallConv != CallingConv::Fast || needsLoad)
3832 // We need to load the argument to a virtual register if we determined
3833 // above that we ran out of physical registers of the appropriate type.
3835 if (ObjSize < ArgSize && !isLittleEndian)
3836 CurArgOffset += ArgSize - ObjSize;
3837 int FI = MFI.CreateFixedObject(ObjSize, CurArgOffset, isImmutable);
3838 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3839 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo());
3842 InVals.push_back(ArgVal);
3845 // Area that is at least reserved in the caller of this function.
3846 unsigned MinReservedArea;
3847 if (HasParameterArea)
3848 MinReservedArea = std::max(ArgOffset, LinkageSize + 8 * PtrByteSize);
3850 MinReservedArea = LinkageSize;
3852 // Set the size that is at least reserved in caller of this function. Tail
3853 // call optimized functions' reserved stack space needs to be aligned so that
3854 // taking the difference between two stack areas will result in an aligned
3857 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
3858 FuncInfo->setMinReservedArea(MinReservedArea);
3860 // If the function takes variable number of arguments, make a frame index for
3861 // the start of the first vararg value... for expansion of llvm.va_start.
3863 int Depth = ArgOffset;
3865 FuncInfo->setVarArgsFrameIndex(
3866 MFI.CreateFixedObject(PtrByteSize, Depth, true));
3867 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3869 // If this function is vararg, store any remaining integer argument regs
3870 // to their spots on the stack so that they may be loaded by dereferencing
3871 // the result of va_next.
3872 for (GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
3873 GPR_idx < Num_GPR_Regs; ++GPR_idx) {
3874 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3875 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3877 DAG.getStore(Val.getValue(1), dl, Val, FIN, MachinePointerInfo());
3878 MemOps.push_back(Store);
3879 // Increment the address by four for the next argument to store
3880 SDValue PtrOff = DAG.getConstant(PtrByteSize, dl, PtrVT);
3881 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3885 if (!MemOps.empty())
3886 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3891 SDValue PPCTargetLowering::LowerFormalArguments_Darwin(
3892 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
3893 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
3894 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
3895 // TODO: add description of PPC stack frame format, or at least some docs.
3897 MachineFunction &MF = DAG.getMachineFunction();
3898 MachineFrameInfo &MFI = MF.getFrameInfo();
3899 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
3901 EVT PtrVT = getPointerTy(MF.getDataLayout());
3902 bool isPPC64 = PtrVT == MVT::i64;
3903 // Potential tail calls could cause overwriting of argument stack slots.
3904 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
3905 (CallConv == CallingConv::Fast));
3906 unsigned PtrByteSize = isPPC64 ? 8 : 4;
3907 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
3908 unsigned ArgOffset = LinkageSize;
3909 // Area that is at least reserved in caller of this function.
3910 unsigned MinReservedArea = ArgOffset;
3912 static const MCPhysReg GPR_32[] = { // 32-bit registers.
3913 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
3914 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
3916 static const MCPhysReg GPR_64[] = { // 64-bit registers.
3917 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
3918 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
3920 static const MCPhysReg VR[] = {
3921 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
3922 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
3925 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
3926 const unsigned Num_FPR_Regs = useSoftFloat() ? 0 : 13;
3927 const unsigned Num_VR_Regs = array_lengthof( VR);
3929 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
3931 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
3933 // In 32-bit non-varargs functions, the stack space for vectors is after the
3934 // stack space for non-vectors. We do not use this space unless we have
3935 // too many vectors to fit in registers, something that only occurs in
3936 // constructed examples:), but we have to walk the arglist to figure
3937 // that out...for the pathological case, compute VecArgOffset as the
3938 // start of the vector parameter area. Computing VecArgOffset is the
3939 // entire point of the following loop.
3940 unsigned VecArgOffset = ArgOffset;
3941 if (!isVarArg && !isPPC64) {
3942 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
3944 EVT ObjectVT = Ins[ArgNo].VT;
3945 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3947 if (Flags.isByVal()) {
3948 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
3949 unsigned ObjSize = Flags.getByValSize();
3951 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3952 VecArgOffset += ArgSize;
3956 switch(ObjectVT.getSimpleVT().SimpleTy) {
3957 default: llvm_unreachable("Unhandled argument type!");
3963 case MVT::i64: // PPC64
3965 // FIXME: We are guaranteed to be !isPPC64 at this point.
3966 // Does MVT::i64 apply?
3973 // Nothing to do, we're only looking at Nonvector args here.
3978 // We've found where the vector parameter area in memory is. Skip the
3979 // first 12 parameters; these don't use that memory.
3980 VecArgOffset = ((VecArgOffset+15)/16)*16;
3981 VecArgOffset += 12*16;
3983 // Add DAG nodes to load the arguments or copy them out of registers. On
3984 // entry to a function on PPC, the arguments start after the linkage area,
3985 // although the first ones are often in registers.
3987 SmallVector<SDValue, 8> MemOps;
3988 unsigned nAltivecParamsAtEnd = 0;
3989 Function::const_arg_iterator FuncArg = MF.getFunction().arg_begin();
3990 unsigned CurArgIdx = 0;
3991 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
3993 bool needsLoad = false;
3994 EVT ObjectVT = Ins[ArgNo].VT;
3995 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
3996 unsigned ArgSize = ObjSize;
3997 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3998 if (Ins[ArgNo].isOrigArg()) {
3999 std::advance(FuncArg, Ins[ArgNo].getOrigArgIndex() - CurArgIdx);
4000 CurArgIdx = Ins[ArgNo].getOrigArgIndex();
4002 unsigned CurArgOffset = ArgOffset;
4004 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
4005 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
4006 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
4007 if (isVarArg || isPPC64) {
4008 MinReservedArea = ((MinReservedArea+15)/16)*16;
4009 MinReservedArea += CalculateStackSlotSize(ObjectVT,
4012 } else nAltivecParamsAtEnd++;
4014 // Calculate min reserved area.
4015 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
4019 // FIXME the codegen can be much improved in some cases.
4020 // We do not have to keep everything in memory.
4021 if (Flags.isByVal()) {
4022 assert(Ins[ArgNo].isOrigArg() && "Byval arguments cannot be implicit");
4024 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
4025 ObjSize = Flags.getByValSize();
4026 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4027 // Objects of size 1 and 2 are right justified, everything else is
4028 // left justified. This means the memory address is adjusted forwards.
4029 if (ObjSize==1 || ObjSize==2) {
4030 CurArgOffset = CurArgOffset + (4 - ObjSize);
4032 // The value of the object is its address.
4033 int FI = MFI.CreateFixedObject(ObjSize, CurArgOffset, false, true);
4034 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4035 InVals.push_back(FIN);
4036 if (ObjSize==1 || ObjSize==2) {
4037 if (GPR_idx != Num_GPR_Regs) {
4040 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
4042 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
4043 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
4044 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16;
4046 DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
4047 MachinePointerInfo(&*FuncArg), ObjType);
4048 MemOps.push_back(Store);
4052 ArgOffset += PtrByteSize;
4056 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
4057 // Store whatever pieces of the object are in registers
4058 // to memory. ArgOffset will be the address of the beginning
4060 if (GPR_idx != Num_GPR_Regs) {
4063 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
4065 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
4066 int FI = MFI.CreateFixedObject(PtrByteSize, ArgOffset, true);
4067 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4068 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
4069 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
4070 MachinePointerInfo(&*FuncArg, j));
4071 MemOps.push_back(Store);
4073 ArgOffset += PtrByteSize;
4075 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
4082 switch (ObjectVT.getSimpleVT().SimpleTy) {
4083 default: llvm_unreachable("Unhandled argument type!");
4087 if (GPR_idx != Num_GPR_Regs) {
4088 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
4089 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
4091 if (ObjectVT == MVT::i1)
4092 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgVal);
4097 ArgSize = PtrByteSize;
4099 // All int arguments reserve stack space in the Darwin ABI.
4100 ArgOffset += PtrByteSize;
4104 case MVT::i64: // PPC64
4105 if (GPR_idx != Num_GPR_Regs) {
4106 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
4107 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
4109 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
4110 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
4111 // value to MVT::i64 and then truncate to the correct register size.
4112 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
4117 ArgSize = PtrByteSize;
4119 // All int arguments reserve stack space in the Darwin ABI.
4125 // Every 4 bytes of argument space consumes one of the GPRs available for
4126 // argument passing.
4127 if (GPR_idx != Num_GPR_Regs) {
4129 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
4132 if (FPR_idx != Num_FPR_Regs) {
4135 if (ObjectVT == MVT::f32)
4136 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
4138 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
4140 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
4146 // All FP arguments reserve stack space in the Darwin ABI.
4147 ArgOffset += isPPC64 ? 8 : ObjSize;
4153 // Note that vector arguments in registers don't reserve stack space,
4154 // except in varargs functions.
4155 if (VR_idx != Num_VR_Regs) {
4156 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
4157 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
4159 while ((ArgOffset % 16) != 0) {
4160 ArgOffset += PtrByteSize;
4161 if (GPR_idx != Num_GPR_Regs)
4165 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
4169 if (!isVarArg && !isPPC64) {
4170 // Vectors go after all the nonvectors.
4171 CurArgOffset = VecArgOffset;
4174 // Vectors are aligned.
4175 ArgOffset = ((ArgOffset+15)/16)*16;
4176 CurArgOffset = ArgOffset;
4184 // We need to load the argument to a virtual register if we determined above
4185 // that we ran out of physical registers of the appropriate type.
4187 int FI = MFI.CreateFixedObject(ObjSize,
4188 CurArgOffset + (ArgSize - ObjSize),
4190 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4191 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo());
4194 InVals.push_back(ArgVal);
4197 // Allow for Altivec parameters at the end, if needed.
4198 if (nAltivecParamsAtEnd) {
4199 MinReservedArea = ((MinReservedArea+15)/16)*16;
4200 MinReservedArea += 16*nAltivecParamsAtEnd;
4203 // Area that is at least reserved in the caller of this function.
4204 MinReservedArea = std::max(MinReservedArea, LinkageSize + 8 * PtrByteSize);
4206 // Set the size that is at least reserved in caller of this function. Tail
4207 // call optimized functions' reserved stack space needs to be aligned so that
4208 // taking the difference between two stack areas will result in an aligned
4211 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
4212 FuncInfo->setMinReservedArea(MinReservedArea);
4214 // If the function takes variable number of arguments, make a frame index for
4215 // the start of the first vararg value... for expansion of llvm.va_start.
4217 int Depth = ArgOffset;
4219 FuncInfo->setVarArgsFrameIndex(
4220 MFI.CreateFixedObject(PtrVT.getSizeInBits()/8,
4222 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
4224 // If this function is vararg, store any remaining integer argument regs
4225 // to their spots on the stack so that they may be loaded by dereferencing
4226 // the result of va_next.
4227 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
4231 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
4233 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
4235 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
4237 DAG.getStore(Val.getValue(1), dl, Val, FIN, MachinePointerInfo());
4238 MemOps.push_back(Store);
4239 // Increment the address by four for the next argument to store
4240 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, dl, PtrVT);
4241 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
4245 if (!MemOps.empty())
4246 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
4251 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
4252 /// adjusted to accommodate the arguments for the tailcall.
4253 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
4254 unsigned ParamSize) {
4256 if (!isTailCall) return 0;
4258 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
4259 unsigned CallerMinReservedArea = FI->getMinReservedArea();
4260 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
4261 // Remember only if the new adjustement is bigger.
4262 if (SPDiff < FI->getTailCallSPDelta())
4263 FI->setTailCallSPDelta(SPDiff);
4268 static bool isFunctionGlobalAddress(SDValue Callee);
4271 callsShareTOCBase(const Function *Caller, SDValue Callee,
4272 const TargetMachine &TM) {
4273 // If !G, Callee can be an external symbol.
4274 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
4278 // The medium and large code models are expected to provide a sufficiently
4279 // large TOC to provide all data addressing needs of a module with a
4280 // single TOC. Since each module will be addressed with a single TOC then we
4281 // only need to check that caller and callee don't cross dso boundaries.
4282 if (CodeModel::Medium == TM.getCodeModel() ||
4283 CodeModel::Large == TM.getCodeModel())
4284 return TM.shouldAssumeDSOLocal(*Caller->getParent(), G->getGlobal());
4286 // Otherwise we need to ensure callee and caller are in the same section,
4287 // since the linker may allocate multiple TOCs, and we don't know which
4288 // sections will belong to the same TOC base.
4290 const GlobalValue *GV = G->getGlobal();
4291 if (!GV->isStrongDefinitionForLinker())
4294 // Any explicitly-specified sections and section prefixes must also match.
4295 // Also, if we're using -ffunction-sections, then each function is always in
4296 // a different section (the same is true for COMDAT functions).
4297 if (TM.getFunctionSections() || GV->hasComdat() || Caller->hasComdat() ||
4298 GV->getSection() != Caller->getSection())
4300 if (const auto *F = dyn_cast<Function>(GV)) {
4301 if (F->getSectionPrefix() != Caller->getSectionPrefix())
4305 // If the callee might be interposed, then we can't assume the ultimate call
4306 // target will be in the same section. Even in cases where we can assume that
4307 // interposition won't happen, in any case where the linker might insert a
4308 // stub to allow for interposition, we must generate code as though
4309 // interposition might occur. To understand why this matters, consider a
4310 // situation where: a -> b -> c where the arrows indicate calls. b and c are
4311 // in the same section, but a is in a different module (i.e. has a different
4312 // TOC base pointer). If the linker allows for interposition between b and c,
4313 // then it will generate a stub for the call edge between b and c which will
4314 // save the TOC pointer into the designated stack slot allocated by b. If we
4315 // return true here, and therefore allow a tail call between b and c, that
4316 // stack slot won't exist and the b -> c stub will end up saving b'c TOC base
4317 // pointer into the stack slot allocated by a (where the a -> b stub saved
4318 // a's TOC base pointer). If we're not considering a tail call, but rather,
4319 // whether a nop is needed after the call instruction in b, because the linker
4320 // will insert a stub, it might complain about a missing nop if we omit it
4321 // (although many don't complain in this case).
4322 if (!TM.shouldAssumeDSOLocal(*Caller->getParent(), GV))
4329 needStackSlotPassParameters(const PPCSubtarget &Subtarget,
4330 const SmallVectorImpl<ISD::OutputArg> &Outs) {
4331 assert(Subtarget.isSVR4ABI() && Subtarget.isPPC64());
4333 const unsigned PtrByteSize = 8;
4334 const unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
4336 static const MCPhysReg GPR[] = {
4337 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4338 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4340 static const MCPhysReg VR[] = {
4341 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4342 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4345 const unsigned NumGPRs = array_lengthof(GPR);
4346 const unsigned NumFPRs = 13;
4347 const unsigned NumVRs = array_lengthof(VR);
4348 const unsigned ParamAreaSize = NumGPRs * PtrByteSize;
4350 unsigned NumBytes = LinkageSize;
4351 unsigned AvailableFPRs = NumFPRs;
4352 unsigned AvailableVRs = NumVRs;
4354 for (const ISD::OutputArg& Param : Outs) {
4355 if (Param.Flags.isNest()) continue;
4357 if (CalculateStackSlotUsed(Param.VT, Param.ArgVT, Param.Flags,
4358 PtrByteSize, LinkageSize, ParamAreaSize,
4359 NumBytes, AvailableFPRs, AvailableVRs,
4360 Subtarget.hasQPX()))
4367 hasSameArgumentList(const Function *CallerFn, ImmutableCallSite CS) {
4368 if (CS.arg_size() != CallerFn->arg_size())
4371 ImmutableCallSite::arg_iterator CalleeArgIter = CS.arg_begin();
4372 ImmutableCallSite::arg_iterator CalleeArgEnd = CS.arg_end();
4373 Function::const_arg_iterator CallerArgIter = CallerFn->arg_begin();
4375 for (; CalleeArgIter != CalleeArgEnd; ++CalleeArgIter, ++CallerArgIter) {
4376 const Value* CalleeArg = *CalleeArgIter;
4377 const Value* CallerArg = &(*CallerArgIter);
4378 if (CalleeArg == CallerArg)
4381 // e.g. @caller([4 x i64] %a, [4 x i64] %b) {
4382 // tail call @callee([4 x i64] undef, [4 x i64] %b)
4384 // 1st argument of callee is undef and has the same type as caller.
4385 if (CalleeArg->getType() == CallerArg->getType() &&
4386 isa<UndefValue>(CalleeArg))
4395 // Returns true if TCO is possible between the callers and callees
4396 // calling conventions.
4398 areCallingConvEligibleForTCO_64SVR4(CallingConv::ID CallerCC,
4399 CallingConv::ID CalleeCC) {
4400 // Tail or Sibling call optimization (TCO/SCO) needs callee and caller to
4401 // have the same calling convention.
4402 if (CallerCC != CalleeCC)
4405 // Tail or Sibling calls can be done with fastcc/ccc.
4406 return (CallerCC == CallingConv::Fast || CallerCC == CallingConv::C);
4410 PPCTargetLowering::IsEligibleForTailCallOptimization_64SVR4(
4412 CallingConv::ID CalleeCC,
4413 ImmutableCallSite CS,
4415 const SmallVectorImpl<ISD::OutputArg> &Outs,
4416 const SmallVectorImpl<ISD::InputArg> &Ins,
4417 SelectionDAG& DAG) const {
4418 bool TailCallOpt = getTargetMachine().Options.GuaranteedTailCallOpt;
4420 if (DisableSCO && !TailCallOpt) return false;
4422 // Variadic argument functions are not supported.
4423 if (isVarArg) return false;
4425 auto &Caller = DAG.getMachineFunction().getFunction();
4426 // Check that the calling conventions are compatible for tco.
4427 if (!areCallingConvEligibleForTCO_64SVR4(Caller.getCallingConv(), CalleeCC))
4430 // Caller contains any byval parameter is not supported.
4431 if (any_of(Ins, [](const ISD::InputArg &IA) { return IA.Flags.isByVal(); }))
4434 // Callee contains any byval parameter is not supported, too.
4435 // Note: This is a quick work around, because in some cases, e.g.
4436 // caller's stack size > callee's stack size, we are still able to apply
4437 // sibling call optimization. See: https://reviews.llvm.org/D23441#513574
4438 if (any_of(Outs, [](const ISD::OutputArg& OA) { return OA.Flags.isByVal(); }))
4441 // No TCO/SCO on indirect call because Caller have to restore its TOC
4442 if (!isFunctionGlobalAddress(Callee) &&
4443 !isa<ExternalSymbolSDNode>(Callee))
4446 // If the caller and callee potentially have different TOC bases then we
4447 // cannot tail call since we need to restore the TOC pointer after the call.
4448 // ref: https://bugzilla.mozilla.org/show_bug.cgi?id=973977
4449 if (!callsShareTOCBase(&Caller, Callee, getTargetMachine()))
4452 // TCO allows altering callee ABI, so we don't have to check further.
4453 if (CalleeCC == CallingConv::Fast && TailCallOpt)
4456 if (DisableSCO) return false;
4458 // If callee use the same argument list that caller is using, then we can
4459 // apply SCO on this case. If it is not, then we need to check if callee needs
4460 // stack for passing arguments.
4461 if (!hasSameArgumentList(&Caller, CS) &&
4462 needStackSlotPassParameters(Subtarget, Outs)) {
4469 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
4470 /// for tail call optimization. Targets which want to do tail call
4471 /// optimization should implement this function.
4473 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
4474 CallingConv::ID CalleeCC,
4476 const SmallVectorImpl<ISD::InputArg> &Ins,
4477 SelectionDAG& DAG) const {
4478 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
4481 // Variable argument functions are not supported.
4485 MachineFunction &MF = DAG.getMachineFunction();
4486 CallingConv::ID CallerCC = MF.getFunction().getCallingConv();
4487 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
4488 // Functions containing by val parameters are not supported.
4489 for (unsigned i = 0; i != Ins.size(); i++) {
4490 ISD::ArgFlagsTy Flags = Ins[i].Flags;
4491 if (Flags.isByVal()) return false;
4494 // Non-PIC/GOT tail calls are supported.
4495 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
4498 // At the moment we can only do local tail calls (in same module, hidden
4499 // or protected) if we are generating PIC.
4500 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
4501 return G->getGlobal()->hasHiddenVisibility()
4502 || G->getGlobal()->hasProtectedVisibility();
4508 /// isCallCompatibleAddress - Return the immediate to use if the specified
4509 /// 32-bit value is representable in the immediate field of a BxA instruction.
4510 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
4511 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
4512 if (!C) return nullptr;
4514 int Addr = C->getZExtValue();
4515 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
4516 SignExtend32<26>(Addr) != Addr)
4517 return nullptr; // Top 6 bits have to be sext of immediate.
4521 (int)C->getZExtValue() >> 2, SDLoc(Op),
4522 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout()))
4528 struct TailCallArgumentInfo {
4533 TailCallArgumentInfo() = default;
4536 } // end anonymous namespace
4538 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
4539 static void StoreTailCallArgumentsToStackSlot(
4540 SelectionDAG &DAG, SDValue Chain,
4541 const SmallVectorImpl<TailCallArgumentInfo> &TailCallArgs,
4542 SmallVectorImpl<SDValue> &MemOpChains, const SDLoc &dl) {
4543 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
4544 SDValue Arg = TailCallArgs[i].Arg;
4545 SDValue FIN = TailCallArgs[i].FrameIdxOp;
4546 int FI = TailCallArgs[i].FrameIdx;
4547 // Store relative to framepointer.
4548 MemOpChains.push_back(DAG.getStore(
4549 Chain, dl, Arg, FIN,
4550 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI)));
4554 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
4555 /// the appropriate stack slot for the tail call optimized function call.
4556 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG, SDValue Chain,
4557 SDValue OldRetAddr, SDValue OldFP,
4558 int SPDiff, const SDLoc &dl) {
4560 // Calculate the new stack slot for the return address.
4561 MachineFunction &MF = DAG.getMachineFunction();
4562 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
4563 const PPCFrameLowering *FL = Subtarget.getFrameLowering();
4564 bool isPPC64 = Subtarget.isPPC64();
4565 int SlotSize = isPPC64 ? 8 : 4;
4566 int NewRetAddrLoc = SPDiff + FL->getReturnSaveOffset();
4567 int NewRetAddr = MF.getFrameInfo().CreateFixedObject(SlotSize,
4568 NewRetAddrLoc, true);
4569 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
4570 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
4571 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
4572 MachinePointerInfo::getFixedStack(MF, NewRetAddr));
4574 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
4575 // slot as the FP is never overwritten.
4576 if (Subtarget.isDarwinABI()) {
4577 int NewFPLoc = SPDiff + FL->getFramePointerSaveOffset();
4578 int NewFPIdx = MF.getFrameInfo().CreateFixedObject(SlotSize, NewFPLoc,
4580 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
4581 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
4582 MachinePointerInfo::getFixedStack(
4583 DAG.getMachineFunction(), NewFPIdx));
4589 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
4590 /// the position of the argument.
4592 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
4593 SDValue Arg, int SPDiff, unsigned ArgOffset,
4594 SmallVectorImpl<TailCallArgumentInfo>& TailCallArguments) {
4595 int Offset = ArgOffset + SPDiff;
4596 uint32_t OpSize = (Arg.getValueSizeInBits() + 7) / 8;
4597 int FI = MF.getFrameInfo().CreateFixedObject(OpSize, Offset, true);
4598 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
4599 SDValue FIN = DAG.getFrameIndex(FI, VT);
4600 TailCallArgumentInfo Info;
4602 Info.FrameIdxOp = FIN;
4604 TailCallArguments.push_back(Info);
4607 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
4608 /// stack slot. Returns the chain as result and the loaded frame pointers in
4609 /// LROpOut/FPOpout. Used when tail calling.
4610 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(
4611 SelectionDAG &DAG, int SPDiff, SDValue Chain, SDValue &LROpOut,
4612 SDValue &FPOpOut, const SDLoc &dl) const {
4614 // Load the LR and FP stack slot for later adjusting.
4615 EVT VT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
4616 LROpOut = getReturnAddrFrameIndex(DAG);
4617 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo());
4618 Chain = SDValue(LROpOut.getNode(), 1);
4620 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
4621 // slot as the FP is never overwritten.
4622 if (Subtarget.isDarwinABI()) {
4623 FPOpOut = getFramePointerFrameIndex(DAG);
4624 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo());
4625 Chain = SDValue(FPOpOut.getNode(), 1);
4631 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
4632 /// by "Src" to address "Dst" of size "Size". Alignment information is
4633 /// specified by the specific parameter attribute. The copy will be passed as
4634 /// a byval function parameter.
4635 /// Sometimes what we are copying is the end of a larger object, the part that
4636 /// does not fit in registers.
4637 static SDValue CreateCopyOfByValArgument(SDValue Src, SDValue Dst,
4638 SDValue Chain, ISD::ArgFlagsTy Flags,
4639 SelectionDAG &DAG, const SDLoc &dl) {
4640 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
4641 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
4642 false, false, false, MachinePointerInfo(),
4643 MachinePointerInfo());
4646 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
4648 static void LowerMemOpCallTo(
4649 SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, SDValue Arg,
4650 SDValue PtrOff, int SPDiff, unsigned ArgOffset, bool isPPC64,
4651 bool isTailCall, bool isVector, SmallVectorImpl<SDValue> &MemOpChains,
4652 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments, const SDLoc &dl) {
4653 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
4658 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4660 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4661 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4662 DAG.getConstant(ArgOffset, dl, PtrVT));
4664 MemOpChains.push_back(
4665 DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo()));
4666 // Calculate and remember argument location.
4667 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
4672 PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
4673 const SDLoc &dl, int SPDiff, unsigned NumBytes, SDValue LROp,
4675 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments) {
4676 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
4677 // might overwrite each other in case of tail call optimization.
4678 SmallVector<SDValue, 8> MemOpChains2;
4679 // Do not flag preceding copytoreg stuff together with the following stuff.
4681 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
4683 if (!MemOpChains2.empty())
4684 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
4686 // Store the return address to the appropriate stack slot.
4687 Chain = EmitTailCallStoreFPAndRetAddr(DAG, Chain, LROp, FPOp, SPDiff, dl);
4689 // Emit callseq_end just before tailcall node.
4690 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
4691 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
4692 InFlag = Chain.getValue(1);
4695 // Is this global address that of a function that can be called by name? (as
4696 // opposed to something that must hold a descriptor for an indirect call).
4697 static bool isFunctionGlobalAddress(SDValue Callee) {
4698 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
4699 if (Callee.getOpcode() == ISD::GlobalTLSAddress ||
4700 Callee.getOpcode() == ISD::TargetGlobalTLSAddress)
4703 return G->getGlobal()->getValueType()->isFunctionTy();
4710 PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag, SDValue &Chain,
4711 SDValue CallSeqStart, const SDLoc &dl, int SPDiff, bool isTailCall,
4712 bool isPatchPoint, bool hasNest,
4713 SmallVectorImpl<std::pair<unsigned, SDValue>> &RegsToPass,
4714 SmallVectorImpl<SDValue> &Ops, std::vector<EVT> &NodeTys,
4715 ImmutableCallSite CS, const PPCSubtarget &Subtarget) {
4716 bool isPPC64 = Subtarget.isPPC64();
4717 bool isSVR4ABI = Subtarget.isSVR4ABI();
4718 bool isELFv2ABI = Subtarget.isELFv2ABI();
4720 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
4721 NodeTys.push_back(MVT::Other); // Returns a chain
4722 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
4724 unsigned CallOpc = PPCISD::CALL;
4726 bool needIndirectCall = true;
4727 if (!isSVR4ABI || !isPPC64)
4728 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) {
4729 // If this is an absolute destination address, use the munged value.
4730 Callee = SDValue(Dest, 0);
4731 needIndirectCall = false;
4734 // PC-relative references to external symbols should go through $stub, unless
4735 // we're building with the leopard linker or later, which automatically
4736 // synthesizes these stubs.
4737 const TargetMachine &TM = DAG.getTarget();
4738 const Module *Mod = DAG.getMachineFunction().getFunction().getParent();
4739 const GlobalValue *GV = nullptr;
4740 if (auto *G = dyn_cast<GlobalAddressSDNode>(Callee))
4741 GV = G->getGlobal();
4742 bool Local = TM.shouldAssumeDSOLocal(*Mod, GV);
4743 bool UsePlt = !Local && Subtarget.isTargetELF() && !isPPC64;
4745 if (isFunctionGlobalAddress(Callee)) {
4746 GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Callee);
4747 // A call to a TLS address is actually an indirect call to a
4748 // thread-specific pointer.
4749 unsigned OpFlags = 0;
4751 OpFlags = PPCII::MO_PLT;
4753 // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
4754 // every direct call is) turn it into a TargetGlobalAddress /
4755 // TargetExternalSymbol node so that legalize doesn't hack it.
4756 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
4757 Callee.getValueType(), 0, OpFlags);
4758 needIndirectCall = false;
4761 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
4762 unsigned char OpFlags = 0;
4765 OpFlags = PPCII::MO_PLT;
4767 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
4769 needIndirectCall = false;
4773 // We'll form an invalid direct call when lowering a patchpoint; the full
4774 // sequence for an indirect call is complicated, and many of the
4775 // instructions introduced might have side effects (and, thus, can't be
4776 // removed later). The call itself will be removed as soon as the
4777 // argument/return lowering is complete, so the fact that it has the wrong
4778 // kind of operands should not really matter.
4779 needIndirectCall = false;
4782 if (needIndirectCall) {
4783 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
4784 // to do the call, we can't use PPCISD::CALL.
4785 SDValue MTCTROps[] = {Chain, Callee, InFlag};
4787 if (isSVR4ABI && isPPC64 && !isELFv2ABI) {
4788 // Function pointers in the 64-bit SVR4 ABI do not point to the function
4789 // entry point, but to the function descriptor (the function entry point
4790 // address is part of the function descriptor though).
4791 // The function descriptor is a three doubleword structure with the
4792 // following fields: function entry point, TOC base address and
4793 // environment pointer.
4794 // Thus for a call through a function pointer, the following actions need
4796 // 1. Save the TOC of the caller in the TOC save area of its stack
4797 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()).
4798 // 2. Load the address of the function entry point from the function
4800 // 3. Load the TOC of the callee from the function descriptor into r2.
4801 // 4. Load the environment pointer from the function descriptor into
4803 // 5. Branch to the function entry point address.
4804 // 6. On return of the callee, the TOC of the caller needs to be
4805 // restored (this is done in FinishCall()).
4807 // The loads are scheduled at the beginning of the call sequence, and the
4808 // register copies are flagged together to ensure that no other
4809 // operations can be scheduled in between. E.g. without flagging the
4810 // copies together, a TOC access in the caller could be scheduled between
4811 // the assignment of the callee TOC and the branch to the callee, which
4812 // results in the TOC access going through the TOC of the callee instead
4813 // of going through the TOC of the caller, which leads to incorrect code.
4815 // Load the address of the function entry point from the function
4817 SDValue LDChain = CallSeqStart.getValue(CallSeqStart->getNumValues()-1);
4818 if (LDChain.getValueType() == MVT::Glue)
4819 LDChain = CallSeqStart.getValue(CallSeqStart->getNumValues()-2);
4821 auto MMOFlags = Subtarget.hasInvariantFunctionDescriptors()
4822 ? (MachineMemOperand::MODereferenceable |
4823 MachineMemOperand::MOInvariant)
4824 : MachineMemOperand::MONone;
4826 MachinePointerInfo MPI(CS ? CS.getCalledValue() : nullptr);
4827 SDValue LoadFuncPtr = DAG.getLoad(MVT::i64, dl, LDChain, Callee, MPI,
4828 /* Alignment = */ 8, MMOFlags);
4830 // Load environment pointer into r11.
4831 SDValue PtrOff = DAG.getIntPtrConstant(16, dl);
4832 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
4833 SDValue LoadEnvPtr =
4834 DAG.getLoad(MVT::i64, dl, LDChain, AddPtr, MPI.getWithOffset(16),
4835 /* Alignment = */ 8, MMOFlags);
4837 SDValue TOCOff = DAG.getIntPtrConstant(8, dl);
4838 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, TOCOff);
4840 DAG.getLoad(MVT::i64, dl, LDChain, AddTOC, MPI.getWithOffset(8),
4841 /* Alignment = */ 8, MMOFlags);
4843 setUsesTOCBasePtr(DAG);
4844 SDValue TOCVal = DAG.getCopyToReg(Chain, dl, PPC::X2, TOCPtr,
4846 Chain = TOCVal.getValue(0);
4847 InFlag = TOCVal.getValue(1);
4849 // If the function call has an explicit 'nest' parameter, it takes the
4850 // place of the environment pointer.
4852 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
4855 Chain = EnvVal.getValue(0);
4856 InFlag = EnvVal.getValue(1);
4859 MTCTROps[0] = Chain;
4860 MTCTROps[1] = LoadFuncPtr;
4861 MTCTROps[2] = InFlag;
4864 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys,
4865 makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
4866 InFlag = Chain.getValue(1);
4869 NodeTys.push_back(MVT::Other);
4870 NodeTys.push_back(MVT::Glue);
4871 Ops.push_back(Chain);
4872 CallOpc = PPCISD::BCTRL;
4873 Callee.setNode(nullptr);
4874 // Add use of X11 (holding environment pointer)
4875 if (isSVR4ABI && isPPC64 && !isELFv2ABI && !hasNest)
4876 Ops.push_back(DAG.getRegister(PPC::X11, PtrVT));
4877 // Add CTR register as callee so a bctr can be emitted later.
4879 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT));
4882 // If this is a direct call, pass the chain and the callee.
4883 if (Callee.getNode()) {
4884 Ops.push_back(Chain);
4885 Ops.push_back(Callee);
4887 // If this is a tail call add stack pointer delta.
4889 Ops.push_back(DAG.getConstant(SPDiff, dl, MVT::i32));
4891 // Add argument registers to the end of the list so that they are known live
4893 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
4894 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
4895 RegsToPass[i].second.getValueType()));
4897 // All calls, in both the ELF V1 and V2 ABIs, need the TOC register live
4899 if (isSVR4ABI && isPPC64 && !isPatchPoint) {
4900 setUsesTOCBasePtr(DAG);
4901 Ops.push_back(DAG.getRegister(PPC::X2, PtrVT));
4907 SDValue PPCTargetLowering::LowerCallResult(
4908 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
4909 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
4910 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
4911 SmallVector<CCValAssign, 16> RVLocs;
4912 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
4914 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
4916 // Copy all of the result registers out of their specified physreg.
4917 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
4918 CCValAssign &VA = RVLocs[i];
4919 assert(VA.isRegLoc() && "Can only return in registers!");
4921 SDValue Val = DAG.getCopyFromReg(Chain, dl,
4922 VA.getLocReg(), VA.getLocVT(), InFlag);
4923 Chain = Val.getValue(1);
4924 InFlag = Val.getValue(2);
4926 switch (VA.getLocInfo()) {
4927 default: llvm_unreachable("Unknown loc info!");
4928 case CCValAssign::Full: break;
4929 case CCValAssign::AExt:
4930 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
4932 case CCValAssign::ZExt:
4933 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
4934 DAG.getValueType(VA.getValVT()));
4935 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
4937 case CCValAssign::SExt:
4938 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
4939 DAG.getValueType(VA.getValVT()));
4940 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
4944 InVals.push_back(Val);
4950 SDValue PPCTargetLowering::FinishCall(
4951 CallingConv::ID CallConv, const SDLoc &dl, bool isTailCall, bool isVarArg,
4952 bool isPatchPoint, bool hasNest, SelectionDAG &DAG,
4953 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass, SDValue InFlag,
4954 SDValue Chain, SDValue CallSeqStart, SDValue &Callee, int SPDiff,
4955 unsigned NumBytes, const SmallVectorImpl<ISD::InputArg> &Ins,
4956 SmallVectorImpl<SDValue> &InVals, ImmutableCallSite CS) const {
4957 std::vector<EVT> NodeTys;
4958 SmallVector<SDValue, 8> Ops;
4959 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, CallSeqStart, dl,
4960 SPDiff, isTailCall, isPatchPoint, hasNest,
4961 RegsToPass, Ops, NodeTys, CS, Subtarget);
4963 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
4964 if (isVarArg && Subtarget.isSVR4ABI() && !Subtarget.isPPC64())
4965 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
4967 // When performing tail call optimization the callee pops its arguments off
4968 // the stack. Account for this here so these bytes can be pushed back on in
4969 // PPCFrameLowering::eliminateCallFramePseudoInstr.
4970 int BytesCalleePops =
4971 (CallConv == CallingConv::Fast &&
4972 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0;
4974 // Add a register mask operand representing the call-preserved registers.
4975 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
4976 const uint32_t *Mask =
4977 TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv);
4978 assert(Mask && "Missing call preserved mask for calling convention");
4979 Ops.push_back(DAG.getRegisterMask(Mask));
4981 if (InFlag.getNode())
4982 Ops.push_back(InFlag);
4986 assert(((Callee.getOpcode() == ISD::Register &&
4987 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
4988 Callee.getOpcode() == ISD::TargetExternalSymbol ||
4989 Callee.getOpcode() == ISD::TargetGlobalAddress ||
4990 isa<ConstantSDNode>(Callee)) &&
4991 "Expecting an global address, external symbol, absolute value or register");
4993 DAG.getMachineFunction().getFrameInfo().setHasTailCall();
4994 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, Ops);
4997 // Add a NOP immediately after the branch instruction when using the 64-bit
4998 // SVR4 ABI. At link time, if caller and callee are in a different module and
4999 // thus have a different TOC, the call will be replaced with a call to a stub
5000 // function which saves the current TOC, loads the TOC of the callee and
5001 // branches to the callee. The NOP will be replaced with a load instruction
5002 // which restores the TOC of the caller from the TOC save slot of the current
5003 // stack frame. If caller and callee belong to the same module (and have the
5004 // same TOC), the NOP will remain unchanged.
5006 MachineFunction &MF = DAG.getMachineFunction();
5007 if (!isTailCall && Subtarget.isSVR4ABI()&& Subtarget.isPPC64() &&
5009 if (CallOpc == PPCISD::BCTRL) {
5010 // This is a call through a function pointer.
5011 // Restore the caller TOC from the save area into R2.
5012 // See PrepareCall() for more information about calls through function
5013 // pointers in the 64-bit SVR4 ABI.
5014 // We are using a target-specific load with r2 hard coded, because the
5015 // result of a target-independent load would never go directly into r2,
5016 // since r2 is a reserved register (which prevents the register allocator
5017 // from allocating it), resulting in an additional register being
5018 // allocated and an unnecessary move instruction being generated.
5019 CallOpc = PPCISD::BCTRL_LOAD_TOC;
5021 EVT PtrVT = getPointerTy(DAG.getDataLayout());
5022 SDValue StackPtr = DAG.getRegister(PPC::X1, PtrVT);
5023 unsigned TOCSaveOffset = Subtarget.getFrameLowering()->getTOCSaveOffset();
5024 SDValue TOCOff = DAG.getIntPtrConstant(TOCSaveOffset, dl);
5025 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, StackPtr, TOCOff);
5027 // The address needs to go after the chain input but before the flag (or
5028 // any other variadic arguments).
5029 Ops.insert(std::next(Ops.begin()), AddTOC);
5030 } else if (CallOpc == PPCISD::CALL &&
5031 !callsShareTOCBase(&MF.getFunction(), Callee, DAG.getTarget())) {
5032 // Otherwise insert NOP for non-local calls.
5033 CallOpc = PPCISD::CALL_NOP;
5037 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
5038 InFlag = Chain.getValue(1);
5040 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
5041 DAG.getIntPtrConstant(BytesCalleePops, dl, true),
5044 InFlag = Chain.getValue(1);
5046 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
5047 Ins, dl, DAG, InVals);
5051 PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
5052 SmallVectorImpl<SDValue> &InVals) const {
5053 SelectionDAG &DAG = CLI.DAG;
5055 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
5056 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
5057 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
5058 SDValue Chain = CLI.Chain;
5059 SDValue Callee = CLI.Callee;
5060 bool &isTailCall = CLI.IsTailCall;
5061 CallingConv::ID CallConv = CLI.CallConv;
5062 bool isVarArg = CLI.IsVarArg;
5063 bool isPatchPoint = CLI.IsPatchPoint;
5064 ImmutableCallSite CS = CLI.CS;
5067 if (Subtarget.useLongCalls() && !(CS && CS.isMustTailCall()))
5069 else if (Subtarget.isSVR4ABI() && Subtarget.isPPC64())
5071 IsEligibleForTailCallOptimization_64SVR4(Callee, CallConv, CS,
5072 isVarArg, Outs, Ins, DAG);
5074 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
5078 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
5081 assert(isa<GlobalAddressSDNode>(Callee) &&
5082 "Callee should be an llvm::Function object.");
5084 const GlobalValue *GV = cast<GlobalAddressSDNode>(Callee)->getGlobal();
5085 const unsigned Width = 80 - strlen("TCO caller: ")
5086 - strlen(", callee linkage: 0, 0");
5087 dbgs() << "TCO caller: "
5088 << left_justify(DAG.getMachineFunction().getName(), Width)
5089 << ", callee linkage: "
5090 << GV->getVisibility() << ", " << GV->getLinkage() << "\n"
5095 if (!isTailCall && CS && CS.isMustTailCall())
5096 report_fatal_error("failed to perform tail call elimination on a call "
5097 "site marked musttail");
5099 // When long calls (i.e. indirect calls) are always used, calls are always
5100 // made via function pointer. If we have a function name, first translate it
5102 if (Subtarget.useLongCalls() && isa<GlobalAddressSDNode>(Callee) &&
5104 Callee = LowerGlobalAddress(Callee, DAG);
5106 if (Subtarget.isSVR4ABI()) {
5107 if (Subtarget.isPPC64())
5108 return LowerCall_64SVR4(Chain, Callee, CallConv, isVarArg,
5109 isTailCall, isPatchPoint, Outs, OutVals, Ins,
5110 dl, DAG, InVals, CS);
5112 return LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg,
5113 isTailCall, isPatchPoint, Outs, OutVals, Ins,
5114 dl, DAG, InVals, CS);
5117 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
5118 isTailCall, isPatchPoint, Outs, OutVals, Ins,
5119 dl, DAG, InVals, CS);
5122 SDValue PPCTargetLowering::LowerCall_32SVR4(
5123 SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg,
5124 bool isTailCall, bool isPatchPoint,
5125 const SmallVectorImpl<ISD::OutputArg> &Outs,
5126 const SmallVectorImpl<SDValue> &OutVals,
5127 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
5128 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
5129 ImmutableCallSite CS) const {
5130 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description
5131 // of the 32-bit SVR4 ABI stack frame layout.
5133 assert((CallConv == CallingConv::C ||
5134 CallConv == CallingConv::Fast) && "Unknown calling convention!");
5136 unsigned PtrByteSize = 4;
5138 MachineFunction &MF = DAG.getMachineFunction();
5140 // Mark this function as potentially containing a function that contains a
5141 // tail call. As a consequence the frame pointer will be used for dynamicalloc
5142 // and restoring the callers stack pointer in this functions epilog. This is
5143 // done because by tail calling the called function might overwrite the value
5144 // in this function's (MF) stack pointer stack slot 0(SP).
5145 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
5146 CallConv == CallingConv::Fast)
5147 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
5149 // Count how many bytes are to be pushed on the stack, including the linkage
5150 // area, parameter list area and the part of the local variable space which
5151 // contains copies of aggregates which are passed by value.
5153 // Assign locations to all of the outgoing arguments.
5154 SmallVector<CCValAssign, 16> ArgLocs;
5155 PPCCCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
5157 // Reserve space for the linkage area on the stack.
5158 CCInfo.AllocateStack(Subtarget.getFrameLowering()->getLinkageSize(),
5161 CCInfo.PreAnalyzeCallOperands(Outs);
5164 // Handle fixed and variable vector arguments differently.
5165 // Fixed vector arguments go into registers as long as registers are
5166 // available. Variable vector arguments always go into memory.
5167 unsigned NumArgs = Outs.size();
5169 for (unsigned i = 0; i != NumArgs; ++i) {
5170 MVT ArgVT = Outs[i].VT;
5171 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
5174 if (Outs[i].IsFixed) {
5175 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
5178 Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
5184 errs() << "Call operand #" << i << " has unhandled type "
5185 << EVT(ArgVT).getEVTString() << "\n";
5187 llvm_unreachable(nullptr);
5191 // All arguments are treated the same.
5192 CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4);
5194 CCInfo.clearWasPPCF128();
5196 // Assign locations to all of the outgoing aggregate by value arguments.
5197 SmallVector<CCValAssign, 16> ByValArgLocs;
5198 CCState CCByValInfo(CallConv, isVarArg, MF, ByValArgLocs, *DAG.getContext());
5200 // Reserve stack space for the allocations in CCInfo.
5201 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
5203 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal);
5205 // Size of the linkage area, parameter list area and the part of the local
5206 // space variable where copies of aggregates which are passed by value are
5208 unsigned NumBytes = CCByValInfo.getNextStackOffset();
5210 // Calculate by how many bytes the stack has to be adjusted in case of tail
5211 // call optimization.
5212 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
5214 // Adjust the stack pointer for the new arguments...
5215 // These operations are automatically eliminated by the prolog/epilog pass
5216 Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, dl);
5217 SDValue CallSeqStart = Chain;
5219 // Load the return address and frame pointer so it can be moved somewhere else
5222 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, dl);
5224 // Set up a copy of the stack pointer for use loading and storing any
5225 // arguments that may not fit in the registers available for argument
5227 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
5229 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
5230 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
5231 SmallVector<SDValue, 8> MemOpChains;
5233 bool seenFloatArg = false;
5234 // Walk the register/memloc assignments, inserting copies/loads.
5235 for (unsigned i = 0, j = 0, e = ArgLocs.size();
5238 CCValAssign &VA = ArgLocs[i];
5239 SDValue Arg = OutVals[i];
5240 ISD::ArgFlagsTy Flags = Outs[i].Flags;
5242 if (Flags.isByVal()) {
5243 // Argument is an aggregate which is passed by value, thus we need to
5244 // create a copy of it in the local variable space of the current stack
5245 // frame (which is the stack frame of the caller) and pass the address of
5246 // this copy to the callee.
5247 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
5248 CCValAssign &ByValVA = ByValArgLocs[j++];
5249 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
5251 // Memory reserved in the local variable space of the callers stack frame.
5252 unsigned LocMemOffset = ByValVA.getLocMemOffset();
5254 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
5255 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(MF.getDataLayout()),
5258 // Create a copy of the argument in the local area of the current
5260 SDValue MemcpyCall =
5261 CreateCopyOfByValArgument(Arg, PtrOff,
5262 CallSeqStart.getNode()->getOperand(0),
5265 // This must go outside the CALLSEQ_START..END.
5266 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, NumBytes, 0,
5268 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
5269 NewCallSeqStart.getNode());
5270 Chain = CallSeqStart = NewCallSeqStart;
5272 // Pass the address of the aggregate copy on the stack either in a
5273 // physical register or in the parameter list area of the current stack
5274 // frame to the callee.
5278 if (VA.isRegLoc()) {
5279 if (Arg.getValueType() == MVT::i1)
5280 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Arg);
5282 seenFloatArg |= VA.getLocVT().isFloatingPoint();
5283 // Put argument in a physical register.
5284 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
5286 // Put argument in the parameter list area of the current stack frame.
5287 assert(VA.isMemLoc());
5288 unsigned LocMemOffset = VA.getLocMemOffset();
5291 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
5292 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(MF.getDataLayout()),
5295 MemOpChains.push_back(
5296 DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo()));
5298 // Calculate and remember argument location.
5299 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
5305 if (!MemOpChains.empty())
5306 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
5308 // Build a sequence of copy-to-reg nodes chained together with token chain
5309 // and flag operands which copy the outgoing args into the appropriate regs.
5311 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
5312 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
5313 RegsToPass[i].second, InFlag);
5314 InFlag = Chain.getValue(1);
5317 // Set CR bit 6 to true if this is a vararg call with floating args passed in
5320 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
5321 SDValue Ops[] = { Chain, InFlag };
5323 Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
5324 dl, VTs, makeArrayRef(Ops, InFlag.getNode() ? 2 : 1));
5326 InFlag = Chain.getValue(1);
5330 PrepareTailCall(DAG, InFlag, Chain, dl, SPDiff, NumBytes, LROp, FPOp,
5333 return FinishCall(CallConv, dl, isTailCall, isVarArg, isPatchPoint,
5334 /* unused except on PPC64 ELFv1 */ false, DAG,
5335 RegsToPass, InFlag, Chain, CallSeqStart, Callee, SPDiff,
5336 NumBytes, Ins, InVals, CS);
5339 // Copy an argument into memory, being careful to do this outside the
5340 // call sequence for the call to which the argument belongs.
5341 SDValue PPCTargetLowering::createMemcpyOutsideCallSeq(
5342 SDValue Arg, SDValue PtrOff, SDValue CallSeqStart, ISD::ArgFlagsTy Flags,
5343 SelectionDAG &DAG, const SDLoc &dl) const {
5344 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
5345 CallSeqStart.getNode()->getOperand(0),
5347 // The MEMCPY must go outside the CALLSEQ_START..END.
5348 int64_t FrameSize = CallSeqStart.getConstantOperandVal(1);
5349 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, FrameSize, 0,
5351 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
5352 NewCallSeqStart.getNode());
5353 return NewCallSeqStart;
5356 SDValue PPCTargetLowering::LowerCall_64SVR4(
5357 SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg,
5358 bool isTailCall, bool isPatchPoint,
5359 const SmallVectorImpl<ISD::OutputArg> &Outs,
5360 const SmallVectorImpl<SDValue> &OutVals,
5361 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
5362 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
5363 ImmutableCallSite CS) const {
5364 bool isELFv2ABI = Subtarget.isELFv2ABI();
5365 bool isLittleEndian = Subtarget.isLittleEndian();
5366 unsigned NumOps = Outs.size();
5367 bool hasNest = false;
5368 bool IsSibCall = false;
5370 EVT PtrVT = getPointerTy(DAG.getDataLayout());
5371 unsigned PtrByteSize = 8;
5373 MachineFunction &MF = DAG.getMachineFunction();
5375 if (isTailCall && !getTargetMachine().Options.GuaranteedTailCallOpt)
5378 // Mark this function as potentially containing a function that contains a
5379 // tail call. As a consequence the frame pointer will be used for dynamicalloc
5380 // and restoring the callers stack pointer in this functions epilog. This is
5381 // done because by tail calling the called function might overwrite the value
5382 // in this function's (MF) stack pointer stack slot 0(SP).
5383 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
5384 CallConv == CallingConv::Fast)
5385 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
5387 assert(!(CallConv == CallingConv::Fast && isVarArg) &&
5388 "fastcc not supported on varargs functions");
5390 // Count how many bytes are to be pushed on the stack, including the linkage
5391 // area, and parameter passing area. On ELFv1, the linkage area is 48 bytes
5392 // reserved space for [SP][CR][LR][2 x unused][TOC]; on ELFv2, the linkage
5393 // area is 32 bytes reserved space for [SP][CR][LR][TOC].
5394 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
5395 unsigned NumBytes = LinkageSize;
5396 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
5397 unsigned &QFPR_idx = FPR_idx;
5399 static const MCPhysReg GPR[] = {
5400 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
5401 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
5403 static const MCPhysReg VR[] = {
5404 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
5405 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
5408 const unsigned NumGPRs = array_lengthof(GPR);
5409 const unsigned NumFPRs = useSoftFloat() ? 0 : 13;
5410 const unsigned NumVRs = array_lengthof(VR);
5411 const unsigned NumQFPRs = NumFPRs;
5413 // On ELFv2, we can avoid allocating the parameter area if all the arguments
5414 // can be passed to the callee in registers.
5415 // For the fast calling convention, there is another check below.
5416 // Note: We should keep consistent with LowerFormalArguments_64SVR4()
5417 bool HasParameterArea = !isELFv2ABI || isVarArg || CallConv == CallingConv::Fast;
5418 if (!HasParameterArea) {
5419 unsigned ParamAreaSize = NumGPRs * PtrByteSize;
5420 unsigned AvailableFPRs = NumFPRs;
5421 unsigned AvailableVRs = NumVRs;
5422 unsigned NumBytesTmp = NumBytes;
5423 for (unsigned i = 0; i != NumOps; ++i) {
5424 if (Outs[i].Flags.isNest()) continue;
5425 if (CalculateStackSlotUsed(Outs[i].VT, Outs[i].ArgVT, Outs[i].Flags,
5426 PtrByteSize, LinkageSize, ParamAreaSize,
5427 NumBytesTmp, AvailableFPRs, AvailableVRs,
5428 Subtarget.hasQPX()))
5429 HasParameterArea = true;
5433 // When using the fast calling convention, we don't provide backing for
5434 // arguments that will be in registers.
5435 unsigned NumGPRsUsed = 0, NumFPRsUsed = 0, NumVRsUsed = 0;
5437 // Add up all the space actually used.
5438 for (unsigned i = 0; i != NumOps; ++i) {
5439 ISD::ArgFlagsTy Flags = Outs[i].Flags;
5440 EVT ArgVT = Outs[i].VT;
5441 EVT OrigVT = Outs[i].ArgVT;
5446 if (CallConv == CallingConv::Fast) {
5447 if (Flags.isByVal())
5448 NumGPRsUsed += (Flags.getByValSize()+7)/8;
5450 switch (ArgVT.getSimpleVT().SimpleTy) {
5451 default: llvm_unreachable("Unexpected ValueType for argument!");
5455 if (++NumGPRsUsed <= NumGPRs)
5464 if (++NumVRsUsed <= NumVRs)
5468 // When using QPX, this is handled like a FP register, otherwise, it
5469 // is an Altivec register.
5470 if (Subtarget.hasQPX()) {
5471 if (++NumFPRsUsed <= NumFPRs)
5474 if (++NumVRsUsed <= NumVRs)
5480 case MVT::v4f64: // QPX
5481 case MVT::v4i1: // QPX
5482 if (++NumFPRsUsed <= NumFPRs)
5488 /* Respect alignment of argument on the stack. */
5490 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
5491 NumBytes = ((NumBytes + Align - 1) / Align) * Align;
5493 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
5494 if (Flags.isInConsecutiveRegsLast())
5495 NumBytes = ((NumBytes + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
5498 unsigned NumBytesActuallyUsed = NumBytes;
5500 // In the old ELFv1 ABI,
5501 // the prolog code of the callee may store up to 8 GPR argument registers to
5502 // the stack, allowing va_start to index over them in memory if its varargs.
5503 // Because we cannot tell if this is needed on the caller side, we have to
5504 // conservatively assume that it is needed. As such, make sure we have at
5505 // least enough stack space for the caller to store the 8 GPRs.
5506 // In the ELFv2 ABI, we allocate the parameter area iff a callee
5507 // really requires memory operands, e.g. a vararg function.
5508 if (HasParameterArea)
5509 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
5511 NumBytes = LinkageSize;
5513 // Tail call needs the stack to be aligned.
5514 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
5515 CallConv == CallingConv::Fast)
5516 NumBytes = EnsureStackAlignment(Subtarget.getFrameLowering(), NumBytes);
5520 // Calculate by how many bytes the stack has to be adjusted in case of tail
5521 // call optimization.
5523 SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
5525 // To protect arguments on the stack from being clobbered in a tail call,
5526 // force all the loads to happen before doing any other lowering.
5528 Chain = DAG.getStackArgumentTokenFactor(Chain);
5530 // Adjust the stack pointer for the new arguments...
5531 // These operations are automatically eliminated by the prolog/epilog pass
5533 Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, dl);
5534 SDValue CallSeqStart = Chain;
5536 // Load the return address and frame pointer so it can be move somewhere else
5539 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, dl);
5541 // Set up a copy of the stack pointer for use loading and storing any
5542 // arguments that may not fit in the registers available for argument
5544 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
5546 // Figure out which arguments are going to go in registers, and which in
5547 // memory. Also, if this is a vararg function, floating point operations
5548 // must be stored to our stack, and loaded into integer regs as well, if
5549 // any integer regs are available for argument passing.
5550 unsigned ArgOffset = LinkageSize;
5552 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
5553 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
5555 SmallVector<SDValue, 8> MemOpChains;
5556 for (unsigned i = 0; i != NumOps; ++i) {
5557 SDValue Arg = OutVals[i];
5558 ISD::ArgFlagsTy Flags = Outs[i].Flags;
5559 EVT ArgVT = Outs[i].VT;
5560 EVT OrigVT = Outs[i].ArgVT;
5562 // PtrOff will be used to store the current argument to the stack if a
5563 // register cannot be found for it.
5566 // We re-align the argument offset for each argument, except when using the
5567 // fast calling convention, when we need to make sure we do that only when
5568 // we'll actually use a stack slot.
5569 auto ComputePtrOff = [&]() {
5570 /* Respect alignment of argument on the stack. */
5572 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
5573 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
5575 PtrOff = DAG.getConstant(ArgOffset, dl, StackPtr.getValueType());
5577 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
5580 if (CallConv != CallingConv::Fast) {
5583 /* Compute GPR index associated with argument offset. */
5584 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
5585 GPR_idx = std::min(GPR_idx, NumGPRs);
5588 // Promote integers to 64-bit values.
5589 if (Arg.getValueType() == MVT::i32 || Arg.getValueType() == MVT::i1) {
5590 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
5591 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
5592 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
5595 // FIXME memcpy is used way more than necessary. Correctness first.
5596 // Note: "by value" is code for passing a structure by value, not
5598 if (Flags.isByVal()) {
5599 // Note: Size includes alignment padding, so
5600 // struct x { short a; char b; }
5601 // will have Size = 4. With #pragma pack(1), it will have Size = 3.
5602 // These are the proper values we need for right-justifying the
5603 // aggregate in a parameter register.
5604 unsigned Size = Flags.getByValSize();
5606 // An empty aggregate parameter takes up no storage and no
5611 if (CallConv == CallingConv::Fast)
5614 // All aggregates smaller than 8 bytes must be passed right-justified.
5615 if (Size==1 || Size==2 || Size==4) {
5616 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32);
5617 if (GPR_idx != NumGPRs) {
5618 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
5619 MachinePointerInfo(), VT);
5620 MemOpChains.push_back(Load.getValue(1));
5621 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5623 ArgOffset += PtrByteSize;
5628 if (GPR_idx == NumGPRs && Size < 8) {
5629 SDValue AddPtr = PtrOff;
5630 if (!isLittleEndian) {
5631 SDValue Const = DAG.getConstant(PtrByteSize - Size, dl,
5632 PtrOff.getValueType());
5633 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
5635 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
5638 ArgOffset += PtrByteSize;
5641 // Copy entire object into memory. There are cases where gcc-generated
5642 // code assumes it is there, even if it could be put entirely into
5643 // registers. (This is not what the doc says.)
5645 // FIXME: The above statement is likely due to a misunderstanding of the
5646 // documents. All arguments must be copied into the parameter area BY
5647 // THE CALLEE in the event that the callee takes the address of any
5648 // formal argument. That has not yet been implemented. However, it is
5649 // reasonable to use the stack area as a staging area for the register
5652 // Skip this for small aggregates, as we will use the same slot for a
5653 // right-justified copy, below.
5655 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
5659 // When a register is available, pass a small aggregate right-justified.
5660 if (Size < 8 && GPR_idx != NumGPRs) {
5661 // The easiest way to get this right-justified in a register
5662 // is to copy the structure into the rightmost portion of a
5663 // local variable slot, then load the whole slot into the
5665 // FIXME: The memcpy seems to produce pretty awful code for
5666 // small aggregates, particularly for packed ones.
5667 // FIXME: It would be preferable to use the slot in the
5668 // parameter save area instead of a new local variable.
5669 SDValue AddPtr = PtrOff;
5670 if (!isLittleEndian) {
5671 SDValue Const = DAG.getConstant(8 - Size, dl, PtrOff.getValueType());
5672 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
5674 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
5678 // Load the slot into the register.
5680 DAG.getLoad(PtrVT, dl, Chain, PtrOff, MachinePointerInfo());
5681 MemOpChains.push_back(Load.getValue(1));
5682 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5684 // Done with this argument.
5685 ArgOffset += PtrByteSize;
5689 // For aggregates larger than PtrByteSize, copy the pieces of the
5690 // object that fit into registers from the parameter save area.
5691 for (unsigned j=0; j<Size; j+=PtrByteSize) {
5692 SDValue Const = DAG.getConstant(j, dl, PtrOff.getValueType());
5693 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
5694 if (GPR_idx != NumGPRs) {
5696 DAG.getLoad(PtrVT, dl, Chain, AddArg, MachinePointerInfo());
5697 MemOpChains.push_back(Load.getValue(1));
5698 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5699 ArgOffset += PtrByteSize;
5701 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
5708 switch (Arg.getSimpleValueType().SimpleTy) {
5709 default: llvm_unreachable("Unexpected ValueType for argument!");
5713 if (Flags.isNest()) {
5714 // The 'nest' parameter, if any, is passed in R11.
5715 RegsToPass.push_back(std::make_pair(PPC::X11, Arg));
5720 // These can be scalar arguments or elements of an integer array type
5721 // passed directly. Clang may use those instead of "byval" aggregate
5722 // types to avoid forcing arguments to memory unnecessarily.
5723 if (GPR_idx != NumGPRs) {
5724 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
5726 if (CallConv == CallingConv::Fast)
5729 assert(HasParameterArea &&
5730 "Parameter area must exist to pass an argument in memory.");
5731 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5732 true, isTailCall, false, MemOpChains,
5733 TailCallArguments, dl);
5734 if (CallConv == CallingConv::Fast)
5735 ArgOffset += PtrByteSize;
5737 if (CallConv != CallingConv::Fast)
5738 ArgOffset += PtrByteSize;
5742 // These can be scalar arguments or elements of a float array type
5743 // passed directly. The latter are used to implement ELFv2 homogenous
5744 // float aggregates.
5746 // Named arguments go into FPRs first, and once they overflow, the
5747 // remaining arguments go into GPRs and then the parameter save area.
5748 // Unnamed arguments for vararg functions always go to GPRs and
5749 // then the parameter save area. For now, put all arguments to vararg
5750 // routines always in both locations (FPR *and* GPR or stack slot).
5751 bool NeedGPROrStack = isVarArg || FPR_idx == NumFPRs;
5752 bool NeededLoad = false;
5754 // First load the argument into the next available FPR.
5755 if (FPR_idx != NumFPRs)
5756 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
5758 // Next, load the argument into GPR or stack slot if needed.
5759 if (!NeedGPROrStack)
5761 else if (GPR_idx != NumGPRs && CallConv != CallingConv::Fast) {
5762 // FIXME: We may want to re-enable this for CallingConv::Fast on the P8
5763 // once we support fp <-> gpr moves.
5765 // In the non-vararg case, this can only ever happen in the
5766 // presence of f32 array types, since otherwise we never run
5767 // out of FPRs before running out of GPRs.
5770 // Double values are always passed in a single GPR.
5771 if (Arg.getValueType() != MVT::f32) {
5772 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
5774 // Non-array float values are extended and passed in a GPR.
5775 } else if (!Flags.isInConsecutiveRegs()) {
5776 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
5777 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal);
5779 // If we have an array of floats, we collect every odd element
5780 // together with its predecessor into one GPR.
5781 } else if (ArgOffset % PtrByteSize != 0) {
5783 Lo = DAG.getNode(ISD::BITCAST, dl, MVT::i32, OutVals[i - 1]);
5784 Hi = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
5785 if (!isLittleEndian)
5787 ArgVal = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
5789 // The final element, if even, goes into the first half of a GPR.
5790 } else if (Flags.isInConsecutiveRegsLast()) {
5791 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
5792 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal);
5793 if (!isLittleEndian)
5794 ArgVal = DAG.getNode(ISD::SHL, dl, MVT::i64, ArgVal,
5795 DAG.getConstant(32, dl, MVT::i32));
5797 // Non-final even elements are skipped; they will be handled
5798 // together the with subsequent argument on the next go-around.
5802 if (ArgVal.getNode())
5803 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], ArgVal));
5805 if (CallConv == CallingConv::Fast)
5808 // Single-precision floating-point values are mapped to the
5809 // second (rightmost) word of the stack doubleword.
5810 if (Arg.getValueType() == MVT::f32 &&
5811 !isLittleEndian && !Flags.isInConsecutiveRegs()) {
5812 SDValue ConstFour = DAG.getConstant(4, dl, PtrOff.getValueType());
5813 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
5816 assert(HasParameterArea &&
5817 "Parameter area must exist to pass an argument in memory.");
5818 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5819 true, isTailCall, false, MemOpChains,
5820 TailCallArguments, dl);
5824 // When passing an array of floats, the array occupies consecutive
5825 // space in the argument area; only round up to the next doubleword
5826 // at the end of the array. Otherwise, each float takes 8 bytes.
5827 if (CallConv != CallingConv::Fast || NeededLoad) {
5828 ArgOffset += (Arg.getValueType() == MVT::f32 &&
5829 Flags.isInConsecutiveRegs()) ? 4 : 8;
5830 if (Flags.isInConsecutiveRegsLast())
5831 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
5842 if (!Subtarget.hasQPX()) {
5843 // These can be scalar arguments or elements of a vector array type
5844 // passed directly. The latter are used to implement ELFv2 homogenous
5845 // vector aggregates.
5847 // For a varargs call, named arguments go into VRs or on the stack as
5848 // usual; unnamed arguments always go to the stack or the corresponding
5849 // GPRs when within range. For now, we always put the value in both
5850 // locations (or even all three).
5852 assert(HasParameterArea &&
5853 "Parameter area must exist if we have a varargs call.");
5854 // We could elide this store in the case where the object fits
5855 // entirely in R registers. Maybe later.
5857 DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo());
5858 MemOpChains.push_back(Store);
5859 if (VR_idx != NumVRs) {
5861 DAG.getLoad(MVT::v4f32, dl, Store, PtrOff, MachinePointerInfo());
5862 MemOpChains.push_back(Load.getValue(1));
5863 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
5866 for (unsigned i=0; i<16; i+=PtrByteSize) {
5867 if (GPR_idx == NumGPRs)
5869 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
5870 DAG.getConstant(i, dl, PtrVT));
5872 DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo());
5873 MemOpChains.push_back(Load.getValue(1));
5874 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5879 // Non-varargs Altivec params go into VRs or on the stack.
5880 if (VR_idx != NumVRs) {
5881 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
5883 if (CallConv == CallingConv::Fast)
5886 assert(HasParameterArea &&
5887 "Parameter area must exist to pass an argument in memory.");
5888 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5889 true, isTailCall, true, MemOpChains,
5890 TailCallArguments, dl);
5891 if (CallConv == CallingConv::Fast)
5895 if (CallConv != CallingConv::Fast)
5900 assert(Arg.getValueType().getSimpleVT().SimpleTy == MVT::v4f32 &&
5901 "Invalid QPX parameter type");
5906 bool IsF32 = Arg.getValueType().getSimpleVT().SimpleTy == MVT::v4f32;
5908 assert(HasParameterArea &&
5909 "Parameter area must exist if we have a varargs call.");
5910 // We could elide this store in the case where the object fits
5911 // entirely in R registers. Maybe later.
5913 DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo());
5914 MemOpChains.push_back(Store);
5915 if (QFPR_idx != NumQFPRs) {
5916 SDValue Load = DAG.getLoad(IsF32 ? MVT::v4f32 : MVT::v4f64, dl, Store,
5917 PtrOff, MachinePointerInfo());
5918 MemOpChains.push_back(Load.getValue(1));
5919 RegsToPass.push_back(std::make_pair(QFPR[QFPR_idx++], Load));
5921 ArgOffset += (IsF32 ? 16 : 32);
5922 for (unsigned i = 0; i < (IsF32 ? 16U : 32U); i += PtrByteSize) {
5923 if (GPR_idx == NumGPRs)
5925 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
5926 DAG.getConstant(i, dl, PtrVT));
5928 DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo());
5929 MemOpChains.push_back(Load.getValue(1));
5930 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5935 // Non-varargs QPX params go into registers or on the stack.
5936 if (QFPR_idx != NumQFPRs) {
5937 RegsToPass.push_back(std::make_pair(QFPR[QFPR_idx++], Arg));
5939 if (CallConv == CallingConv::Fast)
5942 assert(HasParameterArea &&
5943 "Parameter area must exist to pass an argument in memory.");
5944 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5945 true, isTailCall, true, MemOpChains,
5946 TailCallArguments, dl);
5947 if (CallConv == CallingConv::Fast)
5948 ArgOffset += (IsF32 ? 16 : 32);
5951 if (CallConv != CallingConv::Fast)
5952 ArgOffset += (IsF32 ? 16 : 32);
5958 assert((!HasParameterArea || NumBytesActuallyUsed == ArgOffset) &&
5959 "mismatch in size of parameter area");
5960 (void)NumBytesActuallyUsed;
5962 if (!MemOpChains.empty())
5963 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
5965 // Check if this is an indirect call (MTCTR/BCTRL).
5966 // See PrepareCall() for more information about calls through function
5967 // pointers in the 64-bit SVR4 ABI.
5968 if (!isTailCall && !isPatchPoint &&
5969 !isFunctionGlobalAddress(Callee) &&
5970 !isa<ExternalSymbolSDNode>(Callee)) {
5971 // Load r2 into a virtual register and store it to the TOC save area.
5972 setUsesTOCBasePtr(DAG);
5973 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
5974 // TOC save area offset.
5975 unsigned TOCSaveOffset = Subtarget.getFrameLowering()->getTOCSaveOffset();
5976 SDValue PtrOff = DAG.getIntPtrConstant(TOCSaveOffset, dl);
5977 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
5978 Chain = DAG.getStore(
5979 Val.getValue(1), dl, Val, AddPtr,
5980 MachinePointerInfo::getStack(DAG.getMachineFunction(), TOCSaveOffset));
5981 // In the ELFv2 ABI, R12 must contain the address of an indirect callee.
5982 // This does not mean the MTCTR instruction must use R12; it's easier
5983 // to model this as an extra parameter, so do that.
5984 if (isELFv2ABI && !isPatchPoint)
5985 RegsToPass.push_back(std::make_pair((unsigned)PPC::X12, Callee));
5988 // Build a sequence of copy-to-reg nodes chained together with token chain
5989 // and flag operands which copy the outgoing args into the appropriate regs.
5991 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
5992 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
5993 RegsToPass[i].second, InFlag);
5994 InFlag = Chain.getValue(1);
5997 if (isTailCall && !IsSibCall)
5998 PrepareTailCall(DAG, InFlag, Chain, dl, SPDiff, NumBytes, LROp, FPOp,
6001 return FinishCall(CallConv, dl, isTailCall, isVarArg, isPatchPoint, hasNest,
6002 DAG, RegsToPass, InFlag, Chain, CallSeqStart, Callee,
6003 SPDiff, NumBytes, Ins, InVals, CS);
6006 SDValue PPCTargetLowering::LowerCall_Darwin(
6007 SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg,
6008 bool isTailCall, bool isPatchPoint,
6009 const SmallVectorImpl<ISD::OutputArg> &Outs,
6010 const SmallVectorImpl<SDValue> &OutVals,
6011 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
6012 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
6013 ImmutableCallSite CS) const {
6014 unsigned NumOps = Outs.size();
6016 EVT PtrVT = getPointerTy(DAG.getDataLayout());
6017 bool isPPC64 = PtrVT == MVT::i64;
6018 unsigned PtrByteSize = isPPC64 ? 8 : 4;
6020 MachineFunction &MF = DAG.getMachineFunction();
6022 // Mark this function as potentially containing a function that contains a
6023 // tail call. As a consequence the frame pointer will be used for dynamicalloc
6024 // and restoring the callers stack pointer in this functions epilog. This is
6025 // done because by tail calling the called function might overwrite the value
6026 // in this function's (MF) stack pointer stack slot 0(SP).
6027 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
6028 CallConv == CallingConv::Fast)
6029 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
6031 // Count how many bytes are to be pushed on the stack, including the linkage
6032 // area, and parameter passing area. We start with 24/48 bytes, which is
6033 // prereserved space for [SP][CR][LR][3 x unused].
6034 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
6035 unsigned NumBytes = LinkageSize;
6037 // Add up all the space actually used.
6038 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
6039 // they all go in registers, but we must reserve stack space for them for
6040 // possible use by the caller. In varargs or 64-bit calls, parameters are
6041 // assigned stack space in order, with padding so Altivec parameters are
6043 unsigned nAltivecParamsAtEnd = 0;
6044 for (unsigned i = 0; i != NumOps; ++i) {
6045 ISD::ArgFlagsTy Flags = Outs[i].Flags;
6046 EVT ArgVT = Outs[i].VT;
6047 // Varargs Altivec parameters are padded to a 16 byte boundary.
6048 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
6049 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
6050 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64) {
6051 if (!isVarArg && !isPPC64) {
6052 // Non-varargs Altivec parameters go after all the non-Altivec
6053 // parameters; handle those later so we know how much padding we need.
6054 nAltivecParamsAtEnd++;
6057 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
6058 NumBytes = ((NumBytes+15)/16)*16;
6060 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
6063 // Allow for Altivec parameters at the end, if needed.
6064 if (nAltivecParamsAtEnd) {
6065 NumBytes = ((NumBytes+15)/16)*16;
6066 NumBytes += 16*nAltivecParamsAtEnd;
6069 // The prolog code of the callee may store up to 8 GPR argument registers to
6070 // the stack, allowing va_start to index over them in memory if its varargs.
6071 // Because we cannot tell if this is needed on the caller side, we have to
6072 // conservatively assume that it is needed. As such, make sure we have at
6073 // least enough stack space for the caller to store the 8 GPRs.
6074 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
6076 // Tail call needs the stack to be aligned.
6077 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
6078 CallConv == CallingConv::Fast)
6079 NumBytes = EnsureStackAlignment(Subtarget.getFrameLowering(), NumBytes);
6081 // Calculate by how many bytes the stack has to be adjusted in case of tail
6082 // call optimization.
6083 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
6085 // To protect arguments on the stack from being clobbered in a tail call,
6086 // force all the loads to happen before doing any other lowering.
6088 Chain = DAG.getStackArgumentTokenFactor(Chain);
6090 // Adjust the stack pointer for the new arguments...
6091 // These operations are automatically eliminated by the prolog/epilog pass
6092 Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, dl);
6093 SDValue CallSeqStart = Chain;
6095 // Load the return address and frame pointer so it can be move somewhere else
6098 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, dl);
6100 // Set up a copy of the stack pointer for use loading and storing any
6101 // arguments that may not fit in the registers available for argument
6105 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
6107 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
6109 // Figure out which arguments are going to go in registers, and which in
6110 // memory. Also, if this is a vararg function, floating point operations
6111 // must be stored to our stack, and loaded into integer regs as well, if
6112 // any integer regs are available for argument passing.
6113 unsigned ArgOffset = LinkageSize;
6114 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
6116 static const MCPhysReg GPR_32[] = { // 32-bit registers.
6117 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
6118 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
6120 static const MCPhysReg GPR_64[] = { // 64-bit registers.
6121 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
6122 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
6124 static const MCPhysReg VR[] = {
6125 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
6126 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
6128 const unsigned NumGPRs = array_lengthof(GPR_32);
6129 const unsigned NumFPRs = 13;
6130 const unsigned NumVRs = array_lengthof(VR);
6132 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
6134 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
6135 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
6137 SmallVector<SDValue, 8> MemOpChains;
6138 for (unsigned i = 0; i != NumOps; ++i) {
6139 SDValue Arg = OutVals[i];
6140 ISD::ArgFlagsTy Flags = Outs[i].Flags;
6142 // PtrOff will be used to store the current argument to the stack if a
6143 // register cannot be found for it.
6146 PtrOff = DAG.getConstant(ArgOffset, dl, StackPtr.getValueType());
6148 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
6150 // On PPC64, promote integers to 64-bit values.
6151 if (isPPC64 && Arg.getValueType() == MVT::i32) {
6152 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
6153 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
6154 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
6157 // FIXME memcpy is used way more than necessary. Correctness first.
6158 // Note: "by value" is code for passing a structure by value, not
6160 if (Flags.isByVal()) {
6161 unsigned Size = Flags.getByValSize();
6162 // Very small objects are passed right-justified. Everything else is
6163 // passed left-justified.
6164 if (Size==1 || Size==2) {
6165 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
6166 if (GPR_idx != NumGPRs) {
6167 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
6168 MachinePointerInfo(), VT);
6169 MemOpChains.push_back(Load.getValue(1));
6170 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
6172 ArgOffset += PtrByteSize;
6174 SDValue Const = DAG.getConstant(PtrByteSize - Size, dl,
6175 PtrOff.getValueType());
6176 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
6177 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
6180 ArgOffset += PtrByteSize;
6184 // Copy entire object into memory. There are cases where gcc-generated
6185 // code assumes it is there, even if it could be put entirely into
6186 // registers. (This is not what the doc says.)
6187 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
6191 // For small aggregates (Darwin only) and aggregates >= PtrByteSize,
6192 // copy the pieces of the object that fit into registers from the
6193 // parameter save area.
6194 for (unsigned j=0; j<Size; j+=PtrByteSize) {
6195 SDValue Const = DAG.getConstant(j, dl, PtrOff.getValueType());
6196 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
6197 if (GPR_idx != NumGPRs) {
6199 DAG.getLoad(PtrVT, dl, Chain, AddArg, MachinePointerInfo());
6200 MemOpChains.push_back(Load.getValue(1));
6201 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
6202 ArgOffset += PtrByteSize;
6204 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
6211 switch (Arg.getSimpleValueType().SimpleTy) {
6212 default: llvm_unreachable("Unexpected ValueType for argument!");
6216 if (GPR_idx != NumGPRs) {
6217 if (Arg.getValueType() == MVT::i1)
6218 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, PtrVT, Arg);
6220 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
6222 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
6223 isPPC64, isTailCall, false, MemOpChains,
6224 TailCallArguments, dl);
6226 ArgOffset += PtrByteSize;
6230 if (FPR_idx != NumFPRs) {
6231 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
6235 DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo());
6236 MemOpChains.push_back(Store);
6238 // Float varargs are always shadowed in available integer registers
6239 if (GPR_idx != NumGPRs) {
6241 DAG.getLoad(PtrVT, dl, Store, PtrOff, MachinePointerInfo());
6242 MemOpChains.push_back(Load.getValue(1));
6243 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
6245 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
6246 SDValue ConstFour = DAG.getConstant(4, dl, PtrOff.getValueType());
6247 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
6249 DAG.getLoad(PtrVT, dl, Store, PtrOff, MachinePointerInfo());
6250 MemOpChains.push_back(Load.getValue(1));
6251 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
6254 // If we have any FPRs remaining, we may also have GPRs remaining.
6255 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
6257 if (GPR_idx != NumGPRs)
6259 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
6260 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
6264 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
6265 isPPC64, isTailCall, false, MemOpChains,
6266 TailCallArguments, dl);
6270 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
6277 // These go aligned on the stack, or in the corresponding R registers
6278 // when within range. The Darwin PPC ABI doc claims they also go in
6279 // V registers; in fact gcc does this only for arguments that are
6280 // prototyped, not for those that match the ... We do it for all
6281 // arguments, seems to work.
6282 while (ArgOffset % 16 !=0) {
6283 ArgOffset += PtrByteSize;
6284 if (GPR_idx != NumGPRs)
6287 // We could elide this store in the case where the object fits
6288 // entirely in R registers. Maybe later.
6289 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
6290 DAG.getConstant(ArgOffset, dl, PtrVT));
6292 DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo());
6293 MemOpChains.push_back(Store);
6294 if (VR_idx != NumVRs) {
6296 DAG.getLoad(MVT::v4f32, dl, Store, PtrOff, MachinePointerInfo());
6297 MemOpChains.push_back(Load.getValue(1));
6298 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
6301 for (unsigned i=0; i<16; i+=PtrByteSize) {
6302 if (GPR_idx == NumGPRs)
6304 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
6305 DAG.getConstant(i, dl, PtrVT));
6307 DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo());
6308 MemOpChains.push_back(Load.getValue(1));
6309 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
6314 // Non-varargs Altivec params generally go in registers, but have
6315 // stack space allocated at the end.
6316 if (VR_idx != NumVRs) {
6317 // Doesn't have GPR space allocated.
6318 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
6319 } else if (nAltivecParamsAtEnd==0) {
6320 // We are emitting Altivec params in order.
6321 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
6322 isPPC64, isTailCall, true, MemOpChains,
6323 TailCallArguments, dl);
6329 // If all Altivec parameters fit in registers, as they usually do,
6330 // they get stack space following the non-Altivec parameters. We
6331 // don't track this here because nobody below needs it.
6332 // If there are more Altivec parameters than fit in registers emit
6334 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
6336 // Offset is aligned; skip 1st 12 params which go in V registers.
6337 ArgOffset = ((ArgOffset+15)/16)*16;
6339 for (unsigned i = 0; i != NumOps; ++i) {
6340 SDValue Arg = OutVals[i];
6341 EVT ArgType = Outs[i].VT;
6342 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
6343 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
6346 // We are emitting Altivec params in order.
6347 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
6348 isPPC64, isTailCall, true, MemOpChains,
6349 TailCallArguments, dl);
6356 if (!MemOpChains.empty())
6357 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
6359 // On Darwin, R12 must contain the address of an indirect callee. This does
6360 // not mean the MTCTR instruction must use R12; it's easier to model this as
6361 // an extra parameter, so do that.
6363 !isFunctionGlobalAddress(Callee) &&
6364 !isa<ExternalSymbolSDNode>(Callee) &&
6365 !isBLACompatibleAddress(Callee, DAG))
6366 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
6367 PPC::R12), Callee));
6369 // Build a sequence of copy-to-reg nodes chained together with token chain
6370 // and flag operands which copy the outgoing args into the appropriate regs.
6372 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
6373 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
6374 RegsToPass[i].second, InFlag);
6375 InFlag = Chain.getValue(1);
6379 PrepareTailCall(DAG, InFlag, Chain, dl, SPDiff, NumBytes, LROp, FPOp,
6382 return FinishCall(CallConv, dl, isTailCall, isVarArg, isPatchPoint,
6383 /* unused except on PPC64 ELFv1 */ false, DAG,
6384 RegsToPass, InFlag, Chain, CallSeqStart, Callee, SPDiff,
6385 NumBytes, Ins, InVals, CS);
6389 PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
6390 MachineFunction &MF, bool isVarArg,
6391 const SmallVectorImpl<ISD::OutputArg> &Outs,
6392 LLVMContext &Context) const {
6393 SmallVector<CCValAssign, 16> RVLocs;
6394 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
6395 return CCInfo.CheckReturn(Outs, RetCC_PPC);
6399 PPCTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
6401 const SmallVectorImpl<ISD::OutputArg> &Outs,
6402 const SmallVectorImpl<SDValue> &OutVals,
6403 const SDLoc &dl, SelectionDAG &DAG) const {
6404 SmallVector<CCValAssign, 16> RVLocs;
6405 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
6407 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
6410 SmallVector<SDValue, 4> RetOps(1, Chain);
6412 // Copy the result values into the output registers.
6413 for (unsigned i = 0; i != RVLocs.size(); ++i) {
6414 CCValAssign &VA = RVLocs[i];
6415 assert(VA.isRegLoc() && "Can only return in registers!");
6417 SDValue Arg = OutVals[i];
6419 switch (VA.getLocInfo()) {
6420 default: llvm_unreachable("Unknown loc info!");
6421 case CCValAssign::Full: break;
6422 case CCValAssign::AExt:
6423 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
6425 case CCValAssign::ZExt:
6426 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
6428 case CCValAssign::SExt:
6429 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
6433 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
6434 Flag = Chain.getValue(1);
6435 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
6438 const PPCRegisterInfo *TRI = Subtarget.getRegisterInfo();
6439 const MCPhysReg *I =
6440 TRI->getCalleeSavedRegsViaCopy(&DAG.getMachineFunction());
6444 if (PPC::G8RCRegClass.contains(*I))
6445 RetOps.push_back(DAG.getRegister(*I, MVT::i64));
6446 else if (PPC::F8RCRegClass.contains(*I))
6447 RetOps.push_back(DAG.getRegister(*I, MVT::getFloatingPointVT(64)));
6448 else if (PPC::CRRCRegClass.contains(*I))
6449 RetOps.push_back(DAG.getRegister(*I, MVT::i1));
6450 else if (PPC::VRRCRegClass.contains(*I))
6451 RetOps.push_back(DAG.getRegister(*I, MVT::Other));
6453 llvm_unreachable("Unexpected register class in CSRsViaCopy!");
6457 RetOps[0] = Chain; // Update chain.
6459 // Add the flag if we have it.
6461 RetOps.push_back(Flag);
6463 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, RetOps);
6467 PPCTargetLowering::LowerGET_DYNAMIC_AREA_OFFSET(SDValue Op,
6468 SelectionDAG &DAG) const {
6471 // Get the correct type for integers.
6472 EVT IntVT = Op.getValueType();
6475 SDValue Chain = Op.getOperand(0);
6476 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
6477 // Build a DYNAREAOFFSET node.
6478 SDValue Ops[2] = {Chain, FPSIdx};
6479 SDVTList VTs = DAG.getVTList(IntVT);
6480 return DAG.getNode(PPCISD::DYNAREAOFFSET, dl, VTs, Ops);
6483 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op,
6484 SelectionDAG &DAG) const {
6485 // When we pop the dynamic allocation we need to restore the SP link.
6488 // Get the correct type for pointers.
6489 EVT PtrVT = getPointerTy(DAG.getDataLayout());
6491 // Construct the stack pointer operand.
6492 bool isPPC64 = Subtarget.isPPC64();
6493 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
6494 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
6496 // Get the operands for the STACKRESTORE.
6497 SDValue Chain = Op.getOperand(0);
6498 SDValue SaveSP = Op.getOperand(1);
6500 // Load the old link SP.
6501 SDValue LoadLinkSP =
6502 DAG.getLoad(PtrVT, dl, Chain, StackPtr, MachinePointerInfo());
6504 // Restore the stack pointer.
6505 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
6507 // Store the old link SP.
6508 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo());
6511 SDValue PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG &DAG) const {
6512 MachineFunction &MF = DAG.getMachineFunction();
6513 bool isPPC64 = Subtarget.isPPC64();
6514 EVT PtrVT = getPointerTy(MF.getDataLayout());
6516 // Get current frame pointer save index. The users of this index will be
6517 // primarily DYNALLOC instructions.
6518 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
6519 int RASI = FI->getReturnAddrSaveIndex();
6521 // If the frame pointer save index hasn't been defined yet.
6523 // Find out what the fix offset of the frame pointer save area.
6524 int LROffset = Subtarget.getFrameLowering()->getReturnSaveOffset();
6525 // Allocate the frame index for frame pointer save area.
6526 RASI = MF.getFrameInfo().CreateFixedObject(isPPC64? 8 : 4, LROffset, false);
6528 FI->setReturnAddrSaveIndex(RASI);
6530 return DAG.getFrameIndex(RASI, PtrVT);
6534 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
6535 MachineFunction &MF = DAG.getMachineFunction();
6536 bool isPPC64 = Subtarget.isPPC64();
6537 EVT PtrVT = getPointerTy(MF.getDataLayout());
6539 // Get current frame pointer save index. The users of this index will be
6540 // primarily DYNALLOC instructions.
6541 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
6542 int FPSI = FI->getFramePointerSaveIndex();
6544 // If the frame pointer save index hasn't been defined yet.
6546 // Find out what the fix offset of the frame pointer save area.
6547 int FPOffset = Subtarget.getFrameLowering()->getFramePointerSaveOffset();
6548 // Allocate the frame index for frame pointer save area.
6549 FPSI = MF.getFrameInfo().CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
6551 FI->setFramePointerSaveIndex(FPSI);
6553 return DAG.getFrameIndex(FPSI, PtrVT);
6556 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
6557 SelectionDAG &DAG) const {
6559 SDValue Chain = Op.getOperand(0);
6560 SDValue Size = Op.getOperand(1);
6563 // Get the correct type for pointers.
6564 EVT PtrVT = getPointerTy(DAG.getDataLayout());
6566 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
6567 DAG.getConstant(0, dl, PtrVT), Size);
6568 // Construct a node for the frame pointer save index.
6569 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
6570 // Build a DYNALLOC node.
6571 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
6572 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
6573 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops);
6576 SDValue PPCTargetLowering::LowerEH_DWARF_CFA(SDValue Op,
6577 SelectionDAG &DAG) const {
6578 MachineFunction &MF = DAG.getMachineFunction();
6580 bool isPPC64 = Subtarget.isPPC64();
6581 EVT PtrVT = getPointerTy(DAG.getDataLayout());
6583 int FI = MF.getFrameInfo().CreateFixedObject(isPPC64 ? 8 : 4, 0, false);
6584 return DAG.getFrameIndex(FI, PtrVT);
6587 SDValue PPCTargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
6588 SelectionDAG &DAG) const {
6590 return DAG.getNode(PPCISD::EH_SJLJ_SETJMP, DL,
6591 DAG.getVTList(MVT::i32, MVT::Other),
6592 Op.getOperand(0), Op.getOperand(1));
6595 SDValue PPCTargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
6596 SelectionDAG &DAG) const {
6598 return DAG.getNode(PPCISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
6599 Op.getOperand(0), Op.getOperand(1));
6602 SDValue PPCTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
6603 if (Op.getValueType().isVector())
6604 return LowerVectorLoad(Op, DAG);
6606 assert(Op.getValueType() == MVT::i1 &&
6607 "Custom lowering only for i1 loads");
6609 // First, load 8 bits into 32 bits, then truncate to 1 bit.
6612 LoadSDNode *LD = cast<LoadSDNode>(Op);
6614 SDValue Chain = LD->getChain();
6615 SDValue BasePtr = LD->getBasePtr();
6616 MachineMemOperand *MMO = LD->getMemOperand();
6619 DAG.getExtLoad(ISD::EXTLOAD, dl, getPointerTy(DAG.getDataLayout()), Chain,
6620 BasePtr, MVT::i8, MMO);
6621 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewLD);
6623 SDValue Ops[] = { Result, SDValue(NewLD.getNode(), 1) };
6624 return DAG.getMergeValues(Ops, dl);
6627 SDValue PPCTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
6628 if (Op.getOperand(1).getValueType().isVector())
6629 return LowerVectorStore(Op, DAG);
6631 assert(Op.getOperand(1).getValueType() == MVT::i1 &&
6632 "Custom lowering only for i1 stores");
6634 // First, zero extend to 32 bits, then use a truncating store to 8 bits.
6637 StoreSDNode *ST = cast<StoreSDNode>(Op);
6639 SDValue Chain = ST->getChain();
6640 SDValue BasePtr = ST->getBasePtr();
6641 SDValue Value = ST->getValue();
6642 MachineMemOperand *MMO = ST->getMemOperand();
6644 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, getPointerTy(DAG.getDataLayout()),
6646 return DAG.getTruncStore(Chain, dl, Value, BasePtr, MVT::i8, MMO);
6649 // FIXME: Remove this once the ANDI glue bug is fixed:
6650 SDValue PPCTargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
6651 assert(Op.getValueType() == MVT::i1 &&
6652 "Custom lowering only for i1 results");
6655 return DAG.getNode(PPCISD::ANDIo_1_GT_BIT, DL, MVT::i1,
6659 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
6661 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
6662 // Not FP? Not a fsel.
6663 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
6664 !Op.getOperand(2).getValueType().isFloatingPoint())
6667 // We might be able to do better than this under some circumstances, but in
6668 // general, fsel-based lowering of select is a finite-math-only optimization.
6669 // For more information, see section F.3 of the 2.06 ISA specification.
6670 if (!DAG.getTarget().Options.NoInfsFPMath ||
6671 !DAG.getTarget().Options.NoNaNsFPMath)
6673 // TODO: Propagate flags from the select rather than global settings.
6675 Flags.setNoInfs(true);
6676 Flags.setNoNaNs(true);
6678 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
6680 EVT ResVT = Op.getValueType();
6681 EVT CmpVT = Op.getOperand(0).getValueType();
6682 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6683 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
6686 // If the RHS of the comparison is a 0.0, we don't need to do the
6687 // subtraction at all.
6689 if (isFloatingPointZero(RHS))
6691 default: break; // SETUO etc aren't handled by fsel.
6696 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
6697 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
6698 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
6699 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
6700 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
6701 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
6702 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV);
6705 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
6709 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
6710 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
6711 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
6714 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
6718 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
6719 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
6720 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
6721 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
6726 default: break; // SETUO etc aren't handled by fsel.
6731 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS, Flags);
6732 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
6733 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
6734 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
6735 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
6736 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
6737 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
6738 DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV);
6741 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS, Flags);
6742 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
6743 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
6744 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
6747 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS, Flags);
6748 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
6749 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
6750 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
6753 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS, Flags);
6754 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
6755 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
6756 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
6759 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS, Flags);
6760 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
6761 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
6762 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
6767 void PPCTargetLowering::LowerFP_TO_INTForReuse(SDValue Op, ReuseLoadInfo &RLI,
6769 const SDLoc &dl) const {
6770 assert(Op.getOperand(0).getValueType().isFloatingPoint());
6771 SDValue Src = Op.getOperand(0);
6772 if (Src.getValueType() == MVT::f32)
6773 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
6776 switch (Op.getSimpleValueType().SimpleTy) {
6777 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
6780 Op.getOpcode() == ISD::FP_TO_SINT
6782 : (Subtarget.hasFPCVT() ? PPCISD::FCTIWUZ : PPCISD::FCTIDZ),
6786 assert((Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT()) &&
6787 "i64 FP_TO_UINT is supported only with FPCVT");
6788 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
6794 // Convert the FP value to an int value through memory.
6795 bool i32Stack = Op.getValueType() == MVT::i32 && Subtarget.hasSTFIWX() &&
6796 (Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT());
6797 SDValue FIPtr = DAG.CreateStackTemporary(i32Stack ? MVT::i32 : MVT::f64);
6798 int FI = cast<FrameIndexSDNode>(FIPtr)->getIndex();
6799 MachinePointerInfo MPI =
6800 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI);
6802 // Emit a store to the stack slot.
6805 MachineFunction &MF = DAG.getMachineFunction();
6806 MachineMemOperand *MMO =
6807 MF.getMachineMemOperand(MPI, MachineMemOperand::MOStore, 4, 4);
6808 SDValue Ops[] = { DAG.getEntryNode(), Tmp, FIPtr };
6809 Chain = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
6810 DAG.getVTList(MVT::Other), Ops, MVT::i32, MMO);
6812 Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr, MPI);
6814 // Result is a load from the stack slot. If loading 4 bytes, make sure to
6815 // add in a bias on big endian.
6816 if (Op.getValueType() == MVT::i32 && !i32Stack) {
6817 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
6818 DAG.getConstant(4, dl, FIPtr.getValueType()));
6819 MPI = MPI.getWithOffset(Subtarget.isLittleEndian() ? 0 : 4);
6827 /// \brief Custom lowers floating point to integer conversions to use
6828 /// the direct move instructions available in ISA 2.07 to avoid the
6829 /// need for load/store combinations.
6830 SDValue PPCTargetLowering::LowerFP_TO_INTDirectMove(SDValue Op,
6832 const SDLoc &dl) const {
6833 assert(Op.getOperand(0).getValueType().isFloatingPoint());
6834 SDValue Src = Op.getOperand(0);
6836 if (Src.getValueType() == MVT::f32)
6837 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
6840 switch (Op.getSimpleValueType().SimpleTy) {
6841 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
6844 Op.getOpcode() == ISD::FP_TO_SINT
6846 : (Subtarget.hasFPCVT() ? PPCISD::FCTIWUZ : PPCISD::FCTIDZ),
6848 Tmp = DAG.getNode(PPCISD::MFVSR, dl, MVT::i32, Tmp);
6851 assert((Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT()) &&
6852 "i64 FP_TO_UINT is supported only with FPCVT");
6853 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
6856 Tmp = DAG.getNode(PPCISD::MFVSR, dl, MVT::i64, Tmp);
6862 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
6863 const SDLoc &dl) const {
6864 if (Subtarget.hasDirectMove() && Subtarget.isPPC64())
6865 return LowerFP_TO_INTDirectMove(Op, DAG, dl);
6868 LowerFP_TO_INTForReuse(Op, RLI, DAG, dl);
6870 return DAG.getLoad(Op.getValueType(), dl, RLI.Chain, RLI.Ptr, RLI.MPI,
6871 RLI.Alignment, RLI.MMOFlags(), RLI.AAInfo, RLI.Ranges);
6874 // We're trying to insert a regular store, S, and then a load, L. If the
6875 // incoming value, O, is a load, we might just be able to have our load use the
6876 // address used by O. However, we don't know if anything else will store to
6877 // that address before we can load from it. To prevent this situation, we need
6878 // to insert our load, L, into the chain as a peer of O. To do this, we give L
6879 // the same chain operand as O, we create a token factor from the chain results
6880 // of O and L, and we replace all uses of O's chain result with that token
6881 // factor (see spliceIntoChain below for this last part).
6882 bool PPCTargetLowering::canReuseLoadAddress(SDValue Op, EVT MemVT,
6885 ISD::LoadExtType ET) const {
6887 if (ET == ISD::NON_EXTLOAD &&
6888 (Op.getOpcode() == ISD::FP_TO_UINT ||
6889 Op.getOpcode() == ISD::FP_TO_SINT) &&
6890 isOperationLegalOrCustom(Op.getOpcode(),
6891 Op.getOperand(0).getValueType())) {
6893 LowerFP_TO_INTForReuse(Op, RLI, DAG, dl);
6897 LoadSDNode *LD = dyn_cast<LoadSDNode>(Op);
6898 if (!LD || LD->getExtensionType() != ET || LD->isVolatile() ||
6899 LD->isNonTemporal())
6901 if (LD->getMemoryVT() != MemVT)
6904 RLI.Ptr = LD->getBasePtr();
6905 if (LD->isIndexed() && !LD->getOffset().isUndef()) {
6906 assert(LD->getAddressingMode() == ISD::PRE_INC &&
6907 "Non-pre-inc AM on PPC?");
6908 RLI.Ptr = DAG.getNode(ISD::ADD, dl, RLI.Ptr.getValueType(), RLI.Ptr,
6912 RLI.Chain = LD->getChain();
6913 RLI.MPI = LD->getPointerInfo();
6914 RLI.IsDereferenceable = LD->isDereferenceable();
6915 RLI.IsInvariant = LD->isInvariant();
6916 RLI.Alignment = LD->getAlignment();
6917 RLI.AAInfo = LD->getAAInfo();
6918 RLI.Ranges = LD->getRanges();
6920 RLI.ResChain = SDValue(LD, LD->isIndexed() ? 2 : 1);
6924 // Given the head of the old chain, ResChain, insert a token factor containing
6925 // it and NewResChain, and make users of ResChain now be users of that token
6927 // TODO: Remove and use DAG::makeEquivalentMemoryOrdering() instead.
6928 void PPCTargetLowering::spliceIntoChain(SDValue ResChain,
6929 SDValue NewResChain,
6930 SelectionDAG &DAG) const {
6934 SDLoc dl(NewResChain);
6936 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
6937 NewResChain, DAG.getUNDEF(MVT::Other));
6938 assert(TF.getNode() != NewResChain.getNode() &&
6939 "A new TF really is required here");
6941 DAG.ReplaceAllUsesOfValueWith(ResChain, TF);
6942 DAG.UpdateNodeOperands(TF.getNode(), ResChain, NewResChain);
6945 /// \brief Analyze profitability of direct move
6946 /// prefer float load to int load plus direct move
6947 /// when there is no integer use of int load
6948 bool PPCTargetLowering::directMoveIsProfitable(const SDValue &Op) const {
6949 SDNode *Origin = Op.getOperand(0).getNode();
6950 if (Origin->getOpcode() != ISD::LOAD)
6953 // If there is no LXSIBZX/LXSIHZX, like Power8,
6954 // prefer direct move if the memory size is 1 or 2 bytes.
6955 MachineMemOperand *MMO = cast<LoadSDNode>(Origin)->getMemOperand();
6956 if (!Subtarget.hasP9Vector() && MMO->getSize() <= 2)
6959 for (SDNode::use_iterator UI = Origin->use_begin(),
6960 UE = Origin->use_end();
6963 // Only look at the users of the loaded value.
6964 if (UI.getUse().get().getResNo() != 0)
6967 if (UI->getOpcode() != ISD::SINT_TO_FP &&
6968 UI->getOpcode() != ISD::UINT_TO_FP)
6975 /// \brief Custom lowers integer to floating point conversions to use
6976 /// the direct move instructions available in ISA 2.07 to avoid the
6977 /// need for load/store combinations.
6978 SDValue PPCTargetLowering::LowerINT_TO_FPDirectMove(SDValue Op,
6980 const SDLoc &dl) const {
6981 assert((Op.getValueType() == MVT::f32 ||
6982 Op.getValueType() == MVT::f64) &&
6983 "Invalid floating point type as target of conversion");
6984 assert(Subtarget.hasFPCVT() &&
6985 "Int to FP conversions with direct moves require FPCVT");
6987 SDValue Src = Op.getOperand(0);
6988 bool SinglePrec = Op.getValueType() == MVT::f32;
6989 bool WordInt = Src.getSimpleValueType().SimpleTy == MVT::i32;
6990 bool Signed = Op.getOpcode() == ISD::SINT_TO_FP;
6991 unsigned ConvOp = Signed ? (SinglePrec ? PPCISD::FCFIDS : PPCISD::FCFID) :
6992 (SinglePrec ? PPCISD::FCFIDUS : PPCISD::FCFIDU);
6995 FP = DAG.getNode(Signed ? PPCISD::MTVSRA : PPCISD::MTVSRZ,
6997 FP = DAG.getNode(ConvOp, dl, SinglePrec ? MVT::f32 : MVT::f64, FP);
7000 FP = DAG.getNode(PPCISD::MTVSRA, dl, MVT::f64, Src);
7001 FP = DAG.getNode(ConvOp, dl, SinglePrec ? MVT::f32 : MVT::f64, FP);
7007 SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
7008 SelectionDAG &DAG) const {
7011 if (Subtarget.hasQPX() && Op.getOperand(0).getValueType() == MVT::v4i1) {
7012 if (Op.getValueType() != MVT::v4f32 && Op.getValueType() != MVT::v4f64)
7015 SDValue Value = Op.getOperand(0);
7016 // The values are now known to be -1 (false) or 1 (true). To convert this
7017 // into 0 (false) and 1 (true), add 1 and then divide by 2 (multiply by 0.5).
7018 // This can be done with an fma and the 0.5 constant: (V+1.0)*0.5 = 0.5*V+0.5
7019 Value = DAG.getNode(PPCISD::QBFLT, dl, MVT::v4f64, Value);
7021 SDValue FPHalfs = DAG.getConstantFP(0.5, dl, MVT::v4f64);
7023 Value = DAG.getNode(ISD::FMA, dl, MVT::v4f64, Value, FPHalfs, FPHalfs);
7025 if (Op.getValueType() != MVT::v4f64)
7026 Value = DAG.getNode(ISD::FP_ROUND, dl,
7027 Op.getValueType(), Value,
7028 DAG.getIntPtrConstant(1, dl));
7032 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
7033 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
7036 if (Op.getOperand(0).getValueType() == MVT::i1)
7037 return DAG.getNode(ISD::SELECT, dl, Op.getValueType(), Op.getOperand(0),
7038 DAG.getConstantFP(1.0, dl, Op.getValueType()),
7039 DAG.getConstantFP(0.0, dl, Op.getValueType()));
7041 // If we have direct moves, we can do all the conversion, skip the store/load
7042 // however, without FPCVT we can't do most conversions.
7043 if (Subtarget.hasDirectMove() && directMoveIsProfitable(Op) &&
7044 Subtarget.isPPC64() && Subtarget.hasFPCVT())
7045 return LowerINT_TO_FPDirectMove(Op, DAG, dl);
7047 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) &&
7048 "UINT_TO_FP is supported only with FPCVT");
7050 // If we have FCFIDS, then use it when converting to single-precision.
7051 // Otherwise, convert to double-precision and then round.
7052 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
7053 ? (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDUS
7055 : (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDU
7057 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
7061 if (Op.getOperand(0).getValueType() == MVT::i64) {
7062 SDValue SINT = Op.getOperand(0);
7063 // When converting to single-precision, we actually need to convert
7064 // to double-precision first and then round to single-precision.
7065 // To avoid double-rounding effects during that operation, we have
7066 // to prepare the input operand. Bits that might be truncated when
7067 // converting to double-precision are replaced by a bit that won't
7068 // be lost at this stage, but is below the single-precision rounding
7071 // However, if -enable-unsafe-fp-math is in effect, accept double
7072 // rounding to avoid the extra overhead.
7073 if (Op.getValueType() == MVT::f32 &&
7074 !Subtarget.hasFPCVT() &&
7075 !DAG.getTarget().Options.UnsafeFPMath) {
7077 // Twiddle input to make sure the low 11 bits are zero. (If this
7078 // is the case, we are guaranteed the value will fit into the 53 bit
7079 // mantissa of an IEEE double-precision value without rounding.)
7080 // If any of those low 11 bits were not zero originally, make sure
7081 // bit 12 (value 2048) is set instead, so that the final rounding
7082 // to single-precision gets the correct result.
7083 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64,
7084 SINT, DAG.getConstant(2047, dl, MVT::i64));
7085 Round = DAG.getNode(ISD::ADD, dl, MVT::i64,
7086 Round, DAG.getConstant(2047, dl, MVT::i64));
7087 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT);
7088 Round = DAG.getNode(ISD::AND, dl, MVT::i64,
7089 Round, DAG.getConstant(-2048, dl, MVT::i64));
7091 // However, we cannot use that value unconditionally: if the magnitude
7092 // of the input value is small, the bit-twiddling we did above might
7093 // end up visibly changing the output. Fortunately, in that case, we
7094 // don't need to twiddle bits since the original input will convert
7095 // exactly to double-precision floating-point already. Therefore,
7096 // construct a conditional to use the original value if the top 11
7097 // bits are all sign-bit copies, and use the rounded value computed
7099 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64,
7100 SINT, DAG.getConstant(53, dl, MVT::i32));
7101 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64,
7102 Cond, DAG.getConstant(1, dl, MVT::i64));
7103 Cond = DAG.getSetCC(dl, MVT::i32,
7104 Cond, DAG.getConstant(1, dl, MVT::i64), ISD::SETUGT);
7106 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT);
7112 MachineFunction &MF = DAG.getMachineFunction();
7113 if (canReuseLoadAddress(SINT, MVT::i64, RLI, DAG)) {
7114 Bits = DAG.getLoad(MVT::f64, dl, RLI.Chain, RLI.Ptr, RLI.MPI,
7115 RLI.Alignment, RLI.MMOFlags(), RLI.AAInfo, RLI.Ranges);
7116 spliceIntoChain(RLI.ResChain, Bits.getValue(1), DAG);
7117 } else if (Subtarget.hasLFIWAX() &&
7118 canReuseLoadAddress(SINT, MVT::i32, RLI, DAG, ISD::SEXTLOAD)) {
7119 MachineMemOperand *MMO =
7120 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
7121 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
7122 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
7123 Bits = DAG.getMemIntrinsicNode(PPCISD::LFIWAX, dl,
7124 DAG.getVTList(MVT::f64, MVT::Other),
7125 Ops, MVT::i32, MMO);
7126 spliceIntoChain(RLI.ResChain, Bits.getValue(1), DAG);
7127 } else if (Subtarget.hasFPCVT() &&
7128 canReuseLoadAddress(SINT, MVT::i32, RLI, DAG, ISD::ZEXTLOAD)) {
7129 MachineMemOperand *MMO =
7130 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
7131 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
7132 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
7133 Bits = DAG.getMemIntrinsicNode(PPCISD::LFIWZX, dl,
7134 DAG.getVTList(MVT::f64, MVT::Other),
7135 Ops, MVT::i32, MMO);
7136 spliceIntoChain(RLI.ResChain, Bits.getValue(1), DAG);
7137 } else if (((Subtarget.hasLFIWAX() &&
7138 SINT.getOpcode() == ISD::SIGN_EXTEND) ||
7139 (Subtarget.hasFPCVT() &&
7140 SINT.getOpcode() == ISD::ZERO_EXTEND)) &&
7141 SINT.getOperand(0).getValueType() == MVT::i32) {
7142 MachineFrameInfo &MFI = MF.getFrameInfo();
7143 EVT PtrVT = getPointerTy(DAG.getDataLayout());
7145 int FrameIdx = MFI.CreateStackObject(4, 4, false);
7146 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
7149 DAG.getStore(DAG.getEntryNode(), dl, SINT.getOperand(0), FIdx,
7150 MachinePointerInfo::getFixedStack(
7151 DAG.getMachineFunction(), FrameIdx));
7153 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
7154 "Expected an i32 store");
7159 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx);
7162 MachineMemOperand *MMO =
7163 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
7164 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
7165 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
7166 Bits = DAG.getMemIntrinsicNode(SINT.getOpcode() == ISD::ZERO_EXTEND ?
7167 PPCISD::LFIWZX : PPCISD::LFIWAX,
7168 dl, DAG.getVTList(MVT::f64, MVT::Other),
7169 Ops, MVT::i32, MMO);
7171 Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT);
7173 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Bits);
7175 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
7176 FP = DAG.getNode(ISD::FP_ROUND, dl,
7177 MVT::f32, FP, DAG.getIntPtrConstant(0, dl));
7181 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
7182 "Unhandled INT_TO_FP type in custom expander!");
7183 // Since we only generate this in 64-bit mode, we can take advantage of
7184 // 64-bit registers. In particular, sign extend the input value into the
7185 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
7186 // then lfd it and fcfid it.
7187 MachineFunction &MF = DAG.getMachineFunction();
7188 MachineFrameInfo &MFI = MF.getFrameInfo();
7189 EVT PtrVT = getPointerTy(MF.getDataLayout());
7192 if (Subtarget.hasLFIWAX() || Subtarget.hasFPCVT()) {
7195 if (!(ReusingLoad = canReuseLoadAddress(Op.getOperand(0), MVT::i32, RLI,
7197 int FrameIdx = MFI.CreateStackObject(4, 4, false);
7198 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
7201 DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), FIdx,
7202 MachinePointerInfo::getFixedStack(
7203 DAG.getMachineFunction(), FrameIdx));
7205 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
7206 "Expected an i32 store");
7211 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx);
7215 MachineMemOperand *MMO =
7216 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
7217 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
7218 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
7219 Ld = DAG.getMemIntrinsicNode(Op.getOpcode() == ISD::UINT_TO_FP ?
7220 PPCISD::LFIWZX : PPCISD::LFIWAX,
7221 dl, DAG.getVTList(MVT::f64, MVT::Other),
7222 Ops, MVT::i32, MMO);
7224 spliceIntoChain(RLI.ResChain, Ld.getValue(1), DAG);
7226 assert(Subtarget.isPPC64() &&
7227 "i32->FP without LFIWAX supported only on PPC64");
7229 int FrameIdx = MFI.CreateStackObject(8, 8, false);
7230 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
7232 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64,
7235 // STD the extended value into the stack slot.
7236 SDValue Store = DAG.getStore(
7237 DAG.getEntryNode(), dl, Ext64, FIdx,
7238 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx));
7240 // Load the value as a double.
7242 MVT::f64, dl, Store, FIdx,
7243 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx));
7246 // FCFID it and return it.
7247 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Ld);
7248 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
7249 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP,
7250 DAG.getIntPtrConstant(0, dl));
7254 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
7255 SelectionDAG &DAG) const {
7258 The rounding mode is in bits 30:31 of FPSR, and has the following
7265 FLT_ROUNDS, on the other hand, expects the following:
7272 To perform the conversion, we do:
7273 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
7276 MachineFunction &MF = DAG.getMachineFunction();
7277 EVT VT = Op.getValueType();
7278 EVT PtrVT = getPointerTy(MF.getDataLayout());
7280 // Save FP Control Word to register
7282 MVT::f64, // return register
7283 MVT::Glue // unused in this context
7285 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, None);
7287 // Save FP register to stack slot
7288 int SSFI = MF.getFrameInfo().CreateStackObject(8, 8, false);
7289 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
7290 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain, StackSlot,
7291 MachinePointerInfo());
7293 // Load FP Control Word from low 32 bits of stack slot.
7294 SDValue Four = DAG.getConstant(4, dl, PtrVT);
7295 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
7296 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo());
7298 // Transform as necessary
7300 DAG.getNode(ISD::AND, dl, MVT::i32,
7301 CWD, DAG.getConstant(3, dl, MVT::i32));
7303 DAG.getNode(ISD::SRL, dl, MVT::i32,
7304 DAG.getNode(ISD::AND, dl, MVT::i32,
7305 DAG.getNode(ISD::XOR, dl, MVT::i32,
7306 CWD, DAG.getConstant(3, dl, MVT::i32)),
7307 DAG.getConstant(3, dl, MVT::i32)),
7308 DAG.getConstant(1, dl, MVT::i32));
7311 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
7313 return DAG.getNode((VT.getSizeInBits() < 16 ?
7314 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
7317 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
7318 EVT VT = Op.getValueType();
7319 unsigned BitWidth = VT.getSizeInBits();
7321 assert(Op.getNumOperands() == 3 &&
7322 VT == Op.getOperand(1).getValueType() &&
7325 // Expand into a bunch of logical ops. Note that these ops
7326 // depend on the PPC behavior for oversized shift amounts.
7327 SDValue Lo = Op.getOperand(0);
7328 SDValue Hi = Op.getOperand(1);
7329 SDValue Amt = Op.getOperand(2);
7330 EVT AmtVT = Amt.getValueType();
7332 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
7333 DAG.getConstant(BitWidth, dl, AmtVT), Amt);
7334 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
7335 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
7336 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
7337 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
7338 DAG.getConstant(-BitWidth, dl, AmtVT));
7339 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
7340 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
7341 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
7342 SDValue OutOps[] = { OutLo, OutHi };
7343 return DAG.getMergeValues(OutOps, dl);
7346 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
7347 EVT VT = Op.getValueType();
7349 unsigned BitWidth = VT.getSizeInBits();
7350 assert(Op.getNumOperands() == 3 &&
7351 VT == Op.getOperand(1).getValueType() &&
7354 // Expand into a bunch of logical ops. Note that these ops
7355 // depend on the PPC behavior for oversized shift amounts.
7356 SDValue Lo = Op.getOperand(0);
7357 SDValue Hi = Op.getOperand(1);
7358 SDValue Amt = Op.getOperand(2);
7359 EVT AmtVT = Amt.getValueType();
7361 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
7362 DAG.getConstant(BitWidth, dl, AmtVT), Amt);
7363 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
7364 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
7365 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
7366 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
7367 DAG.getConstant(-BitWidth, dl, AmtVT));
7368 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
7369 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
7370 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
7371 SDValue OutOps[] = { OutLo, OutHi };
7372 return DAG.getMergeValues(OutOps, dl);
7375 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
7377 EVT VT = Op.getValueType();
7378 unsigned BitWidth = VT.getSizeInBits();
7379 assert(Op.getNumOperands() == 3 &&
7380 VT == Op.getOperand(1).getValueType() &&
7383 // Expand into a bunch of logical ops, followed by a select_cc.
7384 SDValue Lo = Op.getOperand(0);
7385 SDValue Hi = Op.getOperand(1);
7386 SDValue Amt = Op.getOperand(2);
7387 EVT AmtVT = Amt.getValueType();
7389 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
7390 DAG.getConstant(BitWidth, dl, AmtVT), Amt);
7391 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
7392 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
7393 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
7394 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
7395 DAG.getConstant(-BitWidth, dl, AmtVT));
7396 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
7397 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
7398 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, dl, AmtVT),
7399 Tmp4, Tmp6, ISD::SETLE);
7400 SDValue OutOps[] = { OutLo, OutHi };
7401 return DAG.getMergeValues(OutOps, dl);
7404 //===----------------------------------------------------------------------===//
7405 // Vector related lowering.
7408 /// BuildSplatI - Build a canonical splati of Val with an element size of
7409 /// SplatSize. Cast the result to VT.
7410 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
7411 SelectionDAG &DAG, const SDLoc &dl) {
7412 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
7414 static const MVT VTys[] = { // canonical VT to use for each size.
7415 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
7418 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
7420 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
7424 EVT CanonicalVT = VTys[SplatSize-1];
7426 // Build a canonical splat for this value.
7427 return DAG.getBitcast(ReqVT, DAG.getConstant(Val, dl, CanonicalVT));
7430 /// BuildIntrinsicOp - Return a unary operator intrinsic node with the
7431 /// specified intrinsic ID.
7432 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op, SelectionDAG &DAG,
7433 const SDLoc &dl, EVT DestVT = MVT::Other) {
7434 if (DestVT == MVT::Other) DestVT = Op.getValueType();
7435 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
7436 DAG.getConstant(IID, dl, MVT::i32), Op);
7439 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
7440 /// specified intrinsic ID.
7441 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
7442 SelectionDAG &DAG, const SDLoc &dl,
7443 EVT DestVT = MVT::Other) {
7444 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
7445 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
7446 DAG.getConstant(IID, dl, MVT::i32), LHS, RHS);
7449 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
7450 /// specified intrinsic ID.
7451 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
7452 SDValue Op2, SelectionDAG &DAG, const SDLoc &dl,
7453 EVT DestVT = MVT::Other) {
7454 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
7455 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
7456 DAG.getConstant(IID, dl, MVT::i32), Op0, Op1, Op2);
7459 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
7460 /// amount. The result has the specified value type.
7461 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt, EVT VT,
7462 SelectionDAG &DAG, const SDLoc &dl) {
7463 // Force LHS/RHS to be the right type.
7464 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
7465 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
7468 for (unsigned i = 0; i != 16; ++i)
7470 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
7471 return DAG.getNode(ISD::BITCAST, dl, VT, T);
7474 /// Do we have an efficient pattern in a .td file for this node?
7476 /// \param V - pointer to the BuildVectorSDNode being matched
7477 /// \param HasDirectMove - does this subtarget have VSR <-> GPR direct moves?
7479 /// There are some patterns where it is beneficial to keep a BUILD_VECTOR
7480 /// node as a BUILD_VECTOR node rather than expanding it. The patterns where
7481 /// the opposite is true (expansion is beneficial) are:
7482 /// - The node builds a vector out of integers that are not 32 or 64-bits
7483 /// - The node builds a vector out of constants
7484 /// - The node is a "load-and-splat"
7485 /// In all other cases, we will choose to keep the BUILD_VECTOR.
7486 static bool haveEfficientBuildVectorPattern(BuildVectorSDNode *V,
7489 EVT VecVT = V->getValueType(0);
7490 bool RightType = VecVT == MVT::v2f64 ||
7491 (HasP8Vector && VecVT == MVT::v4f32) ||
7492 (HasDirectMove && (VecVT == MVT::v2i64 || VecVT == MVT::v4i32));
7496 bool IsSplat = true;
7497 bool IsLoad = false;
7498 SDValue Op0 = V->getOperand(0);
7500 // This function is called in a block that confirms the node is not a constant
7501 // splat. So a constant BUILD_VECTOR here means the vector is built out of
7502 // different constants.
7503 if (V->isConstant())
7505 for (int i = 0, e = V->getNumOperands(); i < e; ++i) {
7506 if (V->getOperand(i).isUndef())
7508 // We want to expand nodes that represent load-and-splat even if the
7509 // loaded value is a floating point truncation or conversion to int.
7510 if (V->getOperand(i).getOpcode() == ISD::LOAD ||
7511 (V->getOperand(i).getOpcode() == ISD::FP_ROUND &&
7512 V->getOperand(i).getOperand(0).getOpcode() == ISD::LOAD) ||
7513 (V->getOperand(i).getOpcode() == ISD::FP_TO_SINT &&
7514 V->getOperand(i).getOperand(0).getOpcode() == ISD::LOAD) ||
7515 (V->getOperand(i).getOpcode() == ISD::FP_TO_UINT &&
7516 V->getOperand(i).getOperand(0).getOpcode() == ISD::LOAD))
7518 // If the operands are different or the input is not a load and has more
7519 // uses than just this BV node, then it isn't a splat.
7520 if (V->getOperand(i) != Op0 ||
7521 (!IsLoad && !V->isOnlyUserOf(V->getOperand(i).getNode())))
7524 return !(IsSplat && IsLoad);
7527 // If this is a case we can't handle, return null and let the default
7528 // expansion code take care of it. If we CAN select this case, and if it
7529 // selects to a single instruction, return Op. Otherwise, if we can codegen
7530 // this case more efficiently than a constant pool load, lower it to the
7531 // sequence of ops that should be used.
7532 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
7533 SelectionDAG &DAG) const {
7535 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
7536 assert(BVN && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
7538 if (Subtarget.hasQPX() && Op.getValueType() == MVT::v4i1) {
7539 // We first build an i32 vector, load it into a QPX register,
7540 // then convert it to a floating-point vector and compare it
7541 // to a zero vector to get the boolean result.
7542 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
7543 int FrameIdx = MFI.CreateStackObject(16, 16, false);
7544 MachinePointerInfo PtrInfo =
7545 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx);
7546 EVT PtrVT = getPointerTy(DAG.getDataLayout());
7547 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
7549 assert(BVN->getNumOperands() == 4 &&
7550 "BUILD_VECTOR for v4i1 does not have 4 operands");
7552 bool IsConst = true;
7553 for (unsigned i = 0; i < 4; ++i) {
7554 if (BVN->getOperand(i).isUndef()) continue;
7555 if (!isa<ConstantSDNode>(BVN->getOperand(i))) {
7563 ConstantFP::get(Type::getFloatTy(*DAG.getContext()), 1.0);
7565 ConstantFP::get(Type::getFloatTy(*DAG.getContext()), -1.0);
7568 for (unsigned i = 0; i < 4; ++i) {
7569 if (BVN->getOperand(i).isUndef())
7570 CV[i] = UndefValue::get(Type::getFloatTy(*DAG.getContext()));
7571 else if (isNullConstant(BVN->getOperand(i)))
7577 Constant *CP = ConstantVector::get(CV);
7578 SDValue CPIdx = DAG.getConstantPool(CP, getPointerTy(DAG.getDataLayout()),
7579 16 /* alignment */);
7581 SDValue Ops[] = {DAG.getEntryNode(), CPIdx};
7582 SDVTList VTs = DAG.getVTList({MVT::v4i1, /*chain*/ MVT::Other});
7583 return DAG.getMemIntrinsicNode(
7584 PPCISD::QVLFSb, dl, VTs, Ops, MVT::v4f32,
7585 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
7588 SmallVector<SDValue, 4> Stores;
7589 for (unsigned i = 0; i < 4; ++i) {
7590 if (BVN->getOperand(i).isUndef()) continue;
7592 unsigned Offset = 4*i;
7593 SDValue Idx = DAG.getConstant(Offset, dl, FIdx.getValueType());
7594 Idx = DAG.getNode(ISD::ADD, dl, FIdx.getValueType(), FIdx, Idx);
7596 unsigned StoreSize = BVN->getOperand(i).getValueType().getStoreSize();
7597 if (StoreSize > 4) {
7599 DAG.getTruncStore(DAG.getEntryNode(), dl, BVN->getOperand(i), Idx,
7600 PtrInfo.getWithOffset(Offset), MVT::i32));
7602 SDValue StoreValue = BVN->getOperand(i);
7604 StoreValue = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, StoreValue);
7606 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl, StoreValue, Idx,
7607 PtrInfo.getWithOffset(Offset)));
7612 if (!Stores.empty())
7613 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
7615 StoreChain = DAG.getEntryNode();
7617 // Now load from v4i32 into the QPX register; this will extend it to
7618 // v4i64 but not yet convert it to a floating point. Nevertheless, this
7619 // is typed as v4f64 because the QPX register integer states are not
7620 // explicitly represented.
7622 SDValue Ops[] = {StoreChain,
7623 DAG.getConstant(Intrinsic::ppc_qpx_qvlfiwz, dl, MVT::i32),
7625 SDVTList VTs = DAG.getVTList({MVT::v4f64, /*chain*/ MVT::Other});
7627 SDValue LoadedVect = DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN,
7628 dl, VTs, Ops, MVT::v4i32, PtrInfo);
7629 LoadedVect = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f64,
7630 DAG.getConstant(Intrinsic::ppc_qpx_qvfcfidu, dl, MVT::i32),
7633 SDValue FPZeros = DAG.getConstantFP(0.0, dl, MVT::v4f64);
7635 return DAG.getSetCC(dl, MVT::v4i1, LoadedVect, FPZeros, ISD::SETEQ);
7638 // All other QPX vectors are handled by generic code.
7639 if (Subtarget.hasQPX())
7642 // Check if this is a splat of a constant value.
7643 APInt APSplatBits, APSplatUndef;
7644 unsigned SplatBitSize;
7646 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
7647 HasAnyUndefs, 0, !Subtarget.isLittleEndian()) ||
7648 SplatBitSize > 32) {
7649 // BUILD_VECTOR nodes that are not constant splats of up to 32-bits can be
7650 // lowered to VSX instructions under certain conditions.
7651 // Without VSX, there is no pattern more efficient than expanding the node.
7652 if (Subtarget.hasVSX() &&
7653 haveEfficientBuildVectorPattern(BVN, Subtarget.hasDirectMove(),
7654 Subtarget.hasP8Vector()))
7659 unsigned SplatBits = APSplatBits.getZExtValue();
7660 unsigned SplatUndef = APSplatUndef.getZExtValue();
7661 unsigned SplatSize = SplatBitSize / 8;
7663 // First, handle single instruction cases.
7666 if (SplatBits == 0) {
7667 // Canonicalize all zero vectors to be v4i32.
7668 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
7669 SDValue Z = DAG.getConstant(0, dl, MVT::v4i32);
7670 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
7675 // We have XXSPLTIB for constant splats one byte wide
7676 if (Subtarget.hasP9Vector() && SplatSize == 1) {
7677 // This is a splat of 1-byte elements with some elements potentially undef.
7678 // Rather than trying to match undef in the SDAG patterns, ensure that all
7679 // elements are the same constant.
7680 if (HasAnyUndefs || ISD::isBuildVectorAllOnes(BVN)) {
7681 SmallVector<SDValue, 16> Ops(16, DAG.getConstant(SplatBits,
7683 SDValue NewBV = DAG.getBuildVector(MVT::v16i8, dl, Ops);
7684 if (Op.getValueType() != MVT::v16i8)
7685 return DAG.getBitcast(Op.getValueType(), NewBV);
7689 // BuildVectorSDNode::isConstantSplat() is actually pretty smart. It'll
7690 // detect that constant splats like v8i16: 0xABAB are really just splats
7691 // of a 1-byte constant. In this case, we need to convert the node to a
7692 // splat of v16i8 and a bitcast.
7693 if (Op.getValueType() != MVT::v16i8)
7694 return DAG.getBitcast(Op.getValueType(),
7695 DAG.getConstant(SplatBits, dl, MVT::v16i8));
7700 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
7701 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
7703 if (SextVal >= -16 && SextVal <= 15)
7704 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
7706 // Two instruction sequences.
7708 // If this value is in the range [-32,30] and is even, use:
7709 // VSPLTI[bhw](val/2) + VSPLTI[bhw](val/2)
7710 // If this value is in the range [17,31] and is odd, use:
7711 // VSPLTI[bhw](val-16) - VSPLTI[bhw](-16)
7712 // If this value is in the range [-31,-17] and is odd, use:
7713 // VSPLTI[bhw](val+16) + VSPLTI[bhw](-16)
7714 // Note the last two are three-instruction sequences.
7715 if (SextVal >= -32 && SextVal <= 31) {
7716 // To avoid having these optimizations undone by constant folding,
7717 // we convert to a pseudo that will be expanded later into one of
7719 SDValue Elt = DAG.getConstant(SextVal, dl, MVT::i32);
7720 EVT VT = (SplatSize == 1 ? MVT::v16i8 :
7721 (SplatSize == 2 ? MVT::v8i16 : MVT::v4i32));
7722 SDValue EltSize = DAG.getConstant(SplatSize, dl, MVT::i32);
7723 SDValue RetVal = DAG.getNode(PPCISD::VADD_SPLAT, dl, VT, Elt, EltSize);
7724 if (VT == Op.getValueType())
7727 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), RetVal);
7730 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
7731 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
7733 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
7734 // Make -1 and vspltisw -1:
7735 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
7737 // Make the VSLW intrinsic, computing 0x8000_0000.
7738 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
7741 // xor by OnesV to invert it.
7742 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
7743 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
7746 // Check to see if this is a wide variety of vsplti*, binop self cases.
7747 static const signed char SplatCsts[] = {
7748 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
7749 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
7752 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
7753 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
7754 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
7755 int i = SplatCsts[idx];
7757 // Figure out what shift amount will be used by altivec if shifted by i in
7759 unsigned TypeShiftAmt = i & (SplatBitSize-1);
7761 // vsplti + shl self.
7762 if (SextVal == (int)((unsigned)i << TypeShiftAmt)) {
7763 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
7764 static const unsigned IIDs[] = { // Intrinsic to use for each size.
7765 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
7766 Intrinsic::ppc_altivec_vslw
7768 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
7769 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
7772 // vsplti + srl self.
7773 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
7774 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
7775 static const unsigned IIDs[] = { // Intrinsic to use for each size.
7776 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
7777 Intrinsic::ppc_altivec_vsrw
7779 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
7780 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
7783 // vsplti + sra self.
7784 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
7785 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
7786 static const unsigned IIDs[] = { // Intrinsic to use for each size.
7787 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
7788 Intrinsic::ppc_altivec_vsraw
7790 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
7791 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
7794 // vsplti + rol self.
7795 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
7796 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
7797 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
7798 static const unsigned IIDs[] = { // Intrinsic to use for each size.
7799 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
7800 Intrinsic::ppc_altivec_vrlw
7802 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
7803 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
7806 // t = vsplti c, result = vsldoi t, t, 1
7807 if (SextVal == (int)(((unsigned)i << 8) | (i < 0 ? 0xFF : 0))) {
7808 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
7809 unsigned Amt = Subtarget.isLittleEndian() ? 15 : 1;
7810 return BuildVSLDOI(T, T, Amt, Op.getValueType(), DAG, dl);
7812 // t = vsplti c, result = vsldoi t, t, 2
7813 if (SextVal == (int)(((unsigned)i << 16) | (i < 0 ? 0xFFFF : 0))) {
7814 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
7815 unsigned Amt = Subtarget.isLittleEndian() ? 14 : 2;
7816 return BuildVSLDOI(T, T, Amt, Op.getValueType(), DAG, dl);
7818 // t = vsplti c, result = vsldoi t, t, 3
7819 if (SextVal == (int)(((unsigned)i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
7820 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
7821 unsigned Amt = Subtarget.isLittleEndian() ? 13 : 3;
7822 return BuildVSLDOI(T, T, Amt, Op.getValueType(), DAG, dl);
7829 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
7830 /// the specified operations to build the shuffle.
7831 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
7832 SDValue RHS, SelectionDAG &DAG,
7834 unsigned OpNum = (PFEntry >> 26) & 0x0F;
7835 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
7836 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
7839 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
7851 if (OpNum == OP_COPY) {
7852 if (LHSID == (1*9+2)*9+3) return LHS;
7853 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
7857 SDValue OpLHS, OpRHS;
7858 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
7859 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
7863 default: llvm_unreachable("Unknown i32 permute!");
7865 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
7866 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
7867 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
7868 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
7871 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
7872 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
7873 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
7874 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
7877 for (unsigned i = 0; i != 16; ++i)
7878 ShufIdxs[i] = (i&3)+0;
7881 for (unsigned i = 0; i != 16; ++i)
7882 ShufIdxs[i] = (i&3)+4;
7885 for (unsigned i = 0; i != 16; ++i)
7886 ShufIdxs[i] = (i&3)+8;
7889 for (unsigned i = 0; i != 16; ++i)
7890 ShufIdxs[i] = (i&3)+12;
7893 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
7895 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
7897 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
7899 EVT VT = OpLHS.getValueType();
7900 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
7901 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
7902 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
7903 return DAG.getNode(ISD::BITCAST, dl, VT, T);
7906 /// lowerToVINSERTB - Return the SDValue if this VECTOR_SHUFFLE can be handled
7907 /// by the VINSERTB instruction introduced in ISA 3.0, else just return default
7909 SDValue PPCTargetLowering::lowerToVINSERTB(ShuffleVectorSDNode *N,
7910 SelectionDAG &DAG) const {
7911 const unsigned BytesInVector = 16;
7912 bool IsLE = Subtarget.isLittleEndian();
7914 SDValue V1 = N->getOperand(0);
7915 SDValue V2 = N->getOperand(1);
7916 unsigned ShiftElts = 0, InsertAtByte = 0;
7919 // Shifts required to get the byte we want at element 7.
7920 unsigned LittleEndianShifts[] = {8, 7, 6, 5, 4, 3, 2, 1,
7921 0, 15, 14, 13, 12, 11, 10, 9};
7922 unsigned BigEndianShifts[] = {9, 10, 11, 12, 13, 14, 15, 0,
7923 1, 2, 3, 4, 5, 6, 7, 8};
7925 ArrayRef<int> Mask = N->getMask();
7926 int OriginalOrder[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15};
7928 // For each mask element, find out if we're just inserting something
7929 // from V2 into V1 or vice versa.
7930 // Possible permutations inserting an element from V2 into V1:
7931 // X, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
7932 // 0, X, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
7934 // 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, X
7935 // Inserting from V1 into V2 will be similar, except mask range will be
7938 bool FoundCandidate = false;
7939 // If both vector operands for the shuffle are the same vector, the mask
7940 // will contain only elements from the first one and the second one will be
7942 unsigned VINSERTBSrcElem = IsLE ? 8 : 7;
7943 // Go through the mask of half-words to find an element that's being moved
7944 // from one vector to the other.
7945 for (unsigned i = 0; i < BytesInVector; ++i) {
7946 unsigned CurrentElement = Mask[i];
7947 // If 2nd operand is undefined, we should only look for element 7 in the
7949 if (V2.isUndef() && CurrentElement != VINSERTBSrcElem)
7952 bool OtherElementsInOrder = true;
7953 // Examine the other elements in the Mask to see if they're in original
7955 for (unsigned j = 0; j < BytesInVector; ++j) {
7958 // If CurrentElement is from V1 [0,15], then we the rest of the Mask to be
7959 // from V2 [16,31] and vice versa. Unless the 2nd operand is undefined,
7960 // in which we always assume we're always picking from the 1st operand.
7962 (!V2.isUndef() && CurrentElement < BytesInVector) ? BytesInVector : 0;
7963 if (Mask[j] != OriginalOrder[j] + MaskOffset) {
7964 OtherElementsInOrder = false;
7968 // If other elements are in original order, we record the number of shifts
7969 // we need to get the element we want into element 7. Also record which byte
7970 // in the vector we should insert into.
7971 if (OtherElementsInOrder) {
7972 // If 2nd operand is undefined, we assume no shifts and no swapping.
7977 // Only need the last 4-bits for shifts because operands will be swapped if CurrentElement is >= 2^4.
7978 ShiftElts = IsLE ? LittleEndianShifts[CurrentElement & 0xF]
7979 : BigEndianShifts[CurrentElement & 0xF];
7980 Swap = CurrentElement < BytesInVector;
7982 InsertAtByte = IsLE ? BytesInVector - (i + 1) : i;
7983 FoundCandidate = true;
7988 if (!FoundCandidate)
7991 // Candidate found, construct the proper SDAG sequence with VINSERTB,
7992 // optionally with VECSHL if shift is required.
7998 SDValue Shl = DAG.getNode(PPCISD::VECSHL, dl, MVT::v16i8, V2, V2,
7999 DAG.getConstant(ShiftElts, dl, MVT::i32));
8000 return DAG.getNode(PPCISD::VECINSERT, dl, MVT::v16i8, V1, Shl,
8001 DAG.getConstant(InsertAtByte, dl, MVT::i32));
8003 return DAG.getNode(PPCISD::VECINSERT, dl, MVT::v16i8, V1, V2,
8004 DAG.getConstant(InsertAtByte, dl, MVT::i32));
8007 /// lowerToVINSERTH - Return the SDValue if this VECTOR_SHUFFLE can be handled
8008 /// by the VINSERTH instruction introduced in ISA 3.0, else just return default
8010 SDValue PPCTargetLowering::lowerToVINSERTH(ShuffleVectorSDNode *N,
8011 SelectionDAG &DAG) const {
8012 const unsigned NumHalfWords = 8;
8013 const unsigned BytesInVector = NumHalfWords * 2;
8014 // Check that the shuffle is on half-words.
8015 if (!isNByteElemShuffleMask(N, 2, 1))
8018 bool IsLE = Subtarget.isLittleEndian();
8020 SDValue V1 = N->getOperand(0);
8021 SDValue V2 = N->getOperand(1);
8022 unsigned ShiftElts = 0, InsertAtByte = 0;
8025 // Shifts required to get the half-word we want at element 3.
8026 unsigned LittleEndianShifts[] = {4, 3, 2, 1, 0, 7, 6, 5};
8027 unsigned BigEndianShifts[] = {5, 6, 7, 0, 1, 2, 3, 4};
8030 uint32_t OriginalOrderLow = 0x1234567;
8031 uint32_t OriginalOrderHigh = 0x89ABCDEF;
8032 // Now we look at mask elements 0,2,4,6,8,10,12,14. Pack the mask into a
8033 // 32-bit space, only need 4-bit nibbles per element.
8034 for (unsigned i = 0; i < NumHalfWords; ++i) {
8035 unsigned MaskShift = (NumHalfWords - 1 - i) * 4;
8036 Mask |= ((uint32_t)(N->getMaskElt(i * 2) / 2) << MaskShift);
8039 // For each mask element, find out if we're just inserting something
8040 // from V2 into V1 or vice versa. Possible permutations inserting an element
8042 // X, 1, 2, 3, 4, 5, 6, 7
8043 // 0, X, 2, 3, 4, 5, 6, 7
8044 // 0, 1, X, 3, 4, 5, 6, 7
8045 // 0, 1, 2, X, 4, 5, 6, 7
8046 // 0, 1, 2, 3, X, 5, 6, 7
8047 // 0, 1, 2, 3, 4, X, 6, 7
8048 // 0, 1, 2, 3, 4, 5, X, 7
8049 // 0, 1, 2, 3, 4, 5, 6, X
8050 // Inserting from V1 into V2 will be similar, except mask range will be [8,15].
8052 bool FoundCandidate = false;
8053 // Go through the mask of half-words to find an element that's being moved
8054 // from one vector to the other.
8055 for (unsigned i = 0; i < NumHalfWords; ++i) {
8056 unsigned MaskShift = (NumHalfWords - 1 - i) * 4;
8057 uint32_t MaskOneElt = (Mask >> MaskShift) & 0xF;
8058 uint32_t MaskOtherElts = ~(0xF << MaskShift);
8059 uint32_t TargetOrder = 0x0;
8061 // If both vector operands for the shuffle are the same vector, the mask
8062 // will contain only elements from the first one and the second one will be
8066 unsigned VINSERTHSrcElem = IsLE ? 4 : 3;
8067 TargetOrder = OriginalOrderLow;
8069 // Skip if not the correct element or mask of other elements don't equal
8070 // to our expected order.
8071 if (MaskOneElt == VINSERTHSrcElem &&
8072 (Mask & MaskOtherElts) == (TargetOrder & MaskOtherElts)) {
8073 InsertAtByte = IsLE ? BytesInVector - (i + 1) * 2 : i * 2;
8074 FoundCandidate = true;
8077 } else { // If both operands are defined.
8078 // Target order is [8,15] if the current mask is between [0,7].
8080 (MaskOneElt < NumHalfWords) ? OriginalOrderHigh : OriginalOrderLow;
8081 // Skip if mask of other elements don't equal our expected order.
8082 if ((Mask & MaskOtherElts) == (TargetOrder & MaskOtherElts)) {
8083 // We only need the last 3 bits for the number of shifts.
8084 ShiftElts = IsLE ? LittleEndianShifts[MaskOneElt & 0x7]
8085 : BigEndianShifts[MaskOneElt & 0x7];
8086 InsertAtByte = IsLE ? BytesInVector - (i + 1) * 2 : i * 2;
8087 Swap = MaskOneElt < NumHalfWords;
8088 FoundCandidate = true;
8094 if (!FoundCandidate)
8097 // Candidate found, construct the proper SDAG sequence with VINSERTH,
8098 // optionally with VECSHL if shift is required.
8103 SDValue Conv1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
8105 // Double ShiftElts because we're left shifting on v16i8 type.
8106 SDValue Shl = DAG.getNode(PPCISD::VECSHL, dl, MVT::v16i8, V2, V2,
8107 DAG.getConstant(2 * ShiftElts, dl, MVT::i32));
8108 SDValue Conv2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, Shl);
8109 SDValue Ins = DAG.getNode(PPCISD::VECINSERT, dl, MVT::v8i16, Conv1, Conv2,
8110 DAG.getConstant(InsertAtByte, dl, MVT::i32));
8111 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, Ins);
8113 SDValue Conv2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
8114 SDValue Ins = DAG.getNode(PPCISD::VECINSERT, dl, MVT::v8i16, Conv1, Conv2,
8115 DAG.getConstant(InsertAtByte, dl, MVT::i32));
8116 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, Ins);
8119 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
8120 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
8121 /// return the code it can be lowered into. Worst case, it can always be
8122 /// lowered into a vperm.
8123 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
8124 SelectionDAG &DAG) const {
8126 SDValue V1 = Op.getOperand(0);
8127 SDValue V2 = Op.getOperand(1);
8128 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8129 EVT VT = Op.getValueType();
8130 bool isLittleEndian = Subtarget.isLittleEndian();
8132 unsigned ShiftElts, InsertAtByte;
8134 if (Subtarget.hasP9Vector() &&
8135 PPC::isXXINSERTWMask(SVOp, ShiftElts, InsertAtByte, Swap,
8139 SDValue Conv1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, V1);
8140 SDValue Conv2 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, V2);
8142 SDValue Shl = DAG.getNode(PPCISD::VECSHL, dl, MVT::v4i32, Conv2, Conv2,
8143 DAG.getConstant(ShiftElts, dl, MVT::i32));
8144 SDValue Ins = DAG.getNode(PPCISD::VECINSERT, dl, MVT::v4i32, Conv1, Shl,
8145 DAG.getConstant(InsertAtByte, dl, MVT::i32));
8146 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, Ins);
8148 SDValue Ins = DAG.getNode(PPCISD::VECINSERT, dl, MVT::v4i32, Conv1, Conv2,
8149 DAG.getConstant(InsertAtByte, dl, MVT::i32));
8150 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, Ins);
8153 if (Subtarget.hasP9Altivec()) {
8155 if ((NewISDNode = lowerToVINSERTH(SVOp, DAG)))
8158 if ((NewISDNode = lowerToVINSERTB(SVOp, DAG)))
8162 if (Subtarget.hasVSX() &&
8163 PPC::isXXSLDWIShuffleMask(SVOp, ShiftElts, Swap, isLittleEndian)) {
8166 SDValue Conv1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, V1);
8168 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, V2.isUndef() ? V1 : V2);
8170 SDValue Shl = DAG.getNode(PPCISD::VECSHL, dl, MVT::v4i32, Conv1, Conv2,
8171 DAG.getConstant(ShiftElts, dl, MVT::i32));
8172 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, Shl);
8175 if (Subtarget.hasVSX() &&
8176 PPC::isXXPERMDIShuffleMask(SVOp, ShiftElts, Swap, isLittleEndian)) {
8179 SDValue Conv1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1);
8181 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2.isUndef() ? V1 : V2);
8183 SDValue PermDI = DAG.getNode(PPCISD::XXPERMDI, dl, MVT::v2i64, Conv1, Conv2,
8184 DAG.getConstant(ShiftElts, dl, MVT::i32));
8185 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, PermDI);
8188 if (Subtarget.hasP9Vector()) {
8189 if (PPC::isXXBRHShuffleMask(SVOp)) {
8190 SDValue Conv = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
8191 SDValue ReveHWord = DAG.getNode(PPCISD::XXREVERSE, dl, MVT::v8i16, Conv);
8192 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, ReveHWord);
8193 } else if (PPC::isXXBRWShuffleMask(SVOp)) {
8194 SDValue Conv = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, V1);
8195 SDValue ReveWord = DAG.getNode(PPCISD::XXREVERSE, dl, MVT::v4i32, Conv);
8196 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, ReveWord);
8197 } else if (PPC::isXXBRDShuffleMask(SVOp)) {
8198 SDValue Conv = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1);
8199 SDValue ReveDWord = DAG.getNode(PPCISD::XXREVERSE, dl, MVT::v2i64, Conv);
8200 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, ReveDWord);
8201 } else if (PPC::isXXBRQShuffleMask(SVOp)) {
8202 SDValue Conv = DAG.getNode(ISD::BITCAST, dl, MVT::v1i128, V1);
8203 SDValue ReveQWord = DAG.getNode(PPCISD::XXREVERSE, dl, MVT::v1i128, Conv);
8204 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, ReveQWord);
8208 if (Subtarget.hasVSX()) {
8209 if (V2.isUndef() && PPC::isSplatShuffleMask(SVOp, 4)) {
8210 int SplatIdx = PPC::getVSPLTImmediate(SVOp, 4, DAG);
8212 // If the source for the shuffle is a scalar_to_vector that came from a
8213 // 32-bit load, it will have used LXVWSX so we don't need to splat again.
8214 if (Subtarget.hasP9Vector() &&
8215 ((isLittleEndian && SplatIdx == 3) ||
8216 (!isLittleEndian && SplatIdx == 0))) {
8217 SDValue Src = V1.getOperand(0);
8218 if (Src.getOpcode() == ISD::SCALAR_TO_VECTOR &&
8219 Src.getOperand(0).getOpcode() == ISD::LOAD &&
8220 Src.getOperand(0).hasOneUse())
8223 SDValue Conv = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, V1);
8224 SDValue Splat = DAG.getNode(PPCISD::XXSPLT, dl, MVT::v4i32, Conv,
8225 DAG.getConstant(SplatIdx, dl, MVT::i32));
8226 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, Splat);
8229 // Left shifts of 8 bytes are actually swaps. Convert accordingly.
8230 if (V2.isUndef() && PPC::isVSLDOIShuffleMask(SVOp, 1, DAG) == 8) {
8231 SDValue Conv = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
8232 SDValue Swap = DAG.getNode(PPCISD::SWAP_NO_CHAIN, dl, MVT::v2f64, Conv);
8233 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, Swap);
8237 if (Subtarget.hasQPX()) {
8238 if (VT.getVectorNumElements() != 4)
8241 if (V2.isUndef()) V2 = V1;
8243 int AlignIdx = PPC::isQVALIGNIShuffleMask(SVOp);
8244 if (AlignIdx != -1) {
8245 return DAG.getNode(PPCISD::QVALIGNI, dl, VT, V1, V2,
8246 DAG.getConstant(AlignIdx, dl, MVT::i32));
8247 } else if (SVOp->isSplat()) {
8248 int SplatIdx = SVOp->getSplatIndex();
8249 if (SplatIdx >= 4) {
8254 return DAG.getNode(PPCISD::QVESPLATI, dl, VT, V1,
8255 DAG.getConstant(SplatIdx, dl, MVT::i32));
8258 // Lower this into a qvgpci/qvfperm pair.
8260 // Compute the qvgpci literal
8262 for (unsigned i = 0; i < 4; ++i) {
8263 int m = SVOp->getMaskElt(i);
8264 unsigned mm = m >= 0 ? (unsigned) m : i;
8265 idx |= mm << (3-i)*3;
8268 SDValue V3 = DAG.getNode(PPCISD::QVGPCI, dl, MVT::v4f64,
8269 DAG.getConstant(idx, dl, MVT::i32));
8270 return DAG.getNode(PPCISD::QVFPERM, dl, VT, V1, V2, V3);
8273 // Cases that are handled by instructions that take permute immediates
8274 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
8275 // selected by the instruction selector.
8277 if (PPC::isSplatShuffleMask(SVOp, 1) ||
8278 PPC::isSplatShuffleMask(SVOp, 2) ||
8279 PPC::isSplatShuffleMask(SVOp, 4) ||
8280 PPC::isVPKUWUMShuffleMask(SVOp, 1, DAG) ||
8281 PPC::isVPKUHUMShuffleMask(SVOp, 1, DAG) ||
8282 PPC::isVSLDOIShuffleMask(SVOp, 1, DAG) != -1 ||
8283 PPC::isVMRGLShuffleMask(SVOp, 1, 1, DAG) ||
8284 PPC::isVMRGLShuffleMask(SVOp, 2, 1, DAG) ||
8285 PPC::isVMRGLShuffleMask(SVOp, 4, 1, DAG) ||
8286 PPC::isVMRGHShuffleMask(SVOp, 1, 1, DAG) ||
8287 PPC::isVMRGHShuffleMask(SVOp, 2, 1, DAG) ||
8288 PPC::isVMRGHShuffleMask(SVOp, 4, 1, DAG) ||
8289 (Subtarget.hasP8Altivec() && (
8290 PPC::isVPKUDUMShuffleMask(SVOp, 1, DAG) ||
8291 PPC::isVMRGEOShuffleMask(SVOp, true, 1, DAG) ||
8292 PPC::isVMRGEOShuffleMask(SVOp, false, 1, DAG)))) {
8297 // Altivec has a variety of "shuffle immediates" that take two vector inputs
8298 // and produce a fixed permutation. If any of these match, do not lower to
8300 unsigned int ShuffleKind = isLittleEndian ? 2 : 0;
8301 if (PPC::isVPKUWUMShuffleMask(SVOp, ShuffleKind, DAG) ||
8302 PPC::isVPKUHUMShuffleMask(SVOp, ShuffleKind, DAG) ||
8303 PPC::isVSLDOIShuffleMask(SVOp, ShuffleKind, DAG) != -1 ||
8304 PPC::isVMRGLShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
8305 PPC::isVMRGLShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
8306 PPC::isVMRGLShuffleMask(SVOp, 4, ShuffleKind, DAG) ||
8307 PPC::isVMRGHShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
8308 PPC::isVMRGHShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
8309 PPC::isVMRGHShuffleMask(SVOp, 4, ShuffleKind, DAG) ||
8310 (Subtarget.hasP8Altivec() && (
8311 PPC::isVPKUDUMShuffleMask(SVOp, ShuffleKind, DAG) ||
8312 PPC::isVMRGEOShuffleMask(SVOp, true, ShuffleKind, DAG) ||
8313 PPC::isVMRGEOShuffleMask(SVOp, false, ShuffleKind, DAG))))
8316 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
8317 // perfect shuffle table to emit an optimal matching sequence.
8318 ArrayRef<int> PermMask = SVOp->getMask();
8320 unsigned PFIndexes[4];
8321 bool isFourElementShuffle = true;
8322 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
8323 unsigned EltNo = 8; // Start out undef.
8324 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
8325 if (PermMask[i*4+j] < 0)
8326 continue; // Undef, ignore it.
8328 unsigned ByteSource = PermMask[i*4+j];
8329 if ((ByteSource & 3) != j) {
8330 isFourElementShuffle = false;
8335 EltNo = ByteSource/4;
8336 } else if (EltNo != ByteSource/4) {
8337 isFourElementShuffle = false;
8341 PFIndexes[i] = EltNo;
8344 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
8345 // perfect shuffle vector to determine if it is cost effective to do this as
8346 // discrete instructions, or whether we should use a vperm.
8347 // For now, we skip this for little endian until such time as we have a
8348 // little-endian perfect shuffle table.
8349 if (isFourElementShuffle && !isLittleEndian) {
8350 // Compute the index in the perfect shuffle table.
8351 unsigned PFTableIndex =
8352 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
8354 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
8355 unsigned Cost = (PFEntry >> 30);
8357 // Determining when to avoid vperm is tricky. Many things affect the cost
8358 // of vperm, particularly how many times the perm mask needs to be computed.
8359 // For example, if the perm mask can be hoisted out of a loop or is already
8360 // used (perhaps because there are multiple permutes with the same shuffle
8361 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
8362 // the loop requires an extra register.
8364 // As a compromise, we only emit discrete instructions if the shuffle can be
8365 // generated in 3 or fewer operations. When we have loop information
8366 // available, if this block is within a loop, we should avoid using vperm
8367 // for 3-operation perms and use a constant pool load instead.
8369 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
8372 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
8373 // vector that will get spilled to the constant pool.
8374 if (V2.isUndef()) V2 = V1;
8376 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
8377 // that it is in input element units, not in bytes. Convert now.
8379 // For little endian, the order of the input vectors is reversed, and
8380 // the permutation mask is complemented with respect to 31. This is
8381 // necessary to produce proper semantics with the big-endian-biased vperm
8383 EVT EltVT = V1.getValueType().getVectorElementType();
8384 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
8386 SmallVector<SDValue, 16> ResultMask;
8387 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
8388 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
8390 for (unsigned j = 0; j != BytesPerElement; ++j)
8392 ResultMask.push_back(DAG.getConstant(31 - (SrcElt*BytesPerElement + j),
8395 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement + j, dl,
8399 SDValue VPermMask = DAG.getBuildVector(MVT::v16i8, dl, ResultMask);
8401 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
8404 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
8408 /// getVectorCompareInfo - Given an intrinsic, return false if it is not a
8409 /// vector comparison. If it is, return true and fill in Opc/isDot with
8410 /// information about the intrinsic.
8411 static bool getVectorCompareInfo(SDValue Intrin, int &CompareOpc,
8412 bool &isDot, const PPCSubtarget &Subtarget) {
8413 unsigned IntrinsicID =
8414 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
8417 switch (IntrinsicID) {
8420 // Comparison predicates.
8421 case Intrinsic::ppc_altivec_vcmpbfp_p:
8425 case Intrinsic::ppc_altivec_vcmpeqfp_p:
8429 case Intrinsic::ppc_altivec_vcmpequb_p:
8433 case Intrinsic::ppc_altivec_vcmpequh_p:
8437 case Intrinsic::ppc_altivec_vcmpequw_p:
8441 case Intrinsic::ppc_altivec_vcmpequd_p:
8442 if (Subtarget.hasP8Altivec()) {
8448 case Intrinsic::ppc_altivec_vcmpneb_p:
8449 case Intrinsic::ppc_altivec_vcmpneh_p:
8450 case Intrinsic::ppc_altivec_vcmpnew_p:
8451 case Intrinsic::ppc_altivec_vcmpnezb_p:
8452 case Intrinsic::ppc_altivec_vcmpnezh_p:
8453 case Intrinsic::ppc_altivec_vcmpnezw_p:
8454 if (Subtarget.hasP9Altivec()) {
8455 switch (IntrinsicID) {
8457 llvm_unreachable("Unknown comparison intrinsic.");
8458 case Intrinsic::ppc_altivec_vcmpneb_p:
8461 case Intrinsic::ppc_altivec_vcmpneh_p:
8464 case Intrinsic::ppc_altivec_vcmpnew_p:
8467 case Intrinsic::ppc_altivec_vcmpnezb_p:
8470 case Intrinsic::ppc_altivec_vcmpnezh_p:
8473 case Intrinsic::ppc_altivec_vcmpnezw_p:
8481 case Intrinsic::ppc_altivec_vcmpgefp_p:
8485 case Intrinsic::ppc_altivec_vcmpgtfp_p:
8489 case Intrinsic::ppc_altivec_vcmpgtsb_p:
8493 case Intrinsic::ppc_altivec_vcmpgtsh_p:
8497 case Intrinsic::ppc_altivec_vcmpgtsw_p:
8501 case Intrinsic::ppc_altivec_vcmpgtsd_p:
8502 if (Subtarget.hasP8Altivec()) {
8508 case Intrinsic::ppc_altivec_vcmpgtub_p:
8512 case Intrinsic::ppc_altivec_vcmpgtuh_p:
8516 case Intrinsic::ppc_altivec_vcmpgtuw_p:
8520 case Intrinsic::ppc_altivec_vcmpgtud_p:
8521 if (Subtarget.hasP8Altivec()) {
8528 // VSX predicate comparisons use the same infrastructure
8529 case Intrinsic::ppc_vsx_xvcmpeqdp_p:
8530 case Intrinsic::ppc_vsx_xvcmpgedp_p:
8531 case Intrinsic::ppc_vsx_xvcmpgtdp_p:
8532 case Intrinsic::ppc_vsx_xvcmpeqsp_p:
8533 case Intrinsic::ppc_vsx_xvcmpgesp_p:
8534 case Intrinsic::ppc_vsx_xvcmpgtsp_p:
8535 if (Subtarget.hasVSX()) {
8536 switch (IntrinsicID) {
8537 case Intrinsic::ppc_vsx_xvcmpeqdp_p:
8540 case Intrinsic::ppc_vsx_xvcmpgedp_p:
8543 case Intrinsic::ppc_vsx_xvcmpgtdp_p:
8546 case Intrinsic::ppc_vsx_xvcmpeqsp_p:
8549 case Intrinsic::ppc_vsx_xvcmpgesp_p:
8552 case Intrinsic::ppc_vsx_xvcmpgtsp_p:
8561 // Normal Comparisons.
8562 case Intrinsic::ppc_altivec_vcmpbfp:
8565 case Intrinsic::ppc_altivec_vcmpeqfp:
8568 case Intrinsic::ppc_altivec_vcmpequb:
8571 case Intrinsic::ppc_altivec_vcmpequh:
8574 case Intrinsic::ppc_altivec_vcmpequw:
8577 case Intrinsic::ppc_altivec_vcmpequd:
8578 if (Subtarget.hasP8Altivec())
8583 case Intrinsic::ppc_altivec_vcmpneb:
8584 case Intrinsic::ppc_altivec_vcmpneh:
8585 case Intrinsic::ppc_altivec_vcmpnew:
8586 case Intrinsic::ppc_altivec_vcmpnezb:
8587 case Intrinsic::ppc_altivec_vcmpnezh:
8588 case Intrinsic::ppc_altivec_vcmpnezw:
8589 if (Subtarget.hasP9Altivec())
8590 switch (IntrinsicID) {
8592 llvm_unreachable("Unknown comparison intrinsic.");
8593 case Intrinsic::ppc_altivec_vcmpneb:
8596 case Intrinsic::ppc_altivec_vcmpneh:
8599 case Intrinsic::ppc_altivec_vcmpnew:
8602 case Intrinsic::ppc_altivec_vcmpnezb:
8605 case Intrinsic::ppc_altivec_vcmpnezh:
8608 case Intrinsic::ppc_altivec_vcmpnezw:
8615 case Intrinsic::ppc_altivec_vcmpgefp:
8618 case Intrinsic::ppc_altivec_vcmpgtfp:
8621 case Intrinsic::ppc_altivec_vcmpgtsb:
8624 case Intrinsic::ppc_altivec_vcmpgtsh:
8627 case Intrinsic::ppc_altivec_vcmpgtsw:
8630 case Intrinsic::ppc_altivec_vcmpgtsd:
8631 if (Subtarget.hasP8Altivec())
8636 case Intrinsic::ppc_altivec_vcmpgtub:
8639 case Intrinsic::ppc_altivec_vcmpgtuh:
8642 case Intrinsic::ppc_altivec_vcmpgtuw:
8645 case Intrinsic::ppc_altivec_vcmpgtud:
8646 if (Subtarget.hasP8Altivec())
8655 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
8656 /// lower, do it, otherwise return null.
8657 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
8658 SelectionDAG &DAG) const {
8659 unsigned IntrinsicID =
8660 cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
8664 if (IntrinsicID == Intrinsic::thread_pointer) {
8665 // Reads the thread pointer register, used for __builtin_thread_pointer.
8666 if (Subtarget.isPPC64())
8667 return DAG.getRegister(PPC::X13, MVT::i64);
8668 return DAG.getRegister(PPC::R2, MVT::i32);
8671 // We are looking for absolute values here.
8672 // The idea is to try to fit one of two patterns:
8673 // max (a, (0-a)) OR max ((0-a), a)
8674 if (Subtarget.hasP9Vector() &&
8675 (IntrinsicID == Intrinsic::ppc_altivec_vmaxsw ||
8676 IntrinsicID == Intrinsic::ppc_altivec_vmaxsh ||
8677 IntrinsicID == Intrinsic::ppc_altivec_vmaxsb)) {
8678 SDValue V1 = Op.getOperand(1);
8679 SDValue V2 = Op.getOperand(2);
8680 if (V1.getSimpleValueType() == V2.getSimpleValueType() &&
8681 (V1.getSimpleValueType() == MVT::v4i32 ||
8682 V1.getSimpleValueType() == MVT::v8i16 ||
8683 V1.getSimpleValueType() == MVT::v16i8)) {
8684 if ( V1.getOpcode() == ISD::SUB &&
8685 ISD::isBuildVectorAllZeros(V1.getOperand(0).getNode()) &&
8686 V1.getOperand(1) == V2 ) {
8687 // Generate the abs instruction with the operands
8688 return DAG.getNode(ISD::ABS, dl, V2.getValueType(),V2);
8691 if ( V2.getOpcode() == ISD::SUB &&
8692 ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()) &&
8693 V2.getOperand(1) == V1 ) {
8694 // Generate the abs instruction with the operands
8695 return DAG.getNode(ISD::ABS, dl, V1.getValueType(),V1);
8700 // If this is a lowered altivec predicate compare, CompareOpc is set to the
8701 // opcode number of the comparison.
8704 if (!getVectorCompareInfo(Op, CompareOpc, isDot, Subtarget))
8705 return SDValue(); // Don't custom lower most intrinsics.
8707 // If this is a non-dot comparison, make the VCMP node and we are done.
8709 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
8710 Op.getOperand(1), Op.getOperand(2),
8711 DAG.getConstant(CompareOpc, dl, MVT::i32));
8712 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
8715 // Create the PPCISD altivec 'dot' comparison node.
8717 Op.getOperand(2), // LHS
8718 Op.getOperand(3), // RHS
8719 DAG.getConstant(CompareOpc, dl, MVT::i32)
8721 EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue };
8722 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
8724 // Now that we have the comparison, emit a copy from the CR to a GPR.
8725 // This is flagged to the above dot comparison.
8726 SDValue Flags = DAG.getNode(PPCISD::MFOCRF, dl, MVT::i32,
8727 DAG.getRegister(PPC::CR6, MVT::i32),
8728 CompNode.getValue(1));
8730 // Unpack the result based on how the target uses it.
8731 unsigned BitNo; // Bit # of CR6.
8732 bool InvertBit; // Invert result?
8733 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
8734 default: // Can't happen, don't crash on invalid number though.
8735 case 0: // Return the value of the EQ bit of CR6.
8736 BitNo = 0; InvertBit = false;
8738 case 1: // Return the inverted value of the EQ bit of CR6.
8739 BitNo = 0; InvertBit = true;
8741 case 2: // Return the value of the LT bit of CR6.
8742 BitNo = 2; InvertBit = false;
8744 case 3: // Return the inverted value of the LT bit of CR6.
8745 BitNo = 2; InvertBit = true;
8749 // Shift the bit into the low position.
8750 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
8751 DAG.getConstant(8 - (3 - BitNo), dl, MVT::i32));
8753 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
8754 DAG.getConstant(1, dl, MVT::i32));
8756 // If we are supposed to, toggle the bit.
8758 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
8759 DAG.getConstant(1, dl, MVT::i32));
8763 SDValue PPCTargetLowering::LowerINTRINSIC_VOID(SDValue Op,
8764 SelectionDAG &DAG) const {
8765 // SelectionDAGBuilder::visitTargetIntrinsic may insert one extra chain to
8766 // the beginning of the argument list.
8767 int ArgStart = isa<ConstantSDNode>(Op.getOperand(0)) ? 0 : 1;
8769 switch (cast<ConstantSDNode>(Op.getOperand(ArgStart))->getZExtValue()) {
8770 case Intrinsic::ppc_cfence: {
8771 assert(ArgStart == 1 && "llvm.ppc.cfence must carry a chain argument.");
8772 assert(Subtarget.isPPC64() && "Only 64-bit is supported for now.");
8773 return SDValue(DAG.getMachineNode(PPC::CFENCE8, DL, MVT::Other,
8774 DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64,
8775 Op.getOperand(ArgStart + 1)),
8785 SDValue PPCTargetLowering::LowerREM(SDValue Op, SelectionDAG &DAG) const {
8786 // Check for a DIV with the same operands as this REM.
8787 for (auto UI : Op.getOperand(1)->uses()) {
8788 if ((Op.getOpcode() == ISD::SREM && UI->getOpcode() == ISD::SDIV) ||
8789 (Op.getOpcode() == ISD::UREM && UI->getOpcode() == ISD::UDIV))
8790 if (UI->getOperand(0) == Op.getOperand(0) &&
8791 UI->getOperand(1) == Op.getOperand(1))
8797 // Lower scalar BSWAP64 to xxbrd.
8798 SDValue PPCTargetLowering::LowerBSWAP(SDValue Op, SelectionDAG &DAG) const {
8801 Op = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64, Op.getOperand(0),
8804 Op = DAG.getNode(PPCISD::XXREVERSE, dl, MVT::v2i64, Op);
8806 int VectorIndex = 0;
8807 if (Subtarget.isLittleEndian())
8809 Op = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Op,
8810 DAG.getTargetConstant(VectorIndex, dl, MVT::i32));
8814 SDValue PPCTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
8815 SelectionDAG &DAG) const {
8817 // For v2i64 (VSX), we can pattern patch the v2i32 case (using fp <-> int
8818 // instructions), but for smaller types, we need to first extend up to v2i32
8819 // before doing going farther.
8820 if (Op.getValueType() == MVT::v2i64) {
8821 EVT ExtVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
8822 if (ExtVT != MVT::v2i32) {
8823 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0));
8824 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32, Op,
8825 DAG.getValueType(EVT::getVectorVT(*DAG.getContext(),
8826 ExtVT.getVectorElementType(), 4)));
8827 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Op);
8828 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v2i64, Op,
8829 DAG.getValueType(MVT::v2i32));
8838 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
8839 SelectionDAG &DAG) const {
8841 // Create a stack slot that is 16-byte aligned.
8842 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
8843 int FrameIdx = MFI.CreateStackObject(16, 16, false);
8844 EVT PtrVT = getPointerTy(DAG.getDataLayout());
8845 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
8847 // Store the input value into Value#0 of the stack slot.
8848 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), FIdx,
8849 MachinePointerInfo());
8851 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo());
8854 SDValue PPCTargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
8855 SelectionDAG &DAG) const {
8856 assert(Op.getOpcode() == ISD::INSERT_VECTOR_ELT &&
8857 "Should only be called for ISD::INSERT_VECTOR_ELT");
8859 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(2));
8860 // We have legal lowering for constant indices but not for variable ones.
8864 EVT VT = Op.getValueType();
8866 SDValue V1 = Op.getOperand(0);
8867 SDValue V2 = Op.getOperand(1);
8868 // We can use MTVSRZ + VECINSERT for v8i16 and v16i8 types.
8869 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
8870 SDValue Mtvsrz = DAG.getNode(PPCISD::MTVSRZ, dl, VT, V2);
8871 unsigned BytesInEachElement = VT.getVectorElementType().getSizeInBits() / 8;
8872 unsigned InsertAtElement = C->getZExtValue();
8873 unsigned InsertAtByte = InsertAtElement * BytesInEachElement;
8874 if (Subtarget.isLittleEndian()) {
8875 InsertAtByte = (16 - BytesInEachElement) - InsertAtByte;
8877 return DAG.getNode(PPCISD::VECINSERT, dl, VT, V1, Mtvsrz,
8878 DAG.getConstant(InsertAtByte, dl, MVT::i32));
8883 SDValue PPCTargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
8884 SelectionDAG &DAG) const {
8886 SDNode *N = Op.getNode();
8888 assert(N->getOperand(0).getValueType() == MVT::v4i1 &&
8889 "Unknown extract_vector_elt type");
8891 SDValue Value = N->getOperand(0);
8893 // The first part of this is like the store lowering except that we don't
8894 // need to track the chain.
8896 // The values are now known to be -1 (false) or 1 (true). To convert this
8897 // into 0 (false) and 1 (true), add 1 and then divide by 2 (multiply by 0.5).
8898 // This can be done with an fma and the 0.5 constant: (V+1.0)*0.5 = 0.5*V+0.5
8899 Value = DAG.getNode(PPCISD::QBFLT, dl, MVT::v4f64, Value);
8901 // FIXME: We can make this an f32 vector, but the BUILD_VECTOR code needs to
8902 // understand how to form the extending load.
8903 SDValue FPHalfs = DAG.getConstantFP(0.5, dl, MVT::v4f64);
8905 Value = DAG.getNode(ISD::FMA, dl, MVT::v4f64, Value, FPHalfs, FPHalfs);
8907 // Now convert to an integer and store.
8908 Value = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f64,
8909 DAG.getConstant(Intrinsic::ppc_qpx_qvfctiwu, dl, MVT::i32),
8912 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
8913 int FrameIdx = MFI.CreateStackObject(16, 16, false);
8914 MachinePointerInfo PtrInfo =
8915 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx);
8916 EVT PtrVT = getPointerTy(DAG.getDataLayout());
8917 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
8919 SDValue StoreChain = DAG.getEntryNode();
8920 SDValue Ops[] = {StoreChain,
8921 DAG.getConstant(Intrinsic::ppc_qpx_qvstfiw, dl, MVT::i32),
8923 SDVTList VTs = DAG.getVTList(/*chain*/ MVT::Other);
8925 StoreChain = DAG.getMemIntrinsicNode(ISD::INTRINSIC_VOID,
8926 dl, VTs, Ops, MVT::v4i32, PtrInfo);
8928 // Extract the value requested.
8929 unsigned Offset = 4*cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
8930 SDValue Idx = DAG.getConstant(Offset, dl, FIdx.getValueType());
8931 Idx = DAG.getNode(ISD::ADD, dl, FIdx.getValueType(), FIdx, Idx);
8934 DAG.getLoad(MVT::i32, dl, StoreChain, Idx, PtrInfo.getWithOffset(Offset));
8936 if (!Subtarget.useCRBits())
8939 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, IntVal);
8942 /// Lowering for QPX v4i1 loads
8943 SDValue PPCTargetLowering::LowerVectorLoad(SDValue Op,
8944 SelectionDAG &DAG) const {
8946 LoadSDNode *LN = cast<LoadSDNode>(Op.getNode());
8947 SDValue LoadChain = LN->getChain();
8948 SDValue BasePtr = LN->getBasePtr();
8950 if (Op.getValueType() == MVT::v4f64 ||
8951 Op.getValueType() == MVT::v4f32) {
8952 EVT MemVT = LN->getMemoryVT();
8953 unsigned Alignment = LN->getAlignment();
8955 // If this load is properly aligned, then it is legal.
8956 if (Alignment >= MemVT.getStoreSize())
8959 EVT ScalarVT = Op.getValueType().getScalarType(),
8960 ScalarMemVT = MemVT.getScalarType();
8961 unsigned Stride = ScalarMemVT.getStoreSize();
8963 SDValue Vals[4], LoadChains[4];
8964 for (unsigned Idx = 0; Idx < 4; ++Idx) {
8966 if (ScalarVT != ScalarMemVT)
8967 Load = DAG.getExtLoad(LN->getExtensionType(), dl, ScalarVT, LoadChain,
8969 LN->getPointerInfo().getWithOffset(Idx * Stride),
8970 ScalarMemVT, MinAlign(Alignment, Idx * Stride),
8971 LN->getMemOperand()->getFlags(), LN->getAAInfo());
8973 Load = DAG.getLoad(ScalarVT, dl, LoadChain, BasePtr,
8974 LN->getPointerInfo().getWithOffset(Idx * Stride),
8975 MinAlign(Alignment, Idx * Stride),
8976 LN->getMemOperand()->getFlags(), LN->getAAInfo());
8978 if (Idx == 0 && LN->isIndexed()) {
8979 assert(LN->getAddressingMode() == ISD::PRE_INC &&
8980 "Unknown addressing mode on vector load");
8981 Load = DAG.getIndexedLoad(Load, dl, BasePtr, LN->getOffset(),
8982 LN->getAddressingMode());
8986 LoadChains[Idx] = Load.getValue(1);
8988 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
8989 DAG.getConstant(Stride, dl,
8990 BasePtr.getValueType()));
8993 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoadChains);
8994 SDValue Value = DAG.getBuildVector(Op.getValueType(), dl, Vals);
8996 if (LN->isIndexed()) {
8997 SDValue RetOps[] = { Value, Vals[0].getValue(1), TF };
8998 return DAG.getMergeValues(RetOps, dl);
9001 SDValue RetOps[] = { Value, TF };
9002 return DAG.getMergeValues(RetOps, dl);
9005 assert(Op.getValueType() == MVT::v4i1 && "Unknown load to lower");
9006 assert(LN->isUnindexed() && "Indexed v4i1 loads are not supported");
9008 // To lower v4i1 from a byte array, we load the byte elements of the
9009 // vector and then reuse the BUILD_VECTOR logic.
9011 SDValue VectElmts[4], VectElmtChains[4];
9012 for (unsigned i = 0; i < 4; ++i) {
9013 SDValue Idx = DAG.getConstant(i, dl, BasePtr.getValueType());
9014 Idx = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, Idx);
9016 VectElmts[i] = DAG.getExtLoad(
9017 ISD::EXTLOAD, dl, MVT::i32, LoadChain, Idx,
9018 LN->getPointerInfo().getWithOffset(i), MVT::i8,
9019 /* Alignment = */ 1, LN->getMemOperand()->getFlags(), LN->getAAInfo());
9020 VectElmtChains[i] = VectElmts[i].getValue(1);
9023 LoadChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, VectElmtChains);
9024 SDValue Value = DAG.getBuildVector(MVT::v4i1, dl, VectElmts);
9026 SDValue RVals[] = { Value, LoadChain };
9027 return DAG.getMergeValues(RVals, dl);
9030 /// Lowering for QPX v4i1 stores
9031 SDValue PPCTargetLowering::LowerVectorStore(SDValue Op,
9032 SelectionDAG &DAG) const {
9034 StoreSDNode *SN = cast<StoreSDNode>(Op.getNode());
9035 SDValue StoreChain = SN->getChain();
9036 SDValue BasePtr = SN->getBasePtr();
9037 SDValue Value = SN->getValue();
9039 if (Value.getValueType() == MVT::v4f64 ||
9040 Value.getValueType() == MVT::v4f32) {
9041 EVT MemVT = SN->getMemoryVT();
9042 unsigned Alignment = SN->getAlignment();
9044 // If this store is properly aligned, then it is legal.
9045 if (Alignment >= MemVT.getStoreSize())
9048 EVT ScalarVT = Value.getValueType().getScalarType(),
9049 ScalarMemVT = MemVT.getScalarType();
9050 unsigned Stride = ScalarMemVT.getStoreSize();
9053 for (unsigned Idx = 0; Idx < 4; ++Idx) {
9054 SDValue Ex = DAG.getNode(
9055 ISD::EXTRACT_VECTOR_ELT, dl, ScalarVT, Value,
9056 DAG.getConstant(Idx, dl, getVectorIdxTy(DAG.getDataLayout())));
9058 if (ScalarVT != ScalarMemVT)
9060 DAG.getTruncStore(StoreChain, dl, Ex, BasePtr,
9061 SN->getPointerInfo().getWithOffset(Idx * Stride),
9062 ScalarMemVT, MinAlign(Alignment, Idx * Stride),
9063 SN->getMemOperand()->getFlags(), SN->getAAInfo());
9065 Store = DAG.getStore(StoreChain, dl, Ex, BasePtr,
9066 SN->getPointerInfo().getWithOffset(Idx * Stride),
9067 MinAlign(Alignment, Idx * Stride),
9068 SN->getMemOperand()->getFlags(), SN->getAAInfo());
9070 if (Idx == 0 && SN->isIndexed()) {
9071 assert(SN->getAddressingMode() == ISD::PRE_INC &&
9072 "Unknown addressing mode on vector store");
9073 Store = DAG.getIndexedStore(Store, dl, BasePtr, SN->getOffset(),
9074 SN->getAddressingMode());
9077 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
9078 DAG.getConstant(Stride, dl,
9079 BasePtr.getValueType()));
9080 Stores[Idx] = Store;
9083 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
9085 if (SN->isIndexed()) {
9086 SDValue RetOps[] = { TF, Stores[0].getValue(1) };
9087 return DAG.getMergeValues(RetOps, dl);
9093 assert(SN->isUnindexed() && "Indexed v4i1 stores are not supported");
9094 assert(Value.getValueType() == MVT::v4i1 && "Unknown store to lower");
9096 // The values are now known to be -1 (false) or 1 (true). To convert this
9097 // into 0 (false) and 1 (true), add 1 and then divide by 2 (multiply by 0.5).
9098 // This can be done with an fma and the 0.5 constant: (V+1.0)*0.5 = 0.5*V+0.5
9099 Value = DAG.getNode(PPCISD::QBFLT, dl, MVT::v4f64, Value);
9101 // FIXME: We can make this an f32 vector, but the BUILD_VECTOR code needs to
9102 // understand how to form the extending load.
9103 SDValue FPHalfs = DAG.getConstantFP(0.5, dl, MVT::v4f64);
9105 Value = DAG.getNode(ISD::FMA, dl, MVT::v4f64, Value, FPHalfs, FPHalfs);
9107 // Now convert to an integer and store.
9108 Value = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f64,
9109 DAG.getConstant(Intrinsic::ppc_qpx_qvfctiwu, dl, MVT::i32),
9112 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
9113 int FrameIdx = MFI.CreateStackObject(16, 16, false);
9114 MachinePointerInfo PtrInfo =
9115 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx);
9116 EVT PtrVT = getPointerTy(DAG.getDataLayout());
9117 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
9119 SDValue Ops[] = {StoreChain,
9120 DAG.getConstant(Intrinsic::ppc_qpx_qvstfiw, dl, MVT::i32),
9122 SDVTList VTs = DAG.getVTList(/*chain*/ MVT::Other);
9124 StoreChain = DAG.getMemIntrinsicNode(ISD::INTRINSIC_VOID,
9125 dl, VTs, Ops, MVT::v4i32, PtrInfo);
9127 // Move data into the byte array.
9128 SDValue Loads[4], LoadChains[4];
9129 for (unsigned i = 0; i < 4; ++i) {
9130 unsigned Offset = 4*i;
9131 SDValue Idx = DAG.getConstant(Offset, dl, FIdx.getValueType());
9132 Idx = DAG.getNode(ISD::ADD, dl, FIdx.getValueType(), FIdx, Idx);
9134 Loads[i] = DAG.getLoad(MVT::i32, dl, StoreChain, Idx,
9135 PtrInfo.getWithOffset(Offset));
9136 LoadChains[i] = Loads[i].getValue(1);
9139 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoadChains);
9142 for (unsigned i = 0; i < 4; ++i) {
9143 SDValue Idx = DAG.getConstant(i, dl, BasePtr.getValueType());
9144 Idx = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, Idx);
9146 Stores[i] = DAG.getTruncStore(
9147 StoreChain, dl, Loads[i], Idx, SN->getPointerInfo().getWithOffset(i),
9148 MVT::i8, /* Alignment = */ 1, SN->getMemOperand()->getFlags(),
9152 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
9157 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
9159 if (Op.getValueType() == MVT::v4i32) {
9160 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
9162 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
9163 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
9165 SDValue RHSSwap = // = vrlw RHS, 16
9166 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
9168 // Shrinkify inputs to v8i16.
9169 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
9170 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
9171 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
9173 // Low parts multiplied together, generating 32-bit results (we ignore the
9175 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
9176 LHS, RHS, DAG, dl, MVT::v4i32);
9178 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
9179 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
9180 // Shift the high parts up 16 bits.
9181 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
9183 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
9184 } else if (Op.getValueType() == MVT::v8i16) {
9185 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
9187 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
9189 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
9190 LHS, RHS, Zero, DAG, dl);
9191 } else if (Op.getValueType() == MVT::v16i8) {
9192 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
9193 bool isLittleEndian = Subtarget.isLittleEndian();
9195 // Multiply the even 8-bit parts, producing 16-bit sums.
9196 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
9197 LHS, RHS, DAG, dl, MVT::v8i16);
9198 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
9200 // Multiply the odd 8-bit parts, producing 16-bit sums.
9201 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
9202 LHS, RHS, DAG, dl, MVT::v8i16);
9203 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
9205 // Merge the results together. Because vmuleub and vmuloub are
9206 // instructions with a big-endian bias, we must reverse the
9207 // element numbering and reverse the meaning of "odd" and "even"
9208 // when generating little endian code.
9210 for (unsigned i = 0; i != 8; ++i) {
9211 if (isLittleEndian) {
9213 Ops[i*2+1] = 2*i+16;
9216 Ops[i*2+1] = 2*i+1+16;
9220 return DAG.getVectorShuffle(MVT::v16i8, dl, OddParts, EvenParts, Ops);
9222 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
9224 llvm_unreachable("Unknown mul to lower!");
9228 /// LowerOperation - Provide custom lowering hooks for some operations.
9230 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
9231 switch (Op.getOpcode()) {
9232 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
9233 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
9234 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
9235 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
9236 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
9237 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
9238 case ISD::SETCC: return LowerSETCC(Op, DAG);
9239 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
9240 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
9242 return LowerVASTART(Op, DAG);
9245 return LowerVAARG(Op, DAG);
9248 return LowerVACOPY(Op, DAG);
9250 case ISD::STACKRESTORE:
9251 return LowerSTACKRESTORE(Op, DAG);
9253 case ISD::DYNAMIC_STACKALLOC:
9254 return LowerDYNAMIC_STACKALLOC(Op, DAG);
9256 case ISD::GET_DYNAMIC_AREA_OFFSET:
9257 return LowerGET_DYNAMIC_AREA_OFFSET(Op, DAG);
9259 case ISD::EH_DWARF_CFA:
9260 return LowerEH_DWARF_CFA(Op, DAG);
9262 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
9263 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
9265 case ISD::LOAD: return LowerLOAD(Op, DAG);
9266 case ISD::STORE: return LowerSTORE(Op, DAG);
9267 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
9268 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
9269 case ISD::FP_TO_UINT:
9270 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
9272 case ISD::UINT_TO_FP:
9273 case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
9274 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
9276 // Lower 64-bit shifts.
9277 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
9278 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
9279 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
9281 // Vector-related lowering.
9282 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
9283 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
9284 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
9285 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
9286 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
9287 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
9288 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
9289 case ISD::MUL: return LowerMUL(Op, DAG);
9291 // For counter-based loop handling.
9292 case ISD::INTRINSIC_W_CHAIN: return SDValue();
9294 // Frame & Return address.
9295 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
9296 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
9298 case ISD::INTRINSIC_VOID:
9299 return LowerINTRINSIC_VOID(Op, DAG);
9302 return LowerREM(Op, DAG);
9304 return LowerBSWAP(Op, DAG);
9308 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
9309 SmallVectorImpl<SDValue>&Results,
9310 SelectionDAG &DAG) const {
9312 switch (N->getOpcode()) {
9314 llvm_unreachable("Do not know how to custom type legalize this operation!");
9315 case ISD::READCYCLECOUNTER: {
9316 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
9317 SDValue RTB = DAG.getNode(PPCISD::READ_TIME_BASE, dl, VTs, N->getOperand(0));
9319 Results.push_back(RTB);
9320 Results.push_back(RTB.getValue(1));
9321 Results.push_back(RTB.getValue(2));
9324 case ISD::INTRINSIC_W_CHAIN: {
9325 if (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() !=
9326 Intrinsic::ppc_is_decremented_ctr_nonzero)
9329 assert(N->getValueType(0) == MVT::i1 &&
9330 "Unexpected result type for CTR decrement intrinsic");
9331 EVT SVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
9332 N->getValueType(0));
9333 SDVTList VTs = DAG.getVTList(SVT, MVT::Other);
9334 SDValue NewInt = DAG.getNode(N->getOpcode(), dl, VTs, N->getOperand(0),
9337 Results.push_back(NewInt);
9338 Results.push_back(NewInt.getValue(1));
9342 if (!Subtarget.isSVR4ABI() || Subtarget.isPPC64())
9345 EVT VT = N->getValueType(0);
9347 if (VT == MVT::i64) {
9348 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG);
9350 Results.push_back(NewNode);
9351 Results.push_back(NewNode.getValue(1));
9355 case ISD::FP_ROUND_INREG: {
9356 assert(N->getValueType(0) == MVT::ppcf128);
9357 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
9358 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
9359 MVT::f64, N->getOperand(0),
9360 DAG.getIntPtrConstant(0, dl));
9361 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
9362 MVT::f64, N->getOperand(0),
9363 DAG.getIntPtrConstant(1, dl));
9365 // Add the two halves of the long double in round-to-zero mode.
9366 SDValue FPreg = DAG.getNode(PPCISD::FADDRTZ, dl, MVT::f64, Lo, Hi);
9368 // We know the low half is about to be thrown away, so just use something
9370 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
9374 case ISD::FP_TO_SINT:
9375 case ISD::FP_TO_UINT:
9376 // LowerFP_TO_INT() can only handle f32 and f64.
9377 if (N->getOperand(0).getValueType() == MVT::ppcf128)
9379 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
9384 //===----------------------------------------------------------------------===//
9385 // Other Lowering Code
9386 //===----------------------------------------------------------------------===//
9388 static Instruction* callIntrinsic(IRBuilder<> &Builder, Intrinsic::ID Id) {
9389 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
9390 Function *Func = Intrinsic::getDeclaration(M, Id);
9391 return Builder.CreateCall(Func, {});
9394 // The mappings for emitLeading/TrailingFence is taken from
9395 // http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
9396 Instruction *PPCTargetLowering::emitLeadingFence(IRBuilder<> &Builder,
9398 AtomicOrdering Ord) const {
9399 if (Ord == AtomicOrdering::SequentiallyConsistent)
9400 return callIntrinsic(Builder, Intrinsic::ppc_sync);
9401 if (isReleaseOrStronger(Ord))
9402 return callIntrinsic(Builder, Intrinsic::ppc_lwsync);
9406 Instruction *PPCTargetLowering::emitTrailingFence(IRBuilder<> &Builder,
9408 AtomicOrdering Ord) const {
9409 if (Inst->hasAtomicLoad() && isAcquireOrStronger(Ord)) {
9410 // See http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html and
9411 // http://www.rdrop.com/users/paulmck/scalability/paper/N2745r.2011.03.04a.html
9412 // and http://www.cl.cam.ac.uk/~pes20/cppppc/ for justification.
9413 if (isa<LoadInst>(Inst) && Subtarget.isPPC64())
9414 return Builder.CreateCall(
9415 Intrinsic::getDeclaration(
9416 Builder.GetInsertBlock()->getParent()->getParent(),
9417 Intrinsic::ppc_cfence, {Inst->getType()}),
9419 // FIXME: Can use isync for rmw operation.
9420 return callIntrinsic(Builder, Intrinsic::ppc_lwsync);
9426 PPCTargetLowering::EmitAtomicBinary(MachineInstr &MI, MachineBasicBlock *BB,
9427 unsigned AtomicSize,
9430 unsigned CmpPred) const {
9431 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
9432 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
9434 auto LoadMnemonic = PPC::LDARX;
9435 auto StoreMnemonic = PPC::STDCX;
9436 switch (AtomicSize) {
9438 llvm_unreachable("Unexpected size of atomic entity");
9440 LoadMnemonic = PPC::LBARX;
9441 StoreMnemonic = PPC::STBCX;
9442 assert(Subtarget.hasPartwordAtomics() && "Call this only with size >=4");
9445 LoadMnemonic = PPC::LHARX;
9446 StoreMnemonic = PPC::STHCX;
9447 assert(Subtarget.hasPartwordAtomics() && "Call this only with size >=4");
9450 LoadMnemonic = PPC::LWARX;
9451 StoreMnemonic = PPC::STWCX;
9454 LoadMnemonic = PPC::LDARX;
9455 StoreMnemonic = PPC::STDCX;
9459 const BasicBlock *LLVM_BB = BB->getBasicBlock();
9460 MachineFunction *F = BB->getParent();
9461 MachineFunction::iterator It = ++BB->getIterator();
9463 unsigned dest = MI.getOperand(0).getReg();
9464 unsigned ptrA = MI.getOperand(1).getReg();
9465 unsigned ptrB = MI.getOperand(2).getReg();
9466 unsigned incr = MI.getOperand(3).getReg();
9467 DebugLoc dl = MI.getDebugLoc();
9469 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
9470 MachineBasicBlock *loop2MBB =
9471 CmpOpcode ? F->CreateMachineBasicBlock(LLVM_BB) : nullptr;
9472 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
9473 F->insert(It, loopMBB);
9475 F->insert(It, loop2MBB);
9476 F->insert(It, exitMBB);
9477 exitMBB->splice(exitMBB->begin(), BB,
9478 std::next(MachineBasicBlock::iterator(MI)), BB->end());
9479 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
9481 MachineRegisterInfo &RegInfo = F->getRegInfo();
9482 unsigned TmpReg = (!BinOpcode) ? incr :
9483 RegInfo.createVirtualRegister( AtomicSize == 8 ? &PPC::G8RCRegClass
9484 : &PPC::GPRCRegClass);
9488 // fallthrough --> loopMBB
9489 BB->addSuccessor(loopMBB);
9492 // l[wd]arx dest, ptr
9493 // add r0, dest, incr
9494 // st[wd]cx. r0, ptr
9496 // fallthrough --> exitMBB
9500 // l[wd]arx dest, ptr
9501 // cmpl?[wd] incr, dest
9504 // st[wd]cx. dest, ptr
9506 // fallthrough --> exitMBB
9509 BuildMI(BB, dl, TII->get(LoadMnemonic), dest)
9510 .addReg(ptrA).addReg(ptrB);
9512 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
9514 // Signed comparisons of byte or halfword values must be sign-extended.
9515 if (CmpOpcode == PPC::CMPW && AtomicSize < 4) {
9516 unsigned ExtReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
9517 BuildMI(BB, dl, TII->get(AtomicSize == 1 ? PPC::EXTSB : PPC::EXTSH),
9518 ExtReg).addReg(dest);
9519 BuildMI(BB, dl, TII->get(CmpOpcode), PPC::CR0)
9520 .addReg(incr).addReg(ExtReg);
9522 BuildMI(BB, dl, TII->get(CmpOpcode), PPC::CR0)
9523 .addReg(incr).addReg(dest);
9525 BuildMI(BB, dl, TII->get(PPC::BCC))
9526 .addImm(CmpPred).addReg(PPC::CR0).addMBB(exitMBB);
9527 BB->addSuccessor(loop2MBB);
9528 BB->addSuccessor(exitMBB);
9531 BuildMI(BB, dl, TII->get(StoreMnemonic))
9532 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
9533 BuildMI(BB, dl, TII->get(PPC::BCC))
9534 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
9535 BB->addSuccessor(loopMBB);
9536 BB->addSuccessor(exitMBB);
9545 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr &MI,
9546 MachineBasicBlock *BB,
9547 bool is8bit, // operation
9550 unsigned CmpPred) const {
9551 // If we support part-word atomic mnemonics, just use them
9552 if (Subtarget.hasPartwordAtomics())
9553 return EmitAtomicBinary(MI, BB, is8bit ? 1 : 2, BinOpcode,
9554 CmpOpcode, CmpPred);
9556 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
9557 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
9558 // In 64 bit mode we have to use 64 bits for addresses, even though the
9559 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
9560 // registers without caring whether they're 32 or 64, but here we're
9561 // doing actual arithmetic on the addresses.
9562 bool is64bit = Subtarget.isPPC64();
9563 bool isLittleEndian = Subtarget.isLittleEndian();
9564 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
9566 const BasicBlock *LLVM_BB = BB->getBasicBlock();
9567 MachineFunction *F = BB->getParent();
9568 MachineFunction::iterator It = ++BB->getIterator();
9570 unsigned dest = MI.getOperand(0).getReg();
9571 unsigned ptrA = MI.getOperand(1).getReg();
9572 unsigned ptrB = MI.getOperand(2).getReg();
9573 unsigned incr = MI.getOperand(3).getReg();
9574 DebugLoc dl = MI.getDebugLoc();
9576 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
9577 MachineBasicBlock *loop2MBB =
9578 CmpOpcode ? F->CreateMachineBasicBlock(LLVM_BB) : nullptr;
9579 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
9580 F->insert(It, loopMBB);
9582 F->insert(It, loop2MBB);
9583 F->insert(It, exitMBB);
9584 exitMBB->splice(exitMBB->begin(), BB,
9585 std::next(MachineBasicBlock::iterator(MI)), BB->end());
9586 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
9588 MachineRegisterInfo &RegInfo = F->getRegInfo();
9589 const TargetRegisterClass *RC = is64bit ? &PPC::G8RCRegClass
9590 : &PPC::GPRCRegClass;
9591 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
9592 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
9594 isLittleEndian ? Shift1Reg : RegInfo.createVirtualRegister(RC);
9595 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
9596 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
9597 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
9598 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
9599 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
9600 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
9601 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
9602 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
9604 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
9608 // fallthrough --> loopMBB
9609 BB->addSuccessor(loopMBB);
9611 // The 4-byte load must be aligned, while a char or short may be
9612 // anywhere in the word. Hence all this nasty bookkeeping code.
9613 // add ptr1, ptrA, ptrB [copy if ptrA==0]
9614 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
9615 // xori shift, shift1, 24 [16]
9616 // rlwinm ptr, ptr1, 0, 0, 29
9617 // slw incr2, incr, shift
9618 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
9619 // slw mask, mask2, shift
9621 // lwarx tmpDest, ptr
9622 // add tmp, tmpDest, incr2
9623 // andc tmp2, tmpDest, mask
9624 // and tmp3, tmp, mask
9625 // or tmp4, tmp3, tmp2
9628 // fallthrough --> exitMBB
9629 // srw dest, tmpDest, shift
9630 if (ptrA != ZeroReg) {
9631 Ptr1Reg = RegInfo.createVirtualRegister(RC);
9632 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
9633 .addReg(ptrA).addReg(ptrB);
9637 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
9638 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
9639 if (!isLittleEndian)
9640 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
9641 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
9643 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
9644 .addReg(Ptr1Reg).addImm(0).addImm(61);
9646 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
9647 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
9648 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
9649 .addReg(incr).addReg(ShiftReg);
9651 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
9653 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
9654 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
9656 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
9657 .addReg(Mask2Reg).addReg(ShiftReg);
9660 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
9661 .addReg(ZeroReg).addReg(PtrReg);
9663 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
9664 .addReg(Incr2Reg).addReg(TmpDestReg);
9665 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
9666 .addReg(TmpDestReg).addReg(MaskReg);
9667 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
9668 .addReg(TmpReg).addReg(MaskReg);
9670 // For unsigned comparisons, we can directly compare the shifted values.
9671 // For signed comparisons we shift and sign extend.
9672 unsigned SReg = RegInfo.createVirtualRegister(RC);
9673 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), SReg)
9674 .addReg(TmpDestReg).addReg(MaskReg);
9675 unsigned ValueReg = SReg;
9676 unsigned CmpReg = Incr2Reg;
9677 if (CmpOpcode == PPC::CMPW) {
9678 ValueReg = RegInfo.createVirtualRegister(RC);
9679 BuildMI(BB, dl, TII->get(PPC::SRW), ValueReg)
9680 .addReg(SReg).addReg(ShiftReg);
9681 unsigned ValueSReg = RegInfo.createVirtualRegister(RC);
9682 BuildMI(BB, dl, TII->get(is8bit ? PPC::EXTSB : PPC::EXTSH), ValueSReg)
9684 ValueReg = ValueSReg;
9687 BuildMI(BB, dl, TII->get(CmpOpcode), PPC::CR0)
9688 .addReg(CmpReg).addReg(ValueReg);
9689 BuildMI(BB, dl, TII->get(PPC::BCC))
9690 .addImm(CmpPred).addReg(PPC::CR0).addMBB(exitMBB);
9691 BB->addSuccessor(loop2MBB);
9692 BB->addSuccessor(exitMBB);
9695 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
9696 .addReg(Tmp3Reg).addReg(Tmp2Reg);
9697 BuildMI(BB, dl, TII->get(PPC::STWCX))
9698 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
9699 BuildMI(BB, dl, TII->get(PPC::BCC))
9700 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
9701 BB->addSuccessor(loopMBB);
9702 BB->addSuccessor(exitMBB);
9707 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg)
9712 llvm::MachineBasicBlock *
9713 PPCTargetLowering::emitEHSjLjSetJmp(MachineInstr &MI,
9714 MachineBasicBlock *MBB) const {
9715 DebugLoc DL = MI.getDebugLoc();
9716 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
9717 const PPCRegisterInfo *TRI = Subtarget.getRegisterInfo();
9719 MachineFunction *MF = MBB->getParent();
9720 MachineRegisterInfo &MRI = MF->getRegInfo();
9722 const BasicBlock *BB = MBB->getBasicBlock();
9723 MachineFunction::iterator I = ++MBB->getIterator();
9726 MachineInstr::mmo_iterator MMOBegin = MI.memoperands_begin();
9727 MachineInstr::mmo_iterator MMOEnd = MI.memoperands_end();
9729 unsigned DstReg = MI.getOperand(0).getReg();
9730 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
9731 assert(TRI->isTypeLegalForClass(*RC, MVT::i32) && "Invalid destination!");
9732 unsigned mainDstReg = MRI.createVirtualRegister(RC);
9733 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
9735 MVT PVT = getPointerTy(MF->getDataLayout());
9736 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
9737 "Invalid Pointer Size!");
9738 // For v = setjmp(buf), we generate
9741 // SjLjSetup mainMBB
9747 // buf[LabelOffset] = LR
9751 // v = phi(main, restore)
9754 MachineBasicBlock *thisMBB = MBB;
9755 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
9756 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
9757 MF->insert(I, mainMBB);
9758 MF->insert(I, sinkMBB);
9760 MachineInstrBuilder MIB;
9762 // Transfer the remainder of BB and its successor edges to sinkMBB.
9763 sinkMBB->splice(sinkMBB->begin(), MBB,
9764 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
9765 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
9767 // Note that the structure of the jmp_buf used here is not compatible
9768 // with that used by libc, and is not designed to be. Specifically, it
9769 // stores only those 'reserved' registers that LLVM does not otherwise
9770 // understand how to spill. Also, by convention, by the time this
9771 // intrinsic is called, Clang has already stored the frame address in the
9772 // first slot of the buffer and stack address in the third. Following the
9773 // X86 target code, we'll store the jump address in the second slot. We also
9774 // need to save the TOC pointer (R2) to handle jumps between shared
9775 // libraries, and that will be stored in the fourth slot. The thread
9776 // identifier (R13) is not affected.
9779 const int64_t LabelOffset = 1 * PVT.getStoreSize();
9780 const int64_t TOCOffset = 3 * PVT.getStoreSize();
9781 const int64_t BPOffset = 4 * PVT.getStoreSize();
9783 // Prepare IP either in reg.
9784 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
9785 unsigned LabelReg = MRI.createVirtualRegister(PtrRC);
9786 unsigned BufReg = MI.getOperand(1).getReg();
9788 if (Subtarget.isPPC64() && Subtarget.isSVR4ABI()) {
9789 setUsesTOCBasePtr(*MBB->getParent());
9790 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::STD))
9794 MIB.setMemRefs(MMOBegin, MMOEnd);
9797 // Naked functions never have a base pointer, and so we use r1. For all
9798 // other functions, this decision must be delayed until during PEI.
9800 if (MF->getFunction().hasFnAttribute(Attribute::Naked))
9801 BaseReg = Subtarget.isPPC64() ? PPC::X1 : PPC::R1;
9803 BaseReg = Subtarget.isPPC64() ? PPC::BP8 : PPC::BP;
9805 MIB = BuildMI(*thisMBB, MI, DL,
9806 TII->get(Subtarget.isPPC64() ? PPC::STD : PPC::STW))
9810 MIB.setMemRefs(MMOBegin, MMOEnd);
9813 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::BCLalways)).addMBB(mainMBB);
9814 MIB.addRegMask(TRI->getNoPreservedMask());
9816 BuildMI(*thisMBB, MI, DL, TII->get(PPC::LI), restoreDstReg).addImm(1);
9818 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::EH_SjLj_Setup))
9820 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::B)).addMBB(sinkMBB);
9822 thisMBB->addSuccessor(mainMBB, BranchProbability::getZero());
9823 thisMBB->addSuccessor(sinkMBB, BranchProbability::getOne());
9828 BuildMI(mainMBB, DL,
9829 TII->get(Subtarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg);
9832 if (Subtarget.isPPC64()) {
9833 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STD))
9835 .addImm(LabelOffset)
9838 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STW))
9840 .addImm(LabelOffset)
9844 MIB.setMemRefs(MMOBegin, MMOEnd);
9846 BuildMI(mainMBB, DL, TII->get(PPC::LI), mainDstReg).addImm(0);
9847 mainMBB->addSuccessor(sinkMBB);
9850 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
9851 TII->get(PPC::PHI), DstReg)
9852 .addReg(mainDstReg).addMBB(mainMBB)
9853 .addReg(restoreDstReg).addMBB(thisMBB);
9855 MI.eraseFromParent();
9860 PPCTargetLowering::emitEHSjLjLongJmp(MachineInstr &MI,
9861 MachineBasicBlock *MBB) const {
9862 DebugLoc DL = MI.getDebugLoc();
9863 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
9865 MachineFunction *MF = MBB->getParent();
9866 MachineRegisterInfo &MRI = MF->getRegInfo();
9869 MachineInstr::mmo_iterator MMOBegin = MI.memoperands_begin();
9870 MachineInstr::mmo_iterator MMOEnd = MI.memoperands_end();
9872 MVT PVT = getPointerTy(MF->getDataLayout());
9873 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
9874 "Invalid Pointer Size!");
9876 const TargetRegisterClass *RC =
9877 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
9878 unsigned Tmp = MRI.createVirtualRegister(RC);
9879 // Since FP is only updated here but NOT referenced, it's treated as GPR.
9880 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
9881 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
9885 : (Subtarget.isSVR4ABI() && isPositionIndependent() ? PPC::R29
9888 MachineInstrBuilder MIB;
9890 const int64_t LabelOffset = 1 * PVT.getStoreSize();
9891 const int64_t SPOffset = 2 * PVT.getStoreSize();
9892 const int64_t TOCOffset = 3 * PVT.getStoreSize();
9893 const int64_t BPOffset = 4 * PVT.getStoreSize();
9895 unsigned BufReg = MI.getOperand(0).getReg();
9897 // Reload FP (the jumped-to function may not have had a
9898 // frame pointer, and if so, then its r31 will be restored
9900 if (PVT == MVT::i64) {
9901 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), FP)
9905 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), FP)
9909 MIB.setMemRefs(MMOBegin, MMOEnd);
9912 if (PVT == MVT::i64) {
9913 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), Tmp)
9914 .addImm(LabelOffset)
9917 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), Tmp)
9918 .addImm(LabelOffset)
9921 MIB.setMemRefs(MMOBegin, MMOEnd);
9924 if (PVT == MVT::i64) {
9925 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), SP)
9929 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), SP)
9933 MIB.setMemRefs(MMOBegin, MMOEnd);
9936 if (PVT == MVT::i64) {
9937 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), BP)
9941 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), BP)
9945 MIB.setMemRefs(MMOBegin, MMOEnd);
9948 if (PVT == MVT::i64 && Subtarget.isSVR4ABI()) {
9949 setUsesTOCBasePtr(*MBB->getParent());
9950 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), PPC::X2)
9954 MIB.setMemRefs(MMOBegin, MMOEnd);
9958 BuildMI(*MBB, MI, DL,
9959 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
9960 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));
9962 MI.eraseFromParent();
9967 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
9968 MachineBasicBlock *BB) const {
9969 if (MI.getOpcode() == TargetOpcode::STACKMAP ||
9970 MI.getOpcode() == TargetOpcode::PATCHPOINT) {
9971 if (Subtarget.isPPC64() && Subtarget.isSVR4ABI() &&
9972 MI.getOpcode() == TargetOpcode::PATCHPOINT) {
9973 // Call lowering should have added an r2 operand to indicate a dependence
9974 // on the TOC base pointer value. It can't however, because there is no
9975 // way to mark the dependence as implicit there, and so the stackmap code
9976 // will confuse it with a regular operand. Instead, add the dependence
9978 setUsesTOCBasePtr(*BB->getParent());
9979 MI.addOperand(MachineOperand::CreateReg(PPC::X2, false, true));
9982 return emitPatchPoint(MI, BB);
9985 if (MI.getOpcode() == PPC::EH_SjLj_SetJmp32 ||
9986 MI.getOpcode() == PPC::EH_SjLj_SetJmp64) {
9987 return emitEHSjLjSetJmp(MI, BB);
9988 } else if (MI.getOpcode() == PPC::EH_SjLj_LongJmp32 ||
9989 MI.getOpcode() == PPC::EH_SjLj_LongJmp64) {
9990 return emitEHSjLjLongJmp(MI, BB);
9993 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
9995 // To "insert" these instructions we actually have to insert their
9996 // control-flow patterns.
9997 const BasicBlock *LLVM_BB = BB->getBasicBlock();
9998 MachineFunction::iterator It = ++BB->getIterator();
10000 MachineFunction *F = BB->getParent();
10002 if (MI.getOpcode() == PPC::SELECT_CC_I4 ||
10003 MI.getOpcode() == PPC::SELECT_CC_I8 ||
10004 MI.getOpcode() == PPC::SELECT_I4 || MI.getOpcode() == PPC::SELECT_I8) {
10005 SmallVector<MachineOperand, 2> Cond;
10006 if (MI.getOpcode() == PPC::SELECT_CC_I4 ||
10007 MI.getOpcode() == PPC::SELECT_CC_I8)
10008 Cond.push_back(MI.getOperand(4));
10010 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
10011 Cond.push_back(MI.getOperand(1));
10013 DebugLoc dl = MI.getDebugLoc();
10014 TII->insertSelect(*BB, MI, dl, MI.getOperand(0).getReg(), Cond,
10015 MI.getOperand(2).getReg(), MI.getOperand(3).getReg());
10016 } else if (MI.getOpcode() == PPC::SELECT_CC_I4 ||
10017 MI.getOpcode() == PPC::SELECT_CC_I8 ||
10018 MI.getOpcode() == PPC::SELECT_CC_F4 ||
10019 MI.getOpcode() == PPC::SELECT_CC_F8 ||
10020 MI.getOpcode() == PPC::SELECT_CC_QFRC ||
10021 MI.getOpcode() == PPC::SELECT_CC_QSRC ||
10022 MI.getOpcode() == PPC::SELECT_CC_QBRC ||
10023 MI.getOpcode() == PPC::SELECT_CC_VRRC ||
10024 MI.getOpcode() == PPC::SELECT_CC_VSFRC ||
10025 MI.getOpcode() == PPC::SELECT_CC_VSSRC ||
10026 MI.getOpcode() == PPC::SELECT_CC_VSRC ||
10027 MI.getOpcode() == PPC::SELECT_I4 ||
10028 MI.getOpcode() == PPC::SELECT_I8 ||
10029 MI.getOpcode() == PPC::SELECT_F4 ||
10030 MI.getOpcode() == PPC::SELECT_F8 ||
10031 MI.getOpcode() == PPC::SELECT_QFRC ||
10032 MI.getOpcode() == PPC::SELECT_QSRC ||
10033 MI.getOpcode() == PPC::SELECT_QBRC ||
10034 MI.getOpcode() == PPC::SELECT_VRRC ||
10035 MI.getOpcode() == PPC::SELECT_VSFRC ||
10036 MI.getOpcode() == PPC::SELECT_VSSRC ||
10037 MI.getOpcode() == PPC::SELECT_VSRC) {
10038 // The incoming instruction knows the destination vreg to set, the
10039 // condition code register to branch on, the true/false values to
10040 // select between, and a branch opcode to use.
10045 // cmpTY ccX, r1, r2
10047 // fallthrough --> copy0MBB
10048 MachineBasicBlock *thisMBB = BB;
10049 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
10050 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
10051 DebugLoc dl = MI.getDebugLoc();
10052 F->insert(It, copy0MBB);
10053 F->insert(It, sinkMBB);
10055 // Transfer the remainder of BB and its successor edges to sinkMBB.
10056 sinkMBB->splice(sinkMBB->begin(), BB,
10057 std::next(MachineBasicBlock::iterator(MI)), BB->end());
10058 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
10060 // Next, add the true and fallthrough blocks as its successors.
10061 BB->addSuccessor(copy0MBB);
10062 BB->addSuccessor(sinkMBB);
10064 if (MI.getOpcode() == PPC::SELECT_I4 || MI.getOpcode() == PPC::SELECT_I8 ||
10065 MI.getOpcode() == PPC::SELECT_F4 || MI.getOpcode() == PPC::SELECT_F8 ||
10066 MI.getOpcode() == PPC::SELECT_QFRC ||
10067 MI.getOpcode() == PPC::SELECT_QSRC ||
10068 MI.getOpcode() == PPC::SELECT_QBRC ||
10069 MI.getOpcode() == PPC::SELECT_VRRC ||
10070 MI.getOpcode() == PPC::SELECT_VSFRC ||
10071 MI.getOpcode() == PPC::SELECT_VSSRC ||
10072 MI.getOpcode() == PPC::SELECT_VSRC) {
10073 BuildMI(BB, dl, TII->get(PPC::BC))
10074 .addReg(MI.getOperand(1).getReg())
10077 unsigned SelectPred = MI.getOperand(4).getImm();
10078 BuildMI(BB, dl, TII->get(PPC::BCC))
10079 .addImm(SelectPred)
10080 .addReg(MI.getOperand(1).getReg())
10085 // %FalseValue = ...
10086 // # fallthrough to sinkMBB
10089 // Update machine-CFG edges
10090 BB->addSuccessor(sinkMBB);
10093 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
10096 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::PHI), MI.getOperand(0).getReg())
10097 .addReg(MI.getOperand(3).getReg())
10099 .addReg(MI.getOperand(2).getReg())
10101 } else if (MI.getOpcode() == PPC::ReadTB) {
10102 // To read the 64-bit time-base register on a 32-bit target, we read the
10103 // two halves. Should the counter have wrapped while it was being read, we
10104 // need to try again.
10107 // mfspr Rx,TBU # load from TBU
10108 // mfspr Ry,TB # load from TB
10109 // mfspr Rz,TBU # load from TBU
10110 // cmpw crX,Rx,Rz # check if 'old'='new'
10111 // bne readLoop # branch if they're not equal
10114 MachineBasicBlock *readMBB = F->CreateMachineBasicBlock(LLVM_BB);
10115 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
10116 DebugLoc dl = MI.getDebugLoc();
10117 F->insert(It, readMBB);
10118 F->insert(It, sinkMBB);
10120 // Transfer the remainder of BB and its successor edges to sinkMBB.
10121 sinkMBB->splice(sinkMBB->begin(), BB,
10122 std::next(MachineBasicBlock::iterator(MI)), BB->end());
10123 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
10125 BB->addSuccessor(readMBB);
10128 MachineRegisterInfo &RegInfo = F->getRegInfo();
10129 unsigned ReadAgainReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
10130 unsigned LoReg = MI.getOperand(0).getReg();
10131 unsigned HiReg = MI.getOperand(1).getReg();
10133 BuildMI(BB, dl, TII->get(PPC::MFSPR), HiReg).addImm(269);
10134 BuildMI(BB, dl, TII->get(PPC::MFSPR), LoReg).addImm(268);
10135 BuildMI(BB, dl, TII->get(PPC::MFSPR), ReadAgainReg).addImm(269);
10137 unsigned CmpReg = RegInfo.createVirtualRegister(&PPC::CRRCRegClass);
10139 BuildMI(BB, dl, TII->get(PPC::CMPW), CmpReg)
10140 .addReg(HiReg).addReg(ReadAgainReg);
10141 BuildMI(BB, dl, TII->get(PPC::BCC))
10142 .addImm(PPC::PRED_NE).addReg(CmpReg).addMBB(readMBB);
10144 BB->addSuccessor(readMBB);
10145 BB->addSuccessor(sinkMBB);
10146 } else if (MI.getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
10147 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
10148 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
10149 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
10150 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
10151 BB = EmitAtomicBinary(MI, BB, 4, PPC::ADD4);
10152 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
10153 BB = EmitAtomicBinary(MI, BB, 8, PPC::ADD8);
10155 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
10156 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
10157 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
10158 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
10159 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
10160 BB = EmitAtomicBinary(MI, BB, 4, PPC::AND);
10161 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
10162 BB = EmitAtomicBinary(MI, BB, 8, PPC::AND8);
10164 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
10165 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
10166 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
10167 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
10168 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
10169 BB = EmitAtomicBinary(MI, BB, 4, PPC::OR);
10170 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
10171 BB = EmitAtomicBinary(MI, BB, 8, PPC::OR8);
10173 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
10174 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
10175 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
10176 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
10177 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
10178 BB = EmitAtomicBinary(MI, BB, 4, PPC::XOR);
10179 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
10180 BB = EmitAtomicBinary(MI, BB, 8, PPC::XOR8);
10182 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
10183 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::NAND);
10184 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
10185 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::NAND);
10186 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
10187 BB = EmitAtomicBinary(MI, BB, 4, PPC::NAND);
10188 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
10189 BB = EmitAtomicBinary(MI, BB, 8, PPC::NAND8);
10191 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
10192 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
10193 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
10194 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
10195 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
10196 BB = EmitAtomicBinary(MI, BB, 4, PPC::SUBF);
10197 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
10198 BB = EmitAtomicBinary(MI, BB, 8, PPC::SUBF8);
10200 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_MIN_I8)
10201 BB = EmitPartwordAtomicBinary(MI, BB, true, 0, PPC::CMPW, PPC::PRED_GE);
10202 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_MIN_I16)
10203 BB = EmitPartwordAtomicBinary(MI, BB, false, 0, PPC::CMPW, PPC::PRED_GE);
10204 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_MIN_I32)
10205 BB = EmitAtomicBinary(MI, BB, 4, 0, PPC::CMPW, PPC::PRED_GE);
10206 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_MIN_I64)
10207 BB = EmitAtomicBinary(MI, BB, 8, 0, PPC::CMPD, PPC::PRED_GE);
10209 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_MAX_I8)
10210 BB = EmitPartwordAtomicBinary(MI, BB, true, 0, PPC::CMPW, PPC::PRED_LE);
10211 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_MAX_I16)
10212 BB = EmitPartwordAtomicBinary(MI, BB, false, 0, PPC::CMPW, PPC::PRED_LE);
10213 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_MAX_I32)
10214 BB = EmitAtomicBinary(MI, BB, 4, 0, PPC::CMPW, PPC::PRED_LE);
10215 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_MAX_I64)
10216 BB = EmitAtomicBinary(MI, BB, 8, 0, PPC::CMPD, PPC::PRED_LE);
10218 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_UMIN_I8)
10219 BB = EmitPartwordAtomicBinary(MI, BB, true, 0, PPC::CMPLW, PPC::PRED_GE);
10220 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_UMIN_I16)
10221 BB = EmitPartwordAtomicBinary(MI, BB, false, 0, PPC::CMPLW, PPC::PRED_GE);
10222 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_UMIN_I32)
10223 BB = EmitAtomicBinary(MI, BB, 4, 0, PPC::CMPLW, PPC::PRED_GE);
10224 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_UMIN_I64)
10225 BB = EmitAtomicBinary(MI, BB, 8, 0, PPC::CMPLD, PPC::PRED_GE);
10227 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_UMAX_I8)
10228 BB = EmitPartwordAtomicBinary(MI, BB, true, 0, PPC::CMPLW, PPC::PRED_LE);
10229 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_UMAX_I16)
10230 BB = EmitPartwordAtomicBinary(MI, BB, false, 0, PPC::CMPLW, PPC::PRED_LE);
10231 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_UMAX_I32)
10232 BB = EmitAtomicBinary(MI, BB, 4, 0, PPC::CMPLW, PPC::PRED_LE);
10233 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_UMAX_I64)
10234 BB = EmitAtomicBinary(MI, BB, 8, 0, PPC::CMPLD, PPC::PRED_LE);
10236 else if (MI.getOpcode() == PPC::ATOMIC_SWAP_I8)
10237 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
10238 else if (MI.getOpcode() == PPC::ATOMIC_SWAP_I16)
10239 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
10240 else if (MI.getOpcode() == PPC::ATOMIC_SWAP_I32)
10241 BB = EmitAtomicBinary(MI, BB, 4, 0);
10242 else if (MI.getOpcode() == PPC::ATOMIC_SWAP_I64)
10243 BB = EmitAtomicBinary(MI, BB, 8, 0);
10244 else if (MI.getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
10245 MI.getOpcode() == PPC::ATOMIC_CMP_SWAP_I64 ||
10246 (Subtarget.hasPartwordAtomics() &&
10247 MI.getOpcode() == PPC::ATOMIC_CMP_SWAP_I8) ||
10248 (Subtarget.hasPartwordAtomics() &&
10249 MI.getOpcode() == PPC::ATOMIC_CMP_SWAP_I16)) {
10250 bool is64bit = MI.getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
10252 auto LoadMnemonic = PPC::LDARX;
10253 auto StoreMnemonic = PPC::STDCX;
10254 switch (MI.getOpcode()) {
10256 llvm_unreachable("Compare and swap of unknown size");
10257 case PPC::ATOMIC_CMP_SWAP_I8:
10258 LoadMnemonic = PPC::LBARX;
10259 StoreMnemonic = PPC::STBCX;
10260 assert(Subtarget.hasPartwordAtomics() && "No support partword atomics.");
10262 case PPC::ATOMIC_CMP_SWAP_I16:
10263 LoadMnemonic = PPC::LHARX;
10264 StoreMnemonic = PPC::STHCX;
10265 assert(Subtarget.hasPartwordAtomics() && "No support partword atomics.");
10267 case PPC::ATOMIC_CMP_SWAP_I32:
10268 LoadMnemonic = PPC::LWARX;
10269 StoreMnemonic = PPC::STWCX;
10271 case PPC::ATOMIC_CMP_SWAP_I64:
10272 LoadMnemonic = PPC::LDARX;
10273 StoreMnemonic = PPC::STDCX;
10276 unsigned dest = MI.getOperand(0).getReg();
10277 unsigned ptrA = MI.getOperand(1).getReg();
10278 unsigned ptrB = MI.getOperand(2).getReg();
10279 unsigned oldval = MI.getOperand(3).getReg();
10280 unsigned newval = MI.getOperand(4).getReg();
10281 DebugLoc dl = MI.getDebugLoc();
10283 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
10284 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
10285 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
10286 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
10287 F->insert(It, loop1MBB);
10288 F->insert(It, loop2MBB);
10289 F->insert(It, midMBB);
10290 F->insert(It, exitMBB);
10291 exitMBB->splice(exitMBB->begin(), BB,
10292 std::next(MachineBasicBlock::iterator(MI)), BB->end());
10293 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
10297 // fallthrough --> loopMBB
10298 BB->addSuccessor(loop1MBB);
10301 // l[bhwd]arx dest, ptr
10302 // cmp[wd] dest, oldval
10305 // st[bhwd]cx. newval, ptr
10309 // st[bhwd]cx. dest, ptr
10312 BuildMI(BB, dl, TII->get(LoadMnemonic), dest)
10313 .addReg(ptrA).addReg(ptrB);
10314 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
10315 .addReg(oldval).addReg(dest);
10316 BuildMI(BB, dl, TII->get(PPC::BCC))
10317 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
10318 BB->addSuccessor(loop2MBB);
10319 BB->addSuccessor(midMBB);
10322 BuildMI(BB, dl, TII->get(StoreMnemonic))
10323 .addReg(newval).addReg(ptrA).addReg(ptrB);
10324 BuildMI(BB, dl, TII->get(PPC::BCC))
10325 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
10326 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
10327 BB->addSuccessor(loop1MBB);
10328 BB->addSuccessor(exitMBB);
10331 BuildMI(BB, dl, TII->get(StoreMnemonic))
10332 .addReg(dest).addReg(ptrA).addReg(ptrB);
10333 BB->addSuccessor(exitMBB);
10338 } else if (MI.getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
10339 MI.getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
10340 // We must use 64-bit registers for addresses when targeting 64-bit,
10341 // since we're actually doing arithmetic on them. Other registers
10343 bool is64bit = Subtarget.isPPC64();
10344 bool isLittleEndian = Subtarget.isLittleEndian();
10345 bool is8bit = MI.getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
10347 unsigned dest = MI.getOperand(0).getReg();
10348 unsigned ptrA = MI.getOperand(1).getReg();
10349 unsigned ptrB = MI.getOperand(2).getReg();
10350 unsigned oldval = MI.getOperand(3).getReg();
10351 unsigned newval = MI.getOperand(4).getReg();
10352 DebugLoc dl = MI.getDebugLoc();
10354 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
10355 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
10356 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
10357 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
10358 F->insert(It, loop1MBB);
10359 F->insert(It, loop2MBB);
10360 F->insert(It, midMBB);
10361 F->insert(It, exitMBB);
10362 exitMBB->splice(exitMBB->begin(), BB,
10363 std::next(MachineBasicBlock::iterator(MI)), BB->end());
10364 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
10366 MachineRegisterInfo &RegInfo = F->getRegInfo();
10367 const TargetRegisterClass *RC = is64bit ? &PPC::G8RCRegClass
10368 : &PPC::GPRCRegClass;
10369 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
10370 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
10371 unsigned ShiftReg =
10372 isLittleEndian ? Shift1Reg : RegInfo.createVirtualRegister(RC);
10373 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
10374 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
10375 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
10376 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
10377 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
10378 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
10379 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
10380 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
10381 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
10382 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
10384 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
10385 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
10388 // fallthrough --> loopMBB
10389 BB->addSuccessor(loop1MBB);
10391 // The 4-byte load must be aligned, while a char or short may be
10392 // anywhere in the word. Hence all this nasty bookkeeping code.
10393 // add ptr1, ptrA, ptrB [copy if ptrA==0]
10394 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
10395 // xori shift, shift1, 24 [16]
10396 // rlwinm ptr, ptr1, 0, 0, 29
10397 // slw newval2, newval, shift
10398 // slw oldval2, oldval,shift
10399 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
10400 // slw mask, mask2, shift
10401 // and newval3, newval2, mask
10402 // and oldval3, oldval2, mask
10404 // lwarx tmpDest, ptr
10405 // and tmp, tmpDest, mask
10406 // cmpw tmp, oldval3
10409 // andc tmp2, tmpDest, mask
10410 // or tmp4, tmp2, newval3
10411 // stwcx. tmp4, ptr
10415 // stwcx. tmpDest, ptr
10417 // srw dest, tmpDest, shift
10418 if (ptrA != ZeroReg) {
10419 Ptr1Reg = RegInfo.createVirtualRegister(RC);
10420 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
10421 .addReg(ptrA).addReg(ptrB);
10425 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
10426 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
10427 if (!isLittleEndian)
10428 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
10429 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
10431 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
10432 .addReg(Ptr1Reg).addImm(0).addImm(61);
10434 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
10435 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
10436 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
10437 .addReg(newval).addReg(ShiftReg);
10438 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
10439 .addReg(oldval).addReg(ShiftReg);
10441 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
10443 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
10444 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
10445 .addReg(Mask3Reg).addImm(65535);
10447 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
10448 .addReg(Mask2Reg).addReg(ShiftReg);
10449 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
10450 .addReg(NewVal2Reg).addReg(MaskReg);
10451 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
10452 .addReg(OldVal2Reg).addReg(MaskReg);
10455 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
10456 .addReg(ZeroReg).addReg(PtrReg);
10457 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
10458 .addReg(TmpDestReg).addReg(MaskReg);
10459 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
10460 .addReg(TmpReg).addReg(OldVal3Reg);
10461 BuildMI(BB, dl, TII->get(PPC::BCC))
10462 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
10463 BB->addSuccessor(loop2MBB);
10464 BB->addSuccessor(midMBB);
10467 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
10468 .addReg(TmpDestReg).addReg(MaskReg);
10469 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
10470 .addReg(Tmp2Reg).addReg(NewVal3Reg);
10471 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
10472 .addReg(ZeroReg).addReg(PtrReg);
10473 BuildMI(BB, dl, TII->get(PPC::BCC))
10474 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
10475 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
10476 BB->addSuccessor(loop1MBB);
10477 BB->addSuccessor(exitMBB);
10480 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
10481 .addReg(ZeroReg).addReg(PtrReg);
10482 BB->addSuccessor(exitMBB);
10487 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg)
10489 } else if (MI.getOpcode() == PPC::FADDrtz) {
10490 // This pseudo performs an FADD with rounding mode temporarily forced
10491 // to round-to-zero. We emit this via custom inserter since the FPSCR
10492 // is not modeled at the SelectionDAG level.
10493 unsigned Dest = MI.getOperand(0).getReg();
10494 unsigned Src1 = MI.getOperand(1).getReg();
10495 unsigned Src2 = MI.getOperand(2).getReg();
10496 DebugLoc dl = MI.getDebugLoc();
10498 MachineRegisterInfo &RegInfo = F->getRegInfo();
10499 unsigned MFFSReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
10501 // Save FPSCR value.
10502 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), MFFSReg);
10504 // Set rounding mode to round-to-zero.
10505 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB1)).addImm(31);
10506 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB0)).addImm(30);
10508 // Perform addition.
10509 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);
10511 // Restore FPSCR value.
10512 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSFb)).addImm(1).addReg(MFFSReg);
10513 } else if (MI.getOpcode() == PPC::ANDIo_1_EQ_BIT ||
10514 MI.getOpcode() == PPC::ANDIo_1_GT_BIT ||
10515 MI.getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
10516 MI.getOpcode() == PPC::ANDIo_1_GT_BIT8) {
10517 unsigned Opcode = (MI.getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
10518 MI.getOpcode() == PPC::ANDIo_1_GT_BIT8)
10521 bool isEQ = (MI.getOpcode() == PPC::ANDIo_1_EQ_BIT ||
10522 MI.getOpcode() == PPC::ANDIo_1_EQ_BIT8);
10524 MachineRegisterInfo &RegInfo = F->getRegInfo();
10525 unsigned Dest = RegInfo.createVirtualRegister(Opcode == PPC::ANDIo ?
10526 &PPC::GPRCRegClass :
10527 &PPC::G8RCRegClass);
10529 DebugLoc dl = MI.getDebugLoc();
10530 BuildMI(*BB, MI, dl, TII->get(Opcode), Dest)
10531 .addReg(MI.getOperand(1).getReg())
10533 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY),
10534 MI.getOperand(0).getReg())
10535 .addReg(isEQ ? PPC::CR0EQ : PPC::CR0GT);
10536 } else if (MI.getOpcode() == PPC::TCHECK_RET) {
10537 DebugLoc Dl = MI.getDebugLoc();
10538 MachineRegisterInfo &RegInfo = F->getRegInfo();
10539 unsigned CRReg = RegInfo.createVirtualRegister(&PPC::CRRCRegClass);
10540 BuildMI(*BB, MI, Dl, TII->get(PPC::TCHECK), CRReg);
10543 llvm_unreachable("Unexpected instr type to insert");
10546 MI.eraseFromParent(); // The pseudo instruction is gone now.
10550 //===----------------------------------------------------------------------===//
10551 // Target Optimization Hooks
10552 //===----------------------------------------------------------------------===//
10554 static int getEstimateRefinementSteps(EVT VT, const PPCSubtarget &Subtarget) {
10555 // For the estimates, convergence is quadratic, so we essentially double the
10556 // number of digits correct after every iteration. For both FRE and FRSQRTE,
10557 // the minimum architected relative accuracy is 2^-5. When hasRecipPrec(),
10558 // this is 2^-14. IEEE float has 23 digits and double has 52 digits.
10559 int RefinementSteps = Subtarget.hasRecipPrec() ? 1 : 3;
10560 if (VT.getScalarType() == MVT::f64)
10562 return RefinementSteps;
10565 SDValue PPCTargetLowering::getSqrtEstimate(SDValue Operand, SelectionDAG &DAG,
10566 int Enabled, int &RefinementSteps,
10567 bool &UseOneConstNR,
10568 bool Reciprocal) const {
10569 EVT VT = Operand.getValueType();
10570 if ((VT == MVT::f32 && Subtarget.hasFRSQRTES()) ||
10571 (VT == MVT::f64 && Subtarget.hasFRSQRTE()) ||
10572 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
10573 (VT == MVT::v2f64 && Subtarget.hasVSX()) ||
10574 (VT == MVT::v4f32 && Subtarget.hasQPX()) ||
10575 (VT == MVT::v4f64 && Subtarget.hasQPX())) {
10576 if (RefinementSteps == ReciprocalEstimate::Unspecified)
10577 RefinementSteps = getEstimateRefinementSteps(VT, Subtarget);
10579 UseOneConstNR = true;
10580 return DAG.getNode(PPCISD::FRSQRTE, SDLoc(Operand), VT, Operand);
10585 SDValue PPCTargetLowering::getRecipEstimate(SDValue Operand, SelectionDAG &DAG,
10587 int &RefinementSteps) const {
10588 EVT VT = Operand.getValueType();
10589 if ((VT == MVT::f32 && Subtarget.hasFRES()) ||
10590 (VT == MVT::f64 && Subtarget.hasFRE()) ||
10591 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
10592 (VT == MVT::v2f64 && Subtarget.hasVSX()) ||
10593 (VT == MVT::v4f32 && Subtarget.hasQPX()) ||
10594 (VT == MVT::v4f64 && Subtarget.hasQPX())) {
10595 if (RefinementSteps == ReciprocalEstimate::Unspecified)
10596 RefinementSteps = getEstimateRefinementSteps(VT, Subtarget);
10597 return DAG.getNode(PPCISD::FRE, SDLoc(Operand), VT, Operand);
10602 unsigned PPCTargetLowering::combineRepeatedFPDivisors() const {
10603 // Note: This functionality is used only when unsafe-fp-math is enabled, and
10604 // on cores with reciprocal estimates (which are used when unsafe-fp-math is
10605 // enabled for division), this functionality is redundant with the default
10606 // combiner logic (once the division -> reciprocal/multiply transformation
10607 // has taken place). As a result, this matters more for older cores than for
10610 // Combine multiple FDIVs with the same divisor into multiple FMULs by the
10611 // reciprocal if there are two or more FDIVs (for embedded cores with only
10612 // one FP pipeline) for three or more FDIVs (for generic OOO cores).
10613 switch (Subtarget.getDarwinDirective()) {
10618 case PPC::DIR_E500mc:
10619 case PPC::DIR_E5500:
10624 // isConsecutiveLSLoc needs to work even if all adds have not yet been
10625 // collapsed, and so we need to look through chains of them.
10626 static void getBaseWithConstantOffset(SDValue Loc, SDValue &Base,
10627 int64_t& Offset, SelectionDAG &DAG) {
10628 if (DAG.isBaseWithConstantOffset(Loc)) {
10629 Base = Loc.getOperand(0);
10630 Offset += cast<ConstantSDNode>(Loc.getOperand(1))->getSExtValue();
10632 // The base might itself be a base plus an offset, and if so, accumulate
10634 getBaseWithConstantOffset(Loc.getOperand(0), Base, Offset, DAG);
10638 static bool isConsecutiveLSLoc(SDValue Loc, EVT VT, LSBaseSDNode *Base,
10639 unsigned Bytes, int Dist,
10640 SelectionDAG &DAG) {
10641 if (VT.getSizeInBits() / 8 != Bytes)
10644 SDValue BaseLoc = Base->getBasePtr();
10645 if (Loc.getOpcode() == ISD::FrameIndex) {
10646 if (BaseLoc.getOpcode() != ISD::FrameIndex)
10648 const MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
10649 int FI = cast<FrameIndexSDNode>(Loc)->getIndex();
10650 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex();
10651 int FS = MFI.getObjectSize(FI);
10652 int BFS = MFI.getObjectSize(BFI);
10653 if (FS != BFS || FS != (int)Bytes) return false;
10654 return MFI.getObjectOffset(FI) == (MFI.getObjectOffset(BFI) + Dist*Bytes);
10657 SDValue Base1 = Loc, Base2 = BaseLoc;
10658 int64_t Offset1 = 0, Offset2 = 0;
10659 getBaseWithConstantOffset(Loc, Base1, Offset1, DAG);
10660 getBaseWithConstantOffset(BaseLoc, Base2, Offset2, DAG);
10661 if (Base1 == Base2 && Offset1 == (Offset2 + Dist * Bytes))
10664 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
10665 const GlobalValue *GV1 = nullptr;
10666 const GlobalValue *GV2 = nullptr;
10669 bool isGA1 = TLI.isGAPlusOffset(Loc.getNode(), GV1, Offset1);
10670 bool isGA2 = TLI.isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2);
10671 if (isGA1 && isGA2 && GV1 == GV2)
10672 return Offset1 == (Offset2 + Dist*Bytes);
10676 // Like SelectionDAG::isConsecutiveLoad, but also works for stores, and does
10677 // not enforce equality of the chain operands.
10678 static bool isConsecutiveLS(SDNode *N, LSBaseSDNode *Base,
10679 unsigned Bytes, int Dist,
10680 SelectionDAG &DAG) {
10681 if (LSBaseSDNode *LS = dyn_cast<LSBaseSDNode>(N)) {
10682 EVT VT = LS->getMemoryVT();
10683 SDValue Loc = LS->getBasePtr();
10684 return isConsecutiveLSLoc(Loc, VT, Base, Bytes, Dist, DAG);
10687 if (N->getOpcode() == ISD::INTRINSIC_W_CHAIN) {
10689 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
10690 default: return false;
10691 case Intrinsic::ppc_qpx_qvlfd:
10692 case Intrinsic::ppc_qpx_qvlfda:
10695 case Intrinsic::ppc_qpx_qvlfs:
10696 case Intrinsic::ppc_qpx_qvlfsa:
10699 case Intrinsic::ppc_qpx_qvlfcd:
10700 case Intrinsic::ppc_qpx_qvlfcda:
10703 case Intrinsic::ppc_qpx_qvlfcs:
10704 case Intrinsic::ppc_qpx_qvlfcsa:
10707 case Intrinsic::ppc_qpx_qvlfiwa:
10708 case Intrinsic::ppc_qpx_qvlfiwz:
10709 case Intrinsic::ppc_altivec_lvx:
10710 case Intrinsic::ppc_altivec_lvxl:
10711 case Intrinsic::ppc_vsx_lxvw4x:
10712 case Intrinsic::ppc_vsx_lxvw4x_be:
10715 case Intrinsic::ppc_vsx_lxvd2x:
10716 case Intrinsic::ppc_vsx_lxvd2x_be:
10719 case Intrinsic::ppc_altivec_lvebx:
10722 case Intrinsic::ppc_altivec_lvehx:
10725 case Intrinsic::ppc_altivec_lvewx:
10730 return isConsecutiveLSLoc(N->getOperand(2), VT, Base, Bytes, Dist, DAG);
10733 if (N->getOpcode() == ISD::INTRINSIC_VOID) {
10735 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
10736 default: return false;
10737 case Intrinsic::ppc_qpx_qvstfd:
10738 case Intrinsic::ppc_qpx_qvstfda:
10741 case Intrinsic::ppc_qpx_qvstfs:
10742 case Intrinsic::ppc_qpx_qvstfsa:
10745 case Intrinsic::ppc_qpx_qvstfcd:
10746 case Intrinsic::ppc_qpx_qvstfcda:
10749 case Intrinsic::ppc_qpx_qvstfcs:
10750 case Intrinsic::ppc_qpx_qvstfcsa:
10753 case Intrinsic::ppc_qpx_qvstfiw:
10754 case Intrinsic::ppc_qpx_qvstfiwa:
10755 case Intrinsic::ppc_altivec_stvx:
10756 case Intrinsic::ppc_altivec_stvxl:
10757 case Intrinsic::ppc_vsx_stxvw4x:
10760 case Intrinsic::ppc_vsx_stxvd2x:
10763 case Intrinsic::ppc_vsx_stxvw4x_be:
10766 case Intrinsic::ppc_vsx_stxvd2x_be:
10769 case Intrinsic::ppc_altivec_stvebx:
10772 case Intrinsic::ppc_altivec_stvehx:
10775 case Intrinsic::ppc_altivec_stvewx:
10780 return isConsecutiveLSLoc(N->getOperand(3), VT, Base, Bytes, Dist, DAG);
10786 // Return true is there is a nearyby consecutive load to the one provided
10787 // (regardless of alignment). We search up and down the chain, looking though
10788 // token factors and other loads (but nothing else). As a result, a true result
10789 // indicates that it is safe to create a new consecutive load adjacent to the
10791 static bool findConsecutiveLoad(LoadSDNode *LD, SelectionDAG &DAG) {
10792 SDValue Chain = LD->getChain();
10793 EVT VT = LD->getMemoryVT();
10795 SmallSet<SDNode *, 16> LoadRoots;
10796 SmallVector<SDNode *, 8> Queue(1, Chain.getNode());
10797 SmallSet<SDNode *, 16> Visited;
10799 // First, search up the chain, branching to follow all token-factor operands.
10800 // If we find a consecutive load, then we're done, otherwise, record all
10801 // nodes just above the top-level loads and token factors.
10802 while (!Queue.empty()) {
10803 SDNode *ChainNext = Queue.pop_back_val();
10804 if (!Visited.insert(ChainNext).second)
10807 if (MemSDNode *ChainLD = dyn_cast<MemSDNode>(ChainNext)) {
10808 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
10811 if (!Visited.count(ChainLD->getChain().getNode()))
10812 Queue.push_back(ChainLD->getChain().getNode());
10813 } else if (ChainNext->getOpcode() == ISD::TokenFactor) {
10814 for (const SDUse &O : ChainNext->ops())
10815 if (!Visited.count(O.getNode()))
10816 Queue.push_back(O.getNode());
10818 LoadRoots.insert(ChainNext);
10821 // Second, search down the chain, starting from the top-level nodes recorded
10822 // in the first phase. These top-level nodes are the nodes just above all
10823 // loads and token factors. Starting with their uses, recursively look though
10824 // all loads (just the chain uses) and token factors to find a consecutive
10829 for (SmallSet<SDNode *, 16>::iterator I = LoadRoots.begin(),
10830 IE = LoadRoots.end(); I != IE; ++I) {
10831 Queue.push_back(*I);
10833 while (!Queue.empty()) {
10834 SDNode *LoadRoot = Queue.pop_back_val();
10835 if (!Visited.insert(LoadRoot).second)
10838 if (MemSDNode *ChainLD = dyn_cast<MemSDNode>(LoadRoot))
10839 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
10842 for (SDNode::use_iterator UI = LoadRoot->use_begin(),
10843 UE = LoadRoot->use_end(); UI != UE; ++UI)
10844 if (((isa<MemSDNode>(*UI) &&
10845 cast<MemSDNode>(*UI)->getChain().getNode() == LoadRoot) ||
10846 UI->getOpcode() == ISD::TokenFactor) && !Visited.count(*UI))
10847 Queue.push_back(*UI);
10854 /// This function is called when we have proved that a SETCC node can be replaced
10855 /// by subtraction (and other supporting instructions) so that the result of
10856 /// comparison is kept in a GPR instead of CR. This function is purely for
10857 /// codegen purposes and has some flags to guide the codegen process.
10858 static SDValue generateEquivalentSub(SDNode *N, int Size, bool Complement,
10859 bool Swap, SDLoc &DL, SelectionDAG &DAG) {
10860 assert(N->getOpcode() == ISD::SETCC && "ISD::SETCC Expected.");
10862 // Zero extend the operands to the largest legal integer. Originally, they
10863 // must be of a strictly smaller size.
10864 auto Op0 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, N->getOperand(0),
10865 DAG.getConstant(Size, DL, MVT::i32));
10866 auto Op1 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, N->getOperand(1),
10867 DAG.getConstant(Size, DL, MVT::i32));
10869 // Swap if needed. Depends on the condition code.
10871 std::swap(Op0, Op1);
10873 // Subtract extended integers.
10874 auto SubNode = DAG.getNode(ISD::SUB, DL, MVT::i64, Op0, Op1);
10876 // Move the sign bit to the least significant position and zero out the rest.
10877 // Now the least significant bit carries the result of original comparison.
10878 auto Shifted = DAG.getNode(ISD::SRL, DL, MVT::i64, SubNode,
10879 DAG.getConstant(Size - 1, DL, MVT::i32));
10880 auto Final = Shifted;
10882 // Complement the result if needed. Based on the condition code.
10884 Final = DAG.getNode(ISD::XOR, DL, MVT::i64, Shifted,
10885 DAG.getConstant(1, DL, MVT::i64));
10887 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Final);
10890 SDValue PPCTargetLowering::ConvertSETCCToSubtract(SDNode *N,
10891 DAGCombinerInfo &DCI) const {
10892 assert(N->getOpcode() == ISD::SETCC && "ISD::SETCC Expected.");
10894 SelectionDAG &DAG = DCI.DAG;
10897 // Size of integers being compared has a critical role in the following
10898 // analysis, so we prefer to do this when all types are legal.
10899 if (!DCI.isAfterLegalizeVectorOps())
10902 // If all users of SETCC extend its value to a legal integer type
10903 // then we replace SETCC with a subtraction
10904 for (SDNode::use_iterator UI = N->use_begin(),
10905 UE = N->use_end(); UI != UE; ++UI) {
10906 if (UI->getOpcode() != ISD::ZERO_EXTEND)
10910 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
10911 auto OpSize = N->getOperand(0).getValueSizeInBits();
10913 unsigned Size = DAG.getDataLayout().getLargestLegalIntTypeSizeInBits();
10915 if (OpSize < Size) {
10919 return generateEquivalentSub(N, Size, false, false, DL, DAG);
10921 return generateEquivalentSub(N, Size, true, true, DL, DAG);
10923 return generateEquivalentSub(N, Size, false, true, DL, DAG);
10925 return generateEquivalentSub(N, Size, true, false, DL, DAG);
10932 SDValue PPCTargetLowering::DAGCombineTruncBoolExt(SDNode *N,
10933 DAGCombinerInfo &DCI) const {
10934 SelectionDAG &DAG = DCI.DAG;
10937 assert(Subtarget.useCRBits() && "Expecting to be tracking CR bits");
10938 // If we're tracking CR bits, we need to be careful that we don't have:
10939 // trunc(binary-ops(zext(x), zext(y)))
10941 // trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
10942 // such that we're unnecessarily moving things into GPRs when it would be
10943 // better to keep them in CR bits.
10945 // Note that trunc here can be an actual i1 trunc, or can be the effective
10946 // truncation that comes from a setcc or select_cc.
10947 if (N->getOpcode() == ISD::TRUNCATE &&
10948 N->getValueType(0) != MVT::i1)
10951 if (N->getOperand(0).getValueType() != MVT::i32 &&
10952 N->getOperand(0).getValueType() != MVT::i64)
10955 if (N->getOpcode() == ISD::SETCC ||
10956 N->getOpcode() == ISD::SELECT_CC) {
10957 // If we're looking at a comparison, then we need to make sure that the
10958 // high bits (all except for the first) don't matter the result.
10960 cast<CondCodeSDNode>(N->getOperand(
10961 N->getOpcode() == ISD::SETCC ? 2 : 4))->get();
10962 unsigned OpBits = N->getOperand(0).getValueSizeInBits();
10964 if (ISD::isSignedIntSetCC(CC)) {
10965 if (DAG.ComputeNumSignBits(N->getOperand(0)) != OpBits ||
10966 DAG.ComputeNumSignBits(N->getOperand(1)) != OpBits)
10968 } else if (ISD::isUnsignedIntSetCC(CC)) {
10969 if (!DAG.MaskedValueIsZero(N->getOperand(0),
10970 APInt::getHighBitsSet(OpBits, OpBits-1)) ||
10971 !DAG.MaskedValueIsZero(N->getOperand(1),
10972 APInt::getHighBitsSet(OpBits, OpBits-1)))
10973 return (N->getOpcode() == ISD::SETCC ? ConvertSETCCToSubtract(N, DCI)
10976 // This is neither a signed nor an unsigned comparison, just make sure
10977 // that the high bits are equal.
10978 KnownBits Op1Known, Op2Known;
10979 DAG.computeKnownBits(N->getOperand(0), Op1Known);
10980 DAG.computeKnownBits(N->getOperand(1), Op2Known);
10982 // We don't really care about what is known about the first bit (if
10983 // anything), so clear it in all masks prior to comparing them.
10984 Op1Known.Zero.clearBit(0); Op1Known.One.clearBit(0);
10985 Op2Known.Zero.clearBit(0); Op2Known.One.clearBit(0);
10987 if (Op1Known.Zero != Op2Known.Zero || Op1Known.One != Op2Known.One)
10992 // We now know that the higher-order bits are irrelevant, we just need to
10993 // make sure that all of the intermediate operations are bit operations, and
10994 // all inputs are extensions.
10995 if (N->getOperand(0).getOpcode() != ISD::AND &&
10996 N->getOperand(0).getOpcode() != ISD::OR &&
10997 N->getOperand(0).getOpcode() != ISD::XOR &&
10998 N->getOperand(0).getOpcode() != ISD::SELECT &&
10999 N->getOperand(0).getOpcode() != ISD::SELECT_CC &&
11000 N->getOperand(0).getOpcode() != ISD::TRUNCATE &&
11001 N->getOperand(0).getOpcode() != ISD::SIGN_EXTEND &&
11002 N->getOperand(0).getOpcode() != ISD::ZERO_EXTEND &&
11003 N->getOperand(0).getOpcode() != ISD::ANY_EXTEND)
11006 if ((N->getOpcode() == ISD::SETCC || N->getOpcode() == ISD::SELECT_CC) &&
11007 N->getOperand(1).getOpcode() != ISD::AND &&
11008 N->getOperand(1).getOpcode() != ISD::OR &&
11009 N->getOperand(1).getOpcode() != ISD::XOR &&
11010 N->getOperand(1).getOpcode() != ISD::SELECT &&
11011 N->getOperand(1).getOpcode() != ISD::SELECT_CC &&
11012 N->getOperand(1).getOpcode() != ISD::TRUNCATE &&
11013 N->getOperand(1).getOpcode() != ISD::SIGN_EXTEND &&
11014 N->getOperand(1).getOpcode() != ISD::ZERO_EXTEND &&
11015 N->getOperand(1).getOpcode() != ISD::ANY_EXTEND)
11018 SmallVector<SDValue, 4> Inputs;
11019 SmallVector<SDValue, 8> BinOps, PromOps;
11020 SmallPtrSet<SDNode *, 16> Visited;
11022 for (unsigned i = 0; i < 2; ++i) {
11023 if (((N->getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
11024 N->getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
11025 N->getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
11026 N->getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
11027 isa<ConstantSDNode>(N->getOperand(i)))
11028 Inputs.push_back(N->getOperand(i));
11030 BinOps.push_back(N->getOperand(i));
11032 if (N->getOpcode() == ISD::TRUNCATE)
11036 // Visit all inputs, collect all binary operations (and, or, xor and
11037 // select) that are all fed by extensions.
11038 while (!BinOps.empty()) {
11039 SDValue BinOp = BinOps.back();
11042 if (!Visited.insert(BinOp.getNode()).second)
11045 PromOps.push_back(BinOp);
11047 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
11048 // The condition of the select is not promoted.
11049 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
11051 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
11054 if (((BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
11055 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
11056 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
11057 BinOp.getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
11058 isa<ConstantSDNode>(BinOp.getOperand(i))) {
11059 Inputs.push_back(BinOp.getOperand(i));
11060 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
11061 BinOp.getOperand(i).getOpcode() == ISD::OR ||
11062 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
11063 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
11064 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC ||
11065 BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
11066 BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
11067 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
11068 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) {
11069 BinOps.push_back(BinOp.getOperand(i));
11071 // We have an input that is not an extension or another binary
11072 // operation; we'll abort this transformation.
11078 // Make sure that this is a self-contained cluster of operations (which
11079 // is not quite the same thing as saying that everything has only one
11081 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
11082 if (isa<ConstantSDNode>(Inputs[i]))
11085 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
11086 UE = Inputs[i].getNode()->use_end();
11088 SDNode *User = *UI;
11089 if (User != N && !Visited.count(User))
11092 // Make sure that we're not going to promote the non-output-value
11093 // operand(s) or SELECT or SELECT_CC.
11094 // FIXME: Although we could sometimes handle this, and it does occur in
11095 // practice that one of the condition inputs to the select is also one of
11096 // the outputs, we currently can't deal with this.
11097 if (User->getOpcode() == ISD::SELECT) {
11098 if (User->getOperand(0) == Inputs[i])
11100 } else if (User->getOpcode() == ISD::SELECT_CC) {
11101 if (User->getOperand(0) == Inputs[i] ||
11102 User->getOperand(1) == Inputs[i])
11108 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
11109 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
11110 UE = PromOps[i].getNode()->use_end();
11112 SDNode *User = *UI;
11113 if (User != N && !Visited.count(User))
11116 // Make sure that we're not going to promote the non-output-value
11117 // operand(s) or SELECT or SELECT_CC.
11118 // FIXME: Although we could sometimes handle this, and it does occur in
11119 // practice that one of the condition inputs to the select is also one of
11120 // the outputs, we currently can't deal with this.
11121 if (User->getOpcode() == ISD::SELECT) {
11122 if (User->getOperand(0) == PromOps[i])
11124 } else if (User->getOpcode() == ISD::SELECT_CC) {
11125 if (User->getOperand(0) == PromOps[i] ||
11126 User->getOperand(1) == PromOps[i])
11132 // Replace all inputs with the extension operand.
11133 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
11134 // Constants may have users outside the cluster of to-be-promoted nodes,
11135 // and so we need to replace those as we do the promotions.
11136 if (isa<ConstantSDNode>(Inputs[i]))
11139 DAG.ReplaceAllUsesOfValueWith(Inputs[i], Inputs[i].getOperand(0));
11142 std::list<HandleSDNode> PromOpHandles;
11143 for (auto &PromOp : PromOps)
11144 PromOpHandles.emplace_back(PromOp);
11146 // Replace all operations (these are all the same, but have a different
11147 // (i1) return type). DAG.getNode will validate that the types of
11148 // a binary operator match, so go through the list in reverse so that
11149 // we've likely promoted both operands first. Any intermediate truncations or
11150 // extensions disappear.
11151 while (!PromOpHandles.empty()) {
11152 SDValue PromOp = PromOpHandles.back().getValue();
11153 PromOpHandles.pop_back();
11155 if (PromOp.getOpcode() == ISD::TRUNCATE ||
11156 PromOp.getOpcode() == ISD::SIGN_EXTEND ||
11157 PromOp.getOpcode() == ISD::ZERO_EXTEND ||
11158 PromOp.getOpcode() == ISD::ANY_EXTEND) {
11159 if (!isa<ConstantSDNode>(PromOp.getOperand(0)) &&
11160 PromOp.getOperand(0).getValueType() != MVT::i1) {
11161 // The operand is not yet ready (see comment below).
11162 PromOpHandles.emplace_front(PromOp);
11166 SDValue RepValue = PromOp.getOperand(0);
11167 if (isa<ConstantSDNode>(RepValue))
11168 RepValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, RepValue);
11170 DAG.ReplaceAllUsesOfValueWith(PromOp, RepValue);
11175 switch (PromOp.getOpcode()) {
11176 default: C = 0; break;
11177 case ISD::SELECT: C = 1; break;
11178 case ISD::SELECT_CC: C = 2; break;
11181 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
11182 PromOp.getOperand(C).getValueType() != MVT::i1) ||
11183 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
11184 PromOp.getOperand(C+1).getValueType() != MVT::i1)) {
11185 // The to-be-promoted operands of this node have not yet been
11186 // promoted (this should be rare because we're going through the
11187 // list backward, but if one of the operands has several users in
11188 // this cluster of to-be-promoted nodes, it is possible).
11189 PromOpHandles.emplace_front(PromOp);
11193 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
11194 PromOp.getNode()->op_end());
11196 // If there are any constant inputs, make sure they're replaced now.
11197 for (unsigned i = 0; i < 2; ++i)
11198 if (isa<ConstantSDNode>(Ops[C+i]))
11199 Ops[C+i] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ops[C+i]);
11201 DAG.ReplaceAllUsesOfValueWith(PromOp,
11202 DAG.getNode(PromOp.getOpcode(), dl, MVT::i1, Ops));
11205 // Now we're left with the initial truncation itself.
11206 if (N->getOpcode() == ISD::TRUNCATE)
11207 return N->getOperand(0);
11209 // Otherwise, this is a comparison. The operands to be compared have just
11210 // changed type (to i1), but everything else is the same.
11211 return SDValue(N, 0);
11214 SDValue PPCTargetLowering::DAGCombineExtBoolTrunc(SDNode *N,
11215 DAGCombinerInfo &DCI) const {
11216 SelectionDAG &DAG = DCI.DAG;
11219 // If we're tracking CR bits, we need to be careful that we don't have:
11220 // zext(binary-ops(trunc(x), trunc(y)))
11222 // zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
11223 // such that we're unnecessarily moving things into CR bits that can more
11224 // efficiently stay in GPRs. Note that if we're not certain that the high
11225 // bits are set as required by the final extension, we still may need to do
11226 // some masking to get the proper behavior.
11228 // This same functionality is important on PPC64 when dealing with
11229 // 32-to-64-bit extensions; these occur often when 32-bit values are used as
11230 // the return values of functions. Because it is so similar, it is handled
11233 if (N->getValueType(0) != MVT::i32 &&
11234 N->getValueType(0) != MVT::i64)
11237 if (!((N->getOperand(0).getValueType() == MVT::i1 && Subtarget.useCRBits()) ||
11238 (N->getOperand(0).getValueType() == MVT::i32 && Subtarget.isPPC64())))
11241 if (N->getOperand(0).getOpcode() != ISD::AND &&
11242 N->getOperand(0).getOpcode() != ISD::OR &&
11243 N->getOperand(0).getOpcode() != ISD::XOR &&
11244 N->getOperand(0).getOpcode() != ISD::SELECT &&
11245 N->getOperand(0).getOpcode() != ISD::SELECT_CC)
11248 SmallVector<SDValue, 4> Inputs;
11249 SmallVector<SDValue, 8> BinOps(1, N->getOperand(0)), PromOps;
11250 SmallPtrSet<SDNode *, 16> Visited;
11252 // Visit all inputs, collect all binary operations (and, or, xor and
11253 // select) that are all fed by truncations.
11254 while (!BinOps.empty()) {
11255 SDValue BinOp = BinOps.back();
11258 if (!Visited.insert(BinOp.getNode()).second)
11261 PromOps.push_back(BinOp);
11263 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
11264 // The condition of the select is not promoted.
11265 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
11267 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
11270 if (BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
11271 isa<ConstantSDNode>(BinOp.getOperand(i))) {
11272 Inputs.push_back(BinOp.getOperand(i));
11273 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
11274 BinOp.getOperand(i).getOpcode() == ISD::OR ||
11275 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
11276 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
11277 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC) {
11278 BinOps.push_back(BinOp.getOperand(i));
11280 // We have an input that is not a truncation or another binary
11281 // operation; we'll abort this transformation.
11287 // The operands of a select that must be truncated when the select is
11288 // promoted because the operand is actually part of the to-be-promoted set.
11289 DenseMap<SDNode *, EVT> SelectTruncOp[2];
11291 // Make sure that this is a self-contained cluster of operations (which
11292 // is not quite the same thing as saying that everything has only one
11294 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
11295 if (isa<ConstantSDNode>(Inputs[i]))
11298 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
11299 UE = Inputs[i].getNode()->use_end();
11301 SDNode *User = *UI;
11302 if (User != N && !Visited.count(User))
11305 // If we're going to promote the non-output-value operand(s) or SELECT or
11306 // SELECT_CC, record them for truncation.
11307 if (User->getOpcode() == ISD::SELECT) {
11308 if (User->getOperand(0) == Inputs[i])
11309 SelectTruncOp[0].insert(std::make_pair(User,
11310 User->getOperand(0).getValueType()));
11311 } else if (User->getOpcode() == ISD::SELECT_CC) {
11312 if (User->getOperand(0) == Inputs[i])
11313 SelectTruncOp[0].insert(std::make_pair(User,
11314 User->getOperand(0).getValueType()));
11315 if (User->getOperand(1) == Inputs[i])
11316 SelectTruncOp[1].insert(std::make_pair(User,
11317 User->getOperand(1).getValueType()));
11322 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
11323 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
11324 UE = PromOps[i].getNode()->use_end();
11326 SDNode *User = *UI;
11327 if (User != N && !Visited.count(User))
11330 // If we're going to promote the non-output-value operand(s) or SELECT or
11331 // SELECT_CC, record them for truncation.
11332 if (User->getOpcode() == ISD::SELECT) {
11333 if (User->getOperand(0) == PromOps[i])
11334 SelectTruncOp[0].insert(std::make_pair(User,
11335 User->getOperand(0).getValueType()));
11336 } else if (User->getOpcode() == ISD::SELECT_CC) {
11337 if (User->getOperand(0) == PromOps[i])
11338 SelectTruncOp[0].insert(std::make_pair(User,
11339 User->getOperand(0).getValueType()));
11340 if (User->getOperand(1) == PromOps[i])
11341 SelectTruncOp[1].insert(std::make_pair(User,
11342 User->getOperand(1).getValueType()));
11347 unsigned PromBits = N->getOperand(0).getValueSizeInBits();
11348 bool ReallyNeedsExt = false;
11349 if (N->getOpcode() != ISD::ANY_EXTEND) {
11350 // If all of the inputs are not already sign/zero extended, then
11351 // we'll still need to do that at the end.
11352 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
11353 if (isa<ConstantSDNode>(Inputs[i]))
11357 Inputs[i].getOperand(0).getValueSizeInBits();
11358 assert(PromBits < OpBits && "Truncation not to a smaller bit count?");
11360 if ((N->getOpcode() == ISD::ZERO_EXTEND &&
11361 !DAG.MaskedValueIsZero(Inputs[i].getOperand(0),
11362 APInt::getHighBitsSet(OpBits,
11363 OpBits-PromBits))) ||
11364 (N->getOpcode() == ISD::SIGN_EXTEND &&
11365 DAG.ComputeNumSignBits(Inputs[i].getOperand(0)) <
11366 (OpBits-(PromBits-1)))) {
11367 ReallyNeedsExt = true;
11373 // Replace all inputs, either with the truncation operand, or a
11374 // truncation or extension to the final output type.
11375 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
11376 // Constant inputs need to be replaced with the to-be-promoted nodes that
11377 // use them because they might have users outside of the cluster of
11379 if (isa<ConstantSDNode>(Inputs[i]))
11382 SDValue InSrc = Inputs[i].getOperand(0);
11383 if (Inputs[i].getValueType() == N->getValueType(0))
11384 DAG.ReplaceAllUsesOfValueWith(Inputs[i], InSrc);
11385 else if (N->getOpcode() == ISD::SIGN_EXTEND)
11386 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
11387 DAG.getSExtOrTrunc(InSrc, dl, N->getValueType(0)));
11388 else if (N->getOpcode() == ISD::ZERO_EXTEND)
11389 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
11390 DAG.getZExtOrTrunc(InSrc, dl, N->getValueType(0)));
11392 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
11393 DAG.getAnyExtOrTrunc(InSrc, dl, N->getValueType(0)));
11396 std::list<HandleSDNode> PromOpHandles;
11397 for (auto &PromOp : PromOps)
11398 PromOpHandles.emplace_back(PromOp);
11400 // Replace all operations (these are all the same, but have a different
11401 // (promoted) return type). DAG.getNode will validate that the types of
11402 // a binary operator match, so go through the list in reverse so that
11403 // we've likely promoted both operands first.
11404 while (!PromOpHandles.empty()) {
11405 SDValue PromOp = PromOpHandles.back().getValue();
11406 PromOpHandles.pop_back();
11409 switch (PromOp.getOpcode()) {
11410 default: C = 0; break;
11411 case ISD::SELECT: C = 1; break;
11412 case ISD::SELECT_CC: C = 2; break;
11415 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
11416 PromOp.getOperand(C).getValueType() != N->getValueType(0)) ||
11417 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
11418 PromOp.getOperand(C+1).getValueType() != N->getValueType(0))) {
11419 // The to-be-promoted operands of this node have not yet been
11420 // promoted (this should be rare because we're going through the
11421 // list backward, but if one of the operands has several users in
11422 // this cluster of to-be-promoted nodes, it is possible).
11423 PromOpHandles.emplace_front(PromOp);
11427 // For SELECT and SELECT_CC nodes, we do a similar check for any
11428 // to-be-promoted comparison inputs.
11429 if (PromOp.getOpcode() == ISD::SELECT ||
11430 PromOp.getOpcode() == ISD::SELECT_CC) {
11431 if ((SelectTruncOp[0].count(PromOp.getNode()) &&
11432 PromOp.getOperand(0).getValueType() != N->getValueType(0)) ||
11433 (SelectTruncOp[1].count(PromOp.getNode()) &&
11434 PromOp.getOperand(1).getValueType() != N->getValueType(0))) {
11435 PromOpHandles.emplace_front(PromOp);
11440 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
11441 PromOp.getNode()->op_end());
11443 // If this node has constant inputs, then they'll need to be promoted here.
11444 for (unsigned i = 0; i < 2; ++i) {
11445 if (!isa<ConstantSDNode>(Ops[C+i]))
11447 if (Ops[C+i].getValueType() == N->getValueType(0))
11450 if (N->getOpcode() == ISD::SIGN_EXTEND)
11451 Ops[C+i] = DAG.getSExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
11452 else if (N->getOpcode() == ISD::ZERO_EXTEND)
11453 Ops[C+i] = DAG.getZExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
11455 Ops[C+i] = DAG.getAnyExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
11458 // If we've promoted the comparison inputs of a SELECT or SELECT_CC,
11459 // truncate them again to the original value type.
11460 if (PromOp.getOpcode() == ISD::SELECT ||
11461 PromOp.getOpcode() == ISD::SELECT_CC) {
11462 auto SI0 = SelectTruncOp[0].find(PromOp.getNode());
11463 if (SI0 != SelectTruncOp[0].end())
11464 Ops[0] = DAG.getNode(ISD::TRUNCATE, dl, SI0->second, Ops[0]);
11465 auto SI1 = SelectTruncOp[1].find(PromOp.getNode());
11466 if (SI1 != SelectTruncOp[1].end())
11467 Ops[1] = DAG.getNode(ISD::TRUNCATE, dl, SI1->second, Ops[1]);
11470 DAG.ReplaceAllUsesOfValueWith(PromOp,
11471 DAG.getNode(PromOp.getOpcode(), dl, N->getValueType(0), Ops));
11474 // Now we're left with the initial extension itself.
11475 if (!ReallyNeedsExt)
11476 return N->getOperand(0);
11478 // To zero extend, just mask off everything except for the first bit (in the
11480 if (N->getOpcode() == ISD::ZERO_EXTEND)
11481 return DAG.getNode(ISD::AND, dl, N->getValueType(0), N->getOperand(0),
11482 DAG.getConstant(APInt::getLowBitsSet(
11483 N->getValueSizeInBits(0), PromBits),
11484 dl, N->getValueType(0)));
11486 assert(N->getOpcode() == ISD::SIGN_EXTEND &&
11487 "Invalid extension type");
11488 EVT ShiftAmountTy = getShiftAmountTy(N->getValueType(0), DAG.getDataLayout());
11490 DAG.getConstant(N->getValueSizeInBits(0) - PromBits, dl, ShiftAmountTy);
11491 return DAG.getNode(
11492 ISD::SRA, dl, N->getValueType(0),
11493 DAG.getNode(ISD::SHL, dl, N->getValueType(0), N->getOperand(0), ShiftCst),
11497 /// \brief Reduces the number of fp-to-int conversion when building a vector.
11499 /// If this vector is built out of floating to integer conversions,
11500 /// transform it to a vector built out of floating point values followed by a
11501 /// single floating to integer conversion of the vector.
11502 /// Namely (build_vector (fptosi $A), (fptosi $B), ...)
11503 /// becomes (fptosi (build_vector ($A, $B, ...)))
11504 SDValue PPCTargetLowering::
11505 combineElementTruncationToVectorTruncation(SDNode *N,
11506 DAGCombinerInfo &DCI) const {
11507 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
11508 "Should be called with a BUILD_VECTOR node");
11510 SelectionDAG &DAG = DCI.DAG;
11513 SDValue FirstInput = N->getOperand(0);
11514 assert(FirstInput.getOpcode() == PPCISD::MFVSR &&
11515 "The input operand must be an fp-to-int conversion.");
11517 // This combine happens after legalization so the fp_to_[su]i nodes are
11518 // already converted to PPCSISD nodes.
11519 unsigned FirstConversion = FirstInput.getOperand(0).getOpcode();
11520 if (FirstConversion == PPCISD::FCTIDZ ||
11521 FirstConversion == PPCISD::FCTIDUZ ||
11522 FirstConversion == PPCISD::FCTIWZ ||
11523 FirstConversion == PPCISD::FCTIWUZ) {
11524 bool IsSplat = true;
11525 bool Is32Bit = FirstConversion == PPCISD::FCTIWZ ||
11526 FirstConversion == PPCISD::FCTIWUZ;
11527 EVT SrcVT = FirstInput.getOperand(0).getValueType();
11528 SmallVector<SDValue, 4> Ops;
11529 EVT TargetVT = N->getValueType(0);
11530 for (int i = 0, e = N->getNumOperands(); i < e; ++i) {
11531 if (N->getOperand(i).getOpcode() != PPCISD::MFVSR)
11533 unsigned NextConversion = N->getOperand(i).getOperand(0).getOpcode();
11534 if (NextConversion != FirstConversion)
11536 if (N->getOperand(i) != FirstInput)
11540 // If this is a splat, we leave it as-is since there will be only a single
11541 // fp-to-int conversion followed by a splat of the integer. This is better
11542 // for 32-bit and smaller ints and neutral for 64-bit ints.
11546 // Now that we know we have the right type of node, get its operands
11547 for (int i = 0, e = N->getNumOperands(); i < e; ++i) {
11548 SDValue In = N->getOperand(i).getOperand(0);
11549 // For 32-bit values, we need to add an FP_ROUND node.
11552 Ops.push_back(DAG.getUNDEF(SrcVT));
11554 SDValue Trunc = DAG.getNode(ISD::FP_ROUND, dl,
11555 MVT::f32, In.getOperand(0),
11556 DAG.getIntPtrConstant(1, dl));
11557 Ops.push_back(Trunc);
11560 Ops.push_back(In.isUndef() ? DAG.getUNDEF(SrcVT) : In.getOperand(0));
11564 if (FirstConversion == PPCISD::FCTIDZ ||
11565 FirstConversion == PPCISD::FCTIWZ)
11566 Opcode = ISD::FP_TO_SINT;
11568 Opcode = ISD::FP_TO_UINT;
11570 EVT NewVT = TargetVT == MVT::v2i64 ? MVT::v2f64 : MVT::v4f32;
11571 SDValue BV = DAG.getBuildVector(NewVT, dl, Ops);
11572 return DAG.getNode(Opcode, dl, TargetVT, BV);
11577 /// \brief Reduce the number of loads when building a vector.
11579 /// Building a vector out of multiple loads can be converted to a load
11580 /// of the vector type if the loads are consecutive. If the loads are
11581 /// consecutive but in descending order, a shuffle is added at the end
11582 /// to reorder the vector.
11583 static SDValue combineBVOfConsecutiveLoads(SDNode *N, SelectionDAG &DAG) {
11584 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
11585 "Should be called with a BUILD_VECTOR node");
11588 bool InputsAreConsecutiveLoads = true;
11589 bool InputsAreReverseConsecutive = true;
11590 unsigned ElemSize = N->getValueType(0).getScalarSizeInBits() / 8;
11591 SDValue FirstInput = N->getOperand(0);
11592 bool IsRoundOfExtLoad = false;
11594 if (FirstInput.getOpcode() == ISD::FP_ROUND &&
11595 FirstInput.getOperand(0).getOpcode() == ISD::LOAD) {
11596 LoadSDNode *LD = dyn_cast<LoadSDNode>(FirstInput.getOperand(0));
11597 IsRoundOfExtLoad = LD->getExtensionType() == ISD::EXTLOAD;
11599 // Not a build vector of (possibly fp_rounded) loads.
11600 if (!IsRoundOfExtLoad && FirstInput.getOpcode() != ISD::LOAD)
11603 for (int i = 1, e = N->getNumOperands(); i < e; ++i) {
11604 // If any inputs are fp_round(extload), they all must be.
11605 if (IsRoundOfExtLoad && N->getOperand(i).getOpcode() != ISD::FP_ROUND)
11608 SDValue NextInput = IsRoundOfExtLoad ? N->getOperand(i).getOperand(0) :
11610 if (NextInput.getOpcode() != ISD::LOAD)
11613 SDValue PreviousInput =
11614 IsRoundOfExtLoad ? N->getOperand(i-1).getOperand(0) : N->getOperand(i-1);
11615 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(PreviousInput);
11616 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(NextInput);
11618 // If any inputs are fp_round(extload), they all must be.
11619 if (IsRoundOfExtLoad && LD2->getExtensionType() != ISD::EXTLOAD)
11622 if (!isConsecutiveLS(LD2, LD1, ElemSize, 1, DAG))
11623 InputsAreConsecutiveLoads = false;
11624 if (!isConsecutiveLS(LD1, LD2, ElemSize, 1, DAG))
11625 InputsAreReverseConsecutive = false;
11627 // Exit early if the loads are neither consecutive nor reverse consecutive.
11628 if (!InputsAreConsecutiveLoads && !InputsAreReverseConsecutive)
11632 assert(!(InputsAreConsecutiveLoads && InputsAreReverseConsecutive) &&
11633 "The loads cannot be both consecutive and reverse consecutive.");
11635 SDValue FirstLoadOp =
11636 IsRoundOfExtLoad ? FirstInput.getOperand(0) : FirstInput;
11637 SDValue LastLoadOp =
11638 IsRoundOfExtLoad ? N->getOperand(N->getNumOperands()-1).getOperand(0) :
11639 N->getOperand(N->getNumOperands()-1);
11641 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(FirstLoadOp);
11642 LoadSDNode *LDL = dyn_cast<LoadSDNode>(LastLoadOp);
11643 if (InputsAreConsecutiveLoads) {
11644 assert(LD1 && "Input needs to be a LoadSDNode.");
11645 return DAG.getLoad(N->getValueType(0), dl, LD1->getChain(),
11646 LD1->getBasePtr(), LD1->getPointerInfo(),
11647 LD1->getAlignment());
11649 if (InputsAreReverseConsecutive) {
11650 assert(LDL && "Input needs to be a LoadSDNode.");
11651 SDValue Load = DAG.getLoad(N->getValueType(0), dl, LDL->getChain(),
11652 LDL->getBasePtr(), LDL->getPointerInfo(),
11653 LDL->getAlignment());
11654 SmallVector<int, 16> Ops;
11655 for (int i = N->getNumOperands() - 1; i >= 0; i--)
11658 return DAG.getVectorShuffle(N->getValueType(0), dl, Load,
11659 DAG.getUNDEF(N->getValueType(0)), Ops);
11664 // This function adds the required vector_shuffle needed to get
11665 // the elements of the vector extract in the correct position
11666 // as specified by the CorrectElems encoding.
11667 static SDValue addShuffleForVecExtend(SDNode *N, SelectionDAG &DAG,
11668 SDValue Input, uint64_t Elems,
11669 uint64_t CorrectElems) {
11672 unsigned NumElems = Input.getValueType().getVectorNumElements();
11673 SmallVector<int, 16> ShuffleMask(NumElems, -1);
11675 // Knowing the element indices being extracted from the original
11676 // vector and the order in which they're being inserted, just put
11677 // them at element indices required for the instruction.
11678 for (unsigned i = 0; i < N->getNumOperands(); i++) {
11679 if (DAG.getDataLayout().isLittleEndian())
11680 ShuffleMask[CorrectElems & 0xF] = Elems & 0xF;
11682 ShuffleMask[(CorrectElems & 0xF0) >> 4] = (Elems & 0xF0) >> 4;
11683 CorrectElems = CorrectElems >> 8;
11684 Elems = Elems >> 8;
11688 DAG.getVectorShuffle(Input.getValueType(), dl, Input,
11689 DAG.getUNDEF(Input.getValueType()), ShuffleMask);
11691 EVT Ty = N->getValueType(0);
11692 SDValue BV = DAG.getNode(PPCISD::SExtVElems, dl, Ty, Shuffle);
11696 // Look for build vector patterns where input operands come from sign
11697 // extended vector_extract elements of specific indices. If the correct indices
11698 // aren't used, add a vector shuffle to fix up the indices and create a new
11699 // PPCISD:SExtVElems node which selects the vector sign extend instructions
11700 // during instruction selection.
11701 static SDValue combineBVOfVecSExt(SDNode *N, SelectionDAG &DAG) {
11702 // This array encodes the indices that the vector sign extend instructions
11703 // extract from when extending from one type to another for both BE and LE.
11704 // The right nibble of each byte corresponds to the LE incides.
11705 // and the left nibble of each byte corresponds to the BE incides.
11706 // For example: 0x3074B8FC byte->word
11707 // For LE: the allowed indices are: 0x0,0x4,0x8,0xC
11708 // For BE: the allowed indices are: 0x3,0x7,0xB,0xF
11709 // For example: 0x000070F8 byte->double word
11710 // For LE: the allowed indices are: 0x0,0x8
11711 // For BE: the allowed indices are: 0x7,0xF
11712 uint64_t TargetElems[] = {
11713 0x3074B8FC, // b->w
11714 0x000070F8, // b->d
11715 0x10325476, // h->w
11716 0x00003074, // h->d
11717 0x00001032, // w->d
11720 uint64_t Elems = 0;
11724 auto isSExtOfVecExtract = [&](SDValue Op) -> bool {
11727 if (Op.getOpcode() != ISD::SIGN_EXTEND)
11730 SDValue Extract = Op.getOperand(0);
11731 if (Extract.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
11734 ConstantSDNode *ExtOp = dyn_cast<ConstantSDNode>(Extract.getOperand(1));
11738 Index = ExtOp->getZExtValue();
11739 if (Input && Input != Extract.getOperand(0))
11743 Input = Extract.getOperand(0);
11745 Elems = Elems << 8;
11746 Index = DAG.getDataLayout().isLittleEndian() ? Index : Index << 4;
11752 // If the build vector operands aren't sign extended vector extracts,
11753 // of the same input vector, then return.
11754 for (unsigned i = 0; i < N->getNumOperands(); i++) {
11755 if (!isSExtOfVecExtract(N->getOperand(i))) {
11760 // If the vector extract indicies are not correct, add the appropriate
11762 int TgtElemArrayIdx;
11763 int InputSize = Input.getValueType().getScalarSizeInBits();
11764 int OutputSize = N->getValueType(0).getScalarSizeInBits();
11765 if (InputSize + OutputSize == 40)
11766 TgtElemArrayIdx = 0;
11767 else if (InputSize + OutputSize == 72)
11768 TgtElemArrayIdx = 1;
11769 else if (InputSize + OutputSize == 48)
11770 TgtElemArrayIdx = 2;
11771 else if (InputSize + OutputSize == 80)
11772 TgtElemArrayIdx = 3;
11773 else if (InputSize + OutputSize == 96)
11774 TgtElemArrayIdx = 4;
11778 uint64_t CorrectElems = TargetElems[TgtElemArrayIdx];
11779 CorrectElems = DAG.getDataLayout().isLittleEndian()
11780 ? CorrectElems & 0x0F0F0F0F0F0F0F0F
11781 : CorrectElems & 0xF0F0F0F0F0F0F0F0;
11782 if (Elems != CorrectElems) {
11783 return addShuffleForVecExtend(N, DAG, Input, Elems, CorrectElems);
11786 // Regular lowering will catch cases where a shuffle is not needed.
11790 SDValue PPCTargetLowering::DAGCombineBuildVector(SDNode *N,
11791 DAGCombinerInfo &DCI) const {
11792 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
11793 "Should be called with a BUILD_VECTOR node");
11795 SelectionDAG &DAG = DCI.DAG;
11798 if (!Subtarget.hasVSX())
11801 // The target independent DAG combiner will leave a build_vector of
11802 // float-to-int conversions intact. We can generate MUCH better code for
11803 // a float-to-int conversion of a vector of floats.
11804 SDValue FirstInput = N->getOperand(0);
11805 if (FirstInput.getOpcode() == PPCISD::MFVSR) {
11806 SDValue Reduced = combineElementTruncationToVectorTruncation(N, DCI);
11811 // If we're building a vector out of consecutive loads, just load that
11813 SDValue Reduced = combineBVOfConsecutiveLoads(N, DAG);
11817 // If we're building a vector out of extended elements from another vector
11818 // we have P9 vector integer extend instructions.
11819 if (Subtarget.hasP9Altivec()) {
11820 Reduced = combineBVOfVecSExt(N, DAG);
11826 if (N->getValueType(0) != MVT::v2f64)
11830 // (build_vector ([su]int_to_fp (extractelt 0)), [su]int_to_fp (extractelt 1))
11831 if (FirstInput.getOpcode() != ISD::SINT_TO_FP &&
11832 FirstInput.getOpcode() != ISD::UINT_TO_FP)
11834 if (N->getOperand(1).getOpcode() != ISD::SINT_TO_FP &&
11835 N->getOperand(1).getOpcode() != ISD::UINT_TO_FP)
11837 if (FirstInput.getOpcode() != N->getOperand(1).getOpcode())
11840 SDValue Ext1 = FirstInput.getOperand(0);
11841 SDValue Ext2 = N->getOperand(1).getOperand(0);
11842 if(Ext1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
11843 Ext2.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
11846 ConstantSDNode *Ext1Op = dyn_cast<ConstantSDNode>(Ext1.getOperand(1));
11847 ConstantSDNode *Ext2Op = dyn_cast<ConstantSDNode>(Ext2.getOperand(1));
11848 if (!Ext1Op || !Ext2Op)
11850 if (Ext1.getValueType() != MVT::i32 ||
11851 Ext2.getValueType() != MVT::i32)
11852 if (Ext1.getOperand(0) != Ext2.getOperand(0))
11855 int FirstElem = Ext1Op->getZExtValue();
11856 int SecondElem = Ext2Op->getZExtValue();
11858 if (FirstElem == 0 && SecondElem == 1)
11859 SubvecIdx = Subtarget.isLittleEndian() ? 1 : 0;
11860 else if (FirstElem == 2 && SecondElem == 3)
11861 SubvecIdx = Subtarget.isLittleEndian() ? 0 : 1;
11865 SDValue SrcVec = Ext1.getOperand(0);
11866 auto NodeType = (N->getOperand(1).getOpcode() == ISD::SINT_TO_FP) ?
11867 PPCISD::SINT_VEC_TO_FP : PPCISD::UINT_VEC_TO_FP;
11868 return DAG.getNode(NodeType, dl, MVT::v2f64,
11869 SrcVec, DAG.getIntPtrConstant(SubvecIdx, dl));
11872 SDValue PPCTargetLowering::combineFPToIntToFP(SDNode *N,
11873 DAGCombinerInfo &DCI) const {
11874 assert((N->getOpcode() == ISD::SINT_TO_FP ||
11875 N->getOpcode() == ISD::UINT_TO_FP) &&
11876 "Need an int -> FP conversion node here");
11878 if (useSoftFloat() || !Subtarget.has64BitSupport())
11881 SelectionDAG &DAG = DCI.DAG;
11885 SDValue FirstOperand(Op.getOperand(0));
11886 bool SubWordLoad = FirstOperand.getOpcode() == ISD::LOAD &&
11887 (FirstOperand.getValueType() == MVT::i8 ||
11888 FirstOperand.getValueType() == MVT::i16);
11889 if (Subtarget.hasP9Vector() && Subtarget.hasP9Altivec() && SubWordLoad) {
11890 bool Signed = N->getOpcode() == ISD::SINT_TO_FP;
11891 bool DstDouble = Op.getValueType() == MVT::f64;
11892 unsigned ConvOp = Signed ?
11893 (DstDouble ? PPCISD::FCFID : PPCISD::FCFIDS) :
11894 (DstDouble ? PPCISD::FCFIDU : PPCISD::FCFIDUS);
11895 SDValue WidthConst =
11896 DAG.getIntPtrConstant(FirstOperand.getValueType() == MVT::i8 ? 1 : 2,
11898 LoadSDNode *LDN = cast<LoadSDNode>(FirstOperand.getNode());
11899 SDValue Ops[] = { LDN->getChain(), LDN->getBasePtr(), WidthConst };
11900 SDValue Ld = DAG.getMemIntrinsicNode(PPCISD::LXSIZX, dl,
11901 DAG.getVTList(MVT::f64, MVT::Other),
11902 Ops, MVT::i8, LDN->getMemOperand());
11904 // For signed conversion, we need to sign-extend the value in the VSR
11906 SDValue ExtOps[] = { Ld, WidthConst };
11907 SDValue Ext = DAG.getNode(PPCISD::VEXTS, dl, MVT::f64, ExtOps);
11908 return DAG.getNode(ConvOp, dl, DstDouble ? MVT::f64 : MVT::f32, Ext);
11910 return DAG.getNode(ConvOp, dl, DstDouble ? MVT::f64 : MVT::f32, Ld);
11913 // Don't handle ppc_fp128 here or i1 conversions.
11914 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
11916 if (Op.getOperand(0).getValueType() == MVT::i1)
11919 // For i32 intermediate values, unfortunately, the conversion functions
11920 // leave the upper 32 bits of the value are undefined. Within the set of
11921 // scalar instructions, we have no method for zero- or sign-extending the
11922 // value. Thus, we cannot handle i32 intermediate values here.
11923 if (Op.getOperand(0).getValueType() == MVT::i32)
11926 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) &&
11927 "UINT_TO_FP is supported only with FPCVT");
11929 // If we have FCFIDS, then use it when converting to single-precision.
11930 // Otherwise, convert to double-precision and then round.
11931 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
11932 ? (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDUS
11934 : (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDU
11936 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
11940 // If we're converting from a float, to an int, and back to a float again,
11941 // then we don't need the store/load pair at all.
11942 if ((Op.getOperand(0).getOpcode() == ISD::FP_TO_UINT &&
11943 Subtarget.hasFPCVT()) ||
11944 (Op.getOperand(0).getOpcode() == ISD::FP_TO_SINT)) {
11945 SDValue Src = Op.getOperand(0).getOperand(0);
11946 if (Src.getValueType() == MVT::f32) {
11947 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
11948 DCI.AddToWorklist(Src.getNode());
11949 } else if (Src.getValueType() != MVT::f64) {
11950 // Make sure that we don't pick up a ppc_fp128 source value.
11955 Op.getOperand(0).getOpcode() == ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
11958 SDValue Tmp = DAG.getNode(FCTOp, dl, MVT::f64, Src);
11959 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Tmp);
11961 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT()) {
11962 FP = DAG.getNode(ISD::FP_ROUND, dl,
11963 MVT::f32, FP, DAG.getIntPtrConstant(0, dl));
11964 DCI.AddToWorklist(FP.getNode());
11973 // expandVSXLoadForLE - Convert VSX loads (which may be intrinsics for
11974 // builtins) into loads with swaps.
11975 SDValue PPCTargetLowering::expandVSXLoadForLE(SDNode *N,
11976 DAGCombinerInfo &DCI) const {
11977 SelectionDAG &DAG = DCI.DAG;
11981 MachineMemOperand *MMO;
11983 switch (N->getOpcode()) {
11985 llvm_unreachable("Unexpected opcode for little endian VSX load");
11987 LoadSDNode *LD = cast<LoadSDNode>(N);
11988 Chain = LD->getChain();
11989 Base = LD->getBasePtr();
11990 MMO = LD->getMemOperand();
11991 // If the MMO suggests this isn't a load of a full vector, leave
11992 // things alone. For a built-in, we have to make the change for
11993 // correctness, so if there is a size problem that will be a bug.
11994 if (MMO->getSize() < 16)
11998 case ISD::INTRINSIC_W_CHAIN: {
11999 MemIntrinsicSDNode *Intrin = cast<MemIntrinsicSDNode>(N);
12000 Chain = Intrin->getChain();
12001 // Similarly to the store case below, Intrin->getBasePtr() doesn't get
12002 // us what we want. Get operand 2 instead.
12003 Base = Intrin->getOperand(2);
12004 MMO = Intrin->getMemOperand();
12009 MVT VecTy = N->getValueType(0).getSimpleVT();
12011 // Do not expand to PPCISD::LXVD2X + PPCISD::XXSWAPD when the load is
12012 // aligned and the type is a vector with elements up to 4 bytes
12013 if (Subtarget.needsSwapsForVSXMemOps() && !(MMO->getAlignment()%16)
12014 && VecTy.getScalarSizeInBits() <= 32 ) {
12018 SDValue LoadOps[] = { Chain, Base };
12019 SDValue Load = DAG.getMemIntrinsicNode(PPCISD::LXVD2X, dl,
12020 DAG.getVTList(MVT::v2f64, MVT::Other),
12021 LoadOps, MVT::v2f64, MMO);
12023 DCI.AddToWorklist(Load.getNode());
12024 Chain = Load.getValue(1);
12025 SDValue Swap = DAG.getNode(
12026 PPCISD::XXSWAPD, dl, DAG.getVTList(MVT::v2f64, MVT::Other), Chain, Load);
12027 DCI.AddToWorklist(Swap.getNode());
12029 // Add a bitcast if the resulting load type doesn't match v2f64.
12030 if (VecTy != MVT::v2f64) {
12031 SDValue N = DAG.getNode(ISD::BITCAST, dl, VecTy, Swap);
12032 DCI.AddToWorklist(N.getNode());
12033 // Package {bitcast value, swap's chain} to match Load's shape.
12034 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(VecTy, MVT::Other),
12035 N, Swap.getValue(1));
12041 // expandVSXStoreForLE - Convert VSX stores (which may be intrinsics for
12042 // builtins) into stores with swaps.
12043 SDValue PPCTargetLowering::expandVSXStoreForLE(SDNode *N,
12044 DAGCombinerInfo &DCI) const {
12045 SelectionDAG &DAG = DCI.DAG;
12050 MachineMemOperand *MMO;
12052 switch (N->getOpcode()) {
12054 llvm_unreachable("Unexpected opcode for little endian VSX store");
12056 StoreSDNode *ST = cast<StoreSDNode>(N);
12057 Chain = ST->getChain();
12058 Base = ST->getBasePtr();
12059 MMO = ST->getMemOperand();
12061 // If the MMO suggests this isn't a store of a full vector, leave
12062 // things alone. For a built-in, we have to make the change for
12063 // correctness, so if there is a size problem that will be a bug.
12064 if (MMO->getSize() < 16)
12068 case ISD::INTRINSIC_VOID: {
12069 MemIntrinsicSDNode *Intrin = cast<MemIntrinsicSDNode>(N);
12070 Chain = Intrin->getChain();
12071 // Intrin->getBasePtr() oddly does not get what we want.
12072 Base = Intrin->getOperand(3);
12073 MMO = Intrin->getMemOperand();
12079 SDValue Src = N->getOperand(SrcOpnd);
12080 MVT VecTy = Src.getValueType().getSimpleVT();
12082 // Do not expand to PPCISD::XXSWAPD and PPCISD::STXVD2X when the load is
12083 // aligned and the type is a vector with elements up to 4 bytes
12084 if (Subtarget.needsSwapsForVSXMemOps() && !(MMO->getAlignment()%16)
12085 && VecTy.getScalarSizeInBits() <= 32 ) {
12089 // All stores are done as v2f64 and possible bit cast.
12090 if (VecTy != MVT::v2f64) {
12091 Src = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Src);
12092 DCI.AddToWorklist(Src.getNode());
12095 SDValue Swap = DAG.getNode(PPCISD::XXSWAPD, dl,
12096 DAG.getVTList(MVT::v2f64, MVT::Other), Chain, Src);
12097 DCI.AddToWorklist(Swap.getNode());
12098 Chain = Swap.getValue(1);
12099 SDValue StoreOps[] = { Chain, Swap, Base };
12100 SDValue Store = DAG.getMemIntrinsicNode(PPCISD::STXVD2X, dl,
12101 DAG.getVTList(MVT::Other),
12102 StoreOps, VecTy, MMO);
12103 DCI.AddToWorklist(Store.getNode());
12107 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
12108 DAGCombinerInfo &DCI) const {
12109 SelectionDAG &DAG = DCI.DAG;
12111 switch (N->getOpcode()) {
12114 return combineSHL(N, DCI);
12116 return combineSRA(N, DCI);
12118 return combineSRL(N, DCI);
12120 if (isNullConstant(N->getOperand(0))) // 0 << V -> 0.
12121 return N->getOperand(0);
12124 if (isNullConstant(N->getOperand(0))) // 0 >>u V -> 0.
12125 return N->getOperand(0);
12128 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
12129 if (C->isNullValue() || // 0 >>s V -> 0.
12130 C->isAllOnesValue()) // -1 >>s V -> -1.
12131 return N->getOperand(0);
12134 case ISD::SIGN_EXTEND:
12135 case ISD::ZERO_EXTEND:
12136 case ISD::ANY_EXTEND:
12137 return DAGCombineExtBoolTrunc(N, DCI);
12138 case ISD::TRUNCATE:
12140 case ISD::SELECT_CC:
12141 return DAGCombineTruncBoolExt(N, DCI);
12142 case ISD::SINT_TO_FP:
12143 case ISD::UINT_TO_FP:
12144 return combineFPToIntToFP(N, DCI);
12146 EVT Op1VT = N->getOperand(1).getValueType();
12147 bool ValidTypeForStoreFltAsInt = (Op1VT == MVT::i32) ||
12148 (Subtarget.hasP9Vector() && (Op1VT == MVT::i8 || Op1VT == MVT::i16));
12150 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
12151 if (Subtarget.hasSTFIWX() && !cast<StoreSDNode>(N)->isTruncatingStore() &&
12152 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
12153 ValidTypeForStoreFltAsInt &&
12154 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
12155 SDValue Val = N->getOperand(1).getOperand(0);
12156 if (Val.getValueType() == MVT::f32) {
12157 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
12158 DCI.AddToWorklist(Val.getNode());
12160 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
12161 DCI.AddToWorklist(Val.getNode());
12163 if (Op1VT == MVT::i32) {
12165 N->getOperand(0), Val, N->getOperand(2),
12166 DAG.getValueType(N->getOperand(1).getValueType())
12169 Val = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
12170 DAG.getVTList(MVT::Other), Ops,
12171 cast<StoreSDNode>(N)->getMemoryVT(),
12172 cast<StoreSDNode>(N)->getMemOperand());
12174 unsigned WidthInBytes =
12175 N->getOperand(1).getValueType() == MVT::i8 ? 1 : 2;
12176 SDValue WidthConst = DAG.getIntPtrConstant(WidthInBytes, dl, false);
12179 N->getOperand(0), Val, N->getOperand(2), WidthConst,
12180 DAG.getValueType(N->getOperand(1).getValueType())
12182 Val = DAG.getMemIntrinsicNode(PPCISD::STXSIX, dl,
12183 DAG.getVTList(MVT::Other), Ops,
12184 cast<StoreSDNode>(N)->getMemoryVT(),
12185 cast<StoreSDNode>(N)->getMemOperand());
12188 DCI.AddToWorklist(Val.getNode());
12192 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
12193 if (cast<StoreSDNode>(N)->isUnindexed() &&
12194 N->getOperand(1).getOpcode() == ISD::BSWAP &&
12195 N->getOperand(1).getNode()->hasOneUse() &&
12196 (N->getOperand(1).getValueType() == MVT::i32 ||
12197 N->getOperand(1).getValueType() == MVT::i16 ||
12198 (Subtarget.hasLDBRX() && Subtarget.isPPC64() &&
12199 N->getOperand(1).getValueType() == MVT::i64))) {
12200 SDValue BSwapOp = N->getOperand(1).getOperand(0);
12201 // Do an any-extend to 32-bits if this is a half-word input.
12202 if (BSwapOp.getValueType() == MVT::i16)
12203 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
12205 // If the type of BSWAP operand is wider than stored memory width
12206 // it need to be shifted to the right side before STBRX.
12207 EVT mVT = cast<StoreSDNode>(N)->getMemoryVT();
12208 if (Op1VT.bitsGT(mVT)) {
12209 int Shift = Op1VT.getSizeInBits() - mVT.getSizeInBits();
12210 BSwapOp = DAG.getNode(ISD::SRL, dl, Op1VT, BSwapOp,
12211 DAG.getConstant(Shift, dl, MVT::i32));
12212 // Need to truncate if this is a bswap of i64 stored as i32/i16.
12213 if (Op1VT == MVT::i64)
12214 BSwapOp = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BSwapOp);
12218 N->getOperand(0), BSwapOp, N->getOperand(2), DAG.getValueType(mVT)
12221 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
12222 Ops, cast<StoreSDNode>(N)->getMemoryVT(),
12223 cast<StoreSDNode>(N)->getMemOperand());
12226 // STORE Constant:i32<0> -> STORE<trunc to i32> Constant:i64<0>
12227 // So it can increase the chance of CSE constant construction.
12228 EVT VT = N->getOperand(1).getValueType();
12229 if (Subtarget.isPPC64() && !DCI.isBeforeLegalize() &&
12230 isa<ConstantSDNode>(N->getOperand(1)) && VT == MVT::i32) {
12231 // Need to sign-extended to 64-bits to handle negative values.
12232 EVT MemVT = cast<StoreSDNode>(N)->getMemoryVT();
12233 uint64_t Val64 = SignExtend64(N->getConstantOperandVal(1),
12234 MemVT.getSizeInBits());
12235 SDValue Const64 = DAG.getConstant(Val64, dl, MVT::i64);
12237 // DAG.getTruncStore() can't be used here because it doesn't accept
12238 // the general (base + offset) addressing mode.
12239 // So we use UpdateNodeOperands and setTruncatingStore instead.
12240 DAG.UpdateNodeOperands(N, N->getOperand(0), Const64, N->getOperand(2),
12242 cast<StoreSDNode>(N)->setTruncatingStore(true);
12243 return SDValue(N, 0);
12246 // For little endian, VSX stores require generating xxswapd/lxvd2x.
12247 // Not needed on ISA 3.0 based CPUs since we have a non-permuting store.
12248 if (VT.isSimple()) {
12249 MVT StoreVT = VT.getSimpleVT();
12250 if (Subtarget.needsSwapsForVSXMemOps() &&
12251 (StoreVT == MVT::v2f64 || StoreVT == MVT::v2i64 ||
12252 StoreVT == MVT::v4f32 || StoreVT == MVT::v4i32))
12253 return expandVSXStoreForLE(N, DCI);
12258 LoadSDNode *LD = cast<LoadSDNode>(N);
12259 EVT VT = LD->getValueType(0);
12261 // For little endian, VSX loads require generating lxvd2x/xxswapd.
12262 // Not needed on ISA 3.0 based CPUs since we have a non-permuting load.
12263 if (VT.isSimple()) {
12264 MVT LoadVT = VT.getSimpleVT();
12265 if (Subtarget.needsSwapsForVSXMemOps() &&
12266 (LoadVT == MVT::v2f64 || LoadVT == MVT::v2i64 ||
12267 LoadVT == MVT::v4f32 || LoadVT == MVT::v4i32))
12268 return expandVSXLoadForLE(N, DCI);
12271 // We sometimes end up with a 64-bit integer load, from which we extract
12272 // two single-precision floating-point numbers. This happens with
12273 // std::complex<float>, and other similar structures, because of the way we
12274 // canonicalize structure copies. However, if we lack direct moves,
12275 // then the final bitcasts from the extracted integer values to the
12276 // floating-point numbers turn into store/load pairs. Even with direct moves,
12277 // just loading the two floating-point numbers is likely better.
12278 auto ReplaceTwoFloatLoad = [&]() {
12279 if (VT != MVT::i64)
12282 if (LD->getExtensionType() != ISD::NON_EXTLOAD ||
12286 // We're looking for a sequence like this:
12287 // t13: i64,ch = load<LD8[%ref.tmp]> t0, t6, undef:i64
12288 // t16: i64 = srl t13, Constant:i32<32>
12289 // t17: i32 = truncate t16
12290 // t18: f32 = bitcast t17
12291 // t19: i32 = truncate t13
12292 // t20: f32 = bitcast t19
12294 if (!LD->hasNUsesOfValue(2, 0))
12297 auto UI = LD->use_begin();
12298 while (UI.getUse().getResNo() != 0) ++UI;
12299 SDNode *Trunc = *UI++;
12300 while (UI.getUse().getResNo() != 0) ++UI;
12301 SDNode *RightShift = *UI;
12302 if (Trunc->getOpcode() != ISD::TRUNCATE)
12303 std::swap(Trunc, RightShift);
12305 if (Trunc->getOpcode() != ISD::TRUNCATE ||
12306 Trunc->getValueType(0) != MVT::i32 ||
12307 !Trunc->hasOneUse())
12309 if (RightShift->getOpcode() != ISD::SRL ||
12310 !isa<ConstantSDNode>(RightShift->getOperand(1)) ||
12311 RightShift->getConstantOperandVal(1) != 32 ||
12312 !RightShift->hasOneUse())
12315 SDNode *Trunc2 = *RightShift->use_begin();
12316 if (Trunc2->getOpcode() != ISD::TRUNCATE ||
12317 Trunc2->getValueType(0) != MVT::i32 ||
12318 !Trunc2->hasOneUse())
12321 SDNode *Bitcast = *Trunc->use_begin();
12322 SDNode *Bitcast2 = *Trunc2->use_begin();
12324 if (Bitcast->getOpcode() != ISD::BITCAST ||
12325 Bitcast->getValueType(0) != MVT::f32)
12327 if (Bitcast2->getOpcode() != ISD::BITCAST ||
12328 Bitcast2->getValueType(0) != MVT::f32)
12331 if (Subtarget.isLittleEndian())
12332 std::swap(Bitcast, Bitcast2);
12334 // Bitcast has the second float (in memory-layout order) and Bitcast2
12335 // has the first one.
12337 SDValue BasePtr = LD->getBasePtr();
12338 if (LD->isIndexed()) {
12339 assert(LD->getAddressingMode() == ISD::PRE_INC &&
12340 "Non-pre-inc AM on PPC?");
12342 DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
12347 LD->getMemOperand()->getFlags() & ~MachineMemOperand::MOVolatile;
12348 SDValue FloatLoad = DAG.getLoad(MVT::f32, dl, LD->getChain(), BasePtr,
12349 LD->getPointerInfo(), LD->getAlignment(),
12350 MMOFlags, LD->getAAInfo());
12352 DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
12353 BasePtr, DAG.getIntPtrConstant(4, dl));
12354 SDValue FloatLoad2 = DAG.getLoad(
12355 MVT::f32, dl, SDValue(FloatLoad.getNode(), 1), AddPtr,
12356 LD->getPointerInfo().getWithOffset(4),
12357 MinAlign(LD->getAlignment(), 4), MMOFlags, LD->getAAInfo());
12359 if (LD->isIndexed()) {
12360 // Note that DAGCombine should re-form any pre-increment load(s) from
12361 // what is produced here if that makes sense.
12362 DAG.ReplaceAllUsesOfValueWith(SDValue(LD, 1), BasePtr);
12365 DCI.CombineTo(Bitcast2, FloatLoad);
12366 DCI.CombineTo(Bitcast, FloatLoad2);
12368 DAG.ReplaceAllUsesOfValueWith(SDValue(LD, LD->isIndexed() ? 2 : 1),
12369 SDValue(FloatLoad2.getNode(), 1));
12373 if (ReplaceTwoFloatLoad())
12374 return SDValue(N, 0);
12376 EVT MemVT = LD->getMemoryVT();
12377 Type *Ty = MemVT.getTypeForEVT(*DAG.getContext());
12378 unsigned ABIAlignment = DAG.getDataLayout().getABITypeAlignment(Ty);
12379 Type *STy = MemVT.getScalarType().getTypeForEVT(*DAG.getContext());
12380 unsigned ScalarABIAlignment = DAG.getDataLayout().getABITypeAlignment(STy);
12381 if (LD->isUnindexed() && VT.isVector() &&
12382 ((Subtarget.hasAltivec() && ISD::isNON_EXTLoad(N) &&
12383 // P8 and later hardware should just use LOAD.
12384 !Subtarget.hasP8Vector() && (VT == MVT::v16i8 || VT == MVT::v8i16 ||
12385 VT == MVT::v4i32 || VT == MVT::v4f32)) ||
12386 (Subtarget.hasQPX() && (VT == MVT::v4f64 || VT == MVT::v4f32) &&
12387 LD->getAlignment() >= ScalarABIAlignment)) &&
12388 LD->getAlignment() < ABIAlignment) {
12389 // This is a type-legal unaligned Altivec or QPX load.
12390 SDValue Chain = LD->getChain();
12391 SDValue Ptr = LD->getBasePtr();
12392 bool isLittleEndian = Subtarget.isLittleEndian();
12394 // This implements the loading of unaligned vectors as described in
12395 // the venerable Apple Velocity Engine overview. Specifically:
12396 // https://developer.apple.com/hardwaredrivers/ve/alignment.html
12397 // https://developer.apple.com/hardwaredrivers/ve/code_optimization.html
12399 // The general idea is to expand a sequence of one or more unaligned
12400 // loads into an alignment-based permutation-control instruction (lvsl
12401 // or lvsr), a series of regular vector loads (which always truncate
12402 // their input address to an aligned address), and a series of
12403 // permutations. The results of these permutations are the requested
12404 // loaded values. The trick is that the last "extra" load is not taken
12405 // from the address you might suspect (sizeof(vector) bytes after the
12406 // last requested load), but rather sizeof(vector) - 1 bytes after the
12407 // last requested vector. The point of this is to avoid a page fault if
12408 // the base address happened to be aligned. This works because if the
12409 // base address is aligned, then adding less than a full vector length
12410 // will cause the last vector in the sequence to be (re)loaded.
12411 // Otherwise, the next vector will be fetched as you might suspect was
12414 // We might be able to reuse the permutation generation from
12415 // a different base address offset from this one by an aligned amount.
12416 // The INTRINSIC_WO_CHAIN DAG combine will attempt to perform this
12417 // optimization later.
12418 Intrinsic::ID Intr, IntrLD, IntrPerm;
12419 MVT PermCntlTy, PermTy, LDTy;
12420 if (Subtarget.hasAltivec()) {
12421 Intr = isLittleEndian ? Intrinsic::ppc_altivec_lvsr :
12422 Intrinsic::ppc_altivec_lvsl;
12423 IntrLD = Intrinsic::ppc_altivec_lvx;
12424 IntrPerm = Intrinsic::ppc_altivec_vperm;
12425 PermCntlTy = MVT::v16i8;
12426 PermTy = MVT::v4i32;
12429 Intr = MemVT == MVT::v4f64 ? Intrinsic::ppc_qpx_qvlpcld :
12430 Intrinsic::ppc_qpx_qvlpcls;
12431 IntrLD = MemVT == MVT::v4f64 ? Intrinsic::ppc_qpx_qvlfd :
12432 Intrinsic::ppc_qpx_qvlfs;
12433 IntrPerm = Intrinsic::ppc_qpx_qvfperm;
12434 PermCntlTy = MVT::v4f64;
12435 PermTy = MVT::v4f64;
12436 LDTy = MemVT.getSimpleVT();
12439 SDValue PermCntl = BuildIntrinsicOp(Intr, Ptr, DAG, dl, PermCntlTy);
12441 // Create the new MMO for the new base load. It is like the original MMO,
12442 // but represents an area in memory almost twice the vector size centered
12443 // on the original address. If the address is unaligned, we might start
12444 // reading up to (sizeof(vector)-1) bytes below the address of the
12445 // original unaligned load.
12446 MachineFunction &MF = DAG.getMachineFunction();
12447 MachineMemOperand *BaseMMO =
12448 MF.getMachineMemOperand(LD->getMemOperand(),
12449 -(long)MemVT.getStoreSize()+1,
12450 2*MemVT.getStoreSize()-1);
12452 // Create the new base load.
12454 DAG.getTargetConstant(IntrLD, dl, getPointerTy(MF.getDataLayout()));
12455 SDValue BaseLoadOps[] = { Chain, LDXIntID, Ptr };
12457 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, dl,
12458 DAG.getVTList(PermTy, MVT::Other),
12459 BaseLoadOps, LDTy, BaseMMO);
12461 // Note that the value of IncOffset (which is provided to the next
12462 // load's pointer info offset value, and thus used to calculate the
12463 // alignment), and the value of IncValue (which is actually used to
12464 // increment the pointer value) are different! This is because we
12465 // require the next load to appear to be aligned, even though it
12466 // is actually offset from the base pointer by a lesser amount.
12467 int IncOffset = VT.getSizeInBits() / 8;
12468 int IncValue = IncOffset;
12470 // Walk (both up and down) the chain looking for another load at the real
12471 // (aligned) offset (the alignment of the other load does not matter in
12472 // this case). If found, then do not use the offset reduction trick, as
12473 // that will prevent the loads from being later combined (as they would
12474 // otherwise be duplicates).
12475 if (!findConsecutiveLoad(LD, DAG))
12478 SDValue Increment =
12479 DAG.getConstant(IncValue, dl, getPointerTy(MF.getDataLayout()));
12480 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
12482 MachineMemOperand *ExtraMMO =
12483 MF.getMachineMemOperand(LD->getMemOperand(),
12484 1, 2*MemVT.getStoreSize()-1);
12485 SDValue ExtraLoadOps[] = { Chain, LDXIntID, Ptr };
12486 SDValue ExtraLoad =
12487 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, dl,
12488 DAG.getVTList(PermTy, MVT::Other),
12489 ExtraLoadOps, LDTy, ExtraMMO);
12491 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
12492 BaseLoad.getValue(1), ExtraLoad.getValue(1));
12494 // Because vperm has a big-endian bias, we must reverse the order
12495 // of the input vectors and complement the permute control vector
12496 // when generating little endian code. We have already handled the
12497 // latter by using lvsr instead of lvsl, so just reverse BaseLoad
12498 // and ExtraLoad here.
12500 if (isLittleEndian)
12501 Perm = BuildIntrinsicOp(IntrPerm,
12502 ExtraLoad, BaseLoad, PermCntl, DAG, dl);
12504 Perm = BuildIntrinsicOp(IntrPerm,
12505 BaseLoad, ExtraLoad, PermCntl, DAG, dl);
12508 Perm = Subtarget.hasAltivec() ?
12509 DAG.getNode(ISD::BITCAST, dl, VT, Perm) :
12510 DAG.getNode(ISD::FP_ROUND, dl, VT, Perm, // QPX
12511 DAG.getTargetConstant(1, dl, MVT::i64));
12512 // second argument is 1 because this rounding
12513 // is always exact.
12515 // The output of the permutation is our loaded result, the TokenFactor is
12517 DCI.CombineTo(N, Perm, TF);
12518 return SDValue(N, 0);
12522 case ISD::INTRINSIC_WO_CHAIN: {
12523 bool isLittleEndian = Subtarget.isLittleEndian();
12524 unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
12525 Intrinsic::ID Intr = (isLittleEndian ? Intrinsic::ppc_altivec_lvsr
12526 : Intrinsic::ppc_altivec_lvsl);
12527 if ((IID == Intr ||
12528 IID == Intrinsic::ppc_qpx_qvlpcld ||
12529 IID == Intrinsic::ppc_qpx_qvlpcls) &&
12530 N->getOperand(1)->getOpcode() == ISD::ADD) {
12531 SDValue Add = N->getOperand(1);
12533 int Bits = IID == Intrinsic::ppc_qpx_qvlpcld ?
12534 5 /* 32 byte alignment */ : 4 /* 16 byte alignment */;
12536 if (DAG.MaskedValueIsZero(Add->getOperand(1),
12537 APInt::getAllOnesValue(Bits /* alignment */)
12538 .zext(Add.getScalarValueSizeInBits()))) {
12539 SDNode *BasePtr = Add->getOperand(0).getNode();
12540 for (SDNode::use_iterator UI = BasePtr->use_begin(),
12541 UE = BasePtr->use_end();
12543 if (UI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
12544 cast<ConstantSDNode>(UI->getOperand(0))->getZExtValue() == IID) {
12545 // We've found another LVSL/LVSR, and this address is an aligned
12546 // multiple of that one. The results will be the same, so use the
12547 // one we've just found instead.
12549 return SDValue(*UI, 0);
12554 if (isa<ConstantSDNode>(Add->getOperand(1))) {
12555 SDNode *BasePtr = Add->getOperand(0).getNode();
12556 for (SDNode::use_iterator UI = BasePtr->use_begin(),
12557 UE = BasePtr->use_end(); UI != UE; ++UI) {
12558 if (UI->getOpcode() == ISD::ADD &&
12559 isa<ConstantSDNode>(UI->getOperand(1)) &&
12560 (cast<ConstantSDNode>(Add->getOperand(1))->getZExtValue() -
12561 cast<ConstantSDNode>(UI->getOperand(1))->getZExtValue()) %
12562 (1ULL << Bits) == 0) {
12563 SDNode *OtherAdd = *UI;
12564 for (SDNode::use_iterator VI = OtherAdd->use_begin(),
12565 VE = OtherAdd->use_end(); VI != VE; ++VI) {
12566 if (VI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
12567 cast<ConstantSDNode>(VI->getOperand(0))->getZExtValue() == IID) {
12568 return SDValue(*VI, 0);
12578 case ISD::INTRINSIC_W_CHAIN:
12579 // For little endian, VSX loads require generating lxvd2x/xxswapd.
12580 // Not needed on ISA 3.0 based CPUs since we have a non-permuting load.
12581 if (Subtarget.needsSwapsForVSXMemOps()) {
12582 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
12585 case Intrinsic::ppc_vsx_lxvw4x:
12586 case Intrinsic::ppc_vsx_lxvd2x:
12587 return expandVSXLoadForLE(N, DCI);
12591 case ISD::INTRINSIC_VOID:
12592 // For little endian, VSX stores require generating xxswapd/stxvd2x.
12593 // Not needed on ISA 3.0 based CPUs since we have a non-permuting store.
12594 if (Subtarget.needsSwapsForVSXMemOps()) {
12595 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
12598 case Intrinsic::ppc_vsx_stxvw4x:
12599 case Intrinsic::ppc_vsx_stxvd2x:
12600 return expandVSXStoreForLE(N, DCI);
12605 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
12606 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
12607 N->getOperand(0).hasOneUse() &&
12608 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 ||
12609 (Subtarget.hasLDBRX() && Subtarget.isPPC64() &&
12610 N->getValueType(0) == MVT::i64))) {
12611 SDValue Load = N->getOperand(0);
12612 LoadSDNode *LD = cast<LoadSDNode>(Load);
12613 // Create the byte-swapping load.
12615 LD->getChain(), // Chain
12616 LD->getBasePtr(), // Ptr
12617 DAG.getValueType(N->getValueType(0)) // VT
12620 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
12621 DAG.getVTList(N->getValueType(0) == MVT::i64 ?
12622 MVT::i64 : MVT::i32, MVT::Other),
12623 Ops, LD->getMemoryVT(), LD->getMemOperand());
12625 // If this is an i16 load, insert the truncate.
12626 SDValue ResVal = BSLoad;
12627 if (N->getValueType(0) == MVT::i16)
12628 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
12630 // First, combine the bswap away. This makes the value produced by the
12632 DCI.CombineTo(N, ResVal);
12634 // Next, combine the load away, we give it a bogus result value but a real
12635 // chain result. The result value is dead because the bswap is dead.
12636 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
12638 // Return N so it doesn't get rechecked!
12639 return SDValue(N, 0);
12643 // If a VCMPo node already exists with exactly the same operands as this
12644 // node, use its result instead of this node (VCMPo computes both a CR6 and
12645 // a normal output).
12647 if (!N->getOperand(0).hasOneUse() &&
12648 !N->getOperand(1).hasOneUse() &&
12649 !N->getOperand(2).hasOneUse()) {
12651 // Scan all of the users of the LHS, looking for VCMPo's that match.
12652 SDNode *VCMPoNode = nullptr;
12654 SDNode *LHSN = N->getOperand(0).getNode();
12655 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
12657 if (UI->getOpcode() == PPCISD::VCMPo &&
12658 UI->getOperand(1) == N->getOperand(1) &&
12659 UI->getOperand(2) == N->getOperand(2) &&
12660 UI->getOperand(0) == N->getOperand(0)) {
12665 // If there is no VCMPo node, or if the flag value has a single use, don't
12667 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
12670 // Look at the (necessarily single) use of the flag value. If it has a
12671 // chain, this transformation is more complex. Note that multiple things
12672 // could use the value result, which we should ignore.
12673 SDNode *FlagUser = nullptr;
12674 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
12675 FlagUser == nullptr; ++UI) {
12676 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
12677 SDNode *User = *UI;
12678 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
12679 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
12686 // If the user is a MFOCRF instruction, we know this is safe.
12687 // Otherwise we give up for right now.
12688 if (FlagUser->getOpcode() == PPCISD::MFOCRF)
12689 return SDValue(VCMPoNode, 0);
12692 case ISD::BRCOND: {
12693 SDValue Cond = N->getOperand(1);
12694 SDValue Target = N->getOperand(2);
12696 if (Cond.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
12697 cast<ConstantSDNode>(Cond.getOperand(1))->getZExtValue() ==
12698 Intrinsic::ppc_is_decremented_ctr_nonzero) {
12700 // We now need to make the intrinsic dead (it cannot be instruction
12702 DAG.ReplaceAllUsesOfValueWith(Cond.getValue(1), Cond.getOperand(0));
12703 assert(Cond.getNode()->hasOneUse() &&
12704 "Counter decrement has more than one use");
12706 return DAG.getNode(PPCISD::BDNZ, dl, MVT::Other,
12707 N->getOperand(0), Target);
12712 // If this is a branch on an altivec predicate comparison, lower this so
12713 // that we don't have to do a MFOCRF: instead, branch directly on CR6. This
12714 // lowering is done pre-legalize, because the legalizer lowers the predicate
12715 // compare down to code that is difficult to reassemble.
12716 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
12717 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
12719 // Sometimes the promoted value of the intrinsic is ANDed by some non-zero
12720 // value. If so, pass-through the AND to get to the intrinsic.
12721 if (LHS.getOpcode() == ISD::AND &&
12722 LHS.getOperand(0).getOpcode() == ISD::INTRINSIC_W_CHAIN &&
12723 cast<ConstantSDNode>(LHS.getOperand(0).getOperand(1))->getZExtValue() ==
12724 Intrinsic::ppc_is_decremented_ctr_nonzero &&
12725 isa<ConstantSDNode>(LHS.getOperand(1)) &&
12726 !isNullConstant(LHS.getOperand(1)))
12727 LHS = LHS.getOperand(0);
12729 if (LHS.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
12730 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() ==
12731 Intrinsic::ppc_is_decremented_ctr_nonzero &&
12732 isa<ConstantSDNode>(RHS)) {
12733 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
12734 "Counter decrement comparison is not EQ or NE");
12736 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
12737 bool isBDNZ = (CC == ISD::SETEQ && Val) ||
12738 (CC == ISD::SETNE && !Val);
12740 // We now need to make the intrinsic dead (it cannot be instruction
12742 DAG.ReplaceAllUsesOfValueWith(LHS.getValue(1), LHS.getOperand(0));
12743 assert(LHS.getNode()->hasOneUse() &&
12744 "Counter decrement has more than one use");
12746 return DAG.getNode(isBDNZ ? PPCISD::BDNZ : PPCISD::BDZ, dl, MVT::Other,
12747 N->getOperand(0), N->getOperand(4));
12753 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
12754 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
12755 getVectorCompareInfo(LHS, CompareOpc, isDot, Subtarget)) {
12756 assert(isDot && "Can't compare against a vector result!");
12758 // If this is a comparison against something other than 0/1, then we know
12759 // that the condition is never/always true.
12760 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
12761 if (Val != 0 && Val != 1) {
12762 if (CC == ISD::SETEQ) // Cond never true, remove branch.
12763 return N->getOperand(0);
12764 // Always !=, turn it into an unconditional branch.
12765 return DAG.getNode(ISD::BR, dl, MVT::Other,
12766 N->getOperand(0), N->getOperand(4));
12769 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
12771 // Create the PPCISD altivec 'dot' comparison node.
12773 LHS.getOperand(2), // LHS of compare
12774 LHS.getOperand(3), // RHS of compare
12775 DAG.getConstant(CompareOpc, dl, MVT::i32)
12777 EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue };
12778 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
12780 // Unpack the result based on how the target uses it.
12781 PPC::Predicate CompOpc;
12782 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
12783 default: // Can't happen, don't crash on invalid number though.
12784 case 0: // Branch on the value of the EQ bit of CR6.
12785 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
12787 case 1: // Branch on the inverted value of the EQ bit of CR6.
12788 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
12790 case 2: // Branch on the value of the LT bit of CR6.
12791 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
12793 case 3: // Branch on the inverted value of the LT bit of CR6.
12794 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
12798 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
12799 DAG.getConstant(CompOpc, dl, MVT::i32),
12800 DAG.getRegister(PPC::CR6, MVT::i32),
12801 N->getOperand(4), CompNode.getValue(1));
12805 case ISD::BUILD_VECTOR:
12806 return DAGCombineBuildVector(N, DCI);
12813 PPCTargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
12815 std::vector<SDNode *> *Created) const {
12816 // fold (sdiv X, pow2)
12817 EVT VT = N->getValueType(0);
12818 if (VT == MVT::i64 && !Subtarget.isPPC64())
12820 if ((VT != MVT::i32 && VT != MVT::i64) ||
12821 !(Divisor.isPowerOf2() || (-Divisor).isPowerOf2()))
12825 SDValue N0 = N->getOperand(0);
12827 bool IsNegPow2 = (-Divisor).isPowerOf2();
12828 unsigned Lg2 = (IsNegPow2 ? -Divisor : Divisor).countTrailingZeros();
12829 SDValue ShiftAmt = DAG.getConstant(Lg2, DL, VT);
12831 SDValue Op = DAG.getNode(PPCISD::SRA_ADDZE, DL, VT, N0, ShiftAmt);
12833 Created->push_back(Op.getNode());
12836 Op = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), Op);
12838 Created->push_back(Op.getNode());
12844 //===----------------------------------------------------------------------===//
12845 // Inline Assembly Support
12846 //===----------------------------------------------------------------------===//
12848 void PPCTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
12850 const APInt &DemandedElts,
12851 const SelectionDAG &DAG,
12852 unsigned Depth) const {
12854 switch (Op.getOpcode()) {
12856 case PPCISD::LBRX: {
12857 // lhbrx is known to have the top bits cleared out.
12858 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
12859 Known.Zero = 0xFFFF0000;
12862 case ISD::INTRINSIC_WO_CHAIN: {
12863 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
12865 case Intrinsic::ppc_altivec_vcmpbfp_p:
12866 case Intrinsic::ppc_altivec_vcmpeqfp_p:
12867 case Intrinsic::ppc_altivec_vcmpequb_p:
12868 case Intrinsic::ppc_altivec_vcmpequh_p:
12869 case Intrinsic::ppc_altivec_vcmpequw_p:
12870 case Intrinsic::ppc_altivec_vcmpequd_p:
12871 case Intrinsic::ppc_altivec_vcmpgefp_p:
12872 case Intrinsic::ppc_altivec_vcmpgtfp_p:
12873 case Intrinsic::ppc_altivec_vcmpgtsb_p:
12874 case Intrinsic::ppc_altivec_vcmpgtsh_p:
12875 case Intrinsic::ppc_altivec_vcmpgtsw_p:
12876 case Intrinsic::ppc_altivec_vcmpgtsd_p:
12877 case Intrinsic::ppc_altivec_vcmpgtub_p:
12878 case Intrinsic::ppc_altivec_vcmpgtuh_p:
12879 case Intrinsic::ppc_altivec_vcmpgtuw_p:
12880 case Intrinsic::ppc_altivec_vcmpgtud_p:
12881 Known.Zero = ~1U; // All bits but the low one are known to be zero.
12888 unsigned PPCTargetLowering::getPrefLoopAlignment(MachineLoop *ML) const {
12889 switch (Subtarget.getDarwinDirective()) {
12892 case PPC::DIR_PWR4:
12893 case PPC::DIR_PWR5:
12894 case PPC::DIR_PWR5X:
12895 case PPC::DIR_PWR6:
12896 case PPC::DIR_PWR6X:
12897 case PPC::DIR_PWR7:
12898 case PPC::DIR_PWR8:
12899 case PPC::DIR_PWR9: {
12903 const PPCInstrInfo *TII = Subtarget.getInstrInfo();
12905 // For small loops (between 5 and 8 instructions), align to a 32-byte
12906 // boundary so that the entire loop fits in one instruction-cache line.
12907 uint64_t LoopSize = 0;
12908 for (auto I = ML->block_begin(), IE = ML->block_end(); I != IE; ++I)
12909 for (auto J = (*I)->begin(), JE = (*I)->end(); J != JE; ++J) {
12910 LoopSize += TII->getInstSizeInBytes(*J);
12915 if (LoopSize > 16 && LoopSize <= 32)
12922 return TargetLowering::getPrefLoopAlignment(ML);
12925 /// getConstraintType - Given a constraint, return the type of
12926 /// constraint it is for this target.
12927 PPCTargetLowering::ConstraintType
12928 PPCTargetLowering::getConstraintType(StringRef Constraint) const {
12929 if (Constraint.size() == 1) {
12930 switch (Constraint[0]) {
12938 return C_RegisterClass;
12940 // FIXME: While Z does indicate a memory constraint, it specifically
12941 // indicates an r+r address (used in conjunction with the 'y' modifier
12942 // in the replacement string). Currently, we're forcing the base
12943 // register to be r0 in the asm printer (which is interpreted as zero)
12944 // and forming the complete address in the second register. This is
12948 } else if (Constraint == "wc") { // individual CR bits.
12949 return C_RegisterClass;
12950 } else if (Constraint == "wa" || Constraint == "wd" ||
12951 Constraint == "wf" || Constraint == "ws") {
12952 return C_RegisterClass; // VSX registers.
12954 return TargetLowering::getConstraintType(Constraint);
12957 /// Examine constraint type and operand type and determine a weight value.
12958 /// This object must already have been set up with the operand type
12959 /// and the current alternative constraint selected.
12960 TargetLowering::ConstraintWeight
12961 PPCTargetLowering::getSingleConstraintMatchWeight(
12962 AsmOperandInfo &info, const char *constraint) const {
12963 ConstraintWeight weight = CW_Invalid;
12964 Value *CallOperandVal = info.CallOperandVal;
12965 // If we don't have a value, we can't do a match,
12966 // but allow it at the lowest weight.
12967 if (!CallOperandVal)
12969 Type *type = CallOperandVal->getType();
12971 // Look at the constraint type.
12972 if (StringRef(constraint) == "wc" && type->isIntegerTy(1))
12973 return CW_Register; // an individual CR bit.
12974 else if ((StringRef(constraint) == "wa" ||
12975 StringRef(constraint) == "wd" ||
12976 StringRef(constraint) == "wf") &&
12977 type->isVectorTy())
12978 return CW_Register;
12979 else if (StringRef(constraint) == "ws" && type->isDoubleTy())
12980 return CW_Register;
12982 switch (*constraint) {
12984 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
12987 if (type->isIntegerTy())
12988 weight = CW_Register;
12991 if (type->isFloatTy())
12992 weight = CW_Register;
12995 if (type->isDoubleTy())
12996 weight = CW_Register;
12999 if (type->isVectorTy())
13000 weight = CW_Register;
13003 weight = CW_Register;
13006 weight = CW_Memory;
13012 std::pair<unsigned, const TargetRegisterClass *>
13013 PPCTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
13014 StringRef Constraint,
13016 if (Constraint.size() == 1) {
13017 // GCC RS6000 Constraint Letters
13018 switch (Constraint[0]) {
13019 case 'b': // R1-R31
13020 if (VT == MVT::i64 && Subtarget.isPPC64())
13021 return std::make_pair(0U, &PPC::G8RC_NOX0RegClass);
13022 return std::make_pair(0U, &PPC::GPRC_NOR0RegClass);
13023 case 'r': // R0-R31
13024 if (VT == MVT::i64 && Subtarget.isPPC64())
13025 return std::make_pair(0U, &PPC::G8RCRegClass);
13026 return std::make_pair(0U, &PPC::GPRCRegClass);
13027 // 'd' and 'f' constraints are both defined to be "the floating point
13028 // registers", where one is for 32-bit and the other for 64-bit. We don't
13029 // really care overly much here so just give them all the same reg classes.
13032 if (VT == MVT::f32 || VT == MVT::i32)
13033 return std::make_pair(0U, &PPC::F4RCRegClass);
13034 if (VT == MVT::f64 || VT == MVT::i64)
13035 return std::make_pair(0U, &PPC::F8RCRegClass);
13036 if (VT == MVT::v4f64 && Subtarget.hasQPX())
13037 return std::make_pair(0U, &PPC::QFRCRegClass);
13038 if (VT == MVT::v4f32 && Subtarget.hasQPX())
13039 return std::make_pair(0U, &PPC::QSRCRegClass);
13042 if (VT == MVT::v4f64 && Subtarget.hasQPX())
13043 return std::make_pair(0U, &PPC::QFRCRegClass);
13044 if (VT == MVT::v4f32 && Subtarget.hasQPX())
13045 return std::make_pair(0U, &PPC::QSRCRegClass);
13046 if (Subtarget.hasAltivec())
13047 return std::make_pair(0U, &PPC::VRRCRegClass);
13050 return std::make_pair(0U, &PPC::CRRCRegClass);
13052 } else if (Constraint == "wc" && Subtarget.useCRBits()) {
13053 // An individual CR bit.
13054 return std::make_pair(0U, &PPC::CRBITRCRegClass);
13055 } else if ((Constraint == "wa" || Constraint == "wd" ||
13056 Constraint == "wf") && Subtarget.hasVSX()) {
13057 return std::make_pair(0U, &PPC::VSRCRegClass);
13058 } else if (Constraint == "ws" && Subtarget.hasVSX()) {
13059 if (VT == MVT::f32 && Subtarget.hasP8Vector())
13060 return std::make_pair(0U, &PPC::VSSRCRegClass);
13062 return std::make_pair(0U, &PPC::VSFRCRegClass);
13065 std::pair<unsigned, const TargetRegisterClass *> R =
13066 TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
13068 // r[0-9]+ are used, on PPC64, to refer to the corresponding 64-bit registers
13069 // (which we call X[0-9]+). If a 64-bit value has been requested, and a
13070 // 32-bit GPR has been selected, then 'upgrade' it to the 64-bit parent
13072 // FIXME: If TargetLowering::getRegForInlineAsmConstraint could somehow use
13073 // the AsmName field from *RegisterInfo.td, then this would not be necessary.
13074 if (R.first && VT == MVT::i64 && Subtarget.isPPC64() &&
13075 PPC::GPRCRegClass.contains(R.first))
13076 return std::make_pair(TRI->getMatchingSuperReg(R.first,
13077 PPC::sub_32, &PPC::G8RCRegClass),
13078 &PPC::G8RCRegClass);
13080 // GCC accepts 'cc' as an alias for 'cr0', and we need to do the same.
13081 if (!R.second && StringRef("{cc}").equals_lower(Constraint)) {
13082 R.first = PPC::CR0;
13083 R.second = &PPC::CRRCRegClass;
13089 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
13090 /// vector. If it is invalid, don't add anything to Ops.
13091 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
13092 std::string &Constraint,
13093 std::vector<SDValue>&Ops,
13094 SelectionDAG &DAG) const {
13097 // Only support length 1 constraints.
13098 if (Constraint.length() > 1) return;
13100 char Letter = Constraint[0];
13111 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
13112 if (!CST) return; // Must be an immediate to match.
13114 int64_t Value = CST->getSExtValue();
13115 EVT TCVT = MVT::i64; // All constants taken to be 64 bits so that negative
13116 // numbers are printed as such.
13118 default: llvm_unreachable("Unknown constraint letter!");
13119 case 'I': // "I" is a signed 16-bit constant.
13120 if (isInt<16>(Value))
13121 Result = DAG.getTargetConstant(Value, dl, TCVT);
13123 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
13124 if (isShiftedUInt<16, 16>(Value))
13125 Result = DAG.getTargetConstant(Value, dl, TCVT);
13127 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
13128 if (isShiftedInt<16, 16>(Value))
13129 Result = DAG.getTargetConstant(Value, dl, TCVT);
13131 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
13132 if (isUInt<16>(Value))
13133 Result = DAG.getTargetConstant(Value, dl, TCVT);
13135 case 'M': // "M" is a constant that is greater than 31.
13137 Result = DAG.getTargetConstant(Value, dl, TCVT);
13139 case 'N': // "N" is a positive constant that is an exact power of two.
13140 if (Value > 0 && isPowerOf2_64(Value))
13141 Result = DAG.getTargetConstant(Value, dl, TCVT);
13143 case 'O': // "O" is the constant zero.
13145 Result = DAG.getTargetConstant(Value, dl, TCVT);
13147 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
13148 if (isInt<16>(-Value))
13149 Result = DAG.getTargetConstant(Value, dl, TCVT);
13156 if (Result.getNode()) {
13157 Ops.push_back(Result);
13161 // Handle standard constraint letters.
13162 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
13165 // isLegalAddressingMode - Return true if the addressing mode represented
13166 // by AM is legal for this target, for a load/store of the specified type.
13167 bool PPCTargetLowering::isLegalAddressingMode(const DataLayout &DL,
13168 const AddrMode &AM, Type *Ty,
13169 unsigned AS, Instruction *I) const {
13170 // PPC does not allow r+i addressing modes for vectors!
13171 if (Ty->isVectorTy() && AM.BaseOffs != 0)
13174 // PPC allows a sign-extended 16-bit immediate field.
13175 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
13178 // No global is ever allowed as a base.
13182 // PPC only support r+r,
13183 switch (AM.Scale) {
13184 case 0: // "r+i" or just "i", depending on HasBaseReg.
13187 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
13189 // Otherwise we have r+r or r+i.
13192 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
13194 // Allow 2*r as r+r.
13197 // No other scales are supported.
13204 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
13205 SelectionDAG &DAG) const {
13206 MachineFunction &MF = DAG.getMachineFunction();
13207 MachineFrameInfo &MFI = MF.getFrameInfo();
13208 MFI.setReturnAddressIsTaken(true);
13210 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
13214 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
13216 // Make sure the function does not optimize away the store of the RA to
13218 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
13219 FuncInfo->setLRStoreRequired();
13220 bool isPPC64 = Subtarget.isPPC64();
13221 auto PtrVT = getPointerTy(MF.getDataLayout());
13224 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
13226 DAG.getConstant(Subtarget.getFrameLowering()->getReturnSaveOffset(), dl,
13227 isPPC64 ? MVT::i64 : MVT::i32);
13228 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
13229 DAG.getNode(ISD::ADD, dl, PtrVT, FrameAddr, Offset),
13230 MachinePointerInfo());
13233 // Just load the return address off the stack.
13234 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
13235 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), RetAddrFI,
13236 MachinePointerInfo());
13239 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
13240 SelectionDAG &DAG) const {
13242 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
13244 MachineFunction &MF = DAG.getMachineFunction();
13245 MachineFrameInfo &MFI = MF.getFrameInfo();
13246 MFI.setFrameAddressIsTaken(true);
13248 EVT PtrVT = getPointerTy(MF.getDataLayout());
13249 bool isPPC64 = PtrVT == MVT::i64;
13251 // Naked functions never have a frame pointer, and so we use r1. For all
13252 // other functions, this decision must be delayed until during PEI.
13254 if (MF.getFunction().hasFnAttribute(Attribute::Naked))
13255 FrameReg = isPPC64 ? PPC::X1 : PPC::R1;
13257 FrameReg = isPPC64 ? PPC::FP8 : PPC::FP;
13259 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
13262 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
13263 FrameAddr, MachinePointerInfo());
13267 // FIXME? Maybe this could be a TableGen attribute on some registers and
13268 // this table could be generated automatically from RegInfo.
13269 unsigned PPCTargetLowering::getRegisterByName(const char* RegName, EVT VT,
13270 SelectionDAG &DAG) const {
13271 bool isPPC64 = Subtarget.isPPC64();
13272 bool isDarwinABI = Subtarget.isDarwinABI();
13274 if ((isPPC64 && VT != MVT::i64 && VT != MVT::i32) ||
13275 (!isPPC64 && VT != MVT::i32))
13276 report_fatal_error("Invalid register global variable type");
13278 bool is64Bit = isPPC64 && VT == MVT::i64;
13279 unsigned Reg = StringSwitch<unsigned>(RegName)
13280 .Case("r1", is64Bit ? PPC::X1 : PPC::R1)
13281 .Case("r2", (isDarwinABI || isPPC64) ? 0 : PPC::R2)
13282 .Case("r13", (!isPPC64 && isDarwinABI) ? 0 :
13283 (is64Bit ? PPC::X13 : PPC::R13))
13288 report_fatal_error("Invalid register name global variable");
13292 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
13293 // The PowerPC target isn't yet aware of offsets.
13297 bool PPCTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
13299 MachineFunction &MF,
13300 unsigned Intrinsic) const {
13301 switch (Intrinsic) {
13302 case Intrinsic::ppc_qpx_qvlfd:
13303 case Intrinsic::ppc_qpx_qvlfs:
13304 case Intrinsic::ppc_qpx_qvlfcd:
13305 case Intrinsic::ppc_qpx_qvlfcs:
13306 case Intrinsic::ppc_qpx_qvlfiwa:
13307 case Intrinsic::ppc_qpx_qvlfiwz:
13308 case Intrinsic::ppc_altivec_lvx:
13309 case Intrinsic::ppc_altivec_lvxl:
13310 case Intrinsic::ppc_altivec_lvebx:
13311 case Intrinsic::ppc_altivec_lvehx:
13312 case Intrinsic::ppc_altivec_lvewx:
13313 case Intrinsic::ppc_vsx_lxvd2x:
13314 case Intrinsic::ppc_vsx_lxvw4x: {
13316 switch (Intrinsic) {
13317 case Intrinsic::ppc_altivec_lvebx:
13320 case Intrinsic::ppc_altivec_lvehx:
13323 case Intrinsic::ppc_altivec_lvewx:
13326 case Intrinsic::ppc_vsx_lxvd2x:
13329 case Intrinsic::ppc_qpx_qvlfd:
13332 case Intrinsic::ppc_qpx_qvlfs:
13335 case Intrinsic::ppc_qpx_qvlfcd:
13338 case Intrinsic::ppc_qpx_qvlfcs:
13346 Info.opc = ISD::INTRINSIC_W_CHAIN;
13348 Info.ptrVal = I.getArgOperand(0);
13349 Info.offset = -VT.getStoreSize()+1;
13350 Info.size = 2*VT.getStoreSize()-1;
13352 Info.flags = MachineMemOperand::MOLoad;
13355 case Intrinsic::ppc_qpx_qvlfda:
13356 case Intrinsic::ppc_qpx_qvlfsa:
13357 case Intrinsic::ppc_qpx_qvlfcda:
13358 case Intrinsic::ppc_qpx_qvlfcsa:
13359 case Intrinsic::ppc_qpx_qvlfiwaa:
13360 case Intrinsic::ppc_qpx_qvlfiwza: {
13362 switch (Intrinsic) {
13363 case Intrinsic::ppc_qpx_qvlfda:
13366 case Intrinsic::ppc_qpx_qvlfsa:
13369 case Intrinsic::ppc_qpx_qvlfcda:
13372 case Intrinsic::ppc_qpx_qvlfcsa:
13380 Info.opc = ISD::INTRINSIC_W_CHAIN;
13382 Info.ptrVal = I.getArgOperand(0);
13384 Info.size = VT.getStoreSize();
13386 Info.flags = MachineMemOperand::MOLoad;
13389 case Intrinsic::ppc_qpx_qvstfd:
13390 case Intrinsic::ppc_qpx_qvstfs:
13391 case Intrinsic::ppc_qpx_qvstfcd:
13392 case Intrinsic::ppc_qpx_qvstfcs:
13393 case Intrinsic::ppc_qpx_qvstfiw:
13394 case Intrinsic::ppc_altivec_stvx:
13395 case Intrinsic::ppc_altivec_stvxl:
13396 case Intrinsic::ppc_altivec_stvebx:
13397 case Intrinsic::ppc_altivec_stvehx:
13398 case Intrinsic::ppc_altivec_stvewx:
13399 case Intrinsic::ppc_vsx_stxvd2x:
13400 case Intrinsic::ppc_vsx_stxvw4x: {
13402 switch (Intrinsic) {
13403 case Intrinsic::ppc_altivec_stvebx:
13406 case Intrinsic::ppc_altivec_stvehx:
13409 case Intrinsic::ppc_altivec_stvewx:
13412 case Intrinsic::ppc_vsx_stxvd2x:
13415 case Intrinsic::ppc_qpx_qvstfd:
13418 case Intrinsic::ppc_qpx_qvstfs:
13421 case Intrinsic::ppc_qpx_qvstfcd:
13424 case Intrinsic::ppc_qpx_qvstfcs:
13432 Info.opc = ISD::INTRINSIC_VOID;
13434 Info.ptrVal = I.getArgOperand(1);
13435 Info.offset = -VT.getStoreSize()+1;
13436 Info.size = 2*VT.getStoreSize()-1;
13438 Info.flags = MachineMemOperand::MOStore;
13441 case Intrinsic::ppc_qpx_qvstfda:
13442 case Intrinsic::ppc_qpx_qvstfsa:
13443 case Intrinsic::ppc_qpx_qvstfcda:
13444 case Intrinsic::ppc_qpx_qvstfcsa:
13445 case Intrinsic::ppc_qpx_qvstfiwa: {
13447 switch (Intrinsic) {
13448 case Intrinsic::ppc_qpx_qvstfda:
13451 case Intrinsic::ppc_qpx_qvstfsa:
13454 case Intrinsic::ppc_qpx_qvstfcda:
13457 case Intrinsic::ppc_qpx_qvstfcsa:
13465 Info.opc = ISD::INTRINSIC_VOID;
13467 Info.ptrVal = I.getArgOperand(1);
13469 Info.size = VT.getStoreSize();
13471 Info.flags = MachineMemOperand::MOStore;
13481 /// getOptimalMemOpType - Returns the target specific optimal type for load
13482 /// and store operations as a result of memset, memcpy, and memmove
13483 /// lowering. If DstAlign is zero that means it's safe to destination
13484 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
13485 /// means there isn't a need to check it against alignment requirement,
13486 /// probably because the source does not need to be loaded. If 'IsMemset' is
13487 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
13488 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
13489 /// source is constant so it does not need to be loaded.
13490 /// It returns EVT::Other if the type should be determined using generic
13491 /// target-independent logic.
13492 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size,
13493 unsigned DstAlign, unsigned SrcAlign,
13494 bool IsMemset, bool ZeroMemset,
13496 MachineFunction &MF) const {
13497 if (getTargetMachine().getOptLevel() != CodeGenOpt::None) {
13498 const Function &F = MF.getFunction();
13499 // When expanding a memset, require at least two QPX instructions to cover
13500 // the cost of loading the value to be stored from the constant pool.
13501 if (Subtarget.hasQPX() && Size >= 32 && (!IsMemset || Size >= 64) &&
13502 (!SrcAlign || SrcAlign >= 32) && (!DstAlign || DstAlign >= 32) &&
13503 !F.hasFnAttribute(Attribute::NoImplicitFloat)) {
13507 // We should use Altivec/VSX loads and stores when available. For unaligned
13508 // addresses, unaligned VSX loads are only fast starting with the P8.
13509 if (Subtarget.hasAltivec() && Size >= 16 &&
13510 (((!SrcAlign || SrcAlign >= 16) && (!DstAlign || DstAlign >= 16)) ||
13511 ((IsMemset && Subtarget.hasVSX()) || Subtarget.hasP8Vector())))
13515 if (Subtarget.isPPC64()) {
13522 /// \brief Returns true if it is beneficial to convert a load of a constant
13523 /// to just the constant itself.
13524 bool PPCTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
13526 assert(Ty->isIntegerTy());
13528 unsigned BitSize = Ty->getPrimitiveSizeInBits();
13529 return !(BitSize == 0 || BitSize > 64);
13532 bool PPCTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
13533 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
13535 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
13536 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
13537 return NumBits1 == 64 && NumBits2 == 32;
13540 bool PPCTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
13541 if (!VT1.isInteger() || !VT2.isInteger())
13543 unsigned NumBits1 = VT1.getSizeInBits();
13544 unsigned NumBits2 = VT2.getSizeInBits();
13545 return NumBits1 == 64 && NumBits2 == 32;
13548 bool PPCTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
13549 // Generally speaking, zexts are not free, but they are free when they can be
13550 // folded with other operations.
13551 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Val)) {
13552 EVT MemVT = LD->getMemoryVT();
13553 if ((MemVT == MVT::i1 || MemVT == MVT::i8 || MemVT == MVT::i16 ||
13554 (Subtarget.isPPC64() && MemVT == MVT::i32)) &&
13555 (LD->getExtensionType() == ISD::NON_EXTLOAD ||
13556 LD->getExtensionType() == ISD::ZEXTLOAD))
13560 // FIXME: Add other cases...
13561 // - 32-bit shifts with a zext to i64
13562 // - zext after ctlz, bswap, etc.
13563 // - zext after and by a constant mask
13565 return TargetLowering::isZExtFree(Val, VT2);
13568 bool PPCTargetLowering::isFPExtFree(EVT DestVT, EVT SrcVT) const {
13569 assert(DestVT.isFloatingPoint() && SrcVT.isFloatingPoint() &&
13570 "invalid fpext types");
13574 bool PPCTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
13575 return isInt<16>(Imm) || isUInt<16>(Imm);
13578 bool PPCTargetLowering::isLegalAddImmediate(int64_t Imm) const {
13579 return isInt<16>(Imm) || isUInt<16>(Imm);
13582 bool PPCTargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
13585 bool *Fast) const {
13586 if (DisablePPCUnaligned)
13589 // PowerPC supports unaligned memory access for simple non-vector types.
13590 // Although accessing unaligned addresses is not as efficient as accessing
13591 // aligned addresses, it is generally more efficient than manual expansion,
13592 // and generally only traps for software emulation when crossing page
13595 if (!VT.isSimple())
13598 if (VT.getSimpleVT().isVector()) {
13599 if (Subtarget.hasVSX()) {
13600 if (VT != MVT::v2f64 && VT != MVT::v2i64 &&
13601 VT != MVT::v4f32 && VT != MVT::v4i32)
13608 if (VT == MVT::ppcf128)
13617 bool PPCTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
13618 VT = VT.getScalarType();
13620 if (!VT.isSimple())
13623 switch (VT.getSimpleVT().SimpleTy) {
13635 PPCTargetLowering::getScratchRegisters(CallingConv::ID) const {
13636 // LR is a callee-save register, but we must treat it as clobbered by any call
13637 // site. Hence we include LR in the scratch registers, which are in turn added
13638 // as implicit-defs for stackmaps and patchpoints. The same reasoning applies
13639 // to CTR, which is used by any indirect call.
13640 static const MCPhysReg ScratchRegs[] = {
13641 PPC::X12, PPC::LR8, PPC::CTR8, 0
13644 return ScratchRegs;
13647 unsigned PPCTargetLowering::getExceptionPointerRegister(
13648 const Constant *PersonalityFn) const {
13649 return Subtarget.isPPC64() ? PPC::X3 : PPC::R3;
13652 unsigned PPCTargetLowering::getExceptionSelectorRegister(
13653 const Constant *PersonalityFn) const {
13654 return Subtarget.isPPC64() ? PPC::X4 : PPC::R4;
13658 PPCTargetLowering::shouldExpandBuildVectorWithShuffles(
13659 EVT VT , unsigned DefinedValues) const {
13660 if (VT == MVT::v2i64)
13661 return Subtarget.hasDirectMove(); // Don't need stack ops with direct moves
13663 if (Subtarget.hasVSX() || Subtarget.hasQPX())
13666 return TargetLowering::shouldExpandBuildVectorWithShuffles(VT, DefinedValues);
13669 Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const {
13670 if (DisableILPPref || Subtarget.enableMachineScheduler())
13671 return TargetLowering::getSchedulingPreference(N);
13676 // Create a fast isel object.
13678 PPCTargetLowering::createFastISel(FunctionLoweringInfo &FuncInfo,
13679 const TargetLibraryInfo *LibInfo) const {
13680 return PPC::createFastISel(FuncInfo, LibInfo);
13683 void PPCTargetLowering::initializeSplitCSR(MachineBasicBlock *Entry) const {
13684 if (Subtarget.isDarwinABI()) return;
13685 if (!Subtarget.isPPC64()) return;
13687 // Update IsSplitCSR in PPCFunctionInfo
13688 PPCFunctionInfo *PFI = Entry->getParent()->getInfo<PPCFunctionInfo>();
13689 PFI->setIsSplitCSR(true);
13692 void PPCTargetLowering::insertCopiesSplitCSR(
13693 MachineBasicBlock *Entry,
13694 const SmallVectorImpl<MachineBasicBlock *> &Exits) const {
13695 const PPCRegisterInfo *TRI = Subtarget.getRegisterInfo();
13696 const MCPhysReg *IStart = TRI->getCalleeSavedRegsViaCopy(Entry->getParent());
13700 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
13701 MachineRegisterInfo *MRI = &Entry->getParent()->getRegInfo();
13702 MachineBasicBlock::iterator MBBI = Entry->begin();
13703 for (const MCPhysReg *I = IStart; *I; ++I) {
13704 const TargetRegisterClass *RC = nullptr;
13705 if (PPC::G8RCRegClass.contains(*I))
13706 RC = &PPC::G8RCRegClass;
13707 else if (PPC::F8RCRegClass.contains(*I))
13708 RC = &PPC::F8RCRegClass;
13709 else if (PPC::CRRCRegClass.contains(*I))
13710 RC = &PPC::CRRCRegClass;
13711 else if (PPC::VRRCRegClass.contains(*I))
13712 RC = &PPC::VRRCRegClass;
13714 llvm_unreachable("Unexpected register class in CSRsViaCopy!");
13716 unsigned NewVR = MRI->createVirtualRegister(RC);
13717 // Create copy from CSR to a virtual register.
13718 // FIXME: this currently does not emit CFI pseudo-instructions, it works
13719 // fine for CXX_FAST_TLS since the C++-style TLS access functions should be
13720 // nounwind. If we want to generalize this later, we may need to emit
13721 // CFI pseudo-instructions.
13722 assert(Entry->getParent()->getFunction().hasFnAttribute(
13723 Attribute::NoUnwind) &&
13724 "Function should be nounwind in insertCopiesSplitCSR!");
13725 Entry->addLiveIn(*I);
13726 BuildMI(*Entry, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), NewVR)
13729 // Insert the copy-back instructions right before the terminator
13730 for (auto *Exit : Exits)
13731 BuildMI(*Exit, Exit->getFirstTerminator(), DebugLoc(),
13732 TII->get(TargetOpcode::COPY), *I)
13737 // Override to enable LOAD_STACK_GUARD lowering on Linux.
13738 bool PPCTargetLowering::useLoadStackGuardNode() const {
13739 if (!Subtarget.isTargetLinux())
13740 return TargetLowering::useLoadStackGuardNode();
13744 // Override to disable global variable loading on Linux.
13745 void PPCTargetLowering::insertSSPDeclarations(Module &M) const {
13746 if (!Subtarget.isTargetLinux())
13747 return TargetLowering::insertSSPDeclarations(M);
13750 bool PPCTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
13751 if (!VT.isSimple() || !Subtarget.hasVSX())
13754 switch(VT.getSimpleVT().SimpleTy) {
13756 // For FP types that are currently not supported by PPC backend, return
13757 // false. Examples: f16, f80.
13762 return Imm.isPosZero();
13766 // For vector shift operation op, fold
13767 // (op x, (and y, ((1 << numbits(x)) - 1))) -> (target op x, y)
13768 static SDValue stripModuloOnShift(const TargetLowering &TLI, SDNode *N,
13769 SelectionDAG &DAG) {
13770 SDValue N0 = N->getOperand(0);
13771 SDValue N1 = N->getOperand(1);
13772 EVT VT = N0.getValueType();
13773 unsigned OpSizeInBits = VT.getScalarSizeInBits();
13774 unsigned Opcode = N->getOpcode();
13775 unsigned TargetOpcode;
13779 llvm_unreachable("Unexpected shift operation");
13781 TargetOpcode = PPCISD::SHL;
13784 TargetOpcode = PPCISD::SRL;
13787 TargetOpcode = PPCISD::SRA;
13791 if (VT.isVector() && TLI.isOperationLegal(Opcode, VT) &&
13792 N1->getOpcode() == ISD::AND)
13793 if (ConstantSDNode *Mask = isConstOrConstSplat(N1->getOperand(1)))
13794 if (Mask->getZExtValue() == OpSizeInBits - 1)
13795 return DAG.getNode(TargetOpcode, SDLoc(N), VT, N0, N1->getOperand(0));
13800 SDValue PPCTargetLowering::combineSHL(SDNode *N, DAGCombinerInfo &DCI) const {
13801 if (auto Value = stripModuloOnShift(*this, N, DCI.DAG))
13807 SDValue PPCTargetLowering::combineSRA(SDNode *N, DAGCombinerInfo &DCI) const {
13808 if (auto Value = stripModuloOnShift(*this, N, DCI.DAG))
13814 SDValue PPCTargetLowering::combineSRL(SDNode *N, DAGCombinerInfo &DCI) const {
13815 if (auto Value = stripModuloOnShift(*this, N, DCI.DAG))
13821 bool PPCTargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {
13822 // Only duplicate to increase tail-calls for the 64bit SysV ABIs.
13823 if (!Subtarget.isSVR4ABI() || !Subtarget.isPPC64())
13826 // If not a tail call then no need to proceed.
13827 if (!CI->isTailCall())
13830 // If tail calls are disabled for the caller then we are done.
13831 const Function *Caller = CI->getParent()->getParent();
13832 auto Attr = Caller->getFnAttribute("disable-tail-calls");
13833 if (Attr.getValueAsString() == "true")
13836 // If sibling calls have been disabled and tail-calls aren't guaranteed
13837 // there is no reason to duplicate.
13838 auto &TM = getTargetMachine();
13839 if (!TM.Options.GuaranteedTailCallOpt && DisableSCO)
13842 // Can't tail call a function called indirectly, or if it has variadic args.
13843 const Function *Callee = CI->getCalledFunction();
13844 if (!Callee || Callee->isVarArg())
13847 // Make sure the callee and caller calling conventions are eligible for tco.
13848 if (!areCallingConvEligibleForTCO_64SVR4(Caller->getCallingConv(),
13849 CI->getCallingConv()))
13852 // If the function is local then we have a good chance at tail-calling it
13853 return getTargetMachine().shouldAssumeDSOLocal(*Caller->getParent(), Callee);