1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "MCTargetDesc/PPCPredicates.h"
16 #include "PPCCallingConv.h"
17 #include "PPCCCState.h"
18 #include "PPCMachineFunctionInfo.h"
19 #include "PPCPerfectShuffle.h"
20 #include "PPCTargetMachine.h"
21 #include "PPCTargetObjectFile.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/ADT/Statistic.h"
24 #include "llvm/ADT/StringSwitch.h"
25 #include "llvm/ADT/Triple.h"
26 #include "llvm/CodeGen/CallingConvLower.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineJumpTableInfo.h"
31 #include "llvm/CodeGen/MachineLoopInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/CodeGen/SelectionDAG.h"
34 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
35 #include "llvm/IR/CallingConv.h"
36 #include "llvm/IR/Constants.h"
37 #include "llvm/IR/DerivedTypes.h"
38 #include "llvm/IR/Function.h"
39 #include "llvm/IR/Intrinsics.h"
40 #include "llvm/Support/CommandLine.h"
41 #include "llvm/Support/ErrorHandling.h"
42 #include "llvm/Support/Format.h"
43 #include "llvm/Support/MathExtras.h"
44 #include "llvm/Support/raw_ostream.h"
45 #include "llvm/Target/TargetOptions.h"
50 #define DEBUG_TYPE "ppc-lowering"
52 static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
53 cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
55 static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
56 cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
58 static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
59 cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
61 static cl::opt<bool> DisableSCO("disable-ppc-sco",
62 cl::desc("disable sibling call optimization on ppc"), cl::Hidden);
64 STATISTIC(NumTailCalls, "Number of tail calls");
65 STATISTIC(NumSiblingCalls, "Number of sibling calls");
67 // FIXME: Remove this once the bug has been fixed!
68 extern cl::opt<bool> ANDIGlueBug;
70 PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
71 const PPCSubtarget &STI)
72 : TargetLowering(TM), Subtarget(STI) {
73 // Use _setjmp/_longjmp instead of setjmp/longjmp.
74 setUseUnderscoreSetJmp(true);
75 setUseUnderscoreLongJmp(true);
77 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
78 // arguments are at least 4/8 bytes aligned.
79 bool isPPC64 = Subtarget.isPPC64();
80 setMinStackArgumentAlignment(isPPC64 ? 8:4);
82 // Set up the register classes.
83 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
84 if (!useSoftFloat()) {
85 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
86 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
89 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
90 for (MVT VT : MVT::integer_valuetypes()) {
91 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
92 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand);
95 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
97 // PowerPC has pre-inc load and store's.
98 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
99 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
100 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
101 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
102 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
103 setIndexedLoadAction(ISD::PRE_INC, MVT::f32, Legal);
104 setIndexedLoadAction(ISD::PRE_INC, MVT::f64, Legal);
105 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
106 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
107 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
108 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
109 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
110 setIndexedStoreAction(ISD::PRE_INC, MVT::f32, Legal);
111 setIndexedStoreAction(ISD::PRE_INC, MVT::f64, Legal);
113 if (Subtarget.useCRBits()) {
114 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
116 if (isPPC64 || Subtarget.hasFPCVT()) {
117 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
118 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1,
119 isPPC64 ? MVT::i64 : MVT::i32);
120 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
121 AddPromotedToType(ISD::UINT_TO_FP, MVT::i1,
122 isPPC64 ? MVT::i64 : MVT::i32);
124 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom);
125 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Custom);
128 // PowerPC does not support direct load / store of condition registers
129 setOperationAction(ISD::LOAD, MVT::i1, Custom);
130 setOperationAction(ISD::STORE, MVT::i1, Custom);
132 // FIXME: Remove this once the ANDI glue bug is fixed:
134 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
136 for (MVT VT : MVT::integer_valuetypes()) {
137 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
138 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
139 setTruncStoreAction(VT, MVT::i1, Expand);
142 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass);
145 // This is used in the ppcf128->int sequence. Note it has different semantics
146 // from FP_ROUND: that rounds to nearest, this rounds to zero.
147 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
149 // We do not currently implement these libm ops for PowerPC.
150 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
151 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
152 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
153 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
154 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
155 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
157 // PowerPC has no SREM/UREM instructions
158 setOperationAction(ISD::SREM, MVT::i32, Expand);
159 setOperationAction(ISD::UREM, MVT::i32, Expand);
160 setOperationAction(ISD::SREM, MVT::i64, Expand);
161 setOperationAction(ISD::UREM, MVT::i64, Expand);
163 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
164 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
165 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
166 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
167 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
168 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
169 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
170 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
171 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
173 // We don't support sin/cos/sqrt/fmod/pow
174 setOperationAction(ISD::FSIN , MVT::f64, Expand);
175 setOperationAction(ISD::FCOS , MVT::f64, Expand);
176 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
177 setOperationAction(ISD::FREM , MVT::f64, Expand);
178 setOperationAction(ISD::FPOW , MVT::f64, Expand);
179 setOperationAction(ISD::FMA , MVT::f64, Legal);
180 setOperationAction(ISD::FSIN , MVT::f32, Expand);
181 setOperationAction(ISD::FCOS , MVT::f32, Expand);
182 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
183 setOperationAction(ISD::FREM , MVT::f32, Expand);
184 setOperationAction(ISD::FPOW , MVT::f32, Expand);
185 setOperationAction(ISD::FMA , MVT::f32, Legal);
187 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
189 // If we're enabling GP optimizations, use hardware square root
190 if (!Subtarget.hasFSQRT() &&
191 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTE() &&
193 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
195 if (!Subtarget.hasFSQRT() &&
196 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTES() &&
197 Subtarget.hasFRES()))
198 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
200 if (Subtarget.hasFCPSGN()) {
201 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal);
202 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal);
204 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
205 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
208 if (Subtarget.hasFPRND()) {
209 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
210 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
211 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
212 setOperationAction(ISD::FROUND, MVT::f64, Legal);
214 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
215 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
216 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
217 setOperationAction(ISD::FROUND, MVT::f32, Legal);
220 // PowerPC does not have BSWAP
221 // CTPOP or CTTZ were introduced in P8/P9 respectivelly
222 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
223 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
224 if (Subtarget.isISA3_0()) {
225 setOperationAction(ISD::CTTZ , MVT::i32 , Legal);
226 setOperationAction(ISD::CTTZ , MVT::i64 , Legal);
228 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
229 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
232 if (Subtarget.hasPOPCNTD() == PPCSubtarget::POPCNTD_Fast) {
233 setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
234 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
236 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
237 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
240 // PowerPC does not have ROTR
241 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
242 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
244 if (!Subtarget.useCRBits()) {
245 // PowerPC does not have Select
246 setOperationAction(ISD::SELECT, MVT::i32, Expand);
247 setOperationAction(ISD::SELECT, MVT::i64, Expand);
248 setOperationAction(ISD::SELECT, MVT::f32, Expand);
249 setOperationAction(ISD::SELECT, MVT::f64, Expand);
252 // PowerPC wants to turn select_cc of FP into fsel when possible.
253 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
254 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
256 // PowerPC wants to optimize integer setcc a bit
257 if (!Subtarget.useCRBits())
258 setOperationAction(ISD::SETCC, MVT::i32, Custom);
260 // PowerPC does not have BRCOND which requires SetCC
261 if (!Subtarget.useCRBits())
262 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
264 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
266 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
267 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
269 // PowerPC does not have [U|S]INT_TO_FP
270 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
271 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
273 if (Subtarget.hasDirectMove() && isPPC64) {
274 setOperationAction(ISD::BITCAST, MVT::f32, Legal);
275 setOperationAction(ISD::BITCAST, MVT::i32, Legal);
276 setOperationAction(ISD::BITCAST, MVT::i64, Legal);
277 setOperationAction(ISD::BITCAST, MVT::f64, Legal);
279 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
280 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
281 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
282 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
285 // We cannot sextinreg(i1). Expand to shifts.
286 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
288 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
289 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
290 // support continuation, user-level threading, and etc.. As a result, no
291 // other SjLj exception interfaces are implemented and please don't build
292 // your own exception handling based on them.
293 // LLVM/Clang supports zero-cost DWARF exception handling.
294 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
295 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
297 // We want to legalize GlobalAddress and ConstantPool nodes into the
298 // appropriate instructions to materialize the address.
299 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
300 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
301 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
302 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
303 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
304 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
305 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
306 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
307 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
308 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
311 setOperationAction(ISD::TRAP, MVT::Other, Legal);
313 // TRAMPOLINE is custom lowered.
314 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
315 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
317 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
318 setOperationAction(ISD::VASTART , MVT::Other, Custom);
320 if (Subtarget.isSVR4ABI()) {
322 // VAARG always uses double-word chunks, so promote anything smaller.
323 setOperationAction(ISD::VAARG, MVT::i1, Promote);
324 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
325 setOperationAction(ISD::VAARG, MVT::i8, Promote);
326 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
327 setOperationAction(ISD::VAARG, MVT::i16, Promote);
328 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
329 setOperationAction(ISD::VAARG, MVT::i32, Promote);
330 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64);
331 setOperationAction(ISD::VAARG, MVT::Other, Expand);
333 // VAARG is custom lowered with the 32-bit SVR4 ABI.
334 setOperationAction(ISD::VAARG, MVT::Other, Custom);
335 setOperationAction(ISD::VAARG, MVT::i64, Custom);
338 setOperationAction(ISD::VAARG, MVT::Other, Expand);
340 if (Subtarget.isSVR4ABI() && !isPPC64)
341 // VACOPY is custom lowered with the 32-bit SVR4 ABI.
342 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
344 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
346 // Use the default implementation.
347 setOperationAction(ISD::VAEND , MVT::Other, Expand);
348 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
349 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
350 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
351 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
352 setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, MVT::i32, Custom);
353 setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, MVT::i64, Custom);
354 setOperationAction(ISD::EH_DWARF_CFA, MVT::i32, Custom);
355 setOperationAction(ISD::EH_DWARF_CFA, MVT::i64, Custom);
357 // We want to custom lower some of our intrinsics.
358 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
360 // To handle counter-based loop conditions.
361 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom);
363 // Comparisons that require checking two conditions.
364 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
365 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
366 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
367 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
368 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
369 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
370 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
371 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
372 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
373 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
374 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
375 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
377 if (Subtarget.has64BitSupport()) {
378 // They also have instructions for converting between i64 and fp.
379 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
380 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
381 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
382 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
383 // This is just the low 32 bits of a (signed) fp->i64 conversion.
384 // We cannot do this with Promote because i64 is not a legal type.
385 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
387 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64())
388 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
390 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
391 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
394 // With the instructions enabled under FPCVT, we can do everything.
395 if (Subtarget.hasFPCVT()) {
396 if (Subtarget.has64BitSupport()) {
397 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
398 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
399 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
400 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
403 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
404 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
405 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
406 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
409 if (Subtarget.use64BitRegs()) {
410 // 64-bit PowerPC implementations can support i64 types directly
411 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
412 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
413 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
414 // 64-bit PowerPC wants to expand i128 shifts itself.
415 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
416 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
417 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
419 // 32-bit PowerPC wants to expand i64 shifts itself.
420 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
421 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
422 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
425 if (Subtarget.hasAltivec()) {
426 // First set operation action for all vector types to expand. Then we
427 // will selectively turn on ones that can be effectively codegen'd.
428 for (MVT VT : MVT::vector_valuetypes()) {
429 // add/sub are legal for all supported vector VT's.
430 setOperationAction(ISD::ADD, VT, Legal);
431 setOperationAction(ISD::SUB, VT, Legal);
433 // Vector instructions introduced in P8
434 if (Subtarget.hasP8Altivec() && (VT.SimpleTy != MVT::v1i128)) {
435 setOperationAction(ISD::CTPOP, VT, Legal);
436 setOperationAction(ISD::CTLZ, VT, Legal);
439 setOperationAction(ISD::CTPOP, VT, Expand);
440 setOperationAction(ISD::CTLZ, VT, Expand);
443 // Vector instructions introduced in P9
444 if (Subtarget.hasP9Altivec() && (VT.SimpleTy != MVT::v1i128))
445 setOperationAction(ISD::CTTZ, VT, Legal);
447 setOperationAction(ISD::CTTZ, VT, Expand);
449 // We promote all shuffles to v16i8.
450 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
451 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
453 // We promote all non-typed operations to v4i32.
454 setOperationAction(ISD::AND , VT, Promote);
455 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
456 setOperationAction(ISD::OR , VT, Promote);
457 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
458 setOperationAction(ISD::XOR , VT, Promote);
459 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
460 setOperationAction(ISD::LOAD , VT, Promote);
461 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
462 setOperationAction(ISD::SELECT, VT, Promote);
463 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
464 setOperationAction(ISD::SELECT_CC, VT, Promote);
465 AddPromotedToType (ISD::SELECT_CC, VT, MVT::v4i32);
466 setOperationAction(ISD::STORE, VT, Promote);
467 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
469 // No other operations are legal.
470 setOperationAction(ISD::MUL , VT, Expand);
471 setOperationAction(ISD::SDIV, VT, Expand);
472 setOperationAction(ISD::SREM, VT, Expand);
473 setOperationAction(ISD::UDIV, VT, Expand);
474 setOperationAction(ISD::UREM, VT, Expand);
475 setOperationAction(ISD::FDIV, VT, Expand);
476 setOperationAction(ISD::FREM, VT, Expand);
477 setOperationAction(ISD::FNEG, VT, Expand);
478 setOperationAction(ISD::FSQRT, VT, Expand);
479 setOperationAction(ISD::FLOG, VT, Expand);
480 setOperationAction(ISD::FLOG10, VT, Expand);
481 setOperationAction(ISD::FLOG2, VT, Expand);
482 setOperationAction(ISD::FEXP, VT, Expand);
483 setOperationAction(ISD::FEXP2, VT, Expand);
484 setOperationAction(ISD::FSIN, VT, Expand);
485 setOperationAction(ISD::FCOS, VT, Expand);
486 setOperationAction(ISD::FABS, VT, Expand);
487 setOperationAction(ISD::FPOWI, VT, Expand);
488 setOperationAction(ISD::FFLOOR, VT, Expand);
489 setOperationAction(ISD::FCEIL, VT, Expand);
490 setOperationAction(ISD::FTRUNC, VT, Expand);
491 setOperationAction(ISD::FRINT, VT, Expand);
492 setOperationAction(ISD::FNEARBYINT, VT, Expand);
493 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
494 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
495 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
496 setOperationAction(ISD::MULHU, VT, Expand);
497 setOperationAction(ISD::MULHS, VT, Expand);
498 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
499 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
500 setOperationAction(ISD::UDIVREM, VT, Expand);
501 setOperationAction(ISD::SDIVREM, VT, Expand);
502 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
503 setOperationAction(ISD::FPOW, VT, Expand);
504 setOperationAction(ISD::BSWAP, VT, Expand);
505 setOperationAction(ISD::VSELECT, VT, Expand);
506 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
507 setOperationAction(ISD::ROTL, VT, Expand);
508 setOperationAction(ISD::ROTR, VT, Expand);
510 for (MVT InnerVT : MVT::vector_valuetypes()) {
511 setTruncStoreAction(VT, InnerVT, Expand);
512 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
513 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
514 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
518 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
519 // with merges, splats, etc.
520 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
522 setOperationAction(ISD::AND , MVT::v4i32, Legal);
523 setOperationAction(ISD::OR , MVT::v4i32, Legal);
524 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
525 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
526 setOperationAction(ISD::SELECT, MVT::v4i32,
527 Subtarget.useCRBits() ? Legal : Expand);
528 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
529 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
530 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
531 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
532 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
533 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
534 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
535 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
536 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
538 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
539 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
540 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
541 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
543 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
544 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
546 if (TM.Options.UnsafeFPMath || Subtarget.hasVSX()) {
547 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
548 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
551 if (Subtarget.hasP8Altivec())
552 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
554 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
556 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
557 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
559 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
560 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
562 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
563 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
564 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
565 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
567 // Altivec does not contain unordered floating-point compare instructions
568 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
569 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
570 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
571 setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
573 if (Subtarget.hasVSX()) {
574 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
575 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
576 if (Subtarget.hasP8Vector()) {
577 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal);
578 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Legal);
580 if (Subtarget.hasDirectMove() && isPPC64) {
581 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Legal);
582 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Legal);
583 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Legal);
584 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i64, Legal);
585 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Legal);
586 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Legal);
587 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Legal);
588 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
590 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
592 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
593 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
594 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
595 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
596 setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
598 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
600 setOperationAction(ISD::MUL, MVT::v2f64, Legal);
601 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
603 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
604 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
606 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
607 setOperationAction(ISD::VSELECT, MVT::v8i16, Legal);
608 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
609 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
610 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
612 // Share the Altivec comparison restrictions.
613 setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand);
614 setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand);
615 setCondCodeAction(ISD::SETO, MVT::v2f64, Expand);
616 setCondCodeAction(ISD::SETONE, MVT::v2f64, Expand);
618 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
619 setOperationAction(ISD::STORE, MVT::v2f64, Legal);
621 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Legal);
623 if (Subtarget.hasP8Vector())
624 addRegisterClass(MVT::f32, &PPC::VSSRCRegClass);
626 addRegisterClass(MVT::f64, &PPC::VSFRCRegClass);
628 addRegisterClass(MVT::v4i32, &PPC::VSRCRegClass);
629 addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass);
630 addRegisterClass(MVT::v2f64, &PPC::VSRCRegClass);
632 if (Subtarget.hasP8Altivec()) {
633 setOperationAction(ISD::SHL, MVT::v2i64, Legal);
634 setOperationAction(ISD::SRA, MVT::v2i64, Legal);
635 setOperationAction(ISD::SRL, MVT::v2i64, Legal);
637 setOperationAction(ISD::SETCC, MVT::v2i64, Legal);
640 setOperationAction(ISD::SHL, MVT::v2i64, Expand);
641 setOperationAction(ISD::SRA, MVT::v2i64, Expand);
642 setOperationAction(ISD::SRL, MVT::v2i64, Expand);
644 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
646 // VSX v2i64 only supports non-arithmetic operations.
647 setOperationAction(ISD::ADD, MVT::v2i64, Expand);
648 setOperationAction(ISD::SUB, MVT::v2i64, Expand);
651 setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
652 AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64);
653 setOperationAction(ISD::STORE, MVT::v2i64, Promote);
654 AddPromotedToType (ISD::STORE, MVT::v2i64, MVT::v2f64);
656 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Legal);
658 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
659 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
660 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
661 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
663 // Vector operation legalization checks the result type of
664 // SIGN_EXTEND_INREG, overall legalization checks the inner type.
665 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal);
666 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
667 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
668 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
670 setOperationAction(ISD::FNEG, MVT::v4f32, Legal);
671 setOperationAction(ISD::FNEG, MVT::v2f64, Legal);
672 setOperationAction(ISD::FABS, MVT::v4f32, Legal);
673 setOperationAction(ISD::FABS, MVT::v2f64, Legal);
675 if (Subtarget.hasDirectMove())
676 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
677 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
679 addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
682 if (Subtarget.hasP8Altivec()) {
683 addRegisterClass(MVT::v2i64, &PPC::VRRCRegClass);
684 addRegisterClass(MVT::v1i128, &PPC::VRRCRegClass);
687 if (Subtarget.hasP9Vector()) {
688 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
689 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
693 if (Subtarget.hasQPX()) {
694 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
695 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
696 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
697 setOperationAction(ISD::FREM, MVT::v4f64, Expand);
699 setOperationAction(ISD::FCOPYSIGN, MVT::v4f64, Legal);
700 setOperationAction(ISD::FGETSIGN, MVT::v4f64, Expand);
702 setOperationAction(ISD::LOAD , MVT::v4f64, Custom);
703 setOperationAction(ISD::STORE , MVT::v4f64, Custom);
705 setTruncStoreAction(MVT::v4f64, MVT::v4f32, Custom);
706 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f32, Custom);
708 if (!Subtarget.useCRBits())
709 setOperationAction(ISD::SELECT, MVT::v4f64, Expand);
710 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
712 setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4f64, Legal);
713 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4f64, Expand);
714 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4f64, Expand);
715 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4f64, Expand);
716 setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4f64, Custom);
717 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f64, Legal);
718 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom);
720 setOperationAction(ISD::FP_TO_SINT , MVT::v4f64, Legal);
721 setOperationAction(ISD::FP_TO_UINT , MVT::v4f64, Expand);
723 setOperationAction(ISD::FP_ROUND , MVT::v4f32, Legal);
724 setOperationAction(ISD::FP_ROUND_INREG , MVT::v4f32, Expand);
725 setOperationAction(ISD::FP_EXTEND, MVT::v4f64, Legal);
727 setOperationAction(ISD::FNEG , MVT::v4f64, Legal);
728 setOperationAction(ISD::FABS , MVT::v4f64, Legal);
729 setOperationAction(ISD::FSIN , MVT::v4f64, Expand);
730 setOperationAction(ISD::FCOS , MVT::v4f64, Expand);
731 setOperationAction(ISD::FPOWI , MVT::v4f64, Expand);
732 setOperationAction(ISD::FPOW , MVT::v4f64, Expand);
733 setOperationAction(ISD::FLOG , MVT::v4f64, Expand);
734 setOperationAction(ISD::FLOG2 , MVT::v4f64, Expand);
735 setOperationAction(ISD::FLOG10 , MVT::v4f64, Expand);
736 setOperationAction(ISD::FEXP , MVT::v4f64, Expand);
737 setOperationAction(ISD::FEXP2 , MVT::v4f64, Expand);
739 setOperationAction(ISD::FMINNUM, MVT::v4f64, Legal);
740 setOperationAction(ISD::FMAXNUM, MVT::v4f64, Legal);
742 setIndexedLoadAction(ISD::PRE_INC, MVT::v4f64, Legal);
743 setIndexedStoreAction(ISD::PRE_INC, MVT::v4f64, Legal);
745 addRegisterClass(MVT::v4f64, &PPC::QFRCRegClass);
747 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
748 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
749 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
750 setOperationAction(ISD::FREM, MVT::v4f32, Expand);
752 setOperationAction(ISD::FCOPYSIGN, MVT::v4f32, Legal);
753 setOperationAction(ISD::FGETSIGN, MVT::v4f32, Expand);
755 setOperationAction(ISD::LOAD , MVT::v4f32, Custom);
756 setOperationAction(ISD::STORE , MVT::v4f32, Custom);
758 if (!Subtarget.useCRBits())
759 setOperationAction(ISD::SELECT, MVT::v4f32, Expand);
760 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
762 setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4f32, Legal);
763 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4f32, Expand);
764 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4f32, Expand);
765 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4f32, Expand);
766 setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4f32, Custom);
767 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal);
768 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
770 setOperationAction(ISD::FP_TO_SINT , MVT::v4f32, Legal);
771 setOperationAction(ISD::FP_TO_UINT , MVT::v4f32, Expand);
773 setOperationAction(ISD::FNEG , MVT::v4f32, Legal);
774 setOperationAction(ISD::FABS , MVT::v4f32, Legal);
775 setOperationAction(ISD::FSIN , MVT::v4f32, Expand);
776 setOperationAction(ISD::FCOS , MVT::v4f32, Expand);
777 setOperationAction(ISD::FPOWI , MVT::v4f32, Expand);
778 setOperationAction(ISD::FPOW , MVT::v4f32, Expand);
779 setOperationAction(ISD::FLOG , MVT::v4f32, Expand);
780 setOperationAction(ISD::FLOG2 , MVT::v4f32, Expand);
781 setOperationAction(ISD::FLOG10 , MVT::v4f32, Expand);
782 setOperationAction(ISD::FEXP , MVT::v4f32, Expand);
783 setOperationAction(ISD::FEXP2 , MVT::v4f32, Expand);
785 setOperationAction(ISD::FMINNUM, MVT::v4f32, Legal);
786 setOperationAction(ISD::FMAXNUM, MVT::v4f32, Legal);
788 setIndexedLoadAction(ISD::PRE_INC, MVT::v4f32, Legal);
789 setIndexedStoreAction(ISD::PRE_INC, MVT::v4f32, Legal);
791 addRegisterClass(MVT::v4f32, &PPC::QSRCRegClass);
793 setOperationAction(ISD::AND , MVT::v4i1, Legal);
794 setOperationAction(ISD::OR , MVT::v4i1, Legal);
795 setOperationAction(ISD::XOR , MVT::v4i1, Legal);
797 if (!Subtarget.useCRBits())
798 setOperationAction(ISD::SELECT, MVT::v4i1, Expand);
799 setOperationAction(ISD::VSELECT, MVT::v4i1, Legal);
801 setOperationAction(ISD::LOAD , MVT::v4i1, Custom);
802 setOperationAction(ISD::STORE , MVT::v4i1, Custom);
804 setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4i1, Custom);
805 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4i1, Expand);
806 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4i1, Expand);
807 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4i1, Expand);
808 setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4i1, Custom);
809 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i1, Expand);
810 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i1, Custom);
812 setOperationAction(ISD::SINT_TO_FP, MVT::v4i1, Custom);
813 setOperationAction(ISD::UINT_TO_FP, MVT::v4i1, Custom);
815 addRegisterClass(MVT::v4i1, &PPC::QBRCRegClass);
817 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
818 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
819 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
820 setOperationAction(ISD::FROUND, MVT::v4f64, Legal);
822 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
823 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
824 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
825 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
827 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Expand);
828 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Expand);
830 // These need to set FE_INEXACT, and so cannot be vectorized here.
831 setOperationAction(ISD::FRINT, MVT::v4f64, Expand);
832 setOperationAction(ISD::FRINT, MVT::v4f32, Expand);
834 if (TM.Options.UnsafeFPMath) {
835 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
836 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
838 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
839 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
841 setOperationAction(ISD::FDIV, MVT::v4f64, Expand);
842 setOperationAction(ISD::FSQRT, MVT::v4f64, Expand);
844 setOperationAction(ISD::FDIV, MVT::v4f32, Expand);
845 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
849 if (Subtarget.has64BitSupport())
850 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
852 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, isPPC64 ? Legal : Custom);
855 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
856 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
859 setBooleanContents(ZeroOrOneBooleanContent);
861 if (Subtarget.hasAltivec()) {
862 // Altivec instructions set fields to all zeros or all ones.
863 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
867 // These libcalls are not available in 32-bit.
868 setLibcallName(RTLIB::SHL_I128, nullptr);
869 setLibcallName(RTLIB::SRL_I128, nullptr);
870 setLibcallName(RTLIB::SRA_I128, nullptr);
873 setStackPointerRegisterToSaveRestore(isPPC64 ? PPC::X1 : PPC::R1);
875 // We have target-specific dag combine patterns for the following nodes:
876 setTargetDAGCombine(ISD::SINT_TO_FP);
877 setTargetDAGCombine(ISD::BUILD_VECTOR);
878 if (Subtarget.hasFPCVT())
879 setTargetDAGCombine(ISD::UINT_TO_FP);
880 setTargetDAGCombine(ISD::LOAD);
881 setTargetDAGCombine(ISD::STORE);
882 setTargetDAGCombine(ISD::BR_CC);
883 if (Subtarget.useCRBits())
884 setTargetDAGCombine(ISD::BRCOND);
885 setTargetDAGCombine(ISD::BSWAP);
886 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
887 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
888 setTargetDAGCombine(ISD::INTRINSIC_VOID);
890 setTargetDAGCombine(ISD::SIGN_EXTEND);
891 setTargetDAGCombine(ISD::ZERO_EXTEND);
892 setTargetDAGCombine(ISD::ANY_EXTEND);
894 if (Subtarget.useCRBits()) {
895 setTargetDAGCombine(ISD::TRUNCATE);
896 setTargetDAGCombine(ISD::SETCC);
897 setTargetDAGCombine(ISD::SELECT_CC);
900 // Use reciprocal estimates.
901 if (TM.Options.UnsafeFPMath) {
902 setTargetDAGCombine(ISD::FDIV);
903 setTargetDAGCombine(ISD::FSQRT);
906 // Darwin long double math library functions have $LDBL128 appended.
907 if (Subtarget.isDarwin()) {
908 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
909 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
910 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
911 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
912 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
913 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
914 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
915 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
916 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
917 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
920 // With 32 condition bits, we don't need to sink (and duplicate) compares
921 // aggressively in CodeGenPrep.
922 if (Subtarget.useCRBits()) {
923 setHasMultipleConditionRegisters();
924 setJumpIsExpensive();
927 setMinFunctionAlignment(2);
928 if (Subtarget.isDarwin())
929 setPrefFunctionAlignment(4);
931 switch (Subtarget.getDarwinDirective()) {
935 case PPC::DIR_E500mc:
945 setPrefFunctionAlignment(4);
946 setPrefLoopAlignment(4);
950 if (Subtarget.enableMachineScheduler())
951 setSchedulingPreference(Sched::Source);
953 setSchedulingPreference(Sched::Hybrid);
955 computeRegisterProperties(STI.getRegisterInfo());
957 // The Freescale cores do better with aggressive inlining of memcpy and
958 // friends. GCC uses same threshold of 128 bytes (= 32 word stores).
959 if (Subtarget.getDarwinDirective() == PPC::DIR_E500mc ||
960 Subtarget.getDarwinDirective() == PPC::DIR_E5500) {
961 MaxStoresPerMemset = 32;
962 MaxStoresPerMemsetOptSize = 16;
963 MaxStoresPerMemcpy = 32;
964 MaxStoresPerMemcpyOptSize = 8;
965 MaxStoresPerMemmove = 32;
966 MaxStoresPerMemmoveOptSize = 8;
967 } else if (Subtarget.getDarwinDirective() == PPC::DIR_A2) {
968 // The A2 also benefits from (very) aggressive inlining of memcpy and
969 // friends. The overhead of a the function call, even when warm, can be
970 // over one hundred cycles.
971 MaxStoresPerMemset = 128;
972 MaxStoresPerMemcpy = 128;
973 MaxStoresPerMemmove = 128;
977 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
978 /// the desired ByVal argument alignment.
979 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign,
980 unsigned MaxMaxAlign) {
981 if (MaxAlign == MaxMaxAlign)
983 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
984 if (MaxMaxAlign >= 32 && VTy->getBitWidth() >= 256)
986 else if (VTy->getBitWidth() >= 128 && MaxAlign < 16)
988 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
989 unsigned EltAlign = 0;
990 getMaxByValAlign(ATy->getElementType(), EltAlign, MaxMaxAlign);
991 if (EltAlign > MaxAlign)
993 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
994 for (auto *EltTy : STy->elements()) {
995 unsigned EltAlign = 0;
996 getMaxByValAlign(EltTy, EltAlign, MaxMaxAlign);
997 if (EltAlign > MaxAlign)
999 if (MaxAlign == MaxMaxAlign)
1005 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1006 /// function arguments in the caller parameter area.
1007 unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty,
1008 const DataLayout &DL) const {
1009 // Darwin passes everything on 4 byte boundary.
1010 if (Subtarget.isDarwin())
1013 // 16byte and wider vectors are passed on 16byte boundary.
1014 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
1015 unsigned Align = Subtarget.isPPC64() ? 8 : 4;
1016 if (Subtarget.hasAltivec() || Subtarget.hasQPX())
1017 getMaxByValAlign(Ty, Align, Subtarget.hasQPX() ? 32 : 16);
1021 bool PPCTargetLowering::useSoftFloat() const {
1022 return Subtarget.useSoftFloat();
1025 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
1026 switch ((PPCISD::NodeType)Opcode) {
1027 case PPCISD::FIRST_NUMBER: break;
1028 case PPCISD::FSEL: return "PPCISD::FSEL";
1029 case PPCISD::FCFID: return "PPCISD::FCFID";
1030 case PPCISD::FCFIDU: return "PPCISD::FCFIDU";
1031 case PPCISD::FCFIDS: return "PPCISD::FCFIDS";
1032 case PPCISD::FCFIDUS: return "PPCISD::FCFIDUS";
1033 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
1034 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
1035 case PPCISD::FCTIDUZ: return "PPCISD::FCTIDUZ";
1036 case PPCISD::FCTIWUZ: return "PPCISD::FCTIWUZ";
1037 case PPCISD::FRE: return "PPCISD::FRE";
1038 case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
1039 case PPCISD::STFIWX: return "PPCISD::STFIWX";
1040 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
1041 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
1042 case PPCISD::VPERM: return "PPCISD::VPERM";
1043 case PPCISD::XXSPLT: return "PPCISD::XXSPLT";
1044 case PPCISD::XXINSERT: return "PPCISD::XXINSERT";
1045 case PPCISD::VECSHL: return "PPCISD::VECSHL";
1046 case PPCISD::CMPB: return "PPCISD::CMPB";
1047 case PPCISD::Hi: return "PPCISD::Hi";
1048 case PPCISD::Lo: return "PPCISD::Lo";
1049 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
1050 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
1051 case PPCISD::DYNAREAOFFSET: return "PPCISD::DYNAREAOFFSET";
1052 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
1053 case PPCISD::SRL: return "PPCISD::SRL";
1054 case PPCISD::SRA: return "PPCISD::SRA";
1055 case PPCISD::SHL: return "PPCISD::SHL";
1056 case PPCISD::SRA_ADDZE: return "PPCISD::SRA_ADDZE";
1057 case PPCISD::CALL: return "PPCISD::CALL";
1058 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
1059 case PPCISD::MTCTR: return "PPCISD::MTCTR";
1060 case PPCISD::BCTRL: return "PPCISD::BCTRL";
1061 case PPCISD::BCTRL_LOAD_TOC: return "PPCISD::BCTRL_LOAD_TOC";
1062 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
1063 case PPCISD::READ_TIME_BASE: return "PPCISD::READ_TIME_BASE";
1064 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
1065 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
1066 case PPCISD::MFOCRF: return "PPCISD::MFOCRF";
1067 case PPCISD::MFVSR: return "PPCISD::MFVSR";
1068 case PPCISD::MTVSRA: return "PPCISD::MTVSRA";
1069 case PPCISD::MTVSRZ: return "PPCISD::MTVSRZ";
1070 case PPCISD::SINT_VEC_TO_FP: return "PPCISD::SINT_VEC_TO_FP";
1071 case PPCISD::UINT_VEC_TO_FP: return "PPCISD::UINT_VEC_TO_FP";
1072 case PPCISD::ANDIo_1_EQ_BIT: return "PPCISD::ANDIo_1_EQ_BIT";
1073 case PPCISD::ANDIo_1_GT_BIT: return "PPCISD::ANDIo_1_GT_BIT";
1074 case PPCISD::VCMP: return "PPCISD::VCMP";
1075 case PPCISD::VCMPo: return "PPCISD::VCMPo";
1076 case PPCISD::LBRX: return "PPCISD::LBRX";
1077 case PPCISD::STBRX: return "PPCISD::STBRX";
1078 case PPCISD::LFIWAX: return "PPCISD::LFIWAX";
1079 case PPCISD::LFIWZX: return "PPCISD::LFIWZX";
1080 case PPCISD::LXSIZX: return "PPCISD::LXSIZX";
1081 case PPCISD::STXSIX: return "PPCISD::STXSIX";
1082 case PPCISD::VEXTS: return "PPCISD::VEXTS";
1083 case PPCISD::LXVD2X: return "PPCISD::LXVD2X";
1084 case PPCISD::STXVD2X: return "PPCISD::STXVD2X";
1085 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
1086 case PPCISD::BDNZ: return "PPCISD::BDNZ";
1087 case PPCISD::BDZ: return "PPCISD::BDZ";
1088 case PPCISD::MFFS: return "PPCISD::MFFS";
1089 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
1090 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
1091 case PPCISD::CR6SET: return "PPCISD::CR6SET";
1092 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
1093 case PPCISD::PPC32_GOT: return "PPCISD::PPC32_GOT";
1094 case PPCISD::PPC32_PICGOT: return "PPCISD::PPC32_PICGOT";
1095 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
1096 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
1097 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
1098 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
1099 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
1100 case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR";
1101 case PPCISD::ADDI_TLSGD_L_ADDR: return "PPCISD::ADDI_TLSGD_L_ADDR";
1102 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
1103 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
1104 case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR";
1105 case PPCISD::ADDI_TLSLD_L_ADDR: return "PPCISD::ADDI_TLSLD_L_ADDR";
1106 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
1107 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
1108 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
1109 case PPCISD::SC: return "PPCISD::SC";
1110 case PPCISD::CLRBHRB: return "PPCISD::CLRBHRB";
1111 case PPCISD::MFBHRBE: return "PPCISD::MFBHRBE";
1112 case PPCISD::RFEBB: return "PPCISD::RFEBB";
1113 case PPCISD::XXSWAPD: return "PPCISD::XXSWAPD";
1114 case PPCISD::SWAP_NO_CHAIN: return "PPCISD::SWAP_NO_CHAIN";
1115 case PPCISD::QVFPERM: return "PPCISD::QVFPERM";
1116 case PPCISD::QVGPCI: return "PPCISD::QVGPCI";
1117 case PPCISD::QVALIGNI: return "PPCISD::QVALIGNI";
1118 case PPCISD::QVESPLATI: return "PPCISD::QVESPLATI";
1119 case PPCISD::QBFLT: return "PPCISD::QBFLT";
1120 case PPCISD::QVLFSb: return "PPCISD::QVLFSb";
1125 EVT PPCTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &C,
1128 return Subtarget.useCRBits() ? MVT::i1 : MVT::i32;
1130 if (Subtarget.hasQPX())
1131 return EVT::getVectorVT(C, MVT::i1, VT.getVectorNumElements());
1133 return VT.changeVectorElementTypeToInteger();
1136 bool PPCTargetLowering::enableAggressiveFMAFusion(EVT VT) const {
1137 assert(VT.isFloatingPoint() && "Non-floating-point FMA?");
1141 //===----------------------------------------------------------------------===//
1142 // Node matching predicates, for use by the tblgen matching code.
1143 //===----------------------------------------------------------------------===//
1145 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
1146 static bool isFloatingPointZero(SDValue Op) {
1147 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
1148 return CFP->getValueAPF().isZero();
1149 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
1150 // Maybe this has already been legalized into the constant pool?
1151 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
1152 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
1153 return CFP->getValueAPF().isZero();
1158 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
1159 /// true if Op is undef or if it matches the specified value.
1160 static bool isConstantOrUndef(int Op, int Val) {
1161 return Op < 0 || Op == Val;
1164 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
1165 /// VPKUHUM instruction.
1166 /// The ShuffleKind distinguishes between big-endian operations with
1167 /// two different inputs (0), either-endian operations with two identical
1168 /// inputs (1), and little-endian operations with two different inputs (2).
1169 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1170 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
1171 SelectionDAG &DAG) {
1172 bool IsLE = DAG.getDataLayout().isLittleEndian();
1173 if (ShuffleKind == 0) {
1176 for (unsigned i = 0; i != 16; ++i)
1177 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
1179 } else if (ShuffleKind == 2) {
1182 for (unsigned i = 0; i != 16; ++i)
1183 if (!isConstantOrUndef(N->getMaskElt(i), i*2))
1185 } else if (ShuffleKind == 1) {
1186 unsigned j = IsLE ? 0 : 1;
1187 for (unsigned i = 0; i != 8; ++i)
1188 if (!isConstantOrUndef(N->getMaskElt(i), i*2+j) ||
1189 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j))
1195 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
1196 /// VPKUWUM instruction.
1197 /// The ShuffleKind distinguishes between big-endian operations with
1198 /// two different inputs (0), either-endian operations with two identical
1199 /// inputs (1), and little-endian operations with two different inputs (2).
1200 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1201 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
1202 SelectionDAG &DAG) {
1203 bool IsLE = DAG.getDataLayout().isLittleEndian();
1204 if (ShuffleKind == 0) {
1207 for (unsigned i = 0; i != 16; i += 2)
1208 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
1209 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
1211 } else if (ShuffleKind == 2) {
1214 for (unsigned i = 0; i != 16; i += 2)
1215 if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
1216 !isConstantOrUndef(N->getMaskElt(i+1), i*2+1))
1218 } else if (ShuffleKind == 1) {
1219 unsigned j = IsLE ? 0 : 2;
1220 for (unsigned i = 0; i != 8; i += 2)
1221 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
1222 !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
1223 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
1224 !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1))
1230 /// isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a
1231 /// VPKUDUM instruction, AND the VPKUDUM instruction exists for the
1232 /// current subtarget.
1234 /// The ShuffleKind distinguishes between big-endian operations with
1235 /// two different inputs (0), either-endian operations with two identical
1236 /// inputs (1), and little-endian operations with two different inputs (2).
1237 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1238 bool PPC::isVPKUDUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
1239 SelectionDAG &DAG) {
1240 const PPCSubtarget& Subtarget =
1241 static_cast<const PPCSubtarget&>(DAG.getSubtarget());
1242 if (!Subtarget.hasP8Vector())
1245 bool IsLE = DAG.getDataLayout().isLittleEndian();
1246 if (ShuffleKind == 0) {
1249 for (unsigned i = 0; i != 16; i += 4)
1250 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+4) ||
1251 !isConstantOrUndef(N->getMaskElt(i+1), i*2+5) ||
1252 !isConstantOrUndef(N->getMaskElt(i+2), i*2+6) ||
1253 !isConstantOrUndef(N->getMaskElt(i+3), i*2+7))
1255 } else if (ShuffleKind == 2) {
1258 for (unsigned i = 0; i != 16; i += 4)
1259 if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
1260 !isConstantOrUndef(N->getMaskElt(i+1), i*2+1) ||
1261 !isConstantOrUndef(N->getMaskElt(i+2), i*2+2) ||
1262 !isConstantOrUndef(N->getMaskElt(i+3), i*2+3))
1264 } else if (ShuffleKind == 1) {
1265 unsigned j = IsLE ? 0 : 4;
1266 for (unsigned i = 0; i != 8; i += 4)
1267 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
1268 !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
1269 !isConstantOrUndef(N->getMaskElt(i+2), i*2+j+2) ||
1270 !isConstantOrUndef(N->getMaskElt(i+3), i*2+j+3) ||
1271 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
1272 !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1) ||
1273 !isConstantOrUndef(N->getMaskElt(i+10), i*2+j+2) ||
1274 !isConstantOrUndef(N->getMaskElt(i+11), i*2+j+3))
1280 /// isVMerge - Common function, used to match vmrg* shuffles.
1282 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
1283 unsigned LHSStart, unsigned RHSStart) {
1284 if (N->getValueType(0) != MVT::v16i8)
1286 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
1287 "Unsupported merge size!");
1289 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
1290 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
1291 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
1292 LHSStart+j+i*UnitSize) ||
1293 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
1294 RHSStart+j+i*UnitSize))
1300 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
1301 /// a VMRGL* instruction with the specified unit size (1,2 or 4 bytes).
1302 /// The ShuffleKind distinguishes between big-endian merges with two
1303 /// different inputs (0), either-endian merges with two identical inputs (1),
1304 /// and little-endian merges with two different inputs (2). For the latter,
1305 /// the input operands are swapped (see PPCInstrAltivec.td).
1306 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
1307 unsigned ShuffleKind, SelectionDAG &DAG) {
1308 if (DAG.getDataLayout().isLittleEndian()) {
1309 if (ShuffleKind == 1) // unary
1310 return isVMerge(N, UnitSize, 0, 0);
1311 else if (ShuffleKind == 2) // swapped
1312 return isVMerge(N, UnitSize, 0, 16);
1316 if (ShuffleKind == 1) // unary
1317 return isVMerge(N, UnitSize, 8, 8);
1318 else if (ShuffleKind == 0) // normal
1319 return isVMerge(N, UnitSize, 8, 24);
1325 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
1326 /// a VMRGH* instruction with the specified unit size (1,2 or 4 bytes).
1327 /// The ShuffleKind distinguishes between big-endian merges with two
1328 /// different inputs (0), either-endian merges with two identical inputs (1),
1329 /// and little-endian merges with two different inputs (2). For the latter,
1330 /// the input operands are swapped (see PPCInstrAltivec.td).
1331 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
1332 unsigned ShuffleKind, SelectionDAG &DAG) {
1333 if (DAG.getDataLayout().isLittleEndian()) {
1334 if (ShuffleKind == 1) // unary
1335 return isVMerge(N, UnitSize, 8, 8);
1336 else if (ShuffleKind == 2) // swapped
1337 return isVMerge(N, UnitSize, 8, 24);
1341 if (ShuffleKind == 1) // unary
1342 return isVMerge(N, UnitSize, 0, 0);
1343 else if (ShuffleKind == 0) // normal
1344 return isVMerge(N, UnitSize, 0, 16);
1351 * \brief Common function used to match vmrgew and vmrgow shuffles
1353 * The indexOffset determines whether to look for even or odd words in
1354 * the shuffle mask. This is based on the of the endianness of the target
1357 * - Use offset of 0 to check for odd elements
1358 * - Use offset of 4 to check for even elements
1360 * - Use offset of 0 to check for even elements
1361 * - Use offset of 4 to check for odd elements
1362 * A detailed description of the vector element ordering for little endian and
1363 * big endian can be found at
1364 * http://www.ibm.com/developerworks/library/l-ibm-xl-c-cpp-compiler/index.html
1365 * Targeting your applications - what little endian and big endian IBM XL C/C++
1366 * compiler differences mean to you
1368 * The mask to the shuffle vector instruction specifies the indices of the
1369 * elements from the two input vectors to place in the result. The elements are
1370 * numbered in array-access order, starting with the first vector. These vectors
1371 * are always of type v16i8, thus each vector will contain 16 elements of size
1372 * 8. More info on the shuffle vector can be found in the
1373 * http://llvm.org/docs/LangRef.html#shufflevector-instruction
1374 * Language Reference.
1376 * The RHSStartValue indicates whether the same input vectors are used (unary)
1377 * or two different input vectors are used, based on the following:
1378 * - If the instruction uses the same vector for both inputs, the range of the
1379 * indices will be 0 to 15. In this case, the RHSStart value passed should
1381 * - If the instruction has two different vectors then the range of the
1382 * indices will be 0 to 31. In this case, the RHSStart value passed should
1383 * be 16 (indices 0-15 specify elements in the first vector while indices 16
1384 * to 31 specify elements in the second vector).
1386 * \param[in] N The shuffle vector SD Node to analyze
1387 * \param[in] IndexOffset Specifies whether to look for even or odd elements
1388 * \param[in] RHSStartValue Specifies the starting index for the righthand input
1389 * vector to the shuffle_vector instruction
1390 * \return true iff this shuffle vector represents an even or odd word merge
1392 static bool isVMerge(ShuffleVectorSDNode *N, unsigned IndexOffset,
1393 unsigned RHSStartValue) {
1394 if (N->getValueType(0) != MVT::v16i8)
1397 for (unsigned i = 0; i < 2; ++i)
1398 for (unsigned j = 0; j < 4; ++j)
1399 if (!isConstantOrUndef(N->getMaskElt(i*4+j),
1400 i*RHSStartValue+j+IndexOffset) ||
1401 !isConstantOrUndef(N->getMaskElt(i*4+j+8),
1402 i*RHSStartValue+j+IndexOffset+8))
1408 * \brief Determine if the specified shuffle mask is suitable for the vmrgew or
1409 * vmrgow instructions.
1411 * \param[in] N The shuffle vector SD Node to analyze
1412 * \param[in] CheckEven Check for an even merge (true) or an odd merge (false)
1413 * \param[in] ShuffleKind Identify the type of merge:
1414 * - 0 = big-endian merge with two different inputs;
1415 * - 1 = either-endian merge with two identical inputs;
1416 * - 2 = little-endian merge with two different inputs (inputs are swapped for
1417 * little-endian merges).
1418 * \param[in] DAG The current SelectionDAG
1419 * \return true iff this shuffle mask
1421 bool PPC::isVMRGEOShuffleMask(ShuffleVectorSDNode *N, bool CheckEven,
1422 unsigned ShuffleKind, SelectionDAG &DAG) {
1423 if (DAG.getDataLayout().isLittleEndian()) {
1424 unsigned indexOffset = CheckEven ? 4 : 0;
1425 if (ShuffleKind == 1) // Unary
1426 return isVMerge(N, indexOffset, 0);
1427 else if (ShuffleKind == 2) // swapped
1428 return isVMerge(N, indexOffset, 16);
1433 unsigned indexOffset = CheckEven ? 0 : 4;
1434 if (ShuffleKind == 1) // Unary
1435 return isVMerge(N, indexOffset, 0);
1436 else if (ShuffleKind == 0) // Normal
1437 return isVMerge(N, indexOffset, 16);
1444 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
1445 /// amount, otherwise return -1.
1446 /// The ShuffleKind distinguishes between big-endian operations with two
1447 /// different inputs (0), either-endian operations with two identical inputs
1448 /// (1), and little-endian operations with two different inputs (2). For the
1449 /// latter, the input operands are swapped (see PPCInstrAltivec.td).
1450 int PPC::isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind,
1451 SelectionDAG &DAG) {
1452 if (N->getValueType(0) != MVT::v16i8)
1455 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1457 // Find the first non-undef value in the shuffle mask.
1459 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
1462 if (i == 16) return -1; // all undef.
1464 // Otherwise, check to see if the rest of the elements are consecutively
1465 // numbered from this value.
1466 unsigned ShiftAmt = SVOp->getMaskElt(i);
1467 if (ShiftAmt < i) return -1;
1470 bool isLE = DAG.getDataLayout().isLittleEndian();
1472 if ((ShuffleKind == 0 && !isLE) || (ShuffleKind == 2 && isLE)) {
1473 // Check the rest of the elements to see if they are consecutive.
1474 for (++i; i != 16; ++i)
1475 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
1477 } else if (ShuffleKind == 1) {
1478 // Check the rest of the elements to see if they are consecutive.
1479 for (++i; i != 16; ++i)
1480 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
1486 ShiftAmt = 16 - ShiftAmt;
1491 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
1492 /// specifies a splat of a single element that is suitable for input to
1493 /// VSPLTB/VSPLTH/VSPLTW.
1494 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
1495 assert(N->getValueType(0) == MVT::v16i8 &&
1496 (EltSize == 1 || EltSize == 2 || EltSize == 4));
1498 // The consecutive indices need to specify an element, not part of two
1499 // different elements. So abandon ship early if this isn't the case.
1500 if (N->getMaskElt(0) % EltSize != 0)
1503 // This is a splat operation if each element of the permute is the same, and
1504 // if the value doesn't reference the second vector.
1505 unsigned ElementBase = N->getMaskElt(0);
1507 // FIXME: Handle UNDEF elements too!
1508 if (ElementBase >= 16)
1511 // Check that the indices are consecutive, in the case of a multi-byte element
1512 // splatted with a v16i8 mask.
1513 for (unsigned i = 1; i != EltSize; ++i)
1514 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
1517 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
1518 if (N->getMaskElt(i) < 0) continue;
1519 for (unsigned j = 0; j != EltSize; ++j)
1520 if (N->getMaskElt(i+j) != N->getMaskElt(j))
1526 bool PPC::isXXINSERTWMask(ShuffleVectorSDNode *N, unsigned &ShiftElts,
1527 unsigned &InsertAtByte, bool &Swap, bool IsLE) {
1529 // Check that the mask is shuffling words
1530 for (unsigned i = 0; i < 4; ++i) {
1531 unsigned B0 = N->getMaskElt(i*4);
1532 unsigned B1 = N->getMaskElt(i*4+1);
1533 unsigned B2 = N->getMaskElt(i*4+2);
1534 unsigned B3 = N->getMaskElt(i*4+3);
1537 if (B1 != B0+1 || B2 != B1+1 || B3 != B2+1)
1541 // Now we look at mask elements 0,4,8,12
1542 unsigned M0 = N->getMaskElt(0) / 4;
1543 unsigned M1 = N->getMaskElt(4) / 4;
1544 unsigned M2 = N->getMaskElt(8) / 4;
1545 unsigned M3 = N->getMaskElt(12) / 4;
1546 unsigned LittleEndianShifts[] = { 2, 1, 0, 3 };
1547 unsigned BigEndianShifts[] = { 3, 0, 1, 2 };
1549 // Below, let H and L be arbitrary elements of the shuffle mask
1550 // where H is in the range [4,7] and L is in the range [0,3].
1551 // H, 1, 2, 3 or L, 5, 6, 7
1552 if ((M0 > 3 && M1 == 1 && M2 == 2 && M3 == 3) ||
1553 (M0 < 4 && M1 == 5 && M2 == 6 && M3 == 7)) {
1554 ShiftElts = IsLE ? LittleEndianShifts[M0 & 0x3] : BigEndianShifts[M0 & 0x3];
1555 InsertAtByte = IsLE ? 12 : 0;
1559 // 0, H, 2, 3 or 4, L, 6, 7
1560 if ((M1 > 3 && M0 == 0 && M2 == 2 && M3 == 3) ||
1561 (M1 < 4 && M0 == 4 && M2 == 6 && M3 == 7)) {
1562 ShiftElts = IsLE ? LittleEndianShifts[M1 & 0x3] : BigEndianShifts[M1 & 0x3];
1563 InsertAtByte = IsLE ? 8 : 4;
1567 // 0, 1, H, 3 or 4, 5, L, 7
1568 if ((M2 > 3 && M0 == 0 && M1 == 1 && M3 == 3) ||
1569 (M2 < 4 && M0 == 4 && M1 == 5 && M3 == 7)) {
1570 ShiftElts = IsLE ? LittleEndianShifts[M2 & 0x3] : BigEndianShifts[M2 & 0x3];
1571 InsertAtByte = IsLE ? 4 : 8;
1575 // 0, 1, 2, H or 4, 5, 6, L
1576 if ((M3 > 3 && M0 == 0 && M1 == 1 && M2 == 2) ||
1577 (M3 < 4 && M0 == 4 && M1 == 5 && M2 == 6)) {
1578 ShiftElts = IsLE ? LittleEndianShifts[M3 & 0x3] : BigEndianShifts[M3 & 0x3];
1579 InsertAtByte = IsLE ? 0 : 12;
1584 // If both vector operands for the shuffle are the same vector, the mask will
1585 // contain only elements from the first one and the second one will be undef.
1586 if (N->getOperand(1).isUndef()) {
1589 unsigned XXINSERTWSrcElem = IsLE ? 2 : 1;
1590 if (M0 == XXINSERTWSrcElem && M1 == 1 && M2 == 2 && M3 == 3) {
1591 InsertAtByte = IsLE ? 12 : 0;
1594 if (M0 == 0 && M1 == XXINSERTWSrcElem && M2 == 2 && M3 == 3) {
1595 InsertAtByte = IsLE ? 8 : 4;
1598 if (M0 == 0 && M1 == 1 && M2 == XXINSERTWSrcElem && M3 == 3) {
1599 InsertAtByte = IsLE ? 4 : 8;
1602 if (M0 == 0 && M1 == 1 && M2 == 2 && M3 == XXINSERTWSrcElem) {
1603 InsertAtByte = IsLE ? 0 : 12;
1611 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
1612 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
1613 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize,
1614 SelectionDAG &DAG) {
1615 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1616 assert(isSplatShuffleMask(SVOp, EltSize));
1617 if (DAG.getDataLayout().isLittleEndian())
1618 return (16 / EltSize) - 1 - (SVOp->getMaskElt(0) / EltSize);
1620 return SVOp->getMaskElt(0) / EltSize;
1623 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
1624 /// by using a vspltis[bhw] instruction of the specified element size, return
1625 /// the constant being splatted. The ByteSize field indicates the number of
1626 /// bytes of each element [124] -> [bhw].
1627 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
1628 SDValue OpVal(nullptr, 0);
1630 // If ByteSize of the splat is bigger than the element size of the
1631 // build_vector, then we have a case where we are checking for a splat where
1632 // multiple elements of the buildvector are folded together into a single
1633 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
1634 unsigned EltSize = 16/N->getNumOperands();
1635 if (EltSize < ByteSize) {
1636 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
1637 SDValue UniquedVals[4];
1638 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
1640 // See if all of the elements in the buildvector agree across.
1641 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1642 if (N->getOperand(i).isUndef()) continue;
1643 // If the element isn't a constant, bail fully out.
1644 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
1647 if (!UniquedVals[i&(Multiple-1)].getNode())
1648 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
1649 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
1650 return SDValue(); // no match.
1653 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
1654 // either constant or undef values that are identical for each chunk. See
1655 // if these chunks can form into a larger vspltis*.
1657 // Check to see if all of the leading entries are either 0 or -1. If
1658 // neither, then this won't fit into the immediate field.
1659 bool LeadingZero = true;
1660 bool LeadingOnes = true;
1661 for (unsigned i = 0; i != Multiple-1; ++i) {
1662 if (!UniquedVals[i].getNode()) continue; // Must have been undefs.
1664 LeadingZero &= isNullConstant(UniquedVals[i]);
1665 LeadingOnes &= isAllOnesConstant(UniquedVals[i]);
1667 // Finally, check the least significant entry.
1669 if (!UniquedVals[Multiple-1].getNode())
1670 return DAG.getTargetConstant(0, SDLoc(N), MVT::i32); // 0,0,0,undef
1671 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
1672 if (Val < 16) // 0,0,0,4 -> vspltisw(4)
1673 return DAG.getTargetConstant(Val, SDLoc(N), MVT::i32);
1676 if (!UniquedVals[Multiple-1].getNode())
1677 return DAG.getTargetConstant(~0U, SDLoc(N), MVT::i32); // -1,-1,-1,undef
1678 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
1679 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
1680 return DAG.getTargetConstant(Val, SDLoc(N), MVT::i32);
1686 // Check to see if this buildvec has a single non-undef value in its elements.
1687 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1688 if (N->getOperand(i).isUndef()) continue;
1689 if (!OpVal.getNode())
1690 OpVal = N->getOperand(i);
1691 else if (OpVal != N->getOperand(i))
1695 if (!OpVal.getNode()) return SDValue(); // All UNDEF: use implicit def.
1697 unsigned ValSizeInBytes = EltSize;
1699 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
1700 Value = CN->getZExtValue();
1701 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
1702 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
1703 Value = FloatToBits(CN->getValueAPF().convertToFloat());
1706 // If the splat value is larger than the element value, then we can never do
1707 // this splat. The only case that we could fit the replicated bits into our
1708 // immediate field for would be zero, and we prefer to use vxor for it.
1709 if (ValSizeInBytes < ByteSize) return SDValue();
1711 // If the element value is larger than the splat value, check if it consists
1712 // of a repeated bit pattern of size ByteSize.
1713 if (!APInt(ValSizeInBytes * 8, Value).isSplat(ByteSize * 8))
1716 // Properly sign extend the value.
1717 int MaskVal = SignExtend32(Value, ByteSize * 8);
1719 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
1720 if (MaskVal == 0) return SDValue();
1722 // Finally, if this value fits in a 5 bit sext field, return it
1723 if (SignExtend32<5>(MaskVal) == MaskVal)
1724 return DAG.getTargetConstant(MaskVal, SDLoc(N), MVT::i32);
1728 /// isQVALIGNIShuffleMask - If this is a qvaligni shuffle mask, return the shift
1729 /// amount, otherwise return -1.
1730 int PPC::isQVALIGNIShuffleMask(SDNode *N) {
1731 EVT VT = N->getValueType(0);
1732 if (VT != MVT::v4f64 && VT != MVT::v4f32 && VT != MVT::v4i1)
1735 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1737 // Find the first non-undef value in the shuffle mask.
1739 for (i = 0; i != 4 && SVOp->getMaskElt(i) < 0; ++i)
1742 if (i == 4) return -1; // all undef.
1744 // Otherwise, check to see if the rest of the elements are consecutively
1745 // numbered from this value.
1746 unsigned ShiftAmt = SVOp->getMaskElt(i);
1747 if (ShiftAmt < i) return -1;
1750 // Check the rest of the elements to see if they are consecutive.
1751 for (++i; i != 4; ++i)
1752 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
1758 //===----------------------------------------------------------------------===//
1759 // Addressing Mode Selection
1760 //===----------------------------------------------------------------------===//
1762 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
1763 /// or 64-bit immediate, and if the value can be accurately represented as a
1764 /// sign extension from a 16-bit value. If so, this returns true and the
1766 static bool isIntS16Immediate(SDNode *N, short &Imm) {
1767 if (!isa<ConstantSDNode>(N))
1770 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
1771 if (N->getValueType(0) == MVT::i32)
1772 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
1774 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
1776 static bool isIntS16Immediate(SDValue Op, short &Imm) {
1777 return isIntS16Immediate(Op.getNode(), Imm);
1780 /// SelectAddressRegReg - Given the specified addressed, check to see if it
1781 /// can be represented as an indexed [r+r] operation. Returns false if it
1782 /// can be more efficiently represented with [r+imm].
1783 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
1785 SelectionDAG &DAG) const {
1787 if (N.getOpcode() == ISD::ADD) {
1788 if (isIntS16Immediate(N.getOperand(1), imm))
1789 return false; // r+i
1790 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
1791 return false; // r+i
1793 Base = N.getOperand(0);
1794 Index = N.getOperand(1);
1796 } else if (N.getOpcode() == ISD::OR) {
1797 if (isIntS16Immediate(N.getOperand(1), imm))
1798 return false; // r+i can fold it if we can.
1800 // If this is an or of disjoint bitfields, we can codegen this as an add
1801 // (for better address arithmetic) if the LHS and RHS of the OR are provably
1803 APInt LHSKnownZero, LHSKnownOne;
1804 APInt RHSKnownZero, RHSKnownOne;
1805 DAG.computeKnownBits(N.getOperand(0),
1806 LHSKnownZero, LHSKnownOne);
1808 if (LHSKnownZero.getBoolValue()) {
1809 DAG.computeKnownBits(N.getOperand(1),
1810 RHSKnownZero, RHSKnownOne);
1811 // If all of the bits are known zero on the LHS or RHS, the add won't
1813 if (~(LHSKnownZero | RHSKnownZero) == 0) {
1814 Base = N.getOperand(0);
1815 Index = N.getOperand(1);
1824 // If we happen to be doing an i64 load or store into a stack slot that has
1825 // less than a 4-byte alignment, then the frame-index elimination may need to
1826 // use an indexed load or store instruction (because the offset may not be a
1827 // multiple of 4). The extra register needed to hold the offset comes from the
1828 // register scavenger, and it is possible that the scavenger will need to use
1829 // an emergency spill slot. As a result, we need to make sure that a spill slot
1830 // is allocated when doing an i64 load/store into a less-than-4-byte-aligned
1832 static void fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT) {
1833 // FIXME: This does not handle the LWA case.
1837 // NOTE: We'll exclude negative FIs here, which come from argument
1838 // lowering, because there are no known test cases triggering this problem
1839 // using packed structures (or similar). We can remove this exclusion if
1840 // we find such a test case. The reason why this is so test-case driven is
1841 // because this entire 'fixup' is only to prevent crashes (from the
1842 // register scavenger) on not-really-valid inputs. For example, if we have:
1844 // %b = bitcast i1* %a to i64*
1845 // store i64* a, i64 b
1846 // then the store should really be marked as 'align 1', but is not. If it
1847 // were marked as 'align 1' then the indexed form would have been
1848 // instruction-selected initially, and the problem this 'fixup' is preventing
1849 // won't happen regardless.
1853 MachineFunction &MF = DAG.getMachineFunction();
1854 MachineFrameInfo &MFI = MF.getFrameInfo();
1856 unsigned Align = MFI.getObjectAlignment(FrameIdx);
1860 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1861 FuncInfo->setHasNonRISpills();
1864 /// Returns true if the address N can be represented by a base register plus
1865 /// a signed 16-bit displacement [r+imm], and if it is not better
1866 /// represented as reg+reg. If Aligned is true, only accept displacements
1867 /// suitable for STD and friends, i.e. multiples of 4.
1868 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
1871 bool Aligned) const {
1872 // FIXME dl should come from parent load or store, not from address
1874 // If this can be more profitably realized as r+r, fail.
1875 if (SelectAddressRegReg(N, Disp, Base, DAG))
1878 if (N.getOpcode() == ISD::ADD) {
1880 if (isIntS16Immediate(N.getOperand(1), imm) &&
1881 (!Aligned || (imm & 3) == 0)) {
1882 Disp = DAG.getTargetConstant(imm, dl, N.getValueType());
1883 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1884 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1885 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1887 Base = N.getOperand(0);
1889 return true; // [r+i]
1890 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
1891 // Match LOAD (ADD (X, Lo(G))).
1892 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
1893 && "Cannot handle constant offsets yet!");
1894 Disp = N.getOperand(1).getOperand(0); // The global address.
1895 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
1896 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||
1897 Disp.getOpcode() == ISD::TargetConstantPool ||
1898 Disp.getOpcode() == ISD::TargetJumpTable);
1899 Base = N.getOperand(0);
1900 return true; // [&g+r]
1902 } else if (N.getOpcode() == ISD::OR) {
1904 if (isIntS16Immediate(N.getOperand(1), imm) &&
1905 (!Aligned || (imm & 3) == 0)) {
1906 // If this is an or of disjoint bitfields, we can codegen this as an add
1907 // (for better address arithmetic) if the LHS and RHS of the OR are
1908 // provably disjoint.
1909 APInt LHSKnownZero, LHSKnownOne;
1910 DAG.computeKnownBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
1912 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1913 // If all of the bits are known zero on the LHS or RHS, the add won't
1915 if (FrameIndexSDNode *FI =
1916 dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1917 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1918 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1920 Base = N.getOperand(0);
1922 Disp = DAG.getTargetConstant(imm, dl, N.getValueType());
1926 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1927 // Loading from a constant address.
1929 // If this address fits entirely in a 16-bit sext immediate field, codegen
1932 if (isIntS16Immediate(CN, Imm) && (!Aligned || (Imm & 3) == 0)) {
1933 Disp = DAG.getTargetConstant(Imm, dl, CN->getValueType(0));
1934 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1935 CN->getValueType(0));
1939 // Handle 32-bit sext immediates with LIS + addr mode.
1940 if ((CN->getValueType(0) == MVT::i32 ||
1941 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) &&
1942 (!Aligned || (CN->getZExtValue() & 3) == 0)) {
1943 int Addr = (int)CN->getZExtValue();
1945 // Otherwise, break this down into an LIS + disp.
1946 Disp = DAG.getTargetConstant((short)Addr, dl, MVT::i32);
1948 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, dl,
1950 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1951 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
1956 Disp = DAG.getTargetConstant(0, dl, getPointerTy(DAG.getDataLayout()));
1957 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
1958 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1959 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1962 return true; // [r+0]
1965 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
1966 /// represented as an indexed [r+r] operation.
1967 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
1969 SelectionDAG &DAG) const {
1970 // Check to see if we can easily represent this as an [r+r] address. This
1971 // will fail if it thinks that the address is more profitably represented as
1972 // reg+imm, e.g. where imm = 0.
1973 if (SelectAddressRegReg(N, Base, Index, DAG))
1976 // If the operand is an addition, always emit this as [r+r], since this is
1977 // better (for code size, and execution, as the memop does the add for free)
1978 // than emitting an explicit add.
1979 if (N.getOpcode() == ISD::ADD) {
1980 Base = N.getOperand(0);
1981 Index = N.getOperand(1);
1985 // Otherwise, do it the hard way, using R0 as the base register.
1986 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1992 /// getPreIndexedAddressParts - returns true by value, base pointer and
1993 /// offset pointer and addressing mode by reference if the node's address
1994 /// can be legally represented as pre-indexed load / store address.
1995 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1997 ISD::MemIndexedMode &AM,
1998 SelectionDAG &DAG) const {
1999 if (DisablePPCPreinc) return false;
2005 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
2006 Ptr = LD->getBasePtr();
2007 VT = LD->getMemoryVT();
2008 Alignment = LD->getAlignment();
2009 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
2010 Ptr = ST->getBasePtr();
2011 VT = ST->getMemoryVT();
2012 Alignment = ST->getAlignment();
2017 // PowerPC doesn't have preinc load/store instructions for vectors (except
2018 // for QPX, which does have preinc r+r forms).
2019 if (VT.isVector()) {
2020 if (!Subtarget.hasQPX() || (VT != MVT::v4f64 && VT != MVT::v4f32)) {
2022 } else if (SelectAddressRegRegOnly(Ptr, Offset, Base, DAG)) {
2028 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
2030 // Common code will reject creating a pre-inc form if the base pointer
2031 // is a frame index, or if N is a store and the base pointer is either
2032 // the same as or a predecessor of the value being stored. Check for
2033 // those situations here, and try with swapped Base/Offset instead.
2036 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
2039 SDValue Val = cast<StoreSDNode>(N)->getValue();
2040 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
2045 std::swap(Base, Offset);
2051 // LDU/STU can only handle immediates that are a multiple of 4.
2052 if (VT != MVT::i64) {
2053 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, false))
2056 // LDU/STU need an address with at least 4-byte alignment.
2060 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, true))
2064 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
2065 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
2066 // sext i32 to i64 when addr mode is r+i.
2067 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
2068 LD->getExtensionType() == ISD::SEXTLOAD &&
2069 isa<ConstantSDNode>(Offset))
2077 //===----------------------------------------------------------------------===//
2078 // LowerOperation implementation
2079 //===----------------------------------------------------------------------===//
2081 /// Return true if we should reference labels using a PICBase, set the HiOpFlags
2082 /// and LoOpFlags to the target MO flags.
2083 static void getLabelAccessInfo(bool IsPIC, const PPCSubtarget &Subtarget,
2084 unsigned &HiOpFlags, unsigned &LoOpFlags,
2085 const GlobalValue *GV = nullptr) {
2086 HiOpFlags = PPCII::MO_HA;
2087 LoOpFlags = PPCII::MO_LO;
2089 // Don't use the pic base if not in PIC relocation model.
2091 HiOpFlags |= PPCII::MO_PIC_FLAG;
2092 LoOpFlags |= PPCII::MO_PIC_FLAG;
2095 // If this is a reference to a global value that requires a non-lazy-ptr, make
2096 // sure that instruction lowering adds it.
2097 if (GV && Subtarget.hasLazyResolverStub(GV)) {
2098 HiOpFlags |= PPCII::MO_NLP_FLAG;
2099 LoOpFlags |= PPCII::MO_NLP_FLAG;
2101 if (GV->hasHiddenVisibility()) {
2102 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
2103 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
2108 static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
2109 SelectionDAG &DAG) {
2111 EVT PtrVT = HiPart.getValueType();
2112 SDValue Zero = DAG.getConstant(0, DL, PtrVT);
2114 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
2115 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
2117 // With PIC, the first instruction is actually "GR+hi(&G)".
2119 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
2120 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
2122 // Generate non-pic code that has direct accesses to the constant pool.
2123 // The address of the global is just (hi(&g)+lo(&g)).
2124 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
2127 static void setUsesTOCBasePtr(MachineFunction &MF) {
2128 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2129 FuncInfo->setUsesTOCBasePtr();
2132 static void setUsesTOCBasePtr(SelectionDAG &DAG) {
2133 setUsesTOCBasePtr(DAG.getMachineFunction());
2136 static SDValue getTOCEntry(SelectionDAG &DAG, const SDLoc &dl, bool Is64Bit,
2138 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
2139 SDValue Reg = Is64Bit ? DAG.getRegister(PPC::X2, VT) :
2140 DAG.getNode(PPCISD::GlobalBaseReg, dl, VT);
2142 SDValue Ops[] = { GA, Reg };
2143 return DAG.getMemIntrinsicNode(
2144 PPCISD::TOC_ENTRY, dl, DAG.getVTList(VT, MVT::Other), Ops, VT,
2145 MachinePointerInfo::getGOT(DAG.getMachineFunction()), 0, false, true,
2149 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
2150 SelectionDAG &DAG) const {
2151 EVT PtrVT = Op.getValueType();
2152 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
2153 const Constant *C = CP->getConstVal();
2155 // 64-bit SVR4 ABI code is always position-independent.
2156 // The actual address of the GlobalValue is stored in the TOC.
2157 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
2158 setUsesTOCBasePtr(DAG);
2159 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0);
2160 return getTOCEntry(DAG, SDLoc(CP), true, GA);
2163 unsigned MOHiFlag, MOLoFlag;
2164 bool IsPIC = isPositionIndependent();
2165 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag);
2167 if (IsPIC && Subtarget.isSVR4ABI()) {
2168 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(),
2169 PPCII::MO_PIC_FLAG);
2170 return getTOCEntry(DAG, SDLoc(CP), false, GA);
2174 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
2176 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
2177 return LowerLabelRef(CPIHi, CPILo, IsPIC, DAG);
2180 // For 64-bit PowerPC, prefer the more compact relative encodings.
2181 // This trades 32 bits per jump table entry for one or two instructions
2182 // on the jump site.
2183 unsigned PPCTargetLowering::getJumpTableEncoding() const {
2184 if (isJumpTableRelative())
2185 return MachineJumpTableInfo::EK_LabelDifference32;
2187 return TargetLowering::getJumpTableEncoding();
2190 bool PPCTargetLowering::isJumpTableRelative() const {
2191 if (Subtarget.isPPC64())
2193 return TargetLowering::isJumpTableRelative();
2196 SDValue PPCTargetLowering::getPICJumpTableRelocBase(SDValue Table,
2197 SelectionDAG &DAG) const {
2198 if (!Subtarget.isPPC64())
2199 return TargetLowering::getPICJumpTableRelocBase(Table, DAG);
2201 switch (getTargetMachine().getCodeModel()) {
2202 case CodeModel::Default:
2203 case CodeModel::Small:
2204 case CodeModel::Medium:
2205 return TargetLowering::getPICJumpTableRelocBase(Table, DAG);
2207 return DAG.getNode(PPCISD::GlobalBaseReg, SDLoc(),
2208 getPointerTy(DAG.getDataLayout()));
2213 PPCTargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
2215 MCContext &Ctx) const {
2216 if (!Subtarget.isPPC64())
2217 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
2219 switch (getTargetMachine().getCodeModel()) {
2220 case CodeModel::Default:
2221 case CodeModel::Small:
2222 case CodeModel::Medium:
2223 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
2225 return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
2229 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
2230 EVT PtrVT = Op.getValueType();
2231 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
2233 // 64-bit SVR4 ABI code is always position-independent.
2234 // The actual address of the GlobalValue is stored in the TOC.
2235 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
2236 setUsesTOCBasePtr(DAG);
2237 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
2238 return getTOCEntry(DAG, SDLoc(JT), true, GA);
2241 unsigned MOHiFlag, MOLoFlag;
2242 bool IsPIC = isPositionIndependent();
2243 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag);
2245 if (IsPIC && Subtarget.isSVR4ABI()) {
2246 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
2247 PPCII::MO_PIC_FLAG);
2248 return getTOCEntry(DAG, SDLoc(GA), false, GA);
2251 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
2252 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
2253 return LowerLabelRef(JTIHi, JTILo, IsPIC, DAG);
2256 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
2257 SelectionDAG &DAG) const {
2258 EVT PtrVT = Op.getValueType();
2259 BlockAddressSDNode *BASDN = cast<BlockAddressSDNode>(Op);
2260 const BlockAddress *BA = BASDN->getBlockAddress();
2262 // 64-bit SVR4 ABI code is always position-independent.
2263 // The actual BlockAddress is stored in the TOC.
2264 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
2265 setUsesTOCBasePtr(DAG);
2266 SDValue GA = DAG.getTargetBlockAddress(BA, PtrVT, BASDN->getOffset());
2267 return getTOCEntry(DAG, SDLoc(BASDN), true, GA);
2270 unsigned MOHiFlag, MOLoFlag;
2271 bool IsPIC = isPositionIndependent();
2272 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag);
2273 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
2274 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
2275 return LowerLabelRef(TgtBAHi, TgtBALo, IsPIC, DAG);
2278 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
2279 SelectionDAG &DAG) const {
2281 // FIXME: TLS addresses currently use medium model code sequences,
2282 // which is the most useful form. Eventually support for small and
2283 // large models could be added if users need it, at the cost of
2284 // additional complexity.
2285 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2286 if (DAG.getTarget().Options.EmulatedTLS)
2287 return LowerToTLSEmulatedModel(GA, DAG);
2290 const GlobalValue *GV = GA->getGlobal();
2291 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2292 bool is64bit = Subtarget.isPPC64();
2293 const Module *M = DAG.getMachineFunction().getFunction()->getParent();
2294 PICLevel::Level picLevel = M->getPICLevel();
2296 TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
2298 if (Model == TLSModel::LocalExec) {
2299 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2300 PPCII::MO_TPREL_HA);
2301 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2302 PPCII::MO_TPREL_LO);
2303 SDValue TLSReg = DAG.getRegister(is64bit ? PPC::X13 : PPC::R2,
2304 is64bit ? MVT::i64 : MVT::i32);
2305 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
2306 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
2309 if (Model == TLSModel::InitialExec) {
2310 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
2311 SDValue TGATLS = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2315 setUsesTOCBasePtr(DAG);
2316 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
2317 GOTPtr = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl,
2318 PtrVT, GOTReg, TGA);
2320 GOTPtr = DAG.getNode(PPCISD::PPC32_GOT, dl, PtrVT);
2321 SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl,
2322 PtrVT, TGA, GOTPtr);
2323 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGATLS);
2326 if (Model == TLSModel::GeneralDynamic) {
2327 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
2330 setUsesTOCBasePtr(DAG);
2331 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
2332 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
2335 if (picLevel == PICLevel::SmallPIC)
2336 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
2338 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
2340 return DAG.getNode(PPCISD::ADDI_TLSGD_L_ADDR, dl, PtrVT,
2344 if (Model == TLSModel::LocalDynamic) {
2345 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
2348 setUsesTOCBasePtr(DAG);
2349 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
2350 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
2353 if (picLevel == PICLevel::SmallPIC)
2354 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
2356 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
2358 SDValue TLSAddr = DAG.getNode(PPCISD::ADDI_TLSLD_L_ADDR, dl,
2359 PtrVT, GOTPtr, TGA, TGA);
2360 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl,
2361 PtrVT, TLSAddr, TGA);
2362 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
2365 llvm_unreachable("Unknown TLS model!");
2368 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
2369 SelectionDAG &DAG) const {
2370 EVT PtrVT = Op.getValueType();
2371 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
2373 const GlobalValue *GV = GSDN->getGlobal();
2375 // 64-bit SVR4 ABI code is always position-independent.
2376 // The actual address of the GlobalValue is stored in the TOC.
2377 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
2378 setUsesTOCBasePtr(DAG);
2379 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
2380 return getTOCEntry(DAG, DL, true, GA);
2383 unsigned MOHiFlag, MOLoFlag;
2384 bool IsPIC = isPositionIndependent();
2385 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag, GV);
2387 if (IsPIC && Subtarget.isSVR4ABI()) {
2388 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT,
2390 PPCII::MO_PIC_FLAG);
2391 return getTOCEntry(DAG, DL, false, GA);
2395 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
2397 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
2399 SDValue Ptr = LowerLabelRef(GAHi, GALo, IsPIC, DAG);
2401 // If the global reference is actually to a non-lazy-pointer, we have to do an
2402 // extra load to get the address of the global.
2403 if (MOHiFlag & PPCII::MO_NLP_FLAG)
2404 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo());
2408 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
2409 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
2412 if (Op.getValueType() == MVT::v2i64) {
2413 // When the operands themselves are v2i64 values, we need to do something
2414 // special because VSX has no underlying comparison operations for these.
2415 if (Op.getOperand(0).getValueType() == MVT::v2i64) {
2416 // Equality can be handled by casting to the legal type for Altivec
2417 // comparisons, everything else needs to be expanded.
2418 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
2419 return DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
2420 DAG.getSetCC(dl, MVT::v4i32,
2421 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0)),
2422 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(1)),
2429 // We handle most of these in the usual way.
2433 // If we're comparing for equality to zero, expose the fact that this is
2434 // implemented as a ctlz/srl pair on ppc, so that the dag combiner can
2435 // fold the new nodes.
2436 if (SDValue V = lowerCmpEqZeroToCtlzSrl(Op, DAG))
2439 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
2440 // Leave comparisons against 0 and -1 alone for now, since they're usually
2441 // optimized. FIXME: revisit this when we can custom lower all setcc
2443 if (C->isAllOnesValue() || C->isNullValue())
2447 // If we have an integer seteq/setne, turn it into a compare against zero
2448 // by xor'ing the rhs with the lhs, which is faster than setting a
2449 // condition register, reading it back out, and masking the correct bit. The
2450 // normal approach here uses sub to do this instead of xor. Using xor exposes
2451 // the result to other bit-twiddling opportunities.
2452 EVT LHSVT = Op.getOperand(0).getValueType();
2453 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
2454 EVT VT = Op.getValueType();
2455 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
2457 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, dl, LHSVT), CC);
2462 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
2463 SDNode *Node = Op.getNode();
2464 EVT VT = Node->getValueType(0);
2465 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2466 SDValue InChain = Node->getOperand(0);
2467 SDValue VAListPtr = Node->getOperand(1);
2468 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2471 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only");
2474 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
2475 VAListPtr, MachinePointerInfo(SV), MVT::i8);
2476 InChain = GprIndex.getValue(1);
2478 if (VT == MVT::i64) {
2479 // Check if GprIndex is even
2480 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
2481 DAG.getConstant(1, dl, MVT::i32));
2482 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
2483 DAG.getConstant(0, dl, MVT::i32), ISD::SETNE);
2484 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
2485 DAG.getConstant(1, dl, MVT::i32));
2486 // Align GprIndex to be even if it isn't
2487 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
2491 // fpr index is 1 byte after gpr
2492 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
2493 DAG.getConstant(1, dl, MVT::i32));
2496 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
2497 FprPtr, MachinePointerInfo(SV), MVT::i8);
2498 InChain = FprIndex.getValue(1);
2500 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
2501 DAG.getConstant(8, dl, MVT::i32));
2503 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
2504 DAG.getConstant(4, dl, MVT::i32));
2507 SDValue OverflowArea =
2508 DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr, MachinePointerInfo());
2509 InChain = OverflowArea.getValue(1);
2511 SDValue RegSaveArea =
2512 DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr, MachinePointerInfo());
2513 InChain = RegSaveArea.getValue(1);
2515 // select overflow_area if index > 8
2516 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
2517 DAG.getConstant(8, dl, MVT::i32), ISD::SETLT);
2519 // adjustment constant gpr_index * 4/8
2520 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
2521 VT.isInteger() ? GprIndex : FprIndex,
2522 DAG.getConstant(VT.isInteger() ? 4 : 8, dl,
2525 // OurReg = RegSaveArea + RegConstant
2526 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
2529 // Floating types are 32 bytes into RegSaveArea
2530 if (VT.isFloatingPoint())
2531 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
2532 DAG.getConstant(32, dl, MVT::i32));
2534 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
2535 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
2536 VT.isInteger() ? GprIndex : FprIndex,
2537 DAG.getConstant(VT == MVT::i64 ? 2 : 1, dl,
2540 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
2541 VT.isInteger() ? VAListPtr : FprPtr,
2542 MachinePointerInfo(SV), MVT::i8);
2544 // determine if we should load from reg_save_area or overflow_area
2545 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
2547 // increase overflow_area by 4/8 if gpr/fpr > 8
2548 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
2549 DAG.getConstant(VT.isInteger() ? 4 : 8,
2552 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
2555 InChain = DAG.getTruncStore(InChain, dl, OverflowArea, OverflowAreaPtr,
2556 MachinePointerInfo(), MVT::i32);
2558 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo());
2561 SDValue PPCTargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
2562 assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only");
2564 // We have to copy the entire va_list struct:
2565 // 2*sizeof(char) + 2 Byte alignment + 2*sizeof(char*) = 12 Byte
2566 return DAG.getMemcpy(Op.getOperand(0), Op,
2567 Op.getOperand(1), Op.getOperand(2),
2568 DAG.getConstant(12, SDLoc(Op), MVT::i32), 8, false, true,
2569 false, MachinePointerInfo(), MachinePointerInfo());
2572 SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
2573 SelectionDAG &DAG) const {
2574 return Op.getOperand(0);
2577 SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
2578 SelectionDAG &DAG) const {
2579 SDValue Chain = Op.getOperand(0);
2580 SDValue Trmp = Op.getOperand(1); // trampoline
2581 SDValue FPtr = Op.getOperand(2); // nested function
2582 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
2585 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2586 bool isPPC64 = (PtrVT == MVT::i64);
2587 Type *IntPtrTy = DAG.getDataLayout().getIntPtrType(*DAG.getContext());
2589 TargetLowering::ArgListTy Args;
2590 TargetLowering::ArgListEntry Entry;
2592 Entry.Ty = IntPtrTy;
2593 Entry.Node = Trmp; Args.push_back(Entry);
2595 // TrampSize == (isPPC64 ? 48 : 40);
2596 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40, dl,
2597 isPPC64 ? MVT::i64 : MVT::i32);
2598 Args.push_back(Entry);
2600 Entry.Node = FPtr; Args.push_back(Entry);
2601 Entry.Node = Nest; Args.push_back(Entry);
2603 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
2604 TargetLowering::CallLoweringInfo CLI(DAG);
2605 CLI.setDebugLoc(dl).setChain(Chain)
2606 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
2607 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
2610 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2611 return CallResult.second;
2614 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
2615 MachineFunction &MF = DAG.getMachineFunction();
2616 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2617 EVT PtrVT = getPointerTy(MF.getDataLayout());
2621 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
2622 // vastart just stores the address of the VarArgsFrameIndex slot into the
2623 // memory location argument.
2624 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2625 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2626 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
2627 MachinePointerInfo(SV));
2630 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
2631 // We suppose the given va_list is already allocated.
2634 // char gpr; /* index into the array of 8 GPRs
2635 // * stored in the register save area
2636 // * gpr=0 corresponds to r3,
2637 // * gpr=1 to r4, etc.
2639 // char fpr; /* index into the array of 8 FPRs
2640 // * stored in the register save area
2641 // * fpr=0 corresponds to f1,
2642 // * fpr=1 to f2, etc.
2644 // char *overflow_arg_area;
2645 // /* location on stack that holds
2646 // * the next overflow argument
2648 // char *reg_save_area;
2649 // /* where r3:r10 and f1:f8 (if saved)
2654 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), dl, MVT::i32);
2655 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), dl, MVT::i32);
2656 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
2658 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
2661 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
2662 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, dl, PtrVT);
2664 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
2665 SDValue ConstStackOffset = DAG.getConstant(StackOffset, dl, PtrVT);
2667 uint64_t FPROffset = 1;
2668 SDValue ConstFPROffset = DAG.getConstant(FPROffset, dl, PtrVT);
2670 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2672 // Store first byte : number of int regs
2673 SDValue firstStore =
2674 DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR, Op.getOperand(1),
2675 MachinePointerInfo(SV), MVT::i8);
2676 uint64_t nextOffset = FPROffset;
2677 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
2680 // Store second byte : number of float regs
2681 SDValue secondStore =
2682 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
2683 MachinePointerInfo(SV, nextOffset), MVT::i8);
2684 nextOffset += StackOffset;
2685 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
2687 // Store second word : arguments given on stack
2688 SDValue thirdStore = DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
2689 MachinePointerInfo(SV, nextOffset));
2690 nextOffset += FrameOffset;
2691 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
2693 // Store third word : arguments given in registers
2694 return DAG.getStore(thirdStore, dl, FR, nextPtr,
2695 MachinePointerInfo(SV, nextOffset));
2698 #include "PPCGenCallingConv.inc"
2700 // Function whose sole purpose is to kill compiler warnings
2701 // stemming from unused functions included from PPCGenCallingConv.inc.
2702 CCAssignFn *PPCTargetLowering::useFastISelCCs(unsigned Flag) const {
2703 return Flag ? CC_PPC64_ELF_FIS : RetCC_PPC64_ELF_FIS;
2706 bool llvm::CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
2707 CCValAssign::LocInfo &LocInfo,
2708 ISD::ArgFlagsTy &ArgFlags,
2713 bool llvm::CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
2715 CCValAssign::LocInfo &LocInfo,
2716 ISD::ArgFlagsTy &ArgFlags,
2718 static const MCPhysReg ArgRegs[] = {
2719 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2720 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2722 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2724 unsigned RegNum = State.getFirstUnallocated(ArgRegs);
2726 // Skip one register if the first unallocated register has an even register
2727 // number and there are still argument registers available which have not been
2728 // allocated yet. RegNum is actually an index into ArgRegs, which means we
2729 // need to skip a register if RegNum is odd.
2730 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
2731 State.AllocateReg(ArgRegs[RegNum]);
2734 // Always return false here, as this function only makes sure that the first
2735 // unallocated register has an odd register number and does not actually
2736 // allocate a register for the current argument.
2741 llvm::CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128(unsigned &ValNo, MVT &ValVT,
2743 CCValAssign::LocInfo &LocInfo,
2744 ISD::ArgFlagsTy &ArgFlags,
2746 static const MCPhysReg ArgRegs[] = {
2747 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2748 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2750 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2752 unsigned RegNum = State.getFirstUnallocated(ArgRegs);
2753 int RegsLeft = NumArgRegs - RegNum;
2755 // Skip if there is not enough registers left for long double type (4 gpr regs
2756 // in soft float mode) and put long double argument on the stack.
2757 if (RegNum != NumArgRegs && RegsLeft < 4) {
2758 for (int i = 0; i < RegsLeft; i++) {
2759 State.AllocateReg(ArgRegs[RegNum + i]);
2766 bool llvm::CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
2768 CCValAssign::LocInfo &LocInfo,
2769 ISD::ArgFlagsTy &ArgFlags,
2771 static const MCPhysReg ArgRegs[] = {
2772 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2776 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2778 unsigned RegNum = State.getFirstUnallocated(ArgRegs);
2780 // If there is only one Floating-point register left we need to put both f64
2781 // values of a split ppc_fp128 value on the stack.
2782 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
2783 State.AllocateReg(ArgRegs[RegNum]);
2786 // Always return false here, as this function only makes sure that the two f64
2787 // values a ppc_fp128 value is split into are both passed in registers or both
2788 // passed on the stack and does not actually allocate a register for the
2789 // current argument.
2793 /// FPR - The set of FP registers that should be allocated for arguments,
2795 static const MCPhysReg FPR[] = {PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5,
2796 PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10,
2797 PPC::F11, PPC::F12, PPC::F13};
2799 /// QFPR - The set of QPX registers that should be allocated for arguments.
2800 static const MCPhysReg QFPR[] = {
2801 PPC::QF1, PPC::QF2, PPC::QF3, PPC::QF4, PPC::QF5, PPC::QF6, PPC::QF7,
2802 PPC::QF8, PPC::QF9, PPC::QF10, PPC::QF11, PPC::QF12, PPC::QF13};
2804 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
2806 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
2807 unsigned PtrByteSize) {
2808 unsigned ArgSize = ArgVT.getStoreSize();
2809 if (Flags.isByVal())
2810 ArgSize = Flags.getByValSize();
2812 // Round up to multiples of the pointer size, except for array members,
2813 // which are always packed.
2814 if (!Flags.isInConsecutiveRegs())
2815 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2820 /// CalculateStackSlotAlignment - Calculates the alignment of this argument
2822 static unsigned CalculateStackSlotAlignment(EVT ArgVT, EVT OrigVT,
2823 ISD::ArgFlagsTy Flags,
2824 unsigned PtrByteSize) {
2825 unsigned Align = PtrByteSize;
2827 // Altivec parameters are padded to a 16 byte boundary.
2828 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2829 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
2830 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64 ||
2831 ArgVT == MVT::v1i128)
2833 // QPX vector types stored in double-precision are padded to a 32 byte
2835 else if (ArgVT == MVT::v4f64 || ArgVT == MVT::v4i1)
2838 // ByVal parameters are aligned as requested.
2839 if (Flags.isByVal()) {
2840 unsigned BVAlign = Flags.getByValAlign();
2841 if (BVAlign > PtrByteSize) {
2842 if (BVAlign % PtrByteSize != 0)
2844 "ByVal alignment is not a multiple of the pointer size");
2850 // Array members are always packed to their original alignment.
2851 if (Flags.isInConsecutiveRegs()) {
2852 // If the array member was split into multiple registers, the first
2853 // needs to be aligned to the size of the full type. (Except for
2854 // ppcf128, which is only aligned as its f64 components.)
2855 if (Flags.isSplit() && OrigVT != MVT::ppcf128)
2856 Align = OrigVT.getStoreSize();
2858 Align = ArgVT.getStoreSize();
2864 /// CalculateStackSlotUsed - Return whether this argument will use its
2865 /// stack slot (instead of being passed in registers). ArgOffset,
2866 /// AvailableFPRs, and AvailableVRs must hold the current argument
2867 /// position, and will be updated to account for this argument.
2868 static bool CalculateStackSlotUsed(EVT ArgVT, EVT OrigVT,
2869 ISD::ArgFlagsTy Flags,
2870 unsigned PtrByteSize,
2871 unsigned LinkageSize,
2872 unsigned ParamAreaSize,
2873 unsigned &ArgOffset,
2874 unsigned &AvailableFPRs,
2875 unsigned &AvailableVRs, bool HasQPX) {
2876 bool UseMemory = false;
2878 // Respect alignment of argument on the stack.
2880 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
2881 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
2882 // If there's no space left in the argument save area, we must
2883 // use memory (this check also catches zero-sized arguments).
2884 if (ArgOffset >= LinkageSize + ParamAreaSize)
2887 // Allocate argument on the stack.
2888 ArgOffset += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
2889 if (Flags.isInConsecutiveRegsLast())
2890 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2891 // If we overran the argument save area, we must use memory
2892 // (this check catches arguments passed partially in memory)
2893 if (ArgOffset > LinkageSize + ParamAreaSize)
2896 // However, if the argument is actually passed in an FPR or a VR,
2897 // we don't use memory after all.
2898 if (!Flags.isByVal()) {
2899 if (ArgVT == MVT::f32 || ArgVT == MVT::f64 ||
2900 // QPX registers overlap with the scalar FP registers.
2901 (HasQPX && (ArgVT == MVT::v4f32 ||
2902 ArgVT == MVT::v4f64 ||
2903 ArgVT == MVT::v4i1)))
2904 if (AvailableFPRs > 0) {
2908 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2909 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
2910 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64 ||
2911 ArgVT == MVT::v1i128)
2912 if (AvailableVRs > 0) {
2921 /// EnsureStackAlignment - Round stack frame size up from NumBytes to
2922 /// ensure minimum alignment required for target.
2923 static unsigned EnsureStackAlignment(const PPCFrameLowering *Lowering,
2924 unsigned NumBytes) {
2925 unsigned TargetAlign = Lowering->getStackAlignment();
2926 unsigned AlignMask = TargetAlign - 1;
2927 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
2931 SDValue PPCTargetLowering::LowerFormalArguments(
2932 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
2933 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
2934 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
2935 if (Subtarget.isSVR4ABI()) {
2936 if (Subtarget.isPPC64())
2937 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins,
2940 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
2943 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
2948 SDValue PPCTargetLowering::LowerFormalArguments_32SVR4(
2949 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
2950 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
2951 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
2953 // 32-bit SVR4 ABI Stack Frame Layout:
2954 // +-----------------------------------+
2955 // +--> | Back chain |
2956 // | +-----------------------------------+
2957 // | | Floating-point register save area |
2958 // | +-----------------------------------+
2959 // | | General register save area |
2960 // | +-----------------------------------+
2961 // | | CR save word |
2962 // | +-----------------------------------+
2963 // | | VRSAVE save word |
2964 // | +-----------------------------------+
2965 // | | Alignment padding |
2966 // | +-----------------------------------+
2967 // | | Vector register save area |
2968 // | +-----------------------------------+
2969 // | | Local variable space |
2970 // | +-----------------------------------+
2971 // | | Parameter list area |
2972 // | +-----------------------------------+
2973 // | | LR save word |
2974 // | +-----------------------------------+
2975 // SP--> +--- | Back chain |
2976 // +-----------------------------------+
2979 // System V Application Binary Interface PowerPC Processor Supplement
2980 // AltiVec Technology Programming Interface Manual
2982 MachineFunction &MF = DAG.getMachineFunction();
2983 MachineFrameInfo &MFI = MF.getFrameInfo();
2984 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2986 EVT PtrVT = getPointerTy(MF.getDataLayout());
2987 // Potential tail calls could cause overwriting of argument stack slots.
2988 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2989 (CallConv == CallingConv::Fast));
2990 unsigned PtrByteSize = 4;
2992 // Assign locations to all of the incoming arguments.
2993 SmallVector<CCValAssign, 16> ArgLocs;
2994 PPCCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
2997 // Reserve space for the linkage area on the stack.
2998 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
2999 CCInfo.AllocateStack(LinkageSize, PtrByteSize);
3001 CCInfo.PreAnalyzeFormalArguments(Ins);
3003 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
3004 CCInfo.clearWasPPCF128();
3006 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3007 CCValAssign &VA = ArgLocs[i];
3009 // Arguments stored in registers.
3010 if (VA.isRegLoc()) {
3011 const TargetRegisterClass *RC;
3012 EVT ValVT = VA.getValVT();
3014 switch (ValVT.getSimpleVT().SimpleTy) {
3016 llvm_unreachable("ValVT not supported by formal arguments Lowering");
3019 RC = &PPC::GPRCRegClass;
3022 if (Subtarget.hasP8Vector())
3023 RC = &PPC::VSSRCRegClass;
3025 RC = &PPC::F4RCRegClass;
3028 if (Subtarget.hasVSX())
3029 RC = &PPC::VSFRCRegClass;
3031 RC = &PPC::F8RCRegClass;
3036 RC = &PPC::VRRCRegClass;
3039 RC = Subtarget.hasQPX() ? &PPC::QSRCRegClass : &PPC::VRRCRegClass;
3043 RC = &PPC::VRRCRegClass;
3046 RC = &PPC::QFRCRegClass;
3049 RC = &PPC::QBRCRegClass;
3053 // Transform the arguments stored in physical registers into virtual ones.
3054 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
3055 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg,
3056 ValVT == MVT::i1 ? MVT::i32 : ValVT);
3058 if (ValVT == MVT::i1)
3059 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgValue);
3061 InVals.push_back(ArgValue);
3063 // Argument stored in memory.
3064 assert(VA.isMemLoc());
3066 unsigned ArgSize = VA.getLocVT().getStoreSize();
3067 int FI = MFI.CreateFixedObject(ArgSize, VA.getLocMemOffset(),
3070 // Create load nodes to retrieve arguments from the stack.
3071 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3073 DAG.getLoad(VA.getValVT(), dl, Chain, FIN, MachinePointerInfo()));
3077 // Assign locations to all of the incoming aggregate by value arguments.
3078 // Aggregates passed by value are stored in the local variable space of the
3079 // caller's stack frame, right above the parameter list area.
3080 SmallVector<CCValAssign, 16> ByValArgLocs;
3081 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3082 ByValArgLocs, *DAG.getContext());
3084 // Reserve stack space for the allocations in CCInfo.
3085 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
3087 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
3089 // Area that is at least reserved in the caller of this function.
3090 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
3091 MinReservedArea = std::max(MinReservedArea, LinkageSize);
3093 // Set the size that is at least reserved in caller of this function. Tail
3094 // call optimized function's reserved stack space needs to be aligned so that
3095 // taking the difference between two stack areas will result in an aligned
3098 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
3099 FuncInfo->setMinReservedArea(MinReservedArea);
3101 SmallVector<SDValue, 8> MemOps;
3103 // If the function takes variable number of arguments, make a frame index for
3104 // the start of the first vararg value... for expansion of llvm.va_start.
3106 static const MCPhysReg GPArgRegs[] = {
3107 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
3108 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
3110 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
3112 static const MCPhysReg FPArgRegs[] = {
3113 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
3116 unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
3121 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs));
3122 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs));
3124 // Make room for NumGPArgRegs and NumFPArgRegs.
3125 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
3126 NumFPArgRegs * MVT(MVT::f64).getSizeInBits()/8;
3128 FuncInfo->setVarArgsStackOffset(
3129 MFI.CreateFixedObject(PtrVT.getSizeInBits()/8,
3130 CCInfo.getNextStackOffset(), true));
3132 FuncInfo->setVarArgsFrameIndex(MFI.CreateStackObject(Depth, 8, false));
3133 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3135 // The fixed integer arguments of a variadic function are stored to the
3136 // VarArgsFrameIndex on the stack so that they may be loaded by
3137 // dereferencing the result of va_next.
3138 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
3139 // Get an existing live-in vreg, or add a new one.
3140 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
3142 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
3144 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3146 DAG.getStore(Val.getValue(1), dl, Val, FIN, MachinePointerInfo());
3147 MemOps.push_back(Store);
3148 // Increment the address by four for the next argument to store
3149 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, dl, PtrVT);
3150 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3153 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
3155 // The double arguments are stored to the VarArgsFrameIndex
3157 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
3158 // Get an existing live-in vreg, or add a new one.
3159 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
3161 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
3163 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
3165 DAG.getStore(Val.getValue(1), dl, Val, FIN, MachinePointerInfo());
3166 MemOps.push_back(Store);
3167 // Increment the address by eight for the next argument to store
3168 SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8, dl,
3170 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3174 if (!MemOps.empty())
3175 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3180 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
3181 // value to MVT::i64 and then truncate to the correct register size.
3182 SDValue PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags,
3183 EVT ObjectVT, SelectionDAG &DAG,
3185 const SDLoc &dl) const {
3187 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
3188 DAG.getValueType(ObjectVT));
3189 else if (Flags.isZExt())
3190 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
3191 DAG.getValueType(ObjectVT));
3193 return DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, ArgVal);
3196 SDValue PPCTargetLowering::LowerFormalArguments_64SVR4(
3197 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
3198 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
3199 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
3200 // TODO: add description of PPC stack frame format, or at least some docs.
3202 bool isELFv2ABI = Subtarget.isELFv2ABI();
3203 bool isLittleEndian = Subtarget.isLittleEndian();
3204 MachineFunction &MF = DAG.getMachineFunction();
3205 MachineFrameInfo &MFI = MF.getFrameInfo();
3206 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
3208 assert(!(CallConv == CallingConv::Fast && isVarArg) &&
3209 "fastcc not supported on varargs functions");
3211 EVT PtrVT = getPointerTy(MF.getDataLayout());
3212 // Potential tail calls could cause overwriting of argument stack slots.
3213 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
3214 (CallConv == CallingConv::Fast));
3215 unsigned PtrByteSize = 8;
3216 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
3218 static const MCPhysReg GPR[] = {
3219 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
3220 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
3222 static const MCPhysReg VR[] = {
3223 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
3224 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
3227 const unsigned Num_GPR_Regs = array_lengthof(GPR);
3228 const unsigned Num_FPR_Regs = useSoftFloat() ? 0 : 13;
3229 const unsigned Num_VR_Regs = array_lengthof(VR);
3230 const unsigned Num_QFPR_Regs = Num_FPR_Regs;
3232 // Do a first pass over the arguments to determine whether the ABI
3233 // guarantees that our caller has allocated the parameter save area
3234 // on its stack frame. In the ELFv1 ABI, this is always the case;
3235 // in the ELFv2 ABI, it is true if this is a vararg function or if
3236 // any parameter is located in a stack slot.
3238 bool HasParameterArea = !isELFv2ABI || isVarArg;
3239 unsigned ParamAreaSize = Num_GPR_Regs * PtrByteSize;
3240 unsigned NumBytes = LinkageSize;
3241 unsigned AvailableFPRs = Num_FPR_Regs;
3242 unsigned AvailableVRs = Num_VR_Regs;
3243 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3244 if (Ins[i].Flags.isNest())
3247 if (CalculateStackSlotUsed(Ins[i].VT, Ins[i].ArgVT, Ins[i].Flags,
3248 PtrByteSize, LinkageSize, ParamAreaSize,
3249 NumBytes, AvailableFPRs, AvailableVRs,
3250 Subtarget.hasQPX()))
3251 HasParameterArea = true;
3254 // Add DAG nodes to load the arguments or copy them out of registers. On
3255 // entry to a function on PPC, the arguments start after the linkage area,
3256 // although the first ones are often in registers.
3258 unsigned ArgOffset = LinkageSize;
3259 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
3260 unsigned &QFPR_idx = FPR_idx;
3261 SmallVector<SDValue, 8> MemOps;
3262 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
3263 unsigned CurArgIdx = 0;
3264 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
3266 bool needsLoad = false;
3267 EVT ObjectVT = Ins[ArgNo].VT;
3268 EVT OrigVT = Ins[ArgNo].ArgVT;
3269 unsigned ObjSize = ObjectVT.getStoreSize();
3270 unsigned ArgSize = ObjSize;
3271 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3272 if (Ins[ArgNo].isOrigArg()) {
3273 std::advance(FuncArg, Ins[ArgNo].getOrigArgIndex() - CurArgIdx);
3274 CurArgIdx = Ins[ArgNo].getOrigArgIndex();
3276 // We re-align the argument offset for each argument, except when using the
3277 // fast calling convention, when we need to make sure we do that only when
3278 // we'll actually use a stack slot.
3279 unsigned CurArgOffset, Align;
3280 auto ComputeArgOffset = [&]() {
3281 /* Respect alignment of argument on the stack. */
3282 Align = CalculateStackSlotAlignment(ObjectVT, OrigVT, Flags, PtrByteSize);
3283 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
3284 CurArgOffset = ArgOffset;
3287 if (CallConv != CallingConv::Fast) {
3290 /* Compute GPR index associated with argument offset. */
3291 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
3292 GPR_idx = std::min(GPR_idx, Num_GPR_Regs);
3295 // FIXME the codegen can be much improved in some cases.
3296 // We do not have to keep everything in memory.
3297 if (Flags.isByVal()) {
3298 assert(Ins[ArgNo].isOrigArg() && "Byval arguments cannot be implicit");
3300 if (CallConv == CallingConv::Fast)
3303 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
3304 ObjSize = Flags.getByValSize();
3305 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3306 // Empty aggregate parameters do not take up registers. Examples:
3310 // etc. However, we have to provide a place-holder in InVals, so
3311 // pretend we have an 8-byte item at the current address for that
3314 int FI = MFI.CreateFixedObject(PtrByteSize, ArgOffset, true);
3315 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3316 InVals.push_back(FIN);
3320 // Create a stack object covering all stack doublewords occupied
3321 // by the argument. If the argument is (fully or partially) on
3322 // the stack, or if the argument is fully in registers but the
3323 // caller has allocated the parameter save anyway, we can refer
3324 // directly to the caller's stack frame. Otherwise, create a
3325 // local copy in our own frame.
3327 if (HasParameterArea ||
3328 ArgSize + ArgOffset > LinkageSize + Num_GPR_Regs * PtrByteSize)
3329 FI = MFI.CreateFixedObject(ArgSize, ArgOffset, false, true);
3331 FI = MFI.CreateStackObject(ArgSize, Align, false);
3332 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3334 // Handle aggregates smaller than 8 bytes.
3335 if (ObjSize < PtrByteSize) {
3336 // The value of the object is its address, which differs from the
3337 // address of the enclosing doubleword on big-endian systems.
3339 if (!isLittleEndian) {
3340 SDValue ArgOff = DAG.getConstant(PtrByteSize - ObjSize, dl, PtrVT);
3341 Arg = DAG.getNode(ISD::ADD, dl, ArgOff.getValueType(), Arg, ArgOff);
3343 InVals.push_back(Arg);
3345 if (GPR_idx != Num_GPR_Regs) {
3346 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
3347 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3350 if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
3351 EVT ObjType = (ObjSize == 1 ? MVT::i8 :
3352 (ObjSize == 2 ? MVT::i16 : MVT::i32));
3353 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, Arg,
3354 MachinePointerInfo(&*FuncArg), ObjType);
3356 // For sizes that don't fit a truncating store (3, 5, 6, 7),
3357 // store the whole register as-is to the parameter save area
3359 Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3360 MachinePointerInfo(&*FuncArg));
3363 MemOps.push_back(Store);
3365 // Whether we copied from a register or not, advance the offset
3366 // into the parameter save area by a full doubleword.
3367 ArgOffset += PtrByteSize;
3371 // The value of the object is its address, which is the address of
3372 // its first stack doubleword.
3373 InVals.push_back(FIN);
3375 // Store whatever pieces of the object are in registers to memory.
3376 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
3377 if (GPR_idx == Num_GPR_Regs)
3380 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3381 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3384 SDValue Off = DAG.getConstant(j, dl, PtrVT);
3385 Addr = DAG.getNode(ISD::ADD, dl, Off.getValueType(), Addr, Off);
3387 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, Addr,
3388 MachinePointerInfo(&*FuncArg, j));
3389 MemOps.push_back(Store);
3392 ArgOffset += ArgSize;
3396 switch (ObjectVT.getSimpleVT().SimpleTy) {
3397 default: llvm_unreachable("Unhandled argument type!");
3401 if (Flags.isNest()) {
3402 // The 'nest' parameter, if any, is passed in R11.
3403 unsigned VReg = MF.addLiveIn(PPC::X11, &PPC::G8RCRegClass);
3404 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3406 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
3407 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
3412 // These can be scalar arguments or elements of an integer array type
3413 // passed directly. Clang may use those instead of "byval" aggregate
3414 // types to avoid forcing arguments to memory unnecessarily.
3415 if (GPR_idx != Num_GPR_Regs) {
3416 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
3417 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3419 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
3420 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
3421 // value to MVT::i64 and then truncate to the correct register size.
3422 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
3424 if (CallConv == CallingConv::Fast)
3428 ArgSize = PtrByteSize;
3430 if (CallConv != CallingConv::Fast || needsLoad)
3436 // These can be scalar arguments or elements of a float array type
3437 // passed directly. The latter are used to implement ELFv2 homogenous
3438 // float aggregates.
3439 if (FPR_idx != Num_FPR_Regs) {
3442 if (ObjectVT == MVT::f32)
3443 VReg = MF.addLiveIn(FPR[FPR_idx],
3444 Subtarget.hasP8Vector()
3445 ? &PPC::VSSRCRegClass
3446 : &PPC::F4RCRegClass);
3448 VReg = MF.addLiveIn(FPR[FPR_idx], Subtarget.hasVSX()
3449 ? &PPC::VSFRCRegClass
3450 : &PPC::F8RCRegClass);
3452 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3454 } else if (GPR_idx != Num_GPR_Regs && CallConv != CallingConv::Fast) {
3455 // FIXME: We may want to re-enable this for CallingConv::Fast on the P8
3456 // once we support fp <-> gpr moves.
3458 // This can only ever happen in the presence of f32 array types,
3459 // since otherwise we never run out of FPRs before running out
3461 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
3462 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3464 if (ObjectVT == MVT::f32) {
3465 if ((ArgOffset % PtrByteSize) == (isLittleEndian ? 4 : 0))
3466 ArgVal = DAG.getNode(ISD::SRL, dl, MVT::i64, ArgVal,
3467 DAG.getConstant(32, dl, MVT::i32));
3468 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
3471 ArgVal = DAG.getNode(ISD::BITCAST, dl, ObjectVT, ArgVal);
3473 if (CallConv == CallingConv::Fast)
3479 // When passing an array of floats, the array occupies consecutive
3480 // space in the argument area; only round up to the next doubleword
3481 // at the end of the array. Otherwise, each float takes 8 bytes.
3482 if (CallConv != CallingConv::Fast || needsLoad) {
3483 ArgSize = Flags.isInConsecutiveRegs() ? ObjSize : PtrByteSize;
3484 ArgOffset += ArgSize;
3485 if (Flags.isInConsecutiveRegsLast())
3486 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3496 if (!Subtarget.hasQPX()) {
3497 // These can be scalar arguments or elements of a vector array type
3498 // passed directly. The latter are used to implement ELFv2 homogenous
3499 // vector aggregates.
3500 if (VR_idx != Num_VR_Regs) {
3501 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
3502 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3505 if (CallConv == CallingConv::Fast)
3510 if (CallConv != CallingConv::Fast || needsLoad)
3515 assert(ObjectVT.getSimpleVT().SimpleTy == MVT::v4f32 &&
3516 "Invalid QPX parameter type");
3521 // QPX vectors are treated like their scalar floating-point subregisters
3522 // (except that they're larger).
3523 unsigned Sz = ObjectVT.getSimpleVT().SimpleTy == MVT::v4f32 ? 16 : 32;
3524 if (QFPR_idx != Num_QFPR_Regs) {
3525 const TargetRegisterClass *RC;
3526 switch (ObjectVT.getSimpleVT().SimpleTy) {
3527 case MVT::v4f64: RC = &PPC::QFRCRegClass; break;
3528 case MVT::v4f32: RC = &PPC::QSRCRegClass; break;
3529 default: RC = &PPC::QBRCRegClass; break;
3532 unsigned VReg = MF.addLiveIn(QFPR[QFPR_idx], RC);
3533 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3536 if (CallConv == CallingConv::Fast)
3540 if (CallConv != CallingConv::Fast || needsLoad)
3545 // We need to load the argument to a virtual register if we determined
3546 // above that we ran out of physical registers of the appropriate type.
3548 if (ObjSize < ArgSize && !isLittleEndian)
3549 CurArgOffset += ArgSize - ObjSize;
3550 int FI = MFI.CreateFixedObject(ObjSize, CurArgOffset, isImmutable);
3551 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3552 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo());
3555 InVals.push_back(ArgVal);
3558 // Area that is at least reserved in the caller of this function.
3559 unsigned MinReservedArea;
3560 if (HasParameterArea)
3561 MinReservedArea = std::max(ArgOffset, LinkageSize + 8 * PtrByteSize);
3563 MinReservedArea = LinkageSize;
3565 // Set the size that is at least reserved in caller of this function. Tail
3566 // call optimized functions' reserved stack space needs to be aligned so that
3567 // taking the difference between two stack areas will result in an aligned
3570 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
3571 FuncInfo->setMinReservedArea(MinReservedArea);
3573 // If the function takes variable number of arguments, make a frame index for
3574 // the start of the first vararg value... for expansion of llvm.va_start.
3576 int Depth = ArgOffset;
3578 FuncInfo->setVarArgsFrameIndex(
3579 MFI.CreateFixedObject(PtrByteSize, Depth, true));
3580 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3582 // If this function is vararg, store any remaining integer argument regs
3583 // to their spots on the stack so that they may be loaded by dereferencing
3584 // the result of va_next.
3585 for (GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
3586 GPR_idx < Num_GPR_Regs; ++GPR_idx) {
3587 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3588 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3590 DAG.getStore(Val.getValue(1), dl, Val, FIN, MachinePointerInfo());
3591 MemOps.push_back(Store);
3592 // Increment the address by four for the next argument to store
3593 SDValue PtrOff = DAG.getConstant(PtrByteSize, dl, PtrVT);
3594 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3598 if (!MemOps.empty())
3599 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3604 SDValue PPCTargetLowering::LowerFormalArguments_Darwin(
3605 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
3606 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
3607 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
3608 // TODO: add description of PPC stack frame format, or at least some docs.
3610 MachineFunction &MF = DAG.getMachineFunction();
3611 MachineFrameInfo &MFI = MF.getFrameInfo();
3612 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
3614 EVT PtrVT = getPointerTy(MF.getDataLayout());
3615 bool isPPC64 = PtrVT == MVT::i64;
3616 // Potential tail calls could cause overwriting of argument stack slots.
3617 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
3618 (CallConv == CallingConv::Fast));
3619 unsigned PtrByteSize = isPPC64 ? 8 : 4;
3620 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
3621 unsigned ArgOffset = LinkageSize;
3622 // Area that is at least reserved in caller of this function.
3623 unsigned MinReservedArea = ArgOffset;
3625 static const MCPhysReg GPR_32[] = { // 32-bit registers.
3626 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
3627 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
3629 static const MCPhysReg GPR_64[] = { // 64-bit registers.
3630 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
3631 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
3633 static const MCPhysReg VR[] = {
3634 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
3635 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
3638 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
3639 const unsigned Num_FPR_Regs = useSoftFloat() ? 0 : 13;
3640 const unsigned Num_VR_Regs = array_lengthof( VR);
3642 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
3644 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
3646 // In 32-bit non-varargs functions, the stack space for vectors is after the
3647 // stack space for non-vectors. We do not use this space unless we have
3648 // too many vectors to fit in registers, something that only occurs in
3649 // constructed examples:), but we have to walk the arglist to figure
3650 // that out...for the pathological case, compute VecArgOffset as the
3651 // start of the vector parameter area. Computing VecArgOffset is the
3652 // entire point of the following loop.
3653 unsigned VecArgOffset = ArgOffset;
3654 if (!isVarArg && !isPPC64) {
3655 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
3657 EVT ObjectVT = Ins[ArgNo].VT;
3658 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3660 if (Flags.isByVal()) {
3661 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
3662 unsigned ObjSize = Flags.getByValSize();
3664 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3665 VecArgOffset += ArgSize;
3669 switch(ObjectVT.getSimpleVT().SimpleTy) {
3670 default: llvm_unreachable("Unhandled argument type!");
3676 case MVT::i64: // PPC64
3678 // FIXME: We are guaranteed to be !isPPC64 at this point.
3679 // Does MVT::i64 apply?
3686 // Nothing to do, we're only looking at Nonvector args here.
3691 // We've found where the vector parameter area in memory is. Skip the
3692 // first 12 parameters; these don't use that memory.
3693 VecArgOffset = ((VecArgOffset+15)/16)*16;
3694 VecArgOffset += 12*16;
3696 // Add DAG nodes to load the arguments or copy them out of registers. On
3697 // entry to a function on PPC, the arguments start after the linkage area,
3698 // although the first ones are often in registers.
3700 SmallVector<SDValue, 8> MemOps;
3701 unsigned nAltivecParamsAtEnd = 0;
3702 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
3703 unsigned CurArgIdx = 0;
3704 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
3706 bool needsLoad = false;
3707 EVT ObjectVT = Ins[ArgNo].VT;
3708 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
3709 unsigned ArgSize = ObjSize;
3710 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3711 if (Ins[ArgNo].isOrigArg()) {
3712 std::advance(FuncArg, Ins[ArgNo].getOrigArgIndex() - CurArgIdx);
3713 CurArgIdx = Ins[ArgNo].getOrigArgIndex();
3715 unsigned CurArgOffset = ArgOffset;
3717 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
3718 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
3719 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
3720 if (isVarArg || isPPC64) {
3721 MinReservedArea = ((MinReservedArea+15)/16)*16;
3722 MinReservedArea += CalculateStackSlotSize(ObjectVT,
3725 } else nAltivecParamsAtEnd++;
3727 // Calculate min reserved area.
3728 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
3732 // FIXME the codegen can be much improved in some cases.
3733 // We do not have to keep everything in memory.
3734 if (Flags.isByVal()) {
3735 assert(Ins[ArgNo].isOrigArg() && "Byval arguments cannot be implicit");
3737 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
3738 ObjSize = Flags.getByValSize();
3739 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3740 // Objects of size 1 and 2 are right justified, everything else is
3741 // left justified. This means the memory address is adjusted forwards.
3742 if (ObjSize==1 || ObjSize==2) {
3743 CurArgOffset = CurArgOffset + (4 - ObjSize);
3745 // The value of the object is its address.
3746 int FI = MFI.CreateFixedObject(ObjSize, CurArgOffset, false, true);
3747 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3748 InVals.push_back(FIN);
3749 if (ObjSize==1 || ObjSize==2) {
3750 if (GPR_idx != Num_GPR_Regs) {
3753 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3755 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3756 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3757 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16;
3759 DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
3760 MachinePointerInfo(&*FuncArg), ObjType);
3761 MemOps.push_back(Store);
3765 ArgOffset += PtrByteSize;
3769 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
3770 // Store whatever pieces of the object are in registers
3771 // to memory. ArgOffset will be the address of the beginning
3773 if (GPR_idx != Num_GPR_Regs) {
3776 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3778 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3779 int FI = MFI.CreateFixedObject(PtrByteSize, ArgOffset, true);
3780 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3781 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3782 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3783 MachinePointerInfo(&*FuncArg, j));
3784 MemOps.push_back(Store);
3786 ArgOffset += PtrByteSize;
3788 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
3795 switch (ObjectVT.getSimpleVT().SimpleTy) {
3796 default: llvm_unreachable("Unhandled argument type!");
3800 if (GPR_idx != Num_GPR_Regs) {
3801 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3802 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
3804 if (ObjectVT == MVT::i1)
3805 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgVal);
3810 ArgSize = PtrByteSize;
3812 // All int arguments reserve stack space in the Darwin ABI.
3813 ArgOffset += PtrByteSize;
3817 case MVT::i64: // PPC64
3818 if (GPR_idx != Num_GPR_Regs) {
3819 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3820 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3822 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
3823 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
3824 // value to MVT::i64 and then truncate to the correct register size.
3825 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
3830 ArgSize = PtrByteSize;
3832 // All int arguments reserve stack space in the Darwin ABI.
3838 // Every 4 bytes of argument space consumes one of the GPRs available for
3839 // argument passing.
3840 if (GPR_idx != Num_GPR_Regs) {
3842 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
3845 if (FPR_idx != Num_FPR_Regs) {
3848 if (ObjectVT == MVT::f32)
3849 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
3851 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
3853 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3859 // All FP arguments reserve stack space in the Darwin ABI.
3860 ArgOffset += isPPC64 ? 8 : ObjSize;
3866 // Note that vector arguments in registers don't reserve stack space,
3867 // except in varargs functions.
3868 if (VR_idx != Num_VR_Regs) {
3869 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
3870 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3872 while ((ArgOffset % 16) != 0) {
3873 ArgOffset += PtrByteSize;
3874 if (GPR_idx != Num_GPR_Regs)
3878 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
3882 if (!isVarArg && !isPPC64) {
3883 // Vectors go after all the nonvectors.
3884 CurArgOffset = VecArgOffset;
3887 // Vectors are aligned.
3888 ArgOffset = ((ArgOffset+15)/16)*16;
3889 CurArgOffset = ArgOffset;
3897 // We need to load the argument to a virtual register if we determined above
3898 // that we ran out of physical registers of the appropriate type.
3900 int FI = MFI.CreateFixedObject(ObjSize,
3901 CurArgOffset + (ArgSize - ObjSize),
3903 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3904 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo());
3907 InVals.push_back(ArgVal);
3910 // Allow for Altivec parameters at the end, if needed.
3911 if (nAltivecParamsAtEnd) {
3912 MinReservedArea = ((MinReservedArea+15)/16)*16;
3913 MinReservedArea += 16*nAltivecParamsAtEnd;
3916 // Area that is at least reserved in the caller of this function.
3917 MinReservedArea = std::max(MinReservedArea, LinkageSize + 8 * PtrByteSize);
3919 // Set the size that is at least reserved in caller of this function. Tail
3920 // call optimized functions' reserved stack space needs to be aligned so that
3921 // taking the difference between two stack areas will result in an aligned
3924 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
3925 FuncInfo->setMinReservedArea(MinReservedArea);
3927 // If the function takes variable number of arguments, make a frame index for
3928 // the start of the first vararg value... for expansion of llvm.va_start.
3930 int Depth = ArgOffset;
3932 FuncInfo->setVarArgsFrameIndex(
3933 MFI.CreateFixedObject(PtrVT.getSizeInBits()/8,
3935 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3937 // If this function is vararg, store any remaining integer argument regs
3938 // to their spots on the stack so that they may be loaded by dereferencing
3939 // the result of va_next.
3940 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
3944 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3946 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3948 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3950 DAG.getStore(Val.getValue(1), dl, Val, FIN, MachinePointerInfo());
3951 MemOps.push_back(Store);
3952 // Increment the address by four for the next argument to store
3953 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, dl, PtrVT);
3954 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3958 if (!MemOps.empty())
3959 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3964 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
3965 /// adjusted to accommodate the arguments for the tailcall.
3966 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
3967 unsigned ParamSize) {
3969 if (!isTailCall) return 0;
3971 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
3972 unsigned CallerMinReservedArea = FI->getMinReservedArea();
3973 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
3974 // Remember only if the new adjustement is bigger.
3975 if (SPDiff < FI->getTailCallSPDelta())
3976 FI->setTailCallSPDelta(SPDiff);
3981 static bool isFunctionGlobalAddress(SDValue Callee);
3984 resideInSameModule(SDValue Callee, Reloc::Model RelMod) {
3985 // If !G, Callee can be an external symbol.
3986 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
3987 if (!G) return false;
3989 const GlobalValue *GV = G->getGlobal();
3991 if (GV->isDeclaration()) return false;
3993 switch(GV->getLinkage()) {
3994 default: llvm_unreachable("unknow linkage type");
3995 case GlobalValue::AvailableExternallyLinkage:
3996 case GlobalValue::ExternalWeakLinkage:
3999 // Callee with weak linkage is allowed if it has hidden or protected
4001 case GlobalValue::LinkOnceAnyLinkage:
4002 case GlobalValue::LinkOnceODRLinkage: // e.g. c++ inline functions
4003 case GlobalValue::WeakAnyLinkage:
4004 case GlobalValue::WeakODRLinkage: // e.g. c++ template instantiation
4005 if (GV->hasDefaultVisibility())
4008 case GlobalValue::ExternalLinkage:
4009 case GlobalValue::InternalLinkage:
4010 case GlobalValue::PrivateLinkage:
4014 // With '-fPIC', calling default visiblity function need insert 'nop' after
4015 // function call, no matter that function resides in same module or not, so
4016 // we treat it as in different module.
4017 if (RelMod == Reloc::PIC_ && GV->hasDefaultVisibility())
4024 needStackSlotPassParameters(const PPCSubtarget &Subtarget,
4025 const SmallVectorImpl<ISD::OutputArg> &Outs) {
4026 assert(Subtarget.isSVR4ABI() && Subtarget.isPPC64());
4028 const unsigned PtrByteSize = 8;
4029 const unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
4031 static const MCPhysReg GPR[] = {
4032 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4033 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4035 static const MCPhysReg VR[] = {
4036 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4037 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4040 const unsigned NumGPRs = array_lengthof(GPR);
4041 const unsigned NumFPRs = 13;
4042 const unsigned NumVRs = array_lengthof(VR);
4043 const unsigned ParamAreaSize = NumGPRs * PtrByteSize;
4045 unsigned NumBytes = LinkageSize;
4046 unsigned AvailableFPRs = NumFPRs;
4047 unsigned AvailableVRs = NumVRs;
4049 for (const ISD::OutputArg& Param : Outs) {
4050 if (Param.Flags.isNest()) continue;
4052 if (CalculateStackSlotUsed(Param.VT, Param.ArgVT, Param.Flags,
4053 PtrByteSize, LinkageSize, ParamAreaSize,
4054 NumBytes, AvailableFPRs, AvailableVRs,
4055 Subtarget.hasQPX()))
4062 hasSameArgumentList(const Function *CallerFn, ImmutableCallSite *CS) {
4063 if (CS->arg_size() != CallerFn->getArgumentList().size())
4066 ImmutableCallSite::arg_iterator CalleeArgIter = CS->arg_begin();
4067 ImmutableCallSite::arg_iterator CalleeArgEnd = CS->arg_end();
4068 Function::const_arg_iterator CallerArgIter = CallerFn->arg_begin();
4070 for (; CalleeArgIter != CalleeArgEnd; ++CalleeArgIter, ++CallerArgIter) {
4071 const Value* CalleeArg = *CalleeArgIter;
4072 const Value* CallerArg = &(*CallerArgIter);
4073 if (CalleeArg == CallerArg)
4076 // e.g. @caller([4 x i64] %a, [4 x i64] %b) {
4077 // tail call @callee([4 x i64] undef, [4 x i64] %b)
4079 // 1st argument of callee is undef and has the same type as caller.
4080 if (CalleeArg->getType() == CallerArg->getType() &&
4081 isa<UndefValue>(CalleeArg))
4091 PPCTargetLowering::IsEligibleForTailCallOptimization_64SVR4(
4093 CallingConv::ID CalleeCC,
4094 ImmutableCallSite *CS,
4096 const SmallVectorImpl<ISD::OutputArg> &Outs,
4097 const SmallVectorImpl<ISD::InputArg> &Ins,
4098 SelectionDAG& DAG) const {
4099 bool TailCallOpt = getTargetMachine().Options.GuaranteedTailCallOpt;
4101 if (DisableSCO && !TailCallOpt) return false;
4103 // Variadic argument functions are not supported.
4104 if (isVarArg) return false;
4106 MachineFunction &MF = DAG.getMachineFunction();
4107 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
4109 // Tail or Sibling call optimization (TCO/SCO) needs callee and caller has
4110 // the same calling convention
4111 if (CallerCC != CalleeCC) return false;
4113 // SCO support C calling convention
4114 if (CalleeCC != CallingConv::Fast && CalleeCC != CallingConv::C)
4117 // Caller contains any byval parameter is not supported.
4118 if (any_of(Ins, [](const ISD::InputArg &IA) { return IA.Flags.isByVal(); }))
4121 // Callee contains any byval parameter is not supported, too.
4122 // Note: This is a quick work around, because in some cases, e.g.
4123 // caller's stack size > callee's stack size, we are still able to apply
4124 // sibling call optimization. See: https://reviews.llvm.org/D23441#513574
4125 if (any_of(Outs, [](const ISD::OutputArg& OA) { return OA.Flags.isByVal(); }))
4128 // No TCO/SCO on indirect call because Caller have to restore its TOC
4129 if (!isFunctionGlobalAddress(Callee) &&
4130 !isa<ExternalSymbolSDNode>(Callee))
4133 // Check if Callee resides in the same module, because for now, PPC64 SVR4 ABI
4134 // (ELFv1/ELFv2) doesn't allow tail calls to a symbol resides in another
4136 // ref: https://bugzilla.mozilla.org/show_bug.cgi?id=973977
4137 if (!resideInSameModule(Callee, getTargetMachine().getRelocationModel()))
4140 // TCO allows altering callee ABI, so we don't have to check further.
4141 if (CalleeCC == CallingConv::Fast && TailCallOpt)
4144 if (DisableSCO) return false;
4146 // If callee use the same argument list that caller is using, then we can
4147 // apply SCO on this case. If it is not, then we need to check if callee needs
4148 // stack for passing arguments.
4149 if (!hasSameArgumentList(MF.getFunction(), CS) &&
4150 needStackSlotPassParameters(Subtarget, Outs)) {
4157 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
4158 /// for tail call optimization. Targets which want to do tail call
4159 /// optimization should implement this function.
4161 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
4162 CallingConv::ID CalleeCC,
4164 const SmallVectorImpl<ISD::InputArg> &Ins,
4165 SelectionDAG& DAG) const {
4166 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
4169 // Variable argument functions are not supported.
4173 MachineFunction &MF = DAG.getMachineFunction();
4174 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
4175 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
4176 // Functions containing by val parameters are not supported.
4177 for (unsigned i = 0; i != Ins.size(); i++) {
4178 ISD::ArgFlagsTy Flags = Ins[i].Flags;
4179 if (Flags.isByVal()) return false;
4182 // Non-PIC/GOT tail calls are supported.
4183 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
4186 // At the moment we can only do local tail calls (in same module, hidden
4187 // or protected) if we are generating PIC.
4188 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
4189 return G->getGlobal()->hasHiddenVisibility()
4190 || G->getGlobal()->hasProtectedVisibility();
4196 /// isCallCompatibleAddress - Return the immediate to use if the specified
4197 /// 32-bit value is representable in the immediate field of a BxA instruction.
4198 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
4199 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
4200 if (!C) return nullptr;
4202 int Addr = C->getZExtValue();
4203 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
4204 SignExtend32<26>(Addr) != Addr)
4205 return nullptr; // Top 6 bits have to be sext of immediate.
4209 (int)C->getZExtValue() >> 2, SDLoc(Op),
4210 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout()))
4216 struct TailCallArgumentInfo {
4221 TailCallArgumentInfo() : FrameIdx(0) {}
4225 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
4226 static void StoreTailCallArgumentsToStackSlot(
4227 SelectionDAG &DAG, SDValue Chain,
4228 const SmallVectorImpl<TailCallArgumentInfo> &TailCallArgs,
4229 SmallVectorImpl<SDValue> &MemOpChains, const SDLoc &dl) {
4230 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
4231 SDValue Arg = TailCallArgs[i].Arg;
4232 SDValue FIN = TailCallArgs[i].FrameIdxOp;
4233 int FI = TailCallArgs[i].FrameIdx;
4234 // Store relative to framepointer.
4235 MemOpChains.push_back(DAG.getStore(
4236 Chain, dl, Arg, FIN,
4237 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI)));
4241 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
4242 /// the appropriate stack slot for the tail call optimized function call.
4243 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG, SDValue Chain,
4244 SDValue OldRetAddr, SDValue OldFP,
4245 int SPDiff, const SDLoc &dl) {
4247 // Calculate the new stack slot for the return address.
4248 MachineFunction &MF = DAG.getMachineFunction();
4249 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
4250 const PPCFrameLowering *FL = Subtarget.getFrameLowering();
4251 bool isPPC64 = Subtarget.isPPC64();
4252 int SlotSize = isPPC64 ? 8 : 4;
4253 int NewRetAddrLoc = SPDiff + FL->getReturnSaveOffset();
4254 int NewRetAddr = MF.getFrameInfo().CreateFixedObject(SlotSize,
4255 NewRetAddrLoc, true);
4256 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
4257 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
4258 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
4259 MachinePointerInfo::getFixedStack(MF, NewRetAddr));
4261 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
4262 // slot as the FP is never overwritten.
4263 if (Subtarget.isDarwinABI()) {
4264 int NewFPLoc = SPDiff + FL->getFramePointerSaveOffset();
4265 int NewFPIdx = MF.getFrameInfo().CreateFixedObject(SlotSize, NewFPLoc,
4267 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
4268 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
4269 MachinePointerInfo::getFixedStack(
4270 DAG.getMachineFunction(), NewFPIdx));
4276 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
4277 /// the position of the argument.
4279 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
4280 SDValue Arg, int SPDiff, unsigned ArgOffset,
4281 SmallVectorImpl<TailCallArgumentInfo>& TailCallArguments) {
4282 int Offset = ArgOffset + SPDiff;
4283 uint32_t OpSize = (Arg.getValueSizeInBits() + 7) / 8;
4284 int FI = MF.getFrameInfo().CreateFixedObject(OpSize, Offset, true);
4285 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
4286 SDValue FIN = DAG.getFrameIndex(FI, VT);
4287 TailCallArgumentInfo Info;
4289 Info.FrameIdxOp = FIN;
4291 TailCallArguments.push_back(Info);
4294 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
4295 /// stack slot. Returns the chain as result and the loaded frame pointers in
4296 /// LROpOut/FPOpout. Used when tail calling.
4297 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(
4298 SelectionDAG &DAG, int SPDiff, SDValue Chain, SDValue &LROpOut,
4299 SDValue &FPOpOut, const SDLoc &dl) const {
4301 // Load the LR and FP stack slot for later adjusting.
4302 EVT VT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
4303 LROpOut = getReturnAddrFrameIndex(DAG);
4304 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo());
4305 Chain = SDValue(LROpOut.getNode(), 1);
4307 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
4308 // slot as the FP is never overwritten.
4309 if (Subtarget.isDarwinABI()) {
4310 FPOpOut = getFramePointerFrameIndex(DAG);
4311 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo());
4312 Chain = SDValue(FPOpOut.getNode(), 1);
4318 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
4319 /// by "Src" to address "Dst" of size "Size". Alignment information is
4320 /// specified by the specific parameter attribute. The copy will be passed as
4321 /// a byval function parameter.
4322 /// Sometimes what we are copying is the end of a larger object, the part that
4323 /// does not fit in registers.
4324 static SDValue CreateCopyOfByValArgument(SDValue Src, SDValue Dst,
4325 SDValue Chain, ISD::ArgFlagsTy Flags,
4326 SelectionDAG &DAG, const SDLoc &dl) {
4327 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
4328 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
4329 false, false, false, MachinePointerInfo(),
4330 MachinePointerInfo());
4333 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
4335 static void LowerMemOpCallTo(
4336 SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, SDValue Arg,
4337 SDValue PtrOff, int SPDiff, unsigned ArgOffset, bool isPPC64,
4338 bool isTailCall, bool isVector, SmallVectorImpl<SDValue> &MemOpChains,
4339 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments, const SDLoc &dl) {
4340 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
4345 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4347 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4348 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4349 DAG.getConstant(ArgOffset, dl, PtrVT));
4351 MemOpChains.push_back(
4352 DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo()));
4353 // Calculate and remember argument location.
4354 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
4359 PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
4360 const SDLoc &dl, int SPDiff, unsigned NumBytes, SDValue LROp,
4362 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments) {
4363 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
4364 // might overwrite each other in case of tail call optimization.
4365 SmallVector<SDValue, 8> MemOpChains2;
4366 // Do not flag preceding copytoreg stuff together with the following stuff.
4368 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
4370 if (!MemOpChains2.empty())
4371 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
4373 // Store the return address to the appropriate stack slot.
4374 Chain = EmitTailCallStoreFPAndRetAddr(DAG, Chain, LROp, FPOp, SPDiff, dl);
4376 // Emit callseq_end just before tailcall node.
4377 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
4378 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
4379 InFlag = Chain.getValue(1);
4382 // Is this global address that of a function that can be called by name? (as
4383 // opposed to something that must hold a descriptor for an indirect call).
4384 static bool isFunctionGlobalAddress(SDValue Callee) {
4385 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
4386 if (Callee.getOpcode() == ISD::GlobalTLSAddress ||
4387 Callee.getOpcode() == ISD::TargetGlobalTLSAddress)
4390 return G->getGlobal()->getValueType()->isFunctionTy();
4397 PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag, SDValue &Chain,
4398 SDValue CallSeqStart, const SDLoc &dl, int SPDiff, bool isTailCall,
4399 bool isPatchPoint, bool hasNest,
4400 SmallVectorImpl<std::pair<unsigned, SDValue>> &RegsToPass,
4401 SmallVectorImpl<SDValue> &Ops, std::vector<EVT> &NodeTys,
4402 ImmutableCallSite *CS, const PPCSubtarget &Subtarget) {
4404 bool isPPC64 = Subtarget.isPPC64();
4405 bool isSVR4ABI = Subtarget.isSVR4ABI();
4406 bool isELFv2ABI = Subtarget.isELFv2ABI();
4408 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
4409 NodeTys.push_back(MVT::Other); // Returns a chain
4410 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
4412 unsigned CallOpc = PPCISD::CALL;
4414 bool needIndirectCall = true;
4415 if (!isSVR4ABI || !isPPC64)
4416 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) {
4417 // If this is an absolute destination address, use the munged value.
4418 Callee = SDValue(Dest, 0);
4419 needIndirectCall = false;
4422 // PC-relative references to external symbols should go through $stub, unless
4423 // we're building with the leopard linker or later, which automatically
4424 // synthesizes these stubs.
4425 const TargetMachine &TM = DAG.getTarget();
4426 const Module *Mod = DAG.getMachineFunction().getFunction()->getParent();
4427 const GlobalValue *GV = nullptr;
4428 if (auto *G = dyn_cast<GlobalAddressSDNode>(Callee))
4429 GV = G->getGlobal();
4430 bool Local = TM.shouldAssumeDSOLocal(*Mod, GV);
4431 bool UsePlt = !Local && Subtarget.isTargetELF() && !isPPC64;
4433 if (isFunctionGlobalAddress(Callee)) {
4434 GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Callee);
4435 // A call to a TLS address is actually an indirect call to a
4436 // thread-specific pointer.
4437 unsigned OpFlags = 0;
4439 OpFlags = PPCII::MO_PLT;
4441 // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
4442 // every direct call is) turn it into a TargetGlobalAddress /
4443 // TargetExternalSymbol node so that legalize doesn't hack it.
4444 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
4445 Callee.getValueType(), 0, OpFlags);
4446 needIndirectCall = false;
4449 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
4450 unsigned char OpFlags = 0;
4453 OpFlags = PPCII::MO_PLT;
4455 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
4457 needIndirectCall = false;
4461 // We'll form an invalid direct call when lowering a patchpoint; the full
4462 // sequence for an indirect call is complicated, and many of the
4463 // instructions introduced might have side effects (and, thus, can't be
4464 // removed later). The call itself will be removed as soon as the
4465 // argument/return lowering is complete, so the fact that it has the wrong
4466 // kind of operands should not really matter.
4467 needIndirectCall = false;
4470 if (needIndirectCall) {
4471 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
4472 // to do the call, we can't use PPCISD::CALL.
4473 SDValue MTCTROps[] = {Chain, Callee, InFlag};
4475 if (isSVR4ABI && isPPC64 && !isELFv2ABI) {
4476 // Function pointers in the 64-bit SVR4 ABI do not point to the function
4477 // entry point, but to the function descriptor (the function entry point
4478 // address is part of the function descriptor though).
4479 // The function descriptor is a three doubleword structure with the
4480 // following fields: function entry point, TOC base address and
4481 // environment pointer.
4482 // Thus for a call through a function pointer, the following actions need
4484 // 1. Save the TOC of the caller in the TOC save area of its stack
4485 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()).
4486 // 2. Load the address of the function entry point from the function
4488 // 3. Load the TOC of the callee from the function descriptor into r2.
4489 // 4. Load the environment pointer from the function descriptor into
4491 // 5. Branch to the function entry point address.
4492 // 6. On return of the callee, the TOC of the caller needs to be
4493 // restored (this is done in FinishCall()).
4495 // The loads are scheduled at the beginning of the call sequence, and the
4496 // register copies are flagged together to ensure that no other
4497 // operations can be scheduled in between. E.g. without flagging the
4498 // copies together, a TOC access in the caller could be scheduled between
4499 // the assignment of the callee TOC and the branch to the callee, which
4500 // results in the TOC access going through the TOC of the callee instead
4501 // of going through the TOC of the caller, which leads to incorrect code.
4503 // Load the address of the function entry point from the function
4505 SDValue LDChain = CallSeqStart.getValue(CallSeqStart->getNumValues()-1);
4506 if (LDChain.getValueType() == MVT::Glue)
4507 LDChain = CallSeqStart.getValue(CallSeqStart->getNumValues()-2);
4509 auto MMOFlags = Subtarget.hasInvariantFunctionDescriptors()
4510 ? (MachineMemOperand::MODereferenceable |
4511 MachineMemOperand::MOInvariant)
4512 : MachineMemOperand::MONone;
4514 MachinePointerInfo MPI(CS ? CS->getCalledValue() : nullptr);
4515 SDValue LoadFuncPtr = DAG.getLoad(MVT::i64, dl, LDChain, Callee, MPI,
4516 /* Alignment = */ 8, MMOFlags);
4518 // Load environment pointer into r11.
4519 SDValue PtrOff = DAG.getIntPtrConstant(16, dl);
4520 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
4521 SDValue LoadEnvPtr =
4522 DAG.getLoad(MVT::i64, dl, LDChain, AddPtr, MPI.getWithOffset(16),
4523 /* Alignment = */ 8, MMOFlags);
4525 SDValue TOCOff = DAG.getIntPtrConstant(8, dl);
4526 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, TOCOff);
4528 DAG.getLoad(MVT::i64, dl, LDChain, AddTOC, MPI.getWithOffset(8),
4529 /* Alignment = */ 8, MMOFlags);
4531 setUsesTOCBasePtr(DAG);
4532 SDValue TOCVal = DAG.getCopyToReg(Chain, dl, PPC::X2, TOCPtr,
4534 Chain = TOCVal.getValue(0);
4535 InFlag = TOCVal.getValue(1);
4537 // If the function call has an explicit 'nest' parameter, it takes the
4538 // place of the environment pointer.
4540 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
4543 Chain = EnvVal.getValue(0);
4544 InFlag = EnvVal.getValue(1);
4547 MTCTROps[0] = Chain;
4548 MTCTROps[1] = LoadFuncPtr;
4549 MTCTROps[2] = InFlag;
4552 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys,
4553 makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
4554 InFlag = Chain.getValue(1);
4557 NodeTys.push_back(MVT::Other);
4558 NodeTys.push_back(MVT::Glue);
4559 Ops.push_back(Chain);
4560 CallOpc = PPCISD::BCTRL;
4561 Callee.setNode(nullptr);
4562 // Add use of X11 (holding environment pointer)
4563 if (isSVR4ABI && isPPC64 && !isELFv2ABI && !hasNest)
4564 Ops.push_back(DAG.getRegister(PPC::X11, PtrVT));
4565 // Add CTR register as callee so a bctr can be emitted later.
4567 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT));
4570 // If this is a direct call, pass the chain and the callee.
4571 if (Callee.getNode()) {
4572 Ops.push_back(Chain);
4573 Ops.push_back(Callee);
4575 // If this is a tail call add stack pointer delta.
4577 Ops.push_back(DAG.getConstant(SPDiff, dl, MVT::i32));
4579 // Add argument registers to the end of the list so that they are known live
4581 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
4582 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
4583 RegsToPass[i].second.getValueType()));
4585 // All calls, in both the ELF V1 and V2 ABIs, need the TOC register live
4587 if (isSVR4ABI && isPPC64 && !isPatchPoint) {
4588 setUsesTOCBasePtr(DAG);
4589 Ops.push_back(DAG.getRegister(PPC::X2, PtrVT));
4596 bool isLocalCall(const SDValue &Callee)
4598 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
4599 return G->getGlobal()->isStrongDefinitionForLinker();
4603 SDValue PPCTargetLowering::LowerCallResult(
4604 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
4605 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
4606 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
4608 SmallVector<CCValAssign, 16> RVLocs;
4609 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
4611 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
4613 // Copy all of the result registers out of their specified physreg.
4614 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
4615 CCValAssign &VA = RVLocs[i];
4616 assert(VA.isRegLoc() && "Can only return in registers!");
4618 SDValue Val = DAG.getCopyFromReg(Chain, dl,
4619 VA.getLocReg(), VA.getLocVT(), InFlag);
4620 Chain = Val.getValue(1);
4621 InFlag = Val.getValue(2);
4623 switch (VA.getLocInfo()) {
4624 default: llvm_unreachable("Unknown loc info!");
4625 case CCValAssign::Full: break;
4626 case CCValAssign::AExt:
4627 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
4629 case CCValAssign::ZExt:
4630 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
4631 DAG.getValueType(VA.getValVT()));
4632 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
4634 case CCValAssign::SExt:
4635 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
4636 DAG.getValueType(VA.getValVT()));
4637 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
4641 InVals.push_back(Val);
4647 SDValue PPCTargetLowering::FinishCall(
4648 CallingConv::ID CallConv, const SDLoc &dl, bool isTailCall, bool isVarArg,
4649 bool isPatchPoint, bool hasNest, SelectionDAG &DAG,
4650 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass, SDValue InFlag,
4651 SDValue Chain, SDValue CallSeqStart, SDValue &Callee, int SPDiff,
4652 unsigned NumBytes, const SmallVectorImpl<ISD::InputArg> &Ins,
4653 SmallVectorImpl<SDValue> &InVals, ImmutableCallSite *CS) const {
4655 std::vector<EVT> NodeTys;
4656 SmallVector<SDValue, 8> Ops;
4657 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, CallSeqStart, dl,
4658 SPDiff, isTailCall, isPatchPoint, hasNest,
4659 RegsToPass, Ops, NodeTys, CS, Subtarget);
4661 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
4662 if (isVarArg && Subtarget.isSVR4ABI() && !Subtarget.isPPC64())
4663 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
4665 // When performing tail call optimization the callee pops its arguments off
4666 // the stack. Account for this here so these bytes can be pushed back on in
4667 // PPCFrameLowering::eliminateCallFramePseudoInstr.
4668 int BytesCalleePops =
4669 (CallConv == CallingConv::Fast &&
4670 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0;
4672 // Add a register mask operand representing the call-preserved registers.
4673 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
4674 const uint32_t *Mask =
4675 TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv);
4676 assert(Mask && "Missing call preserved mask for calling convention");
4677 Ops.push_back(DAG.getRegisterMask(Mask));
4679 if (InFlag.getNode())
4680 Ops.push_back(InFlag);
4684 assert(((Callee.getOpcode() == ISD::Register &&
4685 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
4686 Callee.getOpcode() == ISD::TargetExternalSymbol ||
4687 Callee.getOpcode() == ISD::TargetGlobalAddress ||
4688 isa<ConstantSDNode>(Callee)) &&
4689 "Expecting an global address, external symbol, absolute value or register");
4691 DAG.getMachineFunction().getFrameInfo().setHasTailCall();
4692 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, Ops);
4695 // Add a NOP immediately after the branch instruction when using the 64-bit
4696 // SVR4 ABI. At link time, if caller and callee are in a different module and
4697 // thus have a different TOC, the call will be replaced with a call to a stub
4698 // function which saves the current TOC, loads the TOC of the callee and
4699 // branches to the callee. The NOP will be replaced with a load instruction
4700 // which restores the TOC of the caller from the TOC save slot of the current
4701 // stack frame. If caller and callee belong to the same module (and have the
4702 // same TOC), the NOP will remain unchanged.
4704 if (!isTailCall && Subtarget.isSVR4ABI()&& Subtarget.isPPC64() &&
4706 if (CallOpc == PPCISD::BCTRL) {
4707 // This is a call through a function pointer.
4708 // Restore the caller TOC from the save area into R2.
4709 // See PrepareCall() for more information about calls through function
4710 // pointers in the 64-bit SVR4 ABI.
4711 // We are using a target-specific load with r2 hard coded, because the
4712 // result of a target-independent load would never go directly into r2,
4713 // since r2 is a reserved register (which prevents the register allocator
4714 // from allocating it), resulting in an additional register being
4715 // allocated and an unnecessary move instruction being generated.
4716 CallOpc = PPCISD::BCTRL_LOAD_TOC;
4718 EVT PtrVT = getPointerTy(DAG.getDataLayout());
4719 SDValue StackPtr = DAG.getRegister(PPC::X1, PtrVT);
4720 unsigned TOCSaveOffset = Subtarget.getFrameLowering()->getTOCSaveOffset();
4721 SDValue TOCOff = DAG.getIntPtrConstant(TOCSaveOffset, dl);
4722 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, StackPtr, TOCOff);
4724 // The address needs to go after the chain input but before the flag (or
4725 // any other variadic arguments).
4726 Ops.insert(std::next(Ops.begin()), AddTOC);
4727 } else if ((CallOpc == PPCISD::CALL) &&
4728 (!isLocalCall(Callee) ||
4729 DAG.getTarget().getRelocationModel() == Reloc::PIC_))
4730 // Otherwise insert NOP for non-local calls.
4731 CallOpc = PPCISD::CALL_NOP;
4734 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
4735 InFlag = Chain.getValue(1);
4737 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
4738 DAG.getIntPtrConstant(BytesCalleePops, dl, true),
4741 InFlag = Chain.getValue(1);
4743 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
4744 Ins, dl, DAG, InVals);
4748 PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
4749 SmallVectorImpl<SDValue> &InVals) const {
4750 SelectionDAG &DAG = CLI.DAG;
4752 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
4753 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
4754 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
4755 SDValue Chain = CLI.Chain;
4756 SDValue Callee = CLI.Callee;
4757 bool &isTailCall = CLI.IsTailCall;
4758 CallingConv::ID CallConv = CLI.CallConv;
4759 bool isVarArg = CLI.IsVarArg;
4760 bool isPatchPoint = CLI.IsPatchPoint;
4761 ImmutableCallSite *CS = CLI.CS;
4764 if (Subtarget.useLongCalls() && !(CS && CS->isMustTailCall()))
4766 else if (Subtarget.isSVR4ABI() && Subtarget.isPPC64())
4768 IsEligibleForTailCallOptimization_64SVR4(Callee, CallConv, CS,
4769 isVarArg, Outs, Ins, DAG);
4771 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
4775 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
4778 assert(isa<GlobalAddressSDNode>(Callee) &&
4779 "Callee should be an llvm::Function object.");
4781 const GlobalValue *GV = cast<GlobalAddressSDNode>(Callee)->getGlobal();
4782 const unsigned Width = 80 - strlen("TCO caller: ")
4783 - strlen(", callee linkage: 0, 0");
4784 dbgs() << "TCO caller: "
4785 << left_justify(DAG.getMachineFunction().getName(), Width)
4786 << ", callee linkage: "
4787 << GV->getVisibility() << ", " << GV->getLinkage() << "\n"
4792 if (!isTailCall && CS && CS->isMustTailCall())
4793 report_fatal_error("failed to perform tail call elimination on a call "
4794 "site marked musttail");
4796 // When long calls (i.e. indirect calls) are always used, calls are always
4797 // made via function pointer. If we have a function name, first translate it
4799 if (Subtarget.useLongCalls() && isa<GlobalAddressSDNode>(Callee) &&
4801 Callee = LowerGlobalAddress(Callee, DAG);
4803 if (Subtarget.isSVR4ABI()) {
4804 if (Subtarget.isPPC64())
4805 return LowerCall_64SVR4(Chain, Callee, CallConv, isVarArg,
4806 isTailCall, isPatchPoint, Outs, OutVals, Ins,
4807 dl, DAG, InVals, CS);
4809 return LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg,
4810 isTailCall, isPatchPoint, Outs, OutVals, Ins,
4811 dl, DAG, InVals, CS);
4814 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
4815 isTailCall, isPatchPoint, Outs, OutVals, Ins,
4816 dl, DAG, InVals, CS);
4819 SDValue PPCTargetLowering::LowerCall_32SVR4(
4820 SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg,
4821 bool isTailCall, bool isPatchPoint,
4822 const SmallVectorImpl<ISD::OutputArg> &Outs,
4823 const SmallVectorImpl<SDValue> &OutVals,
4824 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
4825 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
4826 ImmutableCallSite *CS) const {
4827 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description
4828 // of the 32-bit SVR4 ABI stack frame layout.
4830 assert((CallConv == CallingConv::C ||
4831 CallConv == CallingConv::Fast) && "Unknown calling convention!");
4833 unsigned PtrByteSize = 4;
4835 MachineFunction &MF = DAG.getMachineFunction();
4837 // Mark this function as potentially containing a function that contains a
4838 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4839 // and restoring the callers stack pointer in this functions epilog. This is
4840 // done because by tail calling the called function might overwrite the value
4841 // in this function's (MF) stack pointer stack slot 0(SP).
4842 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4843 CallConv == CallingConv::Fast)
4844 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4846 // Count how many bytes are to be pushed on the stack, including the linkage
4847 // area, parameter list area and the part of the local variable space which
4848 // contains copies of aggregates which are passed by value.
4850 // Assign locations to all of the outgoing arguments.
4851 SmallVector<CCValAssign, 16> ArgLocs;
4852 PPCCCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
4854 // Reserve space for the linkage area on the stack.
4855 CCInfo.AllocateStack(Subtarget.getFrameLowering()->getLinkageSize(),
4858 CCInfo.PreAnalyzeCallOperands(Outs);
4861 // Handle fixed and variable vector arguments differently.
4862 // Fixed vector arguments go into registers as long as registers are
4863 // available. Variable vector arguments always go into memory.
4864 unsigned NumArgs = Outs.size();
4866 for (unsigned i = 0; i != NumArgs; ++i) {
4867 MVT ArgVT = Outs[i].VT;
4868 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
4871 if (Outs[i].IsFixed) {
4872 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
4875 Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
4881 errs() << "Call operand #" << i << " has unhandled type "
4882 << EVT(ArgVT).getEVTString() << "\n";
4884 llvm_unreachable(nullptr);
4888 // All arguments are treated the same.
4889 CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4);
4891 CCInfo.clearWasPPCF128();
4893 // Assign locations to all of the outgoing aggregate by value arguments.
4894 SmallVector<CCValAssign, 16> ByValArgLocs;
4895 CCState CCByValInfo(CallConv, isVarArg, MF, ByValArgLocs, *DAG.getContext());
4897 // Reserve stack space for the allocations in CCInfo.
4898 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
4900 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal);
4902 // Size of the linkage area, parameter list area and the part of the local
4903 // space variable where copies of aggregates which are passed by value are
4905 unsigned NumBytes = CCByValInfo.getNextStackOffset();
4907 // Calculate by how many bytes the stack has to be adjusted in case of tail
4908 // call optimization.
4909 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4911 // Adjust the stack pointer for the new arguments...
4912 // These operations are automatically eliminated by the prolog/epilog pass
4913 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
4915 SDValue CallSeqStart = Chain;
4917 // Load the return address and frame pointer so it can be moved somewhere else
4920 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, dl);
4922 // Set up a copy of the stack pointer for use loading and storing any
4923 // arguments that may not fit in the registers available for argument
4925 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4927 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4928 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4929 SmallVector<SDValue, 8> MemOpChains;
4931 bool seenFloatArg = false;
4932 // Walk the register/memloc assignments, inserting copies/loads.
4933 for (unsigned i = 0, j = 0, e = ArgLocs.size();
4936 CCValAssign &VA = ArgLocs[i];
4937 SDValue Arg = OutVals[i];
4938 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4940 if (Flags.isByVal()) {
4941 // Argument is an aggregate which is passed by value, thus we need to
4942 // create a copy of it in the local variable space of the current stack
4943 // frame (which is the stack frame of the caller) and pass the address of
4944 // this copy to the callee.
4945 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
4946 CCValAssign &ByValVA = ByValArgLocs[j++];
4947 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
4949 // Memory reserved in the local variable space of the callers stack frame.
4950 unsigned LocMemOffset = ByValVA.getLocMemOffset();
4952 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
4953 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(MF.getDataLayout()),
4956 // Create a copy of the argument in the local area of the current
4958 SDValue MemcpyCall =
4959 CreateCopyOfByValArgument(Arg, PtrOff,
4960 CallSeqStart.getNode()->getOperand(0),
4963 // This must go outside the CALLSEQ_START..END.
4964 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
4965 CallSeqStart.getNode()->getOperand(1),
4967 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
4968 NewCallSeqStart.getNode());
4969 Chain = CallSeqStart = NewCallSeqStart;
4971 // Pass the address of the aggregate copy on the stack either in a
4972 // physical register or in the parameter list area of the current stack
4973 // frame to the callee.
4977 if (VA.isRegLoc()) {
4978 if (Arg.getValueType() == MVT::i1)
4979 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Arg);
4981 seenFloatArg |= VA.getLocVT().isFloatingPoint();
4982 // Put argument in a physical register.
4983 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
4985 // Put argument in the parameter list area of the current stack frame.
4986 assert(VA.isMemLoc());
4987 unsigned LocMemOffset = VA.getLocMemOffset();
4990 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
4991 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(MF.getDataLayout()),
4994 MemOpChains.push_back(
4995 DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo()));
4997 // Calculate and remember argument location.
4998 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
5004 if (!MemOpChains.empty())
5005 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
5007 // Build a sequence of copy-to-reg nodes chained together with token chain
5008 // and flag operands which copy the outgoing args into the appropriate regs.
5010 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
5011 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
5012 RegsToPass[i].second, InFlag);
5013 InFlag = Chain.getValue(1);
5016 // Set CR bit 6 to true if this is a vararg call with floating args passed in
5019 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
5020 SDValue Ops[] = { Chain, InFlag };
5022 Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
5023 dl, VTs, makeArrayRef(Ops, InFlag.getNode() ? 2 : 1));
5025 InFlag = Chain.getValue(1);
5029 PrepareTailCall(DAG, InFlag, Chain, dl, SPDiff, NumBytes, LROp, FPOp,
5032 return FinishCall(CallConv, dl, isTailCall, isVarArg, isPatchPoint,
5033 /* unused except on PPC64 ELFv1 */ false, DAG,
5034 RegsToPass, InFlag, Chain, CallSeqStart, Callee, SPDiff,
5035 NumBytes, Ins, InVals, CS);
5038 // Copy an argument into memory, being careful to do this outside the
5039 // call sequence for the call to which the argument belongs.
5040 SDValue PPCTargetLowering::createMemcpyOutsideCallSeq(
5041 SDValue Arg, SDValue PtrOff, SDValue CallSeqStart, ISD::ArgFlagsTy Flags,
5042 SelectionDAG &DAG, const SDLoc &dl) const {
5043 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
5044 CallSeqStart.getNode()->getOperand(0),
5046 // The MEMCPY must go outside the CALLSEQ_START..END.
5047 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
5048 CallSeqStart.getNode()->getOperand(1),
5050 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
5051 NewCallSeqStart.getNode());
5052 return NewCallSeqStart;
5055 SDValue PPCTargetLowering::LowerCall_64SVR4(
5056 SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg,
5057 bool isTailCall, bool isPatchPoint,
5058 const SmallVectorImpl<ISD::OutputArg> &Outs,
5059 const SmallVectorImpl<SDValue> &OutVals,
5060 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
5061 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
5062 ImmutableCallSite *CS) const {
5064 bool isELFv2ABI = Subtarget.isELFv2ABI();
5065 bool isLittleEndian = Subtarget.isLittleEndian();
5066 unsigned NumOps = Outs.size();
5067 bool hasNest = false;
5068 bool IsSibCall = false;
5070 EVT PtrVT = getPointerTy(DAG.getDataLayout());
5071 unsigned PtrByteSize = 8;
5073 MachineFunction &MF = DAG.getMachineFunction();
5075 if (isTailCall && !getTargetMachine().Options.GuaranteedTailCallOpt)
5078 // Mark this function as potentially containing a function that contains a
5079 // tail call. As a consequence the frame pointer will be used for dynamicalloc
5080 // and restoring the callers stack pointer in this functions epilog. This is
5081 // done because by tail calling the called function might overwrite the value
5082 // in this function's (MF) stack pointer stack slot 0(SP).
5083 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
5084 CallConv == CallingConv::Fast)
5085 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
5087 assert(!(CallConv == CallingConv::Fast && isVarArg) &&
5088 "fastcc not supported on varargs functions");
5090 // Count how many bytes are to be pushed on the stack, including the linkage
5091 // area, and parameter passing area. On ELFv1, the linkage area is 48 bytes
5092 // reserved space for [SP][CR][LR][2 x unused][TOC]; on ELFv2, the linkage
5093 // area is 32 bytes reserved space for [SP][CR][LR][TOC].
5094 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
5095 unsigned NumBytes = LinkageSize;
5096 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
5097 unsigned &QFPR_idx = FPR_idx;
5099 static const MCPhysReg GPR[] = {
5100 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
5101 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
5103 static const MCPhysReg VR[] = {
5104 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
5105 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
5108 const unsigned NumGPRs = array_lengthof(GPR);
5109 const unsigned NumFPRs = 13;
5110 const unsigned NumVRs = array_lengthof(VR);
5111 const unsigned NumQFPRs = NumFPRs;
5113 // When using the fast calling convention, we don't provide backing for
5114 // arguments that will be in registers.
5115 unsigned NumGPRsUsed = 0, NumFPRsUsed = 0, NumVRsUsed = 0;
5117 // Add up all the space actually used.
5118 for (unsigned i = 0; i != NumOps; ++i) {
5119 ISD::ArgFlagsTy Flags = Outs[i].Flags;
5120 EVT ArgVT = Outs[i].VT;
5121 EVT OrigVT = Outs[i].ArgVT;
5126 if (CallConv == CallingConv::Fast) {
5127 if (Flags.isByVal())
5128 NumGPRsUsed += (Flags.getByValSize()+7)/8;
5130 switch (ArgVT.getSimpleVT().SimpleTy) {
5131 default: llvm_unreachable("Unexpected ValueType for argument!");
5135 if (++NumGPRsUsed <= NumGPRs)
5144 if (++NumVRsUsed <= NumVRs)
5148 // When using QPX, this is handled like a FP register, otherwise, it
5149 // is an Altivec register.
5150 if (Subtarget.hasQPX()) {
5151 if (++NumFPRsUsed <= NumFPRs)
5154 if (++NumVRsUsed <= NumVRs)
5160 case MVT::v4f64: // QPX
5161 case MVT::v4i1: // QPX
5162 if (++NumFPRsUsed <= NumFPRs)
5168 /* Respect alignment of argument on the stack. */
5170 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
5171 NumBytes = ((NumBytes + Align - 1) / Align) * Align;
5173 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
5174 if (Flags.isInConsecutiveRegsLast())
5175 NumBytes = ((NumBytes + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
5178 unsigned NumBytesActuallyUsed = NumBytes;
5180 // The prolog code of the callee may store up to 8 GPR argument registers to
5181 // the stack, allowing va_start to index over them in memory if its varargs.
5182 // Because we cannot tell if this is needed on the caller side, we have to
5183 // conservatively assume that it is needed. As such, make sure we have at
5184 // least enough stack space for the caller to store the 8 GPRs.
5185 // FIXME: On ELFv2, it may be unnecessary to allocate the parameter area.
5186 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
5188 // Tail call needs the stack to be aligned.
5189 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
5190 CallConv == CallingConv::Fast)
5191 NumBytes = EnsureStackAlignment(Subtarget.getFrameLowering(), NumBytes);
5195 // Calculate by how many bytes the stack has to be adjusted in case of tail
5196 // call optimization.
5198 SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
5200 // To protect arguments on the stack from being clobbered in a tail call,
5201 // force all the loads to happen before doing any other lowering.
5203 Chain = DAG.getStackArgumentTokenFactor(Chain);
5205 // Adjust the stack pointer for the new arguments...
5206 // These operations are automatically eliminated by the prolog/epilog pass
5208 Chain = DAG.getCALLSEQ_START(Chain,
5209 DAG.getIntPtrConstant(NumBytes, dl, true), dl);
5210 SDValue CallSeqStart = Chain;
5212 // Load the return address and frame pointer so it can be move somewhere else
5215 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, dl);
5217 // Set up a copy of the stack pointer for use loading and storing any
5218 // arguments that may not fit in the registers available for argument
5220 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
5222 // Figure out which arguments are going to go in registers, and which in
5223 // memory. Also, if this is a vararg function, floating point operations
5224 // must be stored to our stack, and loaded into integer regs as well, if
5225 // any integer regs are available for argument passing.
5226 unsigned ArgOffset = LinkageSize;
5228 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
5229 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
5231 SmallVector<SDValue, 8> MemOpChains;
5232 for (unsigned i = 0; i != NumOps; ++i) {
5233 SDValue Arg = OutVals[i];
5234 ISD::ArgFlagsTy Flags = Outs[i].Flags;
5235 EVT ArgVT = Outs[i].VT;
5236 EVT OrigVT = Outs[i].ArgVT;
5238 // PtrOff will be used to store the current argument to the stack if a
5239 // register cannot be found for it.
5242 // We re-align the argument offset for each argument, except when using the
5243 // fast calling convention, when we need to make sure we do that only when
5244 // we'll actually use a stack slot.
5245 auto ComputePtrOff = [&]() {
5246 /* Respect alignment of argument on the stack. */
5248 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
5249 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
5251 PtrOff = DAG.getConstant(ArgOffset, dl, StackPtr.getValueType());
5253 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
5256 if (CallConv != CallingConv::Fast) {
5259 /* Compute GPR index associated with argument offset. */
5260 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
5261 GPR_idx = std::min(GPR_idx, NumGPRs);
5264 // Promote integers to 64-bit values.
5265 if (Arg.getValueType() == MVT::i32 || Arg.getValueType() == MVT::i1) {
5266 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
5267 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
5268 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
5271 // FIXME memcpy is used way more than necessary. Correctness first.
5272 // Note: "by value" is code for passing a structure by value, not
5274 if (Flags.isByVal()) {
5275 // Note: Size includes alignment padding, so
5276 // struct x { short a; char b; }
5277 // will have Size = 4. With #pragma pack(1), it will have Size = 3.
5278 // These are the proper values we need for right-justifying the
5279 // aggregate in a parameter register.
5280 unsigned Size = Flags.getByValSize();
5282 // An empty aggregate parameter takes up no storage and no
5287 if (CallConv == CallingConv::Fast)
5290 // All aggregates smaller than 8 bytes must be passed right-justified.
5291 if (Size==1 || Size==2 || Size==4) {
5292 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32);
5293 if (GPR_idx != NumGPRs) {
5294 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
5295 MachinePointerInfo(), VT);
5296 MemOpChains.push_back(Load.getValue(1));
5297 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5299 ArgOffset += PtrByteSize;
5304 if (GPR_idx == NumGPRs && Size < 8) {
5305 SDValue AddPtr = PtrOff;
5306 if (!isLittleEndian) {
5307 SDValue Const = DAG.getConstant(PtrByteSize - Size, dl,
5308 PtrOff.getValueType());
5309 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
5311 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
5314 ArgOffset += PtrByteSize;
5317 // Copy entire object into memory. There are cases where gcc-generated
5318 // code assumes it is there, even if it could be put entirely into
5319 // registers. (This is not what the doc says.)
5321 // FIXME: The above statement is likely due to a misunderstanding of the
5322 // documents. All arguments must be copied into the parameter area BY
5323 // THE CALLEE in the event that the callee takes the address of any
5324 // formal argument. That has not yet been implemented. However, it is
5325 // reasonable to use the stack area as a staging area for the register
5328 // Skip this for small aggregates, as we will use the same slot for a
5329 // right-justified copy, below.
5331 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
5335 // When a register is available, pass a small aggregate right-justified.
5336 if (Size < 8 && GPR_idx != NumGPRs) {
5337 // The easiest way to get this right-justified in a register
5338 // is to copy the structure into the rightmost portion of a
5339 // local variable slot, then load the whole slot into the
5341 // FIXME: The memcpy seems to produce pretty awful code for
5342 // small aggregates, particularly for packed ones.
5343 // FIXME: It would be preferable to use the slot in the
5344 // parameter save area instead of a new local variable.
5345 SDValue AddPtr = PtrOff;
5346 if (!isLittleEndian) {
5347 SDValue Const = DAG.getConstant(8 - Size, dl, PtrOff.getValueType());
5348 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
5350 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
5354 // Load the slot into the register.
5356 DAG.getLoad(PtrVT, dl, Chain, PtrOff, MachinePointerInfo());
5357 MemOpChains.push_back(Load.getValue(1));
5358 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5360 // Done with this argument.
5361 ArgOffset += PtrByteSize;
5365 // For aggregates larger than PtrByteSize, copy the pieces of the
5366 // object that fit into registers from the parameter save area.
5367 for (unsigned j=0; j<Size; j+=PtrByteSize) {
5368 SDValue Const = DAG.getConstant(j, dl, PtrOff.getValueType());
5369 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
5370 if (GPR_idx != NumGPRs) {
5372 DAG.getLoad(PtrVT, dl, Chain, AddArg, MachinePointerInfo());
5373 MemOpChains.push_back(Load.getValue(1));
5374 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5375 ArgOffset += PtrByteSize;
5377 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
5384 switch (Arg.getSimpleValueType().SimpleTy) {
5385 default: llvm_unreachable("Unexpected ValueType for argument!");
5389 if (Flags.isNest()) {
5390 // The 'nest' parameter, if any, is passed in R11.
5391 RegsToPass.push_back(std::make_pair(PPC::X11, Arg));
5396 // These can be scalar arguments or elements of an integer array type
5397 // passed directly. Clang may use those instead of "byval" aggregate
5398 // types to avoid forcing arguments to memory unnecessarily.
5399 if (GPR_idx != NumGPRs) {
5400 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
5402 if (CallConv == CallingConv::Fast)
5405 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5406 true, isTailCall, false, MemOpChains,
5407 TailCallArguments, dl);
5408 if (CallConv == CallingConv::Fast)
5409 ArgOffset += PtrByteSize;
5411 if (CallConv != CallingConv::Fast)
5412 ArgOffset += PtrByteSize;
5416 // These can be scalar arguments or elements of a float array type
5417 // passed directly. The latter are used to implement ELFv2 homogenous
5418 // float aggregates.
5420 // Named arguments go into FPRs first, and once they overflow, the
5421 // remaining arguments go into GPRs and then the parameter save area.
5422 // Unnamed arguments for vararg functions always go to GPRs and
5423 // then the parameter save area. For now, put all arguments to vararg
5424 // routines always in both locations (FPR *and* GPR or stack slot).
5425 bool NeedGPROrStack = isVarArg || FPR_idx == NumFPRs;
5426 bool NeededLoad = false;
5428 // First load the argument into the next available FPR.
5429 if (FPR_idx != NumFPRs)
5430 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
5432 // Next, load the argument into GPR or stack slot if needed.
5433 if (!NeedGPROrStack)
5435 else if (GPR_idx != NumGPRs && CallConv != CallingConv::Fast) {
5436 // FIXME: We may want to re-enable this for CallingConv::Fast on the P8
5437 // once we support fp <-> gpr moves.
5439 // In the non-vararg case, this can only ever happen in the
5440 // presence of f32 array types, since otherwise we never run
5441 // out of FPRs before running out of GPRs.
5444 // Double values are always passed in a single GPR.
5445 if (Arg.getValueType() != MVT::f32) {
5446 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
5448 // Non-array float values are extended and passed in a GPR.
5449 } else if (!Flags.isInConsecutiveRegs()) {
5450 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
5451 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal);
5453 // If we have an array of floats, we collect every odd element
5454 // together with its predecessor into one GPR.
5455 } else if (ArgOffset % PtrByteSize != 0) {
5457 Lo = DAG.getNode(ISD::BITCAST, dl, MVT::i32, OutVals[i - 1]);
5458 Hi = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
5459 if (!isLittleEndian)
5461 ArgVal = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
5463 // The final element, if even, goes into the first half of a GPR.
5464 } else if (Flags.isInConsecutiveRegsLast()) {
5465 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
5466 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal);
5467 if (!isLittleEndian)
5468 ArgVal = DAG.getNode(ISD::SHL, dl, MVT::i64, ArgVal,
5469 DAG.getConstant(32, dl, MVT::i32));
5471 // Non-final even elements are skipped; they will be handled
5472 // together the with subsequent argument on the next go-around.
5476 if (ArgVal.getNode())
5477 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], ArgVal));
5479 if (CallConv == CallingConv::Fast)
5482 // Single-precision floating-point values are mapped to the
5483 // second (rightmost) word of the stack doubleword.
5484 if (Arg.getValueType() == MVT::f32 &&
5485 !isLittleEndian && !Flags.isInConsecutiveRegs()) {
5486 SDValue ConstFour = DAG.getConstant(4, dl, PtrOff.getValueType());
5487 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
5490 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5491 true, isTailCall, false, MemOpChains,
5492 TailCallArguments, dl);
5496 // When passing an array of floats, the array occupies consecutive
5497 // space in the argument area; only round up to the next doubleword
5498 // at the end of the array. Otherwise, each float takes 8 bytes.
5499 if (CallConv != CallingConv::Fast || NeededLoad) {
5500 ArgOffset += (Arg.getValueType() == MVT::f32 &&
5501 Flags.isInConsecutiveRegs()) ? 4 : 8;
5502 if (Flags.isInConsecutiveRegsLast())
5503 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
5514 if (!Subtarget.hasQPX()) {
5515 // These can be scalar arguments or elements of a vector array type
5516 // passed directly. The latter are used to implement ELFv2 homogenous
5517 // vector aggregates.
5519 // For a varargs call, named arguments go into VRs or on the stack as
5520 // usual; unnamed arguments always go to the stack or the corresponding
5521 // GPRs when within range. For now, we always put the value in both
5522 // locations (or even all three).
5524 // We could elide this store in the case where the object fits
5525 // entirely in R registers. Maybe later.
5527 DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo());
5528 MemOpChains.push_back(Store);
5529 if (VR_idx != NumVRs) {
5531 DAG.getLoad(MVT::v4f32, dl, Store, PtrOff, MachinePointerInfo());
5532 MemOpChains.push_back(Load.getValue(1));
5533 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
5536 for (unsigned i=0; i<16; i+=PtrByteSize) {
5537 if (GPR_idx == NumGPRs)
5539 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
5540 DAG.getConstant(i, dl, PtrVT));
5542 DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo());
5543 MemOpChains.push_back(Load.getValue(1));
5544 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5549 // Non-varargs Altivec params go into VRs or on the stack.
5550 if (VR_idx != NumVRs) {
5551 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
5553 if (CallConv == CallingConv::Fast)
5556 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5557 true, isTailCall, true, MemOpChains,
5558 TailCallArguments, dl);
5559 if (CallConv == CallingConv::Fast)
5563 if (CallConv != CallingConv::Fast)
5568 assert(Arg.getValueType().getSimpleVT().SimpleTy == MVT::v4f32 &&
5569 "Invalid QPX parameter type");
5574 bool IsF32 = Arg.getValueType().getSimpleVT().SimpleTy == MVT::v4f32;
5576 // We could elide this store in the case where the object fits
5577 // entirely in R registers. Maybe later.
5579 DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo());
5580 MemOpChains.push_back(Store);
5581 if (QFPR_idx != NumQFPRs) {
5582 SDValue Load = DAG.getLoad(IsF32 ? MVT::v4f32 : MVT::v4f64, dl, Store,
5583 PtrOff, MachinePointerInfo());
5584 MemOpChains.push_back(Load.getValue(1));
5585 RegsToPass.push_back(std::make_pair(QFPR[QFPR_idx++], Load));
5587 ArgOffset += (IsF32 ? 16 : 32);
5588 for (unsigned i = 0; i < (IsF32 ? 16U : 32U); i += PtrByteSize) {
5589 if (GPR_idx == NumGPRs)
5591 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
5592 DAG.getConstant(i, dl, PtrVT));
5594 DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo());
5595 MemOpChains.push_back(Load.getValue(1));
5596 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5601 // Non-varargs QPX params go into registers or on the stack.
5602 if (QFPR_idx != NumQFPRs) {
5603 RegsToPass.push_back(std::make_pair(QFPR[QFPR_idx++], Arg));
5605 if (CallConv == CallingConv::Fast)
5608 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5609 true, isTailCall, true, MemOpChains,
5610 TailCallArguments, dl);
5611 if (CallConv == CallingConv::Fast)
5612 ArgOffset += (IsF32 ? 16 : 32);
5615 if (CallConv != CallingConv::Fast)
5616 ArgOffset += (IsF32 ? 16 : 32);
5622 assert(NumBytesActuallyUsed == ArgOffset);
5623 (void)NumBytesActuallyUsed;
5625 if (!MemOpChains.empty())
5626 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
5628 // Check if this is an indirect call (MTCTR/BCTRL).
5629 // See PrepareCall() for more information about calls through function
5630 // pointers in the 64-bit SVR4 ABI.
5631 if (!isTailCall && !isPatchPoint &&
5632 !isFunctionGlobalAddress(Callee) &&
5633 !isa<ExternalSymbolSDNode>(Callee)) {
5634 // Load r2 into a virtual register and store it to the TOC save area.
5635 setUsesTOCBasePtr(DAG);
5636 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
5637 // TOC save area offset.
5638 unsigned TOCSaveOffset = Subtarget.getFrameLowering()->getTOCSaveOffset();
5639 SDValue PtrOff = DAG.getIntPtrConstant(TOCSaveOffset, dl);
5640 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
5641 Chain = DAG.getStore(
5642 Val.getValue(1), dl, Val, AddPtr,
5643 MachinePointerInfo::getStack(DAG.getMachineFunction(), TOCSaveOffset));
5644 // In the ELFv2 ABI, R12 must contain the address of an indirect callee.
5645 // This does not mean the MTCTR instruction must use R12; it's easier
5646 // to model this as an extra parameter, so do that.
5647 if (isELFv2ABI && !isPatchPoint)
5648 RegsToPass.push_back(std::make_pair((unsigned)PPC::X12, Callee));
5651 // Build a sequence of copy-to-reg nodes chained together with token chain
5652 // and flag operands which copy the outgoing args into the appropriate regs.
5654 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
5655 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
5656 RegsToPass[i].second, InFlag);
5657 InFlag = Chain.getValue(1);
5660 if (isTailCall && !IsSibCall)
5661 PrepareTailCall(DAG, InFlag, Chain, dl, SPDiff, NumBytes, LROp, FPOp,
5664 return FinishCall(CallConv, dl, isTailCall, isVarArg, isPatchPoint, hasNest,
5665 DAG, RegsToPass, InFlag, Chain, CallSeqStart, Callee,
5666 SPDiff, NumBytes, Ins, InVals, CS);
5669 SDValue PPCTargetLowering::LowerCall_Darwin(
5670 SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg,
5671 bool isTailCall, bool isPatchPoint,
5672 const SmallVectorImpl<ISD::OutputArg> &Outs,
5673 const SmallVectorImpl<SDValue> &OutVals,
5674 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
5675 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
5676 ImmutableCallSite *CS) const {
5678 unsigned NumOps = Outs.size();
5680 EVT PtrVT = getPointerTy(DAG.getDataLayout());
5681 bool isPPC64 = PtrVT == MVT::i64;
5682 unsigned PtrByteSize = isPPC64 ? 8 : 4;
5684 MachineFunction &MF = DAG.getMachineFunction();
5686 // Mark this function as potentially containing a function that contains a
5687 // tail call. As a consequence the frame pointer will be used for dynamicalloc
5688 // and restoring the callers stack pointer in this functions epilog. This is
5689 // done because by tail calling the called function might overwrite the value
5690 // in this function's (MF) stack pointer stack slot 0(SP).
5691 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
5692 CallConv == CallingConv::Fast)
5693 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
5695 // Count how many bytes are to be pushed on the stack, including the linkage
5696 // area, and parameter passing area. We start with 24/48 bytes, which is
5697 // prereserved space for [SP][CR][LR][3 x unused].
5698 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
5699 unsigned NumBytes = LinkageSize;
5701 // Add up all the space actually used.
5702 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
5703 // they all go in registers, but we must reserve stack space for them for
5704 // possible use by the caller. In varargs or 64-bit calls, parameters are
5705 // assigned stack space in order, with padding so Altivec parameters are
5707 unsigned nAltivecParamsAtEnd = 0;
5708 for (unsigned i = 0; i != NumOps; ++i) {
5709 ISD::ArgFlagsTy Flags = Outs[i].Flags;
5710 EVT ArgVT = Outs[i].VT;
5711 // Varargs Altivec parameters are padded to a 16 byte boundary.
5712 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
5713 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
5714 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64) {
5715 if (!isVarArg && !isPPC64) {
5716 // Non-varargs Altivec parameters go after all the non-Altivec
5717 // parameters; handle those later so we know how much padding we need.
5718 nAltivecParamsAtEnd++;
5721 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
5722 NumBytes = ((NumBytes+15)/16)*16;
5724 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
5727 // Allow for Altivec parameters at the end, if needed.
5728 if (nAltivecParamsAtEnd) {
5729 NumBytes = ((NumBytes+15)/16)*16;
5730 NumBytes += 16*nAltivecParamsAtEnd;
5733 // The prolog code of the callee may store up to 8 GPR argument registers to
5734 // the stack, allowing va_start to index over them in memory if its varargs.
5735 // Because we cannot tell if this is needed on the caller side, we have to
5736 // conservatively assume that it is needed. As such, make sure we have at
5737 // least enough stack space for the caller to store the 8 GPRs.
5738 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
5740 // Tail call needs the stack to be aligned.
5741 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
5742 CallConv == CallingConv::Fast)
5743 NumBytes = EnsureStackAlignment(Subtarget.getFrameLowering(), NumBytes);
5745 // Calculate by how many bytes the stack has to be adjusted in case of tail
5746 // call optimization.
5747 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
5749 // To protect arguments on the stack from being clobbered in a tail call,
5750 // force all the loads to happen before doing any other lowering.
5752 Chain = DAG.getStackArgumentTokenFactor(Chain);
5754 // Adjust the stack pointer for the new arguments...
5755 // These operations are automatically eliminated by the prolog/epilog pass
5756 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
5758 SDValue CallSeqStart = Chain;
5760 // Load the return address and frame pointer so it can be move somewhere else
5763 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, dl);
5765 // Set up a copy of the stack pointer for use loading and storing any
5766 // arguments that may not fit in the registers available for argument
5770 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
5772 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
5774 // Figure out which arguments are going to go in registers, and which in
5775 // memory. Also, if this is a vararg function, floating point operations
5776 // must be stored to our stack, and loaded into integer regs as well, if
5777 // any integer regs are available for argument passing.
5778 unsigned ArgOffset = LinkageSize;
5779 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
5781 static const MCPhysReg GPR_32[] = { // 32-bit registers.
5782 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
5783 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
5785 static const MCPhysReg GPR_64[] = { // 64-bit registers.
5786 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
5787 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
5789 static const MCPhysReg VR[] = {
5790 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
5791 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
5793 const unsigned NumGPRs = array_lengthof(GPR_32);
5794 const unsigned NumFPRs = 13;
5795 const unsigned NumVRs = array_lengthof(VR);
5797 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
5799 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
5800 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
5802 SmallVector<SDValue, 8> MemOpChains;
5803 for (unsigned i = 0; i != NumOps; ++i) {
5804 SDValue Arg = OutVals[i];
5805 ISD::ArgFlagsTy Flags = Outs[i].Flags;
5807 // PtrOff will be used to store the current argument to the stack if a
5808 // register cannot be found for it.
5811 PtrOff = DAG.getConstant(ArgOffset, dl, StackPtr.getValueType());
5813 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
5815 // On PPC64, promote integers to 64-bit values.
5816 if (isPPC64 && Arg.getValueType() == MVT::i32) {
5817 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
5818 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
5819 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
5822 // FIXME memcpy is used way more than necessary. Correctness first.
5823 // Note: "by value" is code for passing a structure by value, not
5825 if (Flags.isByVal()) {
5826 unsigned Size = Flags.getByValSize();
5827 // Very small objects are passed right-justified. Everything else is
5828 // passed left-justified.
5829 if (Size==1 || Size==2) {
5830 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
5831 if (GPR_idx != NumGPRs) {
5832 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
5833 MachinePointerInfo(), VT);
5834 MemOpChains.push_back(Load.getValue(1));
5835 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5837 ArgOffset += PtrByteSize;
5839 SDValue Const = DAG.getConstant(PtrByteSize - Size, dl,
5840 PtrOff.getValueType());
5841 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
5842 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
5845 ArgOffset += PtrByteSize;
5849 // Copy entire object into memory. There are cases where gcc-generated
5850 // code assumes it is there, even if it could be put entirely into
5851 // registers. (This is not what the doc says.)
5852 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
5856 // For small aggregates (Darwin only) and aggregates >= PtrByteSize,
5857 // copy the pieces of the object that fit into registers from the
5858 // parameter save area.
5859 for (unsigned j=0; j<Size; j+=PtrByteSize) {
5860 SDValue Const = DAG.getConstant(j, dl, PtrOff.getValueType());
5861 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
5862 if (GPR_idx != NumGPRs) {
5864 DAG.getLoad(PtrVT, dl, Chain, AddArg, MachinePointerInfo());
5865 MemOpChains.push_back(Load.getValue(1));
5866 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5867 ArgOffset += PtrByteSize;
5869 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
5876 switch (Arg.getSimpleValueType().SimpleTy) {
5877 default: llvm_unreachable("Unexpected ValueType for argument!");
5881 if (GPR_idx != NumGPRs) {
5882 if (Arg.getValueType() == MVT::i1)
5883 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, PtrVT, Arg);
5885 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
5887 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5888 isPPC64, isTailCall, false, MemOpChains,
5889 TailCallArguments, dl);
5891 ArgOffset += PtrByteSize;
5895 if (FPR_idx != NumFPRs) {
5896 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
5900 DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo());
5901 MemOpChains.push_back(Store);
5903 // Float varargs are always shadowed in available integer registers
5904 if (GPR_idx != NumGPRs) {
5906 DAG.getLoad(PtrVT, dl, Store, PtrOff, MachinePointerInfo());
5907 MemOpChains.push_back(Load.getValue(1));
5908 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5910 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
5911 SDValue ConstFour = DAG.getConstant(4, dl, PtrOff.getValueType());
5912 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
5914 DAG.getLoad(PtrVT, dl, Store, PtrOff, MachinePointerInfo());
5915 MemOpChains.push_back(Load.getValue(1));
5916 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5919 // If we have any FPRs remaining, we may also have GPRs remaining.
5920 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
5922 if (GPR_idx != NumGPRs)
5924 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
5925 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
5929 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5930 isPPC64, isTailCall, false, MemOpChains,
5931 TailCallArguments, dl);
5935 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
5942 // These go aligned on the stack, or in the corresponding R registers
5943 // when within range. The Darwin PPC ABI doc claims they also go in
5944 // V registers; in fact gcc does this only for arguments that are
5945 // prototyped, not for those that match the ... We do it for all
5946 // arguments, seems to work.
5947 while (ArgOffset % 16 !=0) {
5948 ArgOffset += PtrByteSize;
5949 if (GPR_idx != NumGPRs)
5952 // We could elide this store in the case where the object fits
5953 // entirely in R registers. Maybe later.
5954 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
5955 DAG.getConstant(ArgOffset, dl, PtrVT));
5957 DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo());
5958 MemOpChains.push_back(Store);
5959 if (VR_idx != NumVRs) {
5961 DAG.getLoad(MVT::v4f32, dl, Store, PtrOff, MachinePointerInfo());
5962 MemOpChains.push_back(Load.getValue(1));
5963 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
5966 for (unsigned i=0; i<16; i+=PtrByteSize) {
5967 if (GPR_idx == NumGPRs)
5969 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
5970 DAG.getConstant(i, dl, PtrVT));
5972 DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo());
5973 MemOpChains.push_back(Load.getValue(1));
5974 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5979 // Non-varargs Altivec params generally go in registers, but have
5980 // stack space allocated at the end.
5981 if (VR_idx != NumVRs) {
5982 // Doesn't have GPR space allocated.
5983 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
5984 } else if (nAltivecParamsAtEnd==0) {
5985 // We are emitting Altivec params in order.
5986 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5987 isPPC64, isTailCall, true, MemOpChains,
5988 TailCallArguments, dl);
5994 // If all Altivec parameters fit in registers, as they usually do,
5995 // they get stack space following the non-Altivec parameters. We
5996 // don't track this here because nobody below needs it.
5997 // If there are more Altivec parameters than fit in registers emit
5999 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
6001 // Offset is aligned; skip 1st 12 params which go in V registers.
6002 ArgOffset = ((ArgOffset+15)/16)*16;
6004 for (unsigned i = 0; i != NumOps; ++i) {
6005 SDValue Arg = OutVals[i];
6006 EVT ArgType = Outs[i].VT;
6007 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
6008 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
6011 // We are emitting Altivec params in order.
6012 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
6013 isPPC64, isTailCall, true, MemOpChains,
6014 TailCallArguments, dl);
6021 if (!MemOpChains.empty())
6022 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
6024 // On Darwin, R12 must contain the address of an indirect callee. This does
6025 // not mean the MTCTR instruction must use R12; it's easier to model this as
6026 // an extra parameter, so do that.
6028 !isFunctionGlobalAddress(Callee) &&
6029 !isa<ExternalSymbolSDNode>(Callee) &&
6030 !isBLACompatibleAddress(Callee, DAG))
6031 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
6032 PPC::R12), Callee));
6034 // Build a sequence of copy-to-reg nodes chained together with token chain
6035 // and flag operands which copy the outgoing args into the appropriate regs.
6037 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
6038 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
6039 RegsToPass[i].second, InFlag);
6040 InFlag = Chain.getValue(1);
6044 PrepareTailCall(DAG, InFlag, Chain, dl, SPDiff, NumBytes, LROp, FPOp,
6047 return FinishCall(CallConv, dl, isTailCall, isVarArg, isPatchPoint,
6048 /* unused except on PPC64 ELFv1 */ false, DAG,
6049 RegsToPass, InFlag, Chain, CallSeqStart, Callee, SPDiff,
6050 NumBytes, Ins, InVals, CS);
6054 PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
6055 MachineFunction &MF, bool isVarArg,
6056 const SmallVectorImpl<ISD::OutputArg> &Outs,
6057 LLVMContext &Context) const {
6058 SmallVector<CCValAssign, 16> RVLocs;
6059 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
6060 return CCInfo.CheckReturn(Outs, RetCC_PPC);
6064 PPCTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
6066 const SmallVectorImpl<ISD::OutputArg> &Outs,
6067 const SmallVectorImpl<SDValue> &OutVals,
6068 const SDLoc &dl, SelectionDAG &DAG) const {
6070 SmallVector<CCValAssign, 16> RVLocs;
6071 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
6073 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
6076 SmallVector<SDValue, 4> RetOps(1, Chain);
6078 // Copy the result values into the output registers.
6079 for (unsigned i = 0; i != RVLocs.size(); ++i) {
6080 CCValAssign &VA = RVLocs[i];
6081 assert(VA.isRegLoc() && "Can only return in registers!");
6083 SDValue Arg = OutVals[i];
6085 switch (VA.getLocInfo()) {
6086 default: llvm_unreachable("Unknown loc info!");
6087 case CCValAssign::Full: break;
6088 case CCValAssign::AExt:
6089 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
6091 case CCValAssign::ZExt:
6092 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
6094 case CCValAssign::SExt:
6095 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
6099 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
6100 Flag = Chain.getValue(1);
6101 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
6104 const PPCRegisterInfo *TRI = Subtarget.getRegisterInfo();
6105 const MCPhysReg *I =
6106 TRI->getCalleeSavedRegsViaCopy(&DAG.getMachineFunction());
6110 if (PPC::G8RCRegClass.contains(*I))
6111 RetOps.push_back(DAG.getRegister(*I, MVT::i64));
6112 else if (PPC::F8RCRegClass.contains(*I))
6113 RetOps.push_back(DAG.getRegister(*I, MVT::getFloatingPointVT(64)));
6114 else if (PPC::CRRCRegClass.contains(*I))
6115 RetOps.push_back(DAG.getRegister(*I, MVT::i1));
6116 else if (PPC::VRRCRegClass.contains(*I))
6117 RetOps.push_back(DAG.getRegister(*I, MVT::Other));
6119 llvm_unreachable("Unexpected register class in CSRsViaCopy!");
6123 RetOps[0] = Chain; // Update chain.
6125 // Add the flag if we have it.
6127 RetOps.push_back(Flag);
6129 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, RetOps);
6133 PPCTargetLowering::LowerGET_DYNAMIC_AREA_OFFSET(SDValue Op,
6134 SelectionDAG &DAG) const {
6137 // Get the corect type for integers.
6138 EVT IntVT = Op.getValueType();
6141 SDValue Chain = Op.getOperand(0);
6142 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
6143 // Build a DYNAREAOFFSET node.
6144 SDValue Ops[2] = {Chain, FPSIdx};
6145 SDVTList VTs = DAG.getVTList(IntVT);
6146 return DAG.getNode(PPCISD::DYNAREAOFFSET, dl, VTs, Ops);
6149 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op,
6150 SelectionDAG &DAG) const {
6151 // When we pop the dynamic allocation we need to restore the SP link.
6154 // Get the corect type for pointers.
6155 EVT PtrVT = getPointerTy(DAG.getDataLayout());
6157 // Construct the stack pointer operand.
6158 bool isPPC64 = Subtarget.isPPC64();
6159 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
6160 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
6162 // Get the operands for the STACKRESTORE.
6163 SDValue Chain = Op.getOperand(0);
6164 SDValue SaveSP = Op.getOperand(1);
6166 // Load the old link SP.
6167 SDValue LoadLinkSP =
6168 DAG.getLoad(PtrVT, dl, Chain, StackPtr, MachinePointerInfo());
6170 // Restore the stack pointer.
6171 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
6173 // Store the old link SP.
6174 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo());
6177 SDValue PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG &DAG) const {
6178 MachineFunction &MF = DAG.getMachineFunction();
6179 bool isPPC64 = Subtarget.isPPC64();
6180 EVT PtrVT = getPointerTy(MF.getDataLayout());
6182 // Get current frame pointer save index. The users of this index will be
6183 // primarily DYNALLOC instructions.
6184 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
6185 int RASI = FI->getReturnAddrSaveIndex();
6187 // If the frame pointer save index hasn't been defined yet.
6189 // Find out what the fix offset of the frame pointer save area.
6190 int LROffset = Subtarget.getFrameLowering()->getReturnSaveOffset();
6191 // Allocate the frame index for frame pointer save area.
6192 RASI = MF.getFrameInfo().CreateFixedObject(isPPC64? 8 : 4, LROffset, false);
6194 FI->setReturnAddrSaveIndex(RASI);
6196 return DAG.getFrameIndex(RASI, PtrVT);
6200 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
6201 MachineFunction &MF = DAG.getMachineFunction();
6202 bool isPPC64 = Subtarget.isPPC64();
6203 EVT PtrVT = getPointerTy(MF.getDataLayout());
6205 // Get current frame pointer save index. The users of this index will be
6206 // primarily DYNALLOC instructions.
6207 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
6208 int FPSI = FI->getFramePointerSaveIndex();
6210 // If the frame pointer save index hasn't been defined yet.
6212 // Find out what the fix offset of the frame pointer save area.
6213 int FPOffset = Subtarget.getFrameLowering()->getFramePointerSaveOffset();
6214 // Allocate the frame index for frame pointer save area.
6215 FPSI = MF.getFrameInfo().CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
6217 FI->setFramePointerSaveIndex(FPSI);
6219 return DAG.getFrameIndex(FPSI, PtrVT);
6222 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
6223 SelectionDAG &DAG) const {
6225 SDValue Chain = Op.getOperand(0);
6226 SDValue Size = Op.getOperand(1);
6229 // Get the corect type for pointers.
6230 EVT PtrVT = getPointerTy(DAG.getDataLayout());
6232 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
6233 DAG.getConstant(0, dl, PtrVT), Size);
6234 // Construct a node for the frame pointer save index.
6235 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
6236 // Build a DYNALLOC node.
6237 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
6238 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
6239 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops);
6242 SDValue PPCTargetLowering::LowerEH_DWARF_CFA(SDValue Op,
6243 SelectionDAG &DAG) const {
6244 MachineFunction &MF = DAG.getMachineFunction();
6246 bool isPPC64 = Subtarget.isPPC64();
6247 EVT PtrVT = getPointerTy(DAG.getDataLayout());
6249 int FI = MF.getFrameInfo().CreateFixedObject(isPPC64 ? 8 : 4, 0, false);
6250 return DAG.getFrameIndex(FI, PtrVT);
6253 SDValue PPCTargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
6254 SelectionDAG &DAG) const {
6256 return DAG.getNode(PPCISD::EH_SJLJ_SETJMP, DL,
6257 DAG.getVTList(MVT::i32, MVT::Other),
6258 Op.getOperand(0), Op.getOperand(1));
6261 SDValue PPCTargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
6262 SelectionDAG &DAG) const {
6264 return DAG.getNode(PPCISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
6265 Op.getOperand(0), Op.getOperand(1));
6268 SDValue PPCTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
6269 if (Op.getValueType().isVector())
6270 return LowerVectorLoad(Op, DAG);
6272 assert(Op.getValueType() == MVT::i1 &&
6273 "Custom lowering only for i1 loads");
6275 // First, load 8 bits into 32 bits, then truncate to 1 bit.
6278 LoadSDNode *LD = cast<LoadSDNode>(Op);
6280 SDValue Chain = LD->getChain();
6281 SDValue BasePtr = LD->getBasePtr();
6282 MachineMemOperand *MMO = LD->getMemOperand();
6285 DAG.getExtLoad(ISD::EXTLOAD, dl, getPointerTy(DAG.getDataLayout()), Chain,
6286 BasePtr, MVT::i8, MMO);
6287 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewLD);
6289 SDValue Ops[] = { Result, SDValue(NewLD.getNode(), 1) };
6290 return DAG.getMergeValues(Ops, dl);
6293 SDValue PPCTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
6294 if (Op.getOperand(1).getValueType().isVector())
6295 return LowerVectorStore(Op, DAG);
6297 assert(Op.getOperand(1).getValueType() == MVT::i1 &&
6298 "Custom lowering only for i1 stores");
6300 // First, zero extend to 32 bits, then use a truncating store to 8 bits.
6303 StoreSDNode *ST = cast<StoreSDNode>(Op);
6305 SDValue Chain = ST->getChain();
6306 SDValue BasePtr = ST->getBasePtr();
6307 SDValue Value = ST->getValue();
6308 MachineMemOperand *MMO = ST->getMemOperand();
6310 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, getPointerTy(DAG.getDataLayout()),
6312 return DAG.getTruncStore(Chain, dl, Value, BasePtr, MVT::i8, MMO);
6315 // FIXME: Remove this once the ANDI glue bug is fixed:
6316 SDValue PPCTargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
6317 assert(Op.getValueType() == MVT::i1 &&
6318 "Custom lowering only for i1 results");
6321 return DAG.getNode(PPCISD::ANDIo_1_GT_BIT, DL, MVT::i1,
6325 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
6327 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
6328 // Not FP? Not a fsel.
6329 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
6330 !Op.getOperand(2).getValueType().isFloatingPoint())
6333 // We might be able to do better than this under some circumstances, but in
6334 // general, fsel-based lowering of select is a finite-math-only optimization.
6335 // For more information, see section F.3 of the 2.06 ISA specification.
6336 if (!DAG.getTarget().Options.NoInfsFPMath ||
6337 !DAG.getTarget().Options.NoNaNsFPMath)
6339 // TODO: Propagate flags from the select rather than global settings.
6341 Flags.setNoInfs(true);
6342 Flags.setNoNaNs(true);
6344 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
6346 EVT ResVT = Op.getValueType();
6347 EVT CmpVT = Op.getOperand(0).getValueType();
6348 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6349 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
6352 // If the RHS of the comparison is a 0.0, we don't need to do the
6353 // subtraction at all.
6355 if (isFloatingPointZero(RHS))
6357 default: break; // SETUO etc aren't handled by fsel.
6361 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
6362 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
6363 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
6364 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
6365 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
6366 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
6367 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV);
6370 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
6373 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
6374 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
6375 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
6378 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
6381 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
6382 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
6383 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
6384 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
6389 default: break; // SETUO etc aren't handled by fsel.
6393 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS, &Flags);
6394 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
6395 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
6396 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
6397 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
6398 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
6399 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
6400 DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV);
6403 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS, &Flags);
6404 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
6405 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
6406 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
6409 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS, &Flags);
6410 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
6411 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
6412 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
6415 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS, &Flags);
6416 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
6417 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
6418 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
6421 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS, &Flags);
6422 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
6423 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
6424 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
6429 void PPCTargetLowering::LowerFP_TO_INTForReuse(SDValue Op, ReuseLoadInfo &RLI,
6431 const SDLoc &dl) const {
6432 assert(Op.getOperand(0).getValueType().isFloatingPoint());
6433 SDValue Src = Op.getOperand(0);
6434 if (Src.getValueType() == MVT::f32)
6435 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
6438 switch (Op.getSimpleValueType().SimpleTy) {
6439 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
6442 Op.getOpcode() == ISD::FP_TO_SINT
6444 : (Subtarget.hasFPCVT() ? PPCISD::FCTIWUZ : PPCISD::FCTIDZ),
6448 assert((Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT()) &&
6449 "i64 FP_TO_UINT is supported only with FPCVT");
6450 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
6456 // Convert the FP value to an int value through memory.
6457 bool i32Stack = Op.getValueType() == MVT::i32 && Subtarget.hasSTFIWX() &&
6458 (Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT());
6459 SDValue FIPtr = DAG.CreateStackTemporary(i32Stack ? MVT::i32 : MVT::f64);
6460 int FI = cast<FrameIndexSDNode>(FIPtr)->getIndex();
6461 MachinePointerInfo MPI =
6462 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI);
6464 // Emit a store to the stack slot.
6467 MachineFunction &MF = DAG.getMachineFunction();
6468 MachineMemOperand *MMO =
6469 MF.getMachineMemOperand(MPI, MachineMemOperand::MOStore, 4, 4);
6470 SDValue Ops[] = { DAG.getEntryNode(), Tmp, FIPtr };
6471 Chain = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
6472 DAG.getVTList(MVT::Other), Ops, MVT::i32, MMO);
6474 Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr, MPI);
6476 // Result is a load from the stack slot. If loading 4 bytes, make sure to
6477 // add in a bias on big endian.
6478 if (Op.getValueType() == MVT::i32 && !i32Stack) {
6479 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
6480 DAG.getConstant(4, dl, FIPtr.getValueType()));
6481 MPI = MPI.getWithOffset(Subtarget.isLittleEndian() ? 0 : 4);
6489 /// \brief Custom lowers floating point to integer conversions to use
6490 /// the direct move instructions available in ISA 2.07 to avoid the
6491 /// need for load/store combinations.
6492 SDValue PPCTargetLowering::LowerFP_TO_INTDirectMove(SDValue Op,
6494 const SDLoc &dl) const {
6495 assert(Op.getOperand(0).getValueType().isFloatingPoint());
6496 SDValue Src = Op.getOperand(0);
6498 if (Src.getValueType() == MVT::f32)
6499 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
6502 switch (Op.getSimpleValueType().SimpleTy) {
6503 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
6506 Op.getOpcode() == ISD::FP_TO_SINT
6508 : (Subtarget.hasFPCVT() ? PPCISD::FCTIWUZ : PPCISD::FCTIDZ),
6510 Tmp = DAG.getNode(PPCISD::MFVSR, dl, MVT::i32, Tmp);
6513 assert((Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT()) &&
6514 "i64 FP_TO_UINT is supported only with FPCVT");
6515 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
6518 Tmp = DAG.getNode(PPCISD::MFVSR, dl, MVT::i64, Tmp);
6524 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
6525 const SDLoc &dl) const {
6526 if (Subtarget.hasDirectMove() && Subtarget.isPPC64())
6527 return LowerFP_TO_INTDirectMove(Op, DAG, dl);
6530 LowerFP_TO_INTForReuse(Op, RLI, DAG, dl);
6532 return DAG.getLoad(Op.getValueType(), dl, RLI.Chain, RLI.Ptr, RLI.MPI,
6533 RLI.Alignment, RLI.MMOFlags(), RLI.AAInfo, RLI.Ranges);
6536 // We're trying to insert a regular store, S, and then a load, L. If the
6537 // incoming value, O, is a load, we might just be able to have our load use the
6538 // address used by O. However, we don't know if anything else will store to
6539 // that address before we can load from it. To prevent this situation, we need
6540 // to insert our load, L, into the chain as a peer of O. To do this, we give L
6541 // the same chain operand as O, we create a token factor from the chain results
6542 // of O and L, and we replace all uses of O's chain result with that token
6543 // factor (see spliceIntoChain below for this last part).
6544 bool PPCTargetLowering::canReuseLoadAddress(SDValue Op, EVT MemVT,
6547 ISD::LoadExtType ET) const {
6549 if (ET == ISD::NON_EXTLOAD &&
6550 (Op.getOpcode() == ISD::FP_TO_UINT ||
6551 Op.getOpcode() == ISD::FP_TO_SINT) &&
6552 isOperationLegalOrCustom(Op.getOpcode(),
6553 Op.getOperand(0).getValueType())) {
6555 LowerFP_TO_INTForReuse(Op, RLI, DAG, dl);
6559 LoadSDNode *LD = dyn_cast<LoadSDNode>(Op);
6560 if (!LD || LD->getExtensionType() != ET || LD->isVolatile() ||
6561 LD->isNonTemporal())
6563 if (LD->getMemoryVT() != MemVT)
6566 RLI.Ptr = LD->getBasePtr();
6567 if (LD->isIndexed() && !LD->getOffset().isUndef()) {
6568 assert(LD->getAddressingMode() == ISD::PRE_INC &&
6569 "Non-pre-inc AM on PPC?");
6570 RLI.Ptr = DAG.getNode(ISD::ADD, dl, RLI.Ptr.getValueType(), RLI.Ptr,
6574 RLI.Chain = LD->getChain();
6575 RLI.MPI = LD->getPointerInfo();
6576 RLI.IsDereferenceable = LD->isDereferenceable();
6577 RLI.IsInvariant = LD->isInvariant();
6578 RLI.Alignment = LD->getAlignment();
6579 RLI.AAInfo = LD->getAAInfo();
6580 RLI.Ranges = LD->getRanges();
6582 RLI.ResChain = SDValue(LD, LD->isIndexed() ? 2 : 1);
6586 // Given the head of the old chain, ResChain, insert a token factor containing
6587 // it and NewResChain, and make users of ResChain now be users of that token
6589 void PPCTargetLowering::spliceIntoChain(SDValue ResChain,
6590 SDValue NewResChain,
6591 SelectionDAG &DAG) const {
6595 SDLoc dl(NewResChain);
6597 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
6598 NewResChain, DAG.getUNDEF(MVT::Other));
6599 assert(TF.getNode() != NewResChain.getNode() &&
6600 "A new TF really is required here");
6602 DAG.ReplaceAllUsesOfValueWith(ResChain, TF);
6603 DAG.UpdateNodeOperands(TF.getNode(), ResChain, NewResChain);
6606 /// \brief Analyze profitability of direct move
6607 /// prefer float load to int load plus direct move
6608 /// when there is no integer use of int load
6609 bool PPCTargetLowering::directMoveIsProfitable(const SDValue &Op) const {
6610 SDNode *Origin = Op.getOperand(0).getNode();
6611 if (Origin->getOpcode() != ISD::LOAD)
6614 // If there is no LXSIBZX/LXSIHZX, like Power8,
6615 // prefer direct move if the memory size is 1 or 2 bytes.
6616 MachineMemOperand *MMO = cast<LoadSDNode>(Origin)->getMemOperand();
6617 if (!Subtarget.hasP9Vector() && MMO->getSize() <= 2)
6620 for (SDNode::use_iterator UI = Origin->use_begin(),
6621 UE = Origin->use_end();
6624 // Only look at the users of the loaded value.
6625 if (UI.getUse().get().getResNo() != 0)
6628 if (UI->getOpcode() != ISD::SINT_TO_FP &&
6629 UI->getOpcode() != ISD::UINT_TO_FP)
6636 /// \brief Custom lowers integer to floating point conversions to use
6637 /// the direct move instructions available in ISA 2.07 to avoid the
6638 /// need for load/store combinations.
6639 SDValue PPCTargetLowering::LowerINT_TO_FPDirectMove(SDValue Op,
6641 const SDLoc &dl) const {
6642 assert((Op.getValueType() == MVT::f32 ||
6643 Op.getValueType() == MVT::f64) &&
6644 "Invalid floating point type as target of conversion");
6645 assert(Subtarget.hasFPCVT() &&
6646 "Int to FP conversions with direct moves require FPCVT");
6648 SDValue Src = Op.getOperand(0);
6649 bool SinglePrec = Op.getValueType() == MVT::f32;
6650 bool WordInt = Src.getSimpleValueType().SimpleTy == MVT::i32;
6651 bool Signed = Op.getOpcode() == ISD::SINT_TO_FP;
6652 unsigned ConvOp = Signed ? (SinglePrec ? PPCISD::FCFIDS : PPCISD::FCFID) :
6653 (SinglePrec ? PPCISD::FCFIDUS : PPCISD::FCFIDU);
6656 FP = DAG.getNode(Signed ? PPCISD::MTVSRA : PPCISD::MTVSRZ,
6658 FP = DAG.getNode(ConvOp, dl, SinglePrec ? MVT::f32 : MVT::f64, FP);
6661 FP = DAG.getNode(PPCISD::MTVSRA, dl, MVT::f64, Src);
6662 FP = DAG.getNode(ConvOp, dl, SinglePrec ? MVT::f32 : MVT::f64, FP);
6668 SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
6669 SelectionDAG &DAG) const {
6672 if (Subtarget.hasQPX() && Op.getOperand(0).getValueType() == MVT::v4i1) {
6673 if (Op.getValueType() != MVT::v4f32 && Op.getValueType() != MVT::v4f64)
6676 SDValue Value = Op.getOperand(0);
6677 // The values are now known to be -1 (false) or 1 (true). To convert this
6678 // into 0 (false) and 1 (true), add 1 and then divide by 2 (multiply by 0.5).
6679 // This can be done with an fma and the 0.5 constant: (V+1.0)*0.5 = 0.5*V+0.5
6680 Value = DAG.getNode(PPCISD::QBFLT, dl, MVT::v4f64, Value);
6682 SDValue FPHalfs = DAG.getConstantFP(0.5, dl, MVT::v4f64);
6684 Value = DAG.getNode(ISD::FMA, dl, MVT::v4f64, Value, FPHalfs, FPHalfs);
6686 if (Op.getValueType() != MVT::v4f64)
6687 Value = DAG.getNode(ISD::FP_ROUND, dl,
6688 Op.getValueType(), Value,
6689 DAG.getIntPtrConstant(1, dl));
6693 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
6694 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
6697 if (Op.getOperand(0).getValueType() == MVT::i1)
6698 return DAG.getNode(ISD::SELECT, dl, Op.getValueType(), Op.getOperand(0),
6699 DAG.getConstantFP(1.0, dl, Op.getValueType()),
6700 DAG.getConstantFP(0.0, dl, Op.getValueType()));
6702 // If we have direct moves, we can do all the conversion, skip the store/load
6703 // however, without FPCVT we can't do most conversions.
6704 if (Subtarget.hasDirectMove() && directMoveIsProfitable(Op) &&
6705 Subtarget.isPPC64() && Subtarget.hasFPCVT())
6706 return LowerINT_TO_FPDirectMove(Op, DAG, dl);
6708 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) &&
6709 "UINT_TO_FP is supported only with FPCVT");
6711 // If we have FCFIDS, then use it when converting to single-precision.
6712 // Otherwise, convert to double-precision and then round.
6713 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
6714 ? (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDUS
6716 : (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDU
6718 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
6722 if (Op.getOperand(0).getValueType() == MVT::i64) {
6723 SDValue SINT = Op.getOperand(0);
6724 // When converting to single-precision, we actually need to convert
6725 // to double-precision first and then round to single-precision.
6726 // To avoid double-rounding effects during that operation, we have
6727 // to prepare the input operand. Bits that might be truncated when
6728 // converting to double-precision are replaced by a bit that won't
6729 // be lost at this stage, but is below the single-precision rounding
6732 // However, if -enable-unsafe-fp-math is in effect, accept double
6733 // rounding to avoid the extra overhead.
6734 if (Op.getValueType() == MVT::f32 &&
6735 !Subtarget.hasFPCVT() &&
6736 !DAG.getTarget().Options.UnsafeFPMath) {
6738 // Twiddle input to make sure the low 11 bits are zero. (If this
6739 // is the case, we are guaranteed the value will fit into the 53 bit
6740 // mantissa of an IEEE double-precision value without rounding.)
6741 // If any of those low 11 bits were not zero originally, make sure
6742 // bit 12 (value 2048) is set instead, so that the final rounding
6743 // to single-precision gets the correct result.
6744 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64,
6745 SINT, DAG.getConstant(2047, dl, MVT::i64));
6746 Round = DAG.getNode(ISD::ADD, dl, MVT::i64,
6747 Round, DAG.getConstant(2047, dl, MVT::i64));
6748 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT);
6749 Round = DAG.getNode(ISD::AND, dl, MVT::i64,
6750 Round, DAG.getConstant(-2048, dl, MVT::i64));
6752 // However, we cannot use that value unconditionally: if the magnitude
6753 // of the input value is small, the bit-twiddling we did above might
6754 // end up visibly changing the output. Fortunately, in that case, we
6755 // don't need to twiddle bits since the original input will convert
6756 // exactly to double-precision floating-point already. Therefore,
6757 // construct a conditional to use the original value if the top 11
6758 // bits are all sign-bit copies, and use the rounded value computed
6760 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64,
6761 SINT, DAG.getConstant(53, dl, MVT::i32));
6762 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64,
6763 Cond, DAG.getConstant(1, dl, MVT::i64));
6764 Cond = DAG.getSetCC(dl, MVT::i32,
6765 Cond, DAG.getConstant(1, dl, MVT::i64), ISD::SETUGT);
6767 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT);
6773 MachineFunction &MF = DAG.getMachineFunction();
6774 if (canReuseLoadAddress(SINT, MVT::i64, RLI, DAG)) {
6775 Bits = DAG.getLoad(MVT::f64, dl, RLI.Chain, RLI.Ptr, RLI.MPI,
6776 RLI.Alignment, RLI.MMOFlags(), RLI.AAInfo, RLI.Ranges);
6777 spliceIntoChain(RLI.ResChain, Bits.getValue(1), DAG);
6778 } else if (Subtarget.hasLFIWAX() &&
6779 canReuseLoadAddress(SINT, MVT::i32, RLI, DAG, ISD::SEXTLOAD)) {
6780 MachineMemOperand *MMO =
6781 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
6782 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
6783 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
6784 Bits = DAG.getMemIntrinsicNode(PPCISD::LFIWAX, dl,
6785 DAG.getVTList(MVT::f64, MVT::Other),
6786 Ops, MVT::i32, MMO);
6787 spliceIntoChain(RLI.ResChain, Bits.getValue(1), DAG);
6788 } else if (Subtarget.hasFPCVT() &&
6789 canReuseLoadAddress(SINT, MVT::i32, RLI, DAG, ISD::ZEXTLOAD)) {
6790 MachineMemOperand *MMO =
6791 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
6792 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
6793 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
6794 Bits = DAG.getMemIntrinsicNode(PPCISD::LFIWZX, dl,
6795 DAG.getVTList(MVT::f64, MVT::Other),
6796 Ops, MVT::i32, MMO);
6797 spliceIntoChain(RLI.ResChain, Bits.getValue(1), DAG);
6798 } else if (((Subtarget.hasLFIWAX() &&
6799 SINT.getOpcode() == ISD::SIGN_EXTEND) ||
6800 (Subtarget.hasFPCVT() &&
6801 SINT.getOpcode() == ISD::ZERO_EXTEND)) &&
6802 SINT.getOperand(0).getValueType() == MVT::i32) {
6803 MachineFrameInfo &MFI = MF.getFrameInfo();
6804 EVT PtrVT = getPointerTy(DAG.getDataLayout());
6806 int FrameIdx = MFI.CreateStackObject(4, 4, false);
6807 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6810 DAG.getStore(DAG.getEntryNode(), dl, SINT.getOperand(0), FIdx,
6811 MachinePointerInfo::getFixedStack(
6812 DAG.getMachineFunction(), FrameIdx));
6814 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
6815 "Expected an i32 store");
6820 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx);
6823 MachineMemOperand *MMO =
6824 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
6825 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
6826 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
6827 Bits = DAG.getMemIntrinsicNode(SINT.getOpcode() == ISD::ZERO_EXTEND ?
6828 PPCISD::LFIWZX : PPCISD::LFIWAX,
6829 dl, DAG.getVTList(MVT::f64, MVT::Other),
6830 Ops, MVT::i32, MMO);
6832 Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT);
6834 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Bits);
6836 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
6837 FP = DAG.getNode(ISD::FP_ROUND, dl,
6838 MVT::f32, FP, DAG.getIntPtrConstant(0, dl));
6842 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
6843 "Unhandled INT_TO_FP type in custom expander!");
6844 // Since we only generate this in 64-bit mode, we can take advantage of
6845 // 64-bit registers. In particular, sign extend the input value into the
6846 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
6847 // then lfd it and fcfid it.
6848 MachineFunction &MF = DAG.getMachineFunction();
6849 MachineFrameInfo &MFI = MF.getFrameInfo();
6850 EVT PtrVT = getPointerTy(MF.getDataLayout());
6853 if (Subtarget.hasLFIWAX() || Subtarget.hasFPCVT()) {
6856 if (!(ReusingLoad = canReuseLoadAddress(Op.getOperand(0), MVT::i32, RLI,
6858 int FrameIdx = MFI.CreateStackObject(4, 4, false);
6859 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6862 DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), FIdx,
6863 MachinePointerInfo::getFixedStack(
6864 DAG.getMachineFunction(), FrameIdx));
6866 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
6867 "Expected an i32 store");
6872 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx);
6876 MachineMemOperand *MMO =
6877 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
6878 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
6879 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
6880 Ld = DAG.getMemIntrinsicNode(Op.getOpcode() == ISD::UINT_TO_FP ?
6881 PPCISD::LFIWZX : PPCISD::LFIWAX,
6882 dl, DAG.getVTList(MVT::f64, MVT::Other),
6883 Ops, MVT::i32, MMO);
6885 spliceIntoChain(RLI.ResChain, Ld.getValue(1), DAG);
6887 assert(Subtarget.isPPC64() &&
6888 "i32->FP without LFIWAX supported only on PPC64");
6890 int FrameIdx = MFI.CreateStackObject(8, 8, false);
6891 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6893 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64,
6896 // STD the extended value into the stack slot.
6897 SDValue Store = DAG.getStore(
6898 DAG.getEntryNode(), dl, Ext64, FIdx,
6899 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx));
6901 // Load the value as a double.
6903 MVT::f64, dl, Store, FIdx,
6904 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx));
6907 // FCFID it and return it.
6908 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Ld);
6909 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
6910 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP,
6911 DAG.getIntPtrConstant(0, dl));
6915 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
6916 SelectionDAG &DAG) const {
6919 The rounding mode is in bits 30:31 of FPSR, and has the following
6926 FLT_ROUNDS, on the other hand, expects the following:
6933 To perform the conversion, we do:
6934 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
6937 MachineFunction &MF = DAG.getMachineFunction();
6938 EVT VT = Op.getValueType();
6939 EVT PtrVT = getPointerTy(MF.getDataLayout());
6941 // Save FP Control Word to register
6943 MVT::f64, // return register
6944 MVT::Glue // unused in this context
6946 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, None);
6948 // Save FP register to stack slot
6949 int SSFI = MF.getFrameInfo().CreateStackObject(8, 8, false);
6950 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
6951 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain, StackSlot,
6952 MachinePointerInfo());
6954 // Load FP Control Word from low 32 bits of stack slot.
6955 SDValue Four = DAG.getConstant(4, dl, PtrVT);
6956 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
6957 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo());
6959 // Transform as necessary
6961 DAG.getNode(ISD::AND, dl, MVT::i32,
6962 CWD, DAG.getConstant(3, dl, MVT::i32));
6964 DAG.getNode(ISD::SRL, dl, MVT::i32,
6965 DAG.getNode(ISD::AND, dl, MVT::i32,
6966 DAG.getNode(ISD::XOR, dl, MVT::i32,
6967 CWD, DAG.getConstant(3, dl, MVT::i32)),
6968 DAG.getConstant(3, dl, MVT::i32)),
6969 DAG.getConstant(1, dl, MVT::i32));
6972 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
6974 return DAG.getNode((VT.getSizeInBits() < 16 ?
6975 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
6978 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
6979 EVT VT = Op.getValueType();
6980 unsigned BitWidth = VT.getSizeInBits();
6982 assert(Op.getNumOperands() == 3 &&
6983 VT == Op.getOperand(1).getValueType() &&
6986 // Expand into a bunch of logical ops. Note that these ops
6987 // depend on the PPC behavior for oversized shift amounts.
6988 SDValue Lo = Op.getOperand(0);
6989 SDValue Hi = Op.getOperand(1);
6990 SDValue Amt = Op.getOperand(2);
6991 EVT AmtVT = Amt.getValueType();
6993 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
6994 DAG.getConstant(BitWidth, dl, AmtVT), Amt);
6995 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
6996 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
6997 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
6998 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
6999 DAG.getConstant(-BitWidth, dl, AmtVT));
7000 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
7001 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
7002 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
7003 SDValue OutOps[] = { OutLo, OutHi };
7004 return DAG.getMergeValues(OutOps, dl);
7007 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
7008 EVT VT = Op.getValueType();
7010 unsigned BitWidth = VT.getSizeInBits();
7011 assert(Op.getNumOperands() == 3 &&
7012 VT == Op.getOperand(1).getValueType() &&
7015 // Expand into a bunch of logical ops. Note that these ops
7016 // depend on the PPC behavior for oversized shift amounts.
7017 SDValue Lo = Op.getOperand(0);
7018 SDValue Hi = Op.getOperand(1);
7019 SDValue Amt = Op.getOperand(2);
7020 EVT AmtVT = Amt.getValueType();
7022 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
7023 DAG.getConstant(BitWidth, dl, AmtVT), Amt);
7024 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
7025 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
7026 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
7027 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
7028 DAG.getConstant(-BitWidth, dl, AmtVT));
7029 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
7030 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
7031 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
7032 SDValue OutOps[] = { OutLo, OutHi };
7033 return DAG.getMergeValues(OutOps, dl);
7036 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
7038 EVT VT = Op.getValueType();
7039 unsigned BitWidth = VT.getSizeInBits();
7040 assert(Op.getNumOperands() == 3 &&
7041 VT == Op.getOperand(1).getValueType() &&
7044 // Expand into a bunch of logical ops, followed by a select_cc.
7045 SDValue Lo = Op.getOperand(0);
7046 SDValue Hi = Op.getOperand(1);
7047 SDValue Amt = Op.getOperand(2);
7048 EVT AmtVT = Amt.getValueType();
7050 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
7051 DAG.getConstant(BitWidth, dl, AmtVT), Amt);
7052 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
7053 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
7054 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
7055 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
7056 DAG.getConstant(-BitWidth, dl, AmtVT));
7057 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
7058 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
7059 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, dl, AmtVT),
7060 Tmp4, Tmp6, ISD::SETLE);
7061 SDValue OutOps[] = { OutLo, OutHi };
7062 return DAG.getMergeValues(OutOps, dl);
7065 //===----------------------------------------------------------------------===//
7066 // Vector related lowering.
7069 /// BuildSplatI - Build a canonical splati of Val with an element size of
7070 /// SplatSize. Cast the result to VT.
7071 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
7072 SelectionDAG &DAG, const SDLoc &dl) {
7073 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
7075 static const MVT VTys[] = { // canonical VT to use for each size.
7076 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
7079 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
7081 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
7085 EVT CanonicalVT = VTys[SplatSize-1];
7087 // Build a canonical splat for this value.
7088 return DAG.getBitcast(ReqVT, DAG.getConstant(Val, dl, CanonicalVT));
7091 /// BuildIntrinsicOp - Return a unary operator intrinsic node with the
7092 /// specified intrinsic ID.
7093 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op, SelectionDAG &DAG,
7094 const SDLoc &dl, EVT DestVT = MVT::Other) {
7095 if (DestVT == MVT::Other) DestVT = Op.getValueType();
7096 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
7097 DAG.getConstant(IID, dl, MVT::i32), Op);
7100 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
7101 /// specified intrinsic ID.
7102 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
7103 SelectionDAG &DAG, const SDLoc &dl,
7104 EVT DestVT = MVT::Other) {
7105 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
7106 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
7107 DAG.getConstant(IID, dl, MVT::i32), LHS, RHS);
7110 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
7111 /// specified intrinsic ID.
7112 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
7113 SDValue Op2, SelectionDAG &DAG, const SDLoc &dl,
7114 EVT DestVT = MVT::Other) {
7115 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
7116 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
7117 DAG.getConstant(IID, dl, MVT::i32), Op0, Op1, Op2);
7120 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
7121 /// amount. The result has the specified value type.
7122 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt, EVT VT,
7123 SelectionDAG &DAG, const SDLoc &dl) {
7124 // Force LHS/RHS to be the right type.
7125 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
7126 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
7129 for (unsigned i = 0; i != 16; ++i)
7131 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
7132 return DAG.getNode(ISD::BITCAST, dl, VT, T);
7135 /// Do we have an efficient pattern in a .td file for this node?
7137 /// \param V - pointer to the BuildVectorSDNode being matched
7138 /// \param HasDirectMove - does this subtarget have VSR <-> GPR direct moves?
7140 /// There are some patterns where it is beneficial to keep a BUILD_VECTOR
7141 /// node as a BUILD_VECTOR node rather than expanding it. The patterns where
7142 /// the opposite is true (expansion is beneficial) are:
7143 /// - The node builds a vector out of integers that are not 32 or 64-bits
7144 /// - The node builds a vector out of constants
7145 /// - The node is a "load-and-splat"
7146 /// In all other cases, we will choose to keep the BUILD_VECTOR.
7147 static bool haveEfficientBuildVectorPattern(BuildVectorSDNode *V,
7148 bool HasDirectMove) {
7149 EVT VecVT = V->getValueType(0);
7150 bool RightType = VecVT == MVT::v2f64 || VecVT == MVT::v4f32 ||
7151 (HasDirectMove && (VecVT == MVT::v2i64 || VecVT == MVT::v4i32));
7155 bool IsSplat = true;
7156 bool IsLoad = false;
7157 SDValue Op0 = V->getOperand(0);
7159 // This function is called in a block that confirms the node is not a constant
7160 // splat. So a constant BUILD_VECTOR here means the vector is built out of
7161 // different constants.
7162 if (V->isConstant())
7164 for (int i = 0, e = V->getNumOperands(); i < e; ++i) {
7165 if (V->getOperand(i).isUndef())
7167 // We want to expand nodes that represent load-and-splat even if the
7168 // loaded value is a floating point truncation or conversion to int.
7169 if (V->getOperand(i).getOpcode() == ISD::LOAD ||
7170 (V->getOperand(i).getOpcode() == ISD::FP_ROUND &&
7171 V->getOperand(i).getOperand(0).getOpcode() == ISD::LOAD) ||
7172 (V->getOperand(i).getOpcode() == ISD::FP_TO_SINT &&
7173 V->getOperand(i).getOperand(0).getOpcode() == ISD::LOAD) ||
7174 (V->getOperand(i).getOpcode() == ISD::FP_TO_UINT &&
7175 V->getOperand(i).getOperand(0).getOpcode() == ISD::LOAD))
7177 // If the operands are different or the input is not a load and has more
7178 // uses than just this BV node, then it isn't a splat.
7179 if (V->getOperand(i) != Op0 ||
7180 (!IsLoad && !V->isOnlyUserOf(V->getOperand(i).getNode())))
7183 return !(IsSplat && IsLoad);
7186 // If this is a case we can't handle, return null and let the default
7187 // expansion code take care of it. If we CAN select this case, and if it
7188 // selects to a single instruction, return Op. Otherwise, if we can codegen
7189 // this case more efficiently than a constant pool load, lower it to the
7190 // sequence of ops that should be used.
7191 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
7192 SelectionDAG &DAG) const {
7194 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
7195 assert(BVN && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
7197 if (Subtarget.hasQPX() && Op.getValueType() == MVT::v4i1) {
7198 // We first build an i32 vector, load it into a QPX register,
7199 // then convert it to a floating-point vector and compare it
7200 // to a zero vector to get the boolean result.
7201 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
7202 int FrameIdx = MFI.CreateStackObject(16, 16, false);
7203 MachinePointerInfo PtrInfo =
7204 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx);
7205 EVT PtrVT = getPointerTy(DAG.getDataLayout());
7206 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
7208 assert(BVN->getNumOperands() == 4 &&
7209 "BUILD_VECTOR for v4i1 does not have 4 operands");
7211 bool IsConst = true;
7212 for (unsigned i = 0; i < 4; ++i) {
7213 if (BVN->getOperand(i).isUndef()) continue;
7214 if (!isa<ConstantSDNode>(BVN->getOperand(i))) {
7222 ConstantFP::get(Type::getFloatTy(*DAG.getContext()), 1.0);
7224 ConstantFP::get(Type::getFloatTy(*DAG.getContext()), -1.0);
7227 for (unsigned i = 0; i < 4; ++i) {
7228 if (BVN->getOperand(i).isUndef())
7229 CV[i] = UndefValue::get(Type::getFloatTy(*DAG.getContext()));
7230 else if (isNullConstant(BVN->getOperand(i)))
7236 Constant *CP = ConstantVector::get(CV);
7237 SDValue CPIdx = DAG.getConstantPool(CP, getPointerTy(DAG.getDataLayout()),
7238 16 /* alignment */);
7240 SDValue Ops[] = {DAG.getEntryNode(), CPIdx};
7241 SDVTList VTs = DAG.getVTList({MVT::v4i1, /*chain*/ MVT::Other});
7242 return DAG.getMemIntrinsicNode(
7243 PPCISD::QVLFSb, dl, VTs, Ops, MVT::v4f32,
7244 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
7247 SmallVector<SDValue, 4> Stores;
7248 for (unsigned i = 0; i < 4; ++i) {
7249 if (BVN->getOperand(i).isUndef()) continue;
7251 unsigned Offset = 4*i;
7252 SDValue Idx = DAG.getConstant(Offset, dl, FIdx.getValueType());
7253 Idx = DAG.getNode(ISD::ADD, dl, FIdx.getValueType(), FIdx, Idx);
7255 unsigned StoreSize = BVN->getOperand(i).getValueType().getStoreSize();
7256 if (StoreSize > 4) {
7258 DAG.getTruncStore(DAG.getEntryNode(), dl, BVN->getOperand(i), Idx,
7259 PtrInfo.getWithOffset(Offset), MVT::i32));
7261 SDValue StoreValue = BVN->getOperand(i);
7263 StoreValue = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, StoreValue);
7265 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl, StoreValue, Idx,
7266 PtrInfo.getWithOffset(Offset)));
7271 if (!Stores.empty())
7272 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
7274 StoreChain = DAG.getEntryNode();
7276 // Now load from v4i32 into the QPX register; this will extend it to
7277 // v4i64 but not yet convert it to a floating point. Nevertheless, this
7278 // is typed as v4f64 because the QPX register integer states are not
7279 // explicitly represented.
7281 SDValue Ops[] = {StoreChain,
7282 DAG.getConstant(Intrinsic::ppc_qpx_qvlfiwz, dl, MVT::i32),
7284 SDVTList VTs = DAG.getVTList({MVT::v4f64, /*chain*/ MVT::Other});
7286 SDValue LoadedVect = DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN,
7287 dl, VTs, Ops, MVT::v4i32, PtrInfo);
7288 LoadedVect = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f64,
7289 DAG.getConstant(Intrinsic::ppc_qpx_qvfcfidu, dl, MVT::i32),
7292 SDValue FPZeros = DAG.getConstantFP(0.0, dl, MVT::v4f64);
7294 return DAG.getSetCC(dl, MVT::v4i1, LoadedVect, FPZeros, ISD::SETEQ);
7297 // All other QPX vectors are handled by generic code.
7298 if (Subtarget.hasQPX())
7301 // Check if this is a splat of a constant value.
7302 APInt APSplatBits, APSplatUndef;
7303 unsigned SplatBitSize;
7305 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
7306 HasAnyUndefs, 0, !Subtarget.isLittleEndian()) ||
7307 SplatBitSize > 32) {
7308 // BUILD_VECTOR nodes that are not constant splats of up to 32-bits can be
7309 // lowered to VSX instructions under certain conditions.
7310 // Without VSX, there is no pattern more efficient than expanding the node.
7311 if (Subtarget.hasVSX() &&
7312 haveEfficientBuildVectorPattern(BVN, Subtarget.hasDirectMove()))
7317 unsigned SplatBits = APSplatBits.getZExtValue();
7318 unsigned SplatUndef = APSplatUndef.getZExtValue();
7319 unsigned SplatSize = SplatBitSize / 8;
7321 // First, handle single instruction cases.
7324 if (SplatBits == 0) {
7325 // Canonicalize all zero vectors to be v4i32.
7326 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
7327 SDValue Z = DAG.getConstant(0, dl, MVT::v4i32);
7328 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
7333 // We have XXSPLTIB for constant splats one byte wide
7334 if (Subtarget.hasP9Vector() && SplatSize == 1) {
7335 // This is a splat of 1-byte elements with some elements potentially undef.
7336 // Rather than trying to match undef in the SDAG patterns, ensure that all
7337 // elements are the same constant.
7338 if (HasAnyUndefs || ISD::isBuildVectorAllOnes(BVN)) {
7339 SmallVector<SDValue, 16> Ops(16, DAG.getConstant(SplatBits,
7341 SDValue NewBV = DAG.getBuildVector(MVT::v16i8, dl, Ops);
7342 if (Op.getValueType() != MVT::v16i8)
7343 return DAG.getBitcast(Op.getValueType(), NewBV);
7349 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
7350 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
7352 if (SextVal >= -16 && SextVal <= 15)
7353 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
7355 // Two instruction sequences.
7357 // If this value is in the range [-32,30] and is even, use:
7358 // VSPLTI[bhw](val/2) + VSPLTI[bhw](val/2)
7359 // If this value is in the range [17,31] and is odd, use:
7360 // VSPLTI[bhw](val-16) - VSPLTI[bhw](-16)
7361 // If this value is in the range [-31,-17] and is odd, use:
7362 // VSPLTI[bhw](val+16) + VSPLTI[bhw](-16)
7363 // Note the last two are three-instruction sequences.
7364 if (SextVal >= -32 && SextVal <= 31) {
7365 // To avoid having these optimizations undone by constant folding,
7366 // we convert to a pseudo that will be expanded later into one of
7368 SDValue Elt = DAG.getConstant(SextVal, dl, MVT::i32);
7369 EVT VT = (SplatSize == 1 ? MVT::v16i8 :
7370 (SplatSize == 2 ? MVT::v8i16 : MVT::v4i32));
7371 SDValue EltSize = DAG.getConstant(SplatSize, dl, MVT::i32);
7372 SDValue RetVal = DAG.getNode(PPCISD::VADD_SPLAT, dl, VT, Elt, EltSize);
7373 if (VT == Op.getValueType())
7376 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), RetVal);
7379 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
7380 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
7382 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
7383 // Make -1 and vspltisw -1:
7384 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
7386 // Make the VSLW intrinsic, computing 0x8000_0000.
7387 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
7390 // xor by OnesV to invert it.
7391 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
7392 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
7395 // Check to see if this is a wide variety of vsplti*, binop self cases.
7396 static const signed char SplatCsts[] = {
7397 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
7398 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
7401 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
7402 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
7403 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
7404 int i = SplatCsts[idx];
7406 // Figure out what shift amount will be used by altivec if shifted by i in
7408 unsigned TypeShiftAmt = i & (SplatBitSize-1);
7410 // vsplti + shl self.
7411 if (SextVal == (int)((unsigned)i << TypeShiftAmt)) {
7412 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
7413 static const unsigned IIDs[] = { // Intrinsic to use for each size.
7414 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
7415 Intrinsic::ppc_altivec_vslw
7417 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
7418 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
7421 // vsplti + srl self.
7422 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
7423 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
7424 static const unsigned IIDs[] = { // Intrinsic to use for each size.
7425 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
7426 Intrinsic::ppc_altivec_vsrw
7428 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
7429 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
7432 // vsplti + sra self.
7433 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
7434 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
7435 static const unsigned IIDs[] = { // Intrinsic to use for each size.
7436 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
7437 Intrinsic::ppc_altivec_vsraw
7439 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
7440 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
7443 // vsplti + rol self.
7444 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
7445 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
7446 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
7447 static const unsigned IIDs[] = { // Intrinsic to use for each size.
7448 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
7449 Intrinsic::ppc_altivec_vrlw
7451 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
7452 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
7455 // t = vsplti c, result = vsldoi t, t, 1
7456 if (SextVal == (int)(((unsigned)i << 8) | (i < 0 ? 0xFF : 0))) {
7457 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
7458 unsigned Amt = Subtarget.isLittleEndian() ? 15 : 1;
7459 return BuildVSLDOI(T, T, Amt, Op.getValueType(), DAG, dl);
7461 // t = vsplti c, result = vsldoi t, t, 2
7462 if (SextVal == (int)(((unsigned)i << 16) | (i < 0 ? 0xFFFF : 0))) {
7463 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
7464 unsigned Amt = Subtarget.isLittleEndian() ? 14 : 2;
7465 return BuildVSLDOI(T, T, Amt, Op.getValueType(), DAG, dl);
7467 // t = vsplti c, result = vsldoi t, t, 3
7468 if (SextVal == (int)(((unsigned)i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
7469 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
7470 unsigned Amt = Subtarget.isLittleEndian() ? 13 : 3;
7471 return BuildVSLDOI(T, T, Amt, Op.getValueType(), DAG, dl);
7478 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
7479 /// the specified operations to build the shuffle.
7480 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
7481 SDValue RHS, SelectionDAG &DAG,
7483 unsigned OpNum = (PFEntry >> 26) & 0x0F;
7484 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
7485 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
7488 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
7500 if (OpNum == OP_COPY) {
7501 if (LHSID == (1*9+2)*9+3) return LHS;
7502 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
7506 SDValue OpLHS, OpRHS;
7507 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
7508 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
7512 default: llvm_unreachable("Unknown i32 permute!");
7514 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
7515 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
7516 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
7517 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
7520 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
7521 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
7522 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
7523 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
7526 for (unsigned i = 0; i != 16; ++i)
7527 ShufIdxs[i] = (i&3)+0;
7530 for (unsigned i = 0; i != 16; ++i)
7531 ShufIdxs[i] = (i&3)+4;
7534 for (unsigned i = 0; i != 16; ++i)
7535 ShufIdxs[i] = (i&3)+8;
7538 for (unsigned i = 0; i != 16; ++i)
7539 ShufIdxs[i] = (i&3)+12;
7542 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
7544 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
7546 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
7548 EVT VT = OpLHS.getValueType();
7549 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
7550 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
7551 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
7552 return DAG.getNode(ISD::BITCAST, dl, VT, T);
7555 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
7556 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
7557 /// return the code it can be lowered into. Worst case, it can always be
7558 /// lowered into a vperm.
7559 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
7560 SelectionDAG &DAG) const {
7562 SDValue V1 = Op.getOperand(0);
7563 SDValue V2 = Op.getOperand(1);
7564 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7565 EVT VT = Op.getValueType();
7566 bool isLittleEndian = Subtarget.isLittleEndian();
7568 unsigned ShiftElts, InsertAtByte;
7570 if (Subtarget.hasP9Vector() &&
7571 PPC::isXXINSERTWMask(SVOp, ShiftElts, InsertAtByte, Swap,
7575 SDValue Conv1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, V1);
7576 SDValue Conv2 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, V2);
7578 SDValue Shl = DAG.getNode(PPCISD::VECSHL, dl, MVT::v4i32, Conv2, Conv2,
7579 DAG.getConstant(ShiftElts, dl, MVT::i32));
7580 SDValue Ins = DAG.getNode(PPCISD::XXINSERT, dl, MVT::v4i32, Conv1, Shl,
7581 DAG.getConstant(InsertAtByte, dl, MVT::i32));
7582 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, Ins);
7584 SDValue Ins = DAG.getNode(PPCISD::XXINSERT, dl, MVT::v4i32, Conv1, Conv2,
7585 DAG.getConstant(InsertAtByte, dl, MVT::i32));
7586 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, Ins);
7589 if (Subtarget.hasVSX()) {
7590 if (V2.isUndef() && PPC::isSplatShuffleMask(SVOp, 4)) {
7591 int SplatIdx = PPC::getVSPLTImmediate(SVOp, 4, DAG);
7593 // If the source for the shuffle is a scalar_to_vector that came from a
7594 // 32-bit load, it will have used LXVWSX so we don't need to splat again.
7595 if (Subtarget.hasP9Vector() &&
7596 ((isLittleEndian && SplatIdx == 3) ||
7597 (!isLittleEndian && SplatIdx == 0))) {
7598 SDValue Src = V1.getOperand(0);
7599 if (Src.getOpcode() == ISD::SCALAR_TO_VECTOR &&
7600 Src.getOperand(0).getOpcode() == ISD::LOAD &&
7601 Src.getOperand(0).hasOneUse())
7604 SDValue Conv = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, V1);
7605 SDValue Splat = DAG.getNode(PPCISD::XXSPLT, dl, MVT::v4i32, Conv,
7606 DAG.getConstant(SplatIdx, dl, MVT::i32));
7607 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, Splat);
7610 // Left shifts of 8 bytes are actually swaps. Convert accordingly.
7611 if (V2.isUndef() && PPC::isVSLDOIShuffleMask(SVOp, 1, DAG) == 8) {
7612 SDValue Conv = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
7613 SDValue Swap = DAG.getNode(PPCISD::SWAP_NO_CHAIN, dl, MVT::v2f64, Conv);
7614 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, Swap);
7619 if (Subtarget.hasQPX()) {
7620 if (VT.getVectorNumElements() != 4)
7623 if (V2.isUndef()) V2 = V1;
7625 int AlignIdx = PPC::isQVALIGNIShuffleMask(SVOp);
7626 if (AlignIdx != -1) {
7627 return DAG.getNode(PPCISD::QVALIGNI, dl, VT, V1, V2,
7628 DAG.getConstant(AlignIdx, dl, MVT::i32));
7629 } else if (SVOp->isSplat()) {
7630 int SplatIdx = SVOp->getSplatIndex();
7631 if (SplatIdx >= 4) {
7636 return DAG.getNode(PPCISD::QVESPLATI, dl, VT, V1,
7637 DAG.getConstant(SplatIdx, dl, MVT::i32));
7640 // Lower this into a qvgpci/qvfperm pair.
7642 // Compute the qvgpci literal
7644 for (unsigned i = 0; i < 4; ++i) {
7645 int m = SVOp->getMaskElt(i);
7646 unsigned mm = m >= 0 ? (unsigned) m : i;
7647 idx |= mm << (3-i)*3;
7650 SDValue V3 = DAG.getNode(PPCISD::QVGPCI, dl, MVT::v4f64,
7651 DAG.getConstant(idx, dl, MVT::i32));
7652 return DAG.getNode(PPCISD::QVFPERM, dl, VT, V1, V2, V3);
7655 // Cases that are handled by instructions that take permute immediates
7656 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
7657 // selected by the instruction selector.
7659 if (PPC::isSplatShuffleMask(SVOp, 1) ||
7660 PPC::isSplatShuffleMask(SVOp, 2) ||
7661 PPC::isSplatShuffleMask(SVOp, 4) ||
7662 PPC::isVPKUWUMShuffleMask(SVOp, 1, DAG) ||
7663 PPC::isVPKUHUMShuffleMask(SVOp, 1, DAG) ||
7664 PPC::isVSLDOIShuffleMask(SVOp, 1, DAG) != -1 ||
7665 PPC::isVMRGLShuffleMask(SVOp, 1, 1, DAG) ||
7666 PPC::isVMRGLShuffleMask(SVOp, 2, 1, DAG) ||
7667 PPC::isVMRGLShuffleMask(SVOp, 4, 1, DAG) ||
7668 PPC::isVMRGHShuffleMask(SVOp, 1, 1, DAG) ||
7669 PPC::isVMRGHShuffleMask(SVOp, 2, 1, DAG) ||
7670 PPC::isVMRGHShuffleMask(SVOp, 4, 1, DAG) ||
7671 (Subtarget.hasP8Altivec() && (
7672 PPC::isVPKUDUMShuffleMask(SVOp, 1, DAG) ||
7673 PPC::isVMRGEOShuffleMask(SVOp, true, 1, DAG) ||
7674 PPC::isVMRGEOShuffleMask(SVOp, false, 1, DAG)))) {
7679 // Altivec has a variety of "shuffle immediates" that take two vector inputs
7680 // and produce a fixed permutation. If any of these match, do not lower to
7682 unsigned int ShuffleKind = isLittleEndian ? 2 : 0;
7683 if (PPC::isVPKUWUMShuffleMask(SVOp, ShuffleKind, DAG) ||
7684 PPC::isVPKUHUMShuffleMask(SVOp, ShuffleKind, DAG) ||
7685 PPC::isVSLDOIShuffleMask(SVOp, ShuffleKind, DAG) != -1 ||
7686 PPC::isVMRGLShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
7687 PPC::isVMRGLShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
7688 PPC::isVMRGLShuffleMask(SVOp, 4, ShuffleKind, DAG) ||
7689 PPC::isVMRGHShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
7690 PPC::isVMRGHShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
7691 PPC::isVMRGHShuffleMask(SVOp, 4, ShuffleKind, DAG) ||
7692 (Subtarget.hasP8Altivec() && (
7693 PPC::isVPKUDUMShuffleMask(SVOp, ShuffleKind, DAG) ||
7694 PPC::isVMRGEOShuffleMask(SVOp, true, ShuffleKind, DAG) ||
7695 PPC::isVMRGEOShuffleMask(SVOp, false, ShuffleKind, DAG))))
7698 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
7699 // perfect shuffle table to emit an optimal matching sequence.
7700 ArrayRef<int> PermMask = SVOp->getMask();
7702 unsigned PFIndexes[4];
7703 bool isFourElementShuffle = true;
7704 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
7705 unsigned EltNo = 8; // Start out undef.
7706 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
7707 if (PermMask[i*4+j] < 0)
7708 continue; // Undef, ignore it.
7710 unsigned ByteSource = PermMask[i*4+j];
7711 if ((ByteSource & 3) != j) {
7712 isFourElementShuffle = false;
7717 EltNo = ByteSource/4;
7718 } else if (EltNo != ByteSource/4) {
7719 isFourElementShuffle = false;
7723 PFIndexes[i] = EltNo;
7726 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
7727 // perfect shuffle vector to determine if it is cost effective to do this as
7728 // discrete instructions, or whether we should use a vperm.
7729 // For now, we skip this for little endian until such time as we have a
7730 // little-endian perfect shuffle table.
7731 if (isFourElementShuffle && !isLittleEndian) {
7732 // Compute the index in the perfect shuffle table.
7733 unsigned PFTableIndex =
7734 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
7736 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
7737 unsigned Cost = (PFEntry >> 30);
7739 // Determining when to avoid vperm is tricky. Many things affect the cost
7740 // of vperm, particularly how many times the perm mask needs to be computed.
7741 // For example, if the perm mask can be hoisted out of a loop or is already
7742 // used (perhaps because there are multiple permutes with the same shuffle
7743 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
7744 // the loop requires an extra register.
7746 // As a compromise, we only emit discrete instructions if the shuffle can be
7747 // generated in 3 or fewer operations. When we have loop information
7748 // available, if this block is within a loop, we should avoid using vperm
7749 // for 3-operation perms and use a constant pool load instead.
7751 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
7754 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
7755 // vector that will get spilled to the constant pool.
7756 if (V2.isUndef()) V2 = V1;
7758 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
7759 // that it is in input element units, not in bytes. Convert now.
7761 // For little endian, the order of the input vectors is reversed, and
7762 // the permutation mask is complemented with respect to 31. This is
7763 // necessary to produce proper semantics with the big-endian-biased vperm
7765 EVT EltVT = V1.getValueType().getVectorElementType();
7766 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
7768 SmallVector<SDValue, 16> ResultMask;
7769 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
7770 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
7772 for (unsigned j = 0; j != BytesPerElement; ++j)
7774 ResultMask.push_back(DAG.getConstant(31 - (SrcElt*BytesPerElement + j),
7777 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement + j, dl,
7781 SDValue VPermMask = DAG.getBuildVector(MVT::v16i8, dl, ResultMask);
7783 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
7786 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
7790 /// getVectorCompareInfo - Given an intrinsic, return false if it is not a
7791 /// vector comparison. If it is, return true and fill in Opc/isDot with
7792 /// information about the intrinsic.
7793 static bool getVectorCompareInfo(SDValue Intrin, int &CompareOpc,
7794 bool &isDot, const PPCSubtarget &Subtarget) {
7795 unsigned IntrinsicID =
7796 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
7799 switch (IntrinsicID) {
7800 default: return false;
7801 // Comparison predicates.
7802 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
7803 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
7804 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
7805 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
7806 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
7807 case Intrinsic::ppc_altivec_vcmpequd_p:
7808 if (Subtarget.hasP8Altivec()) {
7815 case Intrinsic::ppc_altivec_vcmpneb_p:
7816 case Intrinsic::ppc_altivec_vcmpneh_p:
7817 case Intrinsic::ppc_altivec_vcmpnew_p:
7818 case Intrinsic::ppc_altivec_vcmpnezb_p:
7819 case Intrinsic::ppc_altivec_vcmpnezh_p:
7820 case Intrinsic::ppc_altivec_vcmpnezw_p:
7821 if (Subtarget.hasP9Altivec()) {
7822 switch(IntrinsicID) {
7823 default: llvm_unreachable("Unknown comparison intrinsic.");
7824 case Intrinsic::ppc_altivec_vcmpneb_p: CompareOpc = 7; break;
7825 case Intrinsic::ppc_altivec_vcmpneh_p: CompareOpc = 71; break;
7826 case Intrinsic::ppc_altivec_vcmpnew_p: CompareOpc = 135; break;
7827 case Intrinsic::ppc_altivec_vcmpnezb_p: CompareOpc = 263; break;
7828 case Intrinsic::ppc_altivec_vcmpnezh_p: CompareOpc = 327; break;
7829 case Intrinsic::ppc_altivec_vcmpnezw_p: CompareOpc = 391; break;
7836 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
7837 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
7838 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
7839 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
7840 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
7841 case Intrinsic::ppc_altivec_vcmpgtsd_p:
7842 if (Subtarget.hasP8Altivec()) {
7849 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
7850 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
7851 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
7852 case Intrinsic::ppc_altivec_vcmpgtud_p:
7853 if (Subtarget.hasP8Altivec()) {
7860 // VSX predicate comparisons use the same infrastructure
7861 case Intrinsic::ppc_vsx_xvcmpeqdp_p:
7862 case Intrinsic::ppc_vsx_xvcmpgedp_p:
7863 case Intrinsic::ppc_vsx_xvcmpgtdp_p:
7864 case Intrinsic::ppc_vsx_xvcmpeqsp_p:
7865 case Intrinsic::ppc_vsx_xvcmpgesp_p:
7866 case Intrinsic::ppc_vsx_xvcmpgtsp_p:
7867 if (Subtarget.hasVSX()) {
7868 switch (IntrinsicID) {
7869 case Intrinsic::ppc_vsx_xvcmpeqdp_p: CompareOpc = 99; break;
7870 case Intrinsic::ppc_vsx_xvcmpgedp_p: CompareOpc = 115; break;
7871 case Intrinsic::ppc_vsx_xvcmpgtdp_p: CompareOpc = 107; break;
7872 case Intrinsic::ppc_vsx_xvcmpeqsp_p: CompareOpc = 67; break;
7873 case Intrinsic::ppc_vsx_xvcmpgesp_p: CompareOpc = 83; break;
7874 case Intrinsic::ppc_vsx_xvcmpgtsp_p: CompareOpc = 75; break;
7883 // Normal Comparisons.
7884 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
7885 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
7886 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
7887 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
7888 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
7889 case Intrinsic::ppc_altivec_vcmpequd:
7890 if (Subtarget.hasP8Altivec()) {
7897 case Intrinsic::ppc_altivec_vcmpneb:
7898 case Intrinsic::ppc_altivec_vcmpneh:
7899 case Intrinsic::ppc_altivec_vcmpnew:
7900 case Intrinsic::ppc_altivec_vcmpnezb:
7901 case Intrinsic::ppc_altivec_vcmpnezh:
7902 case Intrinsic::ppc_altivec_vcmpnezw:
7903 if (Subtarget.hasP9Altivec()) {
7904 switch (IntrinsicID) {
7905 default: llvm_unreachable("Unknown comparison intrinsic.");
7906 case Intrinsic::ppc_altivec_vcmpneb: CompareOpc = 7; break;
7907 case Intrinsic::ppc_altivec_vcmpneh: CompareOpc = 71; break;
7908 case Intrinsic::ppc_altivec_vcmpnew: CompareOpc = 135; break;
7909 case Intrinsic::ppc_altivec_vcmpnezb: CompareOpc = 263; break;
7910 case Intrinsic::ppc_altivec_vcmpnezh: CompareOpc = 327; break;
7911 case Intrinsic::ppc_altivec_vcmpnezw: CompareOpc = 391; break;
7917 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
7918 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
7919 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
7920 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
7921 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
7922 case Intrinsic::ppc_altivec_vcmpgtsd:
7923 if (Subtarget.hasP8Altivec()) {
7930 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
7931 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
7932 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
7933 case Intrinsic::ppc_altivec_vcmpgtud:
7934 if (Subtarget.hasP8Altivec()) {
7945 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
7946 /// lower, do it, otherwise return null.
7947 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
7948 SelectionDAG &DAG) const {
7949 unsigned IntrinsicID =
7950 cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7952 if (IntrinsicID == Intrinsic::thread_pointer) {
7953 // Reads the thread pointer register, used for __builtin_thread_pointer.
7954 bool is64bit = Subtarget.isPPC64();
7955 return DAG.getRegister(is64bit ? PPC::X13 : PPC::R2,
7956 is64bit ? MVT::i64 : MVT::i32);
7959 // If this is a lowered altivec predicate compare, CompareOpc is set to the
7960 // opcode number of the comparison.
7964 if (!getVectorCompareInfo(Op, CompareOpc, isDot, Subtarget))
7965 return SDValue(); // Don't custom lower most intrinsics.
7967 // If this is a non-dot comparison, make the VCMP node and we are done.
7969 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
7970 Op.getOperand(1), Op.getOperand(2),
7971 DAG.getConstant(CompareOpc, dl, MVT::i32));
7972 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
7975 // Create the PPCISD altivec 'dot' comparison node.
7977 Op.getOperand(2), // LHS
7978 Op.getOperand(3), // RHS
7979 DAG.getConstant(CompareOpc, dl, MVT::i32)
7981 EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue };
7982 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
7984 // Now that we have the comparison, emit a copy from the CR to a GPR.
7985 // This is flagged to the above dot comparison.
7986 SDValue Flags = DAG.getNode(PPCISD::MFOCRF, dl, MVT::i32,
7987 DAG.getRegister(PPC::CR6, MVT::i32),
7988 CompNode.getValue(1));
7990 // Unpack the result based on how the target uses it.
7991 unsigned BitNo; // Bit # of CR6.
7992 bool InvertBit; // Invert result?
7993 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
7994 default: // Can't happen, don't crash on invalid number though.
7995 case 0: // Return the value of the EQ bit of CR6.
7996 BitNo = 0; InvertBit = false;
7998 case 1: // Return the inverted value of the EQ bit of CR6.
7999 BitNo = 0; InvertBit = true;
8001 case 2: // Return the value of the LT bit of CR6.
8002 BitNo = 2; InvertBit = false;
8004 case 3: // Return the inverted value of the LT bit of CR6.
8005 BitNo = 2; InvertBit = true;
8009 // Shift the bit into the low position.
8010 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
8011 DAG.getConstant(8 - (3 - BitNo), dl, MVT::i32));
8013 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
8014 DAG.getConstant(1, dl, MVT::i32));
8016 // If we are supposed to, toggle the bit.
8018 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
8019 DAG.getConstant(1, dl, MVT::i32));
8023 SDValue PPCTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
8024 SelectionDAG &DAG) const {
8026 // For v2i64 (VSX), we can pattern patch the v2i32 case (using fp <-> int
8027 // instructions), but for smaller types, we need to first extend up to v2i32
8028 // before doing going farther.
8029 if (Op.getValueType() == MVT::v2i64) {
8030 EVT ExtVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
8031 if (ExtVT != MVT::v2i32) {
8032 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0));
8033 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32, Op,
8034 DAG.getValueType(EVT::getVectorVT(*DAG.getContext(),
8035 ExtVT.getVectorElementType(), 4)));
8036 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Op);
8037 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v2i64, Op,
8038 DAG.getValueType(MVT::v2i32));
8047 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
8048 SelectionDAG &DAG) const {
8050 // Create a stack slot that is 16-byte aligned.
8051 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
8052 int FrameIdx = MFI.CreateStackObject(16, 16, false);
8053 EVT PtrVT = getPointerTy(DAG.getDataLayout());
8054 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
8056 // Store the input value into Value#0 of the stack slot.
8057 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), FIdx,
8058 MachinePointerInfo());
8060 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo());
8063 SDValue PPCTargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
8064 SelectionDAG &DAG) const {
8065 assert(Op.getOpcode() == ISD::INSERT_VECTOR_ELT &&
8066 "Should only be called for ISD::INSERT_VECTOR_ELT");
8067 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(2));
8068 // We have legal lowering for constant indices but not for variable ones.
8074 SDValue PPCTargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
8075 SelectionDAG &DAG) const {
8077 SDNode *N = Op.getNode();
8079 assert(N->getOperand(0).getValueType() == MVT::v4i1 &&
8080 "Unknown extract_vector_elt type");
8082 SDValue Value = N->getOperand(0);
8084 // The first part of this is like the store lowering except that we don't
8085 // need to track the chain.
8087 // The values are now known to be -1 (false) or 1 (true). To convert this
8088 // into 0 (false) and 1 (true), add 1 and then divide by 2 (multiply by 0.5).
8089 // This can be done with an fma and the 0.5 constant: (V+1.0)*0.5 = 0.5*V+0.5
8090 Value = DAG.getNode(PPCISD::QBFLT, dl, MVT::v4f64, Value);
8092 // FIXME: We can make this an f32 vector, but the BUILD_VECTOR code needs to
8093 // understand how to form the extending load.
8094 SDValue FPHalfs = DAG.getConstantFP(0.5, dl, MVT::v4f64);
8096 Value = DAG.getNode(ISD::FMA, dl, MVT::v4f64, Value, FPHalfs, FPHalfs);
8098 // Now convert to an integer and store.
8099 Value = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f64,
8100 DAG.getConstant(Intrinsic::ppc_qpx_qvfctiwu, dl, MVT::i32),
8103 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
8104 int FrameIdx = MFI.CreateStackObject(16, 16, false);
8105 MachinePointerInfo PtrInfo =
8106 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx);
8107 EVT PtrVT = getPointerTy(DAG.getDataLayout());
8108 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
8110 SDValue StoreChain = DAG.getEntryNode();
8111 SDValue Ops[] = {StoreChain,
8112 DAG.getConstant(Intrinsic::ppc_qpx_qvstfiw, dl, MVT::i32),
8114 SDVTList VTs = DAG.getVTList(/*chain*/ MVT::Other);
8116 StoreChain = DAG.getMemIntrinsicNode(ISD::INTRINSIC_VOID,
8117 dl, VTs, Ops, MVT::v4i32, PtrInfo);
8119 // Extract the value requested.
8120 unsigned Offset = 4*cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
8121 SDValue Idx = DAG.getConstant(Offset, dl, FIdx.getValueType());
8122 Idx = DAG.getNode(ISD::ADD, dl, FIdx.getValueType(), FIdx, Idx);
8125 DAG.getLoad(MVT::i32, dl, StoreChain, Idx, PtrInfo.getWithOffset(Offset));
8127 if (!Subtarget.useCRBits())
8130 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, IntVal);
8133 /// Lowering for QPX v4i1 loads
8134 SDValue PPCTargetLowering::LowerVectorLoad(SDValue Op,
8135 SelectionDAG &DAG) const {
8137 LoadSDNode *LN = cast<LoadSDNode>(Op.getNode());
8138 SDValue LoadChain = LN->getChain();
8139 SDValue BasePtr = LN->getBasePtr();
8141 if (Op.getValueType() == MVT::v4f64 ||
8142 Op.getValueType() == MVT::v4f32) {
8143 EVT MemVT = LN->getMemoryVT();
8144 unsigned Alignment = LN->getAlignment();
8146 // If this load is properly aligned, then it is legal.
8147 if (Alignment >= MemVT.getStoreSize())
8150 EVT ScalarVT = Op.getValueType().getScalarType(),
8151 ScalarMemVT = MemVT.getScalarType();
8152 unsigned Stride = ScalarMemVT.getStoreSize();
8154 SDValue Vals[4], LoadChains[4];
8155 for (unsigned Idx = 0; Idx < 4; ++Idx) {
8157 if (ScalarVT != ScalarMemVT)
8158 Load = DAG.getExtLoad(LN->getExtensionType(), dl, ScalarVT, LoadChain,
8160 LN->getPointerInfo().getWithOffset(Idx * Stride),
8161 ScalarMemVT, MinAlign(Alignment, Idx * Stride),
8162 LN->getMemOperand()->getFlags(), LN->getAAInfo());
8164 Load = DAG.getLoad(ScalarVT, dl, LoadChain, BasePtr,
8165 LN->getPointerInfo().getWithOffset(Idx * Stride),
8166 MinAlign(Alignment, Idx * Stride),
8167 LN->getMemOperand()->getFlags(), LN->getAAInfo());
8169 if (Idx == 0 && LN->isIndexed()) {
8170 assert(LN->getAddressingMode() == ISD::PRE_INC &&
8171 "Unknown addressing mode on vector load");
8172 Load = DAG.getIndexedLoad(Load, dl, BasePtr, LN->getOffset(),
8173 LN->getAddressingMode());
8177 LoadChains[Idx] = Load.getValue(1);
8179 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
8180 DAG.getConstant(Stride, dl,
8181 BasePtr.getValueType()));
8184 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoadChains);
8185 SDValue Value = DAG.getBuildVector(Op.getValueType(), dl, Vals);
8187 if (LN->isIndexed()) {
8188 SDValue RetOps[] = { Value, Vals[0].getValue(1), TF };
8189 return DAG.getMergeValues(RetOps, dl);
8192 SDValue RetOps[] = { Value, TF };
8193 return DAG.getMergeValues(RetOps, dl);
8196 assert(Op.getValueType() == MVT::v4i1 && "Unknown load to lower");
8197 assert(LN->isUnindexed() && "Indexed v4i1 loads are not supported");
8199 // To lower v4i1 from a byte array, we load the byte elements of the
8200 // vector and then reuse the BUILD_VECTOR logic.
8202 SDValue VectElmts[4], VectElmtChains[4];
8203 for (unsigned i = 0; i < 4; ++i) {
8204 SDValue Idx = DAG.getConstant(i, dl, BasePtr.getValueType());
8205 Idx = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, Idx);
8207 VectElmts[i] = DAG.getExtLoad(
8208 ISD::EXTLOAD, dl, MVT::i32, LoadChain, Idx,
8209 LN->getPointerInfo().getWithOffset(i), MVT::i8,
8210 /* Alignment = */ 1, LN->getMemOperand()->getFlags(), LN->getAAInfo());
8211 VectElmtChains[i] = VectElmts[i].getValue(1);
8214 LoadChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, VectElmtChains);
8215 SDValue Value = DAG.getBuildVector(MVT::v4i1, dl, VectElmts);
8217 SDValue RVals[] = { Value, LoadChain };
8218 return DAG.getMergeValues(RVals, dl);
8221 /// Lowering for QPX v4i1 stores
8222 SDValue PPCTargetLowering::LowerVectorStore(SDValue Op,
8223 SelectionDAG &DAG) const {
8225 StoreSDNode *SN = cast<StoreSDNode>(Op.getNode());
8226 SDValue StoreChain = SN->getChain();
8227 SDValue BasePtr = SN->getBasePtr();
8228 SDValue Value = SN->getValue();
8230 if (Value.getValueType() == MVT::v4f64 ||
8231 Value.getValueType() == MVT::v4f32) {
8232 EVT MemVT = SN->getMemoryVT();
8233 unsigned Alignment = SN->getAlignment();
8235 // If this store is properly aligned, then it is legal.
8236 if (Alignment >= MemVT.getStoreSize())
8239 EVT ScalarVT = Value.getValueType().getScalarType(),
8240 ScalarMemVT = MemVT.getScalarType();
8241 unsigned Stride = ScalarMemVT.getStoreSize();
8244 for (unsigned Idx = 0; Idx < 4; ++Idx) {
8245 SDValue Ex = DAG.getNode(
8246 ISD::EXTRACT_VECTOR_ELT, dl, ScalarVT, Value,
8247 DAG.getConstant(Idx, dl, getVectorIdxTy(DAG.getDataLayout())));
8249 if (ScalarVT != ScalarMemVT)
8251 DAG.getTruncStore(StoreChain, dl, Ex, BasePtr,
8252 SN->getPointerInfo().getWithOffset(Idx * Stride),
8253 ScalarMemVT, MinAlign(Alignment, Idx * Stride),
8254 SN->getMemOperand()->getFlags(), SN->getAAInfo());
8256 Store = DAG.getStore(StoreChain, dl, Ex, BasePtr,
8257 SN->getPointerInfo().getWithOffset(Idx * Stride),
8258 MinAlign(Alignment, Idx * Stride),
8259 SN->getMemOperand()->getFlags(), SN->getAAInfo());
8261 if (Idx == 0 && SN->isIndexed()) {
8262 assert(SN->getAddressingMode() == ISD::PRE_INC &&
8263 "Unknown addressing mode on vector store");
8264 Store = DAG.getIndexedStore(Store, dl, BasePtr, SN->getOffset(),
8265 SN->getAddressingMode());
8268 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
8269 DAG.getConstant(Stride, dl,
8270 BasePtr.getValueType()));
8271 Stores[Idx] = Store;
8274 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
8276 if (SN->isIndexed()) {
8277 SDValue RetOps[] = { TF, Stores[0].getValue(1) };
8278 return DAG.getMergeValues(RetOps, dl);
8284 assert(SN->isUnindexed() && "Indexed v4i1 stores are not supported");
8285 assert(Value.getValueType() == MVT::v4i1 && "Unknown store to lower");
8287 // The values are now known to be -1 (false) or 1 (true). To convert this
8288 // into 0 (false) and 1 (true), add 1 and then divide by 2 (multiply by 0.5).
8289 // This can be done with an fma and the 0.5 constant: (V+1.0)*0.5 = 0.5*V+0.5
8290 Value = DAG.getNode(PPCISD::QBFLT, dl, MVT::v4f64, Value);
8292 // FIXME: We can make this an f32 vector, but the BUILD_VECTOR code needs to
8293 // understand how to form the extending load.
8294 SDValue FPHalfs = DAG.getConstantFP(0.5, dl, MVT::v4f64);
8296 Value = DAG.getNode(ISD::FMA, dl, MVT::v4f64, Value, FPHalfs, FPHalfs);
8298 // Now convert to an integer and store.
8299 Value = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f64,
8300 DAG.getConstant(Intrinsic::ppc_qpx_qvfctiwu, dl, MVT::i32),
8303 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
8304 int FrameIdx = MFI.CreateStackObject(16, 16, false);
8305 MachinePointerInfo PtrInfo =
8306 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx);
8307 EVT PtrVT = getPointerTy(DAG.getDataLayout());
8308 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
8310 SDValue Ops[] = {StoreChain,
8311 DAG.getConstant(Intrinsic::ppc_qpx_qvstfiw, dl, MVT::i32),
8313 SDVTList VTs = DAG.getVTList(/*chain*/ MVT::Other);
8315 StoreChain = DAG.getMemIntrinsicNode(ISD::INTRINSIC_VOID,
8316 dl, VTs, Ops, MVT::v4i32, PtrInfo);
8318 // Move data into the byte array.
8319 SDValue Loads[4], LoadChains[4];
8320 for (unsigned i = 0; i < 4; ++i) {
8321 unsigned Offset = 4*i;
8322 SDValue Idx = DAG.getConstant(Offset, dl, FIdx.getValueType());
8323 Idx = DAG.getNode(ISD::ADD, dl, FIdx.getValueType(), FIdx, Idx);
8325 Loads[i] = DAG.getLoad(MVT::i32, dl, StoreChain, Idx,
8326 PtrInfo.getWithOffset(Offset));
8327 LoadChains[i] = Loads[i].getValue(1);
8330 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoadChains);
8333 for (unsigned i = 0; i < 4; ++i) {
8334 SDValue Idx = DAG.getConstant(i, dl, BasePtr.getValueType());
8335 Idx = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, Idx);
8337 Stores[i] = DAG.getTruncStore(
8338 StoreChain, dl, Loads[i], Idx, SN->getPointerInfo().getWithOffset(i),
8339 MVT::i8, /* Alignment = */ 1, SN->getMemOperand()->getFlags(),
8343 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
8348 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
8350 if (Op.getValueType() == MVT::v4i32) {
8351 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
8353 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
8354 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
8356 SDValue RHSSwap = // = vrlw RHS, 16
8357 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
8359 // Shrinkify inputs to v8i16.
8360 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
8361 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
8362 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
8364 // Low parts multiplied together, generating 32-bit results (we ignore the
8366 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
8367 LHS, RHS, DAG, dl, MVT::v4i32);
8369 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
8370 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
8371 // Shift the high parts up 16 bits.
8372 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
8374 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
8375 } else if (Op.getValueType() == MVT::v8i16) {
8376 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
8378 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
8380 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
8381 LHS, RHS, Zero, DAG, dl);
8382 } else if (Op.getValueType() == MVT::v16i8) {
8383 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
8384 bool isLittleEndian = Subtarget.isLittleEndian();
8386 // Multiply the even 8-bit parts, producing 16-bit sums.
8387 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
8388 LHS, RHS, DAG, dl, MVT::v8i16);
8389 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
8391 // Multiply the odd 8-bit parts, producing 16-bit sums.
8392 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
8393 LHS, RHS, DAG, dl, MVT::v8i16);
8394 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
8396 // Merge the results together. Because vmuleub and vmuloub are
8397 // instructions with a big-endian bias, we must reverse the
8398 // element numbering and reverse the meaning of "odd" and "even"
8399 // when generating little endian code.
8401 for (unsigned i = 0; i != 8; ++i) {
8402 if (isLittleEndian) {
8404 Ops[i*2+1] = 2*i+16;
8407 Ops[i*2+1] = 2*i+1+16;
8411 return DAG.getVectorShuffle(MVT::v16i8, dl, OddParts, EvenParts, Ops);
8413 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
8415 llvm_unreachable("Unknown mul to lower!");
8419 /// LowerOperation - Provide custom lowering hooks for some operations.
8421 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
8422 switch (Op.getOpcode()) {
8423 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
8424 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
8425 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
8426 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
8427 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
8428 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
8429 case ISD::SETCC: return LowerSETCC(Op, DAG);
8430 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
8431 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
8433 return LowerVASTART(Op, DAG);
8436 return LowerVAARG(Op, DAG);
8439 return LowerVACOPY(Op, DAG);
8441 case ISD::STACKRESTORE:
8442 return LowerSTACKRESTORE(Op, DAG);
8444 case ISD::DYNAMIC_STACKALLOC:
8445 return LowerDYNAMIC_STACKALLOC(Op, DAG);
8447 case ISD::GET_DYNAMIC_AREA_OFFSET:
8448 return LowerGET_DYNAMIC_AREA_OFFSET(Op, DAG);
8450 case ISD::EH_DWARF_CFA:
8451 return LowerEH_DWARF_CFA(Op, DAG);
8453 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
8454 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
8456 case ISD::LOAD: return LowerLOAD(Op, DAG);
8457 case ISD::STORE: return LowerSTORE(Op, DAG);
8458 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
8459 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
8460 case ISD::FP_TO_UINT:
8461 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
8463 case ISD::UINT_TO_FP:
8464 case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
8465 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
8467 // Lower 64-bit shifts.
8468 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
8469 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
8470 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
8472 // Vector-related lowering.
8473 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
8474 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
8475 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
8476 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
8477 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
8478 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
8479 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
8480 case ISD::MUL: return LowerMUL(Op, DAG);
8482 // For counter-based loop handling.
8483 case ISD::INTRINSIC_W_CHAIN: return SDValue();
8485 // Frame & Return address.
8486 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
8487 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
8491 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
8492 SmallVectorImpl<SDValue>&Results,
8493 SelectionDAG &DAG) const {
8495 switch (N->getOpcode()) {
8497 llvm_unreachable("Do not know how to custom type legalize this operation!");
8498 case ISD::READCYCLECOUNTER: {
8499 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
8500 SDValue RTB = DAG.getNode(PPCISD::READ_TIME_BASE, dl, VTs, N->getOperand(0));
8502 Results.push_back(RTB);
8503 Results.push_back(RTB.getValue(1));
8504 Results.push_back(RTB.getValue(2));
8507 case ISD::INTRINSIC_W_CHAIN: {
8508 if (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() !=
8509 Intrinsic::ppc_is_decremented_ctr_nonzero)
8512 assert(N->getValueType(0) == MVT::i1 &&
8513 "Unexpected result type for CTR decrement intrinsic");
8514 EVT SVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
8515 N->getValueType(0));
8516 SDVTList VTs = DAG.getVTList(SVT, MVT::Other);
8517 SDValue NewInt = DAG.getNode(N->getOpcode(), dl, VTs, N->getOperand(0),
8520 Results.push_back(NewInt);
8521 Results.push_back(NewInt.getValue(1));
8525 if (!Subtarget.isSVR4ABI() || Subtarget.isPPC64())
8528 EVT VT = N->getValueType(0);
8530 if (VT == MVT::i64) {
8531 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG);
8533 Results.push_back(NewNode);
8534 Results.push_back(NewNode.getValue(1));
8538 case ISD::FP_ROUND_INREG: {
8539 assert(N->getValueType(0) == MVT::ppcf128);
8540 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
8541 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
8542 MVT::f64, N->getOperand(0),
8543 DAG.getIntPtrConstant(0, dl));
8544 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
8545 MVT::f64, N->getOperand(0),
8546 DAG.getIntPtrConstant(1, dl));
8548 // Add the two halves of the long double in round-to-zero mode.
8549 SDValue FPreg = DAG.getNode(PPCISD::FADDRTZ, dl, MVT::f64, Lo, Hi);
8551 // We know the low half is about to be thrown away, so just use something
8553 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
8557 case ISD::FP_TO_SINT:
8558 case ISD::FP_TO_UINT:
8559 // LowerFP_TO_INT() can only handle f32 and f64.
8560 if (N->getOperand(0).getValueType() == MVT::ppcf128)
8562 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
8567 //===----------------------------------------------------------------------===//
8568 // Other Lowering Code
8569 //===----------------------------------------------------------------------===//
8571 static Instruction* callIntrinsic(IRBuilder<> &Builder, Intrinsic::ID Id) {
8572 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
8573 Function *Func = Intrinsic::getDeclaration(M, Id);
8574 return Builder.CreateCall(Func, {});
8577 // The mappings for emitLeading/TrailingFence is taken from
8578 // http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
8579 Instruction* PPCTargetLowering::emitLeadingFence(IRBuilder<> &Builder,
8580 AtomicOrdering Ord, bool IsStore,
8581 bool IsLoad) const {
8582 if (Ord == AtomicOrdering::SequentiallyConsistent)
8583 return callIntrinsic(Builder, Intrinsic::ppc_sync);
8584 if (isReleaseOrStronger(Ord))
8585 return callIntrinsic(Builder, Intrinsic::ppc_lwsync);
8589 Instruction* PPCTargetLowering::emitTrailingFence(IRBuilder<> &Builder,
8590 AtomicOrdering Ord, bool IsStore,
8591 bool IsLoad) const {
8592 if (IsLoad && isAcquireOrStronger(Ord))
8593 return callIntrinsic(Builder, Intrinsic::ppc_lwsync);
8594 // FIXME: this is too conservative, a dependent branch + isync is enough.
8595 // See http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html and
8596 // http://www.rdrop.com/users/paulmck/scalability/paper/N2745r.2011.03.04a.html
8597 // and http://www.cl.cam.ac.uk/~pes20/cppppc/ for justification.
8602 PPCTargetLowering::EmitAtomicBinary(MachineInstr &MI, MachineBasicBlock *BB,
8603 unsigned AtomicSize,
8606 unsigned CmpPred) const {
8607 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
8608 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
8610 auto LoadMnemonic = PPC::LDARX;
8611 auto StoreMnemonic = PPC::STDCX;
8612 switch (AtomicSize) {
8614 llvm_unreachable("Unexpected size of atomic entity");
8616 LoadMnemonic = PPC::LBARX;
8617 StoreMnemonic = PPC::STBCX;
8618 assert(Subtarget.hasPartwordAtomics() && "Call this only with size >=4");
8621 LoadMnemonic = PPC::LHARX;
8622 StoreMnemonic = PPC::STHCX;
8623 assert(Subtarget.hasPartwordAtomics() && "Call this only with size >=4");
8626 LoadMnemonic = PPC::LWARX;
8627 StoreMnemonic = PPC::STWCX;
8630 LoadMnemonic = PPC::LDARX;
8631 StoreMnemonic = PPC::STDCX;
8635 const BasicBlock *LLVM_BB = BB->getBasicBlock();
8636 MachineFunction *F = BB->getParent();
8637 MachineFunction::iterator It = ++BB->getIterator();
8639 unsigned dest = MI.getOperand(0).getReg();
8640 unsigned ptrA = MI.getOperand(1).getReg();
8641 unsigned ptrB = MI.getOperand(2).getReg();
8642 unsigned incr = MI.getOperand(3).getReg();
8643 DebugLoc dl = MI.getDebugLoc();
8645 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
8646 MachineBasicBlock *loop2MBB =
8647 CmpOpcode ? F->CreateMachineBasicBlock(LLVM_BB) : nullptr;
8648 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
8649 F->insert(It, loopMBB);
8651 F->insert(It, loop2MBB);
8652 F->insert(It, exitMBB);
8653 exitMBB->splice(exitMBB->begin(), BB,
8654 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8655 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
8657 MachineRegisterInfo &RegInfo = F->getRegInfo();
8658 unsigned TmpReg = (!BinOpcode) ? incr :
8659 RegInfo.createVirtualRegister( AtomicSize == 8 ? &PPC::G8RCRegClass
8660 : &PPC::GPRCRegClass);
8664 // fallthrough --> loopMBB
8665 BB->addSuccessor(loopMBB);
8668 // l[wd]arx dest, ptr
8669 // add r0, dest, incr
8670 // st[wd]cx. r0, ptr
8672 // fallthrough --> exitMBB
8676 // l[wd]arx dest, ptr
8677 // cmpl?[wd] incr, dest
8680 // st[wd]cx. dest, ptr
8682 // fallthrough --> exitMBB
8685 BuildMI(BB, dl, TII->get(LoadMnemonic), dest)
8686 .addReg(ptrA).addReg(ptrB);
8688 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
8690 // Signed comparisons of byte or halfword values must be sign-extended.
8691 if (CmpOpcode == PPC::CMPW && AtomicSize < 4) {
8692 unsigned ExtReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
8693 BuildMI(BB, dl, TII->get(AtomicSize == 1 ? PPC::EXTSB : PPC::EXTSH),
8694 ExtReg).addReg(dest);
8695 BuildMI(BB, dl, TII->get(CmpOpcode), PPC::CR0)
8696 .addReg(incr).addReg(ExtReg);
8698 BuildMI(BB, dl, TII->get(CmpOpcode), PPC::CR0)
8699 .addReg(incr).addReg(dest);
8701 BuildMI(BB, dl, TII->get(PPC::BCC))
8702 .addImm(CmpPred).addReg(PPC::CR0).addMBB(exitMBB);
8703 BB->addSuccessor(loop2MBB);
8704 BB->addSuccessor(exitMBB);
8707 BuildMI(BB, dl, TII->get(StoreMnemonic))
8708 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
8709 BuildMI(BB, dl, TII->get(PPC::BCC))
8710 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
8711 BB->addSuccessor(loopMBB);
8712 BB->addSuccessor(exitMBB);
8721 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr &MI,
8722 MachineBasicBlock *BB,
8723 bool is8bit, // operation
8726 unsigned CmpPred) const {
8727 // If we support part-word atomic mnemonics, just use them
8728 if (Subtarget.hasPartwordAtomics())
8729 return EmitAtomicBinary(MI, BB, is8bit ? 1 : 2, BinOpcode,
8730 CmpOpcode, CmpPred);
8732 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
8733 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
8734 // In 64 bit mode we have to use 64 bits for addresses, even though the
8735 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
8736 // registers without caring whether they're 32 or 64, but here we're
8737 // doing actual arithmetic on the addresses.
8738 bool is64bit = Subtarget.isPPC64();
8739 bool isLittleEndian = Subtarget.isLittleEndian();
8740 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
8742 const BasicBlock *LLVM_BB = BB->getBasicBlock();
8743 MachineFunction *F = BB->getParent();
8744 MachineFunction::iterator It = ++BB->getIterator();
8746 unsigned dest = MI.getOperand(0).getReg();
8747 unsigned ptrA = MI.getOperand(1).getReg();
8748 unsigned ptrB = MI.getOperand(2).getReg();
8749 unsigned incr = MI.getOperand(3).getReg();
8750 DebugLoc dl = MI.getDebugLoc();
8752 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
8753 MachineBasicBlock *loop2MBB =
8754 CmpOpcode ? F->CreateMachineBasicBlock(LLVM_BB) : nullptr;
8755 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
8756 F->insert(It, loopMBB);
8758 F->insert(It, loop2MBB);
8759 F->insert(It, exitMBB);
8760 exitMBB->splice(exitMBB->begin(), BB,
8761 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8762 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
8764 MachineRegisterInfo &RegInfo = F->getRegInfo();
8765 const TargetRegisterClass *RC = is64bit ? &PPC::G8RCRegClass
8766 : &PPC::GPRCRegClass;
8767 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
8768 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
8770 isLittleEndian ? Shift1Reg : RegInfo.createVirtualRegister(RC);
8771 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
8772 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
8773 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
8774 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
8775 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
8776 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
8777 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
8778 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
8780 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
8784 // fallthrough --> loopMBB
8785 BB->addSuccessor(loopMBB);
8787 // The 4-byte load must be aligned, while a char or short may be
8788 // anywhere in the word. Hence all this nasty bookkeeping code.
8789 // add ptr1, ptrA, ptrB [copy if ptrA==0]
8790 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
8791 // xori shift, shift1, 24 [16]
8792 // rlwinm ptr, ptr1, 0, 0, 29
8793 // slw incr2, incr, shift
8794 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
8795 // slw mask, mask2, shift
8797 // lwarx tmpDest, ptr
8798 // add tmp, tmpDest, incr2
8799 // andc tmp2, tmpDest, mask
8800 // and tmp3, tmp, mask
8801 // or tmp4, tmp3, tmp2
8804 // fallthrough --> exitMBB
8805 // srw dest, tmpDest, shift
8806 if (ptrA != ZeroReg) {
8807 Ptr1Reg = RegInfo.createVirtualRegister(RC);
8808 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
8809 .addReg(ptrA).addReg(ptrB);
8813 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
8814 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
8815 if (!isLittleEndian)
8816 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
8817 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
8819 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
8820 .addReg(Ptr1Reg).addImm(0).addImm(61);
8822 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
8823 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
8824 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
8825 .addReg(incr).addReg(ShiftReg);
8827 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
8829 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
8830 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
8832 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
8833 .addReg(Mask2Reg).addReg(ShiftReg);
8836 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
8837 .addReg(ZeroReg).addReg(PtrReg);
8839 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
8840 .addReg(Incr2Reg).addReg(TmpDestReg);
8841 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
8842 .addReg(TmpDestReg).addReg(MaskReg);
8843 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
8844 .addReg(TmpReg).addReg(MaskReg);
8846 // For unsigned comparisons, we can directly compare the shifted values.
8847 // For signed comparisons we shift and sign extend.
8848 unsigned SReg = RegInfo.createVirtualRegister(RC);
8849 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), SReg)
8850 .addReg(TmpDestReg).addReg(MaskReg);
8851 unsigned ValueReg = SReg;
8852 unsigned CmpReg = Incr2Reg;
8853 if (CmpOpcode == PPC::CMPW) {
8854 ValueReg = RegInfo.createVirtualRegister(RC);
8855 BuildMI(BB, dl, TII->get(PPC::SRW), ValueReg)
8856 .addReg(SReg).addReg(ShiftReg);
8857 unsigned ValueSReg = RegInfo.createVirtualRegister(RC);
8858 BuildMI(BB, dl, TII->get(is8bit ? PPC::EXTSB : PPC::EXTSH), ValueSReg)
8860 ValueReg = ValueSReg;
8863 BuildMI(BB, dl, TII->get(CmpOpcode), PPC::CR0)
8864 .addReg(CmpReg).addReg(ValueReg);
8865 BuildMI(BB, dl, TII->get(PPC::BCC))
8866 .addImm(CmpPred).addReg(PPC::CR0).addMBB(exitMBB);
8867 BB->addSuccessor(loop2MBB);
8868 BB->addSuccessor(exitMBB);
8871 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
8872 .addReg(Tmp3Reg).addReg(Tmp2Reg);
8873 BuildMI(BB, dl, TII->get(PPC::STWCX))
8874 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
8875 BuildMI(BB, dl, TII->get(PPC::BCC))
8876 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
8877 BB->addSuccessor(loopMBB);
8878 BB->addSuccessor(exitMBB);
8883 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg)
8888 llvm::MachineBasicBlock *
8889 PPCTargetLowering::emitEHSjLjSetJmp(MachineInstr &MI,
8890 MachineBasicBlock *MBB) const {
8891 DebugLoc DL = MI.getDebugLoc();
8892 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
8894 MachineFunction *MF = MBB->getParent();
8895 MachineRegisterInfo &MRI = MF->getRegInfo();
8897 const BasicBlock *BB = MBB->getBasicBlock();
8898 MachineFunction::iterator I = ++MBB->getIterator();
8901 MachineInstr::mmo_iterator MMOBegin = MI.memoperands_begin();
8902 MachineInstr::mmo_iterator MMOEnd = MI.memoperands_end();
8904 unsigned DstReg = MI.getOperand(0).getReg();
8905 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
8906 assert(RC->hasType(MVT::i32) && "Invalid destination!");
8907 unsigned mainDstReg = MRI.createVirtualRegister(RC);
8908 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
8910 MVT PVT = getPointerTy(MF->getDataLayout());
8911 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
8912 "Invalid Pointer Size!");
8913 // For v = setjmp(buf), we generate
8916 // SjLjSetup mainMBB
8922 // buf[LabelOffset] = LR
8926 // v = phi(main, restore)
8929 MachineBasicBlock *thisMBB = MBB;
8930 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
8931 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
8932 MF->insert(I, mainMBB);
8933 MF->insert(I, sinkMBB);
8935 MachineInstrBuilder MIB;
8937 // Transfer the remainder of BB and its successor edges to sinkMBB.
8938 sinkMBB->splice(sinkMBB->begin(), MBB,
8939 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
8940 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
8942 // Note that the structure of the jmp_buf used here is not compatible
8943 // with that used by libc, and is not designed to be. Specifically, it
8944 // stores only those 'reserved' registers that LLVM does not otherwise
8945 // understand how to spill. Also, by convention, by the time this
8946 // intrinsic is called, Clang has already stored the frame address in the
8947 // first slot of the buffer and stack address in the third. Following the
8948 // X86 target code, we'll store the jump address in the second slot. We also
8949 // need to save the TOC pointer (R2) to handle jumps between shared
8950 // libraries, and that will be stored in the fourth slot. The thread
8951 // identifier (R13) is not affected.
8954 const int64_t LabelOffset = 1 * PVT.getStoreSize();
8955 const int64_t TOCOffset = 3 * PVT.getStoreSize();
8956 const int64_t BPOffset = 4 * PVT.getStoreSize();
8958 // Prepare IP either in reg.
8959 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
8960 unsigned LabelReg = MRI.createVirtualRegister(PtrRC);
8961 unsigned BufReg = MI.getOperand(1).getReg();
8963 if (Subtarget.isPPC64() && Subtarget.isSVR4ABI()) {
8964 setUsesTOCBasePtr(*MBB->getParent());
8965 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::STD))
8969 MIB.setMemRefs(MMOBegin, MMOEnd);
8972 // Naked functions never have a base pointer, and so we use r1. For all
8973 // other functions, this decision must be delayed until during PEI.
8975 if (MF->getFunction()->hasFnAttribute(Attribute::Naked))
8976 BaseReg = Subtarget.isPPC64() ? PPC::X1 : PPC::R1;
8978 BaseReg = Subtarget.isPPC64() ? PPC::BP8 : PPC::BP;
8980 MIB = BuildMI(*thisMBB, MI, DL,
8981 TII->get(Subtarget.isPPC64() ? PPC::STD : PPC::STW))
8985 MIB.setMemRefs(MMOBegin, MMOEnd);
8988 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::BCLalways)).addMBB(mainMBB);
8989 const PPCRegisterInfo *TRI = Subtarget.getRegisterInfo();
8990 MIB.addRegMask(TRI->getNoPreservedMask());
8992 BuildMI(*thisMBB, MI, DL, TII->get(PPC::LI), restoreDstReg).addImm(1);
8994 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::EH_SjLj_Setup))
8996 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::B)).addMBB(sinkMBB);
8998 thisMBB->addSuccessor(mainMBB, BranchProbability::getZero());
8999 thisMBB->addSuccessor(sinkMBB, BranchProbability::getOne());
9004 BuildMI(mainMBB, DL,
9005 TII->get(Subtarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg);
9008 if (Subtarget.isPPC64()) {
9009 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STD))
9011 .addImm(LabelOffset)
9014 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STW))
9016 .addImm(LabelOffset)
9020 MIB.setMemRefs(MMOBegin, MMOEnd);
9022 BuildMI(mainMBB, DL, TII->get(PPC::LI), mainDstReg).addImm(0);
9023 mainMBB->addSuccessor(sinkMBB);
9026 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
9027 TII->get(PPC::PHI), DstReg)
9028 .addReg(mainDstReg).addMBB(mainMBB)
9029 .addReg(restoreDstReg).addMBB(thisMBB);
9031 MI.eraseFromParent();
9036 PPCTargetLowering::emitEHSjLjLongJmp(MachineInstr &MI,
9037 MachineBasicBlock *MBB) const {
9038 DebugLoc DL = MI.getDebugLoc();
9039 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
9041 MachineFunction *MF = MBB->getParent();
9042 MachineRegisterInfo &MRI = MF->getRegInfo();
9045 MachineInstr::mmo_iterator MMOBegin = MI.memoperands_begin();
9046 MachineInstr::mmo_iterator MMOEnd = MI.memoperands_end();
9048 MVT PVT = getPointerTy(MF->getDataLayout());
9049 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
9050 "Invalid Pointer Size!");
9052 const TargetRegisterClass *RC =
9053 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
9054 unsigned Tmp = MRI.createVirtualRegister(RC);
9055 // Since FP is only updated here but NOT referenced, it's treated as GPR.
9056 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
9057 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
9061 : (Subtarget.isSVR4ABI() && isPositionIndependent() ? PPC::R29
9064 MachineInstrBuilder MIB;
9066 const int64_t LabelOffset = 1 * PVT.getStoreSize();
9067 const int64_t SPOffset = 2 * PVT.getStoreSize();
9068 const int64_t TOCOffset = 3 * PVT.getStoreSize();
9069 const int64_t BPOffset = 4 * PVT.getStoreSize();
9071 unsigned BufReg = MI.getOperand(0).getReg();
9073 // Reload FP (the jumped-to function may not have had a
9074 // frame pointer, and if so, then its r31 will be restored
9076 if (PVT == MVT::i64) {
9077 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), FP)
9081 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), FP)
9085 MIB.setMemRefs(MMOBegin, MMOEnd);
9088 if (PVT == MVT::i64) {
9089 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), Tmp)
9090 .addImm(LabelOffset)
9093 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), Tmp)
9094 .addImm(LabelOffset)
9097 MIB.setMemRefs(MMOBegin, MMOEnd);
9100 if (PVT == MVT::i64) {
9101 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), SP)
9105 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), SP)
9109 MIB.setMemRefs(MMOBegin, MMOEnd);
9112 if (PVT == MVT::i64) {
9113 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), BP)
9117 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), BP)
9121 MIB.setMemRefs(MMOBegin, MMOEnd);
9124 if (PVT == MVT::i64 && Subtarget.isSVR4ABI()) {
9125 setUsesTOCBasePtr(*MBB->getParent());
9126 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), PPC::X2)
9130 MIB.setMemRefs(MMOBegin, MMOEnd);
9134 BuildMI(*MBB, MI, DL,
9135 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
9136 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));
9138 MI.eraseFromParent();
9143 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
9144 MachineBasicBlock *BB) const {
9145 if (MI.getOpcode() == TargetOpcode::STACKMAP ||
9146 MI.getOpcode() == TargetOpcode::PATCHPOINT) {
9147 if (Subtarget.isPPC64() && Subtarget.isSVR4ABI() &&
9148 MI.getOpcode() == TargetOpcode::PATCHPOINT) {
9149 // Call lowering should have added an r2 operand to indicate a dependence
9150 // on the TOC base pointer value. It can't however, because there is no
9151 // way to mark the dependence as implicit there, and so the stackmap code
9152 // will confuse it with a regular operand. Instead, add the dependence
9154 setUsesTOCBasePtr(*BB->getParent());
9155 MI.addOperand(MachineOperand::CreateReg(PPC::X2, false, true));
9158 return emitPatchPoint(MI, BB);
9161 if (MI.getOpcode() == PPC::EH_SjLj_SetJmp32 ||
9162 MI.getOpcode() == PPC::EH_SjLj_SetJmp64) {
9163 return emitEHSjLjSetJmp(MI, BB);
9164 } else if (MI.getOpcode() == PPC::EH_SjLj_LongJmp32 ||
9165 MI.getOpcode() == PPC::EH_SjLj_LongJmp64) {
9166 return emitEHSjLjLongJmp(MI, BB);
9169 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
9171 // To "insert" these instructions we actually have to insert their
9172 // control-flow patterns.
9173 const BasicBlock *LLVM_BB = BB->getBasicBlock();
9174 MachineFunction::iterator It = ++BB->getIterator();
9176 MachineFunction *F = BB->getParent();
9178 if (Subtarget.hasISEL() &&
9179 (MI.getOpcode() == PPC::SELECT_CC_I4 ||
9180 MI.getOpcode() == PPC::SELECT_CC_I8 ||
9181 MI.getOpcode() == PPC::SELECT_I4 || MI.getOpcode() == PPC::SELECT_I8)) {
9182 SmallVector<MachineOperand, 2> Cond;
9183 if (MI.getOpcode() == PPC::SELECT_CC_I4 ||
9184 MI.getOpcode() == PPC::SELECT_CC_I8)
9185 Cond.push_back(MI.getOperand(4));
9187 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
9188 Cond.push_back(MI.getOperand(1));
9190 DebugLoc dl = MI.getDebugLoc();
9191 TII->insertSelect(*BB, MI, dl, MI.getOperand(0).getReg(), Cond,
9192 MI.getOperand(2).getReg(), MI.getOperand(3).getReg());
9193 } else if (MI.getOpcode() == PPC::SELECT_CC_I4 ||
9194 MI.getOpcode() == PPC::SELECT_CC_I8 ||
9195 MI.getOpcode() == PPC::SELECT_CC_F4 ||
9196 MI.getOpcode() == PPC::SELECT_CC_F8 ||
9197 MI.getOpcode() == PPC::SELECT_CC_QFRC ||
9198 MI.getOpcode() == PPC::SELECT_CC_QSRC ||
9199 MI.getOpcode() == PPC::SELECT_CC_QBRC ||
9200 MI.getOpcode() == PPC::SELECT_CC_VRRC ||
9201 MI.getOpcode() == PPC::SELECT_CC_VSFRC ||
9202 MI.getOpcode() == PPC::SELECT_CC_VSSRC ||
9203 MI.getOpcode() == PPC::SELECT_CC_VSRC ||
9204 MI.getOpcode() == PPC::SELECT_I4 ||
9205 MI.getOpcode() == PPC::SELECT_I8 ||
9206 MI.getOpcode() == PPC::SELECT_F4 ||
9207 MI.getOpcode() == PPC::SELECT_F8 ||
9208 MI.getOpcode() == PPC::SELECT_QFRC ||
9209 MI.getOpcode() == PPC::SELECT_QSRC ||
9210 MI.getOpcode() == PPC::SELECT_QBRC ||
9211 MI.getOpcode() == PPC::SELECT_VRRC ||
9212 MI.getOpcode() == PPC::SELECT_VSFRC ||
9213 MI.getOpcode() == PPC::SELECT_VSSRC ||
9214 MI.getOpcode() == PPC::SELECT_VSRC) {
9215 // The incoming instruction knows the destination vreg to set, the
9216 // condition code register to branch on, the true/false values to
9217 // select between, and a branch opcode to use.
9222 // cmpTY ccX, r1, r2
9224 // fallthrough --> copy0MBB
9225 MachineBasicBlock *thisMBB = BB;
9226 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
9227 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
9228 DebugLoc dl = MI.getDebugLoc();
9229 F->insert(It, copy0MBB);
9230 F->insert(It, sinkMBB);
9232 // Transfer the remainder of BB and its successor edges to sinkMBB.
9233 sinkMBB->splice(sinkMBB->begin(), BB,
9234 std::next(MachineBasicBlock::iterator(MI)), BB->end());
9235 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
9237 // Next, add the true and fallthrough blocks as its successors.
9238 BB->addSuccessor(copy0MBB);
9239 BB->addSuccessor(sinkMBB);
9241 if (MI.getOpcode() == PPC::SELECT_I4 || MI.getOpcode() == PPC::SELECT_I8 ||
9242 MI.getOpcode() == PPC::SELECT_F4 || MI.getOpcode() == PPC::SELECT_F8 ||
9243 MI.getOpcode() == PPC::SELECT_QFRC ||
9244 MI.getOpcode() == PPC::SELECT_QSRC ||
9245 MI.getOpcode() == PPC::SELECT_QBRC ||
9246 MI.getOpcode() == PPC::SELECT_VRRC ||
9247 MI.getOpcode() == PPC::SELECT_VSFRC ||
9248 MI.getOpcode() == PPC::SELECT_VSSRC ||
9249 MI.getOpcode() == PPC::SELECT_VSRC) {
9250 BuildMI(BB, dl, TII->get(PPC::BC))
9251 .addReg(MI.getOperand(1).getReg())
9254 unsigned SelectPred = MI.getOperand(4).getImm();
9255 BuildMI(BB, dl, TII->get(PPC::BCC))
9257 .addReg(MI.getOperand(1).getReg())
9262 // %FalseValue = ...
9263 // # fallthrough to sinkMBB
9266 // Update machine-CFG edges
9267 BB->addSuccessor(sinkMBB);
9270 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
9273 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::PHI), MI.getOperand(0).getReg())
9274 .addReg(MI.getOperand(3).getReg())
9276 .addReg(MI.getOperand(2).getReg())
9278 } else if (MI.getOpcode() == PPC::ReadTB) {
9279 // To read the 64-bit time-base register on a 32-bit target, we read the
9280 // two halves. Should the counter have wrapped while it was being read, we
9281 // need to try again.
9284 // mfspr Rx,TBU # load from TBU
9285 // mfspr Ry,TB # load from TB
9286 // mfspr Rz,TBU # load from TBU
9287 // cmpw crX,Rx,Rz # check if 'old'='new'
9288 // bne readLoop # branch if they're not equal
9291 MachineBasicBlock *readMBB = F->CreateMachineBasicBlock(LLVM_BB);
9292 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
9293 DebugLoc dl = MI.getDebugLoc();
9294 F->insert(It, readMBB);
9295 F->insert(It, sinkMBB);
9297 // Transfer the remainder of BB and its successor edges to sinkMBB.
9298 sinkMBB->splice(sinkMBB->begin(), BB,
9299 std::next(MachineBasicBlock::iterator(MI)), BB->end());
9300 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
9302 BB->addSuccessor(readMBB);
9305 MachineRegisterInfo &RegInfo = F->getRegInfo();
9306 unsigned ReadAgainReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
9307 unsigned LoReg = MI.getOperand(0).getReg();
9308 unsigned HiReg = MI.getOperand(1).getReg();
9310 BuildMI(BB, dl, TII->get(PPC::MFSPR), HiReg).addImm(269);
9311 BuildMI(BB, dl, TII->get(PPC::MFSPR), LoReg).addImm(268);
9312 BuildMI(BB, dl, TII->get(PPC::MFSPR), ReadAgainReg).addImm(269);
9314 unsigned CmpReg = RegInfo.createVirtualRegister(&PPC::CRRCRegClass);
9316 BuildMI(BB, dl, TII->get(PPC::CMPW), CmpReg)
9317 .addReg(HiReg).addReg(ReadAgainReg);
9318 BuildMI(BB, dl, TII->get(PPC::BCC))
9319 .addImm(PPC::PRED_NE).addReg(CmpReg).addMBB(readMBB);
9321 BB->addSuccessor(readMBB);
9322 BB->addSuccessor(sinkMBB);
9323 } else if (MI.getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
9324 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
9325 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
9326 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
9327 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
9328 BB = EmitAtomicBinary(MI, BB, 4, PPC::ADD4);
9329 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
9330 BB = EmitAtomicBinary(MI, BB, 8, PPC::ADD8);
9332 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
9333 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
9334 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
9335 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
9336 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
9337 BB = EmitAtomicBinary(MI, BB, 4, PPC::AND);
9338 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
9339 BB = EmitAtomicBinary(MI, BB, 8, PPC::AND8);
9341 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
9342 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
9343 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
9344 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
9345 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
9346 BB = EmitAtomicBinary(MI, BB, 4, PPC::OR);
9347 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
9348 BB = EmitAtomicBinary(MI, BB, 8, PPC::OR8);
9350 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
9351 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
9352 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
9353 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
9354 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
9355 BB = EmitAtomicBinary(MI, BB, 4, PPC::XOR);
9356 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
9357 BB = EmitAtomicBinary(MI, BB, 8, PPC::XOR8);
9359 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
9360 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::NAND);
9361 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
9362 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::NAND);
9363 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
9364 BB = EmitAtomicBinary(MI, BB, 4, PPC::NAND);
9365 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
9366 BB = EmitAtomicBinary(MI, BB, 8, PPC::NAND8);
9368 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
9369 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
9370 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
9371 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
9372 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
9373 BB = EmitAtomicBinary(MI, BB, 4, PPC::SUBF);
9374 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
9375 BB = EmitAtomicBinary(MI, BB, 8, PPC::SUBF8);
9377 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_MIN_I8)
9378 BB = EmitPartwordAtomicBinary(MI, BB, true, 0, PPC::CMPW, PPC::PRED_GE);
9379 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_MIN_I16)
9380 BB = EmitPartwordAtomicBinary(MI, BB, false, 0, PPC::CMPW, PPC::PRED_GE);
9381 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_MIN_I32)
9382 BB = EmitAtomicBinary(MI, BB, 4, 0, PPC::CMPW, PPC::PRED_GE);
9383 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_MIN_I64)
9384 BB = EmitAtomicBinary(MI, BB, 8, 0, PPC::CMPD, PPC::PRED_GE);
9386 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_MAX_I8)
9387 BB = EmitPartwordAtomicBinary(MI, BB, true, 0, PPC::CMPW, PPC::PRED_LE);
9388 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_MAX_I16)
9389 BB = EmitPartwordAtomicBinary(MI, BB, false, 0, PPC::CMPW, PPC::PRED_LE);
9390 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_MAX_I32)
9391 BB = EmitAtomicBinary(MI, BB, 4, 0, PPC::CMPW, PPC::PRED_LE);
9392 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_MAX_I64)
9393 BB = EmitAtomicBinary(MI, BB, 8, 0, PPC::CMPD, PPC::PRED_LE);
9395 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_UMIN_I8)
9396 BB = EmitPartwordAtomicBinary(MI, BB, true, 0, PPC::CMPLW, PPC::PRED_GE);
9397 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_UMIN_I16)
9398 BB = EmitPartwordAtomicBinary(MI, BB, false, 0, PPC::CMPLW, PPC::PRED_GE);
9399 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_UMIN_I32)
9400 BB = EmitAtomicBinary(MI, BB, 4, 0, PPC::CMPLW, PPC::PRED_GE);
9401 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_UMIN_I64)
9402 BB = EmitAtomicBinary(MI, BB, 8, 0, PPC::CMPLD, PPC::PRED_GE);
9404 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_UMAX_I8)
9405 BB = EmitPartwordAtomicBinary(MI, BB, true, 0, PPC::CMPLW, PPC::PRED_LE);
9406 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_UMAX_I16)
9407 BB = EmitPartwordAtomicBinary(MI, BB, false, 0, PPC::CMPLW, PPC::PRED_LE);
9408 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_UMAX_I32)
9409 BB = EmitAtomicBinary(MI, BB, 4, 0, PPC::CMPLW, PPC::PRED_LE);
9410 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_UMAX_I64)
9411 BB = EmitAtomicBinary(MI, BB, 8, 0, PPC::CMPLD, PPC::PRED_LE);
9413 else if (MI.getOpcode() == PPC::ATOMIC_SWAP_I8)
9414 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
9415 else if (MI.getOpcode() == PPC::ATOMIC_SWAP_I16)
9416 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
9417 else if (MI.getOpcode() == PPC::ATOMIC_SWAP_I32)
9418 BB = EmitAtomicBinary(MI, BB, 4, 0);
9419 else if (MI.getOpcode() == PPC::ATOMIC_SWAP_I64)
9420 BB = EmitAtomicBinary(MI, BB, 8, 0);
9422 else if (MI.getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
9423 MI.getOpcode() == PPC::ATOMIC_CMP_SWAP_I64 ||
9424 (Subtarget.hasPartwordAtomics() &&
9425 MI.getOpcode() == PPC::ATOMIC_CMP_SWAP_I8) ||
9426 (Subtarget.hasPartwordAtomics() &&
9427 MI.getOpcode() == PPC::ATOMIC_CMP_SWAP_I16)) {
9428 bool is64bit = MI.getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
9430 auto LoadMnemonic = PPC::LDARX;
9431 auto StoreMnemonic = PPC::STDCX;
9432 switch (MI.getOpcode()) {
9434 llvm_unreachable("Compare and swap of unknown size");
9435 case PPC::ATOMIC_CMP_SWAP_I8:
9436 LoadMnemonic = PPC::LBARX;
9437 StoreMnemonic = PPC::STBCX;
9438 assert(Subtarget.hasPartwordAtomics() && "No support partword atomics.");
9440 case PPC::ATOMIC_CMP_SWAP_I16:
9441 LoadMnemonic = PPC::LHARX;
9442 StoreMnemonic = PPC::STHCX;
9443 assert(Subtarget.hasPartwordAtomics() && "No support partword atomics.");
9445 case PPC::ATOMIC_CMP_SWAP_I32:
9446 LoadMnemonic = PPC::LWARX;
9447 StoreMnemonic = PPC::STWCX;
9449 case PPC::ATOMIC_CMP_SWAP_I64:
9450 LoadMnemonic = PPC::LDARX;
9451 StoreMnemonic = PPC::STDCX;
9454 unsigned dest = MI.getOperand(0).getReg();
9455 unsigned ptrA = MI.getOperand(1).getReg();
9456 unsigned ptrB = MI.getOperand(2).getReg();
9457 unsigned oldval = MI.getOperand(3).getReg();
9458 unsigned newval = MI.getOperand(4).getReg();
9459 DebugLoc dl = MI.getDebugLoc();
9461 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
9462 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
9463 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
9464 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
9465 F->insert(It, loop1MBB);
9466 F->insert(It, loop2MBB);
9467 F->insert(It, midMBB);
9468 F->insert(It, exitMBB);
9469 exitMBB->splice(exitMBB->begin(), BB,
9470 std::next(MachineBasicBlock::iterator(MI)), BB->end());
9471 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
9475 // fallthrough --> loopMBB
9476 BB->addSuccessor(loop1MBB);
9479 // l[bhwd]arx dest, ptr
9480 // cmp[wd] dest, oldval
9483 // st[bhwd]cx. newval, ptr
9487 // st[bhwd]cx. dest, ptr
9490 BuildMI(BB, dl, TII->get(LoadMnemonic), dest)
9491 .addReg(ptrA).addReg(ptrB);
9492 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
9493 .addReg(oldval).addReg(dest);
9494 BuildMI(BB, dl, TII->get(PPC::BCC))
9495 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
9496 BB->addSuccessor(loop2MBB);
9497 BB->addSuccessor(midMBB);
9500 BuildMI(BB, dl, TII->get(StoreMnemonic))
9501 .addReg(newval).addReg(ptrA).addReg(ptrB);
9502 BuildMI(BB, dl, TII->get(PPC::BCC))
9503 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
9504 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
9505 BB->addSuccessor(loop1MBB);
9506 BB->addSuccessor(exitMBB);
9509 BuildMI(BB, dl, TII->get(StoreMnemonic))
9510 .addReg(dest).addReg(ptrA).addReg(ptrB);
9511 BB->addSuccessor(exitMBB);
9516 } else if (MI.getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
9517 MI.getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
9518 // We must use 64-bit registers for addresses when targeting 64-bit,
9519 // since we're actually doing arithmetic on them. Other registers
9521 bool is64bit = Subtarget.isPPC64();
9522 bool isLittleEndian = Subtarget.isLittleEndian();
9523 bool is8bit = MI.getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
9525 unsigned dest = MI.getOperand(0).getReg();
9526 unsigned ptrA = MI.getOperand(1).getReg();
9527 unsigned ptrB = MI.getOperand(2).getReg();
9528 unsigned oldval = MI.getOperand(3).getReg();
9529 unsigned newval = MI.getOperand(4).getReg();
9530 DebugLoc dl = MI.getDebugLoc();
9532 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
9533 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
9534 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
9535 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
9536 F->insert(It, loop1MBB);
9537 F->insert(It, loop2MBB);
9538 F->insert(It, midMBB);
9539 F->insert(It, exitMBB);
9540 exitMBB->splice(exitMBB->begin(), BB,
9541 std::next(MachineBasicBlock::iterator(MI)), BB->end());
9542 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
9544 MachineRegisterInfo &RegInfo = F->getRegInfo();
9545 const TargetRegisterClass *RC = is64bit ? &PPC::G8RCRegClass
9546 : &PPC::GPRCRegClass;
9547 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
9548 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
9550 isLittleEndian ? Shift1Reg : RegInfo.createVirtualRegister(RC);
9551 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
9552 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
9553 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
9554 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
9555 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
9556 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
9557 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
9558 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
9559 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
9560 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
9562 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
9563 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
9566 // fallthrough --> loopMBB
9567 BB->addSuccessor(loop1MBB);
9569 // The 4-byte load must be aligned, while a char or short may be
9570 // anywhere in the word. Hence all this nasty bookkeeping code.
9571 // add ptr1, ptrA, ptrB [copy if ptrA==0]
9572 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
9573 // xori shift, shift1, 24 [16]
9574 // rlwinm ptr, ptr1, 0, 0, 29
9575 // slw newval2, newval, shift
9576 // slw oldval2, oldval,shift
9577 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
9578 // slw mask, mask2, shift
9579 // and newval3, newval2, mask
9580 // and oldval3, oldval2, mask
9582 // lwarx tmpDest, ptr
9583 // and tmp, tmpDest, mask
9584 // cmpw tmp, oldval3
9587 // andc tmp2, tmpDest, mask
9588 // or tmp4, tmp2, newval3
9593 // stwcx. tmpDest, ptr
9595 // srw dest, tmpDest, shift
9596 if (ptrA != ZeroReg) {
9597 Ptr1Reg = RegInfo.createVirtualRegister(RC);
9598 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
9599 .addReg(ptrA).addReg(ptrB);
9603 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
9604 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
9605 if (!isLittleEndian)
9606 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
9607 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
9609 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
9610 .addReg(Ptr1Reg).addImm(0).addImm(61);
9612 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
9613 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
9614 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
9615 .addReg(newval).addReg(ShiftReg);
9616 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
9617 .addReg(oldval).addReg(ShiftReg);
9619 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
9621 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
9622 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
9623 .addReg(Mask3Reg).addImm(65535);
9625 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
9626 .addReg(Mask2Reg).addReg(ShiftReg);
9627 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
9628 .addReg(NewVal2Reg).addReg(MaskReg);
9629 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
9630 .addReg(OldVal2Reg).addReg(MaskReg);
9633 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
9634 .addReg(ZeroReg).addReg(PtrReg);
9635 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
9636 .addReg(TmpDestReg).addReg(MaskReg);
9637 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
9638 .addReg(TmpReg).addReg(OldVal3Reg);
9639 BuildMI(BB, dl, TII->get(PPC::BCC))
9640 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
9641 BB->addSuccessor(loop2MBB);
9642 BB->addSuccessor(midMBB);
9645 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
9646 .addReg(TmpDestReg).addReg(MaskReg);
9647 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
9648 .addReg(Tmp2Reg).addReg(NewVal3Reg);
9649 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
9650 .addReg(ZeroReg).addReg(PtrReg);
9651 BuildMI(BB, dl, TII->get(PPC::BCC))
9652 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
9653 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
9654 BB->addSuccessor(loop1MBB);
9655 BB->addSuccessor(exitMBB);
9658 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
9659 .addReg(ZeroReg).addReg(PtrReg);
9660 BB->addSuccessor(exitMBB);
9665 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg)
9667 } else if (MI.getOpcode() == PPC::FADDrtz) {
9668 // This pseudo performs an FADD with rounding mode temporarily forced
9669 // to round-to-zero. We emit this via custom inserter since the FPSCR
9670 // is not modeled at the SelectionDAG level.
9671 unsigned Dest = MI.getOperand(0).getReg();
9672 unsigned Src1 = MI.getOperand(1).getReg();
9673 unsigned Src2 = MI.getOperand(2).getReg();
9674 DebugLoc dl = MI.getDebugLoc();
9676 MachineRegisterInfo &RegInfo = F->getRegInfo();
9677 unsigned MFFSReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
9679 // Save FPSCR value.
9680 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), MFFSReg);
9682 // Set rounding mode to round-to-zero.
9683 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB1)).addImm(31);
9684 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB0)).addImm(30);
9686 // Perform addition.
9687 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);
9689 // Restore FPSCR value.
9690 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSFb)).addImm(1).addReg(MFFSReg);
9691 } else if (MI.getOpcode() == PPC::ANDIo_1_EQ_BIT ||
9692 MI.getOpcode() == PPC::ANDIo_1_GT_BIT ||
9693 MI.getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
9694 MI.getOpcode() == PPC::ANDIo_1_GT_BIT8) {
9695 unsigned Opcode = (MI.getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
9696 MI.getOpcode() == PPC::ANDIo_1_GT_BIT8)
9699 bool isEQ = (MI.getOpcode() == PPC::ANDIo_1_EQ_BIT ||
9700 MI.getOpcode() == PPC::ANDIo_1_EQ_BIT8);
9702 MachineRegisterInfo &RegInfo = F->getRegInfo();
9703 unsigned Dest = RegInfo.createVirtualRegister(Opcode == PPC::ANDIo ?
9704 &PPC::GPRCRegClass :
9705 &PPC::G8RCRegClass);
9707 DebugLoc dl = MI.getDebugLoc();
9708 BuildMI(*BB, MI, dl, TII->get(Opcode), Dest)
9709 .addReg(MI.getOperand(1).getReg())
9711 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY),
9712 MI.getOperand(0).getReg())
9713 .addReg(isEQ ? PPC::CR0EQ : PPC::CR0GT);
9714 } else if (MI.getOpcode() == PPC::TCHECK_RET) {
9715 DebugLoc Dl = MI.getDebugLoc();
9716 MachineRegisterInfo &RegInfo = F->getRegInfo();
9717 unsigned CRReg = RegInfo.createVirtualRegister(&PPC::CRRCRegClass);
9718 BuildMI(*BB, MI, Dl, TII->get(PPC::TCHECK), CRReg);
9721 llvm_unreachable("Unexpected instr type to insert");
9724 MI.eraseFromParent(); // The pseudo instruction is gone now.
9728 //===----------------------------------------------------------------------===//
9729 // Target Optimization Hooks
9730 //===----------------------------------------------------------------------===//
9732 static int getEstimateRefinementSteps(EVT VT, const PPCSubtarget &Subtarget) {
9733 // For the estimates, convergence is quadratic, so we essentially double the
9734 // number of digits correct after every iteration. For both FRE and FRSQRTE,
9735 // the minimum architected relative accuracy is 2^-5. When hasRecipPrec(),
9736 // this is 2^-14. IEEE float has 23 digits and double has 52 digits.
9737 int RefinementSteps = Subtarget.hasRecipPrec() ? 1 : 3;
9738 if (VT.getScalarType() == MVT::f64)
9740 return RefinementSteps;
9743 SDValue PPCTargetLowering::getSqrtEstimate(SDValue Operand, SelectionDAG &DAG,
9744 int Enabled, int &RefinementSteps,
9745 bool &UseOneConstNR,
9746 bool Reciprocal) const {
9747 EVT VT = Operand.getValueType();
9748 if ((VT == MVT::f32 && Subtarget.hasFRSQRTES()) ||
9749 (VT == MVT::f64 && Subtarget.hasFRSQRTE()) ||
9750 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
9751 (VT == MVT::v2f64 && Subtarget.hasVSX()) ||
9752 (VT == MVT::v4f32 && Subtarget.hasQPX()) ||
9753 (VT == MVT::v4f64 && Subtarget.hasQPX())) {
9754 if (RefinementSteps == ReciprocalEstimate::Unspecified)
9755 RefinementSteps = getEstimateRefinementSteps(VT, Subtarget);
9757 UseOneConstNR = true;
9758 return DAG.getNode(PPCISD::FRSQRTE, SDLoc(Operand), VT, Operand);
9763 SDValue PPCTargetLowering::getRecipEstimate(SDValue Operand, SelectionDAG &DAG,
9765 int &RefinementSteps) const {
9766 EVT VT = Operand.getValueType();
9767 if ((VT == MVT::f32 && Subtarget.hasFRES()) ||
9768 (VT == MVT::f64 && Subtarget.hasFRE()) ||
9769 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
9770 (VT == MVT::v2f64 && Subtarget.hasVSX()) ||
9771 (VT == MVT::v4f32 && Subtarget.hasQPX()) ||
9772 (VT == MVT::v4f64 && Subtarget.hasQPX())) {
9773 if (RefinementSteps == ReciprocalEstimate::Unspecified)
9774 RefinementSteps = getEstimateRefinementSteps(VT, Subtarget);
9775 return DAG.getNode(PPCISD::FRE, SDLoc(Operand), VT, Operand);
9780 unsigned PPCTargetLowering::combineRepeatedFPDivisors() const {
9781 // Note: This functionality is used only when unsafe-fp-math is enabled, and
9782 // on cores with reciprocal estimates (which are used when unsafe-fp-math is
9783 // enabled for division), this functionality is redundant with the default
9784 // combiner logic (once the division -> reciprocal/multiply transformation
9785 // has taken place). As a result, this matters more for older cores than for
9788 // Combine multiple FDIVs with the same divisor into multiple FMULs by the
9789 // reciprocal if there are two or more FDIVs (for embedded cores with only
9790 // one FP pipeline) for three or more FDIVs (for generic OOO cores).
9791 switch (Subtarget.getDarwinDirective()) {
9796 case PPC::DIR_E500mc:
9797 case PPC::DIR_E5500:
9802 // isConsecutiveLSLoc needs to work even if all adds have not yet been
9803 // collapsed, and so we need to look through chains of them.
9804 static void getBaseWithConstantOffset(SDValue Loc, SDValue &Base,
9805 int64_t& Offset, SelectionDAG &DAG) {
9806 if (DAG.isBaseWithConstantOffset(Loc)) {
9807 Base = Loc.getOperand(0);
9808 Offset += cast<ConstantSDNode>(Loc.getOperand(1))->getSExtValue();
9810 // The base might itself be a base plus an offset, and if so, accumulate
9812 getBaseWithConstantOffset(Loc.getOperand(0), Base, Offset, DAG);
9816 static bool isConsecutiveLSLoc(SDValue Loc, EVT VT, LSBaseSDNode *Base,
9817 unsigned Bytes, int Dist,
9818 SelectionDAG &DAG) {
9819 if (VT.getSizeInBits() / 8 != Bytes)
9822 SDValue BaseLoc = Base->getBasePtr();
9823 if (Loc.getOpcode() == ISD::FrameIndex) {
9824 if (BaseLoc.getOpcode() != ISD::FrameIndex)
9826 const MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
9827 int FI = cast<FrameIndexSDNode>(Loc)->getIndex();
9828 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex();
9829 int FS = MFI.getObjectSize(FI);
9830 int BFS = MFI.getObjectSize(BFI);
9831 if (FS != BFS || FS != (int)Bytes) return false;
9832 return MFI.getObjectOffset(FI) == (MFI.getObjectOffset(BFI) + Dist*Bytes);
9835 SDValue Base1 = Loc, Base2 = BaseLoc;
9836 int64_t Offset1 = 0, Offset2 = 0;
9837 getBaseWithConstantOffset(Loc, Base1, Offset1, DAG);
9838 getBaseWithConstantOffset(BaseLoc, Base2, Offset2, DAG);
9839 if (Base1 == Base2 && Offset1 == (Offset2 + Dist * Bytes))
9842 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9843 const GlobalValue *GV1 = nullptr;
9844 const GlobalValue *GV2 = nullptr;
9847 bool isGA1 = TLI.isGAPlusOffset(Loc.getNode(), GV1, Offset1);
9848 bool isGA2 = TLI.isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2);
9849 if (isGA1 && isGA2 && GV1 == GV2)
9850 return Offset1 == (Offset2 + Dist*Bytes);
9854 // Like SelectionDAG::isConsecutiveLoad, but also works for stores, and does
9855 // not enforce equality of the chain operands.
9856 static bool isConsecutiveLS(SDNode *N, LSBaseSDNode *Base,
9857 unsigned Bytes, int Dist,
9858 SelectionDAG &DAG) {
9859 if (LSBaseSDNode *LS = dyn_cast<LSBaseSDNode>(N)) {
9860 EVT VT = LS->getMemoryVT();
9861 SDValue Loc = LS->getBasePtr();
9862 return isConsecutiveLSLoc(Loc, VT, Base, Bytes, Dist, DAG);
9865 if (N->getOpcode() == ISD::INTRINSIC_W_CHAIN) {
9867 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
9868 default: return false;
9869 case Intrinsic::ppc_qpx_qvlfd:
9870 case Intrinsic::ppc_qpx_qvlfda:
9873 case Intrinsic::ppc_qpx_qvlfs:
9874 case Intrinsic::ppc_qpx_qvlfsa:
9877 case Intrinsic::ppc_qpx_qvlfcd:
9878 case Intrinsic::ppc_qpx_qvlfcda:
9881 case Intrinsic::ppc_qpx_qvlfcs:
9882 case Intrinsic::ppc_qpx_qvlfcsa:
9885 case Intrinsic::ppc_qpx_qvlfiwa:
9886 case Intrinsic::ppc_qpx_qvlfiwz:
9887 case Intrinsic::ppc_altivec_lvx:
9888 case Intrinsic::ppc_altivec_lvxl:
9889 case Intrinsic::ppc_vsx_lxvw4x:
9890 case Intrinsic::ppc_vsx_lxvw4x_be:
9893 case Intrinsic::ppc_vsx_lxvd2x:
9894 case Intrinsic::ppc_vsx_lxvd2x_be:
9897 case Intrinsic::ppc_altivec_lvebx:
9900 case Intrinsic::ppc_altivec_lvehx:
9903 case Intrinsic::ppc_altivec_lvewx:
9908 return isConsecutiveLSLoc(N->getOperand(2), VT, Base, Bytes, Dist, DAG);
9911 if (N->getOpcode() == ISD::INTRINSIC_VOID) {
9913 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
9914 default: return false;
9915 case Intrinsic::ppc_qpx_qvstfd:
9916 case Intrinsic::ppc_qpx_qvstfda:
9919 case Intrinsic::ppc_qpx_qvstfs:
9920 case Intrinsic::ppc_qpx_qvstfsa:
9923 case Intrinsic::ppc_qpx_qvstfcd:
9924 case Intrinsic::ppc_qpx_qvstfcda:
9927 case Intrinsic::ppc_qpx_qvstfcs:
9928 case Intrinsic::ppc_qpx_qvstfcsa:
9931 case Intrinsic::ppc_qpx_qvstfiw:
9932 case Intrinsic::ppc_qpx_qvstfiwa:
9933 case Intrinsic::ppc_altivec_stvx:
9934 case Intrinsic::ppc_altivec_stvxl:
9935 case Intrinsic::ppc_vsx_stxvw4x:
9938 case Intrinsic::ppc_vsx_stxvd2x:
9941 case Intrinsic::ppc_vsx_stxvw4x_be:
9944 case Intrinsic::ppc_vsx_stxvd2x_be:
9947 case Intrinsic::ppc_altivec_stvebx:
9950 case Intrinsic::ppc_altivec_stvehx:
9953 case Intrinsic::ppc_altivec_stvewx:
9958 return isConsecutiveLSLoc(N->getOperand(3), VT, Base, Bytes, Dist, DAG);
9964 // Return true is there is a nearyby consecutive load to the one provided
9965 // (regardless of alignment). We search up and down the chain, looking though
9966 // token factors and other loads (but nothing else). As a result, a true result
9967 // indicates that it is safe to create a new consecutive load adjacent to the
9969 static bool findConsecutiveLoad(LoadSDNode *LD, SelectionDAG &DAG) {
9970 SDValue Chain = LD->getChain();
9971 EVT VT = LD->getMemoryVT();
9973 SmallSet<SDNode *, 16> LoadRoots;
9974 SmallVector<SDNode *, 8> Queue(1, Chain.getNode());
9975 SmallSet<SDNode *, 16> Visited;
9977 // First, search up the chain, branching to follow all token-factor operands.
9978 // If we find a consecutive load, then we're done, otherwise, record all
9979 // nodes just above the top-level loads and token factors.
9980 while (!Queue.empty()) {
9981 SDNode *ChainNext = Queue.pop_back_val();
9982 if (!Visited.insert(ChainNext).second)
9985 if (MemSDNode *ChainLD = dyn_cast<MemSDNode>(ChainNext)) {
9986 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
9989 if (!Visited.count(ChainLD->getChain().getNode()))
9990 Queue.push_back(ChainLD->getChain().getNode());
9991 } else if (ChainNext->getOpcode() == ISD::TokenFactor) {
9992 for (const SDUse &O : ChainNext->ops())
9993 if (!Visited.count(O.getNode()))
9994 Queue.push_back(O.getNode());
9996 LoadRoots.insert(ChainNext);
9999 // Second, search down the chain, starting from the top-level nodes recorded
10000 // in the first phase. These top-level nodes are the nodes just above all
10001 // loads and token factors. Starting with their uses, recursively look though
10002 // all loads (just the chain uses) and token factors to find a consecutive
10007 for (SmallSet<SDNode *, 16>::iterator I = LoadRoots.begin(),
10008 IE = LoadRoots.end(); I != IE; ++I) {
10009 Queue.push_back(*I);
10011 while (!Queue.empty()) {
10012 SDNode *LoadRoot = Queue.pop_back_val();
10013 if (!Visited.insert(LoadRoot).second)
10016 if (MemSDNode *ChainLD = dyn_cast<MemSDNode>(LoadRoot))
10017 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
10020 for (SDNode::use_iterator UI = LoadRoot->use_begin(),
10021 UE = LoadRoot->use_end(); UI != UE; ++UI)
10022 if (((isa<MemSDNode>(*UI) &&
10023 cast<MemSDNode>(*UI)->getChain().getNode() == LoadRoot) ||
10024 UI->getOpcode() == ISD::TokenFactor) && !Visited.count(*UI))
10025 Queue.push_back(*UI);
10033 /// This function is called when we have proved that a SETCC node can be replaced
10034 /// by subtraction (and other supporting instructions) so that the result of
10035 /// comparison is kept in a GPR instead of CR. This function is purely for
10036 /// codegen purposes and has some flags to guide the codegen process.
10037 static SDValue generateEquivalentSub(SDNode *N, int Size, bool Complement,
10038 bool Swap, SDLoc &DL, SelectionDAG &DAG) {
10040 assert(N->getOpcode() == ISD::SETCC && "ISD::SETCC Expected.");
10042 // Zero extend the operands to the largest legal integer. Originally, they
10043 // must be of a strictly smaller size.
10044 auto Op0 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, N->getOperand(0),
10045 DAG.getConstant(Size, DL, MVT::i32));
10046 auto Op1 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, N->getOperand(1),
10047 DAG.getConstant(Size, DL, MVT::i32));
10049 // Swap if needed. Depends on the condition code.
10051 std::swap(Op0, Op1);
10053 // Subtract extended integers.
10054 auto SubNode = DAG.getNode(ISD::SUB, DL, MVT::i64, Op0, Op1);
10056 // Move the sign bit to the least significant position and zero out the rest.
10057 // Now the least significant bit carries the result of original comparison.
10058 auto Shifted = DAG.getNode(ISD::SRL, DL, MVT::i64, SubNode,
10059 DAG.getConstant(Size - 1, DL, MVT::i32));
10060 auto Final = Shifted;
10062 // Complement the result if needed. Based on the condition code.
10064 Final = DAG.getNode(ISD::XOR, DL, MVT::i64, Shifted,
10065 DAG.getConstant(1, DL, MVT::i64));
10067 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Final);
10070 SDValue PPCTargetLowering::ConvertSETCCToSubtract(SDNode *N,
10071 DAGCombinerInfo &DCI) const {
10073 assert(N->getOpcode() == ISD::SETCC && "ISD::SETCC Expected.");
10075 SelectionDAG &DAG = DCI.DAG;
10078 // Size of integers being compared has a critical role in the following
10079 // analysis, so we prefer to do this when all types are legal.
10080 if (!DCI.isAfterLegalizeVectorOps())
10083 // If all users of SETCC extend its value to a legal integer type
10084 // then we replace SETCC with a subtraction
10085 for (SDNode::use_iterator UI = N->use_begin(),
10086 UE = N->use_end(); UI != UE; ++UI) {
10087 if (UI->getOpcode() != ISD::ZERO_EXTEND)
10091 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
10092 auto OpSize = N->getOperand(0).getValueSizeInBits();
10094 unsigned Size = DAG.getDataLayout().getLargestLegalIntTypeSizeInBits();
10096 if (OpSize < Size) {
10100 return generateEquivalentSub(N, Size, false, false, DL, DAG);
10102 return generateEquivalentSub(N, Size, true, true, DL, DAG);
10104 return generateEquivalentSub(N, Size, false, true, DL, DAG);
10106 return generateEquivalentSub(N, Size, true, false, DL, DAG);
10113 SDValue PPCTargetLowering::DAGCombineTruncBoolExt(SDNode *N,
10114 DAGCombinerInfo &DCI) const {
10115 SelectionDAG &DAG = DCI.DAG;
10118 assert(Subtarget.useCRBits() && "Expecting to be tracking CR bits");
10119 // If we're tracking CR bits, we need to be careful that we don't have:
10120 // trunc(binary-ops(zext(x), zext(y)))
10122 // trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
10123 // such that we're unnecessarily moving things into GPRs when it would be
10124 // better to keep them in CR bits.
10126 // Note that trunc here can be an actual i1 trunc, or can be the effective
10127 // truncation that comes from a setcc or select_cc.
10128 if (N->getOpcode() == ISD::TRUNCATE &&
10129 N->getValueType(0) != MVT::i1)
10132 if (N->getOperand(0).getValueType() != MVT::i32 &&
10133 N->getOperand(0).getValueType() != MVT::i64)
10136 if (N->getOpcode() == ISD::SETCC ||
10137 N->getOpcode() == ISD::SELECT_CC) {
10138 // If we're looking at a comparison, then we need to make sure that the
10139 // high bits (all except for the first) don't matter the result.
10141 cast<CondCodeSDNode>(N->getOperand(
10142 N->getOpcode() == ISD::SETCC ? 2 : 4))->get();
10143 unsigned OpBits = N->getOperand(0).getValueSizeInBits();
10145 if (ISD::isSignedIntSetCC(CC)) {
10146 if (DAG.ComputeNumSignBits(N->getOperand(0)) != OpBits ||
10147 DAG.ComputeNumSignBits(N->getOperand(1)) != OpBits)
10149 } else if (ISD::isUnsignedIntSetCC(CC)) {
10150 if (!DAG.MaskedValueIsZero(N->getOperand(0),
10151 APInt::getHighBitsSet(OpBits, OpBits-1)) ||
10152 !DAG.MaskedValueIsZero(N->getOperand(1),
10153 APInt::getHighBitsSet(OpBits, OpBits-1)))
10154 return (N->getOpcode() == ISD::SETCC ? ConvertSETCCToSubtract(N, DCI)
10157 // This is neither a signed nor an unsigned comparison, just make sure
10158 // that the high bits are equal.
10159 APInt Op1Zero, Op1One;
10160 APInt Op2Zero, Op2One;
10161 DAG.computeKnownBits(N->getOperand(0), Op1Zero, Op1One);
10162 DAG.computeKnownBits(N->getOperand(1), Op2Zero, Op2One);
10164 // We don't really care about what is known about the first bit (if
10165 // anything), so clear it in all masks prior to comparing them.
10166 Op1Zero.clearBit(0); Op1One.clearBit(0);
10167 Op2Zero.clearBit(0); Op2One.clearBit(0);
10169 if (Op1Zero != Op2Zero || Op1One != Op2One)
10174 // We now know that the higher-order bits are irrelevant, we just need to
10175 // make sure that all of the intermediate operations are bit operations, and
10176 // all inputs are extensions.
10177 if (N->getOperand(0).getOpcode() != ISD::AND &&
10178 N->getOperand(0).getOpcode() != ISD::OR &&
10179 N->getOperand(0).getOpcode() != ISD::XOR &&
10180 N->getOperand(0).getOpcode() != ISD::SELECT &&
10181 N->getOperand(0).getOpcode() != ISD::SELECT_CC &&
10182 N->getOperand(0).getOpcode() != ISD::TRUNCATE &&
10183 N->getOperand(0).getOpcode() != ISD::SIGN_EXTEND &&
10184 N->getOperand(0).getOpcode() != ISD::ZERO_EXTEND &&
10185 N->getOperand(0).getOpcode() != ISD::ANY_EXTEND)
10188 if ((N->getOpcode() == ISD::SETCC || N->getOpcode() == ISD::SELECT_CC) &&
10189 N->getOperand(1).getOpcode() != ISD::AND &&
10190 N->getOperand(1).getOpcode() != ISD::OR &&
10191 N->getOperand(1).getOpcode() != ISD::XOR &&
10192 N->getOperand(1).getOpcode() != ISD::SELECT &&
10193 N->getOperand(1).getOpcode() != ISD::SELECT_CC &&
10194 N->getOperand(1).getOpcode() != ISD::TRUNCATE &&
10195 N->getOperand(1).getOpcode() != ISD::SIGN_EXTEND &&
10196 N->getOperand(1).getOpcode() != ISD::ZERO_EXTEND &&
10197 N->getOperand(1).getOpcode() != ISD::ANY_EXTEND)
10200 SmallVector<SDValue, 4> Inputs;
10201 SmallVector<SDValue, 8> BinOps, PromOps;
10202 SmallPtrSet<SDNode *, 16> Visited;
10204 for (unsigned i = 0; i < 2; ++i) {
10205 if (((N->getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
10206 N->getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
10207 N->getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
10208 N->getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
10209 isa<ConstantSDNode>(N->getOperand(i)))
10210 Inputs.push_back(N->getOperand(i));
10212 BinOps.push_back(N->getOperand(i));
10214 if (N->getOpcode() == ISD::TRUNCATE)
10218 // Visit all inputs, collect all binary operations (and, or, xor and
10219 // select) that are all fed by extensions.
10220 while (!BinOps.empty()) {
10221 SDValue BinOp = BinOps.back();
10224 if (!Visited.insert(BinOp.getNode()).second)
10227 PromOps.push_back(BinOp);
10229 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
10230 // The condition of the select is not promoted.
10231 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
10233 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
10236 if (((BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
10237 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
10238 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
10239 BinOp.getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
10240 isa<ConstantSDNode>(BinOp.getOperand(i))) {
10241 Inputs.push_back(BinOp.getOperand(i));
10242 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
10243 BinOp.getOperand(i).getOpcode() == ISD::OR ||
10244 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
10245 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
10246 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC ||
10247 BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
10248 BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
10249 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
10250 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) {
10251 BinOps.push_back(BinOp.getOperand(i));
10253 // We have an input that is not an extension or another binary
10254 // operation; we'll abort this transformation.
10260 // Make sure that this is a self-contained cluster of operations (which
10261 // is not quite the same thing as saying that everything has only one
10263 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
10264 if (isa<ConstantSDNode>(Inputs[i]))
10267 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
10268 UE = Inputs[i].getNode()->use_end();
10270 SDNode *User = *UI;
10271 if (User != N && !Visited.count(User))
10274 // Make sure that we're not going to promote the non-output-value
10275 // operand(s) or SELECT or SELECT_CC.
10276 // FIXME: Although we could sometimes handle this, and it does occur in
10277 // practice that one of the condition inputs to the select is also one of
10278 // the outputs, we currently can't deal with this.
10279 if (User->getOpcode() == ISD::SELECT) {
10280 if (User->getOperand(0) == Inputs[i])
10282 } else if (User->getOpcode() == ISD::SELECT_CC) {
10283 if (User->getOperand(0) == Inputs[i] ||
10284 User->getOperand(1) == Inputs[i])
10290 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
10291 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
10292 UE = PromOps[i].getNode()->use_end();
10294 SDNode *User = *UI;
10295 if (User != N && !Visited.count(User))
10298 // Make sure that we're not going to promote the non-output-value
10299 // operand(s) or SELECT or SELECT_CC.
10300 // FIXME: Although we could sometimes handle this, and it does occur in
10301 // practice that one of the condition inputs to the select is also one of
10302 // the outputs, we currently can't deal with this.
10303 if (User->getOpcode() == ISD::SELECT) {
10304 if (User->getOperand(0) == PromOps[i])
10306 } else if (User->getOpcode() == ISD::SELECT_CC) {
10307 if (User->getOperand(0) == PromOps[i] ||
10308 User->getOperand(1) == PromOps[i])
10314 // Replace all inputs with the extension operand.
10315 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
10316 // Constants may have users outside the cluster of to-be-promoted nodes,
10317 // and so we need to replace those as we do the promotions.
10318 if (isa<ConstantSDNode>(Inputs[i]))
10321 DAG.ReplaceAllUsesOfValueWith(Inputs[i], Inputs[i].getOperand(0));
10324 std::list<HandleSDNode> PromOpHandles;
10325 for (auto &PromOp : PromOps)
10326 PromOpHandles.emplace_back(PromOp);
10328 // Replace all operations (these are all the same, but have a different
10329 // (i1) return type). DAG.getNode will validate that the types of
10330 // a binary operator match, so go through the list in reverse so that
10331 // we've likely promoted both operands first. Any intermediate truncations or
10332 // extensions disappear.
10333 while (!PromOpHandles.empty()) {
10334 SDValue PromOp = PromOpHandles.back().getValue();
10335 PromOpHandles.pop_back();
10337 if (PromOp.getOpcode() == ISD::TRUNCATE ||
10338 PromOp.getOpcode() == ISD::SIGN_EXTEND ||
10339 PromOp.getOpcode() == ISD::ZERO_EXTEND ||
10340 PromOp.getOpcode() == ISD::ANY_EXTEND) {
10341 if (!isa<ConstantSDNode>(PromOp.getOperand(0)) &&
10342 PromOp.getOperand(0).getValueType() != MVT::i1) {
10343 // The operand is not yet ready (see comment below).
10344 PromOpHandles.emplace_front(PromOp);
10348 SDValue RepValue = PromOp.getOperand(0);
10349 if (isa<ConstantSDNode>(RepValue))
10350 RepValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, RepValue);
10352 DAG.ReplaceAllUsesOfValueWith(PromOp, RepValue);
10357 switch (PromOp.getOpcode()) {
10358 default: C = 0; break;
10359 case ISD::SELECT: C = 1; break;
10360 case ISD::SELECT_CC: C = 2; break;
10363 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
10364 PromOp.getOperand(C).getValueType() != MVT::i1) ||
10365 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
10366 PromOp.getOperand(C+1).getValueType() != MVT::i1)) {
10367 // The to-be-promoted operands of this node have not yet been
10368 // promoted (this should be rare because we're going through the
10369 // list backward, but if one of the operands has several users in
10370 // this cluster of to-be-promoted nodes, it is possible).
10371 PromOpHandles.emplace_front(PromOp);
10375 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
10376 PromOp.getNode()->op_end());
10378 // If there are any constant inputs, make sure they're replaced now.
10379 for (unsigned i = 0; i < 2; ++i)
10380 if (isa<ConstantSDNode>(Ops[C+i]))
10381 Ops[C+i] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ops[C+i]);
10383 DAG.ReplaceAllUsesOfValueWith(PromOp,
10384 DAG.getNode(PromOp.getOpcode(), dl, MVT::i1, Ops));
10387 // Now we're left with the initial truncation itself.
10388 if (N->getOpcode() == ISD::TRUNCATE)
10389 return N->getOperand(0);
10391 // Otherwise, this is a comparison. The operands to be compared have just
10392 // changed type (to i1), but everything else is the same.
10393 return SDValue(N, 0);
10396 SDValue PPCTargetLowering::DAGCombineExtBoolTrunc(SDNode *N,
10397 DAGCombinerInfo &DCI) const {
10398 SelectionDAG &DAG = DCI.DAG;
10401 // If we're tracking CR bits, we need to be careful that we don't have:
10402 // zext(binary-ops(trunc(x), trunc(y)))
10404 // zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
10405 // such that we're unnecessarily moving things into CR bits that can more
10406 // efficiently stay in GPRs. Note that if we're not certain that the high
10407 // bits are set as required by the final extension, we still may need to do
10408 // some masking to get the proper behavior.
10410 // This same functionality is important on PPC64 when dealing with
10411 // 32-to-64-bit extensions; these occur often when 32-bit values are used as
10412 // the return values of functions. Because it is so similar, it is handled
10415 if (N->getValueType(0) != MVT::i32 &&
10416 N->getValueType(0) != MVT::i64)
10419 if (!((N->getOperand(0).getValueType() == MVT::i1 && Subtarget.useCRBits()) ||
10420 (N->getOperand(0).getValueType() == MVT::i32 && Subtarget.isPPC64())))
10423 if (N->getOperand(0).getOpcode() != ISD::AND &&
10424 N->getOperand(0).getOpcode() != ISD::OR &&
10425 N->getOperand(0).getOpcode() != ISD::XOR &&
10426 N->getOperand(0).getOpcode() != ISD::SELECT &&
10427 N->getOperand(0).getOpcode() != ISD::SELECT_CC)
10430 SmallVector<SDValue, 4> Inputs;
10431 SmallVector<SDValue, 8> BinOps(1, N->getOperand(0)), PromOps;
10432 SmallPtrSet<SDNode *, 16> Visited;
10434 // Visit all inputs, collect all binary operations (and, or, xor and
10435 // select) that are all fed by truncations.
10436 while (!BinOps.empty()) {
10437 SDValue BinOp = BinOps.back();
10440 if (!Visited.insert(BinOp.getNode()).second)
10443 PromOps.push_back(BinOp);
10445 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
10446 // The condition of the select is not promoted.
10447 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
10449 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
10452 if (BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
10453 isa<ConstantSDNode>(BinOp.getOperand(i))) {
10454 Inputs.push_back(BinOp.getOperand(i));
10455 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
10456 BinOp.getOperand(i).getOpcode() == ISD::OR ||
10457 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
10458 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
10459 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC) {
10460 BinOps.push_back(BinOp.getOperand(i));
10462 // We have an input that is not a truncation or another binary
10463 // operation; we'll abort this transformation.
10469 // The operands of a select that must be truncated when the select is
10470 // promoted because the operand is actually part of the to-be-promoted set.
10471 DenseMap<SDNode *, EVT> SelectTruncOp[2];
10473 // Make sure that this is a self-contained cluster of operations (which
10474 // is not quite the same thing as saying that everything has only one
10476 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
10477 if (isa<ConstantSDNode>(Inputs[i]))
10480 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
10481 UE = Inputs[i].getNode()->use_end();
10483 SDNode *User = *UI;
10484 if (User != N && !Visited.count(User))
10487 // If we're going to promote the non-output-value operand(s) or SELECT or
10488 // SELECT_CC, record them for truncation.
10489 if (User->getOpcode() == ISD::SELECT) {
10490 if (User->getOperand(0) == Inputs[i])
10491 SelectTruncOp[0].insert(std::make_pair(User,
10492 User->getOperand(0).getValueType()));
10493 } else if (User->getOpcode() == ISD::SELECT_CC) {
10494 if (User->getOperand(0) == Inputs[i])
10495 SelectTruncOp[0].insert(std::make_pair(User,
10496 User->getOperand(0).getValueType()));
10497 if (User->getOperand(1) == Inputs[i])
10498 SelectTruncOp[1].insert(std::make_pair(User,
10499 User->getOperand(1).getValueType()));
10504 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
10505 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
10506 UE = PromOps[i].getNode()->use_end();
10508 SDNode *User = *UI;
10509 if (User != N && !Visited.count(User))
10512 // If we're going to promote the non-output-value operand(s) or SELECT or
10513 // SELECT_CC, record them for truncation.
10514 if (User->getOpcode() == ISD::SELECT) {
10515 if (User->getOperand(0) == PromOps[i])
10516 SelectTruncOp[0].insert(std::make_pair(User,
10517 User->getOperand(0).getValueType()));
10518 } else if (User->getOpcode() == ISD::SELECT_CC) {
10519 if (User->getOperand(0) == PromOps[i])
10520 SelectTruncOp[0].insert(std::make_pair(User,
10521 User->getOperand(0).getValueType()));
10522 if (User->getOperand(1) == PromOps[i])
10523 SelectTruncOp[1].insert(std::make_pair(User,
10524 User->getOperand(1).getValueType()));
10529 unsigned PromBits = N->getOperand(0).getValueSizeInBits();
10530 bool ReallyNeedsExt = false;
10531 if (N->getOpcode() != ISD::ANY_EXTEND) {
10532 // If all of the inputs are not already sign/zero extended, then
10533 // we'll still need to do that at the end.
10534 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
10535 if (isa<ConstantSDNode>(Inputs[i]))
10539 Inputs[i].getOperand(0).getValueSizeInBits();
10540 assert(PromBits < OpBits && "Truncation not to a smaller bit count?");
10542 if ((N->getOpcode() == ISD::ZERO_EXTEND &&
10543 !DAG.MaskedValueIsZero(Inputs[i].getOperand(0),
10544 APInt::getHighBitsSet(OpBits,
10545 OpBits-PromBits))) ||
10546 (N->getOpcode() == ISD::SIGN_EXTEND &&
10547 DAG.ComputeNumSignBits(Inputs[i].getOperand(0)) <
10548 (OpBits-(PromBits-1)))) {
10549 ReallyNeedsExt = true;
10555 // Replace all inputs, either with the truncation operand, or a
10556 // truncation or extension to the final output type.
10557 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
10558 // Constant inputs need to be replaced with the to-be-promoted nodes that
10559 // use them because they might have users outside of the cluster of
10561 if (isa<ConstantSDNode>(Inputs[i]))
10564 SDValue InSrc = Inputs[i].getOperand(0);
10565 if (Inputs[i].getValueType() == N->getValueType(0))
10566 DAG.ReplaceAllUsesOfValueWith(Inputs[i], InSrc);
10567 else if (N->getOpcode() == ISD::SIGN_EXTEND)
10568 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
10569 DAG.getSExtOrTrunc(InSrc, dl, N->getValueType(0)));
10570 else if (N->getOpcode() == ISD::ZERO_EXTEND)
10571 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
10572 DAG.getZExtOrTrunc(InSrc, dl, N->getValueType(0)));
10574 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
10575 DAG.getAnyExtOrTrunc(InSrc, dl, N->getValueType(0)));
10578 std::list<HandleSDNode> PromOpHandles;
10579 for (auto &PromOp : PromOps)
10580 PromOpHandles.emplace_back(PromOp);
10582 // Replace all operations (these are all the same, but have a different
10583 // (promoted) return type). DAG.getNode will validate that the types of
10584 // a binary operator match, so go through the list in reverse so that
10585 // we've likely promoted both operands first.
10586 while (!PromOpHandles.empty()) {
10587 SDValue PromOp = PromOpHandles.back().getValue();
10588 PromOpHandles.pop_back();
10591 switch (PromOp.getOpcode()) {
10592 default: C = 0; break;
10593 case ISD::SELECT: C = 1; break;
10594 case ISD::SELECT_CC: C = 2; break;
10597 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
10598 PromOp.getOperand(C).getValueType() != N->getValueType(0)) ||
10599 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
10600 PromOp.getOperand(C+1).getValueType() != N->getValueType(0))) {
10601 // The to-be-promoted operands of this node have not yet been
10602 // promoted (this should be rare because we're going through the
10603 // list backward, but if one of the operands has several users in
10604 // this cluster of to-be-promoted nodes, it is possible).
10605 PromOpHandles.emplace_front(PromOp);
10609 // For SELECT and SELECT_CC nodes, we do a similar check for any
10610 // to-be-promoted comparison inputs.
10611 if (PromOp.getOpcode() == ISD::SELECT ||
10612 PromOp.getOpcode() == ISD::SELECT_CC) {
10613 if ((SelectTruncOp[0].count(PromOp.getNode()) &&
10614 PromOp.getOperand(0).getValueType() != N->getValueType(0)) ||
10615 (SelectTruncOp[1].count(PromOp.getNode()) &&
10616 PromOp.getOperand(1).getValueType() != N->getValueType(0))) {
10617 PromOpHandles.emplace_front(PromOp);
10622 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
10623 PromOp.getNode()->op_end());
10625 // If this node has constant inputs, then they'll need to be promoted here.
10626 for (unsigned i = 0; i < 2; ++i) {
10627 if (!isa<ConstantSDNode>(Ops[C+i]))
10629 if (Ops[C+i].getValueType() == N->getValueType(0))
10632 if (N->getOpcode() == ISD::SIGN_EXTEND)
10633 Ops[C+i] = DAG.getSExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
10634 else if (N->getOpcode() == ISD::ZERO_EXTEND)
10635 Ops[C+i] = DAG.getZExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
10637 Ops[C+i] = DAG.getAnyExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
10640 // If we've promoted the comparison inputs of a SELECT or SELECT_CC,
10641 // truncate them again to the original value type.
10642 if (PromOp.getOpcode() == ISD::SELECT ||
10643 PromOp.getOpcode() == ISD::SELECT_CC) {
10644 auto SI0 = SelectTruncOp[0].find(PromOp.getNode());
10645 if (SI0 != SelectTruncOp[0].end())
10646 Ops[0] = DAG.getNode(ISD::TRUNCATE, dl, SI0->second, Ops[0]);
10647 auto SI1 = SelectTruncOp[1].find(PromOp.getNode());
10648 if (SI1 != SelectTruncOp[1].end())
10649 Ops[1] = DAG.getNode(ISD::TRUNCATE, dl, SI1->second, Ops[1]);
10652 DAG.ReplaceAllUsesOfValueWith(PromOp,
10653 DAG.getNode(PromOp.getOpcode(), dl, N->getValueType(0), Ops));
10656 // Now we're left with the initial extension itself.
10657 if (!ReallyNeedsExt)
10658 return N->getOperand(0);
10660 // To zero extend, just mask off everything except for the first bit (in the
10662 if (N->getOpcode() == ISD::ZERO_EXTEND)
10663 return DAG.getNode(ISD::AND, dl, N->getValueType(0), N->getOperand(0),
10664 DAG.getConstant(APInt::getLowBitsSet(
10665 N->getValueSizeInBits(0), PromBits),
10666 dl, N->getValueType(0)));
10668 assert(N->getOpcode() == ISD::SIGN_EXTEND &&
10669 "Invalid extension type");
10670 EVT ShiftAmountTy = getShiftAmountTy(N->getValueType(0), DAG.getDataLayout());
10672 DAG.getConstant(N->getValueSizeInBits(0) - PromBits, dl, ShiftAmountTy);
10673 return DAG.getNode(
10674 ISD::SRA, dl, N->getValueType(0),
10675 DAG.getNode(ISD::SHL, dl, N->getValueType(0), N->getOperand(0), ShiftCst),
10679 /// \brief Reduces the number of fp-to-int conversion when building a vector.
10681 /// If this vector is built out of floating to integer conversions,
10682 /// transform it to a vector built out of floating point values followed by a
10683 /// single floating to integer conversion of the vector.
10684 /// Namely (build_vector (fptosi $A), (fptosi $B), ...)
10685 /// becomes (fptosi (build_vector ($A, $B, ...)))
10686 SDValue PPCTargetLowering::
10687 combineElementTruncationToVectorTruncation(SDNode *N,
10688 DAGCombinerInfo &DCI) const {
10689 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
10690 "Should be called with a BUILD_VECTOR node");
10692 SelectionDAG &DAG = DCI.DAG;
10695 SDValue FirstInput = N->getOperand(0);
10696 assert(FirstInput.getOpcode() == PPCISD::MFVSR &&
10697 "The input operand must be an fp-to-int conversion.");
10699 // This combine happens after legalization so the fp_to_[su]i nodes are
10700 // already converted to PPCSISD nodes.
10701 unsigned FirstConversion = FirstInput.getOperand(0).getOpcode();
10702 if (FirstConversion == PPCISD::FCTIDZ ||
10703 FirstConversion == PPCISD::FCTIDUZ ||
10704 FirstConversion == PPCISD::FCTIWZ ||
10705 FirstConversion == PPCISD::FCTIWUZ) {
10706 bool IsSplat = true;
10707 bool Is32Bit = FirstConversion == PPCISD::FCTIWZ ||
10708 FirstConversion == PPCISD::FCTIWUZ;
10709 EVT SrcVT = FirstInput.getOperand(0).getValueType();
10710 SmallVector<SDValue, 4> Ops;
10711 EVT TargetVT = N->getValueType(0);
10712 for (int i = 0, e = N->getNumOperands(); i < e; ++i) {
10713 if (N->getOperand(i).getOpcode() != PPCISD::MFVSR)
10715 unsigned NextConversion = N->getOperand(i).getOperand(0).getOpcode();
10716 if (NextConversion != FirstConversion)
10718 if (N->getOperand(i) != FirstInput)
10722 // If this is a splat, we leave it as-is since there will be only a single
10723 // fp-to-int conversion followed by a splat of the integer. This is better
10724 // for 32-bit and smaller ints and neutral for 64-bit ints.
10728 // Now that we know we have the right type of node, get its operands
10729 for (int i = 0, e = N->getNumOperands(); i < e; ++i) {
10730 SDValue In = N->getOperand(i).getOperand(0);
10731 // For 32-bit values, we need to add an FP_ROUND node.
10734 Ops.push_back(DAG.getUNDEF(SrcVT));
10736 SDValue Trunc = DAG.getNode(ISD::FP_ROUND, dl,
10737 MVT::f32, In.getOperand(0),
10738 DAG.getIntPtrConstant(1, dl));
10739 Ops.push_back(Trunc);
10742 Ops.push_back(In.isUndef() ? DAG.getUNDEF(SrcVT) : In.getOperand(0));
10746 if (FirstConversion == PPCISD::FCTIDZ ||
10747 FirstConversion == PPCISD::FCTIWZ)
10748 Opcode = ISD::FP_TO_SINT;
10750 Opcode = ISD::FP_TO_UINT;
10752 EVT NewVT = TargetVT == MVT::v2i64 ? MVT::v2f64 : MVT::v4f32;
10753 SDValue BV = DAG.getBuildVector(NewVT, dl, Ops);
10754 return DAG.getNode(Opcode, dl, TargetVT, BV);
10759 /// \brief Reduce the number of loads when building a vector.
10761 /// Building a vector out of multiple loads can be converted to a load
10762 /// of the vector type if the loads are consecutive. If the loads are
10763 /// consecutive but in descending order, a shuffle is added at the end
10764 /// to reorder the vector.
10765 static SDValue combineBVOfConsecutiveLoads(SDNode *N, SelectionDAG &DAG) {
10766 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
10767 "Should be called with a BUILD_VECTOR node");
10770 bool InputsAreConsecutiveLoads = true;
10771 bool InputsAreReverseConsecutive = true;
10772 unsigned ElemSize = N->getValueType(0).getScalarSizeInBits() / 8;
10773 SDValue FirstInput = N->getOperand(0);
10774 bool IsRoundOfExtLoad = false;
10776 if (FirstInput.getOpcode() == ISD::FP_ROUND &&
10777 FirstInput.getOperand(0).getOpcode() == ISD::LOAD) {
10778 LoadSDNode *LD = dyn_cast<LoadSDNode>(FirstInput.getOperand(0));
10779 IsRoundOfExtLoad = LD->getExtensionType() == ISD::EXTLOAD;
10781 // Not a build vector of (possibly fp_rounded) loads.
10782 if (!IsRoundOfExtLoad && FirstInput.getOpcode() != ISD::LOAD)
10785 for (int i = 1, e = N->getNumOperands(); i < e; ++i) {
10786 // If any inputs are fp_round(extload), they all must be.
10787 if (IsRoundOfExtLoad && N->getOperand(i).getOpcode() != ISD::FP_ROUND)
10790 SDValue NextInput = IsRoundOfExtLoad ? N->getOperand(i).getOperand(0) :
10792 if (NextInput.getOpcode() != ISD::LOAD)
10795 SDValue PreviousInput =
10796 IsRoundOfExtLoad ? N->getOperand(i-1).getOperand(0) : N->getOperand(i-1);
10797 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(PreviousInput);
10798 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(NextInput);
10800 // If any inputs are fp_round(extload), they all must be.
10801 if (IsRoundOfExtLoad && LD2->getExtensionType() != ISD::EXTLOAD)
10804 if (!isConsecutiveLS(LD2, LD1, ElemSize, 1, DAG))
10805 InputsAreConsecutiveLoads = false;
10806 if (!isConsecutiveLS(LD1, LD2, ElemSize, 1, DAG))
10807 InputsAreReverseConsecutive = false;
10809 // Exit early if the loads are neither consecutive nor reverse consecutive.
10810 if (!InputsAreConsecutiveLoads && !InputsAreReverseConsecutive)
10814 assert(!(InputsAreConsecutiveLoads && InputsAreReverseConsecutive) &&
10815 "The loads cannot be both consecutive and reverse consecutive.");
10817 SDValue FirstLoadOp =
10818 IsRoundOfExtLoad ? FirstInput.getOperand(0) : FirstInput;
10819 SDValue LastLoadOp =
10820 IsRoundOfExtLoad ? N->getOperand(N->getNumOperands()-1).getOperand(0) :
10821 N->getOperand(N->getNumOperands()-1);
10823 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(FirstLoadOp);
10824 LoadSDNode *LDL = dyn_cast<LoadSDNode>(LastLoadOp);
10825 if (InputsAreConsecutiveLoads) {
10826 assert(LD1 && "Input needs to be a LoadSDNode.");
10827 return DAG.getLoad(N->getValueType(0), dl, LD1->getChain(),
10828 LD1->getBasePtr(), LD1->getPointerInfo(),
10829 LD1->getAlignment());
10831 if (InputsAreReverseConsecutive) {
10832 assert(LDL && "Input needs to be a LoadSDNode.");
10833 SDValue Load = DAG.getLoad(N->getValueType(0), dl, LDL->getChain(),
10834 LDL->getBasePtr(), LDL->getPointerInfo(),
10835 LDL->getAlignment());
10836 SmallVector<int, 16> Ops;
10837 for (int i = N->getNumOperands() - 1; i >= 0; i--)
10840 return DAG.getVectorShuffle(N->getValueType(0), dl, Load,
10841 DAG.getUNDEF(N->getValueType(0)), Ops);
10846 SDValue PPCTargetLowering::DAGCombineBuildVector(SDNode *N,
10847 DAGCombinerInfo &DCI) const {
10848 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
10849 "Should be called with a BUILD_VECTOR node");
10851 SelectionDAG &DAG = DCI.DAG;
10854 if (!Subtarget.hasVSX())
10857 // The target independent DAG combiner will leave a build_vector of
10858 // float-to-int conversions intact. We can generate MUCH better code for
10859 // a float-to-int conversion of a vector of floats.
10860 SDValue FirstInput = N->getOperand(0);
10861 if (FirstInput.getOpcode() == PPCISD::MFVSR) {
10862 SDValue Reduced = combineElementTruncationToVectorTruncation(N, DCI);
10867 // If we're building a vector out of consecutive loads, just load that
10869 SDValue Reduced = combineBVOfConsecutiveLoads(N, DAG);
10873 if (N->getValueType(0) != MVT::v2f64)
10877 // (build_vector ([su]int_to_fp (extractelt 0)), [su]int_to_fp (extractelt 1))
10878 if (FirstInput.getOpcode() != ISD::SINT_TO_FP &&
10879 FirstInput.getOpcode() != ISD::UINT_TO_FP)
10881 if (N->getOperand(1).getOpcode() != ISD::SINT_TO_FP &&
10882 N->getOperand(1).getOpcode() != ISD::UINT_TO_FP)
10884 if (FirstInput.getOpcode() != N->getOperand(1).getOpcode())
10887 SDValue Ext1 = FirstInput.getOperand(0);
10888 SDValue Ext2 = N->getOperand(1).getOperand(0);
10889 if(Ext1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
10890 Ext2.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
10893 ConstantSDNode *Ext1Op = dyn_cast<ConstantSDNode>(Ext1.getOperand(1));
10894 ConstantSDNode *Ext2Op = dyn_cast<ConstantSDNode>(Ext2.getOperand(1));
10895 if (!Ext1Op || !Ext2Op)
10897 if (Ext1.getValueType() != MVT::i32 ||
10898 Ext2.getValueType() != MVT::i32)
10899 if (Ext1.getOperand(0) != Ext2.getOperand(0))
10902 int FirstElem = Ext1Op->getZExtValue();
10903 int SecondElem = Ext2Op->getZExtValue();
10905 if (FirstElem == 0 && SecondElem == 1)
10906 SubvecIdx = Subtarget.isLittleEndian() ? 1 : 0;
10907 else if (FirstElem == 2 && SecondElem == 3)
10908 SubvecIdx = Subtarget.isLittleEndian() ? 0 : 1;
10912 SDValue SrcVec = Ext1.getOperand(0);
10913 auto NodeType = (N->getOperand(1).getOpcode() == ISD::SINT_TO_FP) ?
10914 PPCISD::SINT_VEC_TO_FP : PPCISD::UINT_VEC_TO_FP;
10915 return DAG.getNode(NodeType, dl, MVT::v2f64,
10916 SrcVec, DAG.getIntPtrConstant(SubvecIdx, dl));
10919 SDValue PPCTargetLowering::combineFPToIntToFP(SDNode *N,
10920 DAGCombinerInfo &DCI) const {
10921 assert((N->getOpcode() == ISD::SINT_TO_FP ||
10922 N->getOpcode() == ISD::UINT_TO_FP) &&
10923 "Need an int -> FP conversion node here");
10925 if (useSoftFloat() || !Subtarget.has64BitSupport())
10928 SelectionDAG &DAG = DCI.DAG;
10932 SDValue FirstOperand(Op.getOperand(0));
10933 bool SubWordLoad = FirstOperand.getOpcode() == ISD::LOAD &&
10934 (FirstOperand.getValueType() == MVT::i8 ||
10935 FirstOperand.getValueType() == MVT::i16);
10936 if (Subtarget.hasP9Vector() && Subtarget.hasP9Altivec() && SubWordLoad) {
10937 bool Signed = N->getOpcode() == ISD::SINT_TO_FP;
10938 bool DstDouble = Op.getValueType() == MVT::f64;
10939 unsigned ConvOp = Signed ?
10940 (DstDouble ? PPCISD::FCFID : PPCISD::FCFIDS) :
10941 (DstDouble ? PPCISD::FCFIDU : PPCISD::FCFIDUS);
10942 SDValue WidthConst =
10943 DAG.getIntPtrConstant(FirstOperand.getValueType() == MVT::i8 ? 1 : 2,
10945 LoadSDNode *LDN = cast<LoadSDNode>(FirstOperand.getNode());
10946 SDValue Ops[] = { LDN->getChain(), LDN->getBasePtr(), WidthConst };
10947 SDValue Ld = DAG.getMemIntrinsicNode(PPCISD::LXSIZX, dl,
10948 DAG.getVTList(MVT::f64, MVT::Other),
10949 Ops, MVT::i8, LDN->getMemOperand());
10951 // For signed conversion, we need to sign-extend the value in the VSR
10953 SDValue ExtOps[] = { Ld, WidthConst };
10954 SDValue Ext = DAG.getNode(PPCISD::VEXTS, dl, MVT::f64, ExtOps);
10955 return DAG.getNode(ConvOp, dl, DstDouble ? MVT::f64 : MVT::f32, Ext);
10957 return DAG.getNode(ConvOp, dl, DstDouble ? MVT::f64 : MVT::f32, Ld);
10960 // Don't handle ppc_fp128 here or i1 conversions.
10961 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
10963 if (Op.getOperand(0).getValueType() == MVT::i1)
10966 // For i32 intermediate values, unfortunately, the conversion functions
10967 // leave the upper 32 bits of the value are undefined. Within the set of
10968 // scalar instructions, we have no method for zero- or sign-extending the
10969 // value. Thus, we cannot handle i32 intermediate values here.
10970 if (Op.getOperand(0).getValueType() == MVT::i32)
10973 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) &&
10974 "UINT_TO_FP is supported only with FPCVT");
10976 // If we have FCFIDS, then use it when converting to single-precision.
10977 // Otherwise, convert to double-precision and then round.
10978 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
10979 ? (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDUS
10981 : (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDU
10983 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
10987 // If we're converting from a float, to an int, and back to a float again,
10988 // then we don't need the store/load pair at all.
10989 if ((Op.getOperand(0).getOpcode() == ISD::FP_TO_UINT &&
10990 Subtarget.hasFPCVT()) ||
10991 (Op.getOperand(0).getOpcode() == ISD::FP_TO_SINT)) {
10992 SDValue Src = Op.getOperand(0).getOperand(0);
10993 if (Src.getValueType() == MVT::f32) {
10994 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
10995 DCI.AddToWorklist(Src.getNode());
10996 } else if (Src.getValueType() != MVT::f64) {
10997 // Make sure that we don't pick up a ppc_fp128 source value.
11002 Op.getOperand(0).getOpcode() == ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
11005 SDValue Tmp = DAG.getNode(FCTOp, dl, MVT::f64, Src);
11006 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Tmp);
11008 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT()) {
11009 FP = DAG.getNode(ISD::FP_ROUND, dl,
11010 MVT::f32, FP, DAG.getIntPtrConstant(0, dl));
11011 DCI.AddToWorklist(FP.getNode());
11020 // expandVSXLoadForLE - Convert VSX loads (which may be intrinsics for
11021 // builtins) into loads with swaps.
11022 SDValue PPCTargetLowering::expandVSXLoadForLE(SDNode *N,
11023 DAGCombinerInfo &DCI) const {
11024 SelectionDAG &DAG = DCI.DAG;
11028 MachineMemOperand *MMO;
11030 switch (N->getOpcode()) {
11032 llvm_unreachable("Unexpected opcode for little endian VSX load");
11034 LoadSDNode *LD = cast<LoadSDNode>(N);
11035 Chain = LD->getChain();
11036 Base = LD->getBasePtr();
11037 MMO = LD->getMemOperand();
11038 // If the MMO suggests this isn't a load of a full vector, leave
11039 // things alone. For a built-in, we have to make the change for
11040 // correctness, so if there is a size problem that will be a bug.
11041 if (MMO->getSize() < 16)
11045 case ISD::INTRINSIC_W_CHAIN: {
11046 MemIntrinsicSDNode *Intrin = cast<MemIntrinsicSDNode>(N);
11047 Chain = Intrin->getChain();
11048 // Similarly to the store case below, Intrin->getBasePtr() doesn't get
11049 // us what we want. Get operand 2 instead.
11050 Base = Intrin->getOperand(2);
11051 MMO = Intrin->getMemOperand();
11056 MVT VecTy = N->getValueType(0).getSimpleVT();
11057 SDValue LoadOps[] = { Chain, Base };
11058 SDValue Load = DAG.getMemIntrinsicNode(PPCISD::LXVD2X, dl,
11059 DAG.getVTList(MVT::v2f64, MVT::Other),
11060 LoadOps, MVT::v2f64, MMO);
11062 DCI.AddToWorklist(Load.getNode());
11063 Chain = Load.getValue(1);
11064 SDValue Swap = DAG.getNode(
11065 PPCISD::XXSWAPD, dl, DAG.getVTList(MVT::v2f64, MVT::Other), Chain, Load);
11066 DCI.AddToWorklist(Swap.getNode());
11068 // Add a bitcast if the resulting load type doesn't match v2f64.
11069 if (VecTy != MVT::v2f64) {
11070 SDValue N = DAG.getNode(ISD::BITCAST, dl, VecTy, Swap);
11071 DCI.AddToWorklist(N.getNode());
11072 // Package {bitcast value, swap's chain} to match Load's shape.
11073 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(VecTy, MVT::Other),
11074 N, Swap.getValue(1));
11080 // expandVSXStoreForLE - Convert VSX stores (which may be intrinsics for
11081 // builtins) into stores with swaps.
11082 SDValue PPCTargetLowering::expandVSXStoreForLE(SDNode *N,
11083 DAGCombinerInfo &DCI) const {
11084 SelectionDAG &DAG = DCI.DAG;
11089 MachineMemOperand *MMO;
11091 switch (N->getOpcode()) {
11093 llvm_unreachable("Unexpected opcode for little endian VSX store");
11095 StoreSDNode *ST = cast<StoreSDNode>(N);
11096 Chain = ST->getChain();
11097 Base = ST->getBasePtr();
11098 MMO = ST->getMemOperand();
11100 // If the MMO suggests this isn't a store of a full vector, leave
11101 // things alone. For a built-in, we have to make the change for
11102 // correctness, so if there is a size problem that will be a bug.
11103 if (MMO->getSize() < 16)
11107 case ISD::INTRINSIC_VOID: {
11108 MemIntrinsicSDNode *Intrin = cast<MemIntrinsicSDNode>(N);
11109 Chain = Intrin->getChain();
11110 // Intrin->getBasePtr() oddly does not get what we want.
11111 Base = Intrin->getOperand(3);
11112 MMO = Intrin->getMemOperand();
11118 SDValue Src = N->getOperand(SrcOpnd);
11119 MVT VecTy = Src.getValueType().getSimpleVT();
11121 // All stores are done as v2f64 and possible bit cast.
11122 if (VecTy != MVT::v2f64) {
11123 Src = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Src);
11124 DCI.AddToWorklist(Src.getNode());
11127 SDValue Swap = DAG.getNode(PPCISD::XXSWAPD, dl,
11128 DAG.getVTList(MVT::v2f64, MVT::Other), Chain, Src);
11129 DCI.AddToWorklist(Swap.getNode());
11130 Chain = Swap.getValue(1);
11131 SDValue StoreOps[] = { Chain, Swap, Base };
11132 SDValue Store = DAG.getMemIntrinsicNode(PPCISD::STXVD2X, dl,
11133 DAG.getVTList(MVT::Other),
11134 StoreOps, VecTy, MMO);
11135 DCI.AddToWorklist(Store.getNode());
11139 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
11140 DAGCombinerInfo &DCI) const {
11141 SelectionDAG &DAG = DCI.DAG;
11143 switch (N->getOpcode()) {
11146 if (isNullConstant(N->getOperand(0))) // 0 << V -> 0.
11147 return N->getOperand(0);
11150 if (isNullConstant(N->getOperand(0))) // 0 >>u V -> 0.
11151 return N->getOperand(0);
11154 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
11155 if (C->isNullValue() || // 0 >>s V -> 0.
11156 C->isAllOnesValue()) // -1 >>s V -> -1.
11157 return N->getOperand(0);
11160 case ISD::SIGN_EXTEND:
11161 case ISD::ZERO_EXTEND:
11162 case ISD::ANY_EXTEND:
11163 return DAGCombineExtBoolTrunc(N, DCI);
11164 case ISD::TRUNCATE:
11166 case ISD::SELECT_CC:
11167 return DAGCombineTruncBoolExt(N, DCI);
11168 case ISD::SINT_TO_FP:
11169 case ISD::UINT_TO_FP:
11170 return combineFPToIntToFP(N, DCI);
11172 EVT Op1VT = N->getOperand(1).getValueType();
11173 bool ValidTypeForStoreFltAsInt = (Op1VT == MVT::i32) ||
11174 (Subtarget.hasP9Vector() && (Op1VT == MVT::i8 || Op1VT == MVT::i16));
11176 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
11177 if (Subtarget.hasSTFIWX() && !cast<StoreSDNode>(N)->isTruncatingStore() &&
11178 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
11179 ValidTypeForStoreFltAsInt &&
11180 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
11181 SDValue Val = N->getOperand(1).getOperand(0);
11182 if (Val.getValueType() == MVT::f32) {
11183 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
11184 DCI.AddToWorklist(Val.getNode());
11186 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
11187 DCI.AddToWorklist(Val.getNode());
11189 if (Op1VT == MVT::i32) {
11191 N->getOperand(0), Val, N->getOperand(2),
11192 DAG.getValueType(N->getOperand(1).getValueType())
11195 Val = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
11196 DAG.getVTList(MVT::Other), Ops,
11197 cast<StoreSDNode>(N)->getMemoryVT(),
11198 cast<StoreSDNode>(N)->getMemOperand());
11200 unsigned WidthInBytes =
11201 N->getOperand(1).getValueType() == MVT::i8 ? 1 : 2;
11202 SDValue WidthConst = DAG.getIntPtrConstant(WidthInBytes, dl, false);
11205 N->getOperand(0), Val, N->getOperand(2), WidthConst,
11206 DAG.getValueType(N->getOperand(1).getValueType())
11208 Val = DAG.getMemIntrinsicNode(PPCISD::STXSIX, dl,
11209 DAG.getVTList(MVT::Other), Ops,
11210 cast<StoreSDNode>(N)->getMemoryVT(),
11211 cast<StoreSDNode>(N)->getMemOperand());
11214 DCI.AddToWorklist(Val.getNode());
11218 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
11219 if (cast<StoreSDNode>(N)->isUnindexed() &&
11220 N->getOperand(1).getOpcode() == ISD::BSWAP &&
11221 N->getOperand(1).getNode()->hasOneUse() &&
11222 (N->getOperand(1).getValueType() == MVT::i32 ||
11223 N->getOperand(1).getValueType() == MVT::i16 ||
11224 (Subtarget.hasLDBRX() && Subtarget.isPPC64() &&
11225 N->getOperand(1).getValueType() == MVT::i64))) {
11226 SDValue BSwapOp = N->getOperand(1).getOperand(0);
11227 // Do an any-extend to 32-bits if this is a half-word input.
11228 if (BSwapOp.getValueType() == MVT::i16)
11229 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
11232 N->getOperand(0), BSwapOp, N->getOperand(2),
11233 DAG.getValueType(N->getOperand(1).getValueType())
11236 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
11237 Ops, cast<StoreSDNode>(N)->getMemoryVT(),
11238 cast<StoreSDNode>(N)->getMemOperand());
11241 // For little endian, VSX stores require generating xxswapd/lxvd2x.
11242 // Not needed on ISA 3.0 based CPUs since we have a non-permuting store.
11243 EVT VT = N->getOperand(1).getValueType();
11244 if (VT.isSimple()) {
11245 MVT StoreVT = VT.getSimpleVT();
11246 if (Subtarget.needsSwapsForVSXMemOps() &&
11247 (StoreVT == MVT::v2f64 || StoreVT == MVT::v2i64 ||
11248 StoreVT == MVT::v4f32 || StoreVT == MVT::v4i32))
11249 return expandVSXStoreForLE(N, DCI);
11254 LoadSDNode *LD = cast<LoadSDNode>(N);
11255 EVT VT = LD->getValueType(0);
11257 // For little endian, VSX loads require generating lxvd2x/xxswapd.
11258 // Not needed on ISA 3.0 based CPUs since we have a non-permuting load.
11259 if (VT.isSimple()) {
11260 MVT LoadVT = VT.getSimpleVT();
11261 if (Subtarget.needsSwapsForVSXMemOps() &&
11262 (LoadVT == MVT::v2f64 || LoadVT == MVT::v2i64 ||
11263 LoadVT == MVT::v4f32 || LoadVT == MVT::v4i32))
11264 return expandVSXLoadForLE(N, DCI);
11267 // We sometimes end up with a 64-bit integer load, from which we extract
11268 // two single-precision floating-point numbers. This happens with
11269 // std::complex<float>, and other similar structures, because of the way we
11270 // canonicalize structure copies. However, if we lack direct moves,
11271 // then the final bitcasts from the extracted integer values to the
11272 // floating-point numbers turn into store/load pairs. Even with direct moves,
11273 // just loading the two floating-point numbers is likely better.
11274 auto ReplaceTwoFloatLoad = [&]() {
11275 if (VT != MVT::i64)
11278 if (LD->getExtensionType() != ISD::NON_EXTLOAD ||
11282 // We're looking for a sequence like this:
11283 // t13: i64,ch = load<LD8[%ref.tmp]> t0, t6, undef:i64
11284 // t16: i64 = srl t13, Constant:i32<32>
11285 // t17: i32 = truncate t16
11286 // t18: f32 = bitcast t17
11287 // t19: i32 = truncate t13
11288 // t20: f32 = bitcast t19
11290 if (!LD->hasNUsesOfValue(2, 0))
11293 auto UI = LD->use_begin();
11294 while (UI.getUse().getResNo() != 0) ++UI;
11295 SDNode *Trunc = *UI++;
11296 while (UI.getUse().getResNo() != 0) ++UI;
11297 SDNode *RightShift = *UI;
11298 if (Trunc->getOpcode() != ISD::TRUNCATE)
11299 std::swap(Trunc, RightShift);
11301 if (Trunc->getOpcode() != ISD::TRUNCATE ||
11302 Trunc->getValueType(0) != MVT::i32 ||
11303 !Trunc->hasOneUse())
11305 if (RightShift->getOpcode() != ISD::SRL ||
11306 !isa<ConstantSDNode>(RightShift->getOperand(1)) ||
11307 RightShift->getConstantOperandVal(1) != 32 ||
11308 !RightShift->hasOneUse())
11311 SDNode *Trunc2 = *RightShift->use_begin();
11312 if (Trunc2->getOpcode() != ISD::TRUNCATE ||
11313 Trunc2->getValueType(0) != MVT::i32 ||
11314 !Trunc2->hasOneUse())
11317 SDNode *Bitcast = *Trunc->use_begin();
11318 SDNode *Bitcast2 = *Trunc2->use_begin();
11320 if (Bitcast->getOpcode() != ISD::BITCAST ||
11321 Bitcast->getValueType(0) != MVT::f32)
11323 if (Bitcast2->getOpcode() != ISD::BITCAST ||
11324 Bitcast2->getValueType(0) != MVT::f32)
11327 if (Subtarget.isLittleEndian())
11328 std::swap(Bitcast, Bitcast2);
11330 // Bitcast has the second float (in memory-layout order) and Bitcast2
11331 // has the first one.
11333 SDValue BasePtr = LD->getBasePtr();
11334 if (LD->isIndexed()) {
11335 assert(LD->getAddressingMode() == ISD::PRE_INC &&
11336 "Non-pre-inc AM on PPC?");
11338 DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
11343 LD->getMemOperand()->getFlags() & ~MachineMemOperand::MOVolatile;
11344 SDValue FloatLoad = DAG.getLoad(MVT::f32, dl, LD->getChain(), BasePtr,
11345 LD->getPointerInfo(), LD->getAlignment(),
11346 MMOFlags, LD->getAAInfo());
11348 DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
11349 BasePtr, DAG.getIntPtrConstant(4, dl));
11350 SDValue FloatLoad2 = DAG.getLoad(
11351 MVT::f32, dl, SDValue(FloatLoad.getNode(), 1), AddPtr,
11352 LD->getPointerInfo().getWithOffset(4),
11353 MinAlign(LD->getAlignment(), 4), MMOFlags, LD->getAAInfo());
11355 if (LD->isIndexed()) {
11356 // Note that DAGCombine should re-form any pre-increment load(s) from
11357 // what is produced here if that makes sense.
11358 DAG.ReplaceAllUsesOfValueWith(SDValue(LD, 1), BasePtr);
11361 DCI.CombineTo(Bitcast2, FloatLoad);
11362 DCI.CombineTo(Bitcast, FloatLoad2);
11364 DAG.ReplaceAllUsesOfValueWith(SDValue(LD, LD->isIndexed() ? 2 : 1),
11365 SDValue(FloatLoad2.getNode(), 1));
11369 if (ReplaceTwoFloatLoad())
11370 return SDValue(N, 0);
11372 EVT MemVT = LD->getMemoryVT();
11373 Type *Ty = MemVT.getTypeForEVT(*DAG.getContext());
11374 unsigned ABIAlignment = DAG.getDataLayout().getABITypeAlignment(Ty);
11375 Type *STy = MemVT.getScalarType().getTypeForEVT(*DAG.getContext());
11376 unsigned ScalarABIAlignment = DAG.getDataLayout().getABITypeAlignment(STy);
11377 if (LD->isUnindexed() && VT.isVector() &&
11378 ((Subtarget.hasAltivec() && ISD::isNON_EXTLoad(N) &&
11379 // P8 and later hardware should just use LOAD.
11380 !Subtarget.hasP8Vector() && (VT == MVT::v16i8 || VT == MVT::v8i16 ||
11381 VT == MVT::v4i32 || VT == MVT::v4f32)) ||
11382 (Subtarget.hasQPX() && (VT == MVT::v4f64 || VT == MVT::v4f32) &&
11383 LD->getAlignment() >= ScalarABIAlignment)) &&
11384 LD->getAlignment() < ABIAlignment) {
11385 // This is a type-legal unaligned Altivec or QPX load.
11386 SDValue Chain = LD->getChain();
11387 SDValue Ptr = LD->getBasePtr();
11388 bool isLittleEndian = Subtarget.isLittleEndian();
11390 // This implements the loading of unaligned vectors as described in
11391 // the venerable Apple Velocity Engine overview. Specifically:
11392 // https://developer.apple.com/hardwaredrivers/ve/alignment.html
11393 // https://developer.apple.com/hardwaredrivers/ve/code_optimization.html
11395 // The general idea is to expand a sequence of one or more unaligned
11396 // loads into an alignment-based permutation-control instruction (lvsl
11397 // or lvsr), a series of regular vector loads (which always truncate
11398 // their input address to an aligned address), and a series of
11399 // permutations. The results of these permutations are the requested
11400 // loaded values. The trick is that the last "extra" load is not taken
11401 // from the address you might suspect (sizeof(vector) bytes after the
11402 // last requested load), but rather sizeof(vector) - 1 bytes after the
11403 // last requested vector. The point of this is to avoid a page fault if
11404 // the base address happened to be aligned. This works because if the
11405 // base address is aligned, then adding less than a full vector length
11406 // will cause the last vector in the sequence to be (re)loaded.
11407 // Otherwise, the next vector will be fetched as you might suspect was
11410 // We might be able to reuse the permutation generation from
11411 // a different base address offset from this one by an aligned amount.
11412 // The INTRINSIC_WO_CHAIN DAG combine will attempt to perform this
11413 // optimization later.
11414 Intrinsic::ID Intr, IntrLD, IntrPerm;
11415 MVT PermCntlTy, PermTy, LDTy;
11416 if (Subtarget.hasAltivec()) {
11417 Intr = isLittleEndian ? Intrinsic::ppc_altivec_lvsr :
11418 Intrinsic::ppc_altivec_lvsl;
11419 IntrLD = Intrinsic::ppc_altivec_lvx;
11420 IntrPerm = Intrinsic::ppc_altivec_vperm;
11421 PermCntlTy = MVT::v16i8;
11422 PermTy = MVT::v4i32;
11425 Intr = MemVT == MVT::v4f64 ? Intrinsic::ppc_qpx_qvlpcld :
11426 Intrinsic::ppc_qpx_qvlpcls;
11427 IntrLD = MemVT == MVT::v4f64 ? Intrinsic::ppc_qpx_qvlfd :
11428 Intrinsic::ppc_qpx_qvlfs;
11429 IntrPerm = Intrinsic::ppc_qpx_qvfperm;
11430 PermCntlTy = MVT::v4f64;
11431 PermTy = MVT::v4f64;
11432 LDTy = MemVT.getSimpleVT();
11435 SDValue PermCntl = BuildIntrinsicOp(Intr, Ptr, DAG, dl, PermCntlTy);
11437 // Create the new MMO for the new base load. It is like the original MMO,
11438 // but represents an area in memory almost twice the vector size centered
11439 // on the original address. If the address is unaligned, we might start
11440 // reading up to (sizeof(vector)-1) bytes below the address of the
11441 // original unaligned load.
11442 MachineFunction &MF = DAG.getMachineFunction();
11443 MachineMemOperand *BaseMMO =
11444 MF.getMachineMemOperand(LD->getMemOperand(),
11445 -(long)MemVT.getStoreSize()+1,
11446 2*MemVT.getStoreSize()-1);
11448 // Create the new base load.
11450 DAG.getTargetConstant(IntrLD, dl, getPointerTy(MF.getDataLayout()));
11451 SDValue BaseLoadOps[] = { Chain, LDXIntID, Ptr };
11453 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, dl,
11454 DAG.getVTList(PermTy, MVT::Other),
11455 BaseLoadOps, LDTy, BaseMMO);
11457 // Note that the value of IncOffset (which is provided to the next
11458 // load's pointer info offset value, and thus used to calculate the
11459 // alignment), and the value of IncValue (which is actually used to
11460 // increment the pointer value) are different! This is because we
11461 // require the next load to appear to be aligned, even though it
11462 // is actually offset from the base pointer by a lesser amount.
11463 int IncOffset = VT.getSizeInBits() / 8;
11464 int IncValue = IncOffset;
11466 // Walk (both up and down) the chain looking for another load at the real
11467 // (aligned) offset (the alignment of the other load does not matter in
11468 // this case). If found, then do not use the offset reduction trick, as
11469 // that will prevent the loads from being later combined (as they would
11470 // otherwise be duplicates).
11471 if (!findConsecutiveLoad(LD, DAG))
11474 SDValue Increment =
11475 DAG.getConstant(IncValue, dl, getPointerTy(MF.getDataLayout()));
11476 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
11478 MachineMemOperand *ExtraMMO =
11479 MF.getMachineMemOperand(LD->getMemOperand(),
11480 1, 2*MemVT.getStoreSize()-1);
11481 SDValue ExtraLoadOps[] = { Chain, LDXIntID, Ptr };
11482 SDValue ExtraLoad =
11483 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, dl,
11484 DAG.getVTList(PermTy, MVT::Other),
11485 ExtraLoadOps, LDTy, ExtraMMO);
11487 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
11488 BaseLoad.getValue(1), ExtraLoad.getValue(1));
11490 // Because vperm has a big-endian bias, we must reverse the order
11491 // of the input vectors and complement the permute control vector
11492 // when generating little endian code. We have already handled the
11493 // latter by using lvsr instead of lvsl, so just reverse BaseLoad
11494 // and ExtraLoad here.
11496 if (isLittleEndian)
11497 Perm = BuildIntrinsicOp(IntrPerm,
11498 ExtraLoad, BaseLoad, PermCntl, DAG, dl);
11500 Perm = BuildIntrinsicOp(IntrPerm,
11501 BaseLoad, ExtraLoad, PermCntl, DAG, dl);
11504 Perm = Subtarget.hasAltivec() ?
11505 DAG.getNode(ISD::BITCAST, dl, VT, Perm) :
11506 DAG.getNode(ISD::FP_ROUND, dl, VT, Perm, // QPX
11507 DAG.getTargetConstant(1, dl, MVT::i64));
11508 // second argument is 1 because this rounding
11509 // is always exact.
11511 // The output of the permutation is our loaded result, the TokenFactor is
11513 DCI.CombineTo(N, Perm, TF);
11514 return SDValue(N, 0);
11518 case ISD::INTRINSIC_WO_CHAIN: {
11519 bool isLittleEndian = Subtarget.isLittleEndian();
11520 unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
11521 Intrinsic::ID Intr = (isLittleEndian ? Intrinsic::ppc_altivec_lvsr
11522 : Intrinsic::ppc_altivec_lvsl);
11523 if ((IID == Intr ||
11524 IID == Intrinsic::ppc_qpx_qvlpcld ||
11525 IID == Intrinsic::ppc_qpx_qvlpcls) &&
11526 N->getOperand(1)->getOpcode() == ISD::ADD) {
11527 SDValue Add = N->getOperand(1);
11529 int Bits = IID == Intrinsic::ppc_qpx_qvlpcld ?
11530 5 /* 32 byte alignment */ : 4 /* 16 byte alignment */;
11532 if (DAG.MaskedValueIsZero(Add->getOperand(1),
11533 APInt::getAllOnesValue(Bits /* alignment */)
11534 .zext(Add.getScalarValueSizeInBits()))) {
11535 SDNode *BasePtr = Add->getOperand(0).getNode();
11536 for (SDNode::use_iterator UI = BasePtr->use_begin(),
11537 UE = BasePtr->use_end();
11539 if (UI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
11540 cast<ConstantSDNode>(UI->getOperand(0))->getZExtValue() == IID) {
11541 // We've found another LVSL/LVSR, and this address is an aligned
11542 // multiple of that one. The results will be the same, so use the
11543 // one we've just found instead.
11545 return SDValue(*UI, 0);
11550 if (isa<ConstantSDNode>(Add->getOperand(1))) {
11551 SDNode *BasePtr = Add->getOperand(0).getNode();
11552 for (SDNode::use_iterator UI = BasePtr->use_begin(),
11553 UE = BasePtr->use_end(); UI != UE; ++UI) {
11554 if (UI->getOpcode() == ISD::ADD &&
11555 isa<ConstantSDNode>(UI->getOperand(1)) &&
11556 (cast<ConstantSDNode>(Add->getOperand(1))->getZExtValue() -
11557 cast<ConstantSDNode>(UI->getOperand(1))->getZExtValue()) %
11558 (1ULL << Bits) == 0) {
11559 SDNode *OtherAdd = *UI;
11560 for (SDNode::use_iterator VI = OtherAdd->use_begin(),
11561 VE = OtherAdd->use_end(); VI != VE; ++VI) {
11562 if (VI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
11563 cast<ConstantSDNode>(VI->getOperand(0))->getZExtValue() == IID) {
11564 return SDValue(*VI, 0);
11574 case ISD::INTRINSIC_W_CHAIN: {
11575 // For little endian, VSX loads require generating lxvd2x/xxswapd.
11576 // Not needed on ISA 3.0 based CPUs since we have a non-permuting load.
11577 if (Subtarget.needsSwapsForVSXMemOps()) {
11578 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
11581 case Intrinsic::ppc_vsx_lxvw4x:
11582 case Intrinsic::ppc_vsx_lxvd2x:
11583 return expandVSXLoadForLE(N, DCI);
11588 case ISD::INTRINSIC_VOID: {
11589 // For little endian, VSX stores require generating xxswapd/stxvd2x.
11590 // Not needed on ISA 3.0 based CPUs since we have a non-permuting store.
11591 if (Subtarget.needsSwapsForVSXMemOps()) {
11592 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
11595 case Intrinsic::ppc_vsx_stxvw4x:
11596 case Intrinsic::ppc_vsx_stxvd2x:
11597 return expandVSXStoreForLE(N, DCI);
11603 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
11604 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
11605 N->getOperand(0).hasOneUse() &&
11606 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 ||
11607 (Subtarget.hasLDBRX() && Subtarget.isPPC64() &&
11608 N->getValueType(0) == MVT::i64))) {
11609 SDValue Load = N->getOperand(0);
11610 LoadSDNode *LD = cast<LoadSDNode>(Load);
11611 // Create the byte-swapping load.
11613 LD->getChain(), // Chain
11614 LD->getBasePtr(), // Ptr
11615 DAG.getValueType(N->getValueType(0)) // VT
11618 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
11619 DAG.getVTList(N->getValueType(0) == MVT::i64 ?
11620 MVT::i64 : MVT::i32, MVT::Other),
11621 Ops, LD->getMemoryVT(), LD->getMemOperand());
11623 // If this is an i16 load, insert the truncate.
11624 SDValue ResVal = BSLoad;
11625 if (N->getValueType(0) == MVT::i16)
11626 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
11628 // First, combine the bswap away. This makes the value produced by the
11630 DCI.CombineTo(N, ResVal);
11632 // Next, combine the load away, we give it a bogus result value but a real
11633 // chain result. The result value is dead because the bswap is dead.
11634 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
11636 // Return N so it doesn't get rechecked!
11637 return SDValue(N, 0);
11641 case PPCISD::VCMP: {
11642 // If a VCMPo node already exists with exactly the same operands as this
11643 // node, use its result instead of this node (VCMPo computes both a CR6 and
11644 // a normal output).
11646 if (!N->getOperand(0).hasOneUse() &&
11647 !N->getOperand(1).hasOneUse() &&
11648 !N->getOperand(2).hasOneUse()) {
11650 // Scan all of the users of the LHS, looking for VCMPo's that match.
11651 SDNode *VCMPoNode = nullptr;
11653 SDNode *LHSN = N->getOperand(0).getNode();
11654 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
11656 if (UI->getOpcode() == PPCISD::VCMPo &&
11657 UI->getOperand(1) == N->getOperand(1) &&
11658 UI->getOperand(2) == N->getOperand(2) &&
11659 UI->getOperand(0) == N->getOperand(0)) {
11664 // If there is no VCMPo node, or if the flag value has a single use, don't
11666 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
11669 // Look at the (necessarily single) use of the flag value. If it has a
11670 // chain, this transformation is more complex. Note that multiple things
11671 // could use the value result, which we should ignore.
11672 SDNode *FlagUser = nullptr;
11673 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
11674 FlagUser == nullptr; ++UI) {
11675 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
11676 SDNode *User = *UI;
11677 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
11678 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
11685 // If the user is a MFOCRF instruction, we know this is safe.
11686 // Otherwise we give up for right now.
11687 if (FlagUser->getOpcode() == PPCISD::MFOCRF)
11688 return SDValue(VCMPoNode, 0);
11692 case ISD::BRCOND: {
11693 SDValue Cond = N->getOperand(1);
11694 SDValue Target = N->getOperand(2);
11696 if (Cond.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
11697 cast<ConstantSDNode>(Cond.getOperand(1))->getZExtValue() ==
11698 Intrinsic::ppc_is_decremented_ctr_nonzero) {
11700 // We now need to make the intrinsic dead (it cannot be instruction
11702 DAG.ReplaceAllUsesOfValueWith(Cond.getValue(1), Cond.getOperand(0));
11703 assert(Cond.getNode()->hasOneUse() &&
11704 "Counter decrement has more than one use");
11706 return DAG.getNode(PPCISD::BDNZ, dl, MVT::Other,
11707 N->getOperand(0), Target);
11712 // If this is a branch on an altivec predicate comparison, lower this so
11713 // that we don't have to do a MFOCRF: instead, branch directly on CR6. This
11714 // lowering is done pre-legalize, because the legalizer lowers the predicate
11715 // compare down to code that is difficult to reassemble.
11716 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
11717 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
11719 // Sometimes the promoted value of the intrinsic is ANDed by some non-zero
11720 // value. If so, pass-through the AND to get to the intrinsic.
11721 if (LHS.getOpcode() == ISD::AND &&
11722 LHS.getOperand(0).getOpcode() == ISD::INTRINSIC_W_CHAIN &&
11723 cast<ConstantSDNode>(LHS.getOperand(0).getOperand(1))->getZExtValue() ==
11724 Intrinsic::ppc_is_decremented_ctr_nonzero &&
11725 isa<ConstantSDNode>(LHS.getOperand(1)) &&
11726 !isNullConstant(LHS.getOperand(1)))
11727 LHS = LHS.getOperand(0);
11729 if (LHS.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
11730 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() ==
11731 Intrinsic::ppc_is_decremented_ctr_nonzero &&
11732 isa<ConstantSDNode>(RHS)) {
11733 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
11734 "Counter decrement comparison is not EQ or NE");
11736 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
11737 bool isBDNZ = (CC == ISD::SETEQ && Val) ||
11738 (CC == ISD::SETNE && !Val);
11740 // We now need to make the intrinsic dead (it cannot be instruction
11742 DAG.ReplaceAllUsesOfValueWith(LHS.getValue(1), LHS.getOperand(0));
11743 assert(LHS.getNode()->hasOneUse() &&
11744 "Counter decrement has more than one use");
11746 return DAG.getNode(isBDNZ ? PPCISD::BDNZ : PPCISD::BDZ, dl, MVT::Other,
11747 N->getOperand(0), N->getOperand(4));
11753 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
11754 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
11755 getVectorCompareInfo(LHS, CompareOpc, isDot, Subtarget)) {
11756 assert(isDot && "Can't compare against a vector result!");
11758 // If this is a comparison against something other than 0/1, then we know
11759 // that the condition is never/always true.
11760 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
11761 if (Val != 0 && Val != 1) {
11762 if (CC == ISD::SETEQ) // Cond never true, remove branch.
11763 return N->getOperand(0);
11764 // Always !=, turn it into an unconditional branch.
11765 return DAG.getNode(ISD::BR, dl, MVT::Other,
11766 N->getOperand(0), N->getOperand(4));
11769 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
11771 // Create the PPCISD altivec 'dot' comparison node.
11773 LHS.getOperand(2), // LHS of compare
11774 LHS.getOperand(3), // RHS of compare
11775 DAG.getConstant(CompareOpc, dl, MVT::i32)
11777 EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue };
11778 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
11780 // Unpack the result based on how the target uses it.
11781 PPC::Predicate CompOpc;
11782 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
11783 default: // Can't happen, don't crash on invalid number though.
11784 case 0: // Branch on the value of the EQ bit of CR6.
11785 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
11787 case 1: // Branch on the inverted value of the EQ bit of CR6.
11788 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
11790 case 2: // Branch on the value of the LT bit of CR6.
11791 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
11793 case 3: // Branch on the inverted value of the LT bit of CR6.
11794 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
11798 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
11799 DAG.getConstant(CompOpc, dl, MVT::i32),
11800 DAG.getRegister(PPC::CR6, MVT::i32),
11801 N->getOperand(4), CompNode.getValue(1));
11805 case ISD::BUILD_VECTOR:
11806 return DAGCombineBuildVector(N, DCI);
11813 PPCTargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
11815 std::vector<SDNode *> *Created) const {
11816 // fold (sdiv X, pow2)
11817 EVT VT = N->getValueType(0);
11818 if (VT == MVT::i64 && !Subtarget.isPPC64())
11820 if ((VT != MVT::i32 && VT != MVT::i64) ||
11821 !(Divisor.isPowerOf2() || (-Divisor).isPowerOf2()))
11825 SDValue N0 = N->getOperand(0);
11827 bool IsNegPow2 = (-Divisor).isPowerOf2();
11828 unsigned Lg2 = (IsNegPow2 ? -Divisor : Divisor).countTrailingZeros();
11829 SDValue ShiftAmt = DAG.getConstant(Lg2, DL, VT);
11831 SDValue Op = DAG.getNode(PPCISD::SRA_ADDZE, DL, VT, N0, ShiftAmt);
11833 Created->push_back(Op.getNode());
11836 Op = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), Op);
11838 Created->push_back(Op.getNode());
11844 //===----------------------------------------------------------------------===//
11845 // Inline Assembly Support
11846 //===----------------------------------------------------------------------===//
11848 void PPCTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
11851 const SelectionDAG &DAG,
11852 unsigned Depth) const {
11853 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
11854 switch (Op.getOpcode()) {
11856 case PPCISD::LBRX: {
11857 // lhbrx is known to have the top bits cleared out.
11858 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
11859 KnownZero = 0xFFFF0000;
11862 case ISD::INTRINSIC_WO_CHAIN: {
11863 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
11865 case Intrinsic::ppc_altivec_vcmpbfp_p:
11866 case Intrinsic::ppc_altivec_vcmpeqfp_p:
11867 case Intrinsic::ppc_altivec_vcmpequb_p:
11868 case Intrinsic::ppc_altivec_vcmpequh_p:
11869 case Intrinsic::ppc_altivec_vcmpequw_p:
11870 case Intrinsic::ppc_altivec_vcmpequd_p:
11871 case Intrinsic::ppc_altivec_vcmpgefp_p:
11872 case Intrinsic::ppc_altivec_vcmpgtfp_p:
11873 case Intrinsic::ppc_altivec_vcmpgtsb_p:
11874 case Intrinsic::ppc_altivec_vcmpgtsh_p:
11875 case Intrinsic::ppc_altivec_vcmpgtsw_p:
11876 case Intrinsic::ppc_altivec_vcmpgtsd_p:
11877 case Intrinsic::ppc_altivec_vcmpgtub_p:
11878 case Intrinsic::ppc_altivec_vcmpgtuh_p:
11879 case Intrinsic::ppc_altivec_vcmpgtuw_p:
11880 case Intrinsic::ppc_altivec_vcmpgtud_p:
11881 KnownZero = ~1U; // All bits but the low one are known to be zero.
11888 unsigned PPCTargetLowering::getPrefLoopAlignment(MachineLoop *ML) const {
11889 switch (Subtarget.getDarwinDirective()) {
11892 case PPC::DIR_PWR4:
11893 case PPC::DIR_PWR5:
11894 case PPC::DIR_PWR5X:
11895 case PPC::DIR_PWR6:
11896 case PPC::DIR_PWR6X:
11897 case PPC::DIR_PWR7:
11898 case PPC::DIR_PWR8:
11899 case PPC::DIR_PWR9: {
11903 const PPCInstrInfo *TII = Subtarget.getInstrInfo();
11905 // For small loops (between 5 and 8 instructions), align to a 32-byte
11906 // boundary so that the entire loop fits in one instruction-cache line.
11907 uint64_t LoopSize = 0;
11908 for (auto I = ML->block_begin(), IE = ML->block_end(); I != IE; ++I)
11909 for (auto J = (*I)->begin(), JE = (*I)->end(); J != JE; ++J) {
11910 LoopSize += TII->getInstSizeInBytes(*J);
11915 if (LoopSize > 16 && LoopSize <= 32)
11922 return TargetLowering::getPrefLoopAlignment(ML);
11925 /// getConstraintType - Given a constraint, return the type of
11926 /// constraint it is for this target.
11927 PPCTargetLowering::ConstraintType
11928 PPCTargetLowering::getConstraintType(StringRef Constraint) const {
11929 if (Constraint.size() == 1) {
11930 switch (Constraint[0]) {
11938 return C_RegisterClass;
11940 // FIXME: While Z does indicate a memory constraint, it specifically
11941 // indicates an r+r address (used in conjunction with the 'y' modifier
11942 // in the replacement string). Currently, we're forcing the base
11943 // register to be r0 in the asm printer (which is interpreted as zero)
11944 // and forming the complete address in the second register. This is
11948 } else if (Constraint == "wc") { // individual CR bits.
11949 return C_RegisterClass;
11950 } else if (Constraint == "wa" || Constraint == "wd" ||
11951 Constraint == "wf" || Constraint == "ws") {
11952 return C_RegisterClass; // VSX registers.
11954 return TargetLowering::getConstraintType(Constraint);
11957 /// Examine constraint type and operand type and determine a weight value.
11958 /// This object must already have been set up with the operand type
11959 /// and the current alternative constraint selected.
11960 TargetLowering::ConstraintWeight
11961 PPCTargetLowering::getSingleConstraintMatchWeight(
11962 AsmOperandInfo &info, const char *constraint) const {
11963 ConstraintWeight weight = CW_Invalid;
11964 Value *CallOperandVal = info.CallOperandVal;
11965 // If we don't have a value, we can't do a match,
11966 // but allow it at the lowest weight.
11967 if (!CallOperandVal)
11969 Type *type = CallOperandVal->getType();
11971 // Look at the constraint type.
11972 if (StringRef(constraint) == "wc" && type->isIntegerTy(1))
11973 return CW_Register; // an individual CR bit.
11974 else if ((StringRef(constraint) == "wa" ||
11975 StringRef(constraint) == "wd" ||
11976 StringRef(constraint) == "wf") &&
11977 type->isVectorTy())
11978 return CW_Register;
11979 else if (StringRef(constraint) == "ws" && type->isDoubleTy())
11980 return CW_Register;
11982 switch (*constraint) {
11984 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
11987 if (type->isIntegerTy())
11988 weight = CW_Register;
11991 if (type->isFloatTy())
11992 weight = CW_Register;
11995 if (type->isDoubleTy())
11996 weight = CW_Register;
11999 if (type->isVectorTy())
12000 weight = CW_Register;
12003 weight = CW_Register;
12006 weight = CW_Memory;
12012 std::pair<unsigned, const TargetRegisterClass *>
12013 PPCTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
12014 StringRef Constraint,
12016 if (Constraint.size() == 1) {
12017 // GCC RS6000 Constraint Letters
12018 switch (Constraint[0]) {
12019 case 'b': // R1-R31
12020 if (VT == MVT::i64 && Subtarget.isPPC64())
12021 return std::make_pair(0U, &PPC::G8RC_NOX0RegClass);
12022 return std::make_pair(0U, &PPC::GPRC_NOR0RegClass);
12023 case 'r': // R0-R31
12024 if (VT == MVT::i64 && Subtarget.isPPC64())
12025 return std::make_pair(0U, &PPC::G8RCRegClass);
12026 return std::make_pair(0U, &PPC::GPRCRegClass);
12027 // 'd' and 'f' constraints are both defined to be "the floating point
12028 // registers", where one is for 32-bit and the other for 64-bit. We don't
12029 // really care overly much here so just give them all the same reg classes.
12032 if (VT == MVT::f32 || VT == MVT::i32)
12033 return std::make_pair(0U, &PPC::F4RCRegClass);
12034 if (VT == MVT::f64 || VT == MVT::i64)
12035 return std::make_pair(0U, &PPC::F8RCRegClass);
12036 if (VT == MVT::v4f64 && Subtarget.hasQPX())
12037 return std::make_pair(0U, &PPC::QFRCRegClass);
12038 if (VT == MVT::v4f32 && Subtarget.hasQPX())
12039 return std::make_pair(0U, &PPC::QSRCRegClass);
12042 if (VT == MVT::v4f64 && Subtarget.hasQPX())
12043 return std::make_pair(0U, &PPC::QFRCRegClass);
12044 if (VT == MVT::v4f32 && Subtarget.hasQPX())
12045 return std::make_pair(0U, &PPC::QSRCRegClass);
12046 if (Subtarget.hasAltivec())
12047 return std::make_pair(0U, &PPC::VRRCRegClass);
12049 return std::make_pair(0U, &PPC::CRRCRegClass);
12051 } else if (Constraint == "wc" && Subtarget.useCRBits()) {
12052 // An individual CR bit.
12053 return std::make_pair(0U, &PPC::CRBITRCRegClass);
12054 } else if ((Constraint == "wa" || Constraint == "wd" ||
12055 Constraint == "wf") && Subtarget.hasVSX()) {
12056 return std::make_pair(0U, &PPC::VSRCRegClass);
12057 } else if (Constraint == "ws" && Subtarget.hasVSX()) {
12058 if (VT == MVT::f32 && Subtarget.hasP8Vector())
12059 return std::make_pair(0U, &PPC::VSSRCRegClass);
12061 return std::make_pair(0U, &PPC::VSFRCRegClass);
12064 std::pair<unsigned, const TargetRegisterClass *> R =
12065 TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
12067 // r[0-9]+ are used, on PPC64, to refer to the corresponding 64-bit registers
12068 // (which we call X[0-9]+). If a 64-bit value has been requested, and a
12069 // 32-bit GPR has been selected, then 'upgrade' it to the 64-bit parent
12071 // FIXME: If TargetLowering::getRegForInlineAsmConstraint could somehow use
12072 // the AsmName field from *RegisterInfo.td, then this would not be necessary.
12073 if (R.first && VT == MVT::i64 && Subtarget.isPPC64() &&
12074 PPC::GPRCRegClass.contains(R.first))
12075 return std::make_pair(TRI->getMatchingSuperReg(R.first,
12076 PPC::sub_32, &PPC::G8RCRegClass),
12077 &PPC::G8RCRegClass);
12079 // GCC accepts 'cc' as an alias for 'cr0', and we need to do the same.
12080 if (!R.second && StringRef("{cc}").equals_lower(Constraint)) {
12081 R.first = PPC::CR0;
12082 R.second = &PPC::CRRCRegClass;
12088 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
12089 /// vector. If it is invalid, don't add anything to Ops.
12090 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
12091 std::string &Constraint,
12092 std::vector<SDValue>&Ops,
12093 SelectionDAG &DAG) const {
12096 // Only support length 1 constraints.
12097 if (Constraint.length() > 1) return;
12099 char Letter = Constraint[0];
12110 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
12111 if (!CST) return; // Must be an immediate to match.
12113 int64_t Value = CST->getSExtValue();
12114 EVT TCVT = MVT::i64; // All constants taken to be 64 bits so that negative
12115 // numbers are printed as such.
12117 default: llvm_unreachable("Unknown constraint letter!");
12118 case 'I': // "I" is a signed 16-bit constant.
12119 if (isInt<16>(Value))
12120 Result = DAG.getTargetConstant(Value, dl, TCVT);
12122 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
12123 if (isShiftedUInt<16, 16>(Value))
12124 Result = DAG.getTargetConstant(Value, dl, TCVT);
12126 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
12127 if (isShiftedInt<16, 16>(Value))
12128 Result = DAG.getTargetConstant(Value, dl, TCVT);
12130 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
12131 if (isUInt<16>(Value))
12132 Result = DAG.getTargetConstant(Value, dl, TCVT);
12134 case 'M': // "M" is a constant that is greater than 31.
12136 Result = DAG.getTargetConstant(Value, dl, TCVT);
12138 case 'N': // "N" is a positive constant that is an exact power of two.
12139 if (Value > 0 && isPowerOf2_64(Value))
12140 Result = DAG.getTargetConstant(Value, dl, TCVT);
12142 case 'O': // "O" is the constant zero.
12144 Result = DAG.getTargetConstant(Value, dl, TCVT);
12146 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
12147 if (isInt<16>(-Value))
12148 Result = DAG.getTargetConstant(Value, dl, TCVT);
12155 if (Result.getNode()) {
12156 Ops.push_back(Result);
12160 // Handle standard constraint letters.
12161 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
12164 // isLegalAddressingMode - Return true if the addressing mode represented
12165 // by AM is legal for this target, for a load/store of the specified type.
12166 bool PPCTargetLowering::isLegalAddressingMode(const DataLayout &DL,
12167 const AddrMode &AM, Type *Ty,
12168 unsigned AS) const {
12169 // PPC does not allow r+i addressing modes for vectors!
12170 if (Ty->isVectorTy() && AM.BaseOffs != 0)
12173 // PPC allows a sign-extended 16-bit immediate field.
12174 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
12177 // No global is ever allowed as a base.
12181 // PPC only support r+r,
12182 switch (AM.Scale) {
12183 case 0: // "r+i" or just "i", depending on HasBaseReg.
12186 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
12188 // Otherwise we have r+r or r+i.
12191 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
12193 // Allow 2*r as r+r.
12196 // No other scales are supported.
12203 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
12204 SelectionDAG &DAG) const {
12205 MachineFunction &MF = DAG.getMachineFunction();
12206 MachineFrameInfo &MFI = MF.getFrameInfo();
12207 MFI.setReturnAddressIsTaken(true);
12209 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
12213 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
12215 // Make sure the function does not optimize away the store of the RA to
12217 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
12218 FuncInfo->setLRStoreRequired();
12219 bool isPPC64 = Subtarget.isPPC64();
12220 auto PtrVT = getPointerTy(MF.getDataLayout());
12223 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
12225 DAG.getConstant(Subtarget.getFrameLowering()->getReturnSaveOffset(), dl,
12226 isPPC64 ? MVT::i64 : MVT::i32);
12227 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
12228 DAG.getNode(ISD::ADD, dl, PtrVT, FrameAddr, Offset),
12229 MachinePointerInfo());
12232 // Just load the return address off the stack.
12233 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
12234 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), RetAddrFI,
12235 MachinePointerInfo());
12238 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
12239 SelectionDAG &DAG) const {
12241 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
12243 MachineFunction &MF = DAG.getMachineFunction();
12244 MachineFrameInfo &MFI = MF.getFrameInfo();
12245 MFI.setFrameAddressIsTaken(true);
12247 EVT PtrVT = getPointerTy(MF.getDataLayout());
12248 bool isPPC64 = PtrVT == MVT::i64;
12250 // Naked functions never have a frame pointer, and so we use r1. For all
12251 // other functions, this decision must be delayed until during PEI.
12253 if (MF.getFunction()->hasFnAttribute(Attribute::Naked))
12254 FrameReg = isPPC64 ? PPC::X1 : PPC::R1;
12256 FrameReg = isPPC64 ? PPC::FP8 : PPC::FP;
12258 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
12261 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
12262 FrameAddr, MachinePointerInfo());
12266 // FIXME? Maybe this could be a TableGen attribute on some registers and
12267 // this table could be generated automatically from RegInfo.
12268 unsigned PPCTargetLowering::getRegisterByName(const char* RegName, EVT VT,
12269 SelectionDAG &DAG) const {
12270 bool isPPC64 = Subtarget.isPPC64();
12271 bool isDarwinABI = Subtarget.isDarwinABI();
12273 if ((isPPC64 && VT != MVT::i64 && VT != MVT::i32) ||
12274 (!isPPC64 && VT != MVT::i32))
12275 report_fatal_error("Invalid register global variable type");
12277 bool is64Bit = isPPC64 && VT == MVT::i64;
12278 unsigned Reg = StringSwitch<unsigned>(RegName)
12279 .Case("r1", is64Bit ? PPC::X1 : PPC::R1)
12280 .Case("r2", (isDarwinABI || isPPC64) ? 0 : PPC::R2)
12281 .Case("r13", (!isPPC64 && isDarwinABI) ? 0 :
12282 (is64Bit ? PPC::X13 : PPC::R13))
12287 report_fatal_error("Invalid register name global variable");
12291 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
12292 // The PowerPC target isn't yet aware of offsets.
12296 bool PPCTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
12298 unsigned Intrinsic) const {
12300 switch (Intrinsic) {
12301 case Intrinsic::ppc_qpx_qvlfd:
12302 case Intrinsic::ppc_qpx_qvlfs:
12303 case Intrinsic::ppc_qpx_qvlfcd:
12304 case Intrinsic::ppc_qpx_qvlfcs:
12305 case Intrinsic::ppc_qpx_qvlfiwa:
12306 case Intrinsic::ppc_qpx_qvlfiwz:
12307 case Intrinsic::ppc_altivec_lvx:
12308 case Intrinsic::ppc_altivec_lvxl:
12309 case Intrinsic::ppc_altivec_lvebx:
12310 case Intrinsic::ppc_altivec_lvehx:
12311 case Intrinsic::ppc_altivec_lvewx:
12312 case Intrinsic::ppc_vsx_lxvd2x:
12313 case Intrinsic::ppc_vsx_lxvw4x: {
12315 switch (Intrinsic) {
12316 case Intrinsic::ppc_altivec_lvebx:
12319 case Intrinsic::ppc_altivec_lvehx:
12322 case Intrinsic::ppc_altivec_lvewx:
12325 case Intrinsic::ppc_vsx_lxvd2x:
12328 case Intrinsic::ppc_qpx_qvlfd:
12331 case Intrinsic::ppc_qpx_qvlfs:
12334 case Intrinsic::ppc_qpx_qvlfcd:
12337 case Intrinsic::ppc_qpx_qvlfcs:
12345 Info.opc = ISD::INTRINSIC_W_CHAIN;
12347 Info.ptrVal = I.getArgOperand(0);
12348 Info.offset = -VT.getStoreSize()+1;
12349 Info.size = 2*VT.getStoreSize()-1;
12352 Info.readMem = true;
12353 Info.writeMem = false;
12356 case Intrinsic::ppc_qpx_qvlfda:
12357 case Intrinsic::ppc_qpx_qvlfsa:
12358 case Intrinsic::ppc_qpx_qvlfcda:
12359 case Intrinsic::ppc_qpx_qvlfcsa:
12360 case Intrinsic::ppc_qpx_qvlfiwaa:
12361 case Intrinsic::ppc_qpx_qvlfiwza: {
12363 switch (Intrinsic) {
12364 case Intrinsic::ppc_qpx_qvlfda:
12367 case Intrinsic::ppc_qpx_qvlfsa:
12370 case Intrinsic::ppc_qpx_qvlfcda:
12373 case Intrinsic::ppc_qpx_qvlfcsa:
12381 Info.opc = ISD::INTRINSIC_W_CHAIN;
12383 Info.ptrVal = I.getArgOperand(0);
12385 Info.size = VT.getStoreSize();
12388 Info.readMem = true;
12389 Info.writeMem = false;
12392 case Intrinsic::ppc_qpx_qvstfd:
12393 case Intrinsic::ppc_qpx_qvstfs:
12394 case Intrinsic::ppc_qpx_qvstfcd:
12395 case Intrinsic::ppc_qpx_qvstfcs:
12396 case Intrinsic::ppc_qpx_qvstfiw:
12397 case Intrinsic::ppc_altivec_stvx:
12398 case Intrinsic::ppc_altivec_stvxl:
12399 case Intrinsic::ppc_altivec_stvebx:
12400 case Intrinsic::ppc_altivec_stvehx:
12401 case Intrinsic::ppc_altivec_stvewx:
12402 case Intrinsic::ppc_vsx_stxvd2x:
12403 case Intrinsic::ppc_vsx_stxvw4x: {
12405 switch (Intrinsic) {
12406 case Intrinsic::ppc_altivec_stvebx:
12409 case Intrinsic::ppc_altivec_stvehx:
12412 case Intrinsic::ppc_altivec_stvewx:
12415 case Intrinsic::ppc_vsx_stxvd2x:
12418 case Intrinsic::ppc_qpx_qvstfd:
12421 case Intrinsic::ppc_qpx_qvstfs:
12424 case Intrinsic::ppc_qpx_qvstfcd:
12427 case Intrinsic::ppc_qpx_qvstfcs:
12435 Info.opc = ISD::INTRINSIC_VOID;
12437 Info.ptrVal = I.getArgOperand(1);
12438 Info.offset = -VT.getStoreSize()+1;
12439 Info.size = 2*VT.getStoreSize()-1;
12442 Info.readMem = false;
12443 Info.writeMem = true;
12446 case Intrinsic::ppc_qpx_qvstfda:
12447 case Intrinsic::ppc_qpx_qvstfsa:
12448 case Intrinsic::ppc_qpx_qvstfcda:
12449 case Intrinsic::ppc_qpx_qvstfcsa:
12450 case Intrinsic::ppc_qpx_qvstfiwa: {
12452 switch (Intrinsic) {
12453 case Intrinsic::ppc_qpx_qvstfda:
12456 case Intrinsic::ppc_qpx_qvstfsa:
12459 case Intrinsic::ppc_qpx_qvstfcda:
12462 case Intrinsic::ppc_qpx_qvstfcsa:
12470 Info.opc = ISD::INTRINSIC_VOID;
12472 Info.ptrVal = I.getArgOperand(1);
12474 Info.size = VT.getStoreSize();
12477 Info.readMem = false;
12478 Info.writeMem = true;
12488 /// getOptimalMemOpType - Returns the target specific optimal type for load
12489 /// and store operations as a result of memset, memcpy, and memmove
12490 /// lowering. If DstAlign is zero that means it's safe to destination
12491 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
12492 /// means there isn't a need to check it against alignment requirement,
12493 /// probably because the source does not need to be loaded. If 'IsMemset' is
12494 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
12495 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
12496 /// source is constant so it does not need to be loaded.
12497 /// It returns EVT::Other if the type should be determined using generic
12498 /// target-independent logic.
12499 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size,
12500 unsigned DstAlign, unsigned SrcAlign,
12501 bool IsMemset, bool ZeroMemset,
12503 MachineFunction &MF) const {
12504 if (getTargetMachine().getOptLevel() != CodeGenOpt::None) {
12505 const Function *F = MF.getFunction();
12506 // When expanding a memset, require at least two QPX instructions to cover
12507 // the cost of loading the value to be stored from the constant pool.
12508 if (Subtarget.hasQPX() && Size >= 32 && (!IsMemset || Size >= 64) &&
12509 (!SrcAlign || SrcAlign >= 32) && (!DstAlign || DstAlign >= 32) &&
12510 !F->hasFnAttribute(Attribute::NoImplicitFloat)) {
12514 // We should use Altivec/VSX loads and stores when available. For unaligned
12515 // addresses, unaligned VSX loads are only fast starting with the P8.
12516 if (Subtarget.hasAltivec() && Size >= 16 &&
12517 (((!SrcAlign || SrcAlign >= 16) && (!DstAlign || DstAlign >= 16)) ||
12518 ((IsMemset && Subtarget.hasVSX()) || Subtarget.hasP8Vector())))
12522 if (Subtarget.isPPC64()) {
12529 /// \brief Returns true if it is beneficial to convert a load of a constant
12530 /// to just the constant itself.
12531 bool PPCTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
12533 assert(Ty->isIntegerTy());
12535 unsigned BitSize = Ty->getPrimitiveSizeInBits();
12536 return !(BitSize == 0 || BitSize > 64);
12539 bool PPCTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
12540 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
12542 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
12543 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
12544 return NumBits1 == 64 && NumBits2 == 32;
12547 bool PPCTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
12548 if (!VT1.isInteger() || !VT2.isInteger())
12550 unsigned NumBits1 = VT1.getSizeInBits();
12551 unsigned NumBits2 = VT2.getSizeInBits();
12552 return NumBits1 == 64 && NumBits2 == 32;
12555 bool PPCTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
12556 // Generally speaking, zexts are not free, but they are free when they can be
12557 // folded with other operations.
12558 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Val)) {
12559 EVT MemVT = LD->getMemoryVT();
12560 if ((MemVT == MVT::i1 || MemVT == MVT::i8 || MemVT == MVT::i16 ||
12561 (Subtarget.isPPC64() && MemVT == MVT::i32)) &&
12562 (LD->getExtensionType() == ISD::NON_EXTLOAD ||
12563 LD->getExtensionType() == ISD::ZEXTLOAD))
12567 // FIXME: Add other cases...
12568 // - 32-bit shifts with a zext to i64
12569 // - zext after ctlz, bswap, etc.
12570 // - zext after and by a constant mask
12572 return TargetLowering::isZExtFree(Val, VT2);
12575 bool PPCTargetLowering::isFPExtFree(EVT VT) const {
12576 assert(VT.isFloatingPoint());
12580 bool PPCTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
12581 return isInt<16>(Imm) || isUInt<16>(Imm);
12584 bool PPCTargetLowering::isLegalAddImmediate(int64_t Imm) const {
12585 return isInt<16>(Imm) || isUInt<16>(Imm);
12588 bool PPCTargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
12591 bool *Fast) const {
12592 if (DisablePPCUnaligned)
12595 // PowerPC supports unaligned memory access for simple non-vector types.
12596 // Although accessing unaligned addresses is not as efficient as accessing
12597 // aligned addresses, it is generally more efficient than manual expansion,
12598 // and generally only traps for software emulation when crossing page
12601 if (!VT.isSimple())
12604 if (VT.getSimpleVT().isVector()) {
12605 if (Subtarget.hasVSX()) {
12606 if (VT != MVT::v2f64 && VT != MVT::v2i64 &&
12607 VT != MVT::v4f32 && VT != MVT::v4i32)
12614 if (VT == MVT::ppcf128)
12623 bool PPCTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
12624 VT = VT.getScalarType();
12626 if (!VT.isSimple())
12629 switch (VT.getSimpleVT().SimpleTy) {
12641 PPCTargetLowering::getScratchRegisters(CallingConv::ID) const {
12642 // LR is a callee-save register, but we must treat it as clobbered by any call
12643 // site. Hence we include LR in the scratch registers, which are in turn added
12644 // as implicit-defs for stackmaps and patchpoints. The same reasoning applies
12645 // to CTR, which is used by any indirect call.
12646 static const MCPhysReg ScratchRegs[] = {
12647 PPC::X12, PPC::LR8, PPC::CTR8, 0
12650 return ScratchRegs;
12653 unsigned PPCTargetLowering::getExceptionPointerRegister(
12654 const Constant *PersonalityFn) const {
12655 return Subtarget.isPPC64() ? PPC::X3 : PPC::R3;
12658 unsigned PPCTargetLowering::getExceptionSelectorRegister(
12659 const Constant *PersonalityFn) const {
12660 return Subtarget.isPPC64() ? PPC::X4 : PPC::R4;
12664 PPCTargetLowering::shouldExpandBuildVectorWithShuffles(
12665 EVT VT , unsigned DefinedValues) const {
12666 if (VT == MVT::v2i64)
12667 return Subtarget.hasDirectMove(); // Don't need stack ops with direct moves
12669 if (Subtarget.hasVSX() || Subtarget.hasQPX())
12672 return TargetLowering::shouldExpandBuildVectorWithShuffles(VT, DefinedValues);
12675 Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const {
12676 if (DisableILPPref || Subtarget.enableMachineScheduler())
12677 return TargetLowering::getSchedulingPreference(N);
12682 // Create a fast isel object.
12684 PPCTargetLowering::createFastISel(FunctionLoweringInfo &FuncInfo,
12685 const TargetLibraryInfo *LibInfo) const {
12686 return PPC::createFastISel(FuncInfo, LibInfo);
12689 void PPCTargetLowering::initializeSplitCSR(MachineBasicBlock *Entry) const {
12690 if (Subtarget.isDarwinABI()) return;
12691 if (!Subtarget.isPPC64()) return;
12693 // Update IsSplitCSR in PPCFunctionInfo
12694 PPCFunctionInfo *PFI = Entry->getParent()->getInfo<PPCFunctionInfo>();
12695 PFI->setIsSplitCSR(true);
12698 void PPCTargetLowering::insertCopiesSplitCSR(
12699 MachineBasicBlock *Entry,
12700 const SmallVectorImpl<MachineBasicBlock *> &Exits) const {
12701 const PPCRegisterInfo *TRI = Subtarget.getRegisterInfo();
12702 const MCPhysReg *IStart = TRI->getCalleeSavedRegsViaCopy(Entry->getParent());
12706 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
12707 MachineRegisterInfo *MRI = &Entry->getParent()->getRegInfo();
12708 MachineBasicBlock::iterator MBBI = Entry->begin();
12709 for (const MCPhysReg *I = IStart; *I; ++I) {
12710 const TargetRegisterClass *RC = nullptr;
12711 if (PPC::G8RCRegClass.contains(*I))
12712 RC = &PPC::G8RCRegClass;
12713 else if (PPC::F8RCRegClass.contains(*I))
12714 RC = &PPC::F8RCRegClass;
12715 else if (PPC::CRRCRegClass.contains(*I))
12716 RC = &PPC::CRRCRegClass;
12717 else if (PPC::VRRCRegClass.contains(*I))
12718 RC = &PPC::VRRCRegClass;
12720 llvm_unreachable("Unexpected register class in CSRsViaCopy!");
12722 unsigned NewVR = MRI->createVirtualRegister(RC);
12723 // Create copy from CSR to a virtual register.
12724 // FIXME: this currently does not emit CFI pseudo-instructions, it works
12725 // fine for CXX_FAST_TLS since the C++-style TLS access functions should be
12726 // nounwind. If we want to generalize this later, we may need to emit
12727 // CFI pseudo-instructions.
12728 assert(Entry->getParent()->getFunction()->hasFnAttribute(
12729 Attribute::NoUnwind) &&
12730 "Function should be nounwind in insertCopiesSplitCSR!");
12731 Entry->addLiveIn(*I);
12732 BuildMI(*Entry, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), NewVR)
12735 // Insert the copy-back instructions right before the terminator
12736 for (auto *Exit : Exits)
12737 BuildMI(*Exit, Exit->getFirstTerminator(), DebugLoc(),
12738 TII->get(TargetOpcode::COPY), *I)
12743 // Override to enable LOAD_STACK_GUARD lowering on Linux.
12744 bool PPCTargetLowering::useLoadStackGuardNode() const {
12745 if (!Subtarget.isTargetLinux())
12746 return TargetLowering::useLoadStackGuardNode();
12750 // Override to disable global variable loading on Linux.
12751 void PPCTargetLowering::insertSSPDeclarations(Module &M) const {
12752 if (!Subtarget.isTargetLinux())
12753 return TargetLowering::insertSSPDeclarations(M);
12756 bool PPCTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
12758 if (!VT.isSimple() || !Subtarget.hasVSX())
12761 switch(VT.getSimpleVT().SimpleTy) {
12763 // For FP types that are currently not supported by PPC backend, return
12764 // false. Examples: f16, f80.
12769 return Imm.isPosZero();