1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "MCTargetDesc/PPCPredicates.h"
16 #include "PPCMachineFunctionInfo.h"
17 #include "PPCPerfectShuffle.h"
18 #include "PPCTargetMachine.h"
19 #include "PPCTargetObjectFile.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/StringSwitch.h"
22 #include "llvm/ADT/Triple.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/SelectionDAG.h"
29 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
30 #include "llvm/IR/CallingConv.h"
31 #include "llvm/IR/Constants.h"
32 #include "llvm/IR/DerivedTypes.h"
33 #include "llvm/IR/Function.h"
34 #include "llvm/IR/Intrinsics.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/MathExtras.h"
38 #include "llvm/Support/raw_ostream.h"
39 #include "llvm/Target/TargetOptions.h"
42 static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
43 cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
45 static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
46 cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
48 static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
49 cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
51 // FIXME: Remove this once the bug has been fixed!
52 extern cl::opt<bool> ANDIGlueBug;
54 static TargetLoweringObjectFile *createTLOF(const Triple &TT) {
55 // If it isn't a Mach-O file then it's going to be a linux ELF
58 return new TargetLoweringObjectFileMachO();
60 return new PPC64LinuxTargetObjectFile();
63 PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
64 : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))),
65 Subtarget(*TM.getSubtargetImpl()) {
68 // Use _setjmp/_longjmp instead of setjmp/longjmp.
69 setUseUnderscoreSetJmp(true);
70 setUseUnderscoreLongJmp(true);
72 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
73 // arguments are at least 4/8 bytes aligned.
74 bool isPPC64 = Subtarget.isPPC64();
75 setMinStackArgumentAlignment(isPPC64 ? 8:4);
77 // Set up the register classes.
78 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
79 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
80 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
82 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
83 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
84 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
86 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
88 // PowerPC has pre-inc load and store's.
89 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
90 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
91 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
92 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
93 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
94 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
95 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
96 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
97 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
98 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
100 if (Subtarget.useCRBits()) {
101 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
103 if (isPPC64 || Subtarget.hasFPCVT()) {
104 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
105 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1,
106 isPPC64 ? MVT::i64 : MVT::i32);
107 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
108 AddPromotedToType (ISD::UINT_TO_FP, MVT::i1,
109 isPPC64 ? MVT::i64 : MVT::i32);
111 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom);
112 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Custom);
115 // PowerPC does not support direct load / store of condition registers
116 setOperationAction(ISD::LOAD, MVT::i1, Custom);
117 setOperationAction(ISD::STORE, MVT::i1, Custom);
119 // FIXME: Remove this once the ANDI glue bug is fixed:
121 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
123 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
124 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
125 setTruncStoreAction(MVT::i64, MVT::i1, Expand);
126 setTruncStoreAction(MVT::i32, MVT::i1, Expand);
127 setTruncStoreAction(MVT::i16, MVT::i1, Expand);
128 setTruncStoreAction(MVT::i8, MVT::i1, Expand);
130 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass);
133 // This is used in the ppcf128->int sequence. Note it has different semantics
134 // from FP_ROUND: that rounds to nearest, this rounds to zero.
135 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
137 // We do not currently implement these libm ops for PowerPC.
138 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
139 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
140 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
141 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
142 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
143 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
145 // PowerPC has no SREM/UREM instructions
146 setOperationAction(ISD::SREM, MVT::i32, Expand);
147 setOperationAction(ISD::UREM, MVT::i32, Expand);
148 setOperationAction(ISD::SREM, MVT::i64, Expand);
149 setOperationAction(ISD::UREM, MVT::i64, Expand);
151 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
152 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
153 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
154 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
155 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
156 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
157 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
158 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
159 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
161 // We don't support sin/cos/sqrt/fmod/pow
162 setOperationAction(ISD::FSIN , MVT::f64, Expand);
163 setOperationAction(ISD::FCOS , MVT::f64, Expand);
164 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
165 setOperationAction(ISD::FREM , MVT::f64, Expand);
166 setOperationAction(ISD::FPOW , MVT::f64, Expand);
167 setOperationAction(ISD::FMA , MVT::f64, Legal);
168 setOperationAction(ISD::FSIN , MVT::f32, Expand);
169 setOperationAction(ISD::FCOS , MVT::f32, Expand);
170 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
171 setOperationAction(ISD::FREM , MVT::f32, Expand);
172 setOperationAction(ISD::FPOW , MVT::f32, Expand);
173 setOperationAction(ISD::FMA , MVT::f32, Legal);
175 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
177 // If we're enabling GP optimizations, use hardware square root
178 if (!Subtarget.hasFSQRT() &&
179 !(TM.Options.UnsafeFPMath &&
180 Subtarget.hasFRSQRTE() && Subtarget.hasFRE()))
181 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
183 if (!Subtarget.hasFSQRT() &&
184 !(TM.Options.UnsafeFPMath &&
185 Subtarget.hasFRSQRTES() && Subtarget.hasFRES()))
186 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
188 if (Subtarget.hasFCPSGN()) {
189 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal);
190 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal);
192 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
193 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
196 if (Subtarget.hasFPRND()) {
197 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
198 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
199 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
200 setOperationAction(ISD::FROUND, MVT::f64, Legal);
202 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
203 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
204 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
205 setOperationAction(ISD::FROUND, MVT::f32, Legal);
208 // PowerPC does not have BSWAP, CTPOP or CTTZ
209 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
210 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
211 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
212 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
213 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
214 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
215 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
216 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
218 if (Subtarget.hasPOPCNTD()) {
219 setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
220 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
222 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
223 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
226 // PowerPC does not have ROTR
227 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
228 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
230 if (!Subtarget.useCRBits()) {
231 // PowerPC does not have Select
232 setOperationAction(ISD::SELECT, MVT::i32, Expand);
233 setOperationAction(ISD::SELECT, MVT::i64, Expand);
234 setOperationAction(ISD::SELECT, MVT::f32, Expand);
235 setOperationAction(ISD::SELECT, MVT::f64, Expand);
238 // PowerPC wants to turn select_cc of FP into fsel when possible.
239 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
240 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
242 // PowerPC wants to optimize integer setcc a bit
243 if (!Subtarget.useCRBits())
244 setOperationAction(ISD::SETCC, MVT::i32, Custom);
246 // PowerPC does not have BRCOND which requires SetCC
247 if (!Subtarget.useCRBits())
248 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
250 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
252 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
253 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
255 // PowerPC does not have [U|S]INT_TO_FP
256 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
257 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
259 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
260 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
261 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
262 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
264 // We cannot sextinreg(i1). Expand to shifts.
265 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
267 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
268 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
269 // support continuation, user-level threading, and etc.. As a result, no
270 // other SjLj exception interfaces are implemented and please don't build
271 // your own exception handling based on them.
272 // LLVM/Clang supports zero-cost DWARF exception handling.
273 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
274 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
276 // We want to legalize GlobalAddress and ConstantPool nodes into the
277 // appropriate instructions to materialize the address.
278 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
279 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
280 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
281 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
282 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
283 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
284 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
285 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
286 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
287 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
290 setOperationAction(ISD::TRAP, MVT::Other, Legal);
292 // TRAMPOLINE is custom lowered.
293 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
294 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
296 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
297 setOperationAction(ISD::VASTART , MVT::Other, Custom);
299 if (Subtarget.isSVR4ABI()) {
301 // VAARG always uses double-word chunks, so promote anything smaller.
302 setOperationAction(ISD::VAARG, MVT::i1, Promote);
303 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
304 setOperationAction(ISD::VAARG, MVT::i8, Promote);
305 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
306 setOperationAction(ISD::VAARG, MVT::i16, Promote);
307 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
308 setOperationAction(ISD::VAARG, MVT::i32, Promote);
309 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64);
310 setOperationAction(ISD::VAARG, MVT::Other, Expand);
312 // VAARG is custom lowered with the 32-bit SVR4 ABI.
313 setOperationAction(ISD::VAARG, MVT::Other, Custom);
314 setOperationAction(ISD::VAARG, MVT::i64, Custom);
317 setOperationAction(ISD::VAARG, MVT::Other, Expand);
319 if (Subtarget.isSVR4ABI() && !isPPC64)
320 // VACOPY is custom lowered with the 32-bit SVR4 ABI.
321 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
323 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
325 // Use the default implementation.
326 setOperationAction(ISD::VAEND , MVT::Other, Expand);
327 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
328 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
329 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
330 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
332 // We want to custom lower some of our intrinsics.
333 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
335 // To handle counter-based loop conditions.
336 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom);
338 // Comparisons that require checking two conditions.
339 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
340 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
341 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
342 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
343 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
344 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
345 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
346 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
347 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
348 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
349 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
350 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
352 if (Subtarget.has64BitSupport()) {
353 // They also have instructions for converting between i64 and fp.
354 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
355 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
356 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
357 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
358 // This is just the low 32 bits of a (signed) fp->i64 conversion.
359 // We cannot do this with Promote because i64 is not a legal type.
360 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
362 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64())
363 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
365 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
366 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
369 // With the instructions enabled under FPCVT, we can do everything.
370 if (Subtarget.hasFPCVT()) {
371 if (Subtarget.has64BitSupport()) {
372 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
373 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
374 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
375 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
378 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
379 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
380 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
381 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
384 if (Subtarget.use64BitRegs()) {
385 // 64-bit PowerPC implementations can support i64 types directly
386 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
387 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
388 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
389 // 64-bit PowerPC wants to expand i128 shifts itself.
390 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
391 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
392 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
394 // 32-bit PowerPC wants to expand i64 shifts itself.
395 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
396 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
397 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
400 if (Subtarget.hasAltivec()) {
401 // First set operation action for all vector types to expand. Then we
402 // will selectively turn on ones that can be effectively codegen'd.
403 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
404 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
405 MVT::SimpleValueType VT = (MVT::SimpleValueType)i;
407 // add/sub are legal for all supported vector VT's.
408 setOperationAction(ISD::ADD , VT, Legal);
409 setOperationAction(ISD::SUB , VT, Legal);
411 // We promote all shuffles to v16i8.
412 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
413 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
415 // We promote all non-typed operations to v4i32.
416 setOperationAction(ISD::AND , VT, Promote);
417 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
418 setOperationAction(ISD::OR , VT, Promote);
419 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
420 setOperationAction(ISD::XOR , VT, Promote);
421 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
422 setOperationAction(ISD::LOAD , VT, Promote);
423 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
424 setOperationAction(ISD::SELECT, VT, Promote);
425 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
426 setOperationAction(ISD::STORE, VT, Promote);
427 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
429 // No other operations are legal.
430 setOperationAction(ISD::MUL , VT, Expand);
431 setOperationAction(ISD::SDIV, VT, Expand);
432 setOperationAction(ISD::SREM, VT, Expand);
433 setOperationAction(ISD::UDIV, VT, Expand);
434 setOperationAction(ISD::UREM, VT, Expand);
435 setOperationAction(ISD::FDIV, VT, Expand);
436 setOperationAction(ISD::FREM, VT, Expand);
437 setOperationAction(ISD::FNEG, VT, Expand);
438 setOperationAction(ISD::FSQRT, VT, Expand);
439 setOperationAction(ISD::FLOG, VT, Expand);
440 setOperationAction(ISD::FLOG10, VT, Expand);
441 setOperationAction(ISD::FLOG2, VT, Expand);
442 setOperationAction(ISD::FEXP, VT, Expand);
443 setOperationAction(ISD::FEXP2, VT, Expand);
444 setOperationAction(ISD::FSIN, VT, Expand);
445 setOperationAction(ISD::FCOS, VT, Expand);
446 setOperationAction(ISD::FABS, VT, Expand);
447 setOperationAction(ISD::FPOWI, VT, Expand);
448 setOperationAction(ISD::FFLOOR, VT, Expand);
449 setOperationAction(ISD::FCEIL, VT, Expand);
450 setOperationAction(ISD::FTRUNC, VT, Expand);
451 setOperationAction(ISD::FRINT, VT, Expand);
452 setOperationAction(ISD::FNEARBYINT, VT, Expand);
453 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
454 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
455 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
456 setOperationAction(ISD::MULHU, VT, Expand);
457 setOperationAction(ISD::MULHS, VT, Expand);
458 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
459 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
460 setOperationAction(ISD::UDIVREM, VT, Expand);
461 setOperationAction(ISD::SDIVREM, VT, Expand);
462 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
463 setOperationAction(ISD::FPOW, VT, Expand);
464 setOperationAction(ISD::BSWAP, VT, Expand);
465 setOperationAction(ISD::CTPOP, VT, Expand);
466 setOperationAction(ISD::CTLZ, VT, Expand);
467 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
468 setOperationAction(ISD::CTTZ, VT, Expand);
469 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
470 setOperationAction(ISD::VSELECT, VT, Expand);
471 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
473 for (unsigned j = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
474 j <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++j) {
475 MVT::SimpleValueType InnerVT = (MVT::SimpleValueType)j;
476 setTruncStoreAction(VT, InnerVT, Expand);
478 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
479 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
480 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
483 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
484 // with merges, splats, etc.
485 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
487 setOperationAction(ISD::AND , MVT::v4i32, Legal);
488 setOperationAction(ISD::OR , MVT::v4i32, Legal);
489 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
490 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
491 setOperationAction(ISD::SELECT, MVT::v4i32,
492 Subtarget.useCRBits() ? Legal : Expand);
493 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
494 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
495 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
496 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
497 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
498 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
499 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
500 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
501 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
503 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
504 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
505 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
506 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
508 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
509 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
511 if (TM.Options.UnsafeFPMath || Subtarget.hasVSX()) {
512 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
513 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
516 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
517 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
518 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
520 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
521 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
523 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
524 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
525 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
526 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
528 // Altivec does not contain unordered floating-point compare instructions
529 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
530 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
531 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
532 setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
534 if (Subtarget.hasVSX()) {
535 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
536 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
538 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
539 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
540 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
541 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
542 setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
544 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
546 setOperationAction(ISD::MUL, MVT::v2f64, Legal);
547 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
549 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
550 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
552 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
553 setOperationAction(ISD::VSELECT, MVT::v8i16, Legal);
554 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
555 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
556 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
558 // Share the Altivec comparison restrictions.
559 setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand);
560 setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand);
561 setCondCodeAction(ISD::SETO, MVT::v2f64, Expand);
562 setCondCodeAction(ISD::SETONE, MVT::v2f64, Expand);
564 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
565 setOperationAction(ISD::STORE, MVT::v2f64, Legal);
567 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Legal);
569 addRegisterClass(MVT::f64, &PPC::VSFRCRegClass);
571 addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass);
572 addRegisterClass(MVT::v2f64, &PPC::VSRCRegClass);
574 // VSX v2i64 only supports non-arithmetic operations.
575 setOperationAction(ISD::ADD, MVT::v2i64, Expand);
576 setOperationAction(ISD::SUB, MVT::v2i64, Expand);
578 setOperationAction(ISD::SHL, MVT::v2i64, Expand);
579 setOperationAction(ISD::SRA, MVT::v2i64, Expand);
580 setOperationAction(ISD::SRL, MVT::v2i64, Expand);
582 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
584 setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
585 AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64);
586 setOperationAction(ISD::STORE, MVT::v2i64, Promote);
587 AddPromotedToType (ISD::STORE, MVT::v2i64, MVT::v2f64);
589 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Legal);
591 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
592 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
593 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
594 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
596 // Vector operation legalization checks the result type of
597 // SIGN_EXTEND_INREG, overall legalization checks the inner type.
598 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal);
599 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
600 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
601 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
603 addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
607 if (Subtarget.has64BitSupport()) {
608 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
609 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal);
612 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
613 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
614 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
615 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
617 setBooleanContents(ZeroOrOneBooleanContent);
618 // Altivec instructions set fields to all zeros or all ones.
619 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
622 // These libcalls are not available in 32-bit.
623 setLibcallName(RTLIB::SHL_I128, nullptr);
624 setLibcallName(RTLIB::SRL_I128, nullptr);
625 setLibcallName(RTLIB::SRA_I128, nullptr);
629 setStackPointerRegisterToSaveRestore(PPC::X1);
630 setExceptionPointerRegister(PPC::X3);
631 setExceptionSelectorRegister(PPC::X4);
633 setStackPointerRegisterToSaveRestore(PPC::R1);
634 setExceptionPointerRegister(PPC::R3);
635 setExceptionSelectorRegister(PPC::R4);
638 // We have target-specific dag combine patterns for the following nodes:
639 setTargetDAGCombine(ISD::SINT_TO_FP);
640 setTargetDAGCombine(ISD::LOAD);
641 setTargetDAGCombine(ISD::STORE);
642 setTargetDAGCombine(ISD::BR_CC);
643 if (Subtarget.useCRBits())
644 setTargetDAGCombine(ISD::BRCOND);
645 setTargetDAGCombine(ISD::BSWAP);
646 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
648 setTargetDAGCombine(ISD::SIGN_EXTEND);
649 setTargetDAGCombine(ISD::ZERO_EXTEND);
650 setTargetDAGCombine(ISD::ANY_EXTEND);
652 if (Subtarget.useCRBits()) {
653 setTargetDAGCombine(ISD::TRUNCATE);
654 setTargetDAGCombine(ISD::SETCC);
655 setTargetDAGCombine(ISD::SELECT_CC);
658 // Use reciprocal estimates.
659 if (TM.Options.UnsafeFPMath) {
660 setTargetDAGCombine(ISD::FDIV);
661 setTargetDAGCombine(ISD::FSQRT);
664 // Darwin long double math library functions have $LDBL128 appended.
665 if (Subtarget.isDarwin()) {
666 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
667 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
668 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
669 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
670 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
671 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
672 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
673 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
674 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
675 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
678 // With 32 condition bits, we don't need to sink (and duplicate) compares
679 // aggressively in CodeGenPrep.
680 if (Subtarget.useCRBits())
681 setHasMultipleConditionRegisters();
683 setMinFunctionAlignment(2);
684 if (Subtarget.isDarwin())
685 setPrefFunctionAlignment(4);
687 if (isPPC64 && Subtarget.isJITCodeModel())
688 // Temporary workaround for the inability of PPC64 JIT to handle jump
690 setSupportJumpTables(false);
692 setInsertFencesForAtomic(true);
694 if (Subtarget.enableMachineScheduler())
695 setSchedulingPreference(Sched::Source);
697 setSchedulingPreference(Sched::Hybrid);
699 computeRegisterProperties();
701 // The Freescale cores does better with aggressive inlining of memcpy and
702 // friends. Gcc uses same threshold of 128 bytes (= 32 word stores).
703 if (Subtarget.getDarwinDirective() == PPC::DIR_E500mc ||
704 Subtarget.getDarwinDirective() == PPC::DIR_E5500) {
705 MaxStoresPerMemset = 32;
706 MaxStoresPerMemsetOptSize = 16;
707 MaxStoresPerMemcpy = 32;
708 MaxStoresPerMemcpyOptSize = 8;
709 MaxStoresPerMemmove = 32;
710 MaxStoresPerMemmoveOptSize = 8;
712 setPrefFunctionAlignment(4);
716 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
717 /// the desired ByVal argument alignment.
718 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign,
719 unsigned MaxMaxAlign) {
720 if (MaxAlign == MaxMaxAlign)
722 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
723 if (MaxMaxAlign >= 32 && VTy->getBitWidth() >= 256)
725 else if (VTy->getBitWidth() >= 128 && MaxAlign < 16)
727 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
728 unsigned EltAlign = 0;
729 getMaxByValAlign(ATy->getElementType(), EltAlign, MaxMaxAlign);
730 if (EltAlign > MaxAlign)
732 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
733 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
734 unsigned EltAlign = 0;
735 getMaxByValAlign(STy->getElementType(i), EltAlign, MaxMaxAlign);
736 if (EltAlign > MaxAlign)
738 if (MaxAlign == MaxMaxAlign)
744 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
745 /// function arguments in the caller parameter area.
746 unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty) const {
747 // Darwin passes everything on 4 byte boundary.
748 if (Subtarget.isDarwin())
751 // 16byte and wider vectors are passed on 16byte boundary.
752 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
753 unsigned Align = Subtarget.isPPC64() ? 8 : 4;
754 if (Subtarget.hasAltivec() || Subtarget.hasQPX())
755 getMaxByValAlign(Ty, Align, Subtarget.hasQPX() ? 32 : 16);
759 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
761 default: return nullptr;
762 case PPCISD::FSEL: return "PPCISD::FSEL";
763 case PPCISD::FCFID: return "PPCISD::FCFID";
764 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
765 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
766 case PPCISD::FRE: return "PPCISD::FRE";
767 case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
768 case PPCISD::STFIWX: return "PPCISD::STFIWX";
769 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
770 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
771 case PPCISD::VPERM: return "PPCISD::VPERM";
772 case PPCISD::Hi: return "PPCISD::Hi";
773 case PPCISD::Lo: return "PPCISD::Lo";
774 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
775 case PPCISD::LOAD: return "PPCISD::LOAD";
776 case PPCISD::LOAD_TOC: return "PPCISD::LOAD_TOC";
777 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
778 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
779 case PPCISD::SRL: return "PPCISD::SRL";
780 case PPCISD::SRA: return "PPCISD::SRA";
781 case PPCISD::SHL: return "PPCISD::SHL";
782 case PPCISD::CALL: return "PPCISD::CALL";
783 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
784 case PPCISD::MTCTR: return "PPCISD::MTCTR";
785 case PPCISD::BCTRL: return "PPCISD::BCTRL";
786 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
787 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
788 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
789 case PPCISD::MFOCRF: return "PPCISD::MFOCRF";
790 case PPCISD::VCMP: return "PPCISD::VCMP";
791 case PPCISD::VCMPo: return "PPCISD::VCMPo";
792 case PPCISD::LBRX: return "PPCISD::LBRX";
793 case PPCISD::STBRX: return "PPCISD::STBRX";
794 case PPCISD::LARX: return "PPCISD::LARX";
795 case PPCISD::STCX: return "PPCISD::STCX";
796 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
797 case PPCISD::BDNZ: return "PPCISD::BDNZ";
798 case PPCISD::BDZ: return "PPCISD::BDZ";
799 case PPCISD::MFFS: return "PPCISD::MFFS";
800 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
801 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
802 case PPCISD::CR6SET: return "PPCISD::CR6SET";
803 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
804 case PPCISD::ADDIS_TOC_HA: return "PPCISD::ADDIS_TOC_HA";
805 case PPCISD::LD_TOC_L: return "PPCISD::LD_TOC_L";
806 case PPCISD::ADDI_TOC_L: return "PPCISD::ADDI_TOC_L";
807 case PPCISD::PPC32_GOT: return "PPCISD::PPC32_GOT";
808 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
809 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
810 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
811 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
812 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
813 case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR";
814 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
815 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
816 case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR";
817 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
818 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
819 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
820 case PPCISD::SC: return "PPCISD::SC";
824 EVT PPCTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
826 return Subtarget.useCRBits() ? MVT::i1 : MVT::i32;
827 return VT.changeVectorElementTypeToInteger();
830 //===----------------------------------------------------------------------===//
831 // Node matching predicates, for use by the tblgen matching code.
832 //===----------------------------------------------------------------------===//
834 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
835 static bool isFloatingPointZero(SDValue Op) {
836 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
837 return CFP->getValueAPF().isZero();
838 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
839 // Maybe this has already been legalized into the constant pool?
840 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
841 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
842 return CFP->getValueAPF().isZero();
847 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
848 /// true if Op is undef or if it matches the specified value.
849 static bool isConstantOrUndef(int Op, int Val) {
850 return Op < 0 || Op == Val;
853 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
854 /// VPKUHUM instruction.
855 /// The ShuffleKind distinguishes between big-endian operations with
856 /// two different inputs (0), either-endian operations with two identical
857 /// inputs (1), and little-endian operantion with two different inputs (2).
858 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
859 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
861 if (ShuffleKind == 0) {
862 if (DAG.getTarget().getDataLayout()->isLittleEndian())
864 for (unsigned i = 0; i != 16; ++i)
865 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
867 } else if (ShuffleKind == 2) {
868 if (!DAG.getTarget().getDataLayout()->isLittleEndian())
870 for (unsigned i = 0; i != 16; ++i)
871 if (!isConstantOrUndef(N->getMaskElt(i), i*2))
873 } else if (ShuffleKind == 1) {
874 unsigned j = DAG.getTarget().getDataLayout()->isLittleEndian() ? 0 : 1;
875 for (unsigned i = 0; i != 8; ++i)
876 if (!isConstantOrUndef(N->getMaskElt(i), i*2+j) ||
877 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j))
883 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
884 /// VPKUWUM instruction.
885 /// The ShuffleKind distinguishes between big-endian operations with
886 /// two different inputs (0), either-endian operations with two identical
887 /// inputs (1), and little-endian operantion with two different inputs (2).
888 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
889 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
891 if (ShuffleKind == 0) {
892 if (DAG.getTarget().getDataLayout()->isLittleEndian())
894 for (unsigned i = 0; i != 16; i += 2)
895 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
896 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
898 } else if (ShuffleKind == 2) {
899 if (!DAG.getTarget().getDataLayout()->isLittleEndian())
901 for (unsigned i = 0; i != 16; i += 2)
902 if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
903 !isConstantOrUndef(N->getMaskElt(i+1), i*2+1))
905 } else if (ShuffleKind == 1) {
906 unsigned j = DAG.getTarget().getDataLayout()->isLittleEndian() ? 0 : 2;
907 for (unsigned i = 0; i != 8; i += 2)
908 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
909 !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
910 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
911 !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1))
917 /// isVMerge - Common function, used to match vmrg* shuffles.
919 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
920 unsigned LHSStart, unsigned RHSStart) {
921 if (N->getValueType(0) != MVT::v16i8)
923 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
924 "Unsupported merge size!");
926 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
927 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
928 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
929 LHSStart+j+i*UnitSize) ||
930 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
931 RHSStart+j+i*UnitSize))
937 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
938 /// a VMRGL* instruction with the specified unit size (1,2 or 4 bytes).
939 /// The ShuffleKind distinguishes between big-endian merges with two
940 /// different inputs (0), either-endian merges with two identical inputs (1),
941 /// and little-endian merges with two different inputs (2). For the latter,
942 /// the input operands are swapped (see PPCInstrAltivec.td).
943 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
944 unsigned ShuffleKind, SelectionDAG &DAG) {
945 if (DAG.getTarget().getDataLayout()->isLittleEndian()) {
946 if (ShuffleKind == 1) // unary
947 return isVMerge(N, UnitSize, 0, 0);
948 else if (ShuffleKind == 2) // swapped
949 return isVMerge(N, UnitSize, 0, 16);
953 if (ShuffleKind == 1) // unary
954 return isVMerge(N, UnitSize, 8, 8);
955 else if (ShuffleKind == 0) // normal
956 return isVMerge(N, UnitSize, 8, 24);
962 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
963 /// a VMRGH* instruction with the specified unit size (1,2 or 4 bytes).
964 /// The ShuffleKind distinguishes between big-endian merges with two
965 /// different inputs (0), either-endian merges with two identical inputs (1),
966 /// and little-endian merges with two different inputs (2). For the latter,
967 /// the input operands are swapped (see PPCInstrAltivec.td).
968 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
969 unsigned ShuffleKind, SelectionDAG &DAG) {
970 if (DAG.getTarget().getDataLayout()->isLittleEndian()) {
971 if (ShuffleKind == 1) // unary
972 return isVMerge(N, UnitSize, 8, 8);
973 else if (ShuffleKind == 2) // swapped
974 return isVMerge(N, UnitSize, 8, 24);
978 if (ShuffleKind == 1) // unary
979 return isVMerge(N, UnitSize, 0, 0);
980 else if (ShuffleKind == 0) // normal
981 return isVMerge(N, UnitSize, 0, 16);
988 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
989 /// amount, otherwise return -1.
990 /// The ShuffleKind distinguishes between big-endian operations with two
991 /// different inputs (0), either-endian operations with two identical inputs
992 /// (1), and little-endian operations with two different inputs (2). For the
993 /// latter, the input operands are swapped (see PPCInstrAltivec.td).
994 int PPC::isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind,
996 if (N->getValueType(0) != MVT::v16i8)
999 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1001 // Find the first non-undef value in the shuffle mask.
1003 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
1006 if (i == 16) return -1; // all undef.
1008 // Otherwise, check to see if the rest of the elements are consecutively
1009 // numbered from this value.
1010 unsigned ShiftAmt = SVOp->getMaskElt(i);
1011 if (ShiftAmt < i) return -1;
1014 bool isLE = DAG.getTarget().getDataLayout()->isLittleEndian();
1016 if ((ShuffleKind == 0 && !isLE) || (ShuffleKind == 2 && isLE)) {
1017 // Check the rest of the elements to see if they are consecutive.
1018 for (++i; i != 16; ++i)
1019 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
1021 } else if (ShuffleKind == 1) {
1022 // Check the rest of the elements to see if they are consecutive.
1023 for (++i; i != 16; ++i)
1024 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
1029 if (ShuffleKind == 2 && isLE)
1030 ShiftAmt = 16 - ShiftAmt;
1035 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
1036 /// specifies a splat of a single element that is suitable for input to
1037 /// VSPLTB/VSPLTH/VSPLTW.
1038 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
1039 assert(N->getValueType(0) == MVT::v16i8 &&
1040 (EltSize == 1 || EltSize == 2 || EltSize == 4));
1042 // This is a splat operation if each element of the permute is the same, and
1043 // if the value doesn't reference the second vector.
1044 unsigned ElementBase = N->getMaskElt(0);
1046 // FIXME: Handle UNDEF elements too!
1047 if (ElementBase >= 16)
1050 // Check that the indices are consecutive, in the case of a multi-byte element
1051 // splatted with a v16i8 mask.
1052 for (unsigned i = 1; i != EltSize; ++i)
1053 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
1056 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
1057 if (N->getMaskElt(i) < 0) continue;
1058 for (unsigned j = 0; j != EltSize; ++j)
1059 if (N->getMaskElt(i+j) != N->getMaskElt(j))
1065 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
1067 bool PPC::isAllNegativeZeroVector(SDNode *N) {
1068 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
1070 APInt APVal, APUndef;
1074 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true))
1075 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
1076 return CFP->getValueAPF().isNegZero();
1081 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
1082 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
1083 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize,
1084 SelectionDAG &DAG) {
1085 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1086 assert(isSplatShuffleMask(SVOp, EltSize));
1087 if (DAG.getTarget().getDataLayout()->isLittleEndian())
1088 return (16 / EltSize) - 1 - (SVOp->getMaskElt(0) / EltSize);
1090 return SVOp->getMaskElt(0) / EltSize;
1093 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
1094 /// by using a vspltis[bhw] instruction of the specified element size, return
1095 /// the constant being splatted. The ByteSize field indicates the number of
1096 /// bytes of each element [124] -> [bhw].
1097 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
1098 SDValue OpVal(nullptr, 0);
1100 // If ByteSize of the splat is bigger than the element size of the
1101 // build_vector, then we have a case where we are checking for a splat where
1102 // multiple elements of the buildvector are folded together into a single
1103 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
1104 unsigned EltSize = 16/N->getNumOperands();
1105 if (EltSize < ByteSize) {
1106 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
1107 SDValue UniquedVals[4];
1108 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
1110 // See if all of the elements in the buildvector agree across.
1111 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1112 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1113 // If the element isn't a constant, bail fully out.
1114 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
1117 if (!UniquedVals[i&(Multiple-1)].getNode())
1118 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
1119 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
1120 return SDValue(); // no match.
1123 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
1124 // either constant or undef values that are identical for each chunk. See
1125 // if these chunks can form into a larger vspltis*.
1127 // Check to see if all of the leading entries are either 0 or -1. If
1128 // neither, then this won't fit into the immediate field.
1129 bool LeadingZero = true;
1130 bool LeadingOnes = true;
1131 for (unsigned i = 0; i != Multiple-1; ++i) {
1132 if (!UniquedVals[i].getNode()) continue; // Must have been undefs.
1134 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
1135 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
1137 // Finally, check the least significant entry.
1139 if (!UniquedVals[Multiple-1].getNode())
1140 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
1141 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
1143 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
1146 if (!UniquedVals[Multiple-1].getNode())
1147 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
1148 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
1149 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
1150 return DAG.getTargetConstant(Val, MVT::i32);
1156 // Check to see if this buildvec has a single non-undef value in its elements.
1157 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1158 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1159 if (!OpVal.getNode())
1160 OpVal = N->getOperand(i);
1161 else if (OpVal != N->getOperand(i))
1165 if (!OpVal.getNode()) return SDValue(); // All UNDEF: use implicit def.
1167 unsigned ValSizeInBytes = EltSize;
1169 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
1170 Value = CN->getZExtValue();
1171 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
1172 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
1173 Value = FloatToBits(CN->getValueAPF().convertToFloat());
1176 // If the splat value is larger than the element value, then we can never do
1177 // this splat. The only case that we could fit the replicated bits into our
1178 // immediate field for would be zero, and we prefer to use vxor for it.
1179 if (ValSizeInBytes < ByteSize) return SDValue();
1181 // If the element value is larger than the splat value, cut it in half and
1182 // check to see if the two halves are equal. Continue doing this until we
1183 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
1184 while (ValSizeInBytes > ByteSize) {
1185 ValSizeInBytes >>= 1;
1187 // If the top half equals the bottom half, we're still ok.
1188 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
1189 (Value & ((1 << (8*ValSizeInBytes))-1)))
1193 // Properly sign extend the value.
1194 int MaskVal = SignExtend32(Value, ByteSize * 8);
1196 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
1197 if (MaskVal == 0) return SDValue();
1199 // Finally, if this value fits in a 5 bit sext field, return it
1200 if (SignExtend32<5>(MaskVal) == MaskVal)
1201 return DAG.getTargetConstant(MaskVal, MVT::i32);
1205 //===----------------------------------------------------------------------===//
1206 // Addressing Mode Selection
1207 //===----------------------------------------------------------------------===//
1209 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
1210 /// or 64-bit immediate, and if the value can be accurately represented as a
1211 /// sign extension from a 16-bit value. If so, this returns true and the
1213 static bool isIntS16Immediate(SDNode *N, short &Imm) {
1214 if (!isa<ConstantSDNode>(N))
1217 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
1218 if (N->getValueType(0) == MVT::i32)
1219 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
1221 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
1223 static bool isIntS16Immediate(SDValue Op, short &Imm) {
1224 return isIntS16Immediate(Op.getNode(), Imm);
1228 /// SelectAddressRegReg - Given the specified addressed, check to see if it
1229 /// can be represented as an indexed [r+r] operation. Returns false if it
1230 /// can be more efficiently represented with [r+imm].
1231 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
1233 SelectionDAG &DAG) const {
1235 if (N.getOpcode() == ISD::ADD) {
1236 if (isIntS16Immediate(N.getOperand(1), imm))
1237 return false; // r+i
1238 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
1239 return false; // r+i
1241 Base = N.getOperand(0);
1242 Index = N.getOperand(1);
1244 } else if (N.getOpcode() == ISD::OR) {
1245 if (isIntS16Immediate(N.getOperand(1), imm))
1246 return false; // r+i can fold it if we can.
1248 // If this is an or of disjoint bitfields, we can codegen this as an add
1249 // (for better address arithmetic) if the LHS and RHS of the OR are provably
1251 APInt LHSKnownZero, LHSKnownOne;
1252 APInt RHSKnownZero, RHSKnownOne;
1253 DAG.computeKnownBits(N.getOperand(0),
1254 LHSKnownZero, LHSKnownOne);
1256 if (LHSKnownZero.getBoolValue()) {
1257 DAG.computeKnownBits(N.getOperand(1),
1258 RHSKnownZero, RHSKnownOne);
1259 // If all of the bits are known zero on the LHS or RHS, the add won't
1261 if (~(LHSKnownZero | RHSKnownZero) == 0) {
1262 Base = N.getOperand(0);
1263 Index = N.getOperand(1);
1272 // If we happen to be doing an i64 load or store into a stack slot that has
1273 // less than a 4-byte alignment, then the frame-index elimination may need to
1274 // use an indexed load or store instruction (because the offset may not be a
1275 // multiple of 4). The extra register needed to hold the offset comes from the
1276 // register scavenger, and it is possible that the scavenger will need to use
1277 // an emergency spill slot. As a result, we need to make sure that a spill slot
1278 // is allocated when doing an i64 load/store into a less-than-4-byte-aligned
1280 static void fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT) {
1281 // FIXME: This does not handle the LWA case.
1285 // NOTE: We'll exclude negative FIs here, which come from argument
1286 // lowering, because there are no known test cases triggering this problem
1287 // using packed structures (or similar). We can remove this exclusion if
1288 // we find such a test case. The reason why this is so test-case driven is
1289 // because this entire 'fixup' is only to prevent crashes (from the
1290 // register scavenger) on not-really-valid inputs. For example, if we have:
1292 // %b = bitcast i1* %a to i64*
1293 // store i64* a, i64 b
1294 // then the store should really be marked as 'align 1', but is not. If it
1295 // were marked as 'align 1' then the indexed form would have been
1296 // instruction-selected initially, and the problem this 'fixup' is preventing
1297 // won't happen regardless.
1301 MachineFunction &MF = DAG.getMachineFunction();
1302 MachineFrameInfo *MFI = MF.getFrameInfo();
1304 unsigned Align = MFI->getObjectAlignment(FrameIdx);
1308 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1309 FuncInfo->setHasNonRISpills();
1312 /// Returns true if the address N can be represented by a base register plus
1313 /// a signed 16-bit displacement [r+imm], and if it is not better
1314 /// represented as reg+reg. If Aligned is true, only accept displacements
1315 /// suitable for STD and friends, i.e. multiples of 4.
1316 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
1319 bool Aligned) const {
1320 // FIXME dl should come from parent load or store, not from address
1322 // If this can be more profitably realized as r+r, fail.
1323 if (SelectAddressRegReg(N, Disp, Base, DAG))
1326 if (N.getOpcode() == ISD::ADD) {
1328 if (isIntS16Immediate(N.getOperand(1), imm) &&
1329 (!Aligned || (imm & 3) == 0)) {
1330 Disp = DAG.getTargetConstant(imm, N.getValueType());
1331 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1332 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1333 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1335 Base = N.getOperand(0);
1337 return true; // [r+i]
1338 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
1339 // Match LOAD (ADD (X, Lo(G))).
1340 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
1341 && "Cannot handle constant offsets yet!");
1342 Disp = N.getOperand(1).getOperand(0); // The global address.
1343 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
1344 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||
1345 Disp.getOpcode() == ISD::TargetConstantPool ||
1346 Disp.getOpcode() == ISD::TargetJumpTable);
1347 Base = N.getOperand(0);
1348 return true; // [&g+r]
1350 } else if (N.getOpcode() == ISD::OR) {
1352 if (isIntS16Immediate(N.getOperand(1), imm) &&
1353 (!Aligned || (imm & 3) == 0)) {
1354 // If this is an or of disjoint bitfields, we can codegen this as an add
1355 // (for better address arithmetic) if the LHS and RHS of the OR are
1356 // provably disjoint.
1357 APInt LHSKnownZero, LHSKnownOne;
1358 DAG.computeKnownBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
1360 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1361 // If all of the bits are known zero on the LHS or RHS, the add won't
1363 if (FrameIndexSDNode *FI =
1364 dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1365 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1366 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1368 Base = N.getOperand(0);
1370 Disp = DAG.getTargetConstant(imm, N.getValueType());
1374 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1375 // Loading from a constant address.
1377 // If this address fits entirely in a 16-bit sext immediate field, codegen
1380 if (isIntS16Immediate(CN, Imm) && (!Aligned || (Imm & 3) == 0)) {
1381 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
1382 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1383 CN->getValueType(0));
1387 // Handle 32-bit sext immediates with LIS + addr mode.
1388 if ((CN->getValueType(0) == MVT::i32 ||
1389 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) &&
1390 (!Aligned || (CN->getZExtValue() & 3) == 0)) {
1391 int Addr = (int)CN->getZExtValue();
1393 // Otherwise, break this down into an LIS + disp.
1394 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
1396 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
1397 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1398 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
1403 Disp = DAG.getTargetConstant(0, getPointerTy());
1404 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
1405 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1406 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1409 return true; // [r+0]
1412 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
1413 /// represented as an indexed [r+r] operation.
1414 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
1416 SelectionDAG &DAG) const {
1417 // Check to see if we can easily represent this as an [r+r] address. This
1418 // will fail if it thinks that the address is more profitably represented as
1419 // reg+imm, e.g. where imm = 0.
1420 if (SelectAddressRegReg(N, Base, Index, DAG))
1423 // If the operand is an addition, always emit this as [r+r], since this is
1424 // better (for code size, and execution, as the memop does the add for free)
1425 // than emitting an explicit add.
1426 if (N.getOpcode() == ISD::ADD) {
1427 Base = N.getOperand(0);
1428 Index = N.getOperand(1);
1432 // Otherwise, do it the hard way, using R0 as the base register.
1433 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1439 /// getPreIndexedAddressParts - returns true by value, base pointer and
1440 /// offset pointer and addressing mode by reference if the node's address
1441 /// can be legally represented as pre-indexed load / store address.
1442 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1444 ISD::MemIndexedMode &AM,
1445 SelectionDAG &DAG) const {
1446 if (DisablePPCPreinc) return false;
1452 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1453 Ptr = LD->getBasePtr();
1454 VT = LD->getMemoryVT();
1455 Alignment = LD->getAlignment();
1456 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1457 Ptr = ST->getBasePtr();
1458 VT = ST->getMemoryVT();
1459 Alignment = ST->getAlignment();
1464 // PowerPC doesn't have preinc load/store instructions for vectors.
1468 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
1470 // Common code will reject creating a pre-inc form if the base pointer
1471 // is a frame index, or if N is a store and the base pointer is either
1472 // the same as or a predecessor of the value being stored. Check for
1473 // those situations here, and try with swapped Base/Offset instead.
1476 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
1479 SDValue Val = cast<StoreSDNode>(N)->getValue();
1480 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
1485 std::swap(Base, Offset);
1491 // LDU/STU can only handle immediates that are a multiple of 4.
1492 if (VT != MVT::i64) {
1493 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, false))
1496 // LDU/STU need an address with at least 4-byte alignment.
1500 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, true))
1504 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1505 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1506 // sext i32 to i64 when addr mode is r+i.
1507 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1508 LD->getExtensionType() == ISD::SEXTLOAD &&
1509 isa<ConstantSDNode>(Offset))
1517 //===----------------------------------------------------------------------===//
1518 // LowerOperation implementation
1519 //===----------------------------------------------------------------------===//
1521 /// GetLabelAccessInfo - Return true if we should reference labels using a
1522 /// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.
1523 static bool GetLabelAccessInfo(const TargetMachine &TM, unsigned &HiOpFlags,
1524 unsigned &LoOpFlags,
1525 const GlobalValue *GV = nullptr) {
1526 HiOpFlags = PPCII::MO_HA;
1527 LoOpFlags = PPCII::MO_LO;
1529 // Don't use the pic base if not in PIC relocation model.
1530 bool isPIC = TM.getRelocationModel() == Reloc::PIC_;
1533 HiOpFlags |= PPCII::MO_PIC_FLAG;
1534 LoOpFlags |= PPCII::MO_PIC_FLAG;
1537 // If this is a reference to a global value that requires a non-lazy-ptr, make
1538 // sure that instruction lowering adds it.
1539 if (GV && TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV, TM)) {
1540 HiOpFlags |= PPCII::MO_NLP_FLAG;
1541 LoOpFlags |= PPCII::MO_NLP_FLAG;
1543 if (GV->hasHiddenVisibility()) {
1544 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1545 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1552 static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
1553 SelectionDAG &DAG) {
1554 EVT PtrVT = HiPart.getValueType();
1555 SDValue Zero = DAG.getConstant(0, PtrVT);
1558 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
1559 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
1561 // With PIC, the first instruction is actually "GR+hi(&G)".
1563 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1564 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
1566 // Generate non-pic code that has direct accesses to the constant pool.
1567 // The address of the global is just (hi(&g)+lo(&g)).
1568 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1571 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
1572 SelectionDAG &DAG) const {
1573 EVT PtrVT = Op.getValueType();
1574 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1575 const Constant *C = CP->getConstVal();
1577 // 64-bit SVR4 ABI code is always position-independent.
1578 // The actual address of the GlobalValue is stored in the TOC.
1579 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1580 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0);
1581 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(CP), MVT::i64, GA,
1582 DAG.getRegister(PPC::X2, MVT::i64));
1585 unsigned MOHiFlag, MOLoFlag;
1586 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1588 if (isPIC && Subtarget.isSVR4ABI()) {
1589 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(),
1590 PPCII::MO_PIC_FLAG);
1592 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i32, GA,
1593 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT));
1597 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
1599 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
1600 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG);
1603 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
1604 EVT PtrVT = Op.getValueType();
1605 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1607 // 64-bit SVR4 ABI code is always position-independent.
1608 // The actual address of the GlobalValue is stored in the TOC.
1609 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1610 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1611 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(JT), MVT::i64, GA,
1612 DAG.getRegister(PPC::X2, MVT::i64));
1615 unsigned MOHiFlag, MOLoFlag;
1616 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1618 if (isPIC && Subtarget.isSVR4ABI()) {
1619 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
1620 PPCII::MO_PIC_FLAG);
1622 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(JT), PtrVT, GA,
1623 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT));
1626 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
1627 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
1628 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG);
1631 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
1632 SelectionDAG &DAG) const {
1633 EVT PtrVT = Op.getValueType();
1635 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1637 unsigned MOHiFlag, MOLoFlag;
1638 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1639 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
1640 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
1641 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG);
1644 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1645 SelectionDAG &DAG) const {
1647 // FIXME: TLS addresses currently use medium model code sequences,
1648 // which is the most useful form. Eventually support for small and
1649 // large models could be added if users need it, at the cost of
1650 // additional complexity.
1651 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1653 const GlobalValue *GV = GA->getGlobal();
1654 EVT PtrVT = getPointerTy();
1655 bool is64bit = Subtarget.isPPC64();
1657 TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
1659 if (Model == TLSModel::LocalExec) {
1660 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1661 PPCII::MO_TPREL_HA);
1662 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1663 PPCII::MO_TPREL_LO);
1664 SDValue TLSReg = DAG.getRegister(is64bit ? PPC::X13 : PPC::R2,
1665 is64bit ? MVT::i64 : MVT::i32);
1666 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
1667 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
1670 if (Model == TLSModel::InitialExec) {
1671 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1672 SDValue TGATLS = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1676 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1677 GOTPtr = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl,
1678 PtrVT, GOTReg, TGA);
1680 GOTPtr = DAG.getNode(PPCISD::PPC32_GOT, dl, PtrVT);
1681 SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl,
1682 PtrVT, TGA, GOTPtr);
1683 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGATLS);
1686 if (Model == TLSModel::GeneralDynamic) {
1687 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1690 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1691 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
1694 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
1696 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSGD_L, dl, PtrVT,
1699 // We need a chain node, and don't have one handy. The underlying
1700 // call has no side effects, so using the function entry node
1702 SDValue Chain = DAG.getEntryNode();
1703 Chain = DAG.getCopyToReg(Chain, dl,
1704 is64bit ? PPC::X3 : PPC::R3, GOTEntry);
1705 SDValue ParmReg = DAG.getRegister(is64bit ? PPC::X3 : PPC::R3,
1706 is64bit ? MVT::i64 : MVT::i32);
1707 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLS_ADDR, dl,
1708 PtrVT, ParmReg, TGA);
1709 // The return value from GET_TLS_ADDR really is in X3 already, but
1710 // some hacks are needed here to tie everything together. The extra
1711 // copies dissolve during subsequent transforms.
1712 Chain = DAG.getCopyToReg(Chain, dl, is64bit ? PPC::X3 : PPC::R3, TLSAddr);
1713 return DAG.getCopyFromReg(Chain, dl, is64bit ? PPC::X3 : PPC::R3, PtrVT);
1716 if (Model == TLSModel::LocalDynamic) {
1717 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1720 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1721 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
1724 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
1726 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSLD_L, dl, PtrVT,
1729 // We need a chain node, and don't have one handy. The underlying
1730 // call has no side effects, so using the function entry node
1732 SDValue Chain = DAG.getEntryNode();
1733 Chain = DAG.getCopyToReg(Chain, dl,
1734 is64bit ? PPC::X3 : PPC::R3, GOTEntry);
1735 SDValue ParmReg = DAG.getRegister(is64bit ? PPC::X3 : PPC::R3,
1736 is64bit ? MVT::i64 : MVT::i32);
1737 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLSLD_ADDR, dl,
1738 PtrVT, ParmReg, TGA);
1739 // The return value from GET_TLSLD_ADDR really is in X3 already, but
1740 // some hacks are needed here to tie everything together. The extra
1741 // copies dissolve during subsequent transforms.
1742 Chain = DAG.getCopyToReg(Chain, dl, is64bit ? PPC::X3 : PPC::R3, TLSAddr);
1743 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl, PtrVT,
1744 Chain, ParmReg, TGA);
1745 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
1748 llvm_unreachable("Unknown TLS model!");
1751 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
1752 SelectionDAG &DAG) const {
1753 EVT PtrVT = Op.getValueType();
1754 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1756 const GlobalValue *GV = GSDN->getGlobal();
1758 // 64-bit SVR4 ABI code is always position-independent.
1759 // The actual address of the GlobalValue is stored in the TOC.
1760 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1761 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
1762 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i64, GA,
1763 DAG.getRegister(PPC::X2, MVT::i64));
1766 unsigned MOHiFlag, MOLoFlag;
1767 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag, GV);
1769 if (isPIC && Subtarget.isSVR4ABI()) {
1770 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT,
1772 PPCII::MO_PIC_FLAG);
1773 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i32, GA,
1774 DAG.getNode(PPCISD::GlobalBaseReg, DL, MVT::i32));
1778 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
1780 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
1782 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG);
1784 // If the global reference is actually to a non-lazy-pointer, we have to do an
1785 // extra load to get the address of the global.
1786 if (MOHiFlag & PPCII::MO_NLP_FLAG)
1787 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(),
1788 false, false, false, 0);
1792 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1793 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1796 if (Op.getValueType() == MVT::v2i64) {
1797 // When the operands themselves are v2i64 values, we need to do something
1798 // special because VSX has no underlying comparison operations for these.
1799 if (Op.getOperand(0).getValueType() == MVT::v2i64) {
1800 // Equality can be handled by casting to the legal type for Altivec
1801 // comparisons, everything else needs to be expanded.
1802 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
1803 return DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
1804 DAG.getSetCC(dl, MVT::v4i32,
1805 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0)),
1806 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(1)),
1813 // We handle most of these in the usual way.
1817 // If we're comparing for equality to zero, expose the fact that this is
1818 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1819 // fold the new nodes.
1820 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1821 if (C->isNullValue() && CC == ISD::SETEQ) {
1822 EVT VT = Op.getOperand(0).getValueType();
1823 SDValue Zext = Op.getOperand(0);
1824 if (VT.bitsLT(MVT::i32)) {
1826 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
1828 unsigned Log2b = Log2_32(VT.getSizeInBits());
1829 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
1830 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
1831 DAG.getConstant(Log2b, MVT::i32));
1832 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
1834 // Leave comparisons against 0 and -1 alone for now, since they're usually
1835 // optimized. FIXME: revisit this when we can custom lower all setcc
1837 if (C->isAllOnesValue() || C->isNullValue())
1841 // If we have an integer seteq/setne, turn it into a compare against zero
1842 // by xor'ing the rhs with the lhs, which is faster than setting a
1843 // condition register, reading it back out, and masking the correct bit. The
1844 // normal approach here uses sub to do this instead of xor. Using xor exposes
1845 // the result to other bit-twiddling opportunities.
1846 EVT LHSVT = Op.getOperand(0).getValueType();
1847 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1848 EVT VT = Op.getValueType();
1849 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
1851 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC);
1856 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
1857 const PPCSubtarget &Subtarget) const {
1858 SDNode *Node = Op.getNode();
1859 EVT VT = Node->getValueType(0);
1860 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1861 SDValue InChain = Node->getOperand(0);
1862 SDValue VAListPtr = Node->getOperand(1);
1863 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
1866 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only");
1869 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1870 VAListPtr, MachinePointerInfo(SV), MVT::i8,
1872 InChain = GprIndex.getValue(1);
1874 if (VT == MVT::i64) {
1875 // Check if GprIndex is even
1876 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
1877 DAG.getConstant(1, MVT::i32));
1878 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
1879 DAG.getConstant(0, MVT::i32), ISD::SETNE);
1880 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
1881 DAG.getConstant(1, MVT::i32));
1882 // Align GprIndex to be even if it isn't
1883 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
1887 // fpr index is 1 byte after gpr
1888 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1889 DAG.getConstant(1, MVT::i32));
1892 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1893 FprPtr, MachinePointerInfo(SV), MVT::i8,
1895 InChain = FprIndex.getValue(1);
1897 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1898 DAG.getConstant(8, MVT::i32));
1900 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1901 DAG.getConstant(4, MVT::i32));
1904 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr,
1905 MachinePointerInfo(), false, false,
1907 InChain = OverflowArea.getValue(1);
1909 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr,
1910 MachinePointerInfo(), false, false,
1912 InChain = RegSaveArea.getValue(1);
1914 // select overflow_area if index > 8
1915 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
1916 DAG.getConstant(8, MVT::i32), ISD::SETLT);
1918 // adjustment constant gpr_index * 4/8
1919 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
1920 VT.isInteger() ? GprIndex : FprIndex,
1921 DAG.getConstant(VT.isInteger() ? 4 : 8,
1924 // OurReg = RegSaveArea + RegConstant
1925 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
1928 // Floating types are 32 bytes into RegSaveArea
1929 if (VT.isFloatingPoint())
1930 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
1931 DAG.getConstant(32, MVT::i32));
1933 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
1934 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
1935 VT.isInteger() ? GprIndex : FprIndex,
1936 DAG.getConstant(VT == MVT::i64 ? 2 : 1,
1939 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
1940 VT.isInteger() ? VAListPtr : FprPtr,
1941 MachinePointerInfo(SV),
1942 MVT::i8, false, false, 0);
1944 // determine if we should load from reg_save_area or overflow_area
1945 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
1947 // increase overflow_area by 4/8 if gpr/fpr > 8
1948 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
1949 DAG.getConstant(VT.isInteger() ? 4 : 8,
1952 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
1955 InChain = DAG.getTruncStore(InChain, dl, OverflowArea,
1957 MachinePointerInfo(),
1958 MVT::i32, false, false, 0);
1960 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(),
1961 false, false, false, 0);
1964 SDValue PPCTargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG,
1965 const PPCSubtarget &Subtarget) const {
1966 assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only");
1968 // We have to copy the entire va_list struct:
1969 // 2*sizeof(char) + 2 Byte alignment + 2*sizeof(char*) = 12 Byte
1970 return DAG.getMemcpy(Op.getOperand(0), Op,
1971 Op.getOperand(1), Op.getOperand(2),
1972 DAG.getConstant(12, MVT::i32), 8, false, true,
1973 MachinePointerInfo(), MachinePointerInfo());
1976 SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
1977 SelectionDAG &DAG) const {
1978 return Op.getOperand(0);
1981 SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
1982 SelectionDAG &DAG) const {
1983 SDValue Chain = Op.getOperand(0);
1984 SDValue Trmp = Op.getOperand(1); // trampoline
1985 SDValue FPtr = Op.getOperand(2); // nested function
1986 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
1989 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1990 bool isPPC64 = (PtrVT == MVT::i64);
1992 DAG.getTargetLoweringInfo().getDataLayout()->getIntPtrType(
1995 TargetLowering::ArgListTy Args;
1996 TargetLowering::ArgListEntry Entry;
1998 Entry.Ty = IntPtrTy;
1999 Entry.Node = Trmp; Args.push_back(Entry);
2001 // TrampSize == (isPPC64 ? 48 : 40);
2002 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40,
2003 isPPC64 ? MVT::i64 : MVT::i32);
2004 Args.push_back(Entry);
2006 Entry.Node = FPtr; Args.push_back(Entry);
2007 Entry.Node = Nest; Args.push_back(Entry);
2009 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
2010 TargetLowering::CallLoweringInfo CLI(DAG);
2011 CLI.setDebugLoc(dl).setChain(Chain)
2012 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
2013 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
2014 std::move(Args), 0);
2016 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2017 return CallResult.second;
2020 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
2021 const PPCSubtarget &Subtarget) const {
2022 MachineFunction &MF = DAG.getMachineFunction();
2023 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2027 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
2028 // vastart just stores the address of the VarArgsFrameIndex slot into the
2029 // memory location argument.
2030 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2031 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2032 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2033 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
2034 MachinePointerInfo(SV),
2038 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
2039 // We suppose the given va_list is already allocated.
2042 // char gpr; /* index into the array of 8 GPRs
2043 // * stored in the register save area
2044 // * gpr=0 corresponds to r3,
2045 // * gpr=1 to r4, etc.
2047 // char fpr; /* index into the array of 8 FPRs
2048 // * stored in the register save area
2049 // * fpr=0 corresponds to f1,
2050 // * fpr=1 to f2, etc.
2052 // char *overflow_arg_area;
2053 // /* location on stack that holds
2054 // * the next overflow argument
2056 // char *reg_save_area;
2057 // /* where r3:r10 and f1:f8 (if saved)
2063 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32);
2064 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32);
2067 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2069 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
2071 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
2074 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
2075 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
2077 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
2078 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
2080 uint64_t FPROffset = 1;
2081 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
2083 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2085 // Store first byte : number of int regs
2086 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
2088 MachinePointerInfo(SV),
2089 MVT::i8, false, false, 0);
2090 uint64_t nextOffset = FPROffset;
2091 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
2094 // Store second byte : number of float regs
2095 SDValue secondStore =
2096 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
2097 MachinePointerInfo(SV, nextOffset), MVT::i8,
2099 nextOffset += StackOffset;
2100 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
2102 // Store second word : arguments given on stack
2103 SDValue thirdStore =
2104 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
2105 MachinePointerInfo(SV, nextOffset),
2107 nextOffset += FrameOffset;
2108 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
2110 // Store third word : arguments given in registers
2111 return DAG.getStore(thirdStore, dl, FR, nextPtr,
2112 MachinePointerInfo(SV, nextOffset),
2117 #include "PPCGenCallingConv.inc"
2119 // Function whose sole purpose is to kill compiler warnings
2120 // stemming from unused functions included from PPCGenCallingConv.inc.
2121 CCAssignFn *PPCTargetLowering::useFastISelCCs(unsigned Flag) const {
2122 return Flag ? CC_PPC64_ELF_FIS : RetCC_PPC64_ELF_FIS;
2125 bool llvm::CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
2126 CCValAssign::LocInfo &LocInfo,
2127 ISD::ArgFlagsTy &ArgFlags,
2132 bool llvm::CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
2134 CCValAssign::LocInfo &LocInfo,
2135 ISD::ArgFlagsTy &ArgFlags,
2137 static const MCPhysReg ArgRegs[] = {
2138 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2139 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2141 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2143 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
2145 // Skip one register if the first unallocated register has an even register
2146 // number and there are still argument registers available which have not been
2147 // allocated yet. RegNum is actually an index into ArgRegs, which means we
2148 // need to skip a register if RegNum is odd.
2149 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
2150 State.AllocateReg(ArgRegs[RegNum]);
2153 // Always return false here, as this function only makes sure that the first
2154 // unallocated register has an odd register number and does not actually
2155 // allocate a register for the current argument.
2159 bool llvm::CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
2161 CCValAssign::LocInfo &LocInfo,
2162 ISD::ArgFlagsTy &ArgFlags,
2164 static const MCPhysReg ArgRegs[] = {
2165 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2169 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2171 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
2173 // If there is only one Floating-point register left we need to put both f64
2174 // values of a split ppc_fp128 value on the stack.
2175 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
2176 State.AllocateReg(ArgRegs[RegNum]);
2179 // Always return false here, as this function only makes sure that the two f64
2180 // values a ppc_fp128 value is split into are both passed in registers or both
2181 // passed on the stack and does not actually allocate a register for the
2182 // current argument.
2186 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
2188 static const MCPhysReg *GetFPR() {
2189 static const MCPhysReg FPR[] = {
2190 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2191 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
2197 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
2199 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
2200 unsigned PtrByteSize) {
2201 unsigned ArgSize = ArgVT.getStoreSize();
2202 if (Flags.isByVal())
2203 ArgSize = Flags.getByValSize();
2205 // Round up to multiples of the pointer size, except for array members,
2206 // which are always packed.
2207 if (!Flags.isInConsecutiveRegs())
2208 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2213 /// CalculateStackSlotAlignment - Calculates the alignment of this argument
2215 static unsigned CalculateStackSlotAlignment(EVT ArgVT, EVT OrigVT,
2216 ISD::ArgFlagsTy Flags,
2217 unsigned PtrByteSize) {
2218 unsigned Align = PtrByteSize;
2220 // Altivec parameters are padded to a 16 byte boundary.
2221 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2222 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
2223 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64)
2226 // ByVal parameters are aligned as requested.
2227 if (Flags.isByVal()) {
2228 unsigned BVAlign = Flags.getByValAlign();
2229 if (BVAlign > PtrByteSize) {
2230 if (BVAlign % PtrByteSize != 0)
2232 "ByVal alignment is not a multiple of the pointer size");
2238 // Array members are always packed to their original alignment.
2239 if (Flags.isInConsecutiveRegs()) {
2240 // If the array member was split into multiple registers, the first
2241 // needs to be aligned to the size of the full type. (Except for
2242 // ppcf128, which is only aligned as its f64 components.)
2243 if (Flags.isSplit() && OrigVT != MVT::ppcf128)
2244 Align = OrigVT.getStoreSize();
2246 Align = ArgVT.getStoreSize();
2252 /// CalculateStackSlotUsed - Return whether this argument will use its
2253 /// stack slot (instead of being passed in registers). ArgOffset,
2254 /// AvailableFPRs, and AvailableVRs must hold the current argument
2255 /// position, and will be updated to account for this argument.
2256 static bool CalculateStackSlotUsed(EVT ArgVT, EVT OrigVT,
2257 ISD::ArgFlagsTy Flags,
2258 unsigned PtrByteSize,
2259 unsigned LinkageSize,
2260 unsigned ParamAreaSize,
2261 unsigned &ArgOffset,
2262 unsigned &AvailableFPRs,
2263 unsigned &AvailableVRs) {
2264 bool UseMemory = false;
2266 // Respect alignment of argument on the stack.
2268 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
2269 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
2270 // If there's no space left in the argument save area, we must
2271 // use memory (this check also catches zero-sized arguments).
2272 if (ArgOffset >= LinkageSize + ParamAreaSize)
2275 // Allocate argument on the stack.
2276 ArgOffset += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
2277 if (Flags.isInConsecutiveRegsLast())
2278 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2279 // If we overran the argument save area, we must use memory
2280 // (this check catches arguments passed partially in memory)
2281 if (ArgOffset > LinkageSize + ParamAreaSize)
2284 // However, if the argument is actually passed in an FPR or a VR,
2285 // we don't use memory after all.
2286 if (!Flags.isByVal()) {
2287 if (ArgVT == MVT::f32 || ArgVT == MVT::f64)
2288 if (AvailableFPRs > 0) {
2292 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2293 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
2294 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64)
2295 if (AvailableVRs > 0) {
2304 /// EnsureStackAlignment - Round stack frame size up from NumBytes to
2305 /// ensure minimum alignment required for target.
2306 static unsigned EnsureStackAlignment(const TargetMachine &Target,
2307 unsigned NumBytes) {
2308 unsigned TargetAlign = Target.getFrameLowering()->getStackAlignment();
2309 unsigned AlignMask = TargetAlign - 1;
2310 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
2315 PPCTargetLowering::LowerFormalArguments(SDValue Chain,
2316 CallingConv::ID CallConv, bool isVarArg,
2317 const SmallVectorImpl<ISD::InputArg>
2319 SDLoc dl, SelectionDAG &DAG,
2320 SmallVectorImpl<SDValue> &InVals)
2322 if (Subtarget.isSVR4ABI()) {
2323 if (Subtarget.isPPC64())
2324 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins,
2327 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
2330 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
2336 PPCTargetLowering::LowerFormalArguments_32SVR4(
2338 CallingConv::ID CallConv, bool isVarArg,
2339 const SmallVectorImpl<ISD::InputArg>
2341 SDLoc dl, SelectionDAG &DAG,
2342 SmallVectorImpl<SDValue> &InVals) const {
2344 // 32-bit SVR4 ABI Stack Frame Layout:
2345 // +-----------------------------------+
2346 // +--> | Back chain |
2347 // | +-----------------------------------+
2348 // | | Floating-point register save area |
2349 // | +-----------------------------------+
2350 // | | General register save area |
2351 // | +-----------------------------------+
2352 // | | CR save word |
2353 // | +-----------------------------------+
2354 // | | VRSAVE save word |
2355 // | +-----------------------------------+
2356 // | | Alignment padding |
2357 // | +-----------------------------------+
2358 // | | Vector register save area |
2359 // | +-----------------------------------+
2360 // | | Local variable space |
2361 // | +-----------------------------------+
2362 // | | Parameter list area |
2363 // | +-----------------------------------+
2364 // | | LR save word |
2365 // | +-----------------------------------+
2366 // SP--> +--- | Back chain |
2367 // +-----------------------------------+
2370 // System V Application Binary Interface PowerPC Processor Supplement
2371 // AltiVec Technology Programming Interface Manual
2373 MachineFunction &MF = DAG.getMachineFunction();
2374 MachineFrameInfo *MFI = MF.getFrameInfo();
2375 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2377 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2378 // Potential tail calls could cause overwriting of argument stack slots.
2379 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2380 (CallConv == CallingConv::Fast));
2381 unsigned PtrByteSize = 4;
2383 // Assign locations to all of the incoming arguments.
2384 SmallVector<CCValAssign, 16> ArgLocs;
2385 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2386 getTargetMachine(), ArgLocs, *DAG.getContext());
2388 // Reserve space for the linkage area on the stack.
2389 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(false, false, false);
2390 CCInfo.AllocateStack(LinkageSize, PtrByteSize);
2392 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
2394 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2395 CCValAssign &VA = ArgLocs[i];
2397 // Arguments stored in registers.
2398 if (VA.isRegLoc()) {
2399 const TargetRegisterClass *RC;
2400 EVT ValVT = VA.getValVT();
2402 switch (ValVT.getSimpleVT().SimpleTy) {
2404 llvm_unreachable("ValVT not supported by formal arguments Lowering");
2407 RC = &PPC::GPRCRegClass;
2410 RC = &PPC::F4RCRegClass;
2413 if (Subtarget.hasVSX())
2414 RC = &PPC::VSFRCRegClass;
2416 RC = &PPC::F8RCRegClass;
2422 RC = &PPC::VRRCRegClass;
2426 RC = &PPC::VSHRCRegClass;
2430 // Transform the arguments stored in physical registers into virtual ones.
2431 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2432 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg,
2433 ValVT == MVT::i1 ? MVT::i32 : ValVT);
2435 if (ValVT == MVT::i1)
2436 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgValue);
2438 InVals.push_back(ArgValue);
2440 // Argument stored in memory.
2441 assert(VA.isMemLoc());
2443 unsigned ArgSize = VA.getLocVT().getStoreSize();
2444 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
2447 // Create load nodes to retrieve arguments from the stack.
2448 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2449 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2450 MachinePointerInfo(),
2451 false, false, false, 0));
2455 // Assign locations to all of the incoming aggregate by value arguments.
2456 // Aggregates passed by value are stored in the local variable space of the
2457 // caller's stack frame, right above the parameter list area.
2458 SmallVector<CCValAssign, 16> ByValArgLocs;
2459 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2460 getTargetMachine(), ByValArgLocs, *DAG.getContext());
2462 // Reserve stack space for the allocations in CCInfo.
2463 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
2465 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
2467 // Area that is at least reserved in the caller of this function.
2468 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
2469 MinReservedArea = std::max(MinReservedArea, LinkageSize);
2471 // Set the size that is at least reserved in caller of this function. Tail
2472 // call optimized function's reserved stack space needs to be aligned so that
2473 // taking the difference between two stack areas will result in an aligned
2475 MinReservedArea = EnsureStackAlignment(MF.getTarget(), MinReservedArea);
2476 FuncInfo->setMinReservedArea(MinReservedArea);
2478 SmallVector<SDValue, 8> MemOps;
2480 // If the function takes variable number of arguments, make a frame index for
2481 // the start of the first vararg value... for expansion of llvm.va_start.
2483 static const MCPhysReg GPArgRegs[] = {
2484 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2485 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2487 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
2489 static const MCPhysReg FPArgRegs[] = {
2490 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2493 const unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
2495 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs,
2497 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs,
2500 // Make room for NumGPArgRegs and NumFPArgRegs.
2501 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
2502 NumFPArgRegs * EVT(MVT::f64).getSizeInBits()/8;
2504 FuncInfo->setVarArgsStackOffset(
2505 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2506 CCInfo.getNextStackOffset(), true));
2508 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false));
2509 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2511 // The fixed integer arguments of a variadic function are stored to the
2512 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing
2513 // the result of va_next.
2514 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
2515 // Get an existing live-in vreg, or add a new one.
2516 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
2518 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
2520 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2521 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2522 MachinePointerInfo(), false, false, 0);
2523 MemOps.push_back(Store);
2524 // Increment the address by four for the next argument to store
2525 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2526 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2529 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
2531 // The double arguments are stored to the VarArgsFrameIndex
2533 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
2534 // Get an existing live-in vreg, or add a new one.
2535 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
2537 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
2539 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
2540 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2541 MachinePointerInfo(), false, false, 0);
2542 MemOps.push_back(Store);
2543 // Increment the address by eight for the next argument to store
2544 SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8,
2546 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2550 if (!MemOps.empty())
2551 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2556 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2557 // value to MVT::i64 and then truncate to the correct register size.
2559 PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
2560 SelectionDAG &DAG, SDValue ArgVal,
2563 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
2564 DAG.getValueType(ObjectVT));
2565 else if (Flags.isZExt())
2566 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
2567 DAG.getValueType(ObjectVT));
2569 return DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, ArgVal);
2573 PPCTargetLowering::LowerFormalArguments_64SVR4(
2575 CallingConv::ID CallConv, bool isVarArg,
2576 const SmallVectorImpl<ISD::InputArg>
2578 SDLoc dl, SelectionDAG &DAG,
2579 SmallVectorImpl<SDValue> &InVals) const {
2580 // TODO: add description of PPC stack frame format, or at least some docs.
2582 bool isELFv2ABI = Subtarget.isELFv2ABI();
2583 bool isLittleEndian = Subtarget.isLittleEndian();
2584 MachineFunction &MF = DAG.getMachineFunction();
2585 MachineFrameInfo *MFI = MF.getFrameInfo();
2586 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2588 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2589 // Potential tail calls could cause overwriting of argument stack slots.
2590 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2591 (CallConv == CallingConv::Fast));
2592 unsigned PtrByteSize = 8;
2594 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(true, false,
2597 static const MCPhysReg GPR[] = {
2598 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2599 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2602 static const MCPhysReg *FPR = GetFPR();
2604 static const MCPhysReg VR[] = {
2605 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2606 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2608 static const MCPhysReg VSRH[] = {
2609 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
2610 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
2613 const unsigned Num_GPR_Regs = array_lengthof(GPR);
2614 const unsigned Num_FPR_Regs = 13;
2615 const unsigned Num_VR_Regs = array_lengthof(VR);
2617 // Do a first pass over the arguments to determine whether the ABI
2618 // guarantees that our caller has allocated the parameter save area
2619 // on its stack frame. In the ELFv1 ABI, this is always the case;
2620 // in the ELFv2 ABI, it is true if this is a vararg function or if
2621 // any parameter is located in a stack slot.
2623 bool HasParameterArea = !isELFv2ABI || isVarArg;
2624 unsigned ParamAreaSize = Num_GPR_Regs * PtrByteSize;
2625 unsigned NumBytes = LinkageSize;
2626 unsigned AvailableFPRs = Num_FPR_Regs;
2627 unsigned AvailableVRs = Num_VR_Regs;
2628 for (unsigned i = 0, e = Ins.size(); i != e; ++i)
2629 if (CalculateStackSlotUsed(Ins[i].VT, Ins[i].ArgVT, Ins[i].Flags,
2630 PtrByteSize, LinkageSize, ParamAreaSize,
2631 NumBytes, AvailableFPRs, AvailableVRs))
2632 HasParameterArea = true;
2634 // Add DAG nodes to load the arguments or copy them out of registers. On
2635 // entry to a function on PPC, the arguments start after the linkage area,
2636 // although the first ones are often in registers.
2638 unsigned ArgOffset = LinkageSize;
2639 unsigned GPR_idx, FPR_idx = 0, VR_idx = 0;
2640 SmallVector<SDValue, 8> MemOps;
2641 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2642 unsigned CurArgIdx = 0;
2643 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
2645 bool needsLoad = false;
2646 EVT ObjectVT = Ins[ArgNo].VT;
2647 EVT OrigVT = Ins[ArgNo].ArgVT;
2648 unsigned ObjSize = ObjectVT.getStoreSize();
2649 unsigned ArgSize = ObjSize;
2650 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2651 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2652 CurArgIdx = Ins[ArgNo].OrigArgIndex;
2654 /* Respect alignment of argument on the stack. */
2656 CalculateStackSlotAlignment(ObjectVT, OrigVT, Flags, PtrByteSize);
2657 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
2658 unsigned CurArgOffset = ArgOffset;
2660 /* Compute GPR index associated with argument offset. */
2661 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
2662 GPR_idx = std::min(GPR_idx, Num_GPR_Regs);
2664 // FIXME the codegen can be much improved in some cases.
2665 // We do not have to keep everything in memory.
2666 if (Flags.isByVal()) {
2667 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2668 ObjSize = Flags.getByValSize();
2669 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2670 // Empty aggregate parameters do not take up registers. Examples:
2674 // etc. However, we have to provide a place-holder in InVals, so
2675 // pretend we have an 8-byte item at the current address for that
2678 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2679 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2680 InVals.push_back(FIN);
2684 // Create a stack object covering all stack doublewords occupied
2685 // by the argument. If the argument is (fully or partially) on
2686 // the stack, or if the argument is fully in registers but the
2687 // caller has allocated the parameter save anyway, we can refer
2688 // directly to the caller's stack frame. Otherwise, create a
2689 // local copy in our own frame.
2691 if (HasParameterArea ||
2692 ArgSize + ArgOffset > LinkageSize + Num_GPR_Regs * PtrByteSize)
2693 FI = MFI->CreateFixedObject(ArgSize, ArgOffset, true);
2695 FI = MFI->CreateStackObject(ArgSize, Align, false);
2696 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2698 // Handle aggregates smaller than 8 bytes.
2699 if (ObjSize < PtrByteSize) {
2700 // The value of the object is its address, which differs from the
2701 // address of the enclosing doubleword on big-endian systems.
2703 if (!isLittleEndian) {
2704 SDValue ArgOff = DAG.getConstant(PtrByteSize - ObjSize, PtrVT);
2705 Arg = DAG.getNode(ISD::ADD, dl, ArgOff.getValueType(), Arg, ArgOff);
2707 InVals.push_back(Arg);
2709 if (GPR_idx != Num_GPR_Regs) {
2710 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2711 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2714 if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
2715 EVT ObjType = (ObjSize == 1 ? MVT::i8 :
2716 (ObjSize == 2 ? MVT::i16 : MVT::i32));
2717 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, Arg,
2718 MachinePointerInfo(FuncArg),
2719 ObjType, false, false, 0);
2721 // For sizes that don't fit a truncating store (3, 5, 6, 7),
2722 // store the whole register as-is to the parameter save area
2724 Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2725 MachinePointerInfo(FuncArg),
2729 MemOps.push_back(Store);
2731 // Whether we copied from a register or not, advance the offset
2732 // into the parameter save area by a full doubleword.
2733 ArgOffset += PtrByteSize;
2737 // The value of the object is its address, which is the address of
2738 // its first stack doubleword.
2739 InVals.push_back(FIN);
2741 // Store whatever pieces of the object are in registers to memory.
2742 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2743 if (GPR_idx == Num_GPR_Regs)
2746 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2747 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2750 SDValue Off = DAG.getConstant(j, PtrVT);
2751 Addr = DAG.getNode(ISD::ADD, dl, Off.getValueType(), Addr, Off);
2753 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, Addr,
2754 MachinePointerInfo(FuncArg, j),
2756 MemOps.push_back(Store);
2759 ArgOffset += ArgSize;
2763 switch (ObjectVT.getSimpleVT().SimpleTy) {
2764 default: llvm_unreachable("Unhandled argument type!");
2768 // These can be scalar arguments or elements of an integer array type
2769 // passed directly. Clang may use those instead of "byval" aggregate
2770 // types to avoid forcing arguments to memory unnecessarily.
2771 if (GPR_idx != Num_GPR_Regs) {
2772 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2773 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2775 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
2776 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2777 // value to MVT::i64 and then truncate to the correct register size.
2778 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2781 ArgSize = PtrByteSize;
2788 // These can be scalar arguments or elements of a float array type
2789 // passed directly. The latter are used to implement ELFv2 homogenous
2790 // float aggregates.
2791 if (FPR_idx != Num_FPR_Regs) {
2794 if (ObjectVT == MVT::f32)
2795 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2797 VReg = MF.addLiveIn(FPR[FPR_idx], Subtarget.hasVSX() ?
2798 &PPC::VSFRCRegClass :
2799 &PPC::F8RCRegClass);
2801 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2803 } else if (GPR_idx != Num_GPR_Regs) {
2804 // This can only ever happen in the presence of f32 array types,
2805 // since otherwise we never run out of FPRs before running out
2807 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2808 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2810 if (ObjectVT == MVT::f32) {
2811 if ((ArgOffset % PtrByteSize) == (isLittleEndian ? 4 : 0))
2812 ArgVal = DAG.getNode(ISD::SRL, dl, MVT::i64, ArgVal,
2813 DAG.getConstant(32, MVT::i32));
2814 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
2817 ArgVal = DAG.getNode(ISD::BITCAST, dl, ObjectVT, ArgVal);
2822 // When passing an array of floats, the array occupies consecutive
2823 // space in the argument area; only round up to the next doubleword
2824 // at the end of the array. Otherwise, each float takes 8 bytes.
2825 ArgSize = Flags.isInConsecutiveRegs() ? ObjSize : PtrByteSize;
2826 ArgOffset += ArgSize;
2827 if (Flags.isInConsecutiveRegsLast())
2828 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2836 // These can be scalar arguments or elements of a vector array type
2837 // passed directly. The latter are used to implement ELFv2 homogenous
2838 // vector aggregates.
2839 if (VR_idx != Num_VR_Regs) {
2840 unsigned VReg = (ObjectVT == MVT::v2f64 || ObjectVT == MVT::v2i64) ?
2841 MF.addLiveIn(VSRH[VR_idx], &PPC::VSHRCRegClass) :
2842 MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2843 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2852 // We need to load the argument to a virtual register if we determined
2853 // above that we ran out of physical registers of the appropriate type.
2855 if (ObjSize < ArgSize && !isLittleEndian)
2856 CurArgOffset += ArgSize - ObjSize;
2857 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, isImmutable);
2858 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2859 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2860 false, false, false, 0);
2863 InVals.push_back(ArgVal);
2866 // Area that is at least reserved in the caller of this function.
2867 unsigned MinReservedArea;
2868 if (HasParameterArea)
2869 MinReservedArea = std::max(ArgOffset, LinkageSize + 8 * PtrByteSize);
2871 MinReservedArea = LinkageSize;
2873 // Set the size that is at least reserved in caller of this function. Tail
2874 // call optimized functions' reserved stack space needs to be aligned so that
2875 // taking the difference between two stack areas will result in an aligned
2877 MinReservedArea = EnsureStackAlignment(MF.getTarget(), MinReservedArea);
2878 FuncInfo->setMinReservedArea(MinReservedArea);
2880 // If the function takes variable number of arguments, make a frame index for
2881 // the start of the first vararg value... for expansion of llvm.va_start.
2883 int Depth = ArgOffset;
2885 FuncInfo->setVarArgsFrameIndex(
2886 MFI->CreateFixedObject(PtrByteSize, Depth, true));
2887 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2889 // If this function is vararg, store any remaining integer argument regs
2890 // to their spots on the stack so that they may be loaded by deferencing the
2891 // result of va_next.
2892 for (GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
2893 GPR_idx < Num_GPR_Regs; ++GPR_idx) {
2894 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2895 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2896 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2897 MachinePointerInfo(), false, false, 0);
2898 MemOps.push_back(Store);
2899 // Increment the address by four for the next argument to store
2900 SDValue PtrOff = DAG.getConstant(PtrByteSize, PtrVT);
2901 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2905 if (!MemOps.empty())
2906 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2912 PPCTargetLowering::LowerFormalArguments_Darwin(
2914 CallingConv::ID CallConv, bool isVarArg,
2915 const SmallVectorImpl<ISD::InputArg>
2917 SDLoc dl, SelectionDAG &DAG,
2918 SmallVectorImpl<SDValue> &InVals) const {
2919 // TODO: add description of PPC stack frame format, or at least some docs.
2921 MachineFunction &MF = DAG.getMachineFunction();
2922 MachineFrameInfo *MFI = MF.getFrameInfo();
2923 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2925 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2926 bool isPPC64 = PtrVT == MVT::i64;
2927 // Potential tail calls could cause overwriting of argument stack slots.
2928 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2929 (CallConv == CallingConv::Fast));
2930 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2932 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(isPPC64, true,
2934 unsigned ArgOffset = LinkageSize;
2935 // Area that is at least reserved in caller of this function.
2936 unsigned MinReservedArea = ArgOffset;
2938 static const MCPhysReg GPR_32[] = { // 32-bit registers.
2939 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2940 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2942 static const MCPhysReg GPR_64[] = { // 64-bit registers.
2943 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2944 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2947 static const MCPhysReg *FPR = GetFPR();
2949 static const MCPhysReg VR[] = {
2950 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2951 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2954 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
2955 const unsigned Num_FPR_Regs = 13;
2956 const unsigned Num_VR_Regs = array_lengthof( VR);
2958 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2960 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
2962 // In 32-bit non-varargs functions, the stack space for vectors is after the
2963 // stack space for non-vectors. We do not use this space unless we have
2964 // too many vectors to fit in registers, something that only occurs in
2965 // constructed examples:), but we have to walk the arglist to figure
2966 // that out...for the pathological case, compute VecArgOffset as the
2967 // start of the vector parameter area. Computing VecArgOffset is the
2968 // entire point of the following loop.
2969 unsigned VecArgOffset = ArgOffset;
2970 if (!isVarArg && !isPPC64) {
2971 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
2973 EVT ObjectVT = Ins[ArgNo].VT;
2974 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2976 if (Flags.isByVal()) {
2977 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
2978 unsigned ObjSize = Flags.getByValSize();
2980 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2981 VecArgOffset += ArgSize;
2985 switch(ObjectVT.getSimpleVT().SimpleTy) {
2986 default: llvm_unreachable("Unhandled argument type!");
2992 case MVT::i64: // PPC64
2994 // FIXME: We are guaranteed to be !isPPC64 at this point.
2995 // Does MVT::i64 apply?
3002 // Nothing to do, we're only looking at Nonvector args here.
3007 // We've found where the vector parameter area in memory is. Skip the
3008 // first 12 parameters; these don't use that memory.
3009 VecArgOffset = ((VecArgOffset+15)/16)*16;
3010 VecArgOffset += 12*16;
3012 // Add DAG nodes to load the arguments or copy them out of registers. On
3013 // entry to a function on PPC, the arguments start after the linkage area,
3014 // although the first ones are often in registers.
3016 SmallVector<SDValue, 8> MemOps;
3017 unsigned nAltivecParamsAtEnd = 0;
3018 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
3019 unsigned CurArgIdx = 0;
3020 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
3022 bool needsLoad = false;
3023 EVT ObjectVT = Ins[ArgNo].VT;
3024 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
3025 unsigned ArgSize = ObjSize;
3026 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3027 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
3028 CurArgIdx = Ins[ArgNo].OrigArgIndex;
3030 unsigned CurArgOffset = ArgOffset;
3032 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
3033 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
3034 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
3035 if (isVarArg || isPPC64) {
3036 MinReservedArea = ((MinReservedArea+15)/16)*16;
3037 MinReservedArea += CalculateStackSlotSize(ObjectVT,
3040 } else nAltivecParamsAtEnd++;
3042 // Calculate min reserved area.
3043 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
3047 // FIXME the codegen can be much improved in some cases.
3048 // We do not have to keep everything in memory.
3049 if (Flags.isByVal()) {
3050 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
3051 ObjSize = Flags.getByValSize();
3052 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3053 // Objects of size 1 and 2 are right justified, everything else is
3054 // left justified. This means the memory address is adjusted forwards.
3055 if (ObjSize==1 || ObjSize==2) {
3056 CurArgOffset = CurArgOffset + (4 - ObjSize);
3058 // The value of the object is its address.
3059 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
3060 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3061 InVals.push_back(FIN);
3062 if (ObjSize==1 || ObjSize==2) {
3063 if (GPR_idx != Num_GPR_Regs) {
3066 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3068 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3069 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3070 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16;
3071 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
3072 MachinePointerInfo(FuncArg),
3073 ObjType, false, false, 0);
3074 MemOps.push_back(Store);
3078 ArgOffset += PtrByteSize;
3082 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
3083 // Store whatever pieces of the object are in registers
3084 // to memory. ArgOffset will be the address of the beginning
3086 if (GPR_idx != Num_GPR_Regs) {
3089 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3091 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3092 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
3093 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3094 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3095 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3096 MachinePointerInfo(FuncArg, j),
3098 MemOps.push_back(Store);
3100 ArgOffset += PtrByteSize;
3102 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
3109 switch (ObjectVT.getSimpleVT().SimpleTy) {
3110 default: llvm_unreachable("Unhandled argument type!");
3114 if (GPR_idx != Num_GPR_Regs) {
3115 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3116 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
3118 if (ObjectVT == MVT::i1)
3119 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgVal);
3124 ArgSize = PtrByteSize;
3126 // All int arguments reserve stack space in the Darwin ABI.
3127 ArgOffset += PtrByteSize;
3131 case MVT::i64: // PPC64
3132 if (GPR_idx != Num_GPR_Regs) {
3133 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3134 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3136 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
3137 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
3138 // value to MVT::i64 and then truncate to the correct register size.
3139 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
3144 ArgSize = PtrByteSize;
3146 // All int arguments reserve stack space in the Darwin ABI.
3152 // Every 4 bytes of argument space consumes one of the GPRs available for
3153 // argument passing.
3154 if (GPR_idx != Num_GPR_Regs) {
3156 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
3159 if (FPR_idx != Num_FPR_Regs) {
3162 if (ObjectVT == MVT::f32)
3163 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
3165 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
3167 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3173 // All FP arguments reserve stack space in the Darwin ABI.
3174 ArgOffset += isPPC64 ? 8 : ObjSize;
3180 // Note that vector arguments in registers don't reserve stack space,
3181 // except in varargs functions.
3182 if (VR_idx != Num_VR_Regs) {
3183 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
3184 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3186 while ((ArgOffset % 16) != 0) {
3187 ArgOffset += PtrByteSize;
3188 if (GPR_idx != Num_GPR_Regs)
3192 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
3196 if (!isVarArg && !isPPC64) {
3197 // Vectors go after all the nonvectors.
3198 CurArgOffset = VecArgOffset;
3201 // Vectors are aligned.
3202 ArgOffset = ((ArgOffset+15)/16)*16;
3203 CurArgOffset = ArgOffset;
3211 // We need to load the argument to a virtual register if we determined above
3212 // that we ran out of physical registers of the appropriate type.
3214 int FI = MFI->CreateFixedObject(ObjSize,
3215 CurArgOffset + (ArgSize - ObjSize),
3217 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3218 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
3219 false, false, false, 0);
3222 InVals.push_back(ArgVal);
3225 // Allow for Altivec parameters at the end, if needed.
3226 if (nAltivecParamsAtEnd) {
3227 MinReservedArea = ((MinReservedArea+15)/16)*16;
3228 MinReservedArea += 16*nAltivecParamsAtEnd;
3231 // Area that is at least reserved in the caller of this function.
3232 MinReservedArea = std::max(MinReservedArea, LinkageSize + 8 * PtrByteSize);
3234 // Set the size that is at least reserved in caller of this function. Tail
3235 // call optimized functions' reserved stack space needs to be aligned so that
3236 // taking the difference between two stack areas will result in an aligned
3238 MinReservedArea = EnsureStackAlignment(MF.getTarget(), MinReservedArea);
3239 FuncInfo->setMinReservedArea(MinReservedArea);
3241 // If the function takes variable number of arguments, make a frame index for
3242 // the start of the first vararg value... for expansion of llvm.va_start.
3244 int Depth = ArgOffset;
3246 FuncInfo->setVarArgsFrameIndex(
3247 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
3249 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3251 // If this function is vararg, store any remaining integer argument regs
3252 // to their spots on the stack so that they may be loaded by deferencing the
3253 // result of va_next.
3254 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
3258 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3260 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3262 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3263 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3264 MachinePointerInfo(), false, false, 0);
3265 MemOps.push_back(Store);
3266 // Increment the address by four for the next argument to store
3267 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
3268 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3272 if (!MemOps.empty())
3273 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3278 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
3279 /// adjusted to accommodate the arguments for the tailcall.
3280 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
3281 unsigned ParamSize) {
3283 if (!isTailCall) return 0;
3285 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
3286 unsigned CallerMinReservedArea = FI->getMinReservedArea();
3287 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
3288 // Remember only if the new adjustement is bigger.
3289 if (SPDiff < FI->getTailCallSPDelta())
3290 FI->setTailCallSPDelta(SPDiff);
3295 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3296 /// for tail call optimization. Targets which want to do tail call
3297 /// optimization should implement this function.
3299 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3300 CallingConv::ID CalleeCC,
3302 const SmallVectorImpl<ISD::InputArg> &Ins,
3303 SelectionDAG& DAG) const {
3304 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
3307 // Variable argument functions are not supported.
3311 MachineFunction &MF = DAG.getMachineFunction();
3312 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
3313 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
3314 // Functions containing by val parameters are not supported.
3315 for (unsigned i = 0; i != Ins.size(); i++) {
3316 ISD::ArgFlagsTy Flags = Ins[i].Flags;
3317 if (Flags.isByVal()) return false;
3320 // Non-PIC/GOT tail calls are supported.
3321 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
3324 // At the moment we can only do local tail calls (in same module, hidden
3325 // or protected) if we are generating PIC.
3326 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3327 return G->getGlobal()->hasHiddenVisibility()
3328 || G->getGlobal()->hasProtectedVisibility();
3334 /// isCallCompatibleAddress - Return the immediate to use if the specified
3335 /// 32-bit value is representable in the immediate field of a BxA instruction.
3336 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
3337 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
3338 if (!C) return nullptr;
3340 int Addr = C->getZExtValue();
3341 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
3342 SignExtend32<26>(Addr) != Addr)
3343 return nullptr; // Top 6 bits have to be sext of immediate.
3345 return DAG.getConstant((int)C->getZExtValue() >> 2,
3346 DAG.getTargetLoweringInfo().getPointerTy()).getNode();
3351 struct TailCallArgumentInfo {
3356 TailCallArgumentInfo() : FrameIdx(0) {}
3361 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
3363 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
3365 const SmallVectorImpl<TailCallArgumentInfo> &TailCallArgs,
3366 SmallVectorImpl<SDValue> &MemOpChains,
3368 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
3369 SDValue Arg = TailCallArgs[i].Arg;
3370 SDValue FIN = TailCallArgs[i].FrameIdxOp;
3371 int FI = TailCallArgs[i].FrameIdx;
3372 // Store relative to framepointer.
3373 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
3374 MachinePointerInfo::getFixedStack(FI),
3379 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
3380 /// the appropriate stack slot for the tail call optimized function call.
3381 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
3382 MachineFunction &MF,
3391 // Calculate the new stack slot for the return address.
3392 int SlotSize = isPPC64 ? 8 : 4;
3393 int NewRetAddrLoc = SPDiff + PPCFrameLowering::getReturnSaveOffset(isPPC64,
3395 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3396 NewRetAddrLoc, true);
3397 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3398 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
3399 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
3400 MachinePointerInfo::getFixedStack(NewRetAddr),
3403 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
3404 // slot as the FP is never overwritten.
3407 SPDiff + PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
3408 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
3410 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
3411 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
3412 MachinePointerInfo::getFixedStack(NewFPIdx),
3419 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
3420 /// the position of the argument.
3422 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
3423 SDValue Arg, int SPDiff, unsigned ArgOffset,
3424 SmallVectorImpl<TailCallArgumentInfo>& TailCallArguments) {
3425 int Offset = ArgOffset + SPDiff;
3426 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
3427 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3428 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3429 SDValue FIN = DAG.getFrameIndex(FI, VT);
3430 TailCallArgumentInfo Info;
3432 Info.FrameIdxOp = FIN;
3434 TailCallArguments.push_back(Info);
3437 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
3438 /// stack slot. Returns the chain as result and the loaded frame pointers in
3439 /// LROpOut/FPOpout. Used when tail calling.
3440 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
3448 // Load the LR and FP stack slot for later adjusting.
3449 EVT VT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
3450 LROpOut = getReturnAddrFrameIndex(DAG);
3451 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(),
3452 false, false, false, 0);
3453 Chain = SDValue(LROpOut.getNode(), 1);
3455 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
3456 // slot as the FP is never overwritten.
3458 FPOpOut = getFramePointerFrameIndex(DAG);
3459 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(),
3460 false, false, false, 0);
3461 Chain = SDValue(FPOpOut.getNode(), 1);
3467 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
3468 /// by "Src" to address "Dst" of size "Size". Alignment information is
3469 /// specified by the specific parameter attribute. The copy will be passed as
3470 /// a byval function parameter.
3471 /// Sometimes what we are copying is the end of a larger object, the part that
3472 /// does not fit in registers.
3474 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
3475 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
3477 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
3478 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
3479 false, false, MachinePointerInfo(),
3480 MachinePointerInfo());
3483 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
3486 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
3487 SDValue Arg, SDValue PtrOff, int SPDiff,
3488 unsigned ArgOffset, bool isPPC64, bool isTailCall,
3489 bool isVector, SmallVectorImpl<SDValue> &MemOpChains,
3490 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments,
3492 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3497 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3499 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3500 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
3501 DAG.getConstant(ArgOffset, PtrVT));
3503 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3504 MachinePointerInfo(), false, false, 0));
3505 // Calculate and remember argument location.
3506 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
3511 void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
3512 SDLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
3513 SDValue LROp, SDValue FPOp, bool isDarwinABI,
3514 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments) {
3515 MachineFunction &MF = DAG.getMachineFunction();
3517 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
3518 // might overwrite each other in case of tail call optimization.
3519 SmallVector<SDValue, 8> MemOpChains2;
3520 // Do not flag preceding copytoreg stuff together with the following stuff.
3522 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
3524 if (!MemOpChains2.empty())
3525 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3527 // Store the return address to the appropriate stack slot.
3528 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
3529 isPPC64, isDarwinABI, dl);
3531 // Emit callseq_end just before tailcall node.
3532 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3533 DAG.getIntPtrConstant(0, true), InFlag, dl);
3534 InFlag = Chain.getValue(1);
3538 unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
3539 SDValue &Chain, SDLoc dl, int SPDiff, bool isTailCall,
3540 SmallVectorImpl<std::pair<unsigned, SDValue> > &RegsToPass,
3541 SmallVectorImpl<SDValue> &Ops, std::vector<EVT> &NodeTys,
3542 const PPCSubtarget &Subtarget) {
3544 bool isPPC64 = Subtarget.isPPC64();
3545 bool isSVR4ABI = Subtarget.isSVR4ABI();
3546 bool isELFv2ABI = Subtarget.isELFv2ABI();
3548 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3549 NodeTys.push_back(MVT::Other); // Returns a chain
3550 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
3552 unsigned CallOpc = PPCISD::CALL;
3554 bool needIndirectCall = true;
3555 if (!isSVR4ABI || !isPPC64)
3556 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) {
3557 // If this is an absolute destination address, use the munged value.
3558 Callee = SDValue(Dest, 0);
3559 needIndirectCall = false;
3562 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3563 // XXX Work around for http://llvm.org/bugs/show_bug.cgi?id=5201
3564 // Use indirect calls for ALL functions calls in JIT mode, since the
3565 // far-call stubs may be outside relocation limits for a BL instruction.
3566 if (!DAG.getTarget().getSubtarget<PPCSubtarget>().isJITCodeModel()) {
3567 unsigned OpFlags = 0;
3568 if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
3569 (Subtarget.getTargetTriple().isMacOSX() &&
3570 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5)) &&
3571 (G->getGlobal()->isDeclaration() ||
3572 G->getGlobal()->isWeakForLinker())) ||
3573 (Subtarget.isTargetELF() && !isPPC64 &&
3574 !G->getGlobal()->hasLocalLinkage() &&
3575 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3576 // PC-relative references to external symbols should go through $stub,
3577 // unless we're building with the leopard linker or later, which
3578 // automatically synthesizes these stubs.
3579 OpFlags = PPCII::MO_PLT_OR_STUB;
3582 // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
3583 // every direct call is) turn it into a TargetGlobalAddress /
3584 // TargetExternalSymbol node so that legalize doesn't hack it.
3585 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
3586 Callee.getValueType(),
3588 needIndirectCall = false;
3592 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3593 unsigned char OpFlags = 0;
3595 if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
3596 (Subtarget.getTargetTriple().isMacOSX() &&
3597 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5))) ||
3598 (Subtarget.isTargetELF() && !isPPC64 &&
3599 DAG.getTarget().getRelocationModel() == Reloc::PIC_) ) {
3600 // PC-relative references to external symbols should go through $stub,
3601 // unless we're building with the leopard linker or later, which
3602 // automatically synthesizes these stubs.
3603 OpFlags = PPCII::MO_PLT_OR_STUB;
3606 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
3608 needIndirectCall = false;
3611 if (needIndirectCall) {
3612 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
3613 // to do the call, we can't use PPCISD::CALL.
3614 SDValue MTCTROps[] = {Chain, Callee, InFlag};
3616 if (isSVR4ABI && isPPC64 && !isELFv2ABI) {
3617 // Function pointers in the 64-bit SVR4 ABI do not point to the function
3618 // entry point, but to the function descriptor (the function entry point
3619 // address is part of the function descriptor though).
3620 // The function descriptor is a three doubleword structure with the
3621 // following fields: function entry point, TOC base address and
3622 // environment pointer.
3623 // Thus for a call through a function pointer, the following actions need
3625 // 1. Save the TOC of the caller in the TOC save area of its stack
3626 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()).
3627 // 2. Load the address of the function entry point from the function
3629 // 3. Load the TOC of the callee from the function descriptor into r2.
3630 // 4. Load the environment pointer from the function descriptor into
3632 // 5. Branch to the function entry point address.
3633 // 6. On return of the callee, the TOC of the caller needs to be
3634 // restored (this is done in FinishCall()).
3636 // All those operations are flagged together to ensure that no other
3637 // operations can be scheduled in between. E.g. without flagging the
3638 // operations together, a TOC access in the caller could be scheduled
3639 // between the load of the callee TOC and the branch to the callee, which
3640 // results in the TOC access going through the TOC of the callee instead
3641 // of going through the TOC of the caller, which leads to incorrect code.
3643 // Load the address of the function entry point from the function
3645 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Glue);
3646 SDValue LoadFuncPtr = DAG.getNode(PPCISD::LOAD, dl, VTs,
3647 makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
3648 Chain = LoadFuncPtr.getValue(1);
3649 InFlag = LoadFuncPtr.getValue(2);
3651 // Load environment pointer into r11.
3652 // Offset of the environment pointer within the function descriptor.
3653 SDValue PtrOff = DAG.getIntPtrConstant(16);
3655 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
3656 SDValue LoadEnvPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, Chain, AddPtr,
3658 Chain = LoadEnvPtr.getValue(1);
3659 InFlag = LoadEnvPtr.getValue(2);
3661 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
3663 Chain = EnvVal.getValue(0);
3664 InFlag = EnvVal.getValue(1);
3666 // Load TOC of the callee into r2. We are using a target-specific load
3667 // with r2 hard coded, because the result of a target-independent load
3668 // would never go directly into r2, since r2 is a reserved register (which
3669 // prevents the register allocator from allocating it), resulting in an
3670 // additional register being allocated and an unnecessary move instruction
3672 VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3673 SDValue TOCOff = DAG.getIntPtrConstant(8);
3674 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, TOCOff);
3675 SDValue LoadTOCPtr = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain,
3677 Chain = LoadTOCPtr.getValue(0);
3678 InFlag = LoadTOCPtr.getValue(1);
3680 MTCTROps[0] = Chain;
3681 MTCTROps[1] = LoadFuncPtr;
3682 MTCTROps[2] = InFlag;
3685 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys,
3686 makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
3687 InFlag = Chain.getValue(1);
3690 NodeTys.push_back(MVT::Other);
3691 NodeTys.push_back(MVT::Glue);
3692 Ops.push_back(Chain);
3693 CallOpc = PPCISD::BCTRL;
3694 Callee.setNode(nullptr);
3695 // Add use of X11 (holding environment pointer)
3696 if (isSVR4ABI && isPPC64 && !isELFv2ABI)
3697 Ops.push_back(DAG.getRegister(PPC::X11, PtrVT));
3698 // Add CTR register as callee so a bctr can be emitted later.
3700 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT));
3703 // If this is a direct call, pass the chain and the callee.
3704 if (Callee.getNode()) {
3705 Ops.push_back(Chain);
3706 Ops.push_back(Callee);
3708 // If this is a tail call add stack pointer delta.
3710 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
3712 // Add argument registers to the end of the list so that they are known live
3714 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3715 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3716 RegsToPass[i].second.getValueType()));
3718 // Direct calls in the ELFv2 ABI need the TOC register live into the call.
3719 if (Callee.getNode() && isELFv2ABI)
3720 Ops.push_back(DAG.getRegister(PPC::X2, PtrVT));
3726 bool isLocalCall(const SDValue &Callee)
3728 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3729 return !G->getGlobal()->isDeclaration() &&
3730 !G->getGlobal()->isWeakForLinker();
3735 PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
3736 CallingConv::ID CallConv, bool isVarArg,
3737 const SmallVectorImpl<ISD::InputArg> &Ins,
3738 SDLoc dl, SelectionDAG &DAG,
3739 SmallVectorImpl<SDValue> &InVals) const {
3741 SmallVector<CCValAssign, 16> RVLocs;
3742 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3743 getTargetMachine(), RVLocs, *DAG.getContext());
3744 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
3746 // Copy all of the result registers out of their specified physreg.
3747 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3748 CCValAssign &VA = RVLocs[i];
3749 assert(VA.isRegLoc() && "Can only return in registers!");
3751 SDValue Val = DAG.getCopyFromReg(Chain, dl,
3752 VA.getLocReg(), VA.getLocVT(), InFlag);
3753 Chain = Val.getValue(1);
3754 InFlag = Val.getValue(2);
3756 switch (VA.getLocInfo()) {
3757 default: llvm_unreachable("Unknown loc info!");
3758 case CCValAssign::Full: break;
3759 case CCValAssign::AExt:
3760 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3762 case CCValAssign::ZExt:
3763 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
3764 DAG.getValueType(VA.getValVT()));
3765 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3767 case CCValAssign::SExt:
3768 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
3769 DAG.getValueType(VA.getValVT()));
3770 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3774 InVals.push_back(Val);
3781 PPCTargetLowering::FinishCall(CallingConv::ID CallConv, SDLoc dl,
3782 bool isTailCall, bool isVarArg,
3784 SmallVector<std::pair<unsigned, SDValue>, 8>
3786 SDValue InFlag, SDValue Chain,
3788 int SPDiff, unsigned NumBytes,
3789 const SmallVectorImpl<ISD::InputArg> &Ins,
3790 SmallVectorImpl<SDValue> &InVals) const {
3792 bool isELFv2ABI = Subtarget.isELFv2ABI();
3793 std::vector<EVT> NodeTys;
3794 SmallVector<SDValue, 8> Ops;
3795 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff,
3796 isTailCall, RegsToPass, Ops, NodeTys,
3799 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
3800 if (isVarArg && Subtarget.isSVR4ABI() && !Subtarget.isPPC64())
3801 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
3803 // When performing tail call optimization the callee pops its arguments off
3804 // the stack. Account for this here so these bytes can be pushed back on in
3805 // PPCFrameLowering::eliminateCallFramePseudoInstr.
3806 int BytesCalleePops =
3807 (CallConv == CallingConv::Fast &&
3808 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0;
3810 // Add a register mask operand representing the call-preserved registers.
3811 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
3812 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3813 assert(Mask && "Missing call preserved mask for calling convention");
3814 Ops.push_back(DAG.getRegisterMask(Mask));
3816 if (InFlag.getNode())
3817 Ops.push_back(InFlag);
3821 assert(((Callee.getOpcode() == ISD::Register &&
3822 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
3823 Callee.getOpcode() == ISD::TargetExternalSymbol ||
3824 Callee.getOpcode() == ISD::TargetGlobalAddress ||
3825 isa<ConstantSDNode>(Callee)) &&
3826 "Expecting an global address, external symbol, absolute value or register");
3828 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, Ops);
3831 // Add a NOP immediately after the branch instruction when using the 64-bit
3832 // SVR4 ABI. At link time, if caller and callee are in a different module and
3833 // thus have a different TOC, the call will be replaced with a call to a stub
3834 // function which saves the current TOC, loads the TOC of the callee and
3835 // branches to the callee. The NOP will be replaced with a load instruction
3836 // which restores the TOC of the caller from the TOC save slot of the current
3837 // stack frame. If caller and callee belong to the same module (and have the
3838 // same TOC), the NOP will remain unchanged.
3840 bool needsTOCRestore = false;
3841 if (!isTailCall && Subtarget.isSVR4ABI()&& Subtarget.isPPC64()) {
3842 if (CallOpc == PPCISD::BCTRL) {
3843 // This is a call through a function pointer.
3844 // Restore the caller TOC from the save area into R2.
3845 // See PrepareCall() for more information about calls through function
3846 // pointers in the 64-bit SVR4 ABI.
3847 // We are using a target-specific load with r2 hard coded, because the
3848 // result of a target-independent load would never go directly into r2,
3849 // since r2 is a reserved register (which prevents the register allocator
3850 // from allocating it), resulting in an additional register being
3851 // allocated and an unnecessary move instruction being generated.
3852 needsTOCRestore = true;
3853 } else if ((CallOpc == PPCISD::CALL) &&
3854 (!isLocalCall(Callee) ||
3855 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3856 // Otherwise insert NOP for non-local calls.
3857 CallOpc = PPCISD::CALL_NOP;
3861 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
3862 InFlag = Chain.getValue(1);
3864 if (needsTOCRestore) {
3865 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3866 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3867 SDValue StackPtr = DAG.getRegister(PPC::X1, PtrVT);
3868 unsigned TOCSaveOffset = PPCFrameLowering::getTOCSaveOffset(isELFv2ABI);
3869 SDValue TOCOff = DAG.getIntPtrConstant(TOCSaveOffset);
3870 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, StackPtr, TOCOff);
3871 Chain = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain, AddTOC, InFlag);
3872 InFlag = Chain.getValue(1);
3875 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3876 DAG.getIntPtrConstant(BytesCalleePops, true),
3879 InFlag = Chain.getValue(1);
3881 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3882 Ins, dl, DAG, InVals);
3886 PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
3887 SmallVectorImpl<SDValue> &InVals) const {
3888 SelectionDAG &DAG = CLI.DAG;
3890 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
3891 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
3892 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
3893 SDValue Chain = CLI.Chain;
3894 SDValue Callee = CLI.Callee;
3895 bool &isTailCall = CLI.IsTailCall;
3896 CallingConv::ID CallConv = CLI.CallConv;
3897 bool isVarArg = CLI.IsVarArg;
3900 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
3903 if (!isTailCall && CLI.CS && CLI.CS->isMustTailCall())
3904 report_fatal_error("failed to perform tail call elimination on a call "
3905 "site marked musttail");
3907 if (Subtarget.isSVR4ABI()) {
3908 if (Subtarget.isPPC64())
3909 return LowerCall_64SVR4(Chain, Callee, CallConv, isVarArg,
3910 isTailCall, Outs, OutVals, Ins,
3913 return LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg,
3914 isTailCall, Outs, OutVals, Ins,
3918 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
3919 isTailCall, Outs, OutVals, Ins,
3924 PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee,
3925 CallingConv::ID CallConv, bool isVarArg,
3927 const SmallVectorImpl<ISD::OutputArg> &Outs,
3928 const SmallVectorImpl<SDValue> &OutVals,
3929 const SmallVectorImpl<ISD::InputArg> &Ins,
3930 SDLoc dl, SelectionDAG &DAG,
3931 SmallVectorImpl<SDValue> &InVals) const {
3932 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description
3933 // of the 32-bit SVR4 ABI stack frame layout.
3935 assert((CallConv == CallingConv::C ||
3936 CallConv == CallingConv::Fast) && "Unknown calling convention!");
3938 unsigned PtrByteSize = 4;
3940 MachineFunction &MF = DAG.getMachineFunction();
3942 // Mark this function as potentially containing a function that contains a
3943 // tail call. As a consequence the frame pointer will be used for dynamicalloc
3944 // and restoring the callers stack pointer in this functions epilog. This is
3945 // done because by tail calling the called function might overwrite the value
3946 // in this function's (MF) stack pointer stack slot 0(SP).
3947 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
3948 CallConv == CallingConv::Fast)
3949 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
3951 // Count how many bytes are to be pushed on the stack, including the linkage
3952 // area, parameter list area and the part of the local variable space which
3953 // contains copies of aggregates which are passed by value.
3955 // Assign locations to all of the outgoing arguments.
3956 SmallVector<CCValAssign, 16> ArgLocs;
3957 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3958 getTargetMachine(), ArgLocs, *DAG.getContext());
3960 // Reserve space for the linkage area on the stack.
3961 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false, false),
3965 // Handle fixed and variable vector arguments differently.
3966 // Fixed vector arguments go into registers as long as registers are
3967 // available. Variable vector arguments always go into memory.
3968 unsigned NumArgs = Outs.size();
3970 for (unsigned i = 0; i != NumArgs; ++i) {
3971 MVT ArgVT = Outs[i].VT;
3972 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
3975 if (Outs[i].IsFixed) {
3976 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
3979 Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
3985 errs() << "Call operand #" << i << " has unhandled type "
3986 << EVT(ArgVT).getEVTString() << "\n";
3988 llvm_unreachable(nullptr);
3992 // All arguments are treated the same.
3993 CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4);
3996 // Assign locations to all of the outgoing aggregate by value arguments.
3997 SmallVector<CCValAssign, 16> ByValArgLocs;
3998 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3999 getTargetMachine(), ByValArgLocs, *DAG.getContext());
4001 // Reserve stack space for the allocations in CCInfo.
4002 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
4004 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal);
4006 // Size of the linkage area, parameter list area and the part of the local
4007 // space variable where copies of aggregates which are passed by value are
4009 unsigned NumBytes = CCByValInfo.getNextStackOffset();
4011 // Calculate by how many bytes the stack has to be adjusted in case of tail
4012 // call optimization.
4013 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4015 // Adjust the stack pointer for the new arguments...
4016 // These operations are automatically eliminated by the prolog/epilog pass
4017 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4019 SDValue CallSeqStart = Chain;
4021 // Load the return address and frame pointer so it can be moved somewhere else
4024 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
4027 // Set up a copy of the stack pointer for use loading and storing any
4028 // arguments that may not fit in the registers available for argument
4030 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4032 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4033 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4034 SmallVector<SDValue, 8> MemOpChains;
4036 bool seenFloatArg = false;
4037 // Walk the register/memloc assignments, inserting copies/loads.
4038 for (unsigned i = 0, j = 0, e = ArgLocs.size();
4041 CCValAssign &VA = ArgLocs[i];
4042 SDValue Arg = OutVals[i];
4043 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4045 if (Flags.isByVal()) {
4046 // Argument is an aggregate which is passed by value, thus we need to
4047 // create a copy of it in the local variable space of the current stack
4048 // frame (which is the stack frame of the caller) and pass the address of
4049 // this copy to the callee.
4050 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
4051 CCValAssign &ByValVA = ByValArgLocs[j++];
4052 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
4054 // Memory reserved in the local variable space of the callers stack frame.
4055 unsigned LocMemOffset = ByValVA.getLocMemOffset();
4057 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
4058 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
4060 // Create a copy of the argument in the local area of the current
4062 SDValue MemcpyCall =
4063 CreateCopyOfByValArgument(Arg, PtrOff,
4064 CallSeqStart.getNode()->getOperand(0),
4067 // This must go outside the CALLSEQ_START..END.
4068 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
4069 CallSeqStart.getNode()->getOperand(1),
4071 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
4072 NewCallSeqStart.getNode());
4073 Chain = CallSeqStart = NewCallSeqStart;
4075 // Pass the address of the aggregate copy on the stack either in a
4076 // physical register or in the parameter list area of the current stack
4077 // frame to the callee.
4081 if (VA.isRegLoc()) {
4082 if (Arg.getValueType() == MVT::i1)
4083 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Arg);
4085 seenFloatArg |= VA.getLocVT().isFloatingPoint();
4086 // Put argument in a physical register.
4087 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
4089 // Put argument in the parameter list area of the current stack frame.
4090 assert(VA.isMemLoc());
4091 unsigned LocMemOffset = VA.getLocMemOffset();
4094 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
4095 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
4097 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
4098 MachinePointerInfo(),
4101 // Calculate and remember argument location.
4102 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
4108 if (!MemOpChains.empty())
4109 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4111 // Build a sequence of copy-to-reg nodes chained together with token chain
4112 // and flag operands which copy the outgoing args into the appropriate regs.
4114 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4115 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4116 RegsToPass[i].second, InFlag);
4117 InFlag = Chain.getValue(1);
4120 // Set CR bit 6 to true if this is a vararg call with floating args passed in
4123 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
4124 SDValue Ops[] = { Chain, InFlag };
4126 Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
4127 dl, VTs, makeArrayRef(Ops, InFlag.getNode() ? 2 : 1));
4129 InFlag = Chain.getValue(1);
4133 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
4134 false, TailCallArguments);
4136 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4137 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4141 // Copy an argument into memory, being careful to do this outside the
4142 // call sequence for the call to which the argument belongs.
4144 PPCTargetLowering::createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
4145 SDValue CallSeqStart,
4146 ISD::ArgFlagsTy Flags,
4149 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
4150 CallSeqStart.getNode()->getOperand(0),
4152 // The MEMCPY must go outside the CALLSEQ_START..END.
4153 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
4154 CallSeqStart.getNode()->getOperand(1),
4156 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
4157 NewCallSeqStart.getNode());
4158 return NewCallSeqStart;
4162 PPCTargetLowering::LowerCall_64SVR4(SDValue Chain, SDValue Callee,
4163 CallingConv::ID CallConv, bool isVarArg,
4165 const SmallVectorImpl<ISD::OutputArg> &Outs,
4166 const SmallVectorImpl<SDValue> &OutVals,
4167 const SmallVectorImpl<ISD::InputArg> &Ins,
4168 SDLoc dl, SelectionDAG &DAG,
4169 SmallVectorImpl<SDValue> &InVals) const {
4171 bool isELFv2ABI = Subtarget.isELFv2ABI();
4172 bool isLittleEndian = Subtarget.isLittleEndian();
4173 unsigned NumOps = Outs.size();
4175 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4176 unsigned PtrByteSize = 8;
4178 MachineFunction &MF = DAG.getMachineFunction();
4180 // Mark this function as potentially containing a function that contains a
4181 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4182 // and restoring the callers stack pointer in this functions epilog. This is
4183 // done because by tail calling the called function might overwrite the value
4184 // in this function's (MF) stack pointer stack slot 0(SP).
4185 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4186 CallConv == CallingConv::Fast)
4187 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4189 // Count how many bytes are to be pushed on the stack, including the linkage
4190 // area, and parameter passing area. On ELFv1, the linkage area is 48 bytes
4191 // reserved space for [SP][CR][LR][2 x unused][TOC]; on ELFv2, the linkage
4192 // area is 32 bytes reserved space for [SP][CR][LR][TOC].
4193 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(true, false,
4195 unsigned NumBytes = LinkageSize;
4197 // Add up all the space actually used.
4198 for (unsigned i = 0; i != NumOps; ++i) {
4199 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4200 EVT ArgVT = Outs[i].VT;
4201 EVT OrigVT = Outs[i].ArgVT;
4203 /* Respect alignment of argument on the stack. */
4205 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
4206 NumBytes = ((NumBytes + Align - 1) / Align) * Align;
4208 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
4209 if (Flags.isInConsecutiveRegsLast())
4210 NumBytes = ((NumBytes + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4213 unsigned NumBytesActuallyUsed = NumBytes;
4215 // The prolog code of the callee may store up to 8 GPR argument registers to
4216 // the stack, allowing va_start to index over them in memory if its varargs.
4217 // Because we cannot tell if this is needed on the caller side, we have to
4218 // conservatively assume that it is needed. As such, make sure we have at
4219 // least enough stack space for the caller to store the 8 GPRs.
4220 // FIXME: On ELFv2, it may be unnecessary to allocate the parameter area.
4221 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
4223 // Tail call needs the stack to be aligned.
4224 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4225 CallConv == CallingConv::Fast)
4226 NumBytes = EnsureStackAlignment(MF.getTarget(), NumBytes);
4228 // Calculate by how many bytes the stack has to be adjusted in case of tail
4229 // call optimization.
4230 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4232 // To protect arguments on the stack from being clobbered in a tail call,
4233 // force all the loads to happen before doing any other lowering.
4235 Chain = DAG.getStackArgumentTokenFactor(Chain);
4237 // Adjust the stack pointer for the new arguments...
4238 // These operations are automatically eliminated by the prolog/epilog pass
4239 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4241 SDValue CallSeqStart = Chain;
4243 // Load the return address and frame pointer so it can be move somewhere else
4246 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4249 // Set up a copy of the stack pointer for use loading and storing any
4250 // arguments that may not fit in the registers available for argument
4252 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4254 // Figure out which arguments are going to go in registers, and which in
4255 // memory. Also, if this is a vararg function, floating point operations
4256 // must be stored to our stack, and loaded into integer regs as well, if
4257 // any integer regs are available for argument passing.
4258 unsigned ArgOffset = LinkageSize;
4259 unsigned GPR_idx, FPR_idx = 0, VR_idx = 0;
4261 static const MCPhysReg GPR[] = {
4262 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4263 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4265 static const MCPhysReg *FPR = GetFPR();
4267 static const MCPhysReg VR[] = {
4268 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4269 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4271 static const MCPhysReg VSRH[] = {
4272 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
4273 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
4276 const unsigned NumGPRs = array_lengthof(GPR);
4277 const unsigned NumFPRs = 13;
4278 const unsigned NumVRs = array_lengthof(VR);
4280 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4281 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4283 SmallVector<SDValue, 8> MemOpChains;
4284 for (unsigned i = 0; i != NumOps; ++i) {
4285 SDValue Arg = OutVals[i];
4286 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4287 EVT ArgVT = Outs[i].VT;
4288 EVT OrigVT = Outs[i].ArgVT;
4290 /* Respect alignment of argument on the stack. */
4292 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
4293 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
4295 /* Compute GPR index associated with argument offset. */
4296 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
4297 GPR_idx = std::min(GPR_idx, NumGPRs);
4299 // PtrOff will be used to store the current argument to the stack if a
4300 // register cannot be found for it.
4303 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4305 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4307 // Promote integers to 64-bit values.
4308 if (Arg.getValueType() == MVT::i32 || Arg.getValueType() == MVT::i1) {
4309 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4310 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4311 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4314 // FIXME memcpy is used way more than necessary. Correctness first.
4315 // Note: "by value" is code for passing a structure by value, not
4317 if (Flags.isByVal()) {
4318 // Note: Size includes alignment padding, so
4319 // struct x { short a; char b; }
4320 // will have Size = 4. With #pragma pack(1), it will have Size = 3.
4321 // These are the proper values we need for right-justifying the
4322 // aggregate in a parameter register.
4323 unsigned Size = Flags.getByValSize();
4325 // An empty aggregate parameter takes up no storage and no
4330 // All aggregates smaller than 8 bytes must be passed right-justified.
4331 if (Size==1 || Size==2 || Size==4) {
4332 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32);
4333 if (GPR_idx != NumGPRs) {
4334 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4335 MachinePointerInfo(), VT,
4337 MemOpChains.push_back(Load.getValue(1));
4338 RegsToPass.push_back(std::make_pair(GPR[GPR_idx], Load));
4340 ArgOffset += PtrByteSize;
4345 if (GPR_idx == NumGPRs && Size < 8) {
4346 SDValue AddPtr = PtrOff;
4347 if (!isLittleEndian) {
4348 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4349 PtrOff.getValueType());
4350 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4352 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4355 ArgOffset += PtrByteSize;
4358 // Copy entire object into memory. There are cases where gcc-generated
4359 // code assumes it is there, even if it could be put entirely into
4360 // registers. (This is not what the doc says.)
4362 // FIXME: The above statement is likely due to a misunderstanding of the
4363 // documents. All arguments must be copied into the parameter area BY
4364 // THE CALLEE in the event that the callee takes the address of any
4365 // formal argument. That has not yet been implemented. However, it is
4366 // reasonable to use the stack area as a staging area for the register
4369 // Skip this for small aggregates, as we will use the same slot for a
4370 // right-justified copy, below.
4372 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4376 // When a register is available, pass a small aggregate right-justified.
4377 if (Size < 8 && GPR_idx != NumGPRs) {
4378 // The easiest way to get this right-justified in a register
4379 // is to copy the structure into the rightmost portion of a
4380 // local variable slot, then load the whole slot into the
4382 // FIXME: The memcpy seems to produce pretty awful code for
4383 // small aggregates, particularly for packed ones.
4384 // FIXME: It would be preferable to use the slot in the
4385 // parameter save area instead of a new local variable.
4386 SDValue AddPtr = PtrOff;
4387 if (!isLittleEndian) {
4388 SDValue Const = DAG.getConstant(8 - Size, PtrOff.getValueType());
4389 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4391 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4395 // Load the slot into the register.
4396 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, PtrOff,
4397 MachinePointerInfo(),
4398 false, false, false, 0);
4399 MemOpChains.push_back(Load.getValue(1));
4400 RegsToPass.push_back(std::make_pair(GPR[GPR_idx], Load));
4402 // Done with this argument.
4403 ArgOffset += PtrByteSize;
4407 // For aggregates larger than PtrByteSize, copy the pieces of the
4408 // object that fit into registers from the parameter save area.
4409 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4410 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4411 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4412 if (GPR_idx != NumGPRs) {
4413 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4414 MachinePointerInfo(),
4415 false, false, false, 0);
4416 MemOpChains.push_back(Load.getValue(1));
4417 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4418 ArgOffset += PtrByteSize;
4420 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4427 switch (Arg.getSimpleValueType().SimpleTy) {
4428 default: llvm_unreachable("Unexpected ValueType for argument!");
4432 // These can be scalar arguments or elements of an integer array type
4433 // passed directly. Clang may use those instead of "byval" aggregate
4434 // types to avoid forcing arguments to memory unnecessarily.
4435 if (GPR_idx != NumGPRs) {
4436 RegsToPass.push_back(std::make_pair(GPR[GPR_idx], Arg));
4438 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4439 true, isTailCall, false, MemOpChains,
4440 TailCallArguments, dl);
4442 ArgOffset += PtrByteSize;
4446 // These can be scalar arguments or elements of a float array type
4447 // passed directly. The latter are used to implement ELFv2 homogenous
4448 // float aggregates.
4450 // Named arguments go into FPRs first, and once they overflow, the
4451 // remaining arguments go into GPRs and then the parameter save area.
4452 // Unnamed arguments for vararg functions always go to GPRs and
4453 // then the parameter save area. For now, put all arguments to vararg
4454 // routines always in both locations (FPR *and* GPR or stack slot).
4455 bool NeedGPROrStack = isVarArg || FPR_idx == NumFPRs;
4457 // First load the argument into the next available FPR.
4458 if (FPR_idx != NumFPRs)
4459 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4461 // Next, load the argument into GPR or stack slot if needed.
4462 if (!NeedGPROrStack)
4464 else if (GPR_idx != NumGPRs) {
4465 // In the non-vararg case, this can only ever happen in the
4466 // presence of f32 array types, since otherwise we never run
4467 // out of FPRs before running out of GPRs.
4470 // Double values are always passed in a single GPR.
4471 if (Arg.getValueType() != MVT::f32) {
4472 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
4474 // Non-array float values are extended and passed in a GPR.
4475 } else if (!Flags.isInConsecutiveRegs()) {
4476 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
4477 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal);
4479 // If we have an array of floats, we collect every odd element
4480 // together with its predecessor into one GPR.
4481 } else if (ArgOffset % PtrByteSize != 0) {
4483 Lo = DAG.getNode(ISD::BITCAST, dl, MVT::i32, OutVals[i - 1]);
4484 Hi = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
4485 if (!isLittleEndian)
4487 ArgVal = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
4489 // The final element, if even, goes into the first half of a GPR.
4490 } else if (Flags.isInConsecutiveRegsLast()) {
4491 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
4492 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal);
4493 if (!isLittleEndian)
4494 ArgVal = DAG.getNode(ISD::SHL, dl, MVT::i64, ArgVal,
4495 DAG.getConstant(32, MVT::i32));
4497 // Non-final even elements are skipped; they will be handled
4498 // together the with subsequent argument on the next go-around.
4502 if (ArgVal.getNode())
4503 RegsToPass.push_back(std::make_pair(GPR[GPR_idx], ArgVal));
4505 // Single-precision floating-point values are mapped to the
4506 // second (rightmost) word of the stack doubleword.
4507 if (Arg.getValueType() == MVT::f32 &&
4508 !isLittleEndian && !Flags.isInConsecutiveRegs()) {
4509 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4510 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4513 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4514 true, isTailCall, false, MemOpChains,
4515 TailCallArguments, dl);
4517 // When passing an array of floats, the array occupies consecutive
4518 // space in the argument area; only round up to the next doubleword
4519 // at the end of the array. Otherwise, each float takes 8 bytes.
4520 ArgOffset += (Arg.getValueType() == MVT::f32 &&
4521 Flags.isInConsecutiveRegs()) ? 4 : 8;
4522 if (Flags.isInConsecutiveRegsLast())
4523 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4532 // These can be scalar arguments or elements of a vector array type
4533 // passed directly. The latter are used to implement ELFv2 homogenous
4534 // vector aggregates.
4536 // For a varargs call, named arguments go into VRs or on the stack as
4537 // usual; unnamed arguments always go to the stack or the corresponding
4538 // GPRs when within range. For now, we always put the value in both
4539 // locations (or even all three).
4541 // We could elide this store in the case where the object fits
4542 // entirely in R registers. Maybe later.
4543 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4544 MachinePointerInfo(), false, false, 0);
4545 MemOpChains.push_back(Store);
4546 if (VR_idx != NumVRs) {
4547 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4548 MachinePointerInfo(),
4549 false, false, false, 0);
4550 MemOpChains.push_back(Load.getValue(1));
4552 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
4553 Arg.getSimpleValueType() == MVT::v2i64) ?
4554 VSRH[VR_idx] : VR[VR_idx];
4557 RegsToPass.push_back(std::make_pair(VReg, Load));
4560 for (unsigned i=0; i<16; i+=PtrByteSize) {
4561 if (GPR_idx == NumGPRs)
4563 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4564 DAG.getConstant(i, PtrVT));
4565 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4566 false, false, false, 0);
4567 MemOpChains.push_back(Load.getValue(1));
4568 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4573 // Non-varargs Altivec params go into VRs or on the stack.
4574 if (VR_idx != NumVRs) {
4575 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
4576 Arg.getSimpleValueType() == MVT::v2i64) ?
4577 VSRH[VR_idx] : VR[VR_idx];
4580 RegsToPass.push_back(std::make_pair(VReg, Arg));
4582 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4583 true, isTailCall, true, MemOpChains,
4584 TailCallArguments, dl);
4591 assert(NumBytesActuallyUsed == ArgOffset);
4592 (void)NumBytesActuallyUsed;
4594 if (!MemOpChains.empty())
4595 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4597 // Check if this is an indirect call (MTCTR/BCTRL).
4598 // See PrepareCall() for more information about calls through function
4599 // pointers in the 64-bit SVR4 ABI.
4601 !dyn_cast<GlobalAddressSDNode>(Callee) &&
4602 !dyn_cast<ExternalSymbolSDNode>(Callee)) {
4603 // Load r2 into a virtual register and store it to the TOC save area.
4604 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
4605 // TOC save area offset.
4606 unsigned TOCSaveOffset = PPCFrameLowering::getTOCSaveOffset(isELFv2ABI);
4607 SDValue PtrOff = DAG.getIntPtrConstant(TOCSaveOffset);
4608 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4609 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr, MachinePointerInfo(),
4611 // In the ELFv2 ABI, R12 must contain the address of an indirect callee.
4612 // This does not mean the MTCTR instruction must use R12; it's easier
4613 // to model this as an extra parameter, so do that.
4615 RegsToPass.push_back(std::make_pair((unsigned)PPC::X12, Callee));
4618 // Build a sequence of copy-to-reg nodes chained together with token chain
4619 // and flag operands which copy the outgoing args into the appropriate regs.
4621 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4622 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4623 RegsToPass[i].second, InFlag);
4624 InFlag = Chain.getValue(1);
4628 PrepareTailCall(DAG, InFlag, Chain, dl, true, SPDiff, NumBytes, LROp,
4629 FPOp, true, TailCallArguments);
4631 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4632 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4637 PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
4638 CallingConv::ID CallConv, bool isVarArg,
4640 const SmallVectorImpl<ISD::OutputArg> &Outs,
4641 const SmallVectorImpl<SDValue> &OutVals,
4642 const SmallVectorImpl<ISD::InputArg> &Ins,
4643 SDLoc dl, SelectionDAG &DAG,
4644 SmallVectorImpl<SDValue> &InVals) const {
4646 unsigned NumOps = Outs.size();
4648 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4649 bool isPPC64 = PtrVT == MVT::i64;
4650 unsigned PtrByteSize = isPPC64 ? 8 : 4;
4652 MachineFunction &MF = DAG.getMachineFunction();
4654 // Mark this function as potentially containing a function that contains a
4655 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4656 // and restoring the callers stack pointer in this functions epilog. This is
4657 // done because by tail calling the called function might overwrite the value
4658 // in this function's (MF) stack pointer stack slot 0(SP).
4659 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4660 CallConv == CallingConv::Fast)
4661 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4663 // Count how many bytes are to be pushed on the stack, including the linkage
4664 // area, and parameter passing area. We start with 24/48 bytes, which is
4665 // prereserved space for [SP][CR][LR][3 x unused].
4666 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(isPPC64, true,
4668 unsigned NumBytes = LinkageSize;
4670 // Add up all the space actually used.
4671 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
4672 // they all go in registers, but we must reserve stack space for them for
4673 // possible use by the caller. In varargs or 64-bit calls, parameters are
4674 // assigned stack space in order, with padding so Altivec parameters are
4676 unsigned nAltivecParamsAtEnd = 0;
4677 for (unsigned i = 0; i != NumOps; ++i) {
4678 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4679 EVT ArgVT = Outs[i].VT;
4680 // Varargs Altivec parameters are padded to a 16 byte boundary.
4681 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
4682 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
4683 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64) {
4684 if (!isVarArg && !isPPC64) {
4685 // Non-varargs Altivec parameters go after all the non-Altivec
4686 // parameters; handle those later so we know how much padding we need.
4687 nAltivecParamsAtEnd++;
4690 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
4691 NumBytes = ((NumBytes+15)/16)*16;
4693 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
4696 // Allow for Altivec parameters at the end, if needed.
4697 if (nAltivecParamsAtEnd) {
4698 NumBytes = ((NumBytes+15)/16)*16;
4699 NumBytes += 16*nAltivecParamsAtEnd;
4702 // The prolog code of the callee may store up to 8 GPR argument registers to
4703 // the stack, allowing va_start to index over them in memory if its varargs.
4704 // Because we cannot tell if this is needed on the caller side, we have to
4705 // conservatively assume that it is needed. As such, make sure we have at
4706 // least enough stack space for the caller to store the 8 GPRs.
4707 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
4709 // Tail call needs the stack to be aligned.
4710 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4711 CallConv == CallingConv::Fast)
4712 NumBytes = EnsureStackAlignment(MF.getTarget(), NumBytes);
4714 // Calculate by how many bytes the stack has to be adjusted in case of tail
4715 // call optimization.
4716 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4718 // To protect arguments on the stack from being clobbered in a tail call,
4719 // force all the loads to happen before doing any other lowering.
4721 Chain = DAG.getStackArgumentTokenFactor(Chain);
4723 // Adjust the stack pointer for the new arguments...
4724 // These operations are automatically eliminated by the prolog/epilog pass
4725 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4727 SDValue CallSeqStart = Chain;
4729 // Load the return address and frame pointer so it can be move somewhere else
4732 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4735 // Set up a copy of the stack pointer for use loading and storing any
4736 // arguments that may not fit in the registers available for argument
4740 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4742 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4744 // Figure out which arguments are going to go in registers, and which in
4745 // memory. Also, if this is a vararg function, floating point operations
4746 // must be stored to our stack, and loaded into integer regs as well, if
4747 // any integer regs are available for argument passing.
4748 unsigned ArgOffset = LinkageSize;
4749 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4751 static const MCPhysReg GPR_32[] = { // 32-bit registers.
4752 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
4753 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
4755 static const MCPhysReg GPR_64[] = { // 64-bit registers.
4756 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4757 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4759 static const MCPhysReg *FPR = GetFPR();
4761 static const MCPhysReg VR[] = {
4762 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4763 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4765 const unsigned NumGPRs = array_lengthof(GPR_32);
4766 const unsigned NumFPRs = 13;
4767 const unsigned NumVRs = array_lengthof(VR);
4769 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
4771 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4772 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4774 SmallVector<SDValue, 8> MemOpChains;
4775 for (unsigned i = 0; i != NumOps; ++i) {
4776 SDValue Arg = OutVals[i];
4777 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4779 // PtrOff will be used to store the current argument to the stack if a
4780 // register cannot be found for it.
4783 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4785 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4787 // On PPC64, promote integers to 64-bit values.
4788 if (isPPC64 && Arg.getValueType() == MVT::i32) {
4789 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4790 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4791 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4794 // FIXME memcpy is used way more than necessary. Correctness first.
4795 // Note: "by value" is code for passing a structure by value, not
4797 if (Flags.isByVal()) {
4798 unsigned Size = Flags.getByValSize();
4799 // Very small objects are passed right-justified. Everything else is
4800 // passed left-justified.
4801 if (Size==1 || Size==2) {
4802 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
4803 if (GPR_idx != NumGPRs) {
4804 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4805 MachinePointerInfo(), VT,
4807 MemOpChains.push_back(Load.getValue(1));
4808 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4810 ArgOffset += PtrByteSize;
4812 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4813 PtrOff.getValueType());
4814 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4815 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4818 ArgOffset += PtrByteSize;
4822 // Copy entire object into memory. There are cases where gcc-generated
4823 // code assumes it is there, even if it could be put entirely into
4824 // registers. (This is not what the doc says.)
4825 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4829 // For small aggregates (Darwin only) and aggregates >= PtrByteSize,
4830 // copy the pieces of the object that fit into registers from the
4831 // parameter save area.
4832 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4833 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4834 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4835 if (GPR_idx != NumGPRs) {
4836 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4837 MachinePointerInfo(),
4838 false, false, false, 0);
4839 MemOpChains.push_back(Load.getValue(1));
4840 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4841 ArgOffset += PtrByteSize;
4843 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4850 switch (Arg.getSimpleValueType().SimpleTy) {
4851 default: llvm_unreachable("Unexpected ValueType for argument!");
4855 if (GPR_idx != NumGPRs) {
4856 if (Arg.getValueType() == MVT::i1)
4857 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, PtrVT, Arg);
4859 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
4861 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4862 isPPC64, isTailCall, false, MemOpChains,
4863 TailCallArguments, dl);
4865 ArgOffset += PtrByteSize;
4869 if (FPR_idx != NumFPRs) {
4870 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4873 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4874 MachinePointerInfo(), false, false, 0);
4875 MemOpChains.push_back(Store);
4877 // Float varargs are always shadowed in available integer registers
4878 if (GPR_idx != NumGPRs) {
4879 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4880 MachinePointerInfo(), false, false,
4882 MemOpChains.push_back(Load.getValue(1));
4883 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4885 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
4886 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4887 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4888 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4889 MachinePointerInfo(),
4890 false, false, false, 0);
4891 MemOpChains.push_back(Load.getValue(1));
4892 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4895 // If we have any FPRs remaining, we may also have GPRs remaining.
4896 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
4898 if (GPR_idx != NumGPRs)
4900 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
4901 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
4905 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4906 isPPC64, isTailCall, false, MemOpChains,
4907 TailCallArguments, dl);
4911 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
4918 // These go aligned on the stack, or in the corresponding R registers
4919 // when within range. The Darwin PPC ABI doc claims they also go in
4920 // V registers; in fact gcc does this only for arguments that are
4921 // prototyped, not for those that match the ... We do it for all
4922 // arguments, seems to work.
4923 while (ArgOffset % 16 !=0) {
4924 ArgOffset += PtrByteSize;
4925 if (GPR_idx != NumGPRs)
4928 // We could elide this store in the case where the object fits
4929 // entirely in R registers. Maybe later.
4930 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4931 DAG.getConstant(ArgOffset, PtrVT));
4932 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4933 MachinePointerInfo(), false, false, 0);
4934 MemOpChains.push_back(Store);
4935 if (VR_idx != NumVRs) {
4936 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4937 MachinePointerInfo(),
4938 false, false, false, 0);
4939 MemOpChains.push_back(Load.getValue(1));
4940 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
4943 for (unsigned i=0; i<16; i+=PtrByteSize) {
4944 if (GPR_idx == NumGPRs)
4946 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4947 DAG.getConstant(i, PtrVT));
4948 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4949 false, false, false, 0);
4950 MemOpChains.push_back(Load.getValue(1));
4951 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4956 // Non-varargs Altivec params generally go in registers, but have
4957 // stack space allocated at the end.
4958 if (VR_idx != NumVRs) {
4959 // Doesn't have GPR space allocated.
4960 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
4961 } else if (nAltivecParamsAtEnd==0) {
4962 // We are emitting Altivec params in order.
4963 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4964 isPPC64, isTailCall, true, MemOpChains,
4965 TailCallArguments, dl);
4971 // If all Altivec parameters fit in registers, as they usually do,
4972 // they get stack space following the non-Altivec parameters. We
4973 // don't track this here because nobody below needs it.
4974 // If there are more Altivec parameters than fit in registers emit
4976 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
4978 // Offset is aligned; skip 1st 12 params which go in V registers.
4979 ArgOffset = ((ArgOffset+15)/16)*16;
4981 for (unsigned i = 0; i != NumOps; ++i) {
4982 SDValue Arg = OutVals[i];
4983 EVT ArgType = Outs[i].VT;
4984 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
4985 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
4988 // We are emitting Altivec params in order.
4989 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4990 isPPC64, isTailCall, true, MemOpChains,
4991 TailCallArguments, dl);
4998 if (!MemOpChains.empty())
4999 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
5001 // On Darwin, R12 must contain the address of an indirect callee. This does
5002 // not mean the MTCTR instruction must use R12; it's easier to model this as
5003 // an extra parameter, so do that.
5005 !dyn_cast<GlobalAddressSDNode>(Callee) &&
5006 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
5007 !isBLACompatibleAddress(Callee, DAG))
5008 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
5009 PPC::R12), Callee));
5011 // Build a sequence of copy-to-reg nodes chained together with token chain
5012 // and flag operands which copy the outgoing args into the appropriate regs.
5014 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
5015 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
5016 RegsToPass[i].second, InFlag);
5017 InFlag = Chain.getValue(1);
5021 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
5022 FPOp, true, TailCallArguments);
5024 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
5025 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
5030 PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
5031 MachineFunction &MF, bool isVarArg,
5032 const SmallVectorImpl<ISD::OutputArg> &Outs,
5033 LLVMContext &Context) const {
5034 SmallVector<CCValAssign, 16> RVLocs;
5035 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
5037 return CCInfo.CheckReturn(Outs, RetCC_PPC);
5041 PPCTargetLowering::LowerReturn(SDValue Chain,
5042 CallingConv::ID CallConv, bool isVarArg,
5043 const SmallVectorImpl<ISD::OutputArg> &Outs,
5044 const SmallVectorImpl<SDValue> &OutVals,
5045 SDLoc dl, SelectionDAG &DAG) const {
5047 SmallVector<CCValAssign, 16> RVLocs;
5048 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
5049 getTargetMachine(), RVLocs, *DAG.getContext());
5050 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
5053 SmallVector<SDValue, 4> RetOps(1, Chain);
5055 // Copy the result values into the output registers.
5056 for (unsigned i = 0; i != RVLocs.size(); ++i) {
5057 CCValAssign &VA = RVLocs[i];
5058 assert(VA.isRegLoc() && "Can only return in registers!");
5060 SDValue Arg = OutVals[i];
5062 switch (VA.getLocInfo()) {
5063 default: llvm_unreachable("Unknown loc info!");
5064 case CCValAssign::Full: break;
5065 case CCValAssign::AExt:
5066 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
5068 case CCValAssign::ZExt:
5069 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
5071 case CCValAssign::SExt:
5072 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
5076 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
5077 Flag = Chain.getValue(1);
5078 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
5081 RetOps[0] = Chain; // Update chain.
5083 // Add the flag if we have it.
5085 RetOps.push_back(Flag);
5087 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, RetOps);
5090 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
5091 const PPCSubtarget &Subtarget) const {
5092 // When we pop the dynamic allocation we need to restore the SP link.
5095 // Get the corect type for pointers.
5096 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5098 // Construct the stack pointer operand.
5099 bool isPPC64 = Subtarget.isPPC64();
5100 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
5101 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
5103 // Get the operands for the STACKRESTORE.
5104 SDValue Chain = Op.getOperand(0);
5105 SDValue SaveSP = Op.getOperand(1);
5107 // Load the old link SP.
5108 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr,
5109 MachinePointerInfo(),
5110 false, false, false, 0);
5112 // Restore the stack pointer.
5113 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
5115 // Store the old link SP.
5116 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(),
5123 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
5124 MachineFunction &MF = DAG.getMachineFunction();
5125 bool isPPC64 = Subtarget.isPPC64();
5126 bool isDarwinABI = Subtarget.isDarwinABI();
5127 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5129 // Get current frame pointer save index. The users of this index will be
5130 // primarily DYNALLOC instructions.
5131 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
5132 int RASI = FI->getReturnAddrSaveIndex();
5134 // If the frame pointer save index hasn't been defined yet.
5136 // Find out what the fix offset of the frame pointer save area.
5137 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
5138 // Allocate the frame index for frame pointer save area.
5139 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, true);
5141 FI->setReturnAddrSaveIndex(RASI);
5143 return DAG.getFrameIndex(RASI, PtrVT);
5147 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
5148 MachineFunction &MF = DAG.getMachineFunction();
5149 bool isPPC64 = Subtarget.isPPC64();
5150 bool isDarwinABI = Subtarget.isDarwinABI();
5151 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5153 // Get current frame pointer save index. The users of this index will be
5154 // primarily DYNALLOC instructions.
5155 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
5156 int FPSI = FI->getFramePointerSaveIndex();
5158 // If the frame pointer save index hasn't been defined yet.
5160 // Find out what the fix offset of the frame pointer save area.
5161 int FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64,
5164 // Allocate the frame index for frame pointer save area.
5165 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
5167 FI->setFramePointerSaveIndex(FPSI);
5169 return DAG.getFrameIndex(FPSI, PtrVT);
5172 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
5174 const PPCSubtarget &Subtarget) const {
5176 SDValue Chain = Op.getOperand(0);
5177 SDValue Size = Op.getOperand(1);
5180 // Get the corect type for pointers.
5181 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5183 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
5184 DAG.getConstant(0, PtrVT), Size);
5185 // Construct a node for the frame pointer save index.
5186 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
5187 // Build a DYNALLOC node.
5188 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
5189 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
5190 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops);
5193 SDValue PPCTargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
5194 SelectionDAG &DAG) const {
5196 return DAG.getNode(PPCISD::EH_SJLJ_SETJMP, DL,
5197 DAG.getVTList(MVT::i32, MVT::Other),
5198 Op.getOperand(0), Op.getOperand(1));
5201 SDValue PPCTargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
5202 SelectionDAG &DAG) const {
5204 return DAG.getNode(PPCISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
5205 Op.getOperand(0), Op.getOperand(1));
5208 SDValue PPCTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
5209 assert(Op.getValueType() == MVT::i1 &&
5210 "Custom lowering only for i1 loads");
5212 // First, load 8 bits into 32 bits, then truncate to 1 bit.
5215 LoadSDNode *LD = cast<LoadSDNode>(Op);
5217 SDValue Chain = LD->getChain();
5218 SDValue BasePtr = LD->getBasePtr();
5219 MachineMemOperand *MMO = LD->getMemOperand();
5221 SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, dl, getPointerTy(), Chain,
5222 BasePtr, MVT::i8, MMO);
5223 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewLD);
5225 SDValue Ops[] = { Result, SDValue(NewLD.getNode(), 1) };
5226 return DAG.getMergeValues(Ops, dl);
5229 SDValue PPCTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
5230 assert(Op.getOperand(1).getValueType() == MVT::i1 &&
5231 "Custom lowering only for i1 stores");
5233 // First, zero extend to 32 bits, then use a truncating store to 8 bits.
5236 StoreSDNode *ST = cast<StoreSDNode>(Op);
5238 SDValue Chain = ST->getChain();
5239 SDValue BasePtr = ST->getBasePtr();
5240 SDValue Value = ST->getValue();
5241 MachineMemOperand *MMO = ST->getMemOperand();
5243 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, getPointerTy(), Value);
5244 return DAG.getTruncStore(Chain, dl, Value, BasePtr, MVT::i8, MMO);
5247 // FIXME: Remove this once the ANDI glue bug is fixed:
5248 SDValue PPCTargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
5249 assert(Op.getValueType() == MVT::i1 &&
5250 "Custom lowering only for i1 results");
5253 return DAG.getNode(PPCISD::ANDIo_1_GT_BIT, DL, MVT::i1,
5257 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
5259 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
5260 // Not FP? Not a fsel.
5261 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
5262 !Op.getOperand(2).getValueType().isFloatingPoint())
5265 // We might be able to do better than this under some circumstances, but in
5266 // general, fsel-based lowering of select is a finite-math-only optimization.
5267 // For more information, see section F.3 of the 2.06 ISA specification.
5268 if (!DAG.getTarget().Options.NoInfsFPMath ||
5269 !DAG.getTarget().Options.NoNaNsFPMath)
5272 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5274 EVT ResVT = Op.getValueType();
5275 EVT CmpVT = Op.getOperand(0).getValueType();
5276 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5277 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
5280 // If the RHS of the comparison is a 0.0, we don't need to do the
5281 // subtraction at all.
5283 if (isFloatingPointZero(RHS))
5285 default: break; // SETUO etc aren't handled by fsel.
5289 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5290 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5291 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
5292 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
5293 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
5294 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5295 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV);
5298 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
5301 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5302 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5303 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
5306 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
5309 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5310 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5311 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5312 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
5317 default: break; // SETUO etc aren't handled by fsel.
5321 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5322 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5323 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5324 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5325 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
5326 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
5327 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5328 DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV);
5331 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5332 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5333 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5334 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
5337 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5338 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5339 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5340 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5343 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
5344 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5345 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5346 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
5349 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
5350 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5351 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5352 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5357 // FIXME: Split this code up when LegalizeDAGTypes lands.
5358 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
5360 assert(Op.getOperand(0).getValueType().isFloatingPoint());
5361 SDValue Src = Op.getOperand(0);
5362 if (Src.getValueType() == MVT::f32)
5363 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
5366 switch (Op.getSimpleValueType().SimpleTy) {
5367 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
5369 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ :
5370 (Subtarget.hasFPCVT() ? PPCISD::FCTIWUZ :
5375 assert((Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT()) &&
5376 "i64 FP_TO_UINT is supported only with FPCVT");
5377 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
5383 // Convert the FP value to an int value through memory.
5384 bool i32Stack = Op.getValueType() == MVT::i32 && Subtarget.hasSTFIWX() &&
5385 (Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT());
5386 SDValue FIPtr = DAG.CreateStackTemporary(i32Stack ? MVT::i32 : MVT::f64);
5387 int FI = cast<FrameIndexSDNode>(FIPtr)->getIndex();
5388 MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(FI);
5390 // Emit a store to the stack slot.
5393 MachineFunction &MF = DAG.getMachineFunction();
5394 MachineMemOperand *MMO =
5395 MF.getMachineMemOperand(MPI, MachineMemOperand::MOStore, 4, 4);
5396 SDValue Ops[] = { DAG.getEntryNode(), Tmp, FIPtr };
5397 Chain = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
5398 DAG.getVTList(MVT::Other), Ops, MVT::i32, MMO);
5400 Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr,
5401 MPI, false, false, 0);
5403 // Result is a load from the stack slot. If loading 4 bytes, make sure to
5405 if (Op.getValueType() == MVT::i32 && !i32Stack) {
5406 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
5407 DAG.getConstant(4, FIPtr.getValueType()));
5408 MPI = MachinePointerInfo();
5411 return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, MPI,
5412 false, false, false, 0);
5415 SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
5416 SelectionDAG &DAG) const {
5418 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
5419 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
5422 if (Op.getOperand(0).getValueType() == MVT::i1)
5423 return DAG.getNode(ISD::SELECT, dl, Op.getValueType(), Op.getOperand(0),
5424 DAG.getConstantFP(1.0, Op.getValueType()),
5425 DAG.getConstantFP(0.0, Op.getValueType()));
5427 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) &&
5428 "UINT_TO_FP is supported only with FPCVT");
5430 // If we have FCFIDS, then use it when converting to single-precision.
5431 // Otherwise, convert to double-precision and then round.
5432 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
5433 (Op.getOpcode() == ISD::UINT_TO_FP ?
5434 PPCISD::FCFIDUS : PPCISD::FCFIDS) :
5435 (Op.getOpcode() == ISD::UINT_TO_FP ?
5436 PPCISD::FCFIDU : PPCISD::FCFID);
5437 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
5438 MVT::f32 : MVT::f64;
5440 if (Op.getOperand(0).getValueType() == MVT::i64) {
5441 SDValue SINT = Op.getOperand(0);
5442 // When converting to single-precision, we actually need to convert
5443 // to double-precision first and then round to single-precision.
5444 // To avoid double-rounding effects during that operation, we have
5445 // to prepare the input operand. Bits that might be truncated when
5446 // converting to double-precision are replaced by a bit that won't
5447 // be lost at this stage, but is below the single-precision rounding
5450 // However, if -enable-unsafe-fp-math is in effect, accept double
5451 // rounding to avoid the extra overhead.
5452 if (Op.getValueType() == MVT::f32 &&
5453 !Subtarget.hasFPCVT() &&
5454 !DAG.getTarget().Options.UnsafeFPMath) {
5456 // Twiddle input to make sure the low 11 bits are zero. (If this
5457 // is the case, we are guaranteed the value will fit into the 53 bit
5458 // mantissa of an IEEE double-precision value without rounding.)
5459 // If any of those low 11 bits were not zero originally, make sure
5460 // bit 12 (value 2048) is set instead, so that the final rounding
5461 // to single-precision gets the correct result.
5462 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64,
5463 SINT, DAG.getConstant(2047, MVT::i64));
5464 Round = DAG.getNode(ISD::ADD, dl, MVT::i64,
5465 Round, DAG.getConstant(2047, MVT::i64));
5466 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT);
5467 Round = DAG.getNode(ISD::AND, dl, MVT::i64,
5468 Round, DAG.getConstant(-2048, MVT::i64));
5470 // However, we cannot use that value unconditionally: if the magnitude
5471 // of the input value is small, the bit-twiddling we did above might
5472 // end up visibly changing the output. Fortunately, in that case, we
5473 // don't need to twiddle bits since the original input will convert
5474 // exactly to double-precision floating-point already. Therefore,
5475 // construct a conditional to use the original value if the top 11
5476 // bits are all sign-bit copies, and use the rounded value computed
5478 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64,
5479 SINT, DAG.getConstant(53, MVT::i32));
5480 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64,
5481 Cond, DAG.getConstant(1, MVT::i64));
5482 Cond = DAG.getSetCC(dl, MVT::i32,
5483 Cond, DAG.getConstant(1, MVT::i64), ISD::SETUGT);
5485 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT);
5488 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT);
5489 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Bits);
5491 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
5492 FP = DAG.getNode(ISD::FP_ROUND, dl,
5493 MVT::f32, FP, DAG.getIntPtrConstant(0));
5497 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
5498 "Unhandled INT_TO_FP type in custom expander!");
5499 // Since we only generate this in 64-bit mode, we can take advantage of
5500 // 64-bit registers. In particular, sign extend the input value into the
5501 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
5502 // then lfd it and fcfid it.
5503 MachineFunction &MF = DAG.getMachineFunction();
5504 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
5505 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5508 if (Subtarget.hasLFIWAX() || Subtarget.hasFPCVT()) {
5509 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
5510 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5512 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), FIdx,
5513 MachinePointerInfo::getFixedStack(FrameIdx),
5516 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
5517 "Expected an i32 store");
5518 MachineMemOperand *MMO =
5519 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
5520 MachineMemOperand::MOLoad, 4, 4);
5521 SDValue Ops[] = { Store, FIdx };
5522 Ld = DAG.getMemIntrinsicNode(Op.getOpcode() == ISD::UINT_TO_FP ?
5523 PPCISD::LFIWZX : PPCISD::LFIWAX,
5524 dl, DAG.getVTList(MVT::f64, MVT::Other),
5525 Ops, MVT::i32, MMO);
5527 assert(Subtarget.isPPC64() &&
5528 "i32->FP without LFIWAX supported only on PPC64");
5530 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false);
5531 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5533 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64,
5536 // STD the extended value into the stack slot.
5537 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Ext64, FIdx,
5538 MachinePointerInfo::getFixedStack(FrameIdx),
5541 // Load the value as a double.
5542 Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx,
5543 MachinePointerInfo::getFixedStack(FrameIdx),
5544 false, false, false, 0);
5547 // FCFID it and return it.
5548 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Ld);
5549 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
5550 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
5554 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
5555 SelectionDAG &DAG) const {
5558 The rounding mode is in bits 30:31 of FPSR, and has the following
5565 FLT_ROUNDS, on the other hand, expects the following:
5572 To perform the conversion, we do:
5573 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
5576 MachineFunction &MF = DAG.getMachineFunction();
5577 EVT VT = Op.getValueType();
5578 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5580 // Save FP Control Word to register
5582 MVT::f64, // return register
5583 MVT::Glue // unused in this context
5585 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, None);
5587 // Save FP register to stack slot
5588 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
5589 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
5590 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
5591 StackSlot, MachinePointerInfo(), false, false,0);
5593 // Load FP Control Word from low 32 bits of stack slot.
5594 SDValue Four = DAG.getConstant(4, PtrVT);
5595 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
5596 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(),
5597 false, false, false, 0);
5599 // Transform as necessary
5601 DAG.getNode(ISD::AND, dl, MVT::i32,
5602 CWD, DAG.getConstant(3, MVT::i32));
5604 DAG.getNode(ISD::SRL, dl, MVT::i32,
5605 DAG.getNode(ISD::AND, dl, MVT::i32,
5606 DAG.getNode(ISD::XOR, dl, MVT::i32,
5607 CWD, DAG.getConstant(3, MVT::i32)),
5608 DAG.getConstant(3, MVT::i32)),
5609 DAG.getConstant(1, MVT::i32));
5612 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
5614 return DAG.getNode((VT.getSizeInBits() < 16 ?
5615 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
5618 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5619 EVT VT = Op.getValueType();
5620 unsigned BitWidth = VT.getSizeInBits();
5622 assert(Op.getNumOperands() == 3 &&
5623 VT == Op.getOperand(1).getValueType() &&
5626 // Expand into a bunch of logical ops. Note that these ops
5627 // depend on the PPC behavior for oversized shift amounts.
5628 SDValue Lo = Op.getOperand(0);
5629 SDValue Hi = Op.getOperand(1);
5630 SDValue Amt = Op.getOperand(2);
5631 EVT AmtVT = Amt.getValueType();
5633 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5634 DAG.getConstant(BitWidth, AmtVT), Amt);
5635 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
5636 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
5637 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
5638 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5639 DAG.getConstant(-BitWidth, AmtVT));
5640 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
5641 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5642 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
5643 SDValue OutOps[] = { OutLo, OutHi };
5644 return DAG.getMergeValues(OutOps, dl);
5647 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5648 EVT VT = Op.getValueType();
5650 unsigned BitWidth = VT.getSizeInBits();
5651 assert(Op.getNumOperands() == 3 &&
5652 VT == Op.getOperand(1).getValueType() &&
5655 // Expand into a bunch of logical ops. Note that these ops
5656 // depend on the PPC behavior for oversized shift amounts.
5657 SDValue Lo = Op.getOperand(0);
5658 SDValue Hi = Op.getOperand(1);
5659 SDValue Amt = Op.getOperand(2);
5660 EVT AmtVT = Amt.getValueType();
5662 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5663 DAG.getConstant(BitWidth, AmtVT), Amt);
5664 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5665 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5666 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5667 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5668 DAG.getConstant(-BitWidth, AmtVT));
5669 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
5670 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5671 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
5672 SDValue OutOps[] = { OutLo, OutHi };
5673 return DAG.getMergeValues(OutOps, dl);
5676 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
5678 EVT VT = Op.getValueType();
5679 unsigned BitWidth = VT.getSizeInBits();
5680 assert(Op.getNumOperands() == 3 &&
5681 VT == Op.getOperand(1).getValueType() &&
5684 // Expand into a bunch of logical ops, followed by a select_cc.
5685 SDValue Lo = Op.getOperand(0);
5686 SDValue Hi = Op.getOperand(1);
5687 SDValue Amt = Op.getOperand(2);
5688 EVT AmtVT = Amt.getValueType();
5690 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5691 DAG.getConstant(BitWidth, AmtVT), Amt);
5692 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5693 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5694 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5695 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5696 DAG.getConstant(-BitWidth, AmtVT));
5697 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
5698 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
5699 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT),
5700 Tmp4, Tmp6, ISD::SETLE);
5701 SDValue OutOps[] = { OutLo, OutHi };
5702 return DAG.getMergeValues(OutOps, dl);
5705 //===----------------------------------------------------------------------===//
5706 // Vector related lowering.
5709 /// BuildSplatI - Build a canonical splati of Val with an element size of
5710 /// SplatSize. Cast the result to VT.
5711 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
5712 SelectionDAG &DAG, SDLoc dl) {
5713 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
5715 static const EVT VTys[] = { // canonical VT to use for each size.
5716 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
5719 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
5721 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
5725 EVT CanonicalVT = VTys[SplatSize-1];
5727 // Build a canonical splat for this value.
5728 SDValue Elt = DAG.getConstant(Val, MVT::i32);
5729 SmallVector<SDValue, 8> Ops;
5730 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
5731 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, Ops);
5732 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res);
5735 /// BuildIntrinsicOp - Return a unary operator intrinsic node with the
5736 /// specified intrinsic ID.
5737 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op,
5738 SelectionDAG &DAG, SDLoc dl,
5739 EVT DestVT = MVT::Other) {
5740 if (DestVT == MVT::Other) DestVT = Op.getValueType();
5741 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5742 DAG.getConstant(IID, MVT::i32), Op);
5745 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
5746 /// specified intrinsic ID.
5747 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
5748 SelectionDAG &DAG, SDLoc dl,
5749 EVT DestVT = MVT::Other) {
5750 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
5751 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5752 DAG.getConstant(IID, MVT::i32), LHS, RHS);
5755 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
5756 /// specified intrinsic ID.
5757 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
5758 SDValue Op2, SelectionDAG &DAG,
5759 SDLoc dl, EVT DestVT = MVT::Other) {
5760 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
5761 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5762 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
5766 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
5767 /// amount. The result has the specified value type.
5768 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
5769 EVT VT, SelectionDAG &DAG, SDLoc dl) {
5770 // Force LHS/RHS to be the right type.
5771 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
5772 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
5775 for (unsigned i = 0; i != 16; ++i)
5777 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
5778 return DAG.getNode(ISD::BITCAST, dl, VT, T);
5781 // If this is a case we can't handle, return null and let the default
5782 // expansion code take care of it. If we CAN select this case, and if it
5783 // selects to a single instruction, return Op. Otherwise, if we can codegen
5784 // this case more efficiently than a constant pool load, lower it to the
5785 // sequence of ops that should be used.
5786 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
5787 SelectionDAG &DAG) const {
5789 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
5790 assert(BVN && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
5792 // Check if this is a splat of a constant value.
5793 APInt APSplatBits, APSplatUndef;
5794 unsigned SplatBitSize;
5796 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
5797 HasAnyUndefs, 0, true) || SplatBitSize > 32)
5800 unsigned SplatBits = APSplatBits.getZExtValue();
5801 unsigned SplatUndef = APSplatUndef.getZExtValue();
5802 unsigned SplatSize = SplatBitSize / 8;
5804 // First, handle single instruction cases.
5807 if (SplatBits == 0) {
5808 // Canonicalize all zero vectors to be v4i32.
5809 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
5810 SDValue Z = DAG.getConstant(0, MVT::i32);
5811 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
5812 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
5817 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
5818 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
5820 if (SextVal >= -16 && SextVal <= 15)
5821 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
5824 // Two instruction sequences.
5826 // If this value is in the range [-32,30] and is even, use:
5827 // VSPLTI[bhw](val/2) + VSPLTI[bhw](val/2)
5828 // If this value is in the range [17,31] and is odd, use:
5829 // VSPLTI[bhw](val-16) - VSPLTI[bhw](-16)
5830 // If this value is in the range [-31,-17] and is odd, use:
5831 // VSPLTI[bhw](val+16) + VSPLTI[bhw](-16)
5832 // Note the last two are three-instruction sequences.
5833 if (SextVal >= -32 && SextVal <= 31) {
5834 // To avoid having these optimizations undone by constant folding,
5835 // we convert to a pseudo that will be expanded later into one of
5837 SDValue Elt = DAG.getConstant(SextVal, MVT::i32);
5838 EVT VT = (SplatSize == 1 ? MVT::v16i8 :
5839 (SplatSize == 2 ? MVT::v8i16 : MVT::v4i32));
5840 SDValue EltSize = DAG.getConstant(SplatSize, MVT::i32);
5841 SDValue RetVal = DAG.getNode(PPCISD::VADD_SPLAT, dl, VT, Elt, EltSize);
5842 if (VT == Op.getValueType())
5845 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), RetVal);
5848 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
5849 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
5851 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
5852 // Make -1 and vspltisw -1:
5853 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
5855 // Make the VSLW intrinsic, computing 0x8000_0000.
5856 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
5859 // xor by OnesV to invert it.
5860 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
5861 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5864 // The remaining cases assume either big endian element order or
5865 // a splat-size that equates to the element size of the vector
5866 // to be built. An example that doesn't work for little endian is
5867 // {0, -1, 0, -1, 0, -1, 0, -1} which has a splat size of 32 bits
5868 // and a vector element size of 16 bits. The code below will
5869 // produce the vector in big endian element order, which for little
5870 // endian is {-1, 0, -1, 0, -1, 0, -1, 0}.
5872 // For now, just avoid these optimizations in that case.
5873 // FIXME: Develop correct optimizations for LE with mismatched
5874 // splat and element sizes.
5876 if (Subtarget.isLittleEndian() &&
5877 SplatSize != Op.getValueType().getVectorElementType().getSizeInBits())
5880 // Check to see if this is a wide variety of vsplti*, binop self cases.
5881 static const signed char SplatCsts[] = {
5882 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
5883 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
5886 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
5887 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
5888 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
5889 int i = SplatCsts[idx];
5891 // Figure out what shift amount will be used by altivec if shifted by i in
5893 unsigned TypeShiftAmt = i & (SplatBitSize-1);
5895 // vsplti + shl self.
5896 if (SextVal == (int)((unsigned)i << TypeShiftAmt)) {
5897 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5898 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5899 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
5900 Intrinsic::ppc_altivec_vslw
5902 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5903 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5906 // vsplti + srl self.
5907 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5908 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5909 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5910 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
5911 Intrinsic::ppc_altivec_vsrw
5913 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5914 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5917 // vsplti + sra self.
5918 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5919 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5920 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5921 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
5922 Intrinsic::ppc_altivec_vsraw
5924 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5925 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5928 // vsplti + rol self.
5929 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
5930 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
5931 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5932 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5933 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
5934 Intrinsic::ppc_altivec_vrlw
5936 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5937 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5940 // t = vsplti c, result = vsldoi t, t, 1
5941 if (SextVal == (int)(((unsigned)i << 8) | (i < 0 ? 0xFF : 0))) {
5942 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5943 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
5945 // t = vsplti c, result = vsldoi t, t, 2
5946 if (SextVal == (int)(((unsigned)i << 16) | (i < 0 ? 0xFFFF : 0))) {
5947 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5948 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
5950 // t = vsplti c, result = vsldoi t, t, 3
5951 if (SextVal == (int)(((unsigned)i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
5952 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5953 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
5960 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
5961 /// the specified operations to build the shuffle.
5962 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
5963 SDValue RHS, SelectionDAG &DAG,
5965 unsigned OpNum = (PFEntry >> 26) & 0x0F;
5966 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
5967 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
5970 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
5982 if (OpNum == OP_COPY) {
5983 if (LHSID == (1*9+2)*9+3) return LHS;
5984 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
5988 SDValue OpLHS, OpRHS;
5989 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
5990 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
5994 default: llvm_unreachable("Unknown i32 permute!");
5996 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
5997 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
5998 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
5999 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
6002 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
6003 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
6004 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
6005 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
6008 for (unsigned i = 0; i != 16; ++i)
6009 ShufIdxs[i] = (i&3)+0;
6012 for (unsigned i = 0; i != 16; ++i)
6013 ShufIdxs[i] = (i&3)+4;
6016 for (unsigned i = 0; i != 16; ++i)
6017 ShufIdxs[i] = (i&3)+8;
6020 for (unsigned i = 0; i != 16; ++i)
6021 ShufIdxs[i] = (i&3)+12;
6024 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
6026 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
6028 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
6030 EVT VT = OpLHS.getValueType();
6031 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
6032 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
6033 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
6034 return DAG.getNode(ISD::BITCAST, dl, VT, T);
6037 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
6038 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
6039 /// return the code it can be lowered into. Worst case, it can always be
6040 /// lowered into a vperm.
6041 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
6042 SelectionDAG &DAG) const {
6044 SDValue V1 = Op.getOperand(0);
6045 SDValue V2 = Op.getOperand(1);
6046 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6047 EVT VT = Op.getValueType();
6048 bool isLittleEndian = Subtarget.isLittleEndian();
6050 // Cases that are handled by instructions that take permute immediates
6051 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
6052 // selected by the instruction selector.
6053 if (V2.getOpcode() == ISD::UNDEF) {
6054 if (PPC::isSplatShuffleMask(SVOp, 1) ||
6055 PPC::isSplatShuffleMask(SVOp, 2) ||
6056 PPC::isSplatShuffleMask(SVOp, 4) ||
6057 PPC::isVPKUWUMShuffleMask(SVOp, 1, DAG) ||
6058 PPC::isVPKUHUMShuffleMask(SVOp, 1, DAG) ||
6059 PPC::isVSLDOIShuffleMask(SVOp, 1, DAG) != -1 ||
6060 PPC::isVMRGLShuffleMask(SVOp, 1, 1, DAG) ||
6061 PPC::isVMRGLShuffleMask(SVOp, 2, 1, DAG) ||
6062 PPC::isVMRGLShuffleMask(SVOp, 4, 1, DAG) ||
6063 PPC::isVMRGHShuffleMask(SVOp, 1, 1, DAG) ||
6064 PPC::isVMRGHShuffleMask(SVOp, 2, 1, DAG) ||
6065 PPC::isVMRGHShuffleMask(SVOp, 4, 1, DAG)) {
6070 // Altivec has a variety of "shuffle immediates" that take two vector inputs
6071 // and produce a fixed permutation. If any of these match, do not lower to
6073 unsigned int ShuffleKind = isLittleEndian ? 2 : 0;
6074 if (PPC::isVPKUWUMShuffleMask(SVOp, ShuffleKind, DAG) ||
6075 PPC::isVPKUHUMShuffleMask(SVOp, ShuffleKind, DAG) ||
6076 PPC::isVSLDOIShuffleMask(SVOp, ShuffleKind, DAG) != -1 ||
6077 PPC::isVMRGLShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
6078 PPC::isVMRGLShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
6079 PPC::isVMRGLShuffleMask(SVOp, 4, ShuffleKind, DAG) ||
6080 PPC::isVMRGHShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
6081 PPC::isVMRGHShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
6082 PPC::isVMRGHShuffleMask(SVOp, 4, ShuffleKind, DAG))
6085 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
6086 // perfect shuffle table to emit an optimal matching sequence.
6087 ArrayRef<int> PermMask = SVOp->getMask();
6089 unsigned PFIndexes[4];
6090 bool isFourElementShuffle = true;
6091 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
6092 unsigned EltNo = 8; // Start out undef.
6093 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
6094 if (PermMask[i*4+j] < 0)
6095 continue; // Undef, ignore it.
6097 unsigned ByteSource = PermMask[i*4+j];
6098 if ((ByteSource & 3) != j) {
6099 isFourElementShuffle = false;
6104 EltNo = ByteSource/4;
6105 } else if (EltNo != ByteSource/4) {
6106 isFourElementShuffle = false;
6110 PFIndexes[i] = EltNo;
6113 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
6114 // perfect shuffle vector to determine if it is cost effective to do this as
6115 // discrete instructions, or whether we should use a vperm.
6116 // For now, we skip this for little endian until such time as we have a
6117 // little-endian perfect shuffle table.
6118 if (isFourElementShuffle && !isLittleEndian) {
6119 // Compute the index in the perfect shuffle table.
6120 unsigned PFTableIndex =
6121 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
6123 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
6124 unsigned Cost = (PFEntry >> 30);
6126 // Determining when to avoid vperm is tricky. Many things affect the cost
6127 // of vperm, particularly how many times the perm mask needs to be computed.
6128 // For example, if the perm mask can be hoisted out of a loop or is already
6129 // used (perhaps because there are multiple permutes with the same shuffle
6130 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
6131 // the loop requires an extra register.
6133 // As a compromise, we only emit discrete instructions if the shuffle can be
6134 // generated in 3 or fewer operations. When we have loop information
6135 // available, if this block is within a loop, we should avoid using vperm
6136 // for 3-operation perms and use a constant pool load instead.
6138 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
6141 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
6142 // vector that will get spilled to the constant pool.
6143 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
6145 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
6146 // that it is in input element units, not in bytes. Convert now.
6148 // For little endian, the order of the input vectors is reversed, and
6149 // the permutation mask is complemented with respect to 31. This is
6150 // necessary to produce proper semantics with the big-endian-biased vperm
6152 EVT EltVT = V1.getValueType().getVectorElementType();
6153 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
6155 SmallVector<SDValue, 16> ResultMask;
6156 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
6157 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
6159 for (unsigned j = 0; j != BytesPerElement; ++j)
6161 ResultMask.push_back(DAG.getConstant(31 - (SrcElt*BytesPerElement+j),
6164 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
6168 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
6171 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
6174 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
6178 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
6179 /// altivec comparison. If it is, return true and fill in Opc/isDot with
6180 /// information about the intrinsic.
6181 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
6183 unsigned IntrinsicID =
6184 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
6187 switch (IntrinsicID) {
6188 default: return false;
6189 // Comparison predicates.
6190 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
6191 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
6192 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
6193 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
6194 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
6195 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
6196 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
6197 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
6198 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
6199 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
6200 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
6201 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
6202 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
6204 // Normal Comparisons.
6205 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
6206 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
6207 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
6208 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
6209 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
6210 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
6211 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
6212 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
6213 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
6214 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
6215 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
6216 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
6217 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
6222 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
6223 /// lower, do it, otherwise return null.
6224 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
6225 SelectionDAG &DAG) const {
6226 // If this is a lowered altivec predicate compare, CompareOpc is set to the
6227 // opcode number of the comparison.
6231 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
6232 return SDValue(); // Don't custom lower most intrinsics.
6234 // If this is a non-dot comparison, make the VCMP node and we are done.
6236 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
6237 Op.getOperand(1), Op.getOperand(2),
6238 DAG.getConstant(CompareOpc, MVT::i32));
6239 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
6242 // Create the PPCISD altivec 'dot' comparison node.
6244 Op.getOperand(2), // LHS
6245 Op.getOperand(3), // RHS
6246 DAG.getConstant(CompareOpc, MVT::i32)
6248 EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue };
6249 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
6251 // Now that we have the comparison, emit a copy from the CR to a GPR.
6252 // This is flagged to the above dot comparison.
6253 SDValue Flags = DAG.getNode(PPCISD::MFOCRF, dl, MVT::i32,
6254 DAG.getRegister(PPC::CR6, MVT::i32),
6255 CompNode.getValue(1));
6257 // Unpack the result based on how the target uses it.
6258 unsigned BitNo; // Bit # of CR6.
6259 bool InvertBit; // Invert result?
6260 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
6261 default: // Can't happen, don't crash on invalid number though.
6262 case 0: // Return the value of the EQ bit of CR6.
6263 BitNo = 0; InvertBit = false;
6265 case 1: // Return the inverted value of the EQ bit of CR6.
6266 BitNo = 0; InvertBit = true;
6268 case 2: // Return the value of the LT bit of CR6.
6269 BitNo = 2; InvertBit = false;
6271 case 3: // Return the inverted value of the LT bit of CR6.
6272 BitNo = 2; InvertBit = true;
6276 // Shift the bit into the low position.
6277 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
6278 DAG.getConstant(8-(3-BitNo), MVT::i32));
6280 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
6281 DAG.getConstant(1, MVT::i32));
6283 // If we are supposed to, toggle the bit.
6285 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
6286 DAG.getConstant(1, MVT::i32));
6290 SDValue PPCTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
6291 SelectionDAG &DAG) const {
6293 // For v2i64 (VSX), we can pattern patch the v2i32 case (using fp <-> int
6294 // instructions), but for smaller types, we need to first extend up to v2i32
6295 // before doing going farther.
6296 if (Op.getValueType() == MVT::v2i64) {
6297 EVT ExtVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
6298 if (ExtVT != MVT::v2i32) {
6299 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0));
6300 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32, Op,
6301 DAG.getValueType(EVT::getVectorVT(*DAG.getContext(),
6302 ExtVT.getVectorElementType(), 4)));
6303 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Op);
6304 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v2i64, Op,
6305 DAG.getValueType(MVT::v2i32));
6314 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
6315 SelectionDAG &DAG) const {
6317 // Create a stack slot that is 16-byte aligned.
6318 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
6319 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
6320 EVT PtrVT = getPointerTy();
6321 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6323 // Store the input value into Value#0 of the stack slot.
6324 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
6325 Op.getOperand(0), FIdx, MachinePointerInfo(),
6328 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(),
6329 false, false, false, 0);
6332 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
6334 if (Op.getValueType() == MVT::v4i32) {
6335 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6337 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
6338 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
6340 SDValue RHSSwap = // = vrlw RHS, 16
6341 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
6343 // Shrinkify inputs to v8i16.
6344 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
6345 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
6346 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
6348 // Low parts multiplied together, generating 32-bit results (we ignore the
6350 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
6351 LHS, RHS, DAG, dl, MVT::v4i32);
6353 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
6354 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
6355 // Shift the high parts up 16 bits.
6356 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
6358 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
6359 } else if (Op.getValueType() == MVT::v8i16) {
6360 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6362 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
6364 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
6365 LHS, RHS, Zero, DAG, dl);
6366 } else if (Op.getValueType() == MVT::v16i8) {
6367 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6368 bool isLittleEndian = Subtarget.isLittleEndian();
6370 // Multiply the even 8-bit parts, producing 16-bit sums.
6371 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
6372 LHS, RHS, DAG, dl, MVT::v8i16);
6373 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
6375 // Multiply the odd 8-bit parts, producing 16-bit sums.
6376 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
6377 LHS, RHS, DAG, dl, MVT::v8i16);
6378 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
6380 // Merge the results together. Because vmuleub and vmuloub are
6381 // instructions with a big-endian bias, we must reverse the
6382 // element numbering and reverse the meaning of "odd" and "even"
6383 // when generating little endian code.
6385 for (unsigned i = 0; i != 8; ++i) {
6386 if (isLittleEndian) {
6388 Ops[i*2+1] = 2*i+16;
6391 Ops[i*2+1] = 2*i+1+16;
6395 return DAG.getVectorShuffle(MVT::v16i8, dl, OddParts, EvenParts, Ops);
6397 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
6399 llvm_unreachable("Unknown mul to lower!");
6403 /// LowerOperation - Provide custom lowering hooks for some operations.
6405 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6406 switch (Op.getOpcode()) {
6407 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
6408 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
6409 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
6410 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
6411 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
6412 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
6413 case ISD::SETCC: return LowerSETCC(Op, DAG);
6414 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
6415 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
6417 return LowerVASTART(Op, DAG, Subtarget);
6420 return LowerVAARG(Op, DAG, Subtarget);
6423 return LowerVACOPY(Op, DAG, Subtarget);
6425 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, Subtarget);
6426 case ISD::DYNAMIC_STACKALLOC:
6427 return LowerDYNAMIC_STACKALLOC(Op, DAG, Subtarget);
6429 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
6430 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
6432 case ISD::LOAD: return LowerLOAD(Op, DAG);
6433 case ISD::STORE: return LowerSTORE(Op, DAG);
6434 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
6435 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
6436 case ISD::FP_TO_UINT:
6437 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
6439 case ISD::UINT_TO_FP:
6440 case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
6441 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
6443 // Lower 64-bit shifts.
6444 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
6445 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
6446 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
6448 // Vector-related lowering.
6449 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
6450 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
6451 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
6452 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
6453 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
6454 case ISD::MUL: return LowerMUL(Op, DAG);
6456 // For counter-based loop handling.
6457 case ISD::INTRINSIC_W_CHAIN: return SDValue();
6459 // Frame & Return address.
6460 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
6461 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
6465 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
6466 SmallVectorImpl<SDValue>&Results,
6467 SelectionDAG &DAG) const {
6468 const TargetMachine &TM = getTargetMachine();
6470 switch (N->getOpcode()) {
6472 llvm_unreachable("Do not know how to custom type legalize this operation!");
6473 case ISD::INTRINSIC_W_CHAIN: {
6474 if (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() !=
6475 Intrinsic::ppc_is_decremented_ctr_nonzero)
6478 assert(N->getValueType(0) == MVT::i1 &&
6479 "Unexpected result type for CTR decrement intrinsic");
6480 EVT SVT = getSetCCResultType(*DAG.getContext(), N->getValueType(0));
6481 SDVTList VTs = DAG.getVTList(SVT, MVT::Other);
6482 SDValue NewInt = DAG.getNode(N->getOpcode(), dl, VTs, N->getOperand(0),
6485 Results.push_back(NewInt);
6486 Results.push_back(NewInt.getValue(1));
6490 if (!TM.getSubtarget<PPCSubtarget>().isSVR4ABI()
6491 || TM.getSubtarget<PPCSubtarget>().isPPC64())
6494 EVT VT = N->getValueType(0);
6496 if (VT == MVT::i64) {
6497 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, Subtarget);
6499 Results.push_back(NewNode);
6500 Results.push_back(NewNode.getValue(1));
6504 case ISD::FP_ROUND_INREG: {
6505 assert(N->getValueType(0) == MVT::ppcf128);
6506 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
6507 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
6508 MVT::f64, N->getOperand(0),
6509 DAG.getIntPtrConstant(0));
6510 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
6511 MVT::f64, N->getOperand(0),
6512 DAG.getIntPtrConstant(1));
6514 // Add the two halves of the long double in round-to-zero mode.
6515 SDValue FPreg = DAG.getNode(PPCISD::FADDRTZ, dl, MVT::f64, Lo, Hi);
6517 // We know the low half is about to be thrown away, so just use something
6519 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
6523 case ISD::FP_TO_SINT:
6524 // LowerFP_TO_INT() can only handle f32 and f64.
6525 if (N->getOperand(0).getValueType() == MVT::ppcf128)
6527 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
6533 //===----------------------------------------------------------------------===//
6534 // Other Lowering Code
6535 //===----------------------------------------------------------------------===//
6538 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
6539 bool is64bit, unsigned BinOpcode) const {
6540 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
6541 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6543 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6544 MachineFunction *F = BB->getParent();
6545 MachineFunction::iterator It = BB;
6548 unsigned dest = MI->getOperand(0).getReg();
6549 unsigned ptrA = MI->getOperand(1).getReg();
6550 unsigned ptrB = MI->getOperand(2).getReg();
6551 unsigned incr = MI->getOperand(3).getReg();
6552 DebugLoc dl = MI->getDebugLoc();
6554 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
6555 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6556 F->insert(It, loopMBB);
6557 F->insert(It, exitMBB);
6558 exitMBB->splice(exitMBB->begin(), BB,
6559 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6560 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6562 MachineRegisterInfo &RegInfo = F->getRegInfo();
6563 unsigned TmpReg = (!BinOpcode) ? incr :
6564 RegInfo.createVirtualRegister(
6565 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6566 (const TargetRegisterClass *) &PPC::GPRCRegClass);
6570 // fallthrough --> loopMBB
6571 BB->addSuccessor(loopMBB);
6574 // l[wd]arx dest, ptr
6575 // add r0, dest, incr
6576 // st[wd]cx. r0, ptr
6578 // fallthrough --> exitMBB
6580 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
6581 .addReg(ptrA).addReg(ptrB);
6583 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
6584 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6585 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
6586 BuildMI(BB, dl, TII->get(PPC::BCC))
6587 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
6588 BB->addSuccessor(loopMBB);
6589 BB->addSuccessor(exitMBB);
6598 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
6599 MachineBasicBlock *BB,
6600 bool is8bit, // operation
6601 unsigned BinOpcode) const {
6602 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
6603 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6604 // In 64 bit mode we have to use 64 bits for addresses, even though the
6605 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
6606 // registers without caring whether they're 32 or 64, but here we're
6607 // doing actual arithmetic on the addresses.
6608 bool is64bit = Subtarget.isPPC64();
6609 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
6611 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6612 MachineFunction *F = BB->getParent();
6613 MachineFunction::iterator It = BB;
6616 unsigned dest = MI->getOperand(0).getReg();
6617 unsigned ptrA = MI->getOperand(1).getReg();
6618 unsigned ptrB = MI->getOperand(2).getReg();
6619 unsigned incr = MI->getOperand(3).getReg();
6620 DebugLoc dl = MI->getDebugLoc();
6622 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
6623 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6624 F->insert(It, loopMBB);
6625 F->insert(It, exitMBB);
6626 exitMBB->splice(exitMBB->begin(), BB,
6627 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6628 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6630 MachineRegisterInfo &RegInfo = F->getRegInfo();
6631 const TargetRegisterClass *RC =
6632 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6633 (const TargetRegisterClass *) &PPC::GPRCRegClass;
6634 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
6635 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
6636 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
6637 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
6638 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
6639 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
6640 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
6641 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
6642 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
6643 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
6644 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
6646 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
6650 // fallthrough --> loopMBB
6651 BB->addSuccessor(loopMBB);
6653 // The 4-byte load must be aligned, while a char or short may be
6654 // anywhere in the word. Hence all this nasty bookkeeping code.
6655 // add ptr1, ptrA, ptrB [copy if ptrA==0]
6656 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
6657 // xori shift, shift1, 24 [16]
6658 // rlwinm ptr, ptr1, 0, 0, 29
6659 // slw incr2, incr, shift
6660 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
6661 // slw mask, mask2, shift
6663 // lwarx tmpDest, ptr
6664 // add tmp, tmpDest, incr2
6665 // andc tmp2, tmpDest, mask
6666 // and tmp3, tmp, mask
6667 // or tmp4, tmp3, tmp2
6670 // fallthrough --> exitMBB
6671 // srw dest, tmpDest, shift
6672 if (ptrA != ZeroReg) {
6673 Ptr1Reg = RegInfo.createVirtualRegister(RC);
6674 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
6675 .addReg(ptrA).addReg(ptrB);
6679 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
6680 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
6681 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
6682 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
6684 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
6685 .addReg(Ptr1Reg).addImm(0).addImm(61);
6687 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
6688 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
6689 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
6690 .addReg(incr).addReg(ShiftReg);
6692 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
6694 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
6695 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
6697 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
6698 .addReg(Mask2Reg).addReg(ShiftReg);
6701 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
6702 .addReg(ZeroReg).addReg(PtrReg);
6704 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
6705 .addReg(Incr2Reg).addReg(TmpDestReg);
6706 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
6707 .addReg(TmpDestReg).addReg(MaskReg);
6708 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
6709 .addReg(TmpReg).addReg(MaskReg);
6710 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
6711 .addReg(Tmp3Reg).addReg(Tmp2Reg);
6712 BuildMI(BB, dl, TII->get(PPC::STWCX))
6713 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
6714 BuildMI(BB, dl, TII->get(PPC::BCC))
6715 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
6716 BB->addSuccessor(loopMBB);
6717 BB->addSuccessor(exitMBB);
6722 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg)
6727 llvm::MachineBasicBlock*
6728 PPCTargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
6729 MachineBasicBlock *MBB) const {
6730 DebugLoc DL = MI->getDebugLoc();
6731 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6733 MachineFunction *MF = MBB->getParent();
6734 MachineRegisterInfo &MRI = MF->getRegInfo();
6736 const BasicBlock *BB = MBB->getBasicBlock();
6737 MachineFunction::iterator I = MBB;
6741 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
6742 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
6744 unsigned DstReg = MI->getOperand(0).getReg();
6745 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
6746 assert(RC->hasType(MVT::i32) && "Invalid destination!");
6747 unsigned mainDstReg = MRI.createVirtualRegister(RC);
6748 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
6750 MVT PVT = getPointerTy();
6751 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6752 "Invalid Pointer Size!");
6753 // For v = setjmp(buf), we generate
6756 // SjLjSetup mainMBB
6762 // buf[LabelOffset] = LR
6766 // v = phi(main, restore)
6769 MachineBasicBlock *thisMBB = MBB;
6770 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
6771 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
6772 MF->insert(I, mainMBB);
6773 MF->insert(I, sinkMBB);
6775 MachineInstrBuilder MIB;
6777 // Transfer the remainder of BB and its successor edges to sinkMBB.
6778 sinkMBB->splice(sinkMBB->begin(), MBB,
6779 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
6780 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
6782 // Note that the structure of the jmp_buf used here is not compatible
6783 // with that used by libc, and is not designed to be. Specifically, it
6784 // stores only those 'reserved' registers that LLVM does not otherwise
6785 // understand how to spill. Also, by convention, by the time this
6786 // intrinsic is called, Clang has already stored the frame address in the
6787 // first slot of the buffer and stack address in the third. Following the
6788 // X86 target code, we'll store the jump address in the second slot. We also
6789 // need to save the TOC pointer (R2) to handle jumps between shared
6790 // libraries, and that will be stored in the fourth slot. The thread
6791 // identifier (R13) is not affected.
6794 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6795 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6796 const int64_t BPOffset = 4 * PVT.getStoreSize();
6798 // Prepare IP either in reg.
6799 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
6800 unsigned LabelReg = MRI.createVirtualRegister(PtrRC);
6801 unsigned BufReg = MI->getOperand(1).getReg();
6803 if (Subtarget.isPPC64() && Subtarget.isSVR4ABI()) {
6804 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::STD))
6808 MIB.setMemRefs(MMOBegin, MMOEnd);
6811 // Naked functions never have a base pointer, and so we use r1. For all
6812 // other functions, this decision must be delayed until during PEI.
6814 if (MF->getFunction()->getAttributes().hasAttribute(
6815 AttributeSet::FunctionIndex, Attribute::Naked))
6816 BaseReg = Subtarget.isPPC64() ? PPC::X1 : PPC::R1;
6818 BaseReg = Subtarget.isPPC64() ? PPC::BP8 : PPC::BP;
6820 MIB = BuildMI(*thisMBB, MI, DL,
6821 TII->get(Subtarget.isPPC64() ? PPC::STD : PPC::STW))
6825 MIB.setMemRefs(MMOBegin, MMOEnd);
6828 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::BCLalways)).addMBB(mainMBB);
6829 const PPCRegisterInfo *TRI =
6830 static_cast<const PPCRegisterInfo*>(getTargetMachine().getRegisterInfo());
6831 MIB.addRegMask(TRI->getNoPreservedMask());
6833 BuildMI(*thisMBB, MI, DL, TII->get(PPC::LI), restoreDstReg).addImm(1);
6835 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::EH_SjLj_Setup))
6837 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::B)).addMBB(sinkMBB);
6839 thisMBB->addSuccessor(mainMBB, /* weight */ 0);
6840 thisMBB->addSuccessor(sinkMBB, /* weight */ 1);
6844 MIB = BuildMI(mainMBB, DL,
6845 TII->get(Subtarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg);
6848 if (Subtarget.isPPC64()) {
6849 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STD))
6851 .addImm(LabelOffset)
6854 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STW))
6856 .addImm(LabelOffset)
6860 MIB.setMemRefs(MMOBegin, MMOEnd);
6862 BuildMI(mainMBB, DL, TII->get(PPC::LI), mainDstReg).addImm(0);
6863 mainMBB->addSuccessor(sinkMBB);
6866 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
6867 TII->get(PPC::PHI), DstReg)
6868 .addReg(mainDstReg).addMBB(mainMBB)
6869 .addReg(restoreDstReg).addMBB(thisMBB);
6871 MI->eraseFromParent();
6876 PPCTargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
6877 MachineBasicBlock *MBB) const {
6878 DebugLoc DL = MI->getDebugLoc();
6879 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6881 MachineFunction *MF = MBB->getParent();
6882 MachineRegisterInfo &MRI = MF->getRegInfo();
6885 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
6886 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
6888 MVT PVT = getPointerTy();
6889 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6890 "Invalid Pointer Size!");
6892 const TargetRegisterClass *RC =
6893 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
6894 unsigned Tmp = MRI.createVirtualRegister(RC);
6895 // Since FP is only updated here but NOT referenced, it's treated as GPR.
6896 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
6897 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
6898 unsigned BP = (PVT == MVT::i64) ? PPC::X30 :
6899 (Subtarget.isSVR4ABI() &&
6900 MF->getTarget().getRelocationModel() == Reloc::PIC_ ?
6901 PPC::R29 : PPC::R30);
6903 MachineInstrBuilder MIB;
6905 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6906 const int64_t SPOffset = 2 * PVT.getStoreSize();
6907 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6908 const int64_t BPOffset = 4 * PVT.getStoreSize();
6910 unsigned BufReg = MI->getOperand(0).getReg();
6912 // Reload FP (the jumped-to function may not have had a
6913 // frame pointer, and if so, then its r31 will be restored
6915 if (PVT == MVT::i64) {
6916 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), FP)
6920 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), FP)
6924 MIB.setMemRefs(MMOBegin, MMOEnd);
6927 if (PVT == MVT::i64) {
6928 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), Tmp)
6929 .addImm(LabelOffset)
6932 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), Tmp)
6933 .addImm(LabelOffset)
6936 MIB.setMemRefs(MMOBegin, MMOEnd);
6939 if (PVT == MVT::i64) {
6940 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), SP)
6944 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), SP)
6948 MIB.setMemRefs(MMOBegin, MMOEnd);
6951 if (PVT == MVT::i64) {
6952 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), BP)
6956 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), BP)
6960 MIB.setMemRefs(MMOBegin, MMOEnd);
6963 if (PVT == MVT::i64 && Subtarget.isSVR4ABI()) {
6964 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), PPC::X2)
6968 MIB.setMemRefs(MMOBegin, MMOEnd);
6972 BuildMI(*MBB, MI, DL,
6973 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
6974 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));
6976 MI->eraseFromParent();
6981 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
6982 MachineBasicBlock *BB) const {
6983 if (MI->getOpcode() == PPC::EH_SjLj_SetJmp32 ||
6984 MI->getOpcode() == PPC::EH_SjLj_SetJmp64) {
6985 return emitEHSjLjSetJmp(MI, BB);
6986 } else if (MI->getOpcode() == PPC::EH_SjLj_LongJmp32 ||
6987 MI->getOpcode() == PPC::EH_SjLj_LongJmp64) {
6988 return emitEHSjLjLongJmp(MI, BB);
6991 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6993 // To "insert" these instructions we actually have to insert their
6994 // control-flow patterns.
6995 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6996 MachineFunction::iterator It = BB;
6999 MachineFunction *F = BB->getParent();
7001 if (Subtarget.hasISEL() && (MI->getOpcode() == PPC::SELECT_CC_I4 ||
7002 MI->getOpcode() == PPC::SELECT_CC_I8 ||
7003 MI->getOpcode() == PPC::SELECT_I4 ||
7004 MI->getOpcode() == PPC::SELECT_I8)) {
7005 SmallVector<MachineOperand, 2> Cond;
7006 if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
7007 MI->getOpcode() == PPC::SELECT_CC_I8)
7008 Cond.push_back(MI->getOperand(4));
7010 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
7011 Cond.push_back(MI->getOperand(1));
7013 DebugLoc dl = MI->getDebugLoc();
7014 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7015 TII->insertSelect(*BB, MI, dl, MI->getOperand(0).getReg(),
7016 Cond, MI->getOperand(2).getReg(),
7017 MI->getOperand(3).getReg());
7018 } else if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
7019 MI->getOpcode() == PPC::SELECT_CC_I8 ||
7020 MI->getOpcode() == PPC::SELECT_CC_F4 ||
7021 MI->getOpcode() == PPC::SELECT_CC_F8 ||
7022 MI->getOpcode() == PPC::SELECT_CC_VRRC ||
7023 MI->getOpcode() == PPC::SELECT_I4 ||
7024 MI->getOpcode() == PPC::SELECT_I8 ||
7025 MI->getOpcode() == PPC::SELECT_F4 ||
7026 MI->getOpcode() == PPC::SELECT_F8 ||
7027 MI->getOpcode() == PPC::SELECT_VRRC) {
7028 // The incoming instruction knows the destination vreg to set, the
7029 // condition code register to branch on, the true/false values to
7030 // select between, and a branch opcode to use.
7035 // cmpTY ccX, r1, r2
7037 // fallthrough --> copy0MBB
7038 MachineBasicBlock *thisMBB = BB;
7039 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
7040 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
7041 DebugLoc dl = MI->getDebugLoc();
7042 F->insert(It, copy0MBB);
7043 F->insert(It, sinkMBB);
7045 // Transfer the remainder of BB and its successor edges to sinkMBB.
7046 sinkMBB->splice(sinkMBB->begin(), BB,
7047 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7048 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
7050 // Next, add the true and fallthrough blocks as its successors.
7051 BB->addSuccessor(copy0MBB);
7052 BB->addSuccessor(sinkMBB);
7054 if (MI->getOpcode() == PPC::SELECT_I4 ||
7055 MI->getOpcode() == PPC::SELECT_I8 ||
7056 MI->getOpcode() == PPC::SELECT_F4 ||
7057 MI->getOpcode() == PPC::SELECT_F8 ||
7058 MI->getOpcode() == PPC::SELECT_VRRC) {
7059 BuildMI(BB, dl, TII->get(PPC::BC))
7060 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
7062 unsigned SelectPred = MI->getOperand(4).getImm();
7063 BuildMI(BB, dl, TII->get(PPC::BCC))
7064 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
7068 // %FalseValue = ...
7069 // # fallthrough to sinkMBB
7072 // Update machine-CFG edges
7073 BB->addSuccessor(sinkMBB);
7076 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
7079 BuildMI(*BB, BB->begin(), dl,
7080 TII->get(PPC::PHI), MI->getOperand(0).getReg())
7081 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
7082 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
7084 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
7085 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
7086 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
7087 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
7088 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
7089 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4);
7090 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
7091 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8);
7093 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
7094 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
7095 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
7096 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
7097 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
7098 BB = EmitAtomicBinary(MI, BB, false, PPC::AND);
7099 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
7100 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8);
7102 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
7103 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
7104 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
7105 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
7106 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
7107 BB = EmitAtomicBinary(MI, BB, false, PPC::OR);
7108 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
7109 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8);
7111 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
7112 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
7113 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
7114 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
7115 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
7116 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR);
7117 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
7118 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8);
7120 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
7121 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::NAND);
7122 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
7123 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::NAND);
7124 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
7125 BB = EmitAtomicBinary(MI, BB, false, PPC::NAND);
7126 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
7127 BB = EmitAtomicBinary(MI, BB, true, PPC::NAND8);
7129 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
7130 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
7131 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
7132 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
7133 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
7134 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF);
7135 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
7136 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
7138 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
7139 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
7140 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
7141 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
7142 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
7143 BB = EmitAtomicBinary(MI, BB, false, 0);
7144 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
7145 BB = EmitAtomicBinary(MI, BB, true, 0);
7147 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
7148 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
7149 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
7151 unsigned dest = MI->getOperand(0).getReg();
7152 unsigned ptrA = MI->getOperand(1).getReg();
7153 unsigned ptrB = MI->getOperand(2).getReg();
7154 unsigned oldval = MI->getOperand(3).getReg();
7155 unsigned newval = MI->getOperand(4).getReg();
7156 DebugLoc dl = MI->getDebugLoc();
7158 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
7159 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
7160 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
7161 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
7162 F->insert(It, loop1MBB);
7163 F->insert(It, loop2MBB);
7164 F->insert(It, midMBB);
7165 F->insert(It, exitMBB);
7166 exitMBB->splice(exitMBB->begin(), BB,
7167 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7168 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
7172 // fallthrough --> loopMBB
7173 BB->addSuccessor(loop1MBB);
7176 // l[wd]arx dest, ptr
7177 // cmp[wd] dest, oldval
7180 // st[wd]cx. newval, ptr
7184 // st[wd]cx. dest, ptr
7187 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
7188 .addReg(ptrA).addReg(ptrB);
7189 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
7190 .addReg(oldval).addReg(dest);
7191 BuildMI(BB, dl, TII->get(PPC::BCC))
7192 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
7193 BB->addSuccessor(loop2MBB);
7194 BB->addSuccessor(midMBB);
7197 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
7198 .addReg(newval).addReg(ptrA).addReg(ptrB);
7199 BuildMI(BB, dl, TII->get(PPC::BCC))
7200 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
7201 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
7202 BB->addSuccessor(loop1MBB);
7203 BB->addSuccessor(exitMBB);
7206 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
7207 .addReg(dest).addReg(ptrA).addReg(ptrB);
7208 BB->addSuccessor(exitMBB);
7213 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
7214 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
7215 // We must use 64-bit registers for addresses when targeting 64-bit,
7216 // since we're actually doing arithmetic on them. Other registers
7218 bool is64bit = Subtarget.isPPC64();
7219 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
7221 unsigned dest = MI->getOperand(0).getReg();
7222 unsigned ptrA = MI->getOperand(1).getReg();
7223 unsigned ptrB = MI->getOperand(2).getReg();
7224 unsigned oldval = MI->getOperand(3).getReg();
7225 unsigned newval = MI->getOperand(4).getReg();
7226 DebugLoc dl = MI->getDebugLoc();
7228 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
7229 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
7230 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
7231 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
7232 F->insert(It, loop1MBB);
7233 F->insert(It, loop2MBB);
7234 F->insert(It, midMBB);
7235 F->insert(It, exitMBB);
7236 exitMBB->splice(exitMBB->begin(), BB,
7237 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7238 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
7240 MachineRegisterInfo &RegInfo = F->getRegInfo();
7241 const TargetRegisterClass *RC =
7242 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
7243 (const TargetRegisterClass *) &PPC::GPRCRegClass;
7244 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
7245 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
7246 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
7247 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
7248 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
7249 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
7250 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
7251 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
7252 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
7253 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
7254 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
7255 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
7256 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
7258 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
7259 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
7262 // fallthrough --> loopMBB
7263 BB->addSuccessor(loop1MBB);
7265 // The 4-byte load must be aligned, while a char or short may be
7266 // anywhere in the word. Hence all this nasty bookkeeping code.
7267 // add ptr1, ptrA, ptrB [copy if ptrA==0]
7268 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
7269 // xori shift, shift1, 24 [16]
7270 // rlwinm ptr, ptr1, 0, 0, 29
7271 // slw newval2, newval, shift
7272 // slw oldval2, oldval,shift
7273 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
7274 // slw mask, mask2, shift
7275 // and newval3, newval2, mask
7276 // and oldval3, oldval2, mask
7278 // lwarx tmpDest, ptr
7279 // and tmp, tmpDest, mask
7280 // cmpw tmp, oldval3
7283 // andc tmp2, tmpDest, mask
7284 // or tmp4, tmp2, newval3
7289 // stwcx. tmpDest, ptr
7291 // srw dest, tmpDest, shift
7292 if (ptrA != ZeroReg) {
7293 Ptr1Reg = RegInfo.createVirtualRegister(RC);
7294 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
7295 .addReg(ptrA).addReg(ptrB);
7299 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
7300 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
7301 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
7302 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
7304 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
7305 .addReg(Ptr1Reg).addImm(0).addImm(61);
7307 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
7308 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
7309 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
7310 .addReg(newval).addReg(ShiftReg);
7311 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
7312 .addReg(oldval).addReg(ShiftReg);
7314 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
7316 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
7317 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
7318 .addReg(Mask3Reg).addImm(65535);
7320 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
7321 .addReg(Mask2Reg).addReg(ShiftReg);
7322 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
7323 .addReg(NewVal2Reg).addReg(MaskReg);
7324 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
7325 .addReg(OldVal2Reg).addReg(MaskReg);
7328 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
7329 .addReg(ZeroReg).addReg(PtrReg);
7330 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
7331 .addReg(TmpDestReg).addReg(MaskReg);
7332 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
7333 .addReg(TmpReg).addReg(OldVal3Reg);
7334 BuildMI(BB, dl, TII->get(PPC::BCC))
7335 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
7336 BB->addSuccessor(loop2MBB);
7337 BB->addSuccessor(midMBB);
7340 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
7341 .addReg(TmpDestReg).addReg(MaskReg);
7342 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
7343 .addReg(Tmp2Reg).addReg(NewVal3Reg);
7344 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
7345 .addReg(ZeroReg).addReg(PtrReg);
7346 BuildMI(BB, dl, TII->get(PPC::BCC))
7347 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
7348 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
7349 BB->addSuccessor(loop1MBB);
7350 BB->addSuccessor(exitMBB);
7353 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
7354 .addReg(ZeroReg).addReg(PtrReg);
7355 BB->addSuccessor(exitMBB);
7360 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg)
7362 } else if (MI->getOpcode() == PPC::FADDrtz) {
7363 // This pseudo performs an FADD with rounding mode temporarily forced
7364 // to round-to-zero. We emit this via custom inserter since the FPSCR
7365 // is not modeled at the SelectionDAG level.
7366 unsigned Dest = MI->getOperand(0).getReg();
7367 unsigned Src1 = MI->getOperand(1).getReg();
7368 unsigned Src2 = MI->getOperand(2).getReg();
7369 DebugLoc dl = MI->getDebugLoc();
7371 MachineRegisterInfo &RegInfo = F->getRegInfo();
7372 unsigned MFFSReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
7374 // Save FPSCR value.
7375 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), MFFSReg);
7377 // Set rounding mode to round-to-zero.
7378 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB1)).addImm(31);
7379 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB0)).addImm(30);
7381 // Perform addition.
7382 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);
7384 // Restore FPSCR value.
7385 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSF)).addImm(1).addReg(MFFSReg);
7386 } else if (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
7387 MI->getOpcode() == PPC::ANDIo_1_GT_BIT ||
7388 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
7389 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) {
7390 unsigned Opcode = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
7391 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) ?
7392 PPC::ANDIo8 : PPC::ANDIo;
7393 bool isEQ = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
7394 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8);
7396 MachineRegisterInfo &RegInfo = F->getRegInfo();
7397 unsigned Dest = RegInfo.createVirtualRegister(Opcode == PPC::ANDIo ?
7398 &PPC::GPRCRegClass :
7399 &PPC::G8RCRegClass);
7401 DebugLoc dl = MI->getDebugLoc();
7402 BuildMI(*BB, MI, dl, TII->get(Opcode), Dest)
7403 .addReg(MI->getOperand(1).getReg()).addImm(1);
7404 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY),
7405 MI->getOperand(0).getReg())
7406 .addReg(isEQ ? PPC::CR0EQ : PPC::CR0GT);
7408 llvm_unreachable("Unexpected instr type to insert");
7411 MI->eraseFromParent(); // The pseudo instruction is gone now.
7415 //===----------------------------------------------------------------------===//
7416 // Target Optimization Hooks
7417 //===----------------------------------------------------------------------===//
7419 SDValue PPCTargetLowering::DAGCombineFastRecip(SDValue Op,
7420 DAGCombinerInfo &DCI) const {
7421 if (DCI.isAfterLegalizeVectorOps())
7424 EVT VT = Op.getValueType();
7426 if ((VT == MVT::f32 && Subtarget.hasFRES()) ||
7427 (VT == MVT::f64 && Subtarget.hasFRE()) ||
7428 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
7429 (VT == MVT::v2f64 && Subtarget.hasVSX())) {
7431 // Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
7432 // For the reciprocal, we need to find the zero of the function:
7433 // F(X) = A X - 1 [which has a zero at X = 1/A]
7435 // X_{i+1} = X_i (2 - A X_i) = X_i + X_i (1 - A X_i) [this second form
7436 // does not require additional intermediate precision]
7438 // Convergence is quadratic, so we essentially double the number of digits
7439 // correct after every iteration. The minimum architected relative
7440 // accuracy is 2^-5. When hasRecipPrec(), this is 2^-14. IEEE float has
7441 // 23 digits and double has 52 digits.
7442 int Iterations = Subtarget.hasRecipPrec() ? 1 : 3;
7443 if (VT.getScalarType() == MVT::f64)
7446 SelectionDAG &DAG = DCI.DAG;
7450 DAG.getConstantFP(1.0, VT.getScalarType());
7451 if (VT.isVector()) {
7452 assert(VT.getVectorNumElements() == 4 &&
7453 "Unknown vector type");
7454 FPOne = DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
7455 FPOne, FPOne, FPOne, FPOne);
7458 SDValue Est = DAG.getNode(PPCISD::FRE, dl, VT, Op);
7459 DCI.AddToWorklist(Est.getNode());
7461 // Newton iterations: Est = Est + Est (1 - Arg * Est)
7462 for (int i = 0; i < Iterations; ++i) {
7463 SDValue NewEst = DAG.getNode(ISD::FMUL, dl, VT, Op, Est);
7464 DCI.AddToWorklist(NewEst.getNode());
7466 NewEst = DAG.getNode(ISD::FSUB, dl, VT, FPOne, NewEst);
7467 DCI.AddToWorklist(NewEst.getNode());
7469 NewEst = DAG.getNode(ISD::FMUL, dl, VT, Est, NewEst);
7470 DCI.AddToWorklist(NewEst.getNode());
7472 Est = DAG.getNode(ISD::FADD, dl, VT, Est, NewEst);
7473 DCI.AddToWorklist(Est.getNode());
7482 SDValue PPCTargetLowering::DAGCombineFastRecipFSQRT(SDValue Op,
7483 DAGCombinerInfo &DCI) const {
7484 if (DCI.isAfterLegalizeVectorOps())
7487 EVT VT = Op.getValueType();
7489 if ((VT == MVT::f32 && Subtarget.hasFRSQRTES()) ||
7490 (VT == MVT::f64 && Subtarget.hasFRSQRTE()) ||
7491 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
7492 (VT == MVT::v2f64 && Subtarget.hasVSX())) {
7494 // Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
7495 // For the reciprocal sqrt, we need to find the zero of the function:
7496 // F(X) = 1/X^2 - A [which has a zero at X = 1/sqrt(A)]
7498 // X_{i+1} = X_i (1.5 - A X_i^2 / 2)
7499 // As a result, we precompute A/2 prior to the iteration loop.
7501 // Convergence is quadratic, so we essentially double the number of digits
7502 // correct after every iteration. The minimum architected relative
7503 // accuracy is 2^-5. When hasRecipPrec(), this is 2^-14. IEEE float has
7504 // 23 digits and double has 52 digits.
7505 int Iterations = Subtarget.hasRecipPrec() ? 1 : 3;
7506 if (VT.getScalarType() == MVT::f64)
7509 SelectionDAG &DAG = DCI.DAG;
7512 SDValue FPThreeHalves =
7513 DAG.getConstantFP(1.5, VT.getScalarType());
7514 if (VT.isVector()) {
7515 assert(VT.getVectorNumElements() == 4 &&
7516 "Unknown vector type");
7517 FPThreeHalves = DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
7518 FPThreeHalves, FPThreeHalves,
7519 FPThreeHalves, FPThreeHalves);
7522 SDValue Est = DAG.getNode(PPCISD::FRSQRTE, dl, VT, Op);
7523 DCI.AddToWorklist(Est.getNode());
7525 // We now need 0.5*Arg which we can write as (1.5*Arg - Arg) so that
7526 // this entire sequence requires only one FP constant.
7527 SDValue HalfArg = DAG.getNode(ISD::FMUL, dl, VT, FPThreeHalves, Op);
7528 DCI.AddToWorklist(HalfArg.getNode());
7530 HalfArg = DAG.getNode(ISD::FSUB, dl, VT, HalfArg, Op);
7531 DCI.AddToWorklist(HalfArg.getNode());
7533 // Newton iterations: Est = Est * (1.5 - HalfArg * Est * Est)
7534 for (int i = 0; i < Iterations; ++i) {
7535 SDValue NewEst = DAG.getNode(ISD::FMUL, dl, VT, Est, Est);
7536 DCI.AddToWorklist(NewEst.getNode());
7538 NewEst = DAG.getNode(ISD::FMUL, dl, VT, HalfArg, NewEst);
7539 DCI.AddToWorklist(NewEst.getNode());
7541 NewEst = DAG.getNode(ISD::FSUB, dl, VT, FPThreeHalves, NewEst);
7542 DCI.AddToWorklist(NewEst.getNode());
7544 Est = DAG.getNode(ISD::FMUL, dl, VT, Est, NewEst);
7545 DCI.AddToWorklist(Est.getNode());
7554 // Like SelectionDAG::isConsecutiveLoad, but also works for stores, and does
7555 // not enforce equality of the chain operands.
7556 static bool isConsecutiveLS(LSBaseSDNode *LS, LSBaseSDNode *Base,
7557 unsigned Bytes, int Dist,
7558 SelectionDAG &DAG) {
7559 EVT VT = LS->getMemoryVT();
7560 if (VT.getSizeInBits() / 8 != Bytes)
7563 SDValue Loc = LS->getBasePtr();
7564 SDValue BaseLoc = Base->getBasePtr();
7565 if (Loc.getOpcode() == ISD::FrameIndex) {
7566 if (BaseLoc.getOpcode() != ISD::FrameIndex)
7568 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7569 int FI = cast<FrameIndexSDNode>(Loc)->getIndex();
7570 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex();
7571 int FS = MFI->getObjectSize(FI);
7572 int BFS = MFI->getObjectSize(BFI);
7573 if (FS != BFS || FS != (int)Bytes) return false;
7574 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes);
7578 if (DAG.isBaseWithConstantOffset(Loc) && Loc.getOperand(0) == BaseLoc &&
7579 cast<ConstantSDNode>(Loc.getOperand(1))->getSExtValue() == Dist*Bytes)
7582 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7583 const GlobalValue *GV1 = nullptr;
7584 const GlobalValue *GV2 = nullptr;
7585 int64_t Offset1 = 0;
7586 int64_t Offset2 = 0;
7587 bool isGA1 = TLI.isGAPlusOffset(Loc.getNode(), GV1, Offset1);
7588 bool isGA2 = TLI.isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2);
7589 if (isGA1 && isGA2 && GV1 == GV2)
7590 return Offset1 == (Offset2 + Dist*Bytes);
7594 // Return true is there is a nearyby consecutive load to the one provided
7595 // (regardless of alignment). We search up and down the chain, looking though
7596 // token factors and other loads (but nothing else). As a result, a true
7597 // results indicates that it is safe to create a new consecutive load adjacent
7598 // to the load provided.
7599 static bool findConsecutiveLoad(LoadSDNode *LD, SelectionDAG &DAG) {
7600 SDValue Chain = LD->getChain();
7601 EVT VT = LD->getMemoryVT();
7603 SmallSet<SDNode *, 16> LoadRoots;
7604 SmallVector<SDNode *, 8> Queue(1, Chain.getNode());
7605 SmallSet<SDNode *, 16> Visited;
7607 // First, search up the chain, branching to follow all token-factor operands.
7608 // If we find a consecutive load, then we're done, otherwise, record all
7609 // nodes just above the top-level loads and token factors.
7610 while (!Queue.empty()) {
7611 SDNode *ChainNext = Queue.pop_back_val();
7612 if (!Visited.insert(ChainNext))
7615 if (LoadSDNode *ChainLD = dyn_cast<LoadSDNode>(ChainNext)) {
7616 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
7619 if (!Visited.count(ChainLD->getChain().getNode()))
7620 Queue.push_back(ChainLD->getChain().getNode());
7621 } else if (ChainNext->getOpcode() == ISD::TokenFactor) {
7622 for (const SDUse &O : ChainNext->ops())
7623 if (!Visited.count(O.getNode()))
7624 Queue.push_back(O.getNode());
7626 LoadRoots.insert(ChainNext);
7629 // Second, search down the chain, starting from the top-level nodes recorded
7630 // in the first phase. These top-level nodes are the nodes just above all
7631 // loads and token factors. Starting with their uses, recursively look though
7632 // all loads (just the chain uses) and token factors to find a consecutive
7637 for (SmallSet<SDNode *, 16>::iterator I = LoadRoots.begin(),
7638 IE = LoadRoots.end(); I != IE; ++I) {
7639 Queue.push_back(*I);
7641 while (!Queue.empty()) {
7642 SDNode *LoadRoot = Queue.pop_back_val();
7643 if (!Visited.insert(LoadRoot))
7646 if (LoadSDNode *ChainLD = dyn_cast<LoadSDNode>(LoadRoot))
7647 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
7650 for (SDNode::use_iterator UI = LoadRoot->use_begin(),
7651 UE = LoadRoot->use_end(); UI != UE; ++UI)
7652 if (((isa<LoadSDNode>(*UI) &&
7653 cast<LoadSDNode>(*UI)->getChain().getNode() == LoadRoot) ||
7654 UI->getOpcode() == ISD::TokenFactor) && !Visited.count(*UI))
7655 Queue.push_back(*UI);
7662 SDValue PPCTargetLowering::DAGCombineTruncBoolExt(SDNode *N,
7663 DAGCombinerInfo &DCI) const {
7664 SelectionDAG &DAG = DCI.DAG;
7667 assert(Subtarget.useCRBits() &&
7668 "Expecting to be tracking CR bits");
7669 // If we're tracking CR bits, we need to be careful that we don't have:
7670 // trunc(binary-ops(zext(x), zext(y)))
7672 // trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
7673 // such that we're unnecessarily moving things into GPRs when it would be
7674 // better to keep them in CR bits.
7676 // Note that trunc here can be an actual i1 trunc, or can be the effective
7677 // truncation that comes from a setcc or select_cc.
7678 if (N->getOpcode() == ISD::TRUNCATE &&
7679 N->getValueType(0) != MVT::i1)
7682 if (N->getOperand(0).getValueType() != MVT::i32 &&
7683 N->getOperand(0).getValueType() != MVT::i64)
7686 if (N->getOpcode() == ISD::SETCC ||
7687 N->getOpcode() == ISD::SELECT_CC) {
7688 // If we're looking at a comparison, then we need to make sure that the
7689 // high bits (all except for the first) don't matter the result.
7691 cast<CondCodeSDNode>(N->getOperand(
7692 N->getOpcode() == ISD::SETCC ? 2 : 4))->get();
7693 unsigned OpBits = N->getOperand(0).getValueSizeInBits();
7695 if (ISD::isSignedIntSetCC(CC)) {
7696 if (DAG.ComputeNumSignBits(N->getOperand(0)) != OpBits ||
7697 DAG.ComputeNumSignBits(N->getOperand(1)) != OpBits)
7699 } else if (ISD::isUnsignedIntSetCC(CC)) {
7700 if (!DAG.MaskedValueIsZero(N->getOperand(0),
7701 APInt::getHighBitsSet(OpBits, OpBits-1)) ||
7702 !DAG.MaskedValueIsZero(N->getOperand(1),
7703 APInt::getHighBitsSet(OpBits, OpBits-1)))
7706 // This is neither a signed nor an unsigned comparison, just make sure
7707 // that the high bits are equal.
7708 APInt Op1Zero, Op1One;
7709 APInt Op2Zero, Op2One;
7710 DAG.computeKnownBits(N->getOperand(0), Op1Zero, Op1One);
7711 DAG.computeKnownBits(N->getOperand(1), Op2Zero, Op2One);
7713 // We don't really care about what is known about the first bit (if
7714 // anything), so clear it in all masks prior to comparing them.
7715 Op1Zero.clearBit(0); Op1One.clearBit(0);
7716 Op2Zero.clearBit(0); Op2One.clearBit(0);
7718 if (Op1Zero != Op2Zero || Op1One != Op2One)
7723 // We now know that the higher-order bits are irrelevant, we just need to
7724 // make sure that all of the intermediate operations are bit operations, and
7725 // all inputs are extensions.
7726 if (N->getOperand(0).getOpcode() != ISD::AND &&
7727 N->getOperand(0).getOpcode() != ISD::OR &&
7728 N->getOperand(0).getOpcode() != ISD::XOR &&
7729 N->getOperand(0).getOpcode() != ISD::SELECT &&
7730 N->getOperand(0).getOpcode() != ISD::SELECT_CC &&
7731 N->getOperand(0).getOpcode() != ISD::TRUNCATE &&
7732 N->getOperand(0).getOpcode() != ISD::SIGN_EXTEND &&
7733 N->getOperand(0).getOpcode() != ISD::ZERO_EXTEND &&
7734 N->getOperand(0).getOpcode() != ISD::ANY_EXTEND)
7737 if ((N->getOpcode() == ISD::SETCC || N->getOpcode() == ISD::SELECT_CC) &&
7738 N->getOperand(1).getOpcode() != ISD::AND &&
7739 N->getOperand(1).getOpcode() != ISD::OR &&
7740 N->getOperand(1).getOpcode() != ISD::XOR &&
7741 N->getOperand(1).getOpcode() != ISD::SELECT &&
7742 N->getOperand(1).getOpcode() != ISD::SELECT_CC &&
7743 N->getOperand(1).getOpcode() != ISD::TRUNCATE &&
7744 N->getOperand(1).getOpcode() != ISD::SIGN_EXTEND &&
7745 N->getOperand(1).getOpcode() != ISD::ZERO_EXTEND &&
7746 N->getOperand(1).getOpcode() != ISD::ANY_EXTEND)
7749 SmallVector<SDValue, 4> Inputs;
7750 SmallVector<SDValue, 8> BinOps, PromOps;
7751 SmallPtrSet<SDNode *, 16> Visited;
7753 for (unsigned i = 0; i < 2; ++i) {
7754 if (((N->getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
7755 N->getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
7756 N->getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
7757 N->getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
7758 isa<ConstantSDNode>(N->getOperand(i)))
7759 Inputs.push_back(N->getOperand(i));
7761 BinOps.push_back(N->getOperand(i));
7763 if (N->getOpcode() == ISD::TRUNCATE)
7767 // Visit all inputs, collect all binary operations (and, or, xor and
7768 // select) that are all fed by extensions.
7769 while (!BinOps.empty()) {
7770 SDValue BinOp = BinOps.back();
7773 if (!Visited.insert(BinOp.getNode()))
7776 PromOps.push_back(BinOp);
7778 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
7779 // The condition of the select is not promoted.
7780 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
7782 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
7785 if (((BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
7786 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
7787 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
7788 BinOp.getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
7789 isa<ConstantSDNode>(BinOp.getOperand(i))) {
7790 Inputs.push_back(BinOp.getOperand(i));
7791 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
7792 BinOp.getOperand(i).getOpcode() == ISD::OR ||
7793 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
7794 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
7795 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC ||
7796 BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
7797 BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
7798 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
7799 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) {
7800 BinOps.push_back(BinOp.getOperand(i));
7802 // We have an input that is not an extension or another binary
7803 // operation; we'll abort this transformation.
7809 // Make sure that this is a self-contained cluster of operations (which
7810 // is not quite the same thing as saying that everything has only one
7812 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7813 if (isa<ConstantSDNode>(Inputs[i]))
7816 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
7817 UE = Inputs[i].getNode()->use_end();
7820 if (User != N && !Visited.count(User))
7823 // Make sure that we're not going to promote the non-output-value
7824 // operand(s) or SELECT or SELECT_CC.
7825 // FIXME: Although we could sometimes handle this, and it does occur in
7826 // practice that one of the condition inputs to the select is also one of
7827 // the outputs, we currently can't deal with this.
7828 if (User->getOpcode() == ISD::SELECT) {
7829 if (User->getOperand(0) == Inputs[i])
7831 } else if (User->getOpcode() == ISD::SELECT_CC) {
7832 if (User->getOperand(0) == Inputs[i] ||
7833 User->getOperand(1) == Inputs[i])
7839 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
7840 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
7841 UE = PromOps[i].getNode()->use_end();
7844 if (User != N && !Visited.count(User))
7847 // Make sure that we're not going to promote the non-output-value
7848 // operand(s) or SELECT or SELECT_CC.
7849 // FIXME: Although we could sometimes handle this, and it does occur in
7850 // practice that one of the condition inputs to the select is also one of
7851 // the outputs, we currently can't deal with this.
7852 if (User->getOpcode() == ISD::SELECT) {
7853 if (User->getOperand(0) == PromOps[i])
7855 } else if (User->getOpcode() == ISD::SELECT_CC) {
7856 if (User->getOperand(0) == PromOps[i] ||
7857 User->getOperand(1) == PromOps[i])
7863 // Replace all inputs with the extension operand.
7864 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7865 // Constants may have users outside the cluster of to-be-promoted nodes,
7866 // and so we need to replace those as we do the promotions.
7867 if (isa<ConstantSDNode>(Inputs[i]))
7870 DAG.ReplaceAllUsesOfValueWith(Inputs[i], Inputs[i].getOperand(0));
7873 // Replace all operations (these are all the same, but have a different
7874 // (i1) return type). DAG.getNode will validate that the types of
7875 // a binary operator match, so go through the list in reverse so that
7876 // we've likely promoted both operands first. Any intermediate truncations or
7877 // extensions disappear.
7878 while (!PromOps.empty()) {
7879 SDValue PromOp = PromOps.back();
7882 if (PromOp.getOpcode() == ISD::TRUNCATE ||
7883 PromOp.getOpcode() == ISD::SIGN_EXTEND ||
7884 PromOp.getOpcode() == ISD::ZERO_EXTEND ||
7885 PromOp.getOpcode() == ISD::ANY_EXTEND) {
7886 if (!isa<ConstantSDNode>(PromOp.getOperand(0)) &&
7887 PromOp.getOperand(0).getValueType() != MVT::i1) {
7888 // The operand is not yet ready (see comment below).
7889 PromOps.insert(PromOps.begin(), PromOp);
7893 SDValue RepValue = PromOp.getOperand(0);
7894 if (isa<ConstantSDNode>(RepValue))
7895 RepValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, RepValue);
7897 DAG.ReplaceAllUsesOfValueWith(PromOp, RepValue);
7902 switch (PromOp.getOpcode()) {
7903 default: C = 0; break;
7904 case ISD::SELECT: C = 1; break;
7905 case ISD::SELECT_CC: C = 2; break;
7908 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
7909 PromOp.getOperand(C).getValueType() != MVT::i1) ||
7910 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
7911 PromOp.getOperand(C+1).getValueType() != MVT::i1)) {
7912 // The to-be-promoted operands of this node have not yet been
7913 // promoted (this should be rare because we're going through the
7914 // list backward, but if one of the operands has several users in
7915 // this cluster of to-be-promoted nodes, it is possible).
7916 PromOps.insert(PromOps.begin(), PromOp);
7920 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
7921 PromOp.getNode()->op_end());
7923 // If there are any constant inputs, make sure they're replaced now.
7924 for (unsigned i = 0; i < 2; ++i)
7925 if (isa<ConstantSDNode>(Ops[C+i]))
7926 Ops[C+i] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ops[C+i]);
7928 DAG.ReplaceAllUsesOfValueWith(PromOp,
7929 DAG.getNode(PromOp.getOpcode(), dl, MVT::i1, Ops));
7932 // Now we're left with the initial truncation itself.
7933 if (N->getOpcode() == ISD::TRUNCATE)
7934 return N->getOperand(0);
7936 // Otherwise, this is a comparison. The operands to be compared have just
7937 // changed type (to i1), but everything else is the same.
7938 return SDValue(N, 0);
7941 SDValue PPCTargetLowering::DAGCombineExtBoolTrunc(SDNode *N,
7942 DAGCombinerInfo &DCI) const {
7943 SelectionDAG &DAG = DCI.DAG;
7946 // If we're tracking CR bits, we need to be careful that we don't have:
7947 // zext(binary-ops(trunc(x), trunc(y)))
7949 // zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
7950 // such that we're unnecessarily moving things into CR bits that can more
7951 // efficiently stay in GPRs. Note that if we're not certain that the high
7952 // bits are set as required by the final extension, we still may need to do
7953 // some masking to get the proper behavior.
7955 // This same functionality is important on PPC64 when dealing with
7956 // 32-to-64-bit extensions; these occur often when 32-bit values are used as
7957 // the return values of functions. Because it is so similar, it is handled
7960 if (N->getValueType(0) != MVT::i32 &&
7961 N->getValueType(0) != MVT::i64)
7964 if (!((N->getOperand(0).getValueType() == MVT::i1 &&
7965 Subtarget.useCRBits()) ||
7966 (N->getOperand(0).getValueType() == MVT::i32 &&
7967 Subtarget.isPPC64())))
7970 if (N->getOperand(0).getOpcode() != ISD::AND &&
7971 N->getOperand(0).getOpcode() != ISD::OR &&
7972 N->getOperand(0).getOpcode() != ISD::XOR &&
7973 N->getOperand(0).getOpcode() != ISD::SELECT &&
7974 N->getOperand(0).getOpcode() != ISD::SELECT_CC)
7977 SmallVector<SDValue, 4> Inputs;
7978 SmallVector<SDValue, 8> BinOps(1, N->getOperand(0)), PromOps;
7979 SmallPtrSet<SDNode *, 16> Visited;
7981 // Visit all inputs, collect all binary operations (and, or, xor and
7982 // select) that are all fed by truncations.
7983 while (!BinOps.empty()) {
7984 SDValue BinOp = BinOps.back();
7987 if (!Visited.insert(BinOp.getNode()))
7990 PromOps.push_back(BinOp);
7992 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
7993 // The condition of the select is not promoted.
7994 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
7996 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
7999 if (BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
8000 isa<ConstantSDNode>(BinOp.getOperand(i))) {
8001 Inputs.push_back(BinOp.getOperand(i));
8002 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
8003 BinOp.getOperand(i).getOpcode() == ISD::OR ||
8004 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
8005 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
8006 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC) {
8007 BinOps.push_back(BinOp.getOperand(i));
8009 // We have an input that is not a truncation or another binary
8010 // operation; we'll abort this transformation.
8016 // Make sure that this is a self-contained cluster of operations (which
8017 // is not quite the same thing as saying that everything has only one
8019 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8020 if (isa<ConstantSDNode>(Inputs[i]))
8023 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
8024 UE = Inputs[i].getNode()->use_end();
8027 if (User != N && !Visited.count(User))
8030 // Make sure that we're not going to promote the non-output-value
8031 // operand(s) or SELECT or SELECT_CC.
8032 // FIXME: Although we could sometimes handle this, and it does occur in
8033 // practice that one of the condition inputs to the select is also one of
8034 // the outputs, we currently can't deal with this.
8035 if (User->getOpcode() == ISD::SELECT) {
8036 if (User->getOperand(0) == Inputs[i])
8038 } else if (User->getOpcode() == ISD::SELECT_CC) {
8039 if (User->getOperand(0) == Inputs[i] ||
8040 User->getOperand(1) == Inputs[i])
8046 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
8047 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
8048 UE = PromOps[i].getNode()->use_end();
8051 if (User != N && !Visited.count(User))
8054 // Make sure that we're not going to promote the non-output-value
8055 // operand(s) or SELECT or SELECT_CC.
8056 // FIXME: Although we could sometimes handle this, and it does occur in
8057 // practice that one of the condition inputs to the select is also one of
8058 // the outputs, we currently can't deal with this.
8059 if (User->getOpcode() == ISD::SELECT) {
8060 if (User->getOperand(0) == PromOps[i])
8062 } else if (User->getOpcode() == ISD::SELECT_CC) {
8063 if (User->getOperand(0) == PromOps[i] ||
8064 User->getOperand(1) == PromOps[i])
8070 unsigned PromBits = N->getOperand(0).getValueSizeInBits();
8071 bool ReallyNeedsExt = false;
8072 if (N->getOpcode() != ISD::ANY_EXTEND) {
8073 // If all of the inputs are not already sign/zero extended, then
8074 // we'll still need to do that at the end.
8075 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8076 if (isa<ConstantSDNode>(Inputs[i]))
8080 Inputs[i].getOperand(0).getValueSizeInBits();
8081 assert(PromBits < OpBits && "Truncation not to a smaller bit count?");
8083 if ((N->getOpcode() == ISD::ZERO_EXTEND &&
8084 !DAG.MaskedValueIsZero(Inputs[i].getOperand(0),
8085 APInt::getHighBitsSet(OpBits,
8086 OpBits-PromBits))) ||
8087 (N->getOpcode() == ISD::SIGN_EXTEND &&
8088 DAG.ComputeNumSignBits(Inputs[i].getOperand(0)) <
8089 (OpBits-(PromBits-1)))) {
8090 ReallyNeedsExt = true;
8096 // Replace all inputs, either with the truncation operand, or a
8097 // truncation or extension to the final output type.
8098 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8099 // Constant inputs need to be replaced with the to-be-promoted nodes that
8100 // use them because they might have users outside of the cluster of
8102 if (isa<ConstantSDNode>(Inputs[i]))
8105 SDValue InSrc = Inputs[i].getOperand(0);
8106 if (Inputs[i].getValueType() == N->getValueType(0))
8107 DAG.ReplaceAllUsesOfValueWith(Inputs[i], InSrc);
8108 else if (N->getOpcode() == ISD::SIGN_EXTEND)
8109 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
8110 DAG.getSExtOrTrunc(InSrc, dl, N->getValueType(0)));
8111 else if (N->getOpcode() == ISD::ZERO_EXTEND)
8112 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
8113 DAG.getZExtOrTrunc(InSrc, dl, N->getValueType(0)));
8115 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
8116 DAG.getAnyExtOrTrunc(InSrc, dl, N->getValueType(0)));
8119 // Replace all operations (these are all the same, but have a different
8120 // (promoted) return type). DAG.getNode will validate that the types of
8121 // a binary operator match, so go through the list in reverse so that
8122 // we've likely promoted both operands first.
8123 while (!PromOps.empty()) {
8124 SDValue PromOp = PromOps.back();
8128 switch (PromOp.getOpcode()) {
8129 default: C = 0; break;
8130 case ISD::SELECT: C = 1; break;
8131 case ISD::SELECT_CC: C = 2; break;
8134 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
8135 PromOp.getOperand(C).getValueType() != N->getValueType(0)) ||
8136 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
8137 PromOp.getOperand(C+1).getValueType() != N->getValueType(0))) {
8138 // The to-be-promoted operands of this node have not yet been
8139 // promoted (this should be rare because we're going through the
8140 // list backward, but if one of the operands has several users in
8141 // this cluster of to-be-promoted nodes, it is possible).
8142 PromOps.insert(PromOps.begin(), PromOp);
8146 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
8147 PromOp.getNode()->op_end());
8149 // If this node has constant inputs, then they'll need to be promoted here.
8150 for (unsigned i = 0; i < 2; ++i) {
8151 if (!isa<ConstantSDNode>(Ops[C+i]))
8153 if (Ops[C+i].getValueType() == N->getValueType(0))
8156 if (N->getOpcode() == ISD::SIGN_EXTEND)
8157 Ops[C+i] = DAG.getSExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
8158 else if (N->getOpcode() == ISD::ZERO_EXTEND)
8159 Ops[C+i] = DAG.getZExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
8161 Ops[C+i] = DAG.getAnyExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
8164 DAG.ReplaceAllUsesOfValueWith(PromOp,
8165 DAG.getNode(PromOp.getOpcode(), dl, N->getValueType(0), Ops));
8168 // Now we're left with the initial extension itself.
8169 if (!ReallyNeedsExt)
8170 return N->getOperand(0);
8172 // To zero extend, just mask off everything except for the first bit (in the
8174 if (N->getOpcode() == ISD::ZERO_EXTEND)
8175 return DAG.getNode(ISD::AND, dl, N->getValueType(0), N->getOperand(0),
8176 DAG.getConstant(APInt::getLowBitsSet(
8177 N->getValueSizeInBits(0), PromBits),
8178 N->getValueType(0)));
8180 assert(N->getOpcode() == ISD::SIGN_EXTEND &&
8181 "Invalid extension type");
8182 EVT ShiftAmountTy = getShiftAmountTy(N->getValueType(0));
8184 DAG.getConstant(N->getValueSizeInBits(0)-PromBits, ShiftAmountTy);
8185 return DAG.getNode(ISD::SRA, dl, N->getValueType(0),
8186 DAG.getNode(ISD::SHL, dl, N->getValueType(0),
8187 N->getOperand(0), ShiftCst), ShiftCst);
8190 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
8191 DAGCombinerInfo &DCI) const {
8192 const TargetMachine &TM = getTargetMachine();
8193 SelectionDAG &DAG = DCI.DAG;
8195 switch (N->getOpcode()) {
8198 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8199 if (C->isNullValue()) // 0 << V -> 0.
8200 return N->getOperand(0);
8204 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8205 if (C->isNullValue()) // 0 >>u V -> 0.
8206 return N->getOperand(0);
8210 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8211 if (C->isNullValue() || // 0 >>s V -> 0.
8212 C->isAllOnesValue()) // -1 >>s V -> -1.
8213 return N->getOperand(0);
8216 case ISD::SIGN_EXTEND:
8217 case ISD::ZERO_EXTEND:
8218 case ISD::ANY_EXTEND:
8219 return DAGCombineExtBoolTrunc(N, DCI);
8222 case ISD::SELECT_CC:
8223 return DAGCombineTruncBoolExt(N, DCI);
8225 assert(TM.Options.UnsafeFPMath &&
8226 "Reciprocal estimates require UnsafeFPMath");
8228 if (N->getOperand(1).getOpcode() == ISD::FSQRT) {
8230 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0), DCI);
8232 DCI.AddToWorklist(RV.getNode());
8233 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
8234 N->getOperand(0), RV);
8236 } else if (N->getOperand(1).getOpcode() == ISD::FP_EXTEND &&
8237 N->getOperand(1).getOperand(0).getOpcode() == ISD::FSQRT) {
8239 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0).getOperand(0),
8242 DCI.AddToWorklist(RV.getNode());
8243 RV = DAG.getNode(ISD::FP_EXTEND, SDLoc(N->getOperand(1)),
8244 N->getValueType(0), RV);
8245 DCI.AddToWorklist(RV.getNode());
8246 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
8247 N->getOperand(0), RV);
8249 } else if (N->getOperand(1).getOpcode() == ISD::FP_ROUND &&
8250 N->getOperand(1).getOperand(0).getOpcode() == ISD::FSQRT) {
8252 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0).getOperand(0),
8255 DCI.AddToWorklist(RV.getNode());
8256 RV = DAG.getNode(ISD::FP_ROUND, SDLoc(N->getOperand(1)),
8257 N->getValueType(0), RV,
8258 N->getOperand(1).getOperand(1));
8259 DCI.AddToWorklist(RV.getNode());
8260 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
8261 N->getOperand(0), RV);
8265 SDValue RV = DAGCombineFastRecip(N->getOperand(1), DCI);
8267 DCI.AddToWorklist(RV.getNode());
8268 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
8269 N->getOperand(0), RV);
8275 assert(TM.Options.UnsafeFPMath &&
8276 "Reciprocal estimates require UnsafeFPMath");
8278 // Compute this as 1/(1/sqrt(X)), which is the reciprocal of the
8280 SDValue RV = DAGCombineFastRecipFSQRT(N->getOperand(0), DCI);
8282 DCI.AddToWorklist(RV.getNode());
8283 RV = DAGCombineFastRecip(RV, DCI);
8285 // Unfortunately, RV is now NaN if the input was exactly 0. Select out
8286 // this case and force the answer to 0.
8288 EVT VT = RV.getValueType();
8290 SDValue Zero = DAG.getConstantFP(0.0, VT.getScalarType());
8291 if (VT.isVector()) {
8292 assert(VT.getVectorNumElements() == 4 && "Unknown vector type");
8293 Zero = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Zero, Zero, Zero, Zero);
8297 DAG.getSetCC(dl, getSetCCResultType(*DAG.getContext(), VT),
8298 N->getOperand(0), Zero, ISD::SETEQ);
8299 DCI.AddToWorklist(ZeroCmp.getNode());
8300 DCI.AddToWorklist(RV.getNode());
8302 RV = DAG.getNode(VT.isVector() ? ISD::VSELECT : ISD::SELECT, dl, VT,
8310 case ISD::SINT_TO_FP:
8311 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
8312 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
8313 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
8314 // We allow the src/dst to be either f32/f64, but the intermediate
8315 // type must be i64.
8316 if (N->getOperand(0).getValueType() == MVT::i64 &&
8317 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
8318 SDValue Val = N->getOperand(0).getOperand(0);
8319 if (Val.getValueType() == MVT::f32) {
8320 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
8321 DCI.AddToWorklist(Val.getNode());
8324 Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val);
8325 DCI.AddToWorklist(Val.getNode());
8326 Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val);
8327 DCI.AddToWorklist(Val.getNode());
8328 if (N->getValueType(0) == MVT::f32) {
8329 Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val,
8330 DAG.getIntPtrConstant(0));
8331 DCI.AddToWorklist(Val.getNode());
8334 } else if (N->getOperand(0).getValueType() == MVT::i32) {
8335 // If the intermediate type is i32, we can avoid the load/store here
8342 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
8343 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
8344 !cast<StoreSDNode>(N)->isTruncatingStore() &&
8345 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
8346 N->getOperand(1).getValueType() == MVT::i32 &&
8347 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
8348 SDValue Val = N->getOperand(1).getOperand(0);
8349 if (Val.getValueType() == MVT::f32) {
8350 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
8351 DCI.AddToWorklist(Val.getNode());
8353 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
8354 DCI.AddToWorklist(Val.getNode());
8357 N->getOperand(0), Val, N->getOperand(2),
8358 DAG.getValueType(N->getOperand(1).getValueType())
8361 Val = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
8362 DAG.getVTList(MVT::Other), Ops,
8363 cast<StoreSDNode>(N)->getMemoryVT(),
8364 cast<StoreSDNode>(N)->getMemOperand());
8365 DCI.AddToWorklist(Val.getNode());
8369 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
8370 if (cast<StoreSDNode>(N)->isUnindexed() &&
8371 N->getOperand(1).getOpcode() == ISD::BSWAP &&
8372 N->getOperand(1).getNode()->hasOneUse() &&
8373 (N->getOperand(1).getValueType() == MVT::i32 ||
8374 N->getOperand(1).getValueType() == MVT::i16 ||
8375 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
8376 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
8377 N->getOperand(1).getValueType() == MVT::i64))) {
8378 SDValue BSwapOp = N->getOperand(1).getOperand(0);
8379 // Do an any-extend to 32-bits if this is a half-word input.
8380 if (BSwapOp.getValueType() == MVT::i16)
8381 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
8384 N->getOperand(0), BSwapOp, N->getOperand(2),
8385 DAG.getValueType(N->getOperand(1).getValueType())
8388 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
8389 Ops, cast<StoreSDNode>(N)->getMemoryVT(),
8390 cast<StoreSDNode>(N)->getMemOperand());
8394 LoadSDNode *LD = cast<LoadSDNode>(N);
8395 EVT VT = LD->getValueType(0);
8396 Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
8397 unsigned ABIAlignment = getDataLayout()->getABITypeAlignment(Ty);
8398 if (ISD::isNON_EXTLoad(N) && VT.isVector() &&
8399 TM.getSubtarget<PPCSubtarget>().hasAltivec() &&
8400 (VT == MVT::v16i8 || VT == MVT::v8i16 ||
8401 VT == MVT::v4i32 || VT == MVT::v4f32) &&
8402 LD->getAlignment() < ABIAlignment) {
8403 // This is a type-legal unaligned Altivec load.
8404 SDValue Chain = LD->getChain();
8405 SDValue Ptr = LD->getBasePtr();
8406 bool isLittleEndian = Subtarget.isLittleEndian();
8408 // This implements the loading of unaligned vectors as described in
8409 // the venerable Apple Velocity Engine overview. Specifically:
8410 // https://developer.apple.com/hardwaredrivers/ve/alignment.html
8411 // https://developer.apple.com/hardwaredrivers/ve/code_optimization.html
8413 // The general idea is to expand a sequence of one or more unaligned
8414 // loads into an alignment-based permutation-control instruction (lvsl
8415 // or lvsr), a series of regular vector loads (which always truncate
8416 // their input address to an aligned address), and a series of
8417 // permutations. The results of these permutations are the requested
8418 // loaded values. The trick is that the last "extra" load is not taken
8419 // from the address you might suspect (sizeof(vector) bytes after the
8420 // last requested load), but rather sizeof(vector) - 1 bytes after the
8421 // last requested vector. The point of this is to avoid a page fault if
8422 // the base address happened to be aligned. This works because if the
8423 // base address is aligned, then adding less than a full vector length
8424 // will cause the last vector in the sequence to be (re)loaded.
8425 // Otherwise, the next vector will be fetched as you might suspect was
8428 // We might be able to reuse the permutation generation from
8429 // a different base address offset from this one by an aligned amount.
8430 // The INTRINSIC_WO_CHAIN DAG combine will attempt to perform this
8431 // optimization later.
8432 Intrinsic::ID Intr = (isLittleEndian ?
8433 Intrinsic::ppc_altivec_lvsr :
8434 Intrinsic::ppc_altivec_lvsl);
8435 SDValue PermCntl = BuildIntrinsicOp(Intr, Ptr, DAG, dl, MVT::v16i8);
8437 // Refine the alignment of the original load (a "new" load created here
8438 // which was identical to the first except for the alignment would be
8439 // merged with the existing node regardless).
8440 MachineFunction &MF = DAG.getMachineFunction();
8441 MachineMemOperand *MMO =
8442 MF.getMachineMemOperand(LD->getPointerInfo(),
8443 LD->getMemOperand()->getFlags(),
8444 LD->getMemoryVT().getStoreSize(),
8446 LD->refineAlignment(MMO);
8447 SDValue BaseLoad = SDValue(LD, 0);
8449 // Note that the value of IncOffset (which is provided to the next
8450 // load's pointer info offset value, and thus used to calculate the
8451 // alignment), and the value of IncValue (which is actually used to
8452 // increment the pointer value) are different! This is because we
8453 // require the next load to appear to be aligned, even though it
8454 // is actually offset from the base pointer by a lesser amount.
8455 int IncOffset = VT.getSizeInBits() / 8;
8456 int IncValue = IncOffset;
8458 // Walk (both up and down) the chain looking for another load at the real
8459 // (aligned) offset (the alignment of the other load does not matter in
8460 // this case). If found, then do not use the offset reduction trick, as
8461 // that will prevent the loads from being later combined (as they would
8462 // otherwise be duplicates).
8463 if (!findConsecutiveLoad(LD, DAG))
8466 SDValue Increment = DAG.getConstant(IncValue, getPointerTy());
8467 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
8470 DAG.getLoad(VT, dl, Chain, Ptr,
8471 LD->getPointerInfo().getWithOffset(IncOffset),
8472 LD->isVolatile(), LD->isNonTemporal(),
8473 LD->isInvariant(), ABIAlignment);
8475 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
8476 BaseLoad.getValue(1), ExtraLoad.getValue(1));
8478 if (BaseLoad.getValueType() != MVT::v4i32)
8479 BaseLoad = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, BaseLoad);
8481 if (ExtraLoad.getValueType() != MVT::v4i32)
8482 ExtraLoad = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, ExtraLoad);
8484 // Because vperm has a big-endian bias, we must reverse the order
8485 // of the input vectors and complement the permute control vector
8486 // when generating little endian code. We have already handled the
8487 // latter by using lvsr instead of lvsl, so just reverse BaseLoad
8488 // and ExtraLoad here.
8491 Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm,
8492 ExtraLoad, BaseLoad, PermCntl, DAG, dl);
8494 Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm,
8495 BaseLoad, ExtraLoad, PermCntl, DAG, dl);
8497 if (VT != MVT::v4i32)
8498 Perm = DAG.getNode(ISD::BITCAST, dl, VT, Perm);
8500 // Now we need to be really careful about how we update the users of the
8501 // original load. We cannot just call DCI.CombineTo (or
8502 // DAG.ReplaceAllUsesWith for that matter), because the load still has
8503 // uses created here (the permutation for example) that need to stay.
8504 SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
8506 SDUse &Use = UI.getUse();
8508 // Note: BaseLoad is checked here because it might not be N, but a
8510 if (User == Perm.getNode() || User == BaseLoad.getNode() ||
8511 User == TF.getNode() || Use.getResNo() > 1) {
8516 SDValue To = Use.getResNo() ? TF : Perm;
8519 SmallVector<SDValue, 8> Ops;
8520 for (const SDUse &O : User->ops()) {
8527 DAG.UpdateNodeOperands(User, Ops);
8530 return SDValue(N, 0);
8534 case ISD::INTRINSIC_WO_CHAIN: {
8535 bool isLittleEndian = Subtarget.isLittleEndian();
8536 Intrinsic::ID Intr = (isLittleEndian ?
8537 Intrinsic::ppc_altivec_lvsr :
8538 Intrinsic::ppc_altivec_lvsl);
8539 if (cast<ConstantSDNode>(N->getOperand(0))->getZExtValue() == Intr &&
8540 N->getOperand(1)->getOpcode() == ISD::ADD) {
8541 SDValue Add = N->getOperand(1);
8543 if (DAG.MaskedValueIsZero(Add->getOperand(1),
8544 APInt::getAllOnesValue(4 /* 16 byte alignment */).zext(
8545 Add.getValueType().getScalarType().getSizeInBits()))) {
8546 SDNode *BasePtr = Add->getOperand(0).getNode();
8547 for (SDNode::use_iterator UI = BasePtr->use_begin(),
8548 UE = BasePtr->use_end(); UI != UE; ++UI) {
8549 if (UI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
8550 cast<ConstantSDNode>(UI->getOperand(0))->getZExtValue() ==
8552 // We've found another LVSL/LVSR, and this address is an aligned
8553 // multiple of that one. The results will be the same, so use the
8554 // one we've just found instead.
8556 return SDValue(*UI, 0);
8565 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
8566 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
8567 N->getOperand(0).hasOneUse() &&
8568 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 ||
8569 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
8570 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
8571 N->getValueType(0) == MVT::i64))) {
8572 SDValue Load = N->getOperand(0);
8573 LoadSDNode *LD = cast<LoadSDNode>(Load);
8574 // Create the byte-swapping load.
8576 LD->getChain(), // Chain
8577 LD->getBasePtr(), // Ptr
8578 DAG.getValueType(N->getValueType(0)) // VT
8581 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
8582 DAG.getVTList(N->getValueType(0) == MVT::i64 ?
8583 MVT::i64 : MVT::i32, MVT::Other),
8584 Ops, LD->getMemoryVT(), LD->getMemOperand());
8586 // If this is an i16 load, insert the truncate.
8587 SDValue ResVal = BSLoad;
8588 if (N->getValueType(0) == MVT::i16)
8589 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
8591 // First, combine the bswap away. This makes the value produced by the
8593 DCI.CombineTo(N, ResVal);
8595 // Next, combine the load away, we give it a bogus result value but a real
8596 // chain result. The result value is dead because the bswap is dead.
8597 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
8599 // Return N so it doesn't get rechecked!
8600 return SDValue(N, 0);
8604 case PPCISD::VCMP: {
8605 // If a VCMPo node already exists with exactly the same operands as this
8606 // node, use its result instead of this node (VCMPo computes both a CR6 and
8607 // a normal output).
8609 if (!N->getOperand(0).hasOneUse() &&
8610 !N->getOperand(1).hasOneUse() &&
8611 !N->getOperand(2).hasOneUse()) {
8613 // Scan all of the users of the LHS, looking for VCMPo's that match.
8614 SDNode *VCMPoNode = nullptr;
8616 SDNode *LHSN = N->getOperand(0).getNode();
8617 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
8619 if (UI->getOpcode() == PPCISD::VCMPo &&
8620 UI->getOperand(1) == N->getOperand(1) &&
8621 UI->getOperand(2) == N->getOperand(2) &&
8622 UI->getOperand(0) == N->getOperand(0)) {
8627 // If there is no VCMPo node, or if the flag value has a single use, don't
8629 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
8632 // Look at the (necessarily single) use of the flag value. If it has a
8633 // chain, this transformation is more complex. Note that multiple things
8634 // could use the value result, which we should ignore.
8635 SDNode *FlagUser = nullptr;
8636 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
8637 FlagUser == nullptr; ++UI) {
8638 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
8640 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
8641 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
8648 // If the user is a MFOCRF instruction, we know this is safe.
8649 // Otherwise we give up for right now.
8650 if (FlagUser->getOpcode() == PPCISD::MFOCRF)
8651 return SDValue(VCMPoNode, 0);
8656 SDValue Cond = N->getOperand(1);
8657 SDValue Target = N->getOperand(2);
8659 if (Cond.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
8660 cast<ConstantSDNode>(Cond.getOperand(1))->getZExtValue() ==
8661 Intrinsic::ppc_is_decremented_ctr_nonzero) {
8663 // We now need to make the intrinsic dead (it cannot be instruction
8665 DAG.ReplaceAllUsesOfValueWith(Cond.getValue(1), Cond.getOperand(0));
8666 assert(Cond.getNode()->hasOneUse() &&
8667 "Counter decrement has more than one use");
8669 return DAG.getNode(PPCISD::BDNZ, dl, MVT::Other,
8670 N->getOperand(0), Target);
8675 // If this is a branch on an altivec predicate comparison, lower this so
8676 // that we don't have to do a MFOCRF: instead, branch directly on CR6. This
8677 // lowering is done pre-legalize, because the legalizer lowers the predicate
8678 // compare down to code that is difficult to reassemble.
8679 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
8680 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
8682 // Sometimes the promoted value of the intrinsic is ANDed by some non-zero
8683 // value. If so, pass-through the AND to get to the intrinsic.
8684 if (LHS.getOpcode() == ISD::AND &&
8685 LHS.getOperand(0).getOpcode() == ISD::INTRINSIC_W_CHAIN &&
8686 cast<ConstantSDNode>(LHS.getOperand(0).getOperand(1))->getZExtValue() ==
8687 Intrinsic::ppc_is_decremented_ctr_nonzero &&
8688 isa<ConstantSDNode>(LHS.getOperand(1)) &&
8689 !cast<ConstantSDNode>(LHS.getOperand(1))->getConstantIntValue()->
8691 LHS = LHS.getOperand(0);
8693 if (LHS.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
8694 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() ==
8695 Intrinsic::ppc_is_decremented_ctr_nonzero &&
8696 isa<ConstantSDNode>(RHS)) {
8697 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
8698 "Counter decrement comparison is not EQ or NE");
8700 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
8701 bool isBDNZ = (CC == ISD::SETEQ && Val) ||
8702 (CC == ISD::SETNE && !Val);
8704 // We now need to make the intrinsic dead (it cannot be instruction
8706 DAG.ReplaceAllUsesOfValueWith(LHS.getValue(1), LHS.getOperand(0));
8707 assert(LHS.getNode()->hasOneUse() &&
8708 "Counter decrement has more than one use");
8710 return DAG.getNode(isBDNZ ? PPCISD::BDNZ : PPCISD::BDZ, dl, MVT::Other,
8711 N->getOperand(0), N->getOperand(4));
8717 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
8718 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
8719 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
8720 assert(isDot && "Can't compare against a vector result!");
8722 // If this is a comparison against something other than 0/1, then we know
8723 // that the condition is never/always true.
8724 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
8725 if (Val != 0 && Val != 1) {
8726 if (CC == ISD::SETEQ) // Cond never true, remove branch.
8727 return N->getOperand(0);
8728 // Always !=, turn it into an unconditional branch.
8729 return DAG.getNode(ISD::BR, dl, MVT::Other,
8730 N->getOperand(0), N->getOperand(4));
8733 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
8735 // Create the PPCISD altivec 'dot' comparison node.
8737 LHS.getOperand(2), // LHS of compare
8738 LHS.getOperand(3), // RHS of compare
8739 DAG.getConstant(CompareOpc, MVT::i32)
8741 EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue };
8742 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
8744 // Unpack the result based on how the target uses it.
8745 PPC::Predicate CompOpc;
8746 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
8747 default: // Can't happen, don't crash on invalid number though.
8748 case 0: // Branch on the value of the EQ bit of CR6.
8749 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
8751 case 1: // Branch on the inverted value of the EQ bit of CR6.
8752 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
8754 case 2: // Branch on the value of the LT bit of CR6.
8755 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
8757 case 3: // Branch on the inverted value of the LT bit of CR6.
8758 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
8762 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
8763 DAG.getConstant(CompOpc, MVT::i32),
8764 DAG.getRegister(PPC::CR6, MVT::i32),
8765 N->getOperand(4), CompNode.getValue(1));
8774 //===----------------------------------------------------------------------===//
8775 // Inline Assembly Support
8776 //===----------------------------------------------------------------------===//
8778 void PPCTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
8781 const SelectionDAG &DAG,
8782 unsigned Depth) const {
8783 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
8784 switch (Op.getOpcode()) {
8786 case PPCISD::LBRX: {
8787 // lhbrx is known to have the top bits cleared out.
8788 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
8789 KnownZero = 0xFFFF0000;
8792 case ISD::INTRINSIC_WO_CHAIN: {
8793 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
8795 case Intrinsic::ppc_altivec_vcmpbfp_p:
8796 case Intrinsic::ppc_altivec_vcmpeqfp_p:
8797 case Intrinsic::ppc_altivec_vcmpequb_p:
8798 case Intrinsic::ppc_altivec_vcmpequh_p:
8799 case Intrinsic::ppc_altivec_vcmpequw_p:
8800 case Intrinsic::ppc_altivec_vcmpgefp_p:
8801 case Intrinsic::ppc_altivec_vcmpgtfp_p:
8802 case Intrinsic::ppc_altivec_vcmpgtsb_p:
8803 case Intrinsic::ppc_altivec_vcmpgtsh_p:
8804 case Intrinsic::ppc_altivec_vcmpgtsw_p:
8805 case Intrinsic::ppc_altivec_vcmpgtub_p:
8806 case Intrinsic::ppc_altivec_vcmpgtuh_p:
8807 case Intrinsic::ppc_altivec_vcmpgtuw_p:
8808 KnownZero = ~1U; // All bits but the low one are known to be zero.
8816 /// getConstraintType - Given a constraint, return the type of
8817 /// constraint it is for this target.
8818 PPCTargetLowering::ConstraintType
8819 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
8820 if (Constraint.size() == 1) {
8821 switch (Constraint[0]) {
8828 return C_RegisterClass;
8830 // FIXME: While Z does indicate a memory constraint, it specifically
8831 // indicates an r+r address (used in conjunction with the 'y' modifier
8832 // in the replacement string). Currently, we're forcing the base
8833 // register to be r0 in the asm printer (which is interpreted as zero)
8834 // and forming the complete address in the second register. This is
8838 } else if (Constraint == "wc") { // individual CR bits.
8839 return C_RegisterClass;
8840 } else if (Constraint == "wa" || Constraint == "wd" ||
8841 Constraint == "wf" || Constraint == "ws") {
8842 return C_RegisterClass; // VSX registers.
8844 return TargetLowering::getConstraintType(Constraint);
8847 /// Examine constraint type and operand type and determine a weight value.
8848 /// This object must already have been set up with the operand type
8849 /// and the current alternative constraint selected.
8850 TargetLowering::ConstraintWeight
8851 PPCTargetLowering::getSingleConstraintMatchWeight(
8852 AsmOperandInfo &info, const char *constraint) const {
8853 ConstraintWeight weight = CW_Invalid;
8854 Value *CallOperandVal = info.CallOperandVal;
8855 // If we don't have a value, we can't do a match,
8856 // but allow it at the lowest weight.
8857 if (!CallOperandVal)
8859 Type *type = CallOperandVal->getType();
8861 // Look at the constraint type.
8862 if (StringRef(constraint) == "wc" && type->isIntegerTy(1))
8863 return CW_Register; // an individual CR bit.
8864 else if ((StringRef(constraint) == "wa" ||
8865 StringRef(constraint) == "wd" ||
8866 StringRef(constraint) == "wf") &&
8869 else if (StringRef(constraint) == "ws" && type->isDoubleTy())
8872 switch (*constraint) {
8874 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
8877 if (type->isIntegerTy())
8878 weight = CW_Register;
8881 if (type->isFloatTy())
8882 weight = CW_Register;
8885 if (type->isDoubleTy())
8886 weight = CW_Register;
8889 if (type->isVectorTy())
8890 weight = CW_Register;
8893 weight = CW_Register;
8902 std::pair<unsigned, const TargetRegisterClass*>
8903 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
8905 if (Constraint.size() == 1) {
8906 // GCC RS6000 Constraint Letters
8907 switch (Constraint[0]) {
8909 if (VT == MVT::i64 && Subtarget.isPPC64())
8910 return std::make_pair(0U, &PPC::G8RC_NOX0RegClass);
8911 return std::make_pair(0U, &PPC::GPRC_NOR0RegClass);
8913 if (VT == MVT::i64 && Subtarget.isPPC64())
8914 return std::make_pair(0U, &PPC::G8RCRegClass);
8915 return std::make_pair(0U, &PPC::GPRCRegClass);
8917 if (VT == MVT::f32 || VT == MVT::i32)
8918 return std::make_pair(0U, &PPC::F4RCRegClass);
8919 if (VT == MVT::f64 || VT == MVT::i64)
8920 return std::make_pair(0U, &PPC::F8RCRegClass);
8923 return std::make_pair(0U, &PPC::VRRCRegClass);
8925 return std::make_pair(0U, &PPC::CRRCRegClass);
8927 } else if (Constraint == "wc") { // an individual CR bit.
8928 return std::make_pair(0U, &PPC::CRBITRCRegClass);
8929 } else if (Constraint == "wa" || Constraint == "wd" ||
8930 Constraint == "wf") {
8931 return std::make_pair(0U, &PPC::VSRCRegClass);
8932 } else if (Constraint == "ws") {
8933 return std::make_pair(0U, &PPC::VSFRCRegClass);
8936 std::pair<unsigned, const TargetRegisterClass*> R =
8937 TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
8939 // r[0-9]+ are used, on PPC64, to refer to the corresponding 64-bit registers
8940 // (which we call X[0-9]+). If a 64-bit value has been requested, and a
8941 // 32-bit GPR has been selected, then 'upgrade' it to the 64-bit parent
8943 // FIXME: If TargetLowering::getRegForInlineAsmConstraint could somehow use
8944 // the AsmName field from *RegisterInfo.td, then this would not be necessary.
8945 if (R.first && VT == MVT::i64 && Subtarget.isPPC64() &&
8946 PPC::GPRCRegClass.contains(R.first)) {
8947 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
8948 return std::make_pair(TRI->getMatchingSuperReg(R.first,
8949 PPC::sub_32, &PPC::G8RCRegClass),
8950 &PPC::G8RCRegClass);
8957 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
8958 /// vector. If it is invalid, don't add anything to Ops.
8959 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
8960 std::string &Constraint,
8961 std::vector<SDValue>&Ops,
8962 SelectionDAG &DAG) const {
8965 // Only support length 1 constraints.
8966 if (Constraint.length() > 1) return;
8968 char Letter = Constraint[0];
8979 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
8980 if (!CST) return; // Must be an immediate to match.
8981 unsigned Value = CST->getZExtValue();
8983 default: llvm_unreachable("Unknown constraint letter!");
8984 case 'I': // "I" is a signed 16-bit constant.
8985 if ((short)Value == (int)Value)
8986 Result = DAG.getTargetConstant(Value, Op.getValueType());
8988 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
8989 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
8990 if ((short)Value == 0)
8991 Result = DAG.getTargetConstant(Value, Op.getValueType());
8993 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
8994 if ((Value >> 16) == 0)
8995 Result = DAG.getTargetConstant(Value, Op.getValueType());
8997 case 'M': // "M" is a constant that is greater than 31.
8999 Result = DAG.getTargetConstant(Value, Op.getValueType());
9001 case 'N': // "N" is a positive constant that is an exact power of two.
9002 if ((int)Value > 0 && isPowerOf2_32(Value))
9003 Result = DAG.getTargetConstant(Value, Op.getValueType());
9005 case 'O': // "O" is the constant zero.
9007 Result = DAG.getTargetConstant(Value, Op.getValueType());
9009 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
9010 if ((short)-Value == (int)-Value)
9011 Result = DAG.getTargetConstant(Value, Op.getValueType());
9018 if (Result.getNode()) {
9019 Ops.push_back(Result);
9023 // Handle standard constraint letters.
9024 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
9027 // isLegalAddressingMode - Return true if the addressing mode represented
9028 // by AM is legal for this target, for a load/store of the specified type.
9029 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
9031 // FIXME: PPC does not allow r+i addressing modes for vectors!
9033 // PPC allows a sign-extended 16-bit immediate field.
9034 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
9037 // No global is ever allowed as a base.
9041 // PPC only support r+r,
9043 case 0: // "r+i" or just "i", depending on HasBaseReg.
9046 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
9048 // Otherwise we have r+r or r+i.
9051 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
9053 // Allow 2*r as r+r.
9056 // No other scales are supported.
9063 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
9064 SelectionDAG &DAG) const {
9065 MachineFunction &MF = DAG.getMachineFunction();
9066 MachineFrameInfo *MFI = MF.getFrameInfo();
9067 MFI->setReturnAddressIsTaken(true);
9069 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
9073 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9075 // Make sure the function does not optimize away the store of the RA to
9077 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
9078 FuncInfo->setLRStoreRequired();
9079 bool isPPC64 = Subtarget.isPPC64();
9080 bool isDarwinABI = Subtarget.isDarwinABI();
9083 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
9086 DAG.getConstant(PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI),
9087 isPPC64? MVT::i64 : MVT::i32);
9088 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9089 DAG.getNode(ISD::ADD, dl, getPointerTy(),
9091 MachinePointerInfo(), false, false, false, 0);
9094 // Just load the return address off the stack.
9095 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
9096 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9097 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
9100 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
9101 SelectionDAG &DAG) const {
9103 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9105 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
9106 bool isPPC64 = PtrVT == MVT::i64;
9108 MachineFunction &MF = DAG.getMachineFunction();
9109 MachineFrameInfo *MFI = MF.getFrameInfo();
9110 MFI->setFrameAddressIsTaken(true);
9112 // Naked functions never have a frame pointer, and so we use r1. For all
9113 // other functions, this decision must be delayed until during PEI.
9115 if (MF.getFunction()->getAttributes().hasAttribute(
9116 AttributeSet::FunctionIndex, Attribute::Naked))
9117 FrameReg = isPPC64 ? PPC::X1 : PPC::R1;
9119 FrameReg = isPPC64 ? PPC::FP8 : PPC::FP;
9121 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
9124 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
9125 FrameAddr, MachinePointerInfo(), false, false,
9130 // FIXME? Maybe this could be a TableGen attribute on some registers and
9131 // this table could be generated automatically from RegInfo.
9132 unsigned PPCTargetLowering::getRegisterByName(const char* RegName,
9134 bool isPPC64 = Subtarget.isPPC64();
9135 bool isDarwinABI = Subtarget.isDarwinABI();
9137 if ((isPPC64 && VT != MVT::i64 && VT != MVT::i32) ||
9138 (!isPPC64 && VT != MVT::i32))
9139 report_fatal_error("Invalid register global variable type");
9141 bool is64Bit = isPPC64 && VT == MVT::i64;
9142 unsigned Reg = StringSwitch<unsigned>(RegName)
9143 .Case("r1", is64Bit ? PPC::X1 : PPC::R1)
9144 .Case("r2", isDarwinABI ? 0 : (is64Bit ? PPC::X2 : PPC::R2))
9145 .Case("r13", (!isPPC64 && isDarwinABI) ? 0 :
9146 (is64Bit ? PPC::X13 : PPC::R13))
9151 report_fatal_error("Invalid register name global variable");
9155 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
9156 // The PowerPC target isn't yet aware of offsets.
9160 /// getOptimalMemOpType - Returns the target specific optimal type for load
9161 /// and store operations as a result of memset, memcpy, and memmove
9162 /// lowering. If DstAlign is zero that means it's safe to destination
9163 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
9164 /// means there isn't a need to check it against alignment requirement,
9165 /// probably because the source does not need to be loaded. If 'IsMemset' is
9166 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
9167 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
9168 /// source is constant so it does not need to be loaded.
9169 /// It returns EVT::Other if the type should be determined using generic
9170 /// target-independent logic.
9171 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size,
9172 unsigned DstAlign, unsigned SrcAlign,
9173 bool IsMemset, bool ZeroMemset,
9175 MachineFunction &MF) const {
9176 if (Subtarget.isPPC64()) {
9183 /// \brief Returns true if it is beneficial to convert a load of a constant
9184 /// to just the constant itself.
9185 bool PPCTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
9187 assert(Ty->isIntegerTy());
9189 unsigned BitSize = Ty->getPrimitiveSizeInBits();
9190 if (BitSize == 0 || BitSize > 64)
9195 bool PPCTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
9196 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
9198 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
9199 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
9200 return NumBits1 == 64 && NumBits2 == 32;
9203 bool PPCTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
9204 if (!VT1.isInteger() || !VT2.isInteger())
9206 unsigned NumBits1 = VT1.getSizeInBits();
9207 unsigned NumBits2 = VT2.getSizeInBits();
9208 return NumBits1 == 64 && NumBits2 == 32;
9211 bool PPCTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
9212 return isInt<16>(Imm) || isUInt<16>(Imm);
9215 bool PPCTargetLowering::isLegalAddImmediate(int64_t Imm) const {
9216 return isInt<16>(Imm) || isUInt<16>(Imm);
9219 bool PPCTargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
9222 if (DisablePPCUnaligned)
9225 // PowerPC supports unaligned memory access for simple non-vector types.
9226 // Although accessing unaligned addresses is not as efficient as accessing
9227 // aligned addresses, it is generally more efficient than manual expansion,
9228 // and generally only traps for software emulation when crossing page
9234 if (VT.getSimpleVT().isVector()) {
9235 if (Subtarget.hasVSX()) {
9236 if (VT != MVT::v2f64 && VT != MVT::v2i64)
9243 if (VT == MVT::ppcf128)
9252 bool PPCTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
9253 VT = VT.getScalarType();
9258 switch (VT.getSimpleVT().SimpleTy) {
9270 PPCTargetLowering::shouldExpandBuildVectorWithShuffles(
9271 EVT VT , unsigned DefinedValues) const {
9272 if (VT == MVT::v2i64)
9275 return TargetLowering::shouldExpandBuildVectorWithShuffles(VT, DefinedValues);
9278 Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const {
9279 if (DisableILPPref || Subtarget.enableMachineScheduler())
9280 return TargetLowering::getSchedulingPreference(N);
9285 // Create a fast isel object.
9287 PPCTargetLowering::createFastISel(FunctionLoweringInfo &FuncInfo,
9288 const TargetLibraryInfo *LibInfo) const {
9289 return PPC::createFastISel(FuncInfo, LibInfo);