1 //===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that PPC uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
16 #define LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
19 #include "PPCInstrInfo.h"
20 #include "PPCRegisterInfo.h"
21 #include "PPCSubtarget.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/Target/TargetLowering.h"
29 // Start the numbering where the builtin ops and target ops leave off.
30 FIRST_NUMBER = ISD::BUILTIN_OP_END,
32 /// FSEL - Traditional three-operand fsel node.
36 /// FCFID - The FCFID instruction, taking an f64 operand and producing
37 /// and f64 value containing the FP representation of the integer that
38 /// was temporarily in the f64 operand.
41 /// Newer FCFID[US] integer-to-floating-point conversion instructions for
42 /// unsigned integers and single-precision outputs.
43 FCFIDU, FCFIDS, FCFIDUS,
45 /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64
46 /// operand, producing an f64 value containing the integer representation
50 /// Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for
51 /// unsigned integers.
54 /// Reciprocal estimate instructions (unary FP ops).
57 // VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking
58 // three v4f32 operands and producing a v4f32 result.
61 /// VPERM - The PPC VPERM Instruction.
65 /// Hi/Lo - These represent the high and low 16-bit parts of a global
66 /// address respectively. These nodes have two operands, the first of
67 /// which must be a TargetGlobalAddress, and the second of which must be a
68 /// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C',
69 /// though these are usually folded into other nodes.
74 /// The following three target-specific nodes are used for calls through
75 /// function pointers in the 64-bit SVR4 ABI.
77 /// Restore the TOC from the TOC save area of the current stack frame.
78 /// This is basically a hard coded load instruction which additionally
79 /// takes/produces a flag.
82 /// Like a regular LOAD but additionally taking/producing a flag.
85 /// LOAD into r2 (also taking/producing a flag). Like TOC_RESTORE, this is
86 /// a hard coded load instruction.
89 /// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX)
90 /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to
91 /// compute an allocation on the stack.
94 /// GlobalBaseReg - On Darwin, this node represents the result of the mflr
95 /// at function entry, used for PIC code.
98 /// These nodes represent the 32-bit PPC shifts that operate on 6-bit
99 /// shift amounts. These nodes are generated by the multi-precision shift
103 /// CALL - A direct function call.
104 /// CALL_NOP is a call with the special NOP which follows 64-bit
108 /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a
109 /// MTCTR instruction.
112 /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a
113 /// BCTRL instruction.
116 /// Return with a flag operand, matched by 'blr'
119 /// R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
120 /// This copies the bits corresponding to the specified CRREG into the
121 /// resultant GPR. Bits corresponding to other CR regs are undefined.
124 // EH_SJLJ_SETJMP - SjLj exception handling setjmp.
127 // EH_SJLJ_LONGJMP - SjLj exception handling longjmp.
130 /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP*
131 /// instructions. For lack of better number, we use the opcode number
132 /// encoding for the OPC field to identify the compare. For example, 838
136 /// RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the
137 /// altivec VCMP*o instructions. For lack of better number, we use the
138 /// opcode number encoding for the OPC field to identify the compare. For
139 /// example, 838 is VCMPGTSH.
142 /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This
143 /// corresponds to the COND_BRANCH pseudo instruction. CRRC is the
144 /// condition register to branch on, OPC is the branch opcode to use (e.g.
145 /// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is
146 /// an optional input flag argument.
149 /// CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based
153 /// F8RC = FADDRTZ F8RC, F8RC - This is an FADD done with rounding
154 /// towards zero. Used only as part of the long double-to-int
155 /// conversion sequence.
158 /// F8RC = MFFS - This moves the FPSCR (not modeled) into the register.
161 /// LARX = This corresponds to PPC l{w|d}arx instrcution: load and
162 /// reserve indexed. This is used to implement atomic operations.
165 /// STCX = This corresponds to PPC stcx. instrcution: store conditional
166 /// indexed. This is used to implement atomic operations.
169 /// TC_RETURN - A tail call return.
171 /// operand #1 callee (register or absolute)
172 /// operand #2 stack adjustment
173 /// operand #3 optional in flag
176 /// ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls
182 /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by general dynamic and
183 /// local dynamic TLS on PPC32.
186 /// G8RC = ADDIS_GOT_TPREL_HA %X2, Symbol - Used by the initial-exec
187 /// TLS model, produces an ADDIS8 instruction that adds the GOT
188 /// base to sym\@got\@tprel\@ha.
191 /// G8RC = LD_GOT_TPREL_L Symbol, G8RReg - Used by the initial-exec
192 /// TLS model, produces a LD instruction with base register G8RReg
193 /// and offset sym\@got\@tprel\@l. This completes the addition that
194 /// finds the offset of "sym" relative to the thread pointer.
197 /// G8RC = ADD_TLS G8RReg, Symbol - Used by the initial-exec TLS
198 /// model, produces an ADD instruction that adds the contents of
199 /// G8RReg to the thread pointer. Symbol contains a relocation
200 /// sym\@tls which is to be replaced by the thread pointer and
201 /// identifies to the linker that the instruction is part of a
205 /// G8RC = ADDIS_TLSGD_HA %X2, Symbol - For the general-dynamic TLS
206 /// model, produces an ADDIS8 instruction that adds the GOT base
207 /// register to sym\@got\@tlsgd\@ha.
210 /// G8RC = ADDI_TLSGD_L G8RReg, Symbol - For the general-dynamic TLS
211 /// model, produces an ADDI8 instruction that adds G8RReg to
212 /// sym\@got\@tlsgd\@l.
215 /// G8RC = GET_TLS_ADDR %X3, Symbol - For the general-dynamic TLS
216 /// model, produces a call to __tls_get_addr(sym\@tlsgd).
219 /// G8RC = ADDIS_TLSLD_HA %X2, Symbol - For the local-dynamic TLS
220 /// model, produces an ADDIS8 instruction that adds the GOT base
221 /// register to sym\@got\@tlsld\@ha.
224 /// G8RC = ADDI_TLSLD_L G8RReg, Symbol - For the local-dynamic TLS
225 /// model, produces an ADDI8 instruction that adds G8RReg to
226 /// sym\@got\@tlsld\@l.
229 /// G8RC = GET_TLSLD_ADDR %X3, Symbol - For the local-dynamic TLS
230 /// model, produces a call to __tls_get_addr(sym\@tlsld).
233 /// G8RC = ADDIS_DTPREL_HA %X3, Symbol, Chain - For the
234 /// local-dynamic TLS model, produces an ADDIS8 instruction
235 /// that adds X3 to sym\@dtprel\@ha. The Chain operand is needed
236 /// to tie this in place following a copy to %X3 from the result
237 /// of a GET_TLSLD_ADDR.
240 /// G8RC = ADDI_DTPREL_L G8RReg, Symbol - For the local-dynamic TLS
241 /// model, produces an ADDI8 instruction that adds G8RReg to
242 /// sym\@got\@dtprel\@l.
245 /// VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded
246 /// during instruction selection to optimize a BUILD_VECTOR into
247 /// operations on splats. This is necessary to avoid losing these
248 /// optimizations due to constant folding.
251 /// CHAIN = SC CHAIN, Imm128 - System call. The 7-bit unsigned
252 /// operand identifies the operating system entry point.
255 /// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a
256 /// byte-swapping store instruction. It byte-swaps the low "Type" bits of
257 /// the GPRC input, then stores it through Ptr. Type can be either i16 or
259 STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE,
261 /// GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a
262 /// byte-swapping load instruction. It loads "Type" bits, byte swaps it,
263 /// then puts it in the bottom bits of the GPRC. TYPE can be either i16
267 /// STFIWX - The STFIWX instruction. The first operand is an input token
268 /// chain, then an f64 value to store, then an address to store it to.
271 /// GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point
272 /// load which sign-extends from a 32-bit integer value into the
273 /// destination 64-bit register.
276 /// GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point
277 /// load which zero-extends from a 32-bit integer value into the
278 /// destination 64-bit register.
281 /// G8RC = ADDIS_TOC_HA %X2, Symbol - For medium and large code model,
282 /// produces an ADDIS8 instruction that adds the TOC base register to
286 /// G8RC = LD_TOC_L Symbol, G8RReg - For medium and large code model,
287 /// produces a LD instruction with base register G8RReg and offset
288 /// sym\@toc\@l. Preceded by an ADDIS_TOC_HA to form a full 32-bit offset.
291 /// G8RC = ADDI_TOC_L G8RReg, Symbol - For medium code model, produces
292 /// an ADDI8 instruction that adds G8RReg to sym\@toc\@l.
293 /// Preceded by an ADDIS_TOC_HA to form a full 32-bit offset.
298 /// Define some predicates that are used for node matching.
300 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
301 /// VPKUHUM instruction.
302 bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary);
304 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
305 /// VPKUWUM instruction.
306 bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary);
308 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
309 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
310 bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
313 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
314 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
315 bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
318 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
319 /// amount, otherwise return -1.
320 int isVSLDOIShuffleMask(SDNode *N, bool isUnary);
322 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
323 /// specifies a splat of a single element that is suitable for input to
324 /// VSPLTB/VSPLTH/VSPLTW.
325 bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize);
327 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
329 bool isAllNegativeZeroVector(SDNode *N);
331 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
332 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
333 unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize);
335 /// get_VSPLTI_elt - If this is a build_vector of constants which can be
336 /// formed by using a vspltis[bhw] instruction of the specified element
337 /// size, return the constant being splatted. The ByteSize field indicates
338 /// the number of bytes of each element [124] -> [bhw].
339 SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
342 class PPCTargetLowering : public TargetLowering {
343 const PPCSubtarget &PPCSubTarget;
346 explicit PPCTargetLowering(PPCTargetMachine &TM);
348 /// getTargetNodeName() - This method returns the name of a target specific
350 virtual const char *getTargetNodeName(unsigned Opcode) const;
352 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
354 /// getSetCCResultType - Return the ISD::SETCC ValueType
355 virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
357 /// getPreIndexedAddressParts - returns true by value, base pointer and
358 /// offset pointer and addressing mode by reference if the node's address
359 /// can be legally represented as pre-indexed load / store address.
360 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
362 ISD::MemIndexedMode &AM,
363 SelectionDAG &DAG) const;
365 /// SelectAddressRegReg - Given the specified addressed, check to see if it
366 /// can be represented as an indexed [r+r] operation. Returns false if it
367 /// can be more efficiently represented with [r+imm].
368 bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index,
369 SelectionDAG &DAG) const;
371 /// SelectAddressRegImm - Returns true if the address N can be represented
372 /// by a base register plus a signed 16-bit displacement [r+imm], and if it
373 /// is not better represented as reg+reg. If Aligned is true, only accept
374 /// displacements suitable for STD and friends, i.e. multiples of 4.
375 bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base,
376 SelectionDAG &DAG, bool Aligned) const;
378 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
379 /// represented as an indexed [r+r] operation.
380 bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index,
381 SelectionDAG &DAG) const;
383 Sched::Preference getSchedulingPreference(SDNode *N) const;
385 /// LowerOperation - Provide custom lowering hooks for some operations.
387 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
389 /// ReplaceNodeResults - Replace the results of node with an illegal result
390 /// type with new values built out of custom code.
392 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
393 SelectionDAG &DAG) const;
395 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
397 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
400 const SelectionDAG &DAG,
401 unsigned Depth = 0) const;
403 virtual MachineBasicBlock *
404 EmitInstrWithCustomInserter(MachineInstr *MI,
405 MachineBasicBlock *MBB) const;
406 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI,
407 MachineBasicBlock *MBB, bool is64Bit,
408 unsigned BinOpcode) const;
409 MachineBasicBlock *EmitPartwordAtomicBinary(MachineInstr *MI,
410 MachineBasicBlock *MBB,
411 bool is8bit, unsigned Opcode) const;
413 MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr *MI,
414 MachineBasicBlock *MBB) const;
416 MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr *MI,
417 MachineBasicBlock *MBB) const;
419 ConstraintType getConstraintType(const std::string &Constraint) const;
421 /// Examine constraint string and operand type and determine a weight value.
422 /// The operand object must already have been set up with the operand type.
423 ConstraintWeight getSingleConstraintMatchWeight(
424 AsmOperandInfo &info, const char *constraint) const;
426 std::pair<unsigned, const TargetRegisterClass*>
427 getRegForInlineAsmConstraint(const std::string &Constraint,
430 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
431 /// function arguments in the caller parameter area. This is the actual
432 /// alignment, not its logarithm.
433 unsigned getByValTypeAlignment(Type *Ty) const;
435 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
436 /// vector. If it is invalid, don't add anything to Ops.
437 virtual void LowerAsmOperandForConstraint(SDValue Op,
438 std::string &Constraint,
439 std::vector<SDValue> &Ops,
440 SelectionDAG &DAG) const;
442 /// isLegalAddressingMode - Return true if the addressing mode represented
443 /// by AM is legal for this target, for a load/store of the specified type.
444 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const;
446 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
448 /// getOptimalMemOpType - Returns the target specific optimal type for load
449 /// and store operations as a result of memset, memcpy, and memmove
450 /// lowering. If DstAlign is zero that means it's safe to destination
451 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
452 /// means there isn't a need to check it against alignment requirement,
453 /// probably because the source does not need to be loaded. If 'IsMemset' is
454 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
455 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
456 /// source is constant so it does not need to be loaded.
457 /// It returns EVT::Other if the type should be determined using generic
458 /// target-independent logic.
460 getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
461 bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
462 MachineFunction &MF) const;
464 /// Is unaligned memory access allowed for the given type, and is it fast
465 /// relative to software emulation.
466 virtual bool allowsUnalignedMemoryAccesses(EVT VT, bool *Fast = 0) const;
468 /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
469 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
470 /// expanded to FMAs when this method returns true, otherwise fmuladd is
471 /// expanded to fmul + fadd.
472 virtual bool isFMAFasterThanFMulAndFAdd(EVT VT) const;
474 /// createFastISel - This method returns a target-specific FastISel object,
475 /// or null if the target does not support "fast" instruction selection.
476 virtual FastISel *createFastISel(FunctionLoweringInfo &FuncInfo,
477 const TargetLibraryInfo *LibInfo) const;
480 SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const;
481 SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const;
484 IsEligibleForTailCallOptimization(SDValue Callee,
485 CallingConv::ID CalleeCC,
487 const SmallVectorImpl<ISD::InputArg> &Ins,
488 SelectionDAG& DAG) const;
490 SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
498 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
499 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
500 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
501 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
502 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
503 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
504 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
505 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
506 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
507 SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
508 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
509 const PPCSubtarget &Subtarget) const;
510 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG,
511 const PPCSubtarget &Subtarget) const;
512 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG,
513 const PPCSubtarget &Subtarget) const;
514 SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
515 const PPCSubtarget &Subtarget) const;
516 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG,
517 const PPCSubtarget &Subtarget) const;
518 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
519 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, SDLoc dl) const;
520 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
521 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
522 SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const;
523 SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const;
524 SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const;
525 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
526 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
527 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
528 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
529 SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;
531 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
532 CallingConv::ID CallConv, bool isVarArg,
533 const SmallVectorImpl<ISD::InputArg> &Ins,
534 SDLoc dl, SelectionDAG &DAG,
535 SmallVectorImpl<SDValue> &InVals) const;
536 SDValue FinishCall(CallingConv::ID CallConv, SDLoc dl, bool isTailCall,
539 SmallVector<std::pair<unsigned, SDValue>, 8>
541 SDValue InFlag, SDValue Chain,
543 int SPDiff, unsigned NumBytes,
544 const SmallVectorImpl<ISD::InputArg> &Ins,
545 SmallVectorImpl<SDValue> &InVals) const;
548 LowerFormalArguments(SDValue Chain,
549 CallingConv::ID CallConv, bool isVarArg,
550 const SmallVectorImpl<ISD::InputArg> &Ins,
551 SDLoc dl, SelectionDAG &DAG,
552 SmallVectorImpl<SDValue> &InVals) const;
555 LowerCall(TargetLowering::CallLoweringInfo &CLI,
556 SmallVectorImpl<SDValue> &InVals) const;
559 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
561 const SmallVectorImpl<ISD::OutputArg> &Outs,
562 LLVMContext &Context) const;
565 LowerReturn(SDValue Chain,
566 CallingConv::ID CallConv, bool isVarArg,
567 const SmallVectorImpl<ISD::OutputArg> &Outs,
568 const SmallVectorImpl<SDValue> &OutVals,
569 SDLoc dl, SelectionDAG &DAG) const;
572 extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT, SelectionDAG &DAG,
573 SDValue ArgVal, SDLoc dl) const;
576 setMinReservedArea(MachineFunction &MF, SelectionDAG &DAG,
577 unsigned nAltivecParamsAtEnd,
578 unsigned MinReservedArea, bool isPPC64) const;
581 LowerFormalArguments_Darwin(SDValue Chain,
582 CallingConv::ID CallConv, bool isVarArg,
583 const SmallVectorImpl<ISD::InputArg> &Ins,
584 SDLoc dl, SelectionDAG &DAG,
585 SmallVectorImpl<SDValue> &InVals) const;
587 LowerFormalArguments_64SVR4(SDValue Chain,
588 CallingConv::ID CallConv, bool isVarArg,
589 const SmallVectorImpl<ISD::InputArg> &Ins,
590 SDLoc dl, SelectionDAG &DAG,
591 SmallVectorImpl<SDValue> &InVals) const;
593 LowerFormalArguments_32SVR4(SDValue Chain,
594 CallingConv::ID CallConv, bool isVarArg,
595 const SmallVectorImpl<ISD::InputArg> &Ins,
596 SDLoc dl, SelectionDAG &DAG,
597 SmallVectorImpl<SDValue> &InVals) const;
600 createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
601 SDValue CallSeqStart, ISD::ArgFlagsTy Flags,
602 SelectionDAG &DAG, SDLoc dl) const;
605 LowerCall_Darwin(SDValue Chain, SDValue Callee,
606 CallingConv::ID CallConv,
607 bool isVarArg, bool isTailCall,
608 const SmallVectorImpl<ISD::OutputArg> &Outs,
609 const SmallVectorImpl<SDValue> &OutVals,
610 const SmallVectorImpl<ISD::InputArg> &Ins,
611 SDLoc dl, SelectionDAG &DAG,
612 SmallVectorImpl<SDValue> &InVals) const;
614 LowerCall_64SVR4(SDValue Chain, SDValue Callee,
615 CallingConv::ID CallConv,
616 bool isVarArg, bool isTailCall,
617 const SmallVectorImpl<ISD::OutputArg> &Outs,
618 const SmallVectorImpl<SDValue> &OutVals,
619 const SmallVectorImpl<ISD::InputArg> &Ins,
620 SDLoc dl, SelectionDAG &DAG,
621 SmallVectorImpl<SDValue> &InVals) const;
623 LowerCall_32SVR4(SDValue Chain, SDValue Callee, CallingConv::ID CallConv,
624 bool isVarArg, bool isTailCall,
625 const SmallVectorImpl<ISD::OutputArg> &Outs,
626 const SmallVectorImpl<SDValue> &OutVals,
627 const SmallVectorImpl<ISD::InputArg> &Ins,
628 SDLoc dl, SelectionDAG &DAG,
629 SmallVectorImpl<SDValue> &InVals) const;
631 SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
632 SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
634 SDValue DAGCombineFastRecip(SDValue Op, DAGCombinerInfo &DCI) const;
635 SDValue DAGCombineFastRecipFSQRT(SDValue Op, DAGCombinerInfo &DCI) const;
637 CCAssignFn *useFastISelCCs(unsigned Flag) const;
641 FastISel *createFastISel(FunctionLoweringInfo &FuncInfo,
642 const TargetLibraryInfo *LibInfo);
645 bool CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
646 CCValAssign::LocInfo &LocInfo,
647 ISD::ArgFlagsTy &ArgFlags,
650 bool CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
652 CCValAssign::LocInfo &LocInfo,
653 ISD::ArgFlagsTy &ArgFlags,
656 bool CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
658 CCValAssign::LocInfo &LocInfo,
659 ISD::ArgFlagsTy &ArgFlags,
663 #endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H