1 //===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the PowerPC 64-bit instructions. These patterns are used
11 // both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
18 def s16imm64 : Operand<i64> {
19 let PrintMethod = "printS16ImmOperand";
20 let EncoderMethod = "getImm16Encoding";
21 let ParserMatchClass = PPCS16ImmAsmOperand;
22 let DecoderMethod = "decodeSImmOperand<16>";
24 def u16imm64 : Operand<i64> {
25 let PrintMethod = "printU16ImmOperand";
26 let EncoderMethod = "getImm16Encoding";
27 let ParserMatchClass = PPCU16ImmAsmOperand;
28 let DecoderMethod = "decodeUImmOperand<16>";
30 def s17imm64 : Operand<i64> {
31 // This operand type is used for addis/lis to allow the assembler parser
32 // to accept immediates in the range -65536..65535 for compatibility with
33 // the GNU assembler. The operand is treated as 16-bit otherwise.
34 let PrintMethod = "printS16ImmOperand";
35 let EncoderMethod = "getImm16Encoding";
36 let ParserMatchClass = PPCS17ImmAsmOperand;
37 let DecoderMethod = "decodeSImmOperand<16>";
39 def tocentry : Operand<iPTR> {
40 let MIOperandInfo = (ops i64imm:$imm);
42 def tlsreg : Operand<i64> {
43 let EncoderMethod = "getTLSRegEncoding";
44 let ParserMatchClass = PPCTLSRegOperand;
46 def tlsgd : Operand<i64> {}
47 def tlscall : Operand<i64> {
48 let PrintMethod = "printTLSCall";
49 let MIOperandInfo = (ops calltarget:$func, tlsgd:$sym);
50 let EncoderMethod = "getTLSCallEncoding";
53 //===----------------------------------------------------------------------===//
54 // 64-bit transformation functions.
57 def SHL64 : SDNodeXForm<imm, [{
58 // Transformation function: 63 - imm
59 return getI32Imm(63 - N->getZExtValue(), SDLoc(N));
62 def SRL64 : SDNodeXForm<imm, [{
63 // Transformation function: 64 - imm
64 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue(), SDLoc(N))
65 : getI32Imm(0, SDLoc(N));
69 //===----------------------------------------------------------------------===//
73 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
74 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
75 let isReturn = 1, Uses = [LR8, RM] in
76 def BLR8 : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB,
77 [(retflag)]>, Requires<[In64BitMode]>;
78 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR8] in {
79 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
81 Requires<[In64BitMode]>;
82 def BCCCTR8 : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond),
83 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB,
85 Requires<[In64BitMode]>;
87 def BCCTR8 : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi),
88 "bcctr 12, $bi, 0", IIC_BrB, []>,
89 Requires<[In64BitMode]>;
90 def BCCTR8n : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi),
91 "bcctr 4, $bi, 0", IIC_BrB, []>,
92 Requires<[In64BitMode]>;
97 def MovePCtoLR8 : Pseudo<(outs), (ins), "#MovePCtoLR8", []>,
100 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
101 let Defs = [CTR8], Uses = [CTR8] in {
102 def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
104 def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
108 let isReturn = 1, Defs = [CTR8], Uses = [CTR8, LR8, RM] in {
109 def BDZLR8 : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
110 "bdzlr", IIC_BrB, []>;
111 def BDNZLR8 : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
112 "bdnzlr", IIC_BrB, []>;
118 let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in {
119 // Convenient aliases for call instructions
121 def BL8 : IForm<18, 0, 1, (outs), (ins calltarget:$func),
122 "bl $func", IIC_BrB, []>; // See Pat patterns below.
124 def BL8_TLS : IForm<18, 0, 1, (outs), (ins tlscall:$func),
125 "bl $func", IIC_BrB, []>;
127 def BLA8 : IForm<18, 1, 1, (outs), (ins abscalltarget:$func),
128 "bla $func", IIC_BrB, [(PPCcall (i64 imm:$func))]>;
130 let Uses = [RM], isCodeGenOnly = 1 in {
131 def BL8_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24,
132 (outs), (ins calltarget:$func),
133 "bl $func\n\tnop", IIC_BrB, []>;
135 def BL8_NOP_TLS : IForm_and_DForm_4_zero<18, 0, 1, 24,
136 (outs), (ins tlscall:$func),
137 "bl $func\n\tnop", IIC_BrB, []>;
139 def BLA8_NOP : IForm_and_DForm_4_zero<18, 1, 1, 24,
140 (outs), (ins abscalltarget:$func),
141 "bla $func\n\tnop", IIC_BrB,
142 [(PPCcall_nop (i64 imm:$func))]>;
144 let Uses = [CTR8, RM] in {
145 def BCTRL8 : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
146 "bctrl", IIC_BrB, [(PPCbctrl)]>,
147 Requires<[In64BitMode]>;
149 let isCodeGenOnly = 1 in {
150 def BCCCTRL8 : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond),
151 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB,
153 Requires<[In64BitMode]>;
155 def BCCTRL8 : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi),
156 "bcctrl 12, $bi, 0", IIC_BrB, []>,
157 Requires<[In64BitMode]>;
158 def BCCTRL8n : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi),
159 "bcctrl 4, $bi, 0", IIC_BrB, []>,
160 Requires<[In64BitMode]>;
165 let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1,
166 Defs = [LR8, X2], Uses = [CTR8, RM], RST = 2 in {
167 def BCTRL8_LDinto_toc :
168 XLForm_2_ext_and_DSForm_1<19, 528, 20, 0, 1, 58, 0, (outs),
170 "bctrl\n\tld 2, $src", IIC_BrB,
171 [(PPCbctrl_load_toc ixaddr:$src)]>,
172 Requires<[In64BitMode]>;
175 } // Interpretation64Bit
177 // FIXME: Duplicating this for the asm parser should be unnecessary, but the
178 // previous definition must be marked as CodeGen only to prevent decoding
180 let Interpretation64Bit = 1, isAsmParserOnly = 1 in
181 let isCall = 1, PPC970_Unit = 7, Defs = [LR8], Uses = [RM] in
182 def BL8_TLS_ : IForm<18, 0, 1, (outs), (ins tlscall:$func),
183 "bl $func", IIC_BrB, []>;
186 def : Pat<(PPCcall (i64 tglobaladdr:$dst)),
187 (BL8 tglobaladdr:$dst)>;
188 def : Pat<(PPCcall_nop (i64 tglobaladdr:$dst)),
189 (BL8_NOP tglobaladdr:$dst)>;
191 def : Pat<(PPCcall (i64 texternalsym:$dst)),
192 (BL8 texternalsym:$dst)>;
193 def : Pat<(PPCcall_nop (i64 texternalsym:$dst)),
194 (BL8_NOP texternalsym:$dst)>;
197 // FIXME: some of these might be used with constant operands. This will result
198 // in constant materialization instructions that may be redundant. We currently
199 // clean this up in PPCMIPeephole with calls to
200 // PPCInstrInfo::convertToImmediateForm() but we should probably not emit them
201 // in the first place.
202 let usesCustomInserter = 1 in {
203 let Defs = [CR0] in {
204 def ATOMIC_LOAD_ADD_I64 : Pseudo<
205 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_ADD_I64",
206 [(set i64:$dst, (atomic_load_add_64 xoaddr:$ptr, i64:$incr))]>;
207 def ATOMIC_LOAD_SUB_I64 : Pseudo<
208 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_SUB_I64",
209 [(set i64:$dst, (atomic_load_sub_64 xoaddr:$ptr, i64:$incr))]>;
210 def ATOMIC_LOAD_OR_I64 : Pseudo<
211 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_OR_I64",
212 [(set i64:$dst, (atomic_load_or_64 xoaddr:$ptr, i64:$incr))]>;
213 def ATOMIC_LOAD_XOR_I64 : Pseudo<
214 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_XOR_I64",
215 [(set i64:$dst, (atomic_load_xor_64 xoaddr:$ptr, i64:$incr))]>;
216 def ATOMIC_LOAD_AND_I64 : Pseudo<
217 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_AND_i64",
218 [(set i64:$dst, (atomic_load_and_64 xoaddr:$ptr, i64:$incr))]>;
219 def ATOMIC_LOAD_NAND_I64 : Pseudo<
220 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_NAND_I64",
221 [(set i64:$dst, (atomic_load_nand_64 xoaddr:$ptr, i64:$incr))]>;
222 def ATOMIC_LOAD_MIN_I64 : Pseudo<
223 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_MIN_I64",
224 [(set i64:$dst, (atomic_load_min_64 xoaddr:$ptr, i64:$incr))]>;
225 def ATOMIC_LOAD_MAX_I64 : Pseudo<
226 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_MAX_I64",
227 [(set i64:$dst, (atomic_load_max_64 xoaddr:$ptr, i64:$incr))]>;
228 def ATOMIC_LOAD_UMIN_I64 : Pseudo<
229 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_UMIN_I64",
230 [(set i64:$dst, (atomic_load_umin_64 xoaddr:$ptr, i64:$incr))]>;
231 def ATOMIC_LOAD_UMAX_I64 : Pseudo<
232 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_UMAX_I64",
233 [(set i64:$dst, (atomic_load_umax_64 xoaddr:$ptr, i64:$incr))]>;
235 def ATOMIC_CMP_SWAP_I64 : Pseudo<
236 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$old, g8rc:$new), "#ATOMIC_CMP_SWAP_I64",
237 [(set i64:$dst, (atomic_cmp_swap_64 xoaddr:$ptr, i64:$old, i64:$new))]>;
239 def ATOMIC_SWAP_I64 : Pseudo<
240 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$new), "#ATOMIC_SWAP_I64",
241 [(set i64:$dst, (atomic_swap_64 xoaddr:$ptr, i64:$new))]>;
245 // Instructions to support atomic operations
246 let mayLoad = 1, hasSideEffects = 0 in {
247 def LDARX : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr),
248 "ldarx $rD, $ptr", IIC_LdStLDARX, []>;
250 // Instruction to support lock versions of atomics
251 // (EH=1 - see Power ISA 2.07 Book II 4.4.2)
252 def LDARXL : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr),
253 "ldarx $rD, $ptr, 1", IIC_LdStLDARX, []>, isDOT;
255 let hasExtraDefRegAllocReq = 1 in
256 def LDAT : X_RD5_RS5_IM5<31, 614, (outs g8rc:$rD), (ins g8rc:$rA, u5imm:$FC),
257 "ldat $rD, $rA, $FC", IIC_LdStLoad>, isPPC64,
258 Requires<[IsISA3_0]>;
261 let Defs = [CR0], mayStore = 1, mayLoad = 0, hasSideEffects = 0 in
262 def STDCX : XForm_1<31, 214, (outs), (ins g8rc:$rS, memrr:$dst),
263 "stdcx. $rS, $dst", IIC_LdStSTDCX, []>, isDOT;
265 let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in
266 def STDAT : X_RD5_RS5_IM5<31, 742, (outs), (ins g8rc:$rS, g8rc:$rA, u5imm:$FC),
267 "stdat $rS, $rA, $FC", IIC_LdStStore>, isPPC64,
268 Requires<[IsISA3_0]>;
270 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
271 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
272 def TCRETURNdi8 :Pseudo< (outs),
273 (ins calltarget:$dst, i32imm:$offset),
274 "#TC_RETURNd8 $dst $offset",
277 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
278 def TCRETURNai8 :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset),
279 "#TC_RETURNa8 $func $offset",
280 [(PPCtc_return (i64 imm:$func), imm:$offset)]>;
282 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
283 def TCRETURNri8 : Pseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset),
284 "#TC_RETURNr8 $dst $offset",
287 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
288 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR8, RM] in
289 def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
291 Requires<[In64BitMode]>;
293 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
294 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
295 def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
299 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
300 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
301 def TAILBA8 : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst),
304 } // Interpretation64Bit
306 def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm),
307 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>;
309 def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm),
310 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>;
312 def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm),
313 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>;
316 // 64-bit CR instructions
317 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
318 let hasSideEffects = 0 in {
319 // mtocrf's input needs to be prepared by shifting by an amount dependent
320 // on the cr register selected. Thus, post-ra anti-dep breaking must not
321 // later change that register assignment.
322 let hasExtraDefRegAllocReq = 1 in {
323 def MTOCRF8: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins g8rc:$ST),
324 "mtocrf $FXM, $ST", IIC_BrMCRX>,
325 PPC970_DGroup_First, PPC970_Unit_CRU;
327 // Similarly to mtocrf, the mask for mtcrf must be prepared in a way that
328 // is dependent on the cr fields being set.
329 def MTCRF8 : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, g8rc:$rS),
330 "mtcrf $FXM, $rS", IIC_BrMCRX>,
331 PPC970_MicroCode, PPC970_Unit_CRU;
332 } // hasExtraDefRegAllocReq = 1
334 // mfocrf's input needs to be prepared by shifting by an amount dependent
335 // on the cr register selected. Thus, post-ra anti-dep breaking must not
336 // later change that register assignment.
337 let hasExtraSrcRegAllocReq = 1 in {
338 def MFOCRF8: XFXForm_5a<31, 19, (outs g8rc:$rT), (ins crbitm:$FXM),
339 "mfocrf $rT, $FXM", IIC_SprMFCRF>,
340 PPC970_DGroup_First, PPC970_Unit_CRU;
342 // Similarly to mfocrf, the mask for mfcrf must be prepared in a way that
343 // is dependent on the cr fields being copied.
344 def MFCR8 : XFXForm_3<31, 19, (outs g8rc:$rT), (ins),
345 "mfcr $rT", IIC_SprMFCR>,
346 PPC970_MicroCode, PPC970_Unit_CRU;
347 } // hasExtraSrcRegAllocReq = 1
348 } // hasSideEffects = 0
350 let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
352 def EH_SjLj_SetJmp64 : Pseudo<(outs gprc:$dst), (ins memr:$buf),
354 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
355 Requires<[In64BitMode]>;
356 let isTerminator = 1 in
357 def EH_SjLj_LongJmp64 : Pseudo<(outs), (ins memr:$buf),
358 "#EH_SJLJ_LONGJMP64",
359 [(PPCeh_sjlj_longjmp addr:$buf)]>,
360 Requires<[In64BitMode]>;
363 def MFSPR8 : XFXForm_1<31, 339, (outs g8rc:$RT), (ins i32imm:$SPR),
364 "mfspr $RT, $SPR", IIC_SprMFSPR>;
365 def MTSPR8 : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, g8rc:$RT),
366 "mtspr $SPR, $RT", IIC_SprMTSPR>;
369 //===----------------------------------------------------------------------===//
370 // 64-bit SPR manipulation instrs.
372 let Uses = [CTR8] in {
373 def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs g8rc:$rT), (ins),
374 "mfctr $rT", IIC_SprMFSPR>,
375 PPC970_DGroup_First, PPC970_Unit_FXU;
377 let Pattern = [(PPCmtctr i64:$rS)], Defs = [CTR8] in {
378 def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS),
379 "mtctr $rS", IIC_SprMTSPR>,
380 PPC970_DGroup_First, PPC970_Unit_FXU;
382 let hasSideEffects = 1, Defs = [CTR8] in {
383 let Pattern = [(int_ppc_mtctr i64:$rS)] in
384 def MTCTR8loop : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS),
385 "mtctr $rS", IIC_SprMTSPR>,
386 PPC970_DGroup_First, PPC970_Unit_FXU;
389 let Pattern = [(set i64:$rT, readcyclecounter)] in
390 def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs g8rc:$rT), (ins),
391 "mfspr $rT, 268", IIC_SprMFTB>,
392 PPC970_DGroup_First, PPC970_Unit_FXU;
393 // Note that encoding mftb using mfspr is now the preferred form,
394 // and has been since at least ISA v2.03. The mftb instruction has
395 // now been phased out. Using mfspr, however, is known not to work on
398 let Defs = [X1], Uses = [X1] in
399 def DYNALLOC8 : Pseudo<(outs g8rc:$result), (ins g8rc:$negsize, memri:$fpsi),"#DYNALLOC8",
401 (PPCdynalloc i64:$negsize, iaddr:$fpsi))]>;
402 def DYNAREAOFFSET8 : Pseudo<(outs i64imm:$result), (ins memri:$fpsi), "#DYNAREAOFFSET8",
403 [(set i64:$result, (PPCdynareaoffset iaddr:$fpsi))]>;
405 let Defs = [LR8] in {
406 def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins g8rc:$rS),
407 "mtlr $rS", IIC_SprMTSPR>,
408 PPC970_DGroup_First, PPC970_Unit_FXU;
410 let Uses = [LR8] in {
411 def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs g8rc:$rT), (ins),
412 "mflr $rT", IIC_SprMFSPR>,
413 PPC970_DGroup_First, PPC970_Unit_FXU;
415 } // Interpretation64Bit
417 //===----------------------------------------------------------------------===//
418 // Fixed point instructions.
421 let PPC970_Unit = 1 in { // FXU Operations.
422 let Interpretation64Bit = 1 in {
423 let hasSideEffects = 0 in {
424 let isCodeGenOnly = 1 in {
426 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
427 def LI8 : DForm_2_r0<14, (outs g8rc:$rD), (ins s16imm64:$imm),
428 "li $rD, $imm", IIC_IntSimple,
429 [(set i64:$rD, imm64SExt16:$imm)]>;
430 def LIS8 : DForm_2_r0<15, (outs g8rc:$rD), (ins s17imm64:$imm),
431 "lis $rD, $imm", IIC_IntSimple,
432 [(set i64:$rD, imm16ShiftedSExt:$imm)]>;
436 let isCommutable = 1 in {
437 defm NAND8: XForm_6r<31, 476, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
438 "nand", "$rA, $rS, $rB", IIC_IntSimple,
439 [(set i64:$rA, (not (and i64:$rS, i64:$rB)))]>;
440 defm AND8 : XForm_6r<31, 28, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
441 "and", "$rA, $rS, $rB", IIC_IntSimple,
442 [(set i64:$rA, (and i64:$rS, i64:$rB))]>;
444 defm ANDC8: XForm_6r<31, 60, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
445 "andc", "$rA, $rS, $rB", IIC_IntSimple,
446 [(set i64:$rA, (and i64:$rS, (not i64:$rB)))]>;
447 let isCommutable = 1 in {
448 defm OR8 : XForm_6r<31, 444, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
449 "or", "$rA, $rS, $rB", IIC_IntSimple,
450 [(set i64:$rA, (or i64:$rS, i64:$rB))]>;
451 defm NOR8 : XForm_6r<31, 124, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
452 "nor", "$rA, $rS, $rB", IIC_IntSimple,
453 [(set i64:$rA, (not (or i64:$rS, i64:$rB)))]>;
455 defm ORC8 : XForm_6r<31, 412, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
456 "orc", "$rA, $rS, $rB", IIC_IntSimple,
457 [(set i64:$rA, (or i64:$rS, (not i64:$rB)))]>;
458 let isCommutable = 1 in {
459 defm EQV8 : XForm_6r<31, 284, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
460 "eqv", "$rA, $rS, $rB", IIC_IntSimple,
461 [(set i64:$rA, (not (xor i64:$rS, i64:$rB)))]>;
462 defm XOR8 : XForm_6r<31, 316, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
463 "xor", "$rA, $rS, $rB", IIC_IntSimple,
464 [(set i64:$rA, (xor i64:$rS, i64:$rB))]>;
465 } // let isCommutable = 1
467 // Logical ops with immediate.
468 let Defs = [CR0] in {
469 def ANDIo8 : DForm_4<28, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
470 "andi. $dst, $src1, $src2", IIC_IntGeneral,
471 [(set i64:$dst, (and i64:$src1, immZExt16:$src2))]>,
473 def ANDISo8 : DForm_4<29, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
474 "andis. $dst, $src1, $src2", IIC_IntGeneral,
475 [(set i64:$dst, (and i64:$src1, imm16ShiftedZExt:$src2))]>,
478 def ORI8 : DForm_4<24, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
479 "ori $dst, $src1, $src2", IIC_IntSimple,
480 [(set i64:$dst, (or i64:$src1, immZExt16:$src2))]>;
481 def ORIS8 : DForm_4<25, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
482 "oris $dst, $src1, $src2", IIC_IntSimple,
483 [(set i64:$dst, (or i64:$src1, imm16ShiftedZExt:$src2))]>;
484 def XORI8 : DForm_4<26, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
485 "xori $dst, $src1, $src2", IIC_IntSimple,
486 [(set i64:$dst, (xor i64:$src1, immZExt16:$src2))]>;
487 def XORIS8 : DForm_4<27, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
488 "xoris $dst, $src1, $src2", IIC_IntSimple,
489 [(set i64:$dst, (xor i64:$src1, imm16ShiftedZExt:$src2))]>;
491 let isCommutable = 1 in
492 defm ADD8 : XOForm_1r<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
493 "add", "$rT, $rA, $rB", IIC_IntSimple,
494 [(set i64:$rT, (add i64:$rA, i64:$rB))]>;
495 // ADD8 has a special form: reg = ADD8(reg, sym@tls) for use by the
496 // initial-exec thread-local storage model. We need to forbid r0 here -
497 // while it works for add just fine, the linker can relax this to local-exec
498 // addi, which won't work for r0.
499 def ADD8TLS : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc_nox0:$rA, tlsreg:$rB),
500 "add $rT, $rA, $rB", IIC_IntSimple,
501 [(set i64:$rT, (add i64:$rA, tglobaltlsaddr:$rB))]>;
503 let isCommutable = 1 in
504 defm ADDC8 : XOForm_1rc<31, 10, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
505 "addc", "$rT, $rA, $rB", IIC_IntGeneral,
506 [(set i64:$rT, (addc i64:$rA, i64:$rB))]>,
507 PPC970_DGroup_Cracked;
509 let Defs = [CARRY] in
510 def ADDIC8 : DForm_2<12, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm),
511 "addic $rD, $rA, $imm", IIC_IntGeneral,
512 [(set i64:$rD, (addc i64:$rA, imm64SExt16:$imm))]>;
513 def ADDI8 : DForm_2<14, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s16imm64:$imm),
514 "addi $rD, $rA, $imm", IIC_IntSimple,
515 [(set i64:$rD, (add i64:$rA, imm64SExt16:$imm))]>;
516 def ADDIS8 : DForm_2<15, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s17imm64:$imm),
517 "addis $rD, $rA, $imm", IIC_IntSimple,
518 [(set i64:$rD, (add i64:$rA, imm16ShiftedSExt:$imm))]>;
520 let Defs = [CARRY] in {
521 def SUBFIC8: DForm_2< 8, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm),
522 "subfic $rD, $rA, $imm", IIC_IntGeneral,
523 [(set i64:$rD, (subc imm64SExt16:$imm, i64:$rA))]>;
525 defm SUBFC8 : XOForm_1rc<31, 8, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
526 "subfc", "$rT, $rA, $rB", IIC_IntGeneral,
527 [(set i64:$rT, (subc i64:$rB, i64:$rA))]>,
528 PPC970_DGroup_Cracked;
529 defm SUBF8 : XOForm_1r<31, 40, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
530 "subf", "$rT, $rA, $rB", IIC_IntGeneral,
531 [(set i64:$rT, (sub i64:$rB, i64:$rA))]>;
532 defm NEG8 : XOForm_3r<31, 104, 0, (outs g8rc:$rT), (ins g8rc:$rA),
533 "neg", "$rT, $rA", IIC_IntSimple,
534 [(set i64:$rT, (ineg i64:$rA))]>;
535 let Uses = [CARRY] in {
536 let isCommutable = 1 in
537 defm ADDE8 : XOForm_1rc<31, 138, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
538 "adde", "$rT, $rA, $rB", IIC_IntGeneral,
539 [(set i64:$rT, (adde i64:$rA, i64:$rB))]>;
540 defm ADDME8 : XOForm_3rc<31, 234, 0, (outs g8rc:$rT), (ins g8rc:$rA),
541 "addme", "$rT, $rA", IIC_IntGeneral,
542 [(set i64:$rT, (adde i64:$rA, -1))]>;
543 defm ADDZE8 : XOForm_3rc<31, 202, 0, (outs g8rc:$rT), (ins g8rc:$rA),
544 "addze", "$rT, $rA", IIC_IntGeneral,
545 [(set i64:$rT, (adde i64:$rA, 0))]>;
546 defm SUBFE8 : XOForm_1rc<31, 136, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
547 "subfe", "$rT, $rA, $rB", IIC_IntGeneral,
548 [(set i64:$rT, (sube i64:$rB, i64:$rA))]>;
549 defm SUBFME8 : XOForm_3rc<31, 232, 0, (outs g8rc:$rT), (ins g8rc:$rA),
550 "subfme", "$rT, $rA", IIC_IntGeneral,
551 [(set i64:$rT, (sube -1, i64:$rA))]>;
552 defm SUBFZE8 : XOForm_3rc<31, 200, 0, (outs g8rc:$rT), (ins g8rc:$rA),
553 "subfze", "$rT, $rA", IIC_IntGeneral,
554 [(set i64:$rT, (sube 0, i64:$rA))]>;
558 // FIXME: Duplicating this for the asm parser should be unnecessary, but the
559 // previous definition must be marked as CodeGen only to prevent decoding
561 let isAsmParserOnly = 1 in
562 def ADD8TLS_ : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, tlsreg:$rB),
563 "add $rT, $rA, $rB", IIC_IntSimple, []>;
565 let isCommutable = 1 in {
566 defm MULHD : XOForm_1r<31, 73, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
567 "mulhd", "$rT, $rA, $rB", IIC_IntMulHW,
568 [(set i64:$rT, (mulhs i64:$rA, i64:$rB))]>;
569 defm MULHDU : XOForm_1r<31, 9, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
570 "mulhdu", "$rT, $rA, $rB", IIC_IntMulHWU,
571 [(set i64:$rT, (mulhu i64:$rA, i64:$rB))]>;
574 } // Interpretation64Bit
576 let isCompare = 1, hasSideEffects = 0 in {
577 def CMPD : XForm_16_ext<31, 0, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB),
578 "cmpd $crD, $rA, $rB", IIC_IntCompare>, isPPC64;
579 def CMPLD : XForm_16_ext<31, 32, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB),
580 "cmpld $crD, $rA, $rB", IIC_IntCompare>, isPPC64;
581 def CMPDI : DForm_5_ext<11, (outs crrc:$crD), (ins g8rc:$rA, s16imm64:$imm),
582 "cmpdi $crD, $rA, $imm", IIC_IntCompare>, isPPC64;
583 def CMPLDI : DForm_6_ext<10, (outs crrc:$dst), (ins g8rc:$src1, u16imm64:$src2),
584 "cmpldi $dst, $src1, $src2",
585 IIC_IntCompare>, isPPC64;
586 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
587 def CMPRB8 : X_BF3_L1_RS5_RS5<31, 192, (outs crbitrc:$BF),
588 (ins u1imm:$L, g8rc:$rA, g8rc:$rB),
589 "cmprb $BF, $L, $rA, $rB", IIC_IntCompare, []>,
590 Requires<[IsISA3_0]>;
591 def CMPEQB : X_BF3_RS5_RS5<31, 224, (outs crbitrc:$BF),
592 (ins g8rc:$rA, g8rc:$rB), "cmpeqb $BF, $rA, $rB",
593 IIC_IntCompare, []>, Requires<[IsISA3_0]>;
596 let hasSideEffects = 0 in {
597 defm SLD : XForm_6r<31, 27, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB),
598 "sld", "$rA, $rS, $rB", IIC_IntRotateD,
599 [(set i64:$rA, (PPCshl i64:$rS, i32:$rB))]>, isPPC64;
600 defm SRD : XForm_6r<31, 539, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB),
601 "srd", "$rA, $rS, $rB", IIC_IntRotateD,
602 [(set i64:$rA, (PPCsrl i64:$rS, i32:$rB))]>, isPPC64;
603 defm SRAD : XForm_6rc<31, 794, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB),
604 "srad", "$rA, $rS, $rB", IIC_IntRotateD,
605 [(set i64:$rA, (PPCsra i64:$rS, i32:$rB))]>, isPPC64;
607 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
608 defm CNTLZW8 : XForm_11r<31, 26, (outs g8rc:$rA), (ins g8rc:$rS),
609 "cntlzw", "$rA, $rS", IIC_IntGeneral, []>;
610 defm CNTTZW8 : XForm_11r<31, 538, (outs g8rc:$rA), (ins g8rc:$rS),
611 "cnttzw", "$rA, $rS", IIC_IntGeneral, []>,
612 Requires<[IsISA3_0]>;
614 defm EXTSB8 : XForm_11r<31, 954, (outs g8rc:$rA), (ins g8rc:$rS),
615 "extsb", "$rA, $rS", IIC_IntSimple,
616 [(set i64:$rA, (sext_inreg i64:$rS, i8))]>;
617 defm EXTSH8 : XForm_11r<31, 922, (outs g8rc:$rA), (ins g8rc:$rS),
618 "extsh", "$rA, $rS", IIC_IntSimple,
619 [(set i64:$rA, (sext_inreg i64:$rS, i16))]>;
621 defm SLW8 : XForm_6r<31, 24, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
622 "slw", "$rA, $rS, $rB", IIC_IntGeneral, []>;
623 defm SRW8 : XForm_6r<31, 536, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
624 "srw", "$rA, $rS, $rB", IIC_IntGeneral, []>;
625 } // Interpretation64Bit
628 let isCodeGenOnly = 1 in {
629 def EXTSB8_32_64 : XForm_11<31, 954, (outs g8rc:$rA), (ins gprc:$rS),
630 "extsb $rA, $rS", IIC_IntSimple, []>, isPPC64;
631 def EXTSH8_32_64 : XForm_11<31, 922, (outs g8rc:$rA), (ins gprc:$rS),
632 "extsh $rA, $rS", IIC_IntSimple, []>, isPPC64;
633 } // isCodeGenOnly for fast-isel
635 defm EXTSW : XForm_11r<31, 986, (outs g8rc:$rA), (ins g8rc:$rS),
636 "extsw", "$rA, $rS", IIC_IntSimple,
637 [(set i64:$rA, (sext_inreg i64:$rS, i32))]>, isPPC64;
638 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
639 defm EXTSW_32_64 : XForm_11r<31, 986, (outs g8rc:$rA), (ins gprc:$rS),
640 "extsw", "$rA, $rS", IIC_IntSimple,
641 [(set i64:$rA, (sext i32:$rS))]>, isPPC64;
642 let isCodeGenOnly = 1 in
643 def EXTSW_32 : XForm_11<31, 986, (outs gprc:$rA), (ins gprc:$rS),
644 "extsw $rA, $rS", IIC_IntSimple,
647 defm SRADI : XSForm_1rc<31, 413, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH),
648 "sradi", "$rA, $rS, $SH", IIC_IntRotateDI,
649 [(set i64:$rA, (sra i64:$rS, (i32 imm:$SH)))]>, isPPC64;
651 defm EXTSWSLI : XSForm_1r<31, 445, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH),
652 "extswsli", "$rA, $rS, $SH", IIC_IntRotateDI,
656 let isCodeGenOnly = 1, Defs = [CARRY] in
657 def SRADI_32 : XSForm_1<31, 413, (outs gprc:$rA), (ins gprc:$rS, u6imm:$SH),
658 "sradi $rA, $rS, $SH", IIC_IntRotateDI, []>, isPPC64;
660 defm CNTLZD : XForm_11r<31, 58, (outs g8rc:$rA), (ins g8rc:$rS),
661 "cntlzd", "$rA, $rS", IIC_IntGeneral,
662 [(set i64:$rA, (ctlz i64:$rS))]>;
663 defm CNTTZD : XForm_11r<31, 570, (outs g8rc:$rA), (ins g8rc:$rS),
664 "cnttzd", "$rA, $rS", IIC_IntGeneral,
665 [(set i64:$rA, (cttz i64:$rS))]>, Requires<[IsISA3_0]>;
666 def POPCNTD : XForm_11<31, 506, (outs g8rc:$rA), (ins g8rc:$rS),
667 "popcntd $rA, $rS", IIC_IntGeneral,
668 [(set i64:$rA, (ctpop i64:$rS))]>;
669 def BPERMD : XForm_6<31, 252, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
670 "bpermd $rA, $rS, $rB", IIC_IntGeneral,
671 [(set i64:$rA, (int_ppc_bpermd g8rc:$rS, g8rc:$rB))]>,
672 isPPC64, Requires<[HasBPERMD]>;
674 let isCodeGenOnly = 1, isCommutable = 1 in
675 def CMPB8 : XForm_6<31, 508, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
676 "cmpb $rA, $rS, $rB", IIC_IntGeneral,
677 [(set i64:$rA, (PPCcmpb i64:$rS, i64:$rB))]>;
679 // popcntw also does a population count on the high 32 bits (storing the
680 // results in the high 32-bits of the output). We'll ignore that here (which is
681 // safe because we never separately use the high part of the 64-bit registers).
682 def POPCNTW : XForm_11<31, 378, (outs gprc:$rA), (ins gprc:$rS),
683 "popcntw $rA, $rS", IIC_IntGeneral,
684 [(set i32:$rA, (ctpop i32:$rS))]>;
686 def POPCNTB : XForm_11<31, 122, (outs gprc:$rA), (ins gprc:$rS),
687 "popcntb $rA, $rS", IIC_IntGeneral, []>;
689 defm DIVD : XOForm_1rcr<31, 489, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
690 "divd", "$rT, $rA, $rB", IIC_IntDivD,
691 [(set i64:$rT, (sdiv i64:$rA, i64:$rB))]>, isPPC64;
692 defm DIVDU : XOForm_1rcr<31, 457, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
693 "divdu", "$rT, $rA, $rB", IIC_IntDivD,
694 [(set i64:$rT, (udiv i64:$rA, i64:$rB))]>, isPPC64;
695 def DIVDE : XOForm_1<31, 425, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
696 "divde $rT, $rA, $rB", IIC_IntDivD,
697 [(set i64:$rT, (int_ppc_divde g8rc:$rA, g8rc:$rB))]>,
698 isPPC64, Requires<[HasExtDiv]>;
700 let Predicates = [IsISA3_0] in {
701 def MADDHD : VAForm_1a<48, (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC),
702 "maddhd $RT, $RA, $RB, $RC", IIC_IntMulHD, []>, isPPC64;
703 def MADDHDU : VAForm_1a<49, (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC),
704 "maddhdu $RT, $RA, $RB, $RC", IIC_IntMulHD, []>, isPPC64;
705 def MADDLD : VAForm_1a<51, (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC),
706 "maddld $RT, $RA, $RB, $RC", IIC_IntMulHD, []>, isPPC64;
707 def SETB : XForm_44<31, 128, (outs g8rc:$RT), (ins crrc:$BFA),
708 "setb $RT, $BFA", IIC_IntGeneral>, isPPC64;
709 def DARN : XForm_45<31, 755, (outs g8rc:$RT), (ins i32imm:$L),
710 "darn $RT, $L", IIC_LdStLD>, isPPC64;
711 def ADDPCIS : DXForm<19, 2, (outs g8rc:$RT), (ins i32imm:$D),
712 "addpcis $RT, $D", IIC_BrB, []>, isPPC64;
713 def MODSD : XForm_8<31, 777, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
714 "modsd $rT, $rA, $rB", IIC_IntDivW,
715 [(set i64:$rT, (srem i64:$rA, i64:$rB))]>;
716 def MODUD : XForm_8<31, 265, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
717 "modud $rT, $rA, $rB", IIC_IntDivW,
718 [(set i64:$rT, (urem i64:$rA, i64:$rB))]>;
722 def DIVDEo : XOForm_1<31, 425, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
723 "divde. $rT, $rA, $rB", IIC_IntDivD,
724 []>, isDOT, PPC970_DGroup_Cracked, PPC970_DGroup_First,
725 isPPC64, Requires<[HasExtDiv]>;
726 def DIVDEU : XOForm_1<31, 393, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
727 "divdeu $rT, $rA, $rB", IIC_IntDivD,
728 [(set i64:$rT, (int_ppc_divdeu g8rc:$rA, g8rc:$rB))]>,
729 isPPC64, Requires<[HasExtDiv]>;
731 def DIVDEUo : XOForm_1<31, 393, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
732 "divdeu. $rT, $rA, $rB", IIC_IntDivD,
733 []>, isDOT, PPC970_DGroup_Cracked, PPC970_DGroup_First,
734 isPPC64, Requires<[HasExtDiv]>;
735 let isCommutable = 1 in
736 defm MULLD : XOForm_1r<31, 233, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
737 "mulld", "$rT, $rA, $rB", IIC_IntMulHD,
738 [(set i64:$rT, (mul i64:$rA, i64:$rB))]>, isPPC64;
739 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
740 def MULLI8 : DForm_2<7, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm),
741 "mulli $rD, $rA, $imm", IIC_IntMulLI,
742 [(set i64:$rD, (mul i64:$rA, imm64SExt16:$imm))]>;
745 let hasSideEffects = 0 in {
746 defm RLDIMI : MDForm_1r<30, 3, (outs g8rc:$rA),
747 (ins g8rc:$rSi, g8rc:$rS, u6imm:$SH, u6imm:$MBE),
748 "rldimi", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI,
749 []>, isPPC64, RegConstraint<"$rSi = $rA">,
752 // Rotate instructions.
753 defm RLDCL : MDSForm_1r<30, 8,
754 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE),
755 "rldcl", "$rA, $rS, $rB, $MBE", IIC_IntRotateD,
757 defm RLDCR : MDSForm_1r<30, 9,
758 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE),
759 "rldcr", "$rA, $rS, $rB, $MBE", IIC_IntRotateD,
761 defm RLDICL : MDForm_1r<30, 0,
762 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE),
763 "rldicl", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI,
766 let isCodeGenOnly = 1 in
767 def RLDICL_32_64 : MDForm_1<30, 0,
769 (ins gprc:$rS, u6imm:$SH, u6imm:$MBE),
770 "rldicl $rA, $rS, $SH, $MBE", IIC_IntRotateDI,
773 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
774 defm RLDICL_32 : MDForm_1r<30, 0,
776 (ins gprc:$rS, u6imm:$SH, u6imm:$MBE),
777 "rldicl", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI,
779 defm RLDICR : MDForm_1r<30, 1,
780 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE),
781 "rldicr", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI,
783 let isCodeGenOnly = 1 in
784 def RLDICR_32 : MDForm_1<30, 1,
785 (outs gprc:$rA), (ins gprc:$rS, u6imm:$SH, u6imm:$MBE),
786 "rldicr $rA, $rS, $SH, $MBE", IIC_IntRotateDI,
788 defm RLDIC : MDForm_1r<30, 2,
789 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE),
790 "rldic", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI,
793 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
794 defm RLWINM8 : MForm_2r<21, (outs g8rc:$rA),
795 (ins g8rc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
796 "rlwinm", "$rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
799 defm RLWNM8 : MForm_2r<23, (outs g8rc:$rA),
800 (ins g8rc:$rS, g8rc:$rB, u5imm:$MB, u5imm:$ME),
801 "rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral,
804 // RLWIMI can be commuted if the rotate amount is zero.
805 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
806 defm RLWIMI8 : MForm_2r<20, (outs g8rc:$rA),
807 (ins g8rc:$rSi, g8rc:$rS, u5imm:$SH, u5imm:$MB,
808 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME",
809 IIC_IntRotate, []>, PPC970_DGroup_Cracked,
810 RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">;
813 def ISEL8 : AForm_4<31, 15,
814 (outs g8rc:$rT), (ins g8rc_nox0:$rA, g8rc:$rB, crbitrc:$cond),
815 "isel $rT, $rA, $rB, $cond", IIC_IntISEL,
817 } // Interpretation64Bit
818 } // hasSideEffects = 0
819 } // End FXU Operations.
822 //===----------------------------------------------------------------------===//
823 // Load/Store instructions.
827 // Sign extending loads.
828 let PPC970_Unit = 2 in {
829 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
830 def LHA8: DForm_1<42, (outs g8rc:$rD), (ins memri:$src),
831 "lha $rD, $src", IIC_LdStLHA,
832 [(set i64:$rD, (sextloadi16 iaddr:$src))]>,
833 PPC970_DGroup_Cracked;
834 def LWA : DSForm_1<58, 2, (outs g8rc:$rD), (ins memrix:$src),
835 "lwa $rD, $src", IIC_LdStLWA,
837 (aligned4sextloadi32 ixaddr:$src))]>, isPPC64,
838 PPC970_DGroup_Cracked;
839 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
840 def LHAX8: XForm_1<31, 343, (outs g8rc:$rD), (ins memrr:$src),
841 "lhax $rD, $src", IIC_LdStLHA,
842 [(set i64:$rD, (sextloadi16 xaddr:$src))]>,
843 PPC970_DGroup_Cracked;
844 def LWAX : XForm_1<31, 341, (outs g8rc:$rD), (ins memrr:$src),
845 "lwax $rD, $src", IIC_LdStLHA,
846 [(set i64:$rD, (sextloadi32 xaddr:$src))]>, isPPC64,
847 PPC970_DGroup_Cracked;
849 let isCodeGenOnly = 1, mayLoad = 1 in {
850 def LWA_32 : DSForm_1<58, 2, (outs gprc:$rD), (ins memrix:$src),
851 "lwa $rD, $src", IIC_LdStLWA, []>, isPPC64,
852 PPC970_DGroup_Cracked;
853 def LWAX_32 : XForm_1<31, 341, (outs gprc:$rD), (ins memrr:$src),
854 "lwax $rD, $src", IIC_LdStLHA, []>, isPPC64,
855 PPC970_DGroup_Cracked;
856 } // end fast-isel isCodeGenOnly
859 let mayLoad = 1, hasSideEffects = 0 in {
860 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
861 def LHAU8 : DForm_1<43, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
863 "lhau $rD, $addr", IIC_LdStLHAU,
864 []>, RegConstraint<"$addr.reg = $ea_result">,
865 NoEncode<"$ea_result">;
868 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
869 def LHAUX8 : XForm_1<31, 375, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
871 "lhaux $rD, $addr", IIC_LdStLHAUX,
872 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
873 NoEncode<"$ea_result">;
874 def LWAUX : XForm_1<31, 373, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
876 "lwaux $rD, $addr", IIC_LdStLHAUX,
877 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
878 NoEncode<"$ea_result">, isPPC64;
882 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
883 // Zero extending loads.
884 let PPC970_Unit = 2 in {
885 def LBZ8 : DForm_1<34, (outs g8rc:$rD), (ins memri:$src),
886 "lbz $rD, $src", IIC_LdStLoad,
887 [(set i64:$rD, (zextloadi8 iaddr:$src))]>;
888 def LHZ8 : DForm_1<40, (outs g8rc:$rD), (ins memri:$src),
889 "lhz $rD, $src", IIC_LdStLoad,
890 [(set i64:$rD, (zextloadi16 iaddr:$src))]>;
891 def LWZ8 : DForm_1<32, (outs g8rc:$rD), (ins memri:$src),
892 "lwz $rD, $src", IIC_LdStLoad,
893 [(set i64:$rD, (zextloadi32 iaddr:$src))]>, isPPC64;
895 def LBZX8 : XForm_1<31, 87, (outs g8rc:$rD), (ins memrr:$src),
896 "lbzx $rD, $src", IIC_LdStLoad,
897 [(set i64:$rD, (zextloadi8 xaddr:$src))]>;
898 def LHZX8 : XForm_1<31, 279, (outs g8rc:$rD), (ins memrr:$src),
899 "lhzx $rD, $src", IIC_LdStLoad,
900 [(set i64:$rD, (zextloadi16 xaddr:$src))]>;
901 def LWZX8 : XForm_1<31, 23, (outs g8rc:$rD), (ins memrr:$src),
902 "lwzx $rD, $src", IIC_LdStLoad,
903 [(set i64:$rD, (zextloadi32 xaddr:$src))]>;
907 let mayLoad = 1, hasSideEffects = 0 in {
908 def LBZU8 : DForm_1<35, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
909 "lbzu $rD, $addr", IIC_LdStLoadUpd,
910 []>, RegConstraint<"$addr.reg = $ea_result">,
911 NoEncode<"$ea_result">;
912 def LHZU8 : DForm_1<41, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
913 "lhzu $rD, $addr", IIC_LdStLoadUpd,
914 []>, RegConstraint<"$addr.reg = $ea_result">,
915 NoEncode<"$ea_result">;
916 def LWZU8 : DForm_1<33, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
917 "lwzu $rD, $addr", IIC_LdStLoadUpd,
918 []>, RegConstraint<"$addr.reg = $ea_result">,
919 NoEncode<"$ea_result">;
921 def LBZUX8 : XForm_1<31, 119, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
923 "lbzux $rD, $addr", IIC_LdStLoadUpdX,
924 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
925 NoEncode<"$ea_result">;
926 def LHZUX8 : XForm_1<31, 311, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
928 "lhzux $rD, $addr", IIC_LdStLoadUpdX,
929 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
930 NoEncode<"$ea_result">;
931 def LWZUX8 : XForm_1<31, 55, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
933 "lwzux $rD, $addr", IIC_LdStLoadUpdX,
934 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
935 NoEncode<"$ea_result">;
938 } // Interpretation64Bit
941 // Full 8-byte loads.
942 let PPC970_Unit = 2 in {
943 def LD : DSForm_1<58, 0, (outs g8rc:$rD), (ins memrix:$src),
944 "ld $rD, $src", IIC_LdStLD,
945 [(set i64:$rD, (aligned4load ixaddr:$src))]>, isPPC64;
946 // The following four definitions are selected for small code model only.
947 // Otherwise, we need to create two instructions to form a 32-bit offset,
948 // so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select().
949 def LDtoc: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
952 (PPCtoc_entry tglobaladdr:$disp, i64:$reg))]>, isPPC64;
953 def LDtocJTI: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
956 (PPCtoc_entry tjumptable:$disp, i64:$reg))]>, isPPC64;
957 def LDtocCPT: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
960 (PPCtoc_entry tconstpool:$disp, i64:$reg))]>, isPPC64;
961 def LDtocBA: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
964 (PPCtoc_entry tblockaddress:$disp, i64:$reg))]>, isPPC64;
966 def LDX : XForm_1<31, 21, (outs g8rc:$rD), (ins memrr:$src),
967 "ldx $rD, $src", IIC_LdStLD,
968 [(set i64:$rD, (load xaddr:$src))]>, isPPC64;
969 def LDBRX : XForm_1<31, 532, (outs g8rc:$rD), (ins memrr:$src),
970 "ldbrx $rD, $src", IIC_LdStLoad,
971 [(set i64:$rD, (PPClbrx xoaddr:$src, i64))]>, isPPC64;
973 let mayLoad = 1, hasSideEffects = 0, isCodeGenOnly = 1 in {
974 def LHBRX8 : XForm_1<31, 790, (outs g8rc:$rD), (ins memrr:$src),
975 "lhbrx $rD, $src", IIC_LdStLoad, []>;
976 def LWBRX8 : XForm_1<31, 534, (outs g8rc:$rD), (ins memrr:$src),
977 "lwbrx $rD, $src", IIC_LdStLoad, []>;
980 let mayLoad = 1, hasSideEffects = 0 in {
981 def LDU : DSForm_1<58, 1, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memrix:$addr),
982 "ldu $rD, $addr", IIC_LdStLDU,
983 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64,
984 NoEncode<"$ea_result">;
986 def LDUX : XForm_1<31, 53, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
988 "ldux $rD, $addr", IIC_LdStLDUX,
989 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
990 NoEncode<"$ea_result">, isPPC64;
992 def LDMX : XForm_1<31, 309, (outs g8rc:$rD), (ins memrr:$src),
993 "ldmx $rD, $src", IIC_LdStLD, []>, isPPC64,
994 Requires<[IsISA3_0]>;
998 // Support for medium and large code model.
999 let hasSideEffects = 0 in {
1000 let isReMaterializable = 1 in {
1001 def ADDIStocHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp),
1002 "#ADDIStocHA", []>, isPPC64;
1003 def ADDItocL: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp),
1004 "#ADDItocL", []>, isPPC64;
1007 def LDtocL: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc_nox0:$reg),
1008 "#LDtocL", []>, isPPC64;
1011 // Support for thread-local storage.
1012 def ADDISgotTprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
1015 (PPCaddisGotTprelHA i64:$reg,
1016 tglobaltlsaddr:$disp))]>,
1018 def LDgotTprelL: Pseudo<(outs g8rc:$rD), (ins s16imm64:$disp, g8rc_nox0:$reg),
1021 (PPCldGotTprelL tglobaltlsaddr:$disp, i64:$reg))]>,
1024 let isPseudo = 1, Defs = [CR7], Itinerary = IIC_LdStSync in
1025 def CFENCE8 : Pseudo<(outs), (ins g8rc:$cr), "#CFENCE8", []>;
1027 def : Pat<(PPCaddTls i64:$in, tglobaltlsaddr:$g),
1028 (ADD8TLS $in, tglobaltlsaddr:$g)>;
1029 def ADDIStlsgdHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
1032 (PPCaddisTlsgdHA i64:$reg, tglobaltlsaddr:$disp))]>,
1034 def ADDItlsgdL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
1037 (PPCaddiTlsgdL i64:$reg, tglobaltlsaddr:$disp))]>,
1039 // LR8 is a true define, while the rest of the Defs are clobbers. X3 is
1040 // explicitly defined when this op is created, so not mentioned here.
1041 // This is lowered to BL8_NOP_TLS by the assembly printer, so the size must be
1042 // correct because the branch select pass is relying on it.
1043 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, Size = 8,
1044 Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in
1045 def GETtlsADDR : Pseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym),
1048 (PPCgetTlsAddr i64:$reg, tglobaltlsaddr:$sym))]>,
1050 // Combined op for ADDItlsgdL and GETtlsADDR, late expanded. X3 and LR8
1051 // are true defines while the rest of the Defs are clobbers.
1052 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
1053 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7]
1055 def ADDItlsgdLADDR : Pseudo<(outs g8rc:$rD),
1056 (ins g8rc_nox0:$reg, s16imm64:$disp, tlsgd:$sym),
1059 (PPCaddiTlsgdLAddr i64:$reg,
1060 tglobaltlsaddr:$disp,
1061 tglobaltlsaddr:$sym))]>,
1063 def ADDIStlsldHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
1066 (PPCaddisTlsldHA i64:$reg, tglobaltlsaddr:$disp))]>,
1068 def ADDItlsldL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
1071 (PPCaddiTlsldL i64:$reg, tglobaltlsaddr:$disp))]>,
1073 // LR8 is a true define, while the rest of the Defs are clobbers. X3 is
1074 // explicitly defined when this op is created, so not mentioned here.
1075 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
1076 Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in
1077 def GETtlsldADDR : Pseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym),
1080 (PPCgetTlsldAddr i64:$reg, tglobaltlsaddr:$sym))]>,
1082 // Combined op for ADDItlsldL and GETtlsADDR, late expanded. X3 and LR8
1083 // are true defines, while the rest of the Defs are clobbers.
1084 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
1085 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7]
1087 def ADDItlsldLADDR : Pseudo<(outs g8rc:$rD),
1088 (ins g8rc_nox0:$reg, s16imm64:$disp, tlsgd:$sym),
1091 (PPCaddiTlsldLAddr i64:$reg,
1092 tglobaltlsaddr:$disp,
1093 tglobaltlsaddr:$sym))]>,
1095 def ADDISdtprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
1098 (PPCaddisDtprelHA i64:$reg,
1099 tglobaltlsaddr:$disp))]>,
1101 def ADDIdtprelL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
1104 (PPCaddiDtprelL i64:$reg, tglobaltlsaddr:$disp))]>,
1107 let PPC970_Unit = 2 in {
1108 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
1109 // Truncating stores.
1110 def STB8 : DForm_1<38, (outs), (ins g8rc:$rS, memri:$src),
1111 "stb $rS, $src", IIC_LdStStore,
1112 [(truncstorei8 i64:$rS, iaddr:$src)]>;
1113 def STH8 : DForm_1<44, (outs), (ins g8rc:$rS, memri:$src),
1114 "sth $rS, $src", IIC_LdStStore,
1115 [(truncstorei16 i64:$rS, iaddr:$src)]>;
1116 def STW8 : DForm_1<36, (outs), (ins g8rc:$rS, memri:$src),
1117 "stw $rS, $src", IIC_LdStStore,
1118 [(truncstorei32 i64:$rS, iaddr:$src)]>;
1119 def STBX8 : XForm_8<31, 215, (outs), (ins g8rc:$rS, memrr:$dst),
1120 "stbx $rS, $dst", IIC_LdStStore,
1121 [(truncstorei8 i64:$rS, xaddr:$dst)]>,
1122 PPC970_DGroup_Cracked;
1123 def STHX8 : XForm_8<31, 407, (outs), (ins g8rc:$rS, memrr:$dst),
1124 "sthx $rS, $dst", IIC_LdStStore,
1125 [(truncstorei16 i64:$rS, xaddr:$dst)]>,
1126 PPC970_DGroup_Cracked;
1127 def STWX8 : XForm_8<31, 151, (outs), (ins g8rc:$rS, memrr:$dst),
1128 "stwx $rS, $dst", IIC_LdStStore,
1129 [(truncstorei32 i64:$rS, xaddr:$dst)]>,
1130 PPC970_DGroup_Cracked;
1131 } // Interpretation64Bit
1133 // Normal 8-byte stores.
1134 def STD : DSForm_1<62, 0, (outs), (ins g8rc:$rS, memrix:$dst),
1135 "std $rS, $dst", IIC_LdStSTD,
1136 [(aligned4store i64:$rS, ixaddr:$dst)]>, isPPC64;
1137 def STDX : XForm_8<31, 149, (outs), (ins g8rc:$rS, memrr:$dst),
1138 "stdx $rS, $dst", IIC_LdStSTD,
1139 [(store i64:$rS, xaddr:$dst)]>, isPPC64,
1140 PPC970_DGroup_Cracked;
1141 def STDBRX: XForm_8<31, 660, (outs), (ins g8rc:$rS, memrr:$dst),
1142 "stdbrx $rS, $dst", IIC_LdStStore,
1143 [(PPCstbrx i64:$rS, xoaddr:$dst, i64)]>, isPPC64,
1144 PPC970_DGroup_Cracked;
1147 // Stores with Update (pre-inc).
1148 let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in {
1149 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
1150 def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst),
1151 "stbu $rS, $dst", IIC_LdStStoreUpd, []>,
1152 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1153 def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst),
1154 "sthu $rS, $dst", IIC_LdStStoreUpd, []>,
1155 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1156 def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst),
1157 "stwu $rS, $dst", IIC_LdStStoreUpd, []>,
1158 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1160 def STBUX8: XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
1161 "stbux $rS, $dst", IIC_LdStStoreUpd, []>,
1162 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1163 PPC970_DGroup_Cracked;
1164 def STHUX8: XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
1165 "sthux $rS, $dst", IIC_LdStStoreUpd, []>,
1166 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1167 PPC970_DGroup_Cracked;
1168 def STWUX8: XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
1169 "stwux $rS, $dst", IIC_LdStStoreUpd, []>,
1170 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1171 PPC970_DGroup_Cracked;
1172 } // Interpretation64Bit
1174 def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrix:$dst),
1175 "stdu $rS, $dst", IIC_LdStSTDU, []>,
1176 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">,
1179 def STDUX : XForm_8<31, 181, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
1180 "stdux $rS, $dst", IIC_LdStSTDUX, []>,
1181 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1182 PPC970_DGroup_Cracked, isPPC64;
1185 // Patterns to match the pre-inc stores. We can't put the patterns on
1186 // the instruction definitions directly as ISel wants the address base
1187 // and offset to be separate operands, not a single complex operand.
1188 def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1189 (STBU8 $rS, iaddroff:$ptroff, $ptrreg)>;
1190 def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1191 (STHU8 $rS, iaddroff:$ptroff, $ptrreg)>;
1192 def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1193 (STWU8 $rS, iaddroff:$ptroff, $ptrreg)>;
1194 def : Pat<(aligned4pre_store i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1195 (STDU $rS, iaddroff:$ptroff, $ptrreg)>;
1197 def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1198 (STBUX8 $rS, $ptrreg, $ptroff)>;
1199 def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1200 (STHUX8 $rS, $ptrreg, $ptroff)>;
1201 def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1202 (STWUX8 $rS, $ptrreg, $ptroff)>;
1203 def : Pat<(pre_store i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1204 (STDUX $rS, $ptrreg, $ptroff)>;
1207 //===----------------------------------------------------------------------===//
1208 // Floating point instructions.
1212 let PPC970_Unit = 3, hasSideEffects = 0,
1213 Uses = [RM] in { // FPU Operations.
1214 defm FCFID : XForm_26r<63, 846, (outs f8rc:$frD), (ins f8rc:$frB),
1215 "fcfid", "$frD, $frB", IIC_FPGeneral,
1216 [(set f64:$frD, (PPCfcfid f64:$frB))]>, isPPC64;
1217 defm FCTID : XForm_26r<63, 814, (outs f8rc:$frD), (ins f8rc:$frB),
1218 "fctid", "$frD, $frB", IIC_FPGeneral,
1220 defm FCTIDU : XForm_26r<63, 942, (outs f8rc:$frD), (ins f8rc:$frB),
1221 "fctidu", "$frD, $frB", IIC_FPGeneral,
1223 defm FCTIDZ : XForm_26r<63, 815, (outs f8rc:$frD), (ins f8rc:$frB),
1224 "fctidz", "$frD, $frB", IIC_FPGeneral,
1225 [(set f64:$frD, (PPCfctidz f64:$frB))]>, isPPC64;
1227 defm FCFIDU : XForm_26r<63, 974, (outs f8rc:$frD), (ins f8rc:$frB),
1228 "fcfidu", "$frD, $frB", IIC_FPGeneral,
1229 [(set f64:$frD, (PPCfcfidu f64:$frB))]>, isPPC64;
1230 defm FCFIDS : XForm_26r<59, 846, (outs f4rc:$frD), (ins f8rc:$frB),
1231 "fcfids", "$frD, $frB", IIC_FPGeneral,
1232 [(set f32:$frD, (PPCfcfids f64:$frB))]>, isPPC64;
1233 defm FCFIDUS : XForm_26r<59, 974, (outs f4rc:$frD), (ins f8rc:$frB),
1234 "fcfidus", "$frD, $frB", IIC_FPGeneral,
1235 [(set f32:$frD, (PPCfcfidus f64:$frB))]>, isPPC64;
1236 defm FCTIDUZ : XForm_26r<63, 943, (outs f8rc:$frD), (ins f8rc:$frB),
1237 "fctiduz", "$frD, $frB", IIC_FPGeneral,
1238 [(set f64:$frD, (PPCfctiduz f64:$frB))]>, isPPC64;
1239 defm FCTIWUZ : XForm_26r<63, 143, (outs f8rc:$frD), (ins f8rc:$frB),
1240 "fctiwuz", "$frD, $frB", IIC_FPGeneral,
1241 [(set f64:$frD, (PPCfctiwuz f64:$frB))]>, isPPC64;
1245 //===----------------------------------------------------------------------===//
1246 // Instruction Patterns
1249 // Extensions and truncates to/from 32-bit regs.
1250 def : Pat<(i64 (zext i32:$in)),
1251 (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32),
1253 def : Pat<(i64 (anyext i32:$in)),
1254 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32)>;
1255 def : Pat<(i32 (trunc i64:$in)),
1256 (EXTRACT_SUBREG $in, sub_32)>;
1258 // Implement the 'not' operation with the NOR instruction.
1259 // (we could use the default xori pattern, but nor has lower latency on some
1260 // cores (such as the A2)).
1261 def i64not : OutPatFrag<(ops node:$in),
1263 def : Pat<(not i64:$in),
1266 // Extending loads with i64 targets.
1267 def : Pat<(zextloadi1 iaddr:$src),
1269 def : Pat<(zextloadi1 xaddr:$src),
1270 (LBZX8 xaddr:$src)>;
1271 def : Pat<(extloadi1 iaddr:$src),
1273 def : Pat<(extloadi1 xaddr:$src),
1274 (LBZX8 xaddr:$src)>;
1275 def : Pat<(extloadi8 iaddr:$src),
1277 def : Pat<(extloadi8 xaddr:$src),
1278 (LBZX8 xaddr:$src)>;
1279 def : Pat<(extloadi16 iaddr:$src),
1281 def : Pat<(extloadi16 xaddr:$src),
1282 (LHZX8 xaddr:$src)>;
1283 def : Pat<(extloadi32 iaddr:$src),
1285 def : Pat<(extloadi32 xaddr:$src),
1286 (LWZX8 xaddr:$src)>;
1288 // Standard shifts. These are represented separately from the real shifts above
1289 // so that we can distinguish between shifts that allow 6-bit and 7-bit shift
1291 def : Pat<(sra i64:$rS, i32:$rB),
1293 def : Pat<(srl i64:$rS, i32:$rB),
1295 def : Pat<(shl i64:$rS, i32:$rB),
1299 def : Pat<(sub imm64SExt16:$imm, i64:$in),
1300 (SUBFIC8 $in, imm:$imm)>;
1303 def : Pat<(shl i64:$in, (i32 imm:$imm)),
1304 (RLDICR $in, imm:$imm, (SHL64 imm:$imm))>;
1305 def : Pat<(srl i64:$in, (i32 imm:$imm)),
1306 (RLDICL $in, (SRL64 imm:$imm), imm:$imm)>;
1309 def : Pat<(rotl i64:$in, i32:$sh),
1310 (RLDCL $in, $sh, 0)>;
1311 def : Pat<(rotl i64:$in, (i32 imm:$imm)),
1312 (RLDICL $in, imm:$imm, 0)>;
1314 // Hi and Lo for Darwin Global Addresses.
1315 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>;
1316 def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>;
1317 def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>;
1318 def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>;
1319 def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>;
1320 def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>;
1321 def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>;
1322 def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>;
1323 def : Pat<(PPChi tglobaltlsaddr:$g, i64:$in),
1324 (ADDIS8 $in, tglobaltlsaddr:$g)>;
1325 def : Pat<(PPClo tglobaltlsaddr:$g, i64:$in),
1326 (ADDI8 $in, tglobaltlsaddr:$g)>;
1327 def : Pat<(add i64:$in, (PPChi tglobaladdr:$g, 0)),
1328 (ADDIS8 $in, tglobaladdr:$g)>;
1329 def : Pat<(add i64:$in, (PPChi tconstpool:$g, 0)),
1330 (ADDIS8 $in, tconstpool:$g)>;
1331 def : Pat<(add i64:$in, (PPChi tjumptable:$g, 0)),
1332 (ADDIS8 $in, tjumptable:$g)>;
1333 def : Pat<(add i64:$in, (PPChi tblockaddress:$g, 0)),
1334 (ADDIS8 $in, tblockaddress:$g)>;
1336 // Patterns to match r+r indexed loads and stores for
1337 // addresses without at least 4-byte alignment.
1338 def : Pat<(i64 (unaligned4sextloadi32 xoaddr:$src)),
1339 (LWAX xoaddr:$src)>;
1340 def : Pat<(i64 (unaligned4load xoaddr:$src)),
1342 def : Pat<(unaligned4store i64:$rS, xoaddr:$dst),
1343 (STDX $rS, xoaddr:$dst)>;
1345 // 64-bits atomic loads and stores
1346 def : Pat<(atomic_load_64 ixaddr:$src), (LD memrix:$src)>;
1347 def : Pat<(atomic_load_64 xaddr:$src), (LDX memrr:$src)>;
1349 def : Pat<(atomic_store_64 ixaddr:$ptr, i64:$val), (STD g8rc:$val, memrix:$ptr)>;
1350 def : Pat<(atomic_store_64 xaddr:$ptr, i64:$val), (STDX g8rc:$val, memrr:$ptr)>;
1352 let Predicates = [IsISA3_0] in {
1354 class X_L1_RA5_RB5<bits<6> opcode, bits<10> xo, string opc, RegisterOperand ty,
1355 InstrItinClass itin, list<dag> pattern>
1356 : X_L1_RS5_RS5<opcode, xo, (outs), (ins ty:$rA, ty:$rB, u1imm:$L),
1357 !strconcat(opc, " $rA, $rB, $L"), itin, pattern>;
1359 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
1360 def CP_COPY8 : X_L1_RA5_RB5<31, 774, "copy" , g8rc, IIC_LdStCOPY, []>;
1361 def CP_PASTE8 : X_L1_RA5_RB5<31, 902, "paste" , g8rc, IIC_LdStPASTE, []>;
1362 def CP_PASTE8o : X_L1_RA5_RB5<31, 902, "paste.", g8rc, IIC_LdStPASTE, []>,isDOT;
1365 // SLB Invalidate Entry Global
1366 def SLBIEG : XForm_26<31, 466, (outs), (ins gprc:$RS, gprc:$RB),
1367 "slbieg $RS, $RB", IIC_SprSLBIEG, []>;
1369 def SLBSYNC : XForm_0<31, 338, (outs), (ins), "slbsync", IIC_SprSLBSYNC, []>;