1 //===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the PowerPC 64-bit instructions. These patterns are used
11 // both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
18 def s16imm64 : Operand<i64> {
19 let PrintMethod = "printS16ImmOperand";
20 let EncoderMethod = "getImm16Encoding";
21 let ParserMatchClass = PPCS16ImmAsmOperand;
22 let DecoderMethod = "decodeSImmOperand<16>";
24 def u16imm64 : Operand<i64> {
25 let PrintMethod = "printU16ImmOperand";
26 let EncoderMethod = "getImm16Encoding";
27 let ParserMatchClass = PPCU16ImmAsmOperand;
28 let DecoderMethod = "decodeUImmOperand<16>";
30 def s17imm64 : Operand<i64> {
31 // This operand type is used for addis/lis to allow the assembler parser
32 // to accept immediates in the range -65536..65535 for compatibility with
33 // the GNU assembler. The operand is treated as 16-bit otherwise.
34 let PrintMethod = "printS16ImmOperand";
35 let EncoderMethod = "getImm16Encoding";
36 let ParserMatchClass = PPCS17ImmAsmOperand;
37 let DecoderMethod = "decodeSImmOperand<16>";
39 def tocentry : Operand<iPTR> {
40 let MIOperandInfo = (ops i64imm:$imm);
42 def tlsreg : Operand<i64> {
43 let EncoderMethod = "getTLSRegEncoding";
44 let ParserMatchClass = PPCTLSRegOperand;
46 def tlsgd : Operand<i64> {}
47 def tlscall : Operand<i64> {
48 let PrintMethod = "printTLSCall";
49 let MIOperandInfo = (ops calltarget:$func, tlsgd:$sym);
50 let EncoderMethod = "getTLSCallEncoding";
53 //===----------------------------------------------------------------------===//
54 // 64-bit transformation functions.
57 def SHL64 : SDNodeXForm<imm, [{
58 // Transformation function: 63 - imm
59 return getI32Imm(63 - N->getZExtValue(), SDLoc(N));
62 def SRL64 : SDNodeXForm<imm, [{
63 // Transformation function: 64 - imm
64 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue(), SDLoc(N))
65 : getI32Imm(0, SDLoc(N));
69 //===----------------------------------------------------------------------===//
73 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
74 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
75 let isReturn = 1, Uses = [LR8, RM] in
76 def BLR8 : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB,
77 [(retflag)]>, Requires<[In64BitMode]>;
78 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR8] in {
79 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
81 Requires<[In64BitMode]>;
82 def BCCCTR8 : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond),
83 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB,
85 Requires<[In64BitMode]>;
87 def BCCTR8 : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi),
88 "bcctr 12, $bi, 0", IIC_BrB, []>,
89 Requires<[In64BitMode]>;
90 def BCCTR8n : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi),
91 "bcctr 4, $bi, 0", IIC_BrB, []>,
92 Requires<[In64BitMode]>;
97 def MovePCtoLR8 : Pseudo<(outs), (ins), "#MovePCtoLR8", []>,
100 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
101 let Defs = [CTR8], Uses = [CTR8] in {
102 def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
104 def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
108 let isReturn = 1, Defs = [CTR8], Uses = [CTR8, LR8, RM] in {
109 def BDZLR8 : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
110 "bdzlr", IIC_BrB, []>;
111 def BDNZLR8 : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
112 "bdnzlr", IIC_BrB, []>;
118 let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in {
119 // Convenient aliases for call instructions
121 def BL8 : IForm<18, 0, 1, (outs), (ins calltarget:$func),
122 "bl $func", IIC_BrB, []>; // See Pat patterns below.
124 def BL8_TLS : IForm<18, 0, 1, (outs), (ins tlscall:$func),
125 "bl $func", IIC_BrB, []>;
127 def BLA8 : IForm<18, 1, 1, (outs), (ins abscalltarget:$func),
128 "bla $func", IIC_BrB, [(PPCcall (i64 imm:$func))]>;
130 let Uses = [RM], isCodeGenOnly = 1 in {
131 def BL8_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24,
132 (outs), (ins calltarget:$func),
133 "bl $func\n\tnop", IIC_BrB, []>;
135 def BL8_NOP_TLS : IForm_and_DForm_4_zero<18, 0, 1, 24,
136 (outs), (ins tlscall:$func),
137 "bl $func\n\tnop", IIC_BrB, []>;
139 def BLA8_NOP : IForm_and_DForm_4_zero<18, 1, 1, 24,
140 (outs), (ins abscalltarget:$func),
141 "bla $func\n\tnop", IIC_BrB,
142 [(PPCcall_nop (i64 imm:$func))]>;
144 let Uses = [CTR8, RM] in {
145 def BCTRL8 : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
146 "bctrl", IIC_BrB, [(PPCbctrl)]>,
147 Requires<[In64BitMode]>;
149 let isCodeGenOnly = 1 in {
150 def BCCCTRL8 : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond),
151 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB,
153 Requires<[In64BitMode]>;
155 def BCCTRL8 : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi),
156 "bcctrl 12, $bi, 0", IIC_BrB, []>,
157 Requires<[In64BitMode]>;
158 def BCCTRL8n : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi),
159 "bcctrl 4, $bi, 0", IIC_BrB, []>,
160 Requires<[In64BitMode]>;
165 let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1,
166 Defs = [LR8, X2], Uses = [CTR8, RM], RST = 2 in {
167 def BCTRL8_LDinto_toc :
168 XLForm_2_ext_and_DSForm_1<19, 528, 20, 0, 1, 58, 0, (outs),
170 "bctrl\n\tld 2, $src", IIC_BrB,
171 [(PPCbctrl_load_toc ixaddr:$src)]>,
172 Requires<[In64BitMode]>;
175 } // Interpretation64Bit
177 // FIXME: Duplicating this for the asm parser should be unnecessary, but the
178 // previous definition must be marked as CodeGen only to prevent decoding
180 let Interpretation64Bit = 1, isAsmParserOnly = 1 in
181 let isCall = 1, PPC970_Unit = 7, Defs = [LR8], Uses = [RM] in
182 def BL8_TLS_ : IForm<18, 0, 1, (outs), (ins tlscall:$func),
183 "bl $func", IIC_BrB, []>;
186 def : Pat<(PPCcall (i64 tglobaladdr:$dst)),
187 (BL8 tglobaladdr:$dst)>;
188 def : Pat<(PPCcall_nop (i64 tglobaladdr:$dst)),
189 (BL8_NOP tglobaladdr:$dst)>;
191 def : Pat<(PPCcall (i64 texternalsym:$dst)),
192 (BL8 texternalsym:$dst)>;
193 def : Pat<(PPCcall_nop (i64 texternalsym:$dst)),
194 (BL8_NOP texternalsym:$dst)>;
197 // FIXME: some of these might be used with constant operands. This will result
198 // in constant materialization instructions that may be redundant. We currently
199 // clean this up in PPCMIPeephole with calls to
200 // PPCInstrInfo::convertToImmediateForm() but we should probably not emit them
201 // in the first place.
202 let usesCustomInserter = 1 in {
203 let Defs = [CR0] in {
204 def ATOMIC_LOAD_ADD_I64 : Pseudo<
205 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_ADD_I64",
206 [(set i64:$dst, (atomic_load_add_64 xoaddr:$ptr, i64:$incr))]>;
207 def ATOMIC_LOAD_SUB_I64 : Pseudo<
208 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_SUB_I64",
209 [(set i64:$dst, (atomic_load_sub_64 xoaddr:$ptr, i64:$incr))]>;
210 def ATOMIC_LOAD_OR_I64 : Pseudo<
211 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_OR_I64",
212 [(set i64:$dst, (atomic_load_or_64 xoaddr:$ptr, i64:$incr))]>;
213 def ATOMIC_LOAD_XOR_I64 : Pseudo<
214 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_XOR_I64",
215 [(set i64:$dst, (atomic_load_xor_64 xoaddr:$ptr, i64:$incr))]>;
216 def ATOMIC_LOAD_AND_I64 : Pseudo<
217 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_AND_i64",
218 [(set i64:$dst, (atomic_load_and_64 xoaddr:$ptr, i64:$incr))]>;
219 def ATOMIC_LOAD_NAND_I64 : Pseudo<
220 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_NAND_I64",
221 [(set i64:$dst, (atomic_load_nand_64 xoaddr:$ptr, i64:$incr))]>;
222 def ATOMIC_LOAD_MIN_I64 : Pseudo<
223 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_MIN_I64",
224 [(set i64:$dst, (atomic_load_min_64 xoaddr:$ptr, i64:$incr))]>;
225 def ATOMIC_LOAD_MAX_I64 : Pseudo<
226 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_MAX_I64",
227 [(set i64:$dst, (atomic_load_max_64 xoaddr:$ptr, i64:$incr))]>;
228 def ATOMIC_LOAD_UMIN_I64 : Pseudo<
229 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_UMIN_I64",
230 [(set i64:$dst, (atomic_load_umin_64 xoaddr:$ptr, i64:$incr))]>;
231 def ATOMIC_LOAD_UMAX_I64 : Pseudo<
232 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_UMAX_I64",
233 [(set i64:$dst, (atomic_load_umax_64 xoaddr:$ptr, i64:$incr))]>;
235 def ATOMIC_CMP_SWAP_I64 : Pseudo<
236 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$old, g8rc:$new), "#ATOMIC_CMP_SWAP_I64",
237 [(set i64:$dst, (atomic_cmp_swap_64 xoaddr:$ptr, i64:$old, i64:$new))]>;
239 def ATOMIC_SWAP_I64 : Pseudo<
240 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$new), "#ATOMIC_SWAP_I64",
241 [(set i64:$dst, (atomic_swap_64 xoaddr:$ptr, i64:$new))]>;
245 // Instructions to support atomic operations
246 let mayLoad = 1, hasSideEffects = 0 in {
247 def LDARX : XForm_1_memOp<31, 84, (outs g8rc:$rD), (ins memrr:$ptr),
248 "ldarx $rD, $ptr", IIC_LdStLDARX, []>;
250 // Instruction to support lock versions of atomics
251 // (EH=1 - see Power ISA 2.07 Book II 4.4.2)
252 def LDARXL : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr),
253 "ldarx $rD, $ptr, 1", IIC_LdStLDARX, []>, isDOT;
255 let hasExtraDefRegAllocReq = 1 in
256 def LDAT : X_RD5_RS5_IM5<31, 614, (outs g8rc:$rD), (ins g8rc:$rA, u5imm:$FC),
257 "ldat $rD, $rA, $FC", IIC_LdStLoad>, isPPC64,
258 Requires<[IsISA3_0]>;
261 let Defs = [CR0], mayStore = 1, mayLoad = 0, hasSideEffects = 0 in
262 def STDCX : XForm_1_memOp<31, 214, (outs), (ins g8rc:$rS, memrr:$dst),
263 "stdcx. $rS, $dst", IIC_LdStSTDCX, []>, isDOT;
265 let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in
266 def STDAT : X_RD5_RS5_IM5<31, 742, (outs), (ins g8rc:$rS, g8rc:$rA, u5imm:$FC),
267 "stdat $rS, $rA, $FC", IIC_LdStStore>, isPPC64,
268 Requires<[IsISA3_0]>;
270 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
271 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
272 def TCRETURNdi8 :Pseudo< (outs),
273 (ins calltarget:$dst, i32imm:$offset),
274 "#TC_RETURNd8 $dst $offset",
277 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
278 def TCRETURNai8 :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset),
279 "#TC_RETURNa8 $func $offset",
280 [(PPCtc_return (i64 imm:$func), imm:$offset)]>;
282 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
283 def TCRETURNri8 : Pseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset),
284 "#TC_RETURNr8 $dst $offset",
287 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
288 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR8, RM] in
289 def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
291 Requires<[In64BitMode]>;
293 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
294 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
295 def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
299 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
300 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
301 def TAILBA8 : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst),
304 } // Interpretation64Bit
306 def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm),
307 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>;
309 def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm),
310 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>;
312 def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm),
313 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>;
316 // 64-bit CR instructions
317 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
318 let hasSideEffects = 0 in {
319 // mtocrf's input needs to be prepared by shifting by an amount dependent
320 // on the cr register selected. Thus, post-ra anti-dep breaking must not
321 // later change that register assignment.
322 let hasExtraDefRegAllocReq = 1 in {
323 def MTOCRF8: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins g8rc:$ST),
324 "mtocrf $FXM, $ST", IIC_BrMCRX>,
325 PPC970_DGroup_First, PPC970_Unit_CRU;
327 // Similarly to mtocrf, the mask for mtcrf must be prepared in a way that
328 // is dependent on the cr fields being set.
329 def MTCRF8 : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, g8rc:$rS),
330 "mtcrf $FXM, $rS", IIC_BrMCRX>,
331 PPC970_MicroCode, PPC970_Unit_CRU;
332 } // hasExtraDefRegAllocReq = 1
334 // mfocrf's input needs to be prepared by shifting by an amount dependent
335 // on the cr register selected. Thus, post-ra anti-dep breaking must not
336 // later change that register assignment.
337 let hasExtraSrcRegAllocReq = 1 in {
338 def MFOCRF8: XFXForm_5a<31, 19, (outs g8rc:$rT), (ins crbitm:$FXM),
339 "mfocrf $rT, $FXM", IIC_SprMFCRF>,
340 PPC970_DGroup_First, PPC970_Unit_CRU;
342 // Similarly to mfocrf, the mask for mfcrf must be prepared in a way that
343 // is dependent on the cr fields being copied.
344 def MFCR8 : XFXForm_3<31, 19, (outs g8rc:$rT), (ins),
345 "mfcr $rT", IIC_SprMFCR>,
346 PPC970_MicroCode, PPC970_Unit_CRU;
347 } // hasExtraSrcRegAllocReq = 1
348 } // hasSideEffects = 0
350 let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
352 def EH_SjLj_SetJmp64 : Pseudo<(outs gprc:$dst), (ins memr:$buf),
354 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
355 Requires<[In64BitMode]>;
356 let isTerminator = 1 in
357 def EH_SjLj_LongJmp64 : Pseudo<(outs), (ins memr:$buf),
358 "#EH_SJLJ_LONGJMP64",
359 [(PPCeh_sjlj_longjmp addr:$buf)]>,
360 Requires<[In64BitMode]>;
363 def MFSPR8 : XFXForm_1<31, 339, (outs g8rc:$RT), (ins i32imm:$SPR),
364 "mfspr $RT, $SPR", IIC_SprMFSPR>;
365 def MTSPR8 : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, g8rc:$RT),
366 "mtspr $SPR, $RT", IIC_SprMTSPR>;
369 //===----------------------------------------------------------------------===//
370 // 64-bit SPR manipulation instrs.
372 let Uses = [CTR8] in {
373 def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs g8rc:$rT), (ins),
374 "mfctr $rT", IIC_SprMFSPR>,
375 PPC970_DGroup_First, PPC970_Unit_FXU;
377 let Pattern = [(PPCmtctr i64:$rS)], Defs = [CTR8] in {
378 def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS),
379 "mtctr $rS", IIC_SprMTSPR>,
380 PPC970_DGroup_First, PPC970_Unit_FXU;
382 let hasSideEffects = 1, Defs = [CTR8] in {
383 let Pattern = [(int_ppc_mtctr i64:$rS)] in
384 def MTCTR8loop : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS),
385 "mtctr $rS", IIC_SprMTSPR>,
386 PPC970_DGroup_First, PPC970_Unit_FXU;
389 let Pattern = [(set i64:$rT, readcyclecounter)] in
390 def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs g8rc:$rT), (ins),
391 "mfspr $rT, 268", IIC_SprMFTB>,
392 PPC970_DGroup_First, PPC970_Unit_FXU;
393 // Note that encoding mftb using mfspr is now the preferred form,
394 // and has been since at least ISA v2.03. The mftb instruction has
395 // now been phased out. Using mfspr, however, is known not to work on
398 let Defs = [X1], Uses = [X1] in
399 def DYNALLOC8 : Pseudo<(outs g8rc:$result), (ins g8rc:$negsize, memri:$fpsi),"#DYNALLOC8",
401 (PPCdynalloc i64:$negsize, iaddr:$fpsi))]>;
402 def DYNAREAOFFSET8 : Pseudo<(outs i64imm:$result), (ins memri:$fpsi), "#DYNAREAOFFSET8",
403 [(set i64:$result, (PPCdynareaoffset iaddr:$fpsi))]>;
405 let Defs = [LR8] in {
406 def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins g8rc:$rS),
407 "mtlr $rS", IIC_SprMTSPR>,
408 PPC970_DGroup_First, PPC970_Unit_FXU;
410 let Uses = [LR8] in {
411 def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs g8rc:$rT), (ins),
412 "mflr $rT", IIC_SprMFSPR>,
413 PPC970_DGroup_First, PPC970_Unit_FXU;
415 } // Interpretation64Bit
417 //===----------------------------------------------------------------------===//
418 // Fixed point instructions.
421 let PPC970_Unit = 1 in { // FXU Operations.
422 let Interpretation64Bit = 1 in {
423 let hasSideEffects = 0 in {
424 let isCodeGenOnly = 1 in {
426 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
427 def LI8 : DForm_2_r0<14, (outs g8rc:$rD), (ins s16imm64:$imm),
428 "li $rD, $imm", IIC_IntSimple,
429 [(set i64:$rD, imm64SExt16:$imm)]>;
430 def LIS8 : DForm_2_r0<15, (outs g8rc:$rD), (ins s17imm64:$imm),
431 "lis $rD, $imm", IIC_IntSimple,
432 [(set i64:$rD, imm16ShiftedSExt:$imm)]>;
436 let isCommutable = 1 in {
437 defm NAND8: XForm_6r<31, 476, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
438 "nand", "$rA, $rS, $rB", IIC_IntSimple,
439 [(set i64:$rA, (not (and i64:$rS, i64:$rB)))]>;
440 defm AND8 : XForm_6r<31, 28, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
441 "and", "$rA, $rS, $rB", IIC_IntSimple,
442 [(set i64:$rA, (and i64:$rS, i64:$rB))]>;
444 defm ANDC8: XForm_6r<31, 60, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
445 "andc", "$rA, $rS, $rB", IIC_IntSimple,
446 [(set i64:$rA, (and i64:$rS, (not i64:$rB)))]>;
447 let isCommutable = 1 in {
448 defm OR8 : XForm_6r<31, 444, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
449 "or", "$rA, $rS, $rB", IIC_IntSimple,
450 [(set i64:$rA, (or i64:$rS, i64:$rB))]>;
451 defm NOR8 : XForm_6r<31, 124, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
452 "nor", "$rA, $rS, $rB", IIC_IntSimple,
453 [(set i64:$rA, (not (or i64:$rS, i64:$rB)))]>;
455 defm ORC8 : XForm_6r<31, 412, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
456 "orc", "$rA, $rS, $rB", IIC_IntSimple,
457 [(set i64:$rA, (or i64:$rS, (not i64:$rB)))]>;
458 let isCommutable = 1 in {
459 defm EQV8 : XForm_6r<31, 284, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
460 "eqv", "$rA, $rS, $rB", IIC_IntSimple,
461 [(set i64:$rA, (not (xor i64:$rS, i64:$rB)))]>;
462 defm XOR8 : XForm_6r<31, 316, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
463 "xor", "$rA, $rS, $rB", IIC_IntSimple,
464 [(set i64:$rA, (xor i64:$rS, i64:$rB))]>;
465 } // let isCommutable = 1
467 // Logical ops with immediate.
468 let Defs = [CR0] in {
469 def ANDIo8 : DForm_4<28, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
470 "andi. $dst, $src1, $src2", IIC_IntGeneral,
471 [(set i64:$dst, (and i64:$src1, immZExt16:$src2))]>,
473 def ANDISo8 : DForm_4<29, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
474 "andis. $dst, $src1, $src2", IIC_IntGeneral,
475 [(set i64:$dst, (and i64:$src1, imm16ShiftedZExt:$src2))]>,
478 def ORI8 : DForm_4<24, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
479 "ori $dst, $src1, $src2", IIC_IntSimple,
480 [(set i64:$dst, (or i64:$src1, immZExt16:$src2))]>;
481 def ORIS8 : DForm_4<25, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
482 "oris $dst, $src1, $src2", IIC_IntSimple,
483 [(set i64:$dst, (or i64:$src1, imm16ShiftedZExt:$src2))]>;
484 def XORI8 : DForm_4<26, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
485 "xori $dst, $src1, $src2", IIC_IntSimple,
486 [(set i64:$dst, (xor i64:$src1, immZExt16:$src2))]>;
487 def XORIS8 : DForm_4<27, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
488 "xoris $dst, $src1, $src2", IIC_IntSimple,
489 [(set i64:$dst, (xor i64:$src1, imm16ShiftedZExt:$src2))]>;
491 let isCommutable = 1 in
492 defm ADD8 : XOForm_1r<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
493 "add", "$rT, $rA, $rB", IIC_IntSimple,
494 [(set i64:$rT, (add i64:$rA, i64:$rB))]>;
495 // ADD8 has a special form: reg = ADD8(reg, sym@tls) for use by the
496 // initial-exec thread-local storage model. We need to forbid r0 here -
497 // while it works for add just fine, the linker can relax this to local-exec
498 // addi, which won't work for r0.
499 def ADD8TLS : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc_nox0:$rA, tlsreg:$rB),
500 "add $rT, $rA, $rB", IIC_IntSimple,
501 [(set i64:$rT, (add i64:$rA, tglobaltlsaddr:$rB))]>;
503 def LBZXTLS : XForm_1<31, 87, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB),
504 "lbzx $rD, $rA, $rB", IIC_LdStLoad, []>;
505 def LHZXTLS : XForm_1<31, 279, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB),
506 "lhzx $rD, $rA, $rB", IIC_LdStLoad, []>;
507 def LWZXTLS : XForm_1<31, 23, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB),
508 "lwzx $rD, $rA, $rB", IIC_LdStLoad, []>;
509 def LDXTLS : XForm_1<31, 21, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB),
510 "ldx $rD, $rA, $rB", IIC_LdStLD, []>, isPPC64;
511 def LBZXTLS_32 : XForm_1<31, 87, (outs gprc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB),
512 "lbzx $rD, $rA, $rB", IIC_LdStLoad, []>;
513 def LHZXTLS_32 : XForm_1<31, 279, (outs gprc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB),
514 "lhzx $rD, $rA, $rB", IIC_LdStLoad, []>;
515 def LWZXTLS_32 : XForm_1<31, 23, (outs gprc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB),
516 "lwzx $rD, $rA, $rB", IIC_LdStLoad, []>;
520 let mayStore = 1 in {
521 def STBXTLS : XForm_8<31, 215, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB),
522 "stbx $rS, $rA, $rB", IIC_LdStStore, []>,
523 PPC970_DGroup_Cracked;
524 def STHXTLS : XForm_8<31, 407, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB),
525 "sthx $rS, $rA, $rB", IIC_LdStStore, []>,
526 PPC970_DGroup_Cracked;
527 def STWXTLS : XForm_8<31, 151, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB),
528 "stwx $rS, $rA, $rB", IIC_LdStStore, []>,
529 PPC970_DGroup_Cracked;
530 def STDXTLS : XForm_8<31, 149, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB),
531 "stdx $rS, $rA, $rB", IIC_LdStSTD, []>, isPPC64,
532 PPC970_DGroup_Cracked;
533 def STBXTLS_32 : XForm_8<31, 215, (outs), (ins gprc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB),
534 "stbx $rS, $rA, $rB", IIC_LdStStore, []>,
535 PPC970_DGroup_Cracked;
536 def STHXTLS_32 : XForm_8<31, 407, (outs), (ins gprc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB),
537 "sthx $rS, $rA, $rB", IIC_LdStStore, []>,
538 PPC970_DGroup_Cracked;
539 def STWXTLS_32 : XForm_8<31, 151, (outs), (ins gprc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB),
540 "stwx $rS, $rA, $rB", IIC_LdStStore, []>,
541 PPC970_DGroup_Cracked;
545 let isCommutable = 1 in
546 defm ADDC8 : XOForm_1rc<31, 10, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
547 "addc", "$rT, $rA, $rB", IIC_IntGeneral,
548 [(set i64:$rT, (addc i64:$rA, i64:$rB))]>,
549 PPC970_DGroup_Cracked;
551 let Defs = [CARRY] in
552 def ADDIC8 : DForm_2<12, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm),
553 "addic $rD, $rA, $imm", IIC_IntGeneral,
554 [(set i64:$rD, (addc i64:$rA, imm64SExt16:$imm))]>;
555 def ADDI8 : DForm_2<14, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s16imm64:$imm),
556 "addi $rD, $rA, $imm", IIC_IntSimple,
557 [(set i64:$rD, (add i64:$rA, imm64SExt16:$imm))]>;
558 def ADDIS8 : DForm_2<15, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s17imm64:$imm),
559 "addis $rD, $rA, $imm", IIC_IntSimple,
560 [(set i64:$rD, (add i64:$rA, imm16ShiftedSExt:$imm))]>;
562 let Defs = [CARRY] in {
563 def SUBFIC8: DForm_2< 8, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm),
564 "subfic $rD, $rA, $imm", IIC_IntGeneral,
565 [(set i64:$rD, (subc imm64SExt16:$imm, i64:$rA))]>;
567 defm SUBFC8 : XOForm_1rc<31, 8, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
568 "subfc", "$rT, $rA, $rB", IIC_IntGeneral,
569 [(set i64:$rT, (subc i64:$rB, i64:$rA))]>,
570 PPC970_DGroup_Cracked;
571 defm SUBF8 : XOForm_1r<31, 40, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
572 "subf", "$rT, $rA, $rB", IIC_IntGeneral,
573 [(set i64:$rT, (sub i64:$rB, i64:$rA))]>;
574 defm NEG8 : XOForm_3r<31, 104, 0, (outs g8rc:$rT), (ins g8rc:$rA),
575 "neg", "$rT, $rA", IIC_IntSimple,
576 [(set i64:$rT, (ineg i64:$rA))]>;
577 let Uses = [CARRY] in {
578 let isCommutable = 1 in
579 defm ADDE8 : XOForm_1rc<31, 138, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
580 "adde", "$rT, $rA, $rB", IIC_IntGeneral,
581 [(set i64:$rT, (adde i64:$rA, i64:$rB))]>;
582 defm ADDME8 : XOForm_3rc<31, 234, 0, (outs g8rc:$rT), (ins g8rc:$rA),
583 "addme", "$rT, $rA", IIC_IntGeneral,
584 [(set i64:$rT, (adde i64:$rA, -1))]>;
585 defm ADDZE8 : XOForm_3rc<31, 202, 0, (outs g8rc:$rT), (ins g8rc:$rA),
586 "addze", "$rT, $rA", IIC_IntGeneral,
587 [(set i64:$rT, (adde i64:$rA, 0))]>;
588 defm SUBFE8 : XOForm_1rc<31, 136, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
589 "subfe", "$rT, $rA, $rB", IIC_IntGeneral,
590 [(set i64:$rT, (sube i64:$rB, i64:$rA))]>;
591 defm SUBFME8 : XOForm_3rc<31, 232, 0, (outs g8rc:$rT), (ins g8rc:$rA),
592 "subfme", "$rT, $rA", IIC_IntGeneral,
593 [(set i64:$rT, (sube -1, i64:$rA))]>;
594 defm SUBFZE8 : XOForm_3rc<31, 200, 0, (outs g8rc:$rT), (ins g8rc:$rA),
595 "subfze", "$rT, $rA", IIC_IntGeneral,
596 [(set i64:$rT, (sube 0, i64:$rA))]>;
600 // FIXME: Duplicating this for the asm parser should be unnecessary, but the
601 // previous definition must be marked as CodeGen only to prevent decoding
603 let isAsmParserOnly = 1 in {
604 def ADD8TLS_ : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, tlsreg:$rB),
605 "add $rT, $rA, $rB", IIC_IntSimple, []>;
608 def LBZXTLS_ : XForm_1<31, 87, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB),
609 "lbzx $rD, $rA, $rB", IIC_LdStLoad, []>;
610 def LHZXTLS_ : XForm_1<31, 279, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB),
611 "lhzx $rD, $rA, $rB", IIC_LdStLoad, []>;
612 def LWZXTLS_ : XForm_1<31, 23, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB),
613 "lwzx $rD, $rA, $rB", IIC_LdStLoad, []>;
614 def LDXTLS_ : XForm_1<31, 21, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB),
615 "ldx $rD, $rA, $rB", IIC_LdStLD, []>, isPPC64;
618 let mayStore = 1 in {
619 def STBXTLS_ : XForm_8<31, 215, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB),
620 "stbx $rS, $rA, $rB", IIC_LdStStore, []>,
621 PPC970_DGroup_Cracked;
622 def STHXTLS_ : XForm_8<31, 407, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB),
623 "sthx $rS, $rA, $rB", IIC_LdStStore, []>,
624 PPC970_DGroup_Cracked;
625 def STWXTLS_ : XForm_8<31, 151, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB),
626 "stwx $rS, $rA, $rB", IIC_LdStStore, []>,
627 PPC970_DGroup_Cracked;
628 def STDXTLS_ : XForm_8<31, 149, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB),
629 "stdx $rS, $rA, $rB", IIC_LdStSTD, []>, isPPC64,
630 PPC970_DGroup_Cracked;
634 let isCommutable = 1 in {
635 defm MULHD : XOForm_1r<31, 73, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
636 "mulhd", "$rT, $rA, $rB", IIC_IntMulHW,
637 [(set i64:$rT, (mulhs i64:$rA, i64:$rB))]>;
638 defm MULHDU : XOForm_1r<31, 9, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
639 "mulhdu", "$rT, $rA, $rB", IIC_IntMulHWU,
640 [(set i64:$rT, (mulhu i64:$rA, i64:$rB))]>;
643 } // Interpretation64Bit
645 let isCompare = 1, hasSideEffects = 0 in {
646 def CMPD : XForm_16_ext<31, 0, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB),
647 "cmpd $crD, $rA, $rB", IIC_IntCompare>, isPPC64;
648 def CMPLD : XForm_16_ext<31, 32, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB),
649 "cmpld $crD, $rA, $rB", IIC_IntCompare>, isPPC64;
650 def CMPDI : DForm_5_ext<11, (outs crrc:$crD), (ins g8rc:$rA, s16imm64:$imm),
651 "cmpdi $crD, $rA, $imm", IIC_IntCompare>, isPPC64;
652 def CMPLDI : DForm_6_ext<10, (outs crrc:$dst), (ins g8rc:$src1, u16imm64:$src2),
653 "cmpldi $dst, $src1, $src2",
654 IIC_IntCompare>, isPPC64;
655 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
656 def CMPRB8 : X_BF3_L1_RS5_RS5<31, 192, (outs crbitrc:$BF),
657 (ins u1imm:$L, g8rc:$rA, g8rc:$rB),
658 "cmprb $BF, $L, $rA, $rB", IIC_IntCompare, []>,
659 Requires<[IsISA3_0]>;
660 def CMPEQB : X_BF3_RS5_RS5<31, 224, (outs crbitrc:$BF),
661 (ins g8rc:$rA, g8rc:$rB), "cmpeqb $BF, $rA, $rB",
662 IIC_IntCompare, []>, Requires<[IsISA3_0]>;
665 let hasSideEffects = 0 in {
666 defm SLD : XForm_6r<31, 27, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB),
667 "sld", "$rA, $rS, $rB", IIC_IntRotateD,
668 [(set i64:$rA, (PPCshl i64:$rS, i32:$rB))]>, isPPC64;
669 defm SRD : XForm_6r<31, 539, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB),
670 "srd", "$rA, $rS, $rB", IIC_IntRotateD,
671 [(set i64:$rA, (PPCsrl i64:$rS, i32:$rB))]>, isPPC64;
672 defm SRAD : XForm_6rc<31, 794, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB),
673 "srad", "$rA, $rS, $rB", IIC_IntRotateD,
674 [(set i64:$rA, (PPCsra i64:$rS, i32:$rB))]>, isPPC64;
676 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
677 defm CNTLZW8 : XForm_11r<31, 26, (outs g8rc:$rA), (ins g8rc:$rS),
678 "cntlzw", "$rA, $rS", IIC_IntGeneral, []>;
679 defm CNTTZW8 : XForm_11r<31, 538, (outs g8rc:$rA), (ins g8rc:$rS),
680 "cnttzw", "$rA, $rS", IIC_IntGeneral, []>,
681 Requires<[IsISA3_0]>;
683 defm EXTSB8 : XForm_11r<31, 954, (outs g8rc:$rA), (ins g8rc:$rS),
684 "extsb", "$rA, $rS", IIC_IntSimple,
685 [(set i64:$rA, (sext_inreg i64:$rS, i8))]>;
686 defm EXTSH8 : XForm_11r<31, 922, (outs g8rc:$rA), (ins g8rc:$rS),
687 "extsh", "$rA, $rS", IIC_IntSimple,
688 [(set i64:$rA, (sext_inreg i64:$rS, i16))]>;
690 defm SLW8 : XForm_6r<31, 24, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
691 "slw", "$rA, $rS, $rB", IIC_IntGeneral, []>;
692 defm SRW8 : XForm_6r<31, 536, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
693 "srw", "$rA, $rS, $rB", IIC_IntGeneral, []>;
694 } // Interpretation64Bit
697 let isCodeGenOnly = 1 in {
698 def EXTSB8_32_64 : XForm_11<31, 954, (outs g8rc:$rA), (ins gprc:$rS),
699 "extsb $rA, $rS", IIC_IntSimple, []>, isPPC64;
700 def EXTSH8_32_64 : XForm_11<31, 922, (outs g8rc:$rA), (ins gprc:$rS),
701 "extsh $rA, $rS", IIC_IntSimple, []>, isPPC64;
702 } // isCodeGenOnly for fast-isel
704 defm EXTSW : XForm_11r<31, 986, (outs g8rc:$rA), (ins g8rc:$rS),
705 "extsw", "$rA, $rS", IIC_IntSimple,
706 [(set i64:$rA, (sext_inreg i64:$rS, i32))]>, isPPC64;
707 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
708 defm EXTSW_32_64 : XForm_11r<31, 986, (outs g8rc:$rA), (ins gprc:$rS),
709 "extsw", "$rA, $rS", IIC_IntSimple,
710 [(set i64:$rA, (sext i32:$rS))]>, isPPC64;
711 let isCodeGenOnly = 1 in
712 def EXTSW_32 : XForm_11<31, 986, (outs gprc:$rA), (ins gprc:$rS),
713 "extsw $rA, $rS", IIC_IntSimple,
716 defm SRADI : XSForm_1rc<31, 413, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH),
717 "sradi", "$rA, $rS, $SH", IIC_IntRotateDI,
718 [(set i64:$rA, (sra i64:$rS, (i32 imm:$SH)))]>, isPPC64;
720 defm EXTSWSLI : XSForm_1r<31, 445, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH),
721 "extswsli", "$rA, $rS, $SH", IIC_IntRotateDI,
725 let isCodeGenOnly = 1, Defs = [CARRY] in
726 def SRADI_32 : XSForm_1<31, 413, (outs gprc:$rA), (ins gprc:$rS, u6imm:$SH),
727 "sradi $rA, $rS, $SH", IIC_IntRotateDI, []>, isPPC64;
729 defm CNTLZD : XForm_11r<31, 58, (outs g8rc:$rA), (ins g8rc:$rS),
730 "cntlzd", "$rA, $rS", IIC_IntGeneral,
731 [(set i64:$rA, (ctlz i64:$rS))]>;
732 defm CNTTZD : XForm_11r<31, 570, (outs g8rc:$rA), (ins g8rc:$rS),
733 "cnttzd", "$rA, $rS", IIC_IntGeneral,
734 [(set i64:$rA, (cttz i64:$rS))]>, Requires<[IsISA3_0]>;
735 def POPCNTD : XForm_11<31, 506, (outs g8rc:$rA), (ins g8rc:$rS),
736 "popcntd $rA, $rS", IIC_IntGeneral,
737 [(set i64:$rA, (ctpop i64:$rS))]>;
738 def BPERMD : XForm_6<31, 252, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
739 "bpermd $rA, $rS, $rB", IIC_IntGeneral,
740 [(set i64:$rA, (int_ppc_bpermd g8rc:$rS, g8rc:$rB))]>,
741 isPPC64, Requires<[HasBPERMD]>;
743 let isCodeGenOnly = 1, isCommutable = 1 in
744 def CMPB8 : XForm_6<31, 508, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
745 "cmpb $rA, $rS, $rB", IIC_IntGeneral,
746 [(set i64:$rA, (PPCcmpb i64:$rS, i64:$rB))]>;
748 // popcntw also does a population count on the high 32 bits (storing the
749 // results in the high 32-bits of the output). We'll ignore that here (which is
750 // safe because we never separately use the high part of the 64-bit registers).
751 def POPCNTW : XForm_11<31, 378, (outs gprc:$rA), (ins gprc:$rS),
752 "popcntw $rA, $rS", IIC_IntGeneral,
753 [(set i32:$rA, (ctpop i32:$rS))]>;
755 def POPCNTB : XForm_11<31, 122, (outs gprc:$rA), (ins gprc:$rS),
756 "popcntb $rA, $rS", IIC_IntGeneral, []>;
758 defm DIVD : XOForm_1rcr<31, 489, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
759 "divd", "$rT, $rA, $rB", IIC_IntDivD,
760 [(set i64:$rT, (sdiv i64:$rA, i64:$rB))]>, isPPC64;
761 defm DIVDU : XOForm_1rcr<31, 457, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
762 "divdu", "$rT, $rA, $rB", IIC_IntDivD,
763 [(set i64:$rT, (udiv i64:$rA, i64:$rB))]>, isPPC64;
764 def DIVDE : XOForm_1<31, 425, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
765 "divde $rT, $rA, $rB", IIC_IntDivD,
766 [(set i64:$rT, (int_ppc_divde g8rc:$rA, g8rc:$rB))]>,
767 isPPC64, Requires<[HasExtDiv]>;
769 let Predicates = [IsISA3_0] in {
770 def MADDHD : VAForm_1a<48, (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC),
771 "maddhd $RT, $RA, $RB, $RC", IIC_IntMulHD, []>, isPPC64;
772 def MADDHDU : VAForm_1a<49, (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC),
773 "maddhdu $RT, $RA, $RB, $RC", IIC_IntMulHD, []>, isPPC64;
774 def MADDLD : VAForm_1a<51, (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC),
775 "maddld $RT, $RA, $RB, $RC", IIC_IntMulHD, []>, isPPC64;
776 def SETB : XForm_44<31, 128, (outs g8rc:$RT), (ins crrc:$BFA),
777 "setb $RT, $BFA", IIC_IntGeneral>, isPPC64;
778 def DARN : XForm_45<31, 755, (outs g8rc:$RT), (ins i32imm:$L),
779 "darn $RT, $L", IIC_LdStLD>, isPPC64;
780 def ADDPCIS : DXForm<19, 2, (outs g8rc:$RT), (ins i32imm:$D),
781 "addpcis $RT, $D", IIC_BrB, []>, isPPC64;
782 def MODSD : XForm_8<31, 777, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
783 "modsd $rT, $rA, $rB", IIC_IntDivW,
784 [(set i64:$rT, (srem i64:$rA, i64:$rB))]>;
785 def MODUD : XForm_8<31, 265, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
786 "modud $rT, $rA, $rB", IIC_IntDivW,
787 [(set i64:$rT, (urem i64:$rA, i64:$rB))]>;
791 def DIVDEo : XOForm_1<31, 425, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
792 "divde. $rT, $rA, $rB", IIC_IntDivD,
793 []>, isDOT, PPC970_DGroup_Cracked, PPC970_DGroup_First,
794 isPPC64, Requires<[HasExtDiv]>;
795 def DIVDEU : XOForm_1<31, 393, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
796 "divdeu $rT, $rA, $rB", IIC_IntDivD,
797 [(set i64:$rT, (int_ppc_divdeu g8rc:$rA, g8rc:$rB))]>,
798 isPPC64, Requires<[HasExtDiv]>;
800 def DIVDEUo : XOForm_1<31, 393, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
801 "divdeu. $rT, $rA, $rB", IIC_IntDivD,
802 []>, isDOT, PPC970_DGroup_Cracked, PPC970_DGroup_First,
803 isPPC64, Requires<[HasExtDiv]>;
804 let isCommutable = 1 in
805 defm MULLD : XOForm_1r<31, 233, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
806 "mulld", "$rT, $rA, $rB", IIC_IntMulHD,
807 [(set i64:$rT, (mul i64:$rA, i64:$rB))]>, isPPC64;
808 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
809 def MULLI8 : DForm_2<7, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm),
810 "mulli $rD, $rA, $imm", IIC_IntMulLI,
811 [(set i64:$rD, (mul i64:$rA, imm64SExt16:$imm))]>;
814 let hasSideEffects = 0 in {
815 defm RLDIMI : MDForm_1r<30, 3, (outs g8rc:$rA),
816 (ins g8rc:$rSi, g8rc:$rS, u6imm:$SH, u6imm:$MBE),
817 "rldimi", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI,
818 []>, isPPC64, RegConstraint<"$rSi = $rA">,
821 // Rotate instructions.
822 defm RLDCL : MDSForm_1r<30, 8,
823 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE),
824 "rldcl", "$rA, $rS, $rB, $MBE", IIC_IntRotateD,
826 defm RLDCR : MDSForm_1r<30, 9,
827 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE),
828 "rldcr", "$rA, $rS, $rB, $MBE", IIC_IntRotateD,
830 defm RLDICL : MDForm_1r<30, 0,
831 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE),
832 "rldicl", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI,
835 let isCodeGenOnly = 1 in
836 def RLDICL_32_64 : MDForm_1<30, 0,
838 (ins gprc:$rS, u6imm:$SH, u6imm:$MBE),
839 "rldicl $rA, $rS, $SH, $MBE", IIC_IntRotateDI,
842 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
843 defm RLDICL_32 : MDForm_1r<30, 0,
845 (ins gprc:$rS, u6imm:$SH, u6imm:$MBE),
846 "rldicl", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI,
848 defm RLDICR : MDForm_1r<30, 1,
849 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE),
850 "rldicr", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI,
852 let isCodeGenOnly = 1 in
853 def RLDICR_32 : MDForm_1<30, 1,
854 (outs gprc:$rA), (ins gprc:$rS, u6imm:$SH, u6imm:$MBE),
855 "rldicr $rA, $rS, $SH, $MBE", IIC_IntRotateDI,
857 defm RLDIC : MDForm_1r<30, 2,
858 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE),
859 "rldic", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI,
862 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
863 defm RLWINM8 : MForm_2r<21, (outs g8rc:$rA),
864 (ins g8rc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
865 "rlwinm", "$rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
868 defm RLWNM8 : MForm_2r<23, (outs g8rc:$rA),
869 (ins g8rc:$rS, g8rc:$rB, u5imm:$MB, u5imm:$ME),
870 "rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral,
873 // RLWIMI can be commuted if the rotate amount is zero.
874 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
875 defm RLWIMI8 : MForm_2r<20, (outs g8rc:$rA),
876 (ins g8rc:$rSi, g8rc:$rS, u5imm:$SH, u5imm:$MB,
877 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME",
878 IIC_IntRotate, []>, PPC970_DGroup_Cracked,
879 RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">;
882 def ISEL8 : AForm_4<31, 15,
883 (outs g8rc:$rT), (ins g8rc_nox0:$rA, g8rc:$rB, crbitrc:$cond),
884 "isel $rT, $rA, $rB, $cond", IIC_IntISEL,
886 } // Interpretation64Bit
887 } // hasSideEffects = 0
888 } // End FXU Operations.
891 //===----------------------------------------------------------------------===//
892 // Load/Store instructions.
896 // Sign extending loads.
897 let PPC970_Unit = 2 in {
898 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
899 def LHA8: DForm_1<42, (outs g8rc:$rD), (ins memri:$src),
900 "lha $rD, $src", IIC_LdStLHA,
901 [(set i64:$rD, (sextloadi16 iaddr:$src))]>,
902 PPC970_DGroup_Cracked;
903 def LWA : DSForm_1<58, 2, (outs g8rc:$rD), (ins memrix:$src),
904 "lwa $rD, $src", IIC_LdStLWA,
906 (aligned4sextloadi32 ixaddr:$src))]>, isPPC64,
907 PPC970_DGroup_Cracked;
908 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
909 def LHAX8: XForm_1_memOp<31, 343, (outs g8rc:$rD), (ins memrr:$src),
910 "lhax $rD, $src", IIC_LdStLHA,
911 [(set i64:$rD, (sextloadi16 xaddr:$src))]>,
912 PPC970_DGroup_Cracked;
913 def LWAX : XForm_1_memOp<31, 341, (outs g8rc:$rD), (ins memrr:$src),
914 "lwax $rD, $src", IIC_LdStLHA,
915 [(set i64:$rD, (sextloadi32 xaddr:$src))]>, isPPC64,
916 PPC970_DGroup_Cracked;
918 let isCodeGenOnly = 1, mayLoad = 1 in {
919 def LWA_32 : DSForm_1<58, 2, (outs gprc:$rD), (ins memrix:$src),
920 "lwa $rD, $src", IIC_LdStLWA, []>, isPPC64,
921 PPC970_DGroup_Cracked;
922 def LWAX_32 : XForm_1_memOp<31, 341, (outs gprc:$rD), (ins memrr:$src),
923 "lwax $rD, $src", IIC_LdStLHA, []>, isPPC64,
924 PPC970_DGroup_Cracked;
925 } // end fast-isel isCodeGenOnly
928 let mayLoad = 1, hasSideEffects = 0 in {
929 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
930 def LHAU8 : DForm_1<43, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
932 "lhau $rD, $addr", IIC_LdStLHAU,
933 []>, RegConstraint<"$addr.reg = $ea_result">,
934 NoEncode<"$ea_result">;
937 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
938 def LHAUX8 : XForm_1_memOp<31, 375, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
940 "lhaux $rD, $addr", IIC_LdStLHAUX,
941 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
942 NoEncode<"$ea_result">;
943 def LWAUX : XForm_1_memOp<31, 373, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
945 "lwaux $rD, $addr", IIC_LdStLHAUX,
946 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
947 NoEncode<"$ea_result">, isPPC64;
951 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
952 // Zero extending loads.
953 let PPC970_Unit = 2 in {
954 def LBZ8 : DForm_1<34, (outs g8rc:$rD), (ins memri:$src),
955 "lbz $rD, $src", IIC_LdStLoad,
956 [(set i64:$rD, (zextloadi8 iaddr:$src))]>;
957 def LHZ8 : DForm_1<40, (outs g8rc:$rD), (ins memri:$src),
958 "lhz $rD, $src", IIC_LdStLoad,
959 [(set i64:$rD, (zextloadi16 iaddr:$src))]>;
960 def LWZ8 : DForm_1<32, (outs g8rc:$rD), (ins memri:$src),
961 "lwz $rD, $src", IIC_LdStLoad,
962 [(set i64:$rD, (zextloadi32 iaddr:$src))]>, isPPC64;
964 def LBZX8 : XForm_1_memOp<31, 87, (outs g8rc:$rD), (ins memrr:$src),
965 "lbzx $rD, $src", IIC_LdStLoad,
966 [(set i64:$rD, (zextloadi8 xaddr:$src))]>;
967 def LHZX8 : XForm_1_memOp<31, 279, (outs g8rc:$rD), (ins memrr:$src),
968 "lhzx $rD, $src", IIC_LdStLoad,
969 [(set i64:$rD, (zextloadi16 xaddr:$src))]>;
970 def LWZX8 : XForm_1_memOp<31, 23, (outs g8rc:$rD), (ins memrr:$src),
971 "lwzx $rD, $src", IIC_LdStLoad,
972 [(set i64:$rD, (zextloadi32 xaddr:$src))]>;
976 let mayLoad = 1, hasSideEffects = 0 in {
977 def LBZU8 : DForm_1<35, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
979 "lbzu $rD, $addr", IIC_LdStLoadUpd,
980 []>, RegConstraint<"$addr.reg = $ea_result">,
981 NoEncode<"$ea_result">;
982 def LHZU8 : DForm_1<41, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
984 "lhzu $rD, $addr", IIC_LdStLoadUpd,
985 []>, RegConstraint<"$addr.reg = $ea_result">,
986 NoEncode<"$ea_result">;
987 def LWZU8 : DForm_1<33, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
989 "lwzu $rD, $addr", IIC_LdStLoadUpd,
990 []>, RegConstraint<"$addr.reg = $ea_result">,
991 NoEncode<"$ea_result">;
993 def LBZUX8 : XForm_1_memOp<31, 119, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
995 "lbzux $rD, $addr", IIC_LdStLoadUpdX,
996 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
997 NoEncode<"$ea_result">;
998 def LHZUX8 : XForm_1_memOp<31, 311, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
1000 "lhzux $rD, $addr", IIC_LdStLoadUpdX,
1001 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1002 NoEncode<"$ea_result">;
1003 def LWZUX8 : XForm_1_memOp<31, 55, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
1005 "lwzux $rD, $addr", IIC_LdStLoadUpdX,
1006 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1007 NoEncode<"$ea_result">;
1010 } // Interpretation64Bit
1013 // Full 8-byte loads.
1014 let PPC970_Unit = 2 in {
1015 def LD : DSForm_1<58, 0, (outs g8rc:$rD), (ins memrix:$src),
1016 "ld $rD, $src", IIC_LdStLD,
1017 [(set i64:$rD, (aligned4load ixaddr:$src))]>, isPPC64;
1018 // The following four definitions are selected for small code model only.
1019 // Otherwise, we need to create two instructions to form a 32-bit offset,
1020 // so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select().
1021 def LDtoc: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
1024 (PPCtoc_entry tglobaladdr:$disp, i64:$reg))]>, isPPC64;
1025 def LDtocJTI: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
1028 (PPCtoc_entry tjumptable:$disp, i64:$reg))]>, isPPC64;
1029 def LDtocCPT: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
1032 (PPCtoc_entry tconstpool:$disp, i64:$reg))]>, isPPC64;
1033 def LDtocBA: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
1036 (PPCtoc_entry tblockaddress:$disp, i64:$reg))]>, isPPC64;
1038 def LDX : XForm_1_memOp<31, 21, (outs g8rc:$rD), (ins memrr:$src),
1039 "ldx $rD, $src", IIC_LdStLD,
1040 [(set i64:$rD, (load xaddr:$src))]>, isPPC64;
1041 def LDBRX : XForm_1_memOp<31, 532, (outs g8rc:$rD), (ins memrr:$src),
1042 "ldbrx $rD, $src", IIC_LdStLoad,
1043 [(set i64:$rD, (PPClbrx xoaddr:$src, i64))]>, isPPC64;
1045 let mayLoad = 1, hasSideEffects = 0, isCodeGenOnly = 1 in {
1046 def LHBRX8 : XForm_1_memOp<31, 790, (outs g8rc:$rD), (ins memrr:$src),
1047 "lhbrx $rD, $src", IIC_LdStLoad, []>;
1048 def LWBRX8 : XForm_1_memOp<31, 534, (outs g8rc:$rD), (ins memrr:$src),
1049 "lwbrx $rD, $src", IIC_LdStLoad, []>;
1052 let mayLoad = 1, hasSideEffects = 0 in {
1053 def LDU : DSForm_1<58, 1, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
1055 "ldu $rD, $addr", IIC_LdStLDU,
1056 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64,
1057 NoEncode<"$ea_result">;
1059 def LDUX : XForm_1_memOp<31, 53, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
1061 "ldux $rD, $addr", IIC_LdStLDUX,
1062 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1063 NoEncode<"$ea_result">, isPPC64;
1065 def LDMX : XForm_1<31, 309, (outs g8rc:$rD), (ins memrr:$src),
1066 "ldmx $rD, $src", IIC_LdStLD, []>, isPPC64,
1067 Requires<[IsISA3_0]>;
1071 // Support for medium and large code model.
1072 let hasSideEffects = 0 in {
1073 let isReMaterializable = 1 in {
1074 def ADDIStocHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp),
1075 "#ADDIStocHA", []>, isPPC64;
1076 def ADDItocL: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp),
1077 "#ADDItocL", []>, isPPC64;
1080 def LDtocL: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc_nox0:$reg),
1081 "#LDtocL", []>, isPPC64;
1084 // Support for thread-local storage.
1085 def ADDISgotTprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
1088 (PPCaddisGotTprelHA i64:$reg,
1089 tglobaltlsaddr:$disp))]>,
1091 def LDgotTprelL: Pseudo<(outs g8rc:$rD), (ins s16imm64:$disp, g8rc_nox0:$reg),
1094 (PPCldGotTprelL tglobaltlsaddr:$disp, i64:$reg))]>,
1097 let isPseudo = 1, Defs = [CR7], Itinerary = IIC_LdStSync in
1098 def CFENCE8 : Pseudo<(outs), (ins g8rc:$cr), "#CFENCE8", []>;
1100 def : Pat<(PPCaddTls i64:$in, tglobaltlsaddr:$g),
1101 (ADD8TLS $in, tglobaltlsaddr:$g)>;
1102 def ADDIStlsgdHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
1105 (PPCaddisTlsgdHA i64:$reg, tglobaltlsaddr:$disp))]>,
1107 def ADDItlsgdL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
1110 (PPCaddiTlsgdL i64:$reg, tglobaltlsaddr:$disp))]>,
1112 // LR8 is a true define, while the rest of the Defs are clobbers. X3 is
1113 // explicitly defined when this op is created, so not mentioned here.
1114 // This is lowered to BL8_NOP_TLS by the assembly printer, so the size must be
1115 // correct because the branch select pass is relying on it.
1116 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, Size = 8,
1117 Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in
1118 def GETtlsADDR : Pseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym),
1121 (PPCgetTlsAddr i64:$reg, tglobaltlsaddr:$sym))]>,
1123 // Combined op for ADDItlsgdL and GETtlsADDR, late expanded. X3 and LR8
1124 // are true defines while the rest of the Defs are clobbers.
1125 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
1126 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7]
1128 def ADDItlsgdLADDR : Pseudo<(outs g8rc:$rD),
1129 (ins g8rc_nox0:$reg, s16imm64:$disp, tlsgd:$sym),
1132 (PPCaddiTlsgdLAddr i64:$reg,
1133 tglobaltlsaddr:$disp,
1134 tglobaltlsaddr:$sym))]>,
1136 def ADDIStlsldHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
1139 (PPCaddisTlsldHA i64:$reg, tglobaltlsaddr:$disp))]>,
1141 def ADDItlsldL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
1144 (PPCaddiTlsldL i64:$reg, tglobaltlsaddr:$disp))]>,
1146 // LR8 is a true define, while the rest of the Defs are clobbers. X3 is
1147 // explicitly defined when this op is created, so not mentioned here.
1148 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
1149 Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in
1150 def GETtlsldADDR : Pseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym),
1153 (PPCgetTlsldAddr i64:$reg, tglobaltlsaddr:$sym))]>,
1155 // Combined op for ADDItlsldL and GETtlsADDR, late expanded. X3 and LR8
1156 // are true defines, while the rest of the Defs are clobbers.
1157 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
1158 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7]
1160 def ADDItlsldLADDR : Pseudo<(outs g8rc:$rD),
1161 (ins g8rc_nox0:$reg, s16imm64:$disp, tlsgd:$sym),
1164 (PPCaddiTlsldLAddr i64:$reg,
1165 tglobaltlsaddr:$disp,
1166 tglobaltlsaddr:$sym))]>,
1168 def ADDISdtprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
1171 (PPCaddisDtprelHA i64:$reg,
1172 tglobaltlsaddr:$disp))]>,
1174 def ADDIdtprelL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
1177 (PPCaddiDtprelL i64:$reg, tglobaltlsaddr:$disp))]>,
1180 let PPC970_Unit = 2 in {
1181 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
1182 // Truncating stores.
1183 def STB8 : DForm_1<38, (outs), (ins g8rc:$rS, memri:$src),
1184 "stb $rS, $src", IIC_LdStStore,
1185 [(truncstorei8 i64:$rS, iaddr:$src)]>;
1186 def STH8 : DForm_1<44, (outs), (ins g8rc:$rS, memri:$src),
1187 "sth $rS, $src", IIC_LdStStore,
1188 [(truncstorei16 i64:$rS, iaddr:$src)]>;
1189 def STW8 : DForm_1<36, (outs), (ins g8rc:$rS, memri:$src),
1190 "stw $rS, $src", IIC_LdStStore,
1191 [(truncstorei32 i64:$rS, iaddr:$src)]>;
1192 def STBX8 : XForm_8_memOp<31, 215, (outs), (ins g8rc:$rS, memrr:$dst),
1193 "stbx $rS, $dst", IIC_LdStStore,
1194 [(truncstorei8 i64:$rS, xaddr:$dst)]>,
1195 PPC970_DGroup_Cracked;
1196 def STHX8 : XForm_8_memOp<31, 407, (outs), (ins g8rc:$rS, memrr:$dst),
1197 "sthx $rS, $dst", IIC_LdStStore,
1198 [(truncstorei16 i64:$rS, xaddr:$dst)]>,
1199 PPC970_DGroup_Cracked;
1200 def STWX8 : XForm_8_memOp<31, 151, (outs), (ins g8rc:$rS, memrr:$dst),
1201 "stwx $rS, $dst", IIC_LdStStore,
1202 [(truncstorei32 i64:$rS, xaddr:$dst)]>,
1203 PPC970_DGroup_Cracked;
1204 } // Interpretation64Bit
1206 // Normal 8-byte stores.
1207 def STD : DSForm_1<62, 0, (outs), (ins g8rc:$rS, memrix:$dst),
1208 "std $rS, $dst", IIC_LdStSTD,
1209 [(aligned4store i64:$rS, ixaddr:$dst)]>, isPPC64;
1210 def STDX : XForm_8_memOp<31, 149, (outs), (ins g8rc:$rS, memrr:$dst),
1211 "stdx $rS, $dst", IIC_LdStSTD,
1212 [(store i64:$rS, xaddr:$dst)]>, isPPC64,
1213 PPC970_DGroup_Cracked;
1214 def STDBRX: XForm_8_memOp<31, 660, (outs), (ins g8rc:$rS, memrr:$dst),
1215 "stdbrx $rS, $dst", IIC_LdStStore,
1216 [(PPCstbrx i64:$rS, xoaddr:$dst, i64)]>, isPPC64,
1217 PPC970_DGroup_Cracked;
1220 // Stores with Update (pre-inc).
1221 let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in {
1222 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
1223 def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst),
1224 "stbu $rS, $dst", IIC_LdStStoreUpd, []>,
1225 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1226 def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst),
1227 "sthu $rS, $dst", IIC_LdStStoreUpd, []>,
1228 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1229 def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst),
1230 "stwu $rS, $dst", IIC_LdStStoreUpd, []>,
1231 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1233 def STBUX8: XForm_8_memOp<31, 247, (outs ptr_rc_nor0:$ea_res),
1234 (ins g8rc:$rS, memrr:$dst),
1235 "stbux $rS, $dst", IIC_LdStStoreUpd, []>,
1236 RegConstraint<"$dst.ptrreg = $ea_res">,
1237 NoEncode<"$ea_res">,
1238 PPC970_DGroup_Cracked;
1239 def STHUX8: XForm_8_memOp<31, 439, (outs ptr_rc_nor0:$ea_res),
1240 (ins g8rc:$rS, memrr:$dst),
1241 "sthux $rS, $dst", IIC_LdStStoreUpd, []>,
1242 RegConstraint<"$dst.ptrreg = $ea_res">,
1243 NoEncode<"$ea_res">,
1244 PPC970_DGroup_Cracked;
1245 def STWUX8: XForm_8_memOp<31, 183, (outs ptr_rc_nor0:$ea_res),
1246 (ins g8rc:$rS, memrr:$dst),
1247 "stwux $rS, $dst", IIC_LdStStoreUpd, []>,
1248 RegConstraint<"$dst.ptrreg = $ea_res">,
1249 NoEncode<"$ea_res">,
1250 PPC970_DGroup_Cracked;
1251 } // Interpretation64Bit
1253 def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res),
1254 (ins g8rc:$rS, memrix:$dst),
1255 "stdu $rS, $dst", IIC_LdStSTDU, []>,
1256 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">,
1259 def STDUX : XForm_8_memOp<31, 181, (outs ptr_rc_nor0:$ea_res),
1260 (ins g8rc:$rS, memrr:$dst),
1261 "stdux $rS, $dst", IIC_LdStSTDUX, []>,
1262 RegConstraint<"$dst.ptrreg = $ea_res">,
1263 NoEncode<"$ea_res">,
1264 PPC970_DGroup_Cracked, isPPC64;
1267 // Patterns to match the pre-inc stores. We can't put the patterns on
1268 // the instruction definitions directly as ISel wants the address base
1269 // and offset to be separate operands, not a single complex operand.
1270 def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1271 (STBU8 $rS, iaddroff:$ptroff, $ptrreg)>;
1272 def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1273 (STHU8 $rS, iaddroff:$ptroff, $ptrreg)>;
1274 def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1275 (STWU8 $rS, iaddroff:$ptroff, $ptrreg)>;
1276 def : Pat<(aligned4pre_store i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1277 (STDU $rS, iaddroff:$ptroff, $ptrreg)>;
1279 def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1280 (STBUX8 $rS, $ptrreg, $ptroff)>;
1281 def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1282 (STHUX8 $rS, $ptrreg, $ptroff)>;
1283 def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1284 (STWUX8 $rS, $ptrreg, $ptroff)>;
1285 def : Pat<(pre_store i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1286 (STDUX $rS, $ptrreg, $ptroff)>;
1289 //===----------------------------------------------------------------------===//
1290 // Floating point instructions.
1294 let PPC970_Unit = 3, hasSideEffects = 0,
1295 Uses = [RM] in { // FPU Operations.
1296 defm FCFID : XForm_26r<63, 846, (outs f8rc:$frD), (ins f8rc:$frB),
1297 "fcfid", "$frD, $frB", IIC_FPGeneral,
1298 [(set f64:$frD, (PPCfcfid f64:$frB))]>, isPPC64;
1299 defm FCTID : XForm_26r<63, 814, (outs f8rc:$frD), (ins f8rc:$frB),
1300 "fctid", "$frD, $frB", IIC_FPGeneral,
1302 defm FCTIDU : XForm_26r<63, 942, (outs f8rc:$frD), (ins f8rc:$frB),
1303 "fctidu", "$frD, $frB", IIC_FPGeneral,
1305 defm FCTIDZ : XForm_26r<63, 815, (outs f8rc:$frD), (ins f8rc:$frB),
1306 "fctidz", "$frD, $frB", IIC_FPGeneral,
1307 [(set f64:$frD, (PPCfctidz f64:$frB))]>, isPPC64;
1309 defm FCFIDU : XForm_26r<63, 974, (outs f8rc:$frD), (ins f8rc:$frB),
1310 "fcfidu", "$frD, $frB", IIC_FPGeneral,
1311 [(set f64:$frD, (PPCfcfidu f64:$frB))]>, isPPC64;
1312 defm FCFIDS : XForm_26r<59, 846, (outs f4rc:$frD), (ins f8rc:$frB),
1313 "fcfids", "$frD, $frB", IIC_FPGeneral,
1314 [(set f32:$frD, (PPCfcfids f64:$frB))]>, isPPC64;
1315 defm FCFIDUS : XForm_26r<59, 974, (outs f4rc:$frD), (ins f8rc:$frB),
1316 "fcfidus", "$frD, $frB", IIC_FPGeneral,
1317 [(set f32:$frD, (PPCfcfidus f64:$frB))]>, isPPC64;
1318 defm FCTIDUZ : XForm_26r<63, 943, (outs f8rc:$frD), (ins f8rc:$frB),
1319 "fctiduz", "$frD, $frB", IIC_FPGeneral,
1320 [(set f64:$frD, (PPCfctiduz f64:$frB))]>, isPPC64;
1321 defm FCTIWUZ : XForm_26r<63, 143, (outs f8rc:$frD), (ins f8rc:$frB),
1322 "fctiwuz", "$frD, $frB", IIC_FPGeneral,
1323 [(set f64:$frD, (PPCfctiwuz f64:$frB))]>, isPPC64;
1327 //===----------------------------------------------------------------------===//
1328 // Instruction Patterns
1331 // Extensions and truncates to/from 32-bit regs.
1332 def : Pat<(i64 (zext i32:$in)),
1333 (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32),
1335 def : Pat<(i64 (anyext i32:$in)),
1336 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32)>;
1337 def : Pat<(i32 (trunc i64:$in)),
1338 (EXTRACT_SUBREG $in, sub_32)>;
1340 // Implement the 'not' operation with the NOR instruction.
1341 // (we could use the default xori pattern, but nor has lower latency on some
1342 // cores (such as the A2)).
1343 def i64not : OutPatFrag<(ops node:$in),
1345 def : Pat<(not i64:$in),
1348 // Extending loads with i64 targets.
1349 def : Pat<(zextloadi1 iaddr:$src),
1351 def : Pat<(zextloadi1 xaddr:$src),
1352 (LBZX8 xaddr:$src)>;
1353 def : Pat<(extloadi1 iaddr:$src),
1355 def : Pat<(extloadi1 xaddr:$src),
1356 (LBZX8 xaddr:$src)>;
1357 def : Pat<(extloadi8 iaddr:$src),
1359 def : Pat<(extloadi8 xaddr:$src),
1360 (LBZX8 xaddr:$src)>;
1361 def : Pat<(extloadi16 iaddr:$src),
1363 def : Pat<(extloadi16 xaddr:$src),
1364 (LHZX8 xaddr:$src)>;
1365 def : Pat<(extloadi32 iaddr:$src),
1367 def : Pat<(extloadi32 xaddr:$src),
1368 (LWZX8 xaddr:$src)>;
1370 // Standard shifts. These are represented separately from the real shifts above
1371 // so that we can distinguish between shifts that allow 6-bit and 7-bit shift
1373 def : Pat<(sra i64:$rS, i32:$rB),
1375 def : Pat<(srl i64:$rS, i32:$rB),
1377 def : Pat<(shl i64:$rS, i32:$rB),
1381 def : Pat<(sub imm64SExt16:$imm, i64:$in),
1382 (SUBFIC8 $in, imm:$imm)>;
1385 def : Pat<(shl i64:$in, (i32 imm:$imm)),
1386 (RLDICR $in, imm:$imm, (SHL64 imm:$imm))>;
1387 def : Pat<(srl i64:$in, (i32 imm:$imm)),
1388 (RLDICL $in, (SRL64 imm:$imm), imm:$imm)>;
1391 def : Pat<(rotl i64:$in, i32:$sh),
1392 (RLDCL $in, $sh, 0)>;
1393 def : Pat<(rotl i64:$in, (i32 imm:$imm)),
1394 (RLDICL $in, imm:$imm, 0)>;
1396 // Hi and Lo for Darwin Global Addresses.
1397 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>;
1398 def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>;
1399 def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>;
1400 def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>;
1401 def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>;
1402 def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>;
1403 def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>;
1404 def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>;
1405 def : Pat<(PPChi tglobaltlsaddr:$g, i64:$in),
1406 (ADDIS8 $in, tglobaltlsaddr:$g)>;
1407 def : Pat<(PPClo tglobaltlsaddr:$g, i64:$in),
1408 (ADDI8 $in, tglobaltlsaddr:$g)>;
1409 def : Pat<(add i64:$in, (PPChi tglobaladdr:$g, 0)),
1410 (ADDIS8 $in, tglobaladdr:$g)>;
1411 def : Pat<(add i64:$in, (PPChi tconstpool:$g, 0)),
1412 (ADDIS8 $in, tconstpool:$g)>;
1413 def : Pat<(add i64:$in, (PPChi tjumptable:$g, 0)),
1414 (ADDIS8 $in, tjumptable:$g)>;
1415 def : Pat<(add i64:$in, (PPChi tblockaddress:$g, 0)),
1416 (ADDIS8 $in, tblockaddress:$g)>;
1418 // Patterns to match r+r indexed loads and stores for
1419 // addresses without at least 4-byte alignment.
1420 def : Pat<(i64 (unaligned4sextloadi32 xoaddr:$src)),
1421 (LWAX xoaddr:$src)>;
1422 def : Pat<(i64 (unaligned4load xoaddr:$src)),
1424 def : Pat<(unaligned4store i64:$rS, xoaddr:$dst),
1425 (STDX $rS, xoaddr:$dst)>;
1427 // 64-bits atomic loads and stores
1428 def : Pat<(atomic_load_64 ixaddr:$src), (LD memrix:$src)>;
1429 def : Pat<(atomic_load_64 xaddr:$src), (LDX memrr:$src)>;
1431 def : Pat<(atomic_store_64 ixaddr:$ptr, i64:$val), (STD g8rc:$val, memrix:$ptr)>;
1432 def : Pat<(atomic_store_64 xaddr:$ptr, i64:$val), (STDX g8rc:$val, memrr:$ptr)>;
1434 let Predicates = [IsISA3_0] in {
1436 class X_L1_RA5_RB5<bits<6> opcode, bits<10> xo, string opc, RegisterOperand ty,
1437 InstrItinClass itin, list<dag> pattern>
1438 : X_L1_RS5_RS5<opcode, xo, (outs), (ins ty:$rA, ty:$rB, u1imm:$L),
1439 !strconcat(opc, " $rA, $rB, $L"), itin, pattern>;
1441 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
1442 def CP_COPY8 : X_L1_RA5_RB5<31, 774, "copy" , g8rc, IIC_LdStCOPY, []>;
1443 def CP_PASTE8 : X_L1_RA5_RB5<31, 902, "paste" , g8rc, IIC_LdStPASTE, []>;
1444 def CP_PASTE8o : X_L1_RA5_RB5<31, 902, "paste.", g8rc, IIC_LdStPASTE, []>,isDOT;
1447 // SLB Invalidate Entry Global
1448 def SLBIEG : XForm_26<31, 466, (outs), (ins gprc:$RS, gprc:$RB),
1449 "slbieg $RS, $RB", IIC_SprSLBIEG, []>;
1451 def SLBSYNC : XForm_0<31, 338, (outs), (ins), "slbsync", IIC_SprSLBSYNC, []>;