1 //===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the PowerPC 64-bit instructions. These patterns are used
11 // both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
18 def s16imm64 : Operand<i64> {
19 let PrintMethod = "printS16ImmOperand";
20 let EncoderMethod = "getImm16Encoding";
21 let ParserMatchClass = PPCS16ImmAsmOperand;
23 def u16imm64 : Operand<i64> {
24 let PrintMethod = "printU16ImmOperand";
25 let EncoderMethod = "getImm16Encoding";
26 let ParserMatchClass = PPCU16ImmAsmOperand;
28 def s17imm64 : Operand<i64> {
29 // This operand type is used for addis/lis to allow the assembler parser
30 // to accept immediates in the range -65536..65535 for compatibility with
31 // the GNU assembler. The operand is treated as 16-bit otherwise.
32 let PrintMethod = "printS16ImmOperand";
33 let EncoderMethod = "getImm16Encoding";
34 let ParserMatchClass = PPCS17ImmAsmOperand;
36 def tocentry : Operand<iPTR> {
37 let MIOperandInfo = (ops i64imm:$imm);
39 def tlsreg : Operand<i64> {
40 let EncoderMethod = "getTLSRegEncoding";
41 let ParserMatchClass = PPCTLSRegOperand;
43 def tlsgd : Operand<i64> {}
44 def tlscall : Operand<i64> {
45 let PrintMethod = "printTLSCall";
46 let MIOperandInfo = (ops calltarget:$func, tlsgd:$sym);
47 let EncoderMethod = "getTLSCallEncoding";
50 //===----------------------------------------------------------------------===//
51 // 64-bit transformation functions.
54 def SHL64 : SDNodeXForm<imm, [{
55 // Transformation function: 63 - imm
56 return getI32Imm(63 - N->getZExtValue());
59 def SRL64 : SDNodeXForm<imm, [{
60 // Transformation function: 64 - imm
61 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue()) : getI32Imm(0);
64 def HI32_48 : SDNodeXForm<imm, [{
65 // Transformation function: shift the immediate value down into the low bits.
66 return getI32Imm((unsigned short)(N->getZExtValue() >> 32));
69 def HI48_64 : SDNodeXForm<imm, [{
70 // Transformation function: shift the immediate value down into the low bits.
71 return getI32Imm((unsigned short)(N->getZExtValue() >> 48));
75 //===----------------------------------------------------------------------===//
79 let Interpretation64Bit = 1 in {
80 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
81 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR8] in {
82 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
83 Requires<[In64BitMode]>;
85 let isCodeGenOnly = 1 in
86 def BCCTR8 : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond),
87 "b${cond:cc}ctr${cond:pm} ${cond:reg}", BrB, []>,
88 Requires<[In64BitMode]>;
93 def MovePCtoLR8 : Pseudo<(outs), (ins), "#MovePCtoLR8", []>,
96 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
97 let Defs = [CTR8], Uses = [CTR8] in {
98 def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
100 def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
104 let isReturn = 1, Defs = [CTR8], Uses = [CTR8, LR8, RM] in {
105 def BDZLR8 : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
107 def BDNZLR8 : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
114 let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in {
115 // Convenient aliases for call instructions
117 def BL8 : IForm<18, 0, 1, (outs), (ins calltarget:$func),
118 "bl $func", BrB, []>; // See Pat patterns below.
120 def BL8_TLS : IForm<18, 0, 1, (outs), (ins tlscall:$func),
121 "bl $func", BrB, []>;
123 def BLA8 : IForm<18, 1, 1, (outs), (ins abscalltarget:$func),
124 "bla $func", BrB, [(PPCcall (i64 imm:$func))]>;
126 let Uses = [RM], isCodeGenOnly = 1 in {
127 def BL8_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24,
128 (outs), (ins calltarget:$func),
129 "bl $func\n\tnop", BrB, []>;
131 def BL8_NOP_TLS : IForm_and_DForm_4_zero<18, 0, 1, 24,
132 (outs), (ins tlscall:$func),
133 "bl $func\n\tnop", BrB, []>;
135 def BLA8_NOP : IForm_and_DForm_4_zero<18, 1, 1, 24,
136 (outs), (ins abscalltarget:$func),
137 "bla $func\n\tnop", BrB,
138 [(PPCcall_nop (i64 imm:$func))]>;
140 let Uses = [CTR8, RM] in {
141 def BCTRL8 : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
142 "bctrl", BrB, [(PPCbctrl)]>,
143 Requires<[In64BitMode]>;
145 let isCodeGenOnly = 1 in
146 def BCCTRL8 : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond),
147 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", BrB, []>,
148 Requires<[In64BitMode]>;
151 } // Interpretation64Bit
154 def : Pat<(PPCcall (i64 tglobaladdr:$dst)),
155 (BL8 tglobaladdr:$dst)>;
156 def : Pat<(PPCcall_nop (i64 tglobaladdr:$dst)),
157 (BL8_NOP tglobaladdr:$dst)>;
159 def : Pat<(PPCcall (i64 texternalsym:$dst)),
160 (BL8 texternalsym:$dst)>;
161 def : Pat<(PPCcall_nop (i64 texternalsym:$dst)),
162 (BL8_NOP texternalsym:$dst)>;
165 let usesCustomInserter = 1 in {
166 let Defs = [CR0] in {
167 def ATOMIC_LOAD_ADD_I64 : Pseudo<
168 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_ADD_I64",
169 [(set i64:$dst, (atomic_load_add_64 xoaddr:$ptr, i64:$incr))]>;
170 def ATOMIC_LOAD_SUB_I64 : Pseudo<
171 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_SUB_I64",
172 [(set i64:$dst, (atomic_load_sub_64 xoaddr:$ptr, i64:$incr))]>;
173 def ATOMIC_LOAD_OR_I64 : Pseudo<
174 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_OR_I64",
175 [(set i64:$dst, (atomic_load_or_64 xoaddr:$ptr, i64:$incr))]>;
176 def ATOMIC_LOAD_XOR_I64 : Pseudo<
177 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_XOR_I64",
178 [(set i64:$dst, (atomic_load_xor_64 xoaddr:$ptr, i64:$incr))]>;
179 def ATOMIC_LOAD_AND_I64 : Pseudo<
180 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_AND_i64",
181 [(set i64:$dst, (atomic_load_and_64 xoaddr:$ptr, i64:$incr))]>;
182 def ATOMIC_LOAD_NAND_I64 : Pseudo<
183 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_NAND_I64",
184 [(set i64:$dst, (atomic_load_nand_64 xoaddr:$ptr, i64:$incr))]>;
186 def ATOMIC_CMP_SWAP_I64 : Pseudo<
187 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$old, g8rc:$new), "#ATOMIC_CMP_SWAP_I64",
188 [(set i64:$dst, (atomic_cmp_swap_64 xoaddr:$ptr, i64:$old, i64:$new))]>;
190 def ATOMIC_SWAP_I64 : Pseudo<
191 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$new), "#ATOMIC_SWAP_I64",
192 [(set i64:$dst, (atomic_swap_64 xoaddr:$ptr, i64:$new))]>;
196 // Instructions to support atomic operations
197 def LDARX : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr),
198 "ldarx $rD, $ptr", LdStLDARX,
199 [(set i64:$rD, (PPClarx xoaddr:$ptr))]>;
202 def STDCX : XForm_1<31, 214, (outs), (ins g8rc:$rS, memrr:$dst),
203 "stdcx. $rS, $dst", LdStSTDCX,
204 [(PPCstcx i64:$rS, xoaddr:$dst)]>,
207 let Interpretation64Bit = 1 in {
208 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
209 def TCRETURNdi8 :Pseudo< (outs),
210 (ins calltarget:$dst, i32imm:$offset),
211 "#TC_RETURNd8 $dst $offset",
214 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
215 def TCRETURNai8 :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset),
216 "#TC_RETURNa8 $func $offset",
217 [(PPCtc_return (i64 imm:$func), imm:$offset)]>;
219 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
220 def TCRETURNri8 : Pseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset),
221 "#TC_RETURNr8 $dst $offset",
224 let isCodeGenOnly = 1 in {
226 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
227 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR8, RM] in
228 def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
229 Requires<[In64BitMode]>;
232 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
233 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
234 def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
239 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
240 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
241 def TAILBA8 : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst),
246 } // Interpretation64Bit
248 def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm),
249 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>;
251 def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm),
252 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>;
254 def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm),
255 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>;
258 // 64-bit CR instructions
259 let Interpretation64Bit = 1 in {
260 let neverHasSideEffects = 1 in {
261 def MTOCRF8: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins g8rc:$ST),
262 "mtocrf $FXM, $ST", BrMCRX>,
263 PPC970_DGroup_First, PPC970_Unit_CRU;
265 def MTCRF8 : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, g8rc:$rS),
266 "mtcrf $FXM, $rS", BrMCRX>,
267 PPC970_MicroCode, PPC970_Unit_CRU;
269 let hasExtraSrcRegAllocReq = 1 in // to enable post-ra anti-dep breaking.
270 def MFOCRF8: XFXForm_5a<31, 19, (outs g8rc:$rT), (ins crbitm:$FXM),
271 "mfocrf $rT, $FXM", SprMFCR>,
272 PPC970_DGroup_First, PPC970_Unit_CRU;
274 def MFCR8 : XFXForm_3<31, 19, (outs g8rc:$rT), (ins),
275 "mfcr $rT", SprMFCR>,
276 PPC970_MicroCode, PPC970_Unit_CRU;
277 } // neverHasSideEffects = 1
279 let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
281 def EH_SjLj_SetJmp64 : Pseudo<(outs gprc:$dst), (ins memr:$buf),
283 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
284 Requires<[In64BitMode]>;
285 let isTerminator = 1 in
286 def EH_SjLj_LongJmp64 : Pseudo<(outs), (ins memr:$buf),
287 "#EH_SJLJ_LONGJMP64",
288 [(PPCeh_sjlj_longjmp addr:$buf)]>,
289 Requires<[In64BitMode]>;
292 //===----------------------------------------------------------------------===//
293 // 64-bit SPR manipulation instrs.
295 let Uses = [CTR8] in {
296 def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs g8rc:$rT), (ins),
297 "mfctr $rT", SprMFSPR>,
298 PPC970_DGroup_First, PPC970_Unit_FXU;
300 let Pattern = [(PPCmtctr i64:$rS)], Defs = [CTR8] in {
301 def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS),
302 "mtctr $rS", SprMTSPR>,
303 PPC970_DGroup_First, PPC970_Unit_FXU;
305 let hasSideEffects = 1, isCodeGenOnly = 1, Defs = [CTR8] in {
306 let Pattern = [(int_ppc_mtctr i64:$rS)] in
307 def MTCTR8loop : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS),
308 "mtctr $rS", SprMTSPR>,
309 PPC970_DGroup_First, PPC970_Unit_FXU;
312 let isCodeGenOnly = 1, Pattern = [(set i64:$rT, readcyclecounter)] in
313 def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs g8rc:$rT), (ins),
314 "mfspr $rT, 268", SprMFTB>,
315 PPC970_DGroup_First, PPC970_Unit_FXU;
316 // Note that encoding mftb using mfspr is now the preferred form,
317 // and has been since at least ISA v2.03. The mftb instruction has
318 // now been phased out. Using mfspr, however, is known not to work on
321 let Defs = [X1], Uses = [X1] in
322 def DYNALLOC8 : Pseudo<(outs g8rc:$result), (ins g8rc:$negsize, memri:$fpsi),"#DYNALLOC8",
324 (PPCdynalloc i64:$negsize, iaddr:$fpsi))]>;
326 let Defs = [LR8] in {
327 def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins g8rc:$rS),
328 "mtlr $rS", SprMTSPR>,
329 PPC970_DGroup_First, PPC970_Unit_FXU;
331 let Uses = [LR8] in {
332 def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs g8rc:$rT), (ins),
333 "mflr $rT", SprMFSPR>,
334 PPC970_DGroup_First, PPC970_Unit_FXU;
336 } // Interpretation64Bit
338 //===----------------------------------------------------------------------===//
339 // Fixed point instructions.
342 let PPC970_Unit = 1 in { // FXU Operations.
343 let Interpretation64Bit = 1 in {
344 let neverHasSideEffects = 1 in {
346 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
347 def LI8 : DForm_2_r0<14, (outs g8rc:$rD), (ins s16imm64:$imm),
348 "li $rD, $imm", IntSimple,
349 [(set i64:$rD, imm64SExt16:$imm)]>;
350 def LIS8 : DForm_2_r0<15, (outs g8rc:$rD), (ins s17imm64:$imm),
351 "lis $rD, $imm", IntSimple,
352 [(set i64:$rD, imm16ShiftedSExt:$imm)]>;
356 defm NAND8: XForm_6r<31, 476, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
357 "nand", "$rA, $rS, $rB", IntSimple,
358 [(set i64:$rA, (not (and i64:$rS, i64:$rB)))]>;
359 defm AND8 : XForm_6r<31, 28, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
360 "and", "$rA, $rS, $rB", IntSimple,
361 [(set i64:$rA, (and i64:$rS, i64:$rB))]>;
362 defm ANDC8: XForm_6r<31, 60, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
363 "andc", "$rA, $rS, $rB", IntSimple,
364 [(set i64:$rA, (and i64:$rS, (not i64:$rB)))]>;
365 defm OR8 : XForm_6r<31, 444, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
366 "or", "$rA, $rS, $rB", IntSimple,
367 [(set i64:$rA, (or i64:$rS, i64:$rB))]>;
368 defm NOR8 : XForm_6r<31, 124, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
369 "nor", "$rA, $rS, $rB", IntSimple,
370 [(set i64:$rA, (not (or i64:$rS, i64:$rB)))]>;
371 defm ORC8 : XForm_6r<31, 412, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
372 "orc", "$rA, $rS, $rB", IntSimple,
373 [(set i64:$rA, (or i64:$rS, (not i64:$rB)))]>;
374 defm EQV8 : XForm_6r<31, 284, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
375 "eqv", "$rA, $rS, $rB", IntSimple,
376 [(set i64:$rA, (not (xor i64:$rS, i64:$rB)))]>;
377 defm XOR8 : XForm_6r<31, 316, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
378 "xor", "$rA, $rS, $rB", IntSimple,
379 [(set i64:$rA, (xor i64:$rS, i64:$rB))]>;
381 // Logical ops with immediate.
382 let Defs = [CR0] in {
383 def ANDIo8 : DForm_4<28, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
384 "andi. $dst, $src1, $src2", IntGeneral,
385 [(set i64:$dst, (and i64:$src1, immZExt16:$src2))]>,
387 def ANDISo8 : DForm_4<29, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
388 "andis. $dst, $src1, $src2", IntGeneral,
389 [(set i64:$dst, (and i64:$src1, imm16ShiftedZExt:$src2))]>,
392 def ORI8 : DForm_4<24, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
393 "ori $dst, $src1, $src2", IntSimple,
394 [(set i64:$dst, (or i64:$src1, immZExt16:$src2))]>;
395 def ORIS8 : DForm_4<25, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
396 "oris $dst, $src1, $src2", IntSimple,
397 [(set i64:$dst, (or i64:$src1, imm16ShiftedZExt:$src2))]>;
398 def XORI8 : DForm_4<26, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
399 "xori $dst, $src1, $src2", IntSimple,
400 [(set i64:$dst, (xor i64:$src1, immZExt16:$src2))]>;
401 def XORIS8 : DForm_4<27, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
402 "xoris $dst, $src1, $src2", IntSimple,
403 [(set i64:$dst, (xor i64:$src1, imm16ShiftedZExt:$src2))]>;
405 defm ADD8 : XOForm_1r<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
406 "add", "$rT, $rA, $rB", IntSimple,
407 [(set i64:$rT, (add i64:$rA, i64:$rB))]>;
408 // ADD8 has a special form: reg = ADD8(reg, sym@tls) for use by the
409 // initial-exec thread-local storage model.
410 def ADD8TLS : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, tlsreg:$rB),
411 "add $rT, $rA, $rB", IntSimple,
412 [(set i64:$rT, (add i64:$rA, tglobaltlsaddr:$rB))]>;
414 defm ADDC8 : XOForm_1rc<31, 10, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
415 "addc", "$rT, $rA, $rB", IntGeneral,
416 [(set i64:$rT, (addc i64:$rA, i64:$rB))]>,
417 PPC970_DGroup_Cracked;
418 let Defs = [CARRY] in
419 def ADDIC8 : DForm_2<12, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm),
420 "addic $rD, $rA, $imm", IntGeneral,
421 [(set i64:$rD, (addc i64:$rA, imm64SExt16:$imm))]>;
422 def ADDI8 : DForm_2<14, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s16imm64:$imm),
423 "addi $rD, $rA, $imm", IntSimple,
424 [(set i64:$rD, (add i64:$rA, imm64SExt16:$imm))]>;
425 def ADDIS8 : DForm_2<15, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s17imm64:$imm),
426 "addis $rD, $rA, $imm", IntSimple,
427 [(set i64:$rD, (add i64:$rA, imm16ShiftedSExt:$imm))]>;
429 let Defs = [CARRY] in {
430 def SUBFIC8: DForm_2< 8, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm),
431 "subfic $rD, $rA, $imm", IntGeneral,
432 [(set i64:$rD, (subc imm64SExt16:$imm, i64:$rA))]>;
433 defm SUBFC8 : XOForm_1r<31, 8, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
434 "subfc", "$rT, $rA, $rB", IntGeneral,
435 [(set i64:$rT, (subc i64:$rB, i64:$rA))]>,
436 PPC970_DGroup_Cracked;
438 defm SUBF8 : XOForm_1r<31, 40, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
439 "subf", "$rT, $rA, $rB", IntGeneral,
440 [(set i64:$rT, (sub i64:$rB, i64:$rA))]>;
441 defm NEG8 : XOForm_3r<31, 104, 0, (outs g8rc:$rT), (ins g8rc:$rA),
442 "neg", "$rT, $rA", IntSimple,
443 [(set i64:$rT, (ineg i64:$rA))]>;
444 let Uses = [CARRY] in {
445 defm ADDE8 : XOForm_1rc<31, 138, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
446 "adde", "$rT, $rA, $rB", IntGeneral,
447 [(set i64:$rT, (adde i64:$rA, i64:$rB))]>;
448 defm ADDME8 : XOForm_3rc<31, 234, 0, (outs g8rc:$rT), (ins g8rc:$rA),
449 "addme", "$rT, $rA", IntGeneral,
450 [(set i64:$rT, (adde i64:$rA, -1))]>;
451 defm ADDZE8 : XOForm_3rc<31, 202, 0, (outs g8rc:$rT), (ins g8rc:$rA),
452 "addze", "$rT, $rA", IntGeneral,
453 [(set i64:$rT, (adde i64:$rA, 0))]>;
454 defm SUBFE8 : XOForm_1rc<31, 136, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
455 "subfe", "$rT, $rA, $rB", IntGeneral,
456 [(set i64:$rT, (sube i64:$rB, i64:$rA))]>;
457 defm SUBFME8 : XOForm_3rc<31, 232, 0, (outs g8rc:$rT), (ins g8rc:$rA),
458 "subfme", "$rT, $rA", IntGeneral,
459 [(set i64:$rT, (sube -1, i64:$rA))]>;
460 defm SUBFZE8 : XOForm_3rc<31, 200, 0, (outs g8rc:$rT), (ins g8rc:$rA),
461 "subfze", "$rT, $rA", IntGeneral,
462 [(set i64:$rT, (sube 0, i64:$rA))]>;
466 defm MULHD : XOForm_1r<31, 73, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
467 "mulhd", "$rT, $rA, $rB", IntMulHW,
468 [(set i64:$rT, (mulhs i64:$rA, i64:$rB))]>;
469 defm MULHDU : XOForm_1r<31, 9, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
470 "mulhdu", "$rT, $rA, $rB", IntMulHWU,
471 [(set i64:$rT, (mulhu i64:$rA, i64:$rB))]>;
473 } // Interpretation64Bit
475 let isCompare = 1, neverHasSideEffects = 1 in {
476 def CMPD : XForm_16_ext<31, 0, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB),
477 "cmpd $crD, $rA, $rB", IntCompare>, isPPC64;
478 def CMPLD : XForm_16_ext<31, 32, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB),
479 "cmpld $crD, $rA, $rB", IntCompare>, isPPC64;
480 def CMPDI : DForm_5_ext<11, (outs crrc:$crD), (ins g8rc:$rA, s16imm:$imm),
481 "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64;
482 def CMPLDI : DForm_6_ext<10, (outs crrc:$dst), (ins g8rc:$src1, u16imm:$src2),
483 "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64;
486 let neverHasSideEffects = 1 in {
487 defm SLD : XForm_6r<31, 27, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB),
488 "sld", "$rA, $rS, $rB", IntRotateD,
489 [(set i64:$rA, (PPCshl i64:$rS, i32:$rB))]>, isPPC64;
490 defm SRD : XForm_6r<31, 539, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB),
491 "srd", "$rA, $rS, $rB", IntRotateD,
492 [(set i64:$rA, (PPCsrl i64:$rS, i32:$rB))]>, isPPC64;
493 defm SRAD : XForm_6rc<31, 794, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB),
494 "srad", "$rA, $rS, $rB", IntRotateD,
495 [(set i64:$rA, (PPCsra i64:$rS, i32:$rB))]>, isPPC64;
497 let Interpretation64Bit = 1 in {
498 defm EXTSB8 : XForm_11r<31, 954, (outs g8rc:$rA), (ins g8rc:$rS),
499 "extsb", "$rA, $rS", IntSimple,
500 [(set i64:$rA, (sext_inreg i64:$rS, i8))]>;
501 defm EXTSH8 : XForm_11r<31, 922, (outs g8rc:$rA), (ins g8rc:$rS),
502 "extsh", "$rA, $rS", IntSimple,
503 [(set i64:$rA, (sext_inreg i64:$rS, i16))]>;
504 } // Interpretation64Bit
507 let isCodeGenOnly = 1 in {
508 def EXTSB8_32_64 : XForm_11<31, 954, (outs g8rc:$rA), (ins gprc:$rS),
509 "extsb $rA, $rS", IntSimple, []>, isPPC64;
510 def EXTSH8_32_64 : XForm_11<31, 922, (outs g8rc:$rA), (ins gprc:$rS),
511 "extsh $rA, $rS", IntSimple, []>, isPPC64;
512 } // isCodeGenOnly for fast-isel
514 defm EXTSW : XForm_11r<31, 986, (outs g8rc:$rA), (ins g8rc:$rS),
515 "extsw", "$rA, $rS", IntSimple,
516 [(set i64:$rA, (sext_inreg i64:$rS, i32))]>, isPPC64;
517 let Interpretation64Bit = 1 in
518 defm EXTSW_32_64 : XForm_11r<31, 986, (outs g8rc:$rA), (ins gprc:$rS),
519 "extsw", "$rA, $rS", IntSimple,
520 [(set i64:$rA, (sext i32:$rS))]>, isPPC64;
522 defm SRADI : XSForm_1rc<31, 413, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH),
523 "sradi", "$rA, $rS, $SH", IntRotateDI,
524 [(set i64:$rA, (sra i64:$rS, (i32 imm:$SH)))]>, isPPC64;
525 defm CNTLZD : XForm_11r<31, 58, (outs g8rc:$rA), (ins g8rc:$rS),
526 "cntlzd", "$rA, $rS", IntGeneral,
527 [(set i64:$rA, (ctlz i64:$rS))]>;
528 def POPCNTD : XForm_11<31, 506, (outs g8rc:$rA), (ins g8rc:$rS),
529 "popcntd $rA, $rS", IntGeneral,
530 [(set i64:$rA, (ctpop i64:$rS))]>;
532 // popcntw also does a population count on the high 32 bits (storing the
533 // results in the high 32-bits of the output). We'll ignore that here (which is
534 // safe because we never separately use the high part of the 64-bit registers).
535 def POPCNTW : XForm_11<31, 378, (outs gprc:$rA), (ins gprc:$rS),
536 "popcntw $rA, $rS", IntGeneral,
537 [(set i32:$rA, (ctpop i32:$rS))]>;
539 defm DIVD : XOForm_1r<31, 489, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
540 "divd", "$rT, $rA, $rB", IntDivD,
541 [(set i64:$rT, (sdiv i64:$rA, i64:$rB))]>, isPPC64,
542 PPC970_DGroup_First, PPC970_DGroup_Cracked;
543 defm DIVDU : XOForm_1r<31, 457, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
544 "divdu", "$rT, $rA, $rB", IntDivD,
545 [(set i64:$rT, (udiv i64:$rA, i64:$rB))]>, isPPC64,
546 PPC970_DGroup_First, PPC970_DGroup_Cracked;
547 defm MULLD : XOForm_1r<31, 233, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
548 "mulld", "$rT, $rA, $rB", IntMulHD,
549 [(set i64:$rT, (mul i64:$rA, i64:$rB))]>, isPPC64;
550 def MULLI8 : DForm_2<7, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm),
551 "mulli $rD, $rA, $imm", IntMulLI,
552 [(set i64:$rD, (mul i64:$rA, imm64SExt16:$imm))]>;
555 let neverHasSideEffects = 1 in {
556 let isCommutable = 1 in {
557 defm RLDIMI : MDForm_1r<30, 3, (outs g8rc:$rA),
558 (ins g8rc:$rSi, g8rc:$rS, u6imm:$SH, u6imm:$MBE),
559 "rldimi", "$rA, $rS, $SH, $MBE", IntRotateDI,
560 []>, isPPC64, RegConstraint<"$rSi = $rA">,
564 // Rotate instructions.
565 defm RLDCL : MDSForm_1r<30, 8,
566 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE),
567 "rldcl", "$rA, $rS, $rB, $MBE", IntRotateD,
569 defm RLDCR : MDSForm_1r<30, 9,
570 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE),
571 "rldcr", "$rA, $rS, $rB, $MBE", IntRotateD,
573 defm RLDICL : MDForm_1r<30, 0,
574 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE),
575 "rldicl", "$rA, $rS, $SH, $MBE", IntRotateDI,
578 let isCodeGenOnly = 1 in
579 def RLDICL_32_64 : MDForm_1<30, 0,
581 (ins gprc:$rS, u6imm:$SH, u6imm:$MBE),
582 "rldicl $rA, $rS, $SH, $MBE", IntRotateDI,
585 defm RLDICR : MDForm_1r<30, 1,
586 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE),
587 "rldicr", "$rA, $rS, $SH, $MBE", IntRotateDI,
589 defm RLDIC : MDForm_1r<30, 2,
590 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE),
591 "rldic", "$rA, $rS, $SH, $MBE", IntRotateDI,
594 let Interpretation64Bit = 1 in {
595 defm RLWINM8 : MForm_2r<21, (outs g8rc:$rA),
596 (ins g8rc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
597 "rlwinm", "$rA, $rS, $SH, $MB, $ME", IntGeneral,
601 def ISEL8 : AForm_4<31, 15,
602 (outs g8rc:$rT), (ins g8rc_nox0:$rA, g8rc:$rB, crbitrc:$cond),
603 "isel $rT, $rA, $rB, $cond", IntGeneral,
605 } // Interpretation64Bit
606 } // neverHasSideEffects = 1
607 } // End FXU Operations.
610 //===----------------------------------------------------------------------===//
611 // Load/Store instructions.
615 // Sign extending loads.
616 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
617 let Interpretation64Bit = 1 in
618 def LHA8: DForm_1<42, (outs g8rc:$rD), (ins memri:$src),
619 "lha $rD, $src", LdStLHA,
620 [(set i64:$rD, (sextloadi16 iaddr:$src))]>,
621 PPC970_DGroup_Cracked;
622 def LWA : DSForm_1<58, 2, (outs g8rc:$rD), (ins memrix:$src),
623 "lwa $rD, $src", LdStLWA,
625 (aligned4sextloadi32 ixaddr:$src))]>, isPPC64,
626 PPC970_DGroup_Cracked;
627 let Interpretation64Bit = 1 in
628 def LHAX8: XForm_1<31, 343, (outs g8rc:$rD), (ins memrr:$src),
629 "lhax $rD, $src", LdStLHA,
630 [(set i64:$rD, (sextloadi16 xaddr:$src))]>,
631 PPC970_DGroup_Cracked;
632 def LWAX : XForm_1<31, 341, (outs g8rc:$rD), (ins memrr:$src),
633 "lwax $rD, $src", LdStLHA,
634 [(set i64:$rD, (sextloadi32 xaddr:$src))]>, isPPC64,
635 PPC970_DGroup_Cracked;
637 let isCodeGenOnly = 1, mayLoad = 1 in {
638 def LWA_32 : DSForm_1<58, 2, (outs gprc:$rD), (ins memrix:$src),
639 "lwa $rD, $src", LdStLWA, []>, isPPC64,
640 PPC970_DGroup_Cracked;
641 def LWAX_32 : XForm_1<31, 341, (outs gprc:$rD), (ins memrr:$src),
642 "lwax $rD, $src", LdStLHA, []>, isPPC64,
643 PPC970_DGroup_Cracked;
644 } // end fast-isel isCodeGenOnly
647 let mayLoad = 1, neverHasSideEffects = 1 in {
648 let Interpretation64Bit = 1 in
649 def LHAU8 : DForm_1<43, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
651 "lhau $rD, $addr", LdStLHAU,
652 []>, RegConstraint<"$addr.reg = $ea_result">,
653 NoEncode<"$ea_result">;
656 let Interpretation64Bit = 1 in
657 def LHAUX8 : XForm_1<31, 375, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
659 "lhaux $rD, $addr", LdStLHAU,
660 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
661 NoEncode<"$ea_result">;
662 def LWAUX : XForm_1<31, 373, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
664 "lwaux $rD, $addr", LdStLHAU,
665 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
666 NoEncode<"$ea_result">, isPPC64;
670 let Interpretation64Bit = 1 in {
671 // Zero extending loads.
672 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
673 def LBZ8 : DForm_1<34, (outs g8rc:$rD), (ins memri:$src),
674 "lbz $rD, $src", LdStLoad,
675 [(set i64:$rD, (zextloadi8 iaddr:$src))]>;
676 def LHZ8 : DForm_1<40, (outs g8rc:$rD), (ins memri:$src),
677 "lhz $rD, $src", LdStLoad,
678 [(set i64:$rD, (zextloadi16 iaddr:$src))]>;
679 def LWZ8 : DForm_1<32, (outs g8rc:$rD), (ins memri:$src),
680 "lwz $rD, $src", LdStLoad,
681 [(set i64:$rD, (zextloadi32 iaddr:$src))]>, isPPC64;
683 def LBZX8 : XForm_1<31, 87, (outs g8rc:$rD), (ins memrr:$src),
684 "lbzx $rD, $src", LdStLoad,
685 [(set i64:$rD, (zextloadi8 xaddr:$src))]>;
686 def LHZX8 : XForm_1<31, 279, (outs g8rc:$rD), (ins memrr:$src),
687 "lhzx $rD, $src", LdStLoad,
688 [(set i64:$rD, (zextloadi16 xaddr:$src))]>;
689 def LWZX8 : XForm_1<31, 23, (outs g8rc:$rD), (ins memrr:$src),
690 "lwzx $rD, $src", LdStLoad,
691 [(set i64:$rD, (zextloadi32 xaddr:$src))]>;
695 let mayLoad = 1, neverHasSideEffects = 1 in {
696 def LBZU8 : DForm_1<35, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
697 "lbzu $rD, $addr", LdStLoadUpd,
698 []>, RegConstraint<"$addr.reg = $ea_result">,
699 NoEncode<"$ea_result">;
700 def LHZU8 : DForm_1<41, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
701 "lhzu $rD, $addr", LdStLoadUpd,
702 []>, RegConstraint<"$addr.reg = $ea_result">,
703 NoEncode<"$ea_result">;
704 def LWZU8 : DForm_1<33, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
705 "lwzu $rD, $addr", LdStLoadUpd,
706 []>, RegConstraint<"$addr.reg = $ea_result">,
707 NoEncode<"$ea_result">;
709 def LBZUX8 : XForm_1<31, 119, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
711 "lbzux $rD, $addr", LdStLoadUpd,
712 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
713 NoEncode<"$ea_result">;
714 def LHZUX8 : XForm_1<31, 311, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
716 "lhzux $rD, $addr", LdStLoadUpd,
717 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
718 NoEncode<"$ea_result">;
719 def LWZUX8 : XForm_1<31, 55, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
721 "lwzux $rD, $addr", LdStLoadUpd,
722 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
723 NoEncode<"$ea_result">;
726 } // Interpretation64Bit
729 // Full 8-byte loads.
730 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
731 def LD : DSForm_1<58, 0, (outs g8rc:$rD), (ins memrix:$src),
732 "ld $rD, $src", LdStLD,
733 [(set i64:$rD, (aligned4load ixaddr:$src))]>, isPPC64;
734 // The following three definitions are selected for small code model only.
735 // Otherwise, we need to create two instructions to form a 32-bit offset,
736 // so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select().
737 def LDtoc: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
740 (PPCtoc_entry tglobaladdr:$disp, i64:$reg))]>, isPPC64;
741 def LDtocJTI: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
744 (PPCtoc_entry tjumptable:$disp, i64:$reg))]>, isPPC64;
745 def LDtocCPT: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
748 (PPCtoc_entry tconstpool:$disp, i64:$reg))]>, isPPC64;
750 let hasSideEffects = 1, isCodeGenOnly = 1 in {
751 let RST = 2, DS = 2 in
752 def LDinto_toc: DSForm_1a<58, 0, (outs), (ins g8rc:$reg),
753 "ld 2, 8($reg)", LdStLD,
754 [(PPCload_toc i64:$reg)]>, isPPC64;
756 let RST = 2, DS = 10, RA = 1 in
757 def LDtoc_restore : DSForm_1a<58, 0, (outs), (ins),
758 "ld 2, 40(1)", LdStLD,
759 [(PPCtoc_restore)]>, isPPC64;
761 def LDX : XForm_1<31, 21, (outs g8rc:$rD), (ins memrr:$src),
762 "ldx $rD, $src", LdStLD,
763 [(set i64:$rD, (load xaddr:$src))]>, isPPC64;
764 def LDBRX : XForm_1<31, 532, (outs g8rc:$rD), (ins memrr:$src),
765 "ldbrx $rD, $src", LdStLoad,
766 [(set i64:$rD, (PPClbrx xoaddr:$src, i64))]>, isPPC64;
768 let mayLoad = 1, neverHasSideEffects = 1 in {
769 def LDU : DSForm_1<58, 1, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memrix:$addr),
770 "ldu $rD, $addr", LdStLDU,
771 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64,
772 NoEncode<"$ea_result">;
774 def LDUX : XForm_1<31, 53, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
776 "ldux $rD, $addr", LdStLDU,
777 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
778 NoEncode<"$ea_result">, isPPC64;
782 def : Pat<(PPCload ixaddr:$src),
784 def : Pat<(PPCload xaddr:$src),
787 // Support for medium and large code model.
788 def ADDIStocHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp),
791 (PPCaddisTocHA i64:$reg, tglobaladdr:$disp))]>,
793 def LDtocL: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc_nox0:$reg),
796 (PPCldTocL tglobaladdr:$disp, i64:$reg))]>, isPPC64;
797 def ADDItocL: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp),
800 (PPCaddiTocL i64:$reg, tglobaladdr:$disp))]>, isPPC64;
802 // Support for thread-local storage.
803 def ADDISgotTprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
806 (PPCaddisGotTprelHA i64:$reg,
807 tglobaltlsaddr:$disp))]>,
809 def LDgotTprelL: Pseudo<(outs g8rc:$rD), (ins s16imm64:$disp, g8rc_nox0:$reg),
812 (PPCldGotTprelL tglobaltlsaddr:$disp, i64:$reg))]>,
814 def : Pat<(PPCaddTls i64:$in, tglobaltlsaddr:$g),
815 (ADD8TLS $in, tglobaltlsaddr:$g)>;
816 def ADDIStlsgdHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
819 (PPCaddisTlsgdHA i64:$reg, tglobaltlsaddr:$disp))]>,
821 def ADDItlsgdL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
824 (PPCaddiTlsgdL i64:$reg, tglobaltlsaddr:$disp))]>,
826 def GETtlsADDR : Pseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym),
829 (PPCgetTlsAddr i64:$reg, tglobaltlsaddr:$sym))]>,
831 def ADDIStlsldHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
834 (PPCaddisTlsldHA i64:$reg, tglobaltlsaddr:$disp))]>,
836 def ADDItlsldL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
839 (PPCaddiTlsldL i64:$reg, tglobaltlsaddr:$disp))]>,
841 def GETtlsldADDR : Pseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym),
844 (PPCgetTlsldAddr i64:$reg, tglobaltlsaddr:$sym))]>,
846 def ADDISdtprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
849 (PPCaddisDtprelHA i64:$reg,
850 tglobaltlsaddr:$disp))]>,
852 def ADDIdtprelL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
855 (PPCaddiDtprelL i64:$reg, tglobaltlsaddr:$disp))]>,
858 let PPC970_Unit = 2 in {
859 let Interpretation64Bit = 1 in {
860 // Truncating stores.
861 def STB8 : DForm_1<38, (outs), (ins g8rc:$rS, memri:$src),
862 "stb $rS, $src", LdStStore,
863 [(truncstorei8 i64:$rS, iaddr:$src)]>;
864 def STH8 : DForm_1<44, (outs), (ins g8rc:$rS, memri:$src),
865 "sth $rS, $src", LdStStore,
866 [(truncstorei16 i64:$rS, iaddr:$src)]>;
867 def STW8 : DForm_1<36, (outs), (ins g8rc:$rS, memri:$src),
868 "stw $rS, $src", LdStStore,
869 [(truncstorei32 i64:$rS, iaddr:$src)]>;
870 def STBX8 : XForm_8<31, 215, (outs), (ins g8rc:$rS, memrr:$dst),
871 "stbx $rS, $dst", LdStStore,
872 [(truncstorei8 i64:$rS, xaddr:$dst)]>,
873 PPC970_DGroup_Cracked;
874 def STHX8 : XForm_8<31, 407, (outs), (ins g8rc:$rS, memrr:$dst),
875 "sthx $rS, $dst", LdStStore,
876 [(truncstorei16 i64:$rS, xaddr:$dst)]>,
877 PPC970_DGroup_Cracked;
878 def STWX8 : XForm_8<31, 151, (outs), (ins g8rc:$rS, memrr:$dst),
879 "stwx $rS, $dst", LdStStore,
880 [(truncstorei32 i64:$rS, xaddr:$dst)]>,
881 PPC970_DGroup_Cracked;
882 } // Interpretation64Bit
884 // Normal 8-byte stores.
885 def STD : DSForm_1<62, 0, (outs), (ins g8rc:$rS, memrix:$dst),
886 "std $rS, $dst", LdStSTD,
887 [(aligned4store i64:$rS, ixaddr:$dst)]>, isPPC64;
888 def STDX : XForm_8<31, 149, (outs), (ins g8rc:$rS, memrr:$dst),
889 "stdx $rS, $dst", LdStSTD,
890 [(store i64:$rS, xaddr:$dst)]>, isPPC64,
891 PPC970_DGroup_Cracked;
892 def STDBRX: XForm_8<31, 660, (outs), (ins g8rc:$rS, memrr:$dst),
893 "stdbrx $rS, $dst", LdStStore,
894 [(PPCstbrx i64:$rS, xoaddr:$dst, i64)]>, isPPC64,
895 PPC970_DGroup_Cracked;
898 // Stores with Update (pre-inc).
899 let PPC970_Unit = 2, mayStore = 1 in {
900 let Interpretation64Bit = 1 in {
901 def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst),
902 "stbu $rS, $dst", LdStStoreUpd, []>,
903 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
904 def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst),
905 "sthu $rS, $dst", LdStStoreUpd, []>,
906 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
907 def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst),
908 "stwu $rS, $dst", LdStStoreUpd, []>,
909 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
910 def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrix:$dst),
911 "stdu $rS, $dst", LdStSTDU, []>,
912 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">,
915 def STBUX8: XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
916 "stbux $rS, $dst", LdStStoreUpd, []>,
917 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
918 PPC970_DGroup_Cracked;
919 def STHUX8: XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
920 "sthux $rS, $dst", LdStStoreUpd, []>,
921 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
922 PPC970_DGroup_Cracked;
923 def STWUX8: XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
924 "stwux $rS, $dst", LdStStoreUpd, []>,
925 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
926 PPC970_DGroup_Cracked;
927 } // Interpretation64Bit
929 def STDUX : XForm_8<31, 181, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
930 "stdux $rS, $dst", LdStSTDU, []>,
931 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
932 PPC970_DGroup_Cracked, isPPC64;
935 // Patterns to match the pre-inc stores. We can't put the patterns on
936 // the instruction definitions directly as ISel wants the address base
937 // and offset to be separate operands, not a single complex operand.
938 def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
939 (STBU8 $rS, iaddroff:$ptroff, $ptrreg)>;
940 def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
941 (STHU8 $rS, iaddroff:$ptroff, $ptrreg)>;
942 def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
943 (STWU8 $rS, iaddroff:$ptroff, $ptrreg)>;
944 def : Pat<(aligned4pre_store i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
945 (STDU $rS, iaddroff:$ptroff, $ptrreg)>;
947 def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
948 (STBUX8 $rS, $ptrreg, $ptroff)>;
949 def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
950 (STHUX8 $rS, $ptrreg, $ptroff)>;
951 def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
952 (STWUX8 $rS, $ptrreg, $ptroff)>;
953 def : Pat<(pre_store i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
954 (STDUX $rS, $ptrreg, $ptroff)>;
957 //===----------------------------------------------------------------------===//
958 // Floating point instructions.
962 let PPC970_Unit = 3, neverHasSideEffects = 1,
963 Uses = [RM] in { // FPU Operations.
964 defm FCFID : XForm_26r<63, 846, (outs f8rc:$frD), (ins f8rc:$frB),
965 "fcfid", "$frD, $frB", FPGeneral,
966 [(set f64:$frD, (PPCfcfid f64:$frB))]>, isPPC64;
967 defm FCTID : XForm_26r<63, 814, (outs f8rc:$frD), (ins f8rc:$frB),
968 "fctid", "$frD, $frB", FPGeneral,
970 defm FCTIDZ : XForm_26r<63, 815, (outs f8rc:$frD), (ins f8rc:$frB),
971 "fctidz", "$frD, $frB", FPGeneral,
972 [(set f64:$frD, (PPCfctidz f64:$frB))]>, isPPC64;
974 defm FCFIDU : XForm_26r<63, 974, (outs f8rc:$frD), (ins f8rc:$frB),
975 "fcfidu", "$frD, $frB", FPGeneral,
976 [(set f64:$frD, (PPCfcfidu f64:$frB))]>, isPPC64;
977 defm FCFIDS : XForm_26r<59, 846, (outs f4rc:$frD), (ins f8rc:$frB),
978 "fcfids", "$frD, $frB", FPGeneral,
979 [(set f32:$frD, (PPCfcfids f64:$frB))]>, isPPC64;
980 defm FCFIDUS : XForm_26r<59, 974, (outs f4rc:$frD), (ins f8rc:$frB),
981 "fcfidus", "$frD, $frB", FPGeneral,
982 [(set f32:$frD, (PPCfcfidus f64:$frB))]>, isPPC64;
983 defm FCTIDUZ : XForm_26r<63, 943, (outs f8rc:$frD), (ins f8rc:$frB),
984 "fctiduz", "$frD, $frB", FPGeneral,
985 [(set f64:$frD, (PPCfctiduz f64:$frB))]>, isPPC64;
986 defm FCTIWUZ : XForm_26r<63, 143, (outs f8rc:$frD), (ins f8rc:$frB),
987 "fctiwuz", "$frD, $frB", FPGeneral,
988 [(set f64:$frD, (PPCfctiwuz f64:$frB))]>, isPPC64;
992 //===----------------------------------------------------------------------===//
993 // Instruction Patterns
996 // Extensions and truncates to/from 32-bit regs.
997 def : Pat<(i64 (zext i32:$in)),
998 (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32),
1000 def : Pat<(i64 (anyext i32:$in)),
1001 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32)>;
1002 def : Pat<(i32 (trunc i64:$in)),
1003 (EXTRACT_SUBREG $in, sub_32)>;
1005 // Extending loads with i64 targets.
1006 def : Pat<(zextloadi1 iaddr:$src),
1008 def : Pat<(zextloadi1 xaddr:$src),
1009 (LBZX8 xaddr:$src)>;
1010 def : Pat<(extloadi1 iaddr:$src),
1012 def : Pat<(extloadi1 xaddr:$src),
1013 (LBZX8 xaddr:$src)>;
1014 def : Pat<(extloadi8 iaddr:$src),
1016 def : Pat<(extloadi8 xaddr:$src),
1017 (LBZX8 xaddr:$src)>;
1018 def : Pat<(extloadi16 iaddr:$src),
1020 def : Pat<(extloadi16 xaddr:$src),
1021 (LHZX8 xaddr:$src)>;
1022 def : Pat<(extloadi32 iaddr:$src),
1024 def : Pat<(extloadi32 xaddr:$src),
1025 (LWZX8 xaddr:$src)>;
1027 // Standard shifts. These are represented separately from the real shifts above
1028 // so that we can distinguish between shifts that allow 6-bit and 7-bit shift
1030 def : Pat<(sra i64:$rS, i32:$rB),
1032 def : Pat<(srl i64:$rS, i32:$rB),
1034 def : Pat<(shl i64:$rS, i32:$rB),
1038 def : Pat<(shl i64:$in, (i32 imm:$imm)),
1039 (RLDICR $in, imm:$imm, (SHL64 imm:$imm))>;
1040 def : Pat<(srl i64:$in, (i32 imm:$imm)),
1041 (RLDICL $in, (SRL64 imm:$imm), imm:$imm)>;
1044 def : Pat<(rotl i64:$in, i32:$sh),
1045 (RLDCL $in, $sh, 0)>;
1046 def : Pat<(rotl i64:$in, (i32 imm:$imm)),
1047 (RLDICL $in, imm:$imm, 0)>;
1049 // Hi and Lo for Darwin Global Addresses.
1050 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>;
1051 def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>;
1052 def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>;
1053 def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>;
1054 def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>;
1055 def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>;
1056 def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>;
1057 def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>;
1058 def : Pat<(PPChi tglobaltlsaddr:$g, i64:$in),
1059 (ADDIS8 $in, tglobaltlsaddr:$g)>;
1060 def : Pat<(PPClo tglobaltlsaddr:$g, i64:$in),
1061 (ADDI8 $in, tglobaltlsaddr:$g)>;
1062 def : Pat<(add i64:$in, (PPChi tglobaladdr:$g, 0)),
1063 (ADDIS8 $in, tglobaladdr:$g)>;
1064 def : Pat<(add i64:$in, (PPChi tconstpool:$g, 0)),
1065 (ADDIS8 $in, tconstpool:$g)>;
1066 def : Pat<(add i64:$in, (PPChi tjumptable:$g, 0)),
1067 (ADDIS8 $in, tjumptable:$g)>;
1068 def : Pat<(add i64:$in, (PPChi tblockaddress:$g, 0)),
1069 (ADDIS8 $in, tblockaddress:$g)>;
1071 // Patterns to match r+r indexed loads and stores for
1072 // addresses without at least 4-byte alignment.
1073 def : Pat<(i64 (unaligned4sextloadi32 xoaddr:$src)),
1074 (LWAX xoaddr:$src)>;
1075 def : Pat<(i64 (unaligned4load xoaddr:$src)),
1077 def : Pat<(unaligned4store i64:$rS, xoaddr:$dst),
1078 (STDX $rS, xoaddr:$dst)>;