1 //===-- PPCInstrAltivec.td - The PowerPC Altivec Extension -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Altivec extension to the PowerPC instruction set.
12 //===----------------------------------------------------------------------===//
14 // *********************************** NOTE ***********************************
15 // ** For POWER8 Little Endian, the VSX swap optimization relies on knowing **
16 // ** which VMX and VSX instructions are lane-sensitive and which are not. **
17 // ** A lane-sensitive instruction relies, implicitly or explicitly, on **
18 // ** whether lanes are numbered from left to right. An instruction like **
19 // ** VADDFP is not lane-sensitive, because each lane of the result vector **
20 // ** relies only on the corresponding lane of the source vectors. However, **
21 // ** an instruction like VMULESB is lane-sensitive, because "even" and **
22 // ** "odd" lanes are different for big-endian and little-endian numbering. **
24 // ** When adding new VMX and VSX instructions, please consider whether they **
25 // ** are lane-sensitive. If so, they must be added to a switch statement **
26 // ** in PPCVSXSwapRemoval::gatherVectorInstructions(). **
27 // ****************************************************************************
30 //===----------------------------------------------------------------------===//
31 // Altivec transformation functions and pattern fragments.
34 // Since we canonicalize buildvectors to v16i8, all vnots "-1" operands will be
36 def vnot_ppc : PatFrag<(ops node:$in),
37 (xor node:$in, (bitconvert (v16i8 immAllOnesV)))>;
39 def vpkuhum_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
40 (vector_shuffle node:$lhs, node:$rhs), [{
41 return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), 0, *CurDAG);
43 def vpkuwum_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
44 (vector_shuffle node:$lhs, node:$rhs), [{
45 return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), 0, *CurDAG);
47 def vpkudum_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
48 (vector_shuffle node:$lhs, node:$rhs), [{
49 return PPC::isVPKUDUMShuffleMask(cast<ShuffleVectorSDNode>(N), 0, *CurDAG);
51 def vpkuhum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
52 (vector_shuffle node:$lhs, node:$rhs), [{
53 return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), 1, *CurDAG);
55 def vpkuwum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
56 (vector_shuffle node:$lhs, node:$rhs), [{
57 return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), 1, *CurDAG);
59 def vpkudum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
60 (vector_shuffle node:$lhs, node:$rhs), [{
61 return PPC::isVPKUDUMShuffleMask(cast<ShuffleVectorSDNode>(N), 1, *CurDAG);
64 // These fragments are provided for little-endian, where the inputs must be
65 // swapped for correct semantics.
66 def vpkuhum_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
67 (vector_shuffle node:$lhs, node:$rhs), [{
68 return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), 2, *CurDAG);
70 def vpkuwum_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
71 (vector_shuffle node:$lhs, node:$rhs), [{
72 return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), 2, *CurDAG);
74 def vpkudum_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
75 (vector_shuffle node:$lhs, node:$rhs), [{
76 return PPC::isVPKUDUMShuffleMask(cast<ShuffleVectorSDNode>(N), 2, *CurDAG);
79 def vmrglb_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
80 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
81 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 0, *CurDAG);
83 def vmrglh_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
84 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
85 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 0, *CurDAG);
87 def vmrglw_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
88 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
89 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 0, *CurDAG);
91 def vmrghb_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
92 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
93 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 0, *CurDAG);
95 def vmrghh_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
96 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
97 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 0, *CurDAG);
99 def vmrghw_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
100 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
101 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 0, *CurDAG);
105 def vmrglb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
106 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
107 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 1, *CurDAG);
109 def vmrglh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
110 (vector_shuffle node:$lhs, node:$rhs), [{
111 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 1, *CurDAG);
113 def vmrglw_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
114 (vector_shuffle node:$lhs, node:$rhs), [{
115 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 1, *CurDAG);
117 def vmrghb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
118 (vector_shuffle node:$lhs, node:$rhs), [{
119 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 1, *CurDAG);
121 def vmrghh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
122 (vector_shuffle node:$lhs, node:$rhs), [{
123 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 1, *CurDAG);
125 def vmrghw_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
126 (vector_shuffle node:$lhs, node:$rhs), [{
127 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 1, *CurDAG);
131 // These fragments are provided for little-endian, where the inputs must be
132 // swapped for correct semantics.
133 def vmrglb_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
134 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
135 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 2, *CurDAG);
137 def vmrglh_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
138 (vector_shuffle node:$lhs, node:$rhs), [{
139 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 2, *CurDAG);
141 def vmrglw_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
142 (vector_shuffle node:$lhs, node:$rhs), [{
143 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 2, *CurDAG);
145 def vmrghb_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
146 (vector_shuffle node:$lhs, node:$rhs), [{
147 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 2, *CurDAG);
149 def vmrghh_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
150 (vector_shuffle node:$lhs, node:$rhs), [{
151 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 2, *CurDAG);
153 def vmrghw_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
154 (vector_shuffle node:$lhs, node:$rhs), [{
155 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 2, *CurDAG);
159 def vmrgew_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
160 (vector_shuffle node:$lhs, node:$rhs), [{
161 return PPC::isVMRGEOShuffleMask(cast<ShuffleVectorSDNode>(N), true, 0, *CurDAG);
163 def vmrgow_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
164 (vector_shuffle node:$lhs, node:$rhs), [{
165 return PPC::isVMRGEOShuffleMask(cast<ShuffleVectorSDNode>(N), false, 0, *CurDAG);
167 def vmrgew_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
168 (vector_shuffle node:$lhs, node:$rhs), [{
169 return PPC::isVMRGEOShuffleMask(cast<ShuffleVectorSDNode>(N), true, 1, *CurDAG);
171 def vmrgow_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
172 (vector_shuffle node:$lhs, node:$rhs), [{
173 return PPC::isVMRGEOShuffleMask(cast<ShuffleVectorSDNode>(N), false, 1, *CurDAG);
175 def vmrgew_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
176 (vector_shuffle node:$lhs, node:$rhs), [{
177 return PPC::isVMRGEOShuffleMask(cast<ShuffleVectorSDNode>(N), true, 2, *CurDAG);
179 def vmrgow_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
180 (vector_shuffle node:$lhs, node:$rhs), [{
181 return PPC::isVMRGEOShuffleMask(cast<ShuffleVectorSDNode>(N), false, 2, *CurDAG);
186 def VSLDOI_get_imm : SDNodeXForm<vector_shuffle, [{
187 return getI32Imm(PPC::isVSLDOIShuffleMask(N, 0, *CurDAG), SDLoc(N));
189 def vsldoi_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
190 (vector_shuffle node:$lhs, node:$rhs), [{
191 return PPC::isVSLDOIShuffleMask(N, 0, *CurDAG) != -1;
195 /// VSLDOI_unary* - These are used to match vsldoi(X,X), which is turned into
196 /// vector_shuffle(X,undef,mask) by the dag combiner.
197 def VSLDOI_unary_get_imm : SDNodeXForm<vector_shuffle, [{
198 return getI32Imm(PPC::isVSLDOIShuffleMask(N, 1, *CurDAG), SDLoc(N));
200 def vsldoi_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
201 (vector_shuffle node:$lhs, node:$rhs), [{
202 return PPC::isVSLDOIShuffleMask(N, 1, *CurDAG) != -1;
203 }], VSLDOI_unary_get_imm>;
206 /// VSLDOI_swapped* - These fragments are provided for little-endian, where
207 /// the inputs must be swapped for correct semantics.
208 def VSLDOI_swapped_get_imm : SDNodeXForm<vector_shuffle, [{
209 return getI32Imm(PPC::isVSLDOIShuffleMask(N, 2, *CurDAG), SDLoc(N));
211 def vsldoi_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
212 (vector_shuffle node:$lhs, node:$rhs), [{
213 return PPC::isVSLDOIShuffleMask(N, 2, *CurDAG) != -1;
217 // VSPLT*_get_imm xform function: convert vector_shuffle mask to VSPLT* imm.
218 def VSPLTB_get_imm : SDNodeXForm<vector_shuffle, [{
219 return getI32Imm(PPC::getVSPLTImmediate(N, 1, *CurDAG), SDLoc(N));
221 def vspltb_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
222 (vector_shuffle node:$lhs, node:$rhs), [{
223 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 1);
225 def VSPLTH_get_imm : SDNodeXForm<vector_shuffle, [{
226 return getI32Imm(PPC::getVSPLTImmediate(N, 2, *CurDAG), SDLoc(N));
228 def vsplth_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
229 (vector_shuffle node:$lhs, node:$rhs), [{
230 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 2);
232 def VSPLTW_get_imm : SDNodeXForm<vector_shuffle, [{
233 return getI32Imm(PPC::getVSPLTImmediate(N, 4, *CurDAG), SDLoc(N));
235 def vspltw_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
236 (vector_shuffle node:$lhs, node:$rhs), [{
237 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 4);
241 // VSPLTISB_get_imm xform function: convert build_vector to VSPLTISB imm.
242 def VSPLTISB_get_imm : SDNodeXForm<build_vector, [{
243 return PPC::get_VSPLTI_elt(N, 1, *CurDAG);
245 def vecspltisb : PatLeaf<(build_vector), [{
246 return PPC::get_VSPLTI_elt(N, 1, *CurDAG).getNode() != nullptr;
247 }], VSPLTISB_get_imm>;
249 // VSPLTISH_get_imm xform function: convert build_vector to VSPLTISH imm.
250 def VSPLTISH_get_imm : SDNodeXForm<build_vector, [{
251 return PPC::get_VSPLTI_elt(N, 2, *CurDAG);
253 def vecspltish : PatLeaf<(build_vector), [{
254 return PPC::get_VSPLTI_elt(N, 2, *CurDAG).getNode() != nullptr;
255 }], VSPLTISH_get_imm>;
257 // VSPLTISW_get_imm xform function: convert build_vector to VSPLTISW imm.
258 def VSPLTISW_get_imm : SDNodeXForm<build_vector, [{
259 return PPC::get_VSPLTI_elt(N, 4, *CurDAG);
261 def vecspltisw : PatLeaf<(build_vector), [{
262 return PPC::get_VSPLTI_elt(N, 4, *CurDAG).getNode() != nullptr;
263 }], VSPLTISW_get_imm>;
265 //===----------------------------------------------------------------------===//
266 // Helpers for defining instructions that directly correspond to intrinsics.
268 // VA1a_Int_Ty - A VAForm_1a intrinsic definition of specific type.
269 class VA1a_Int_Ty<bits<6> xo, string opc, Intrinsic IntID, ValueType Ty>
270 : VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC),
271 !strconcat(opc, " $vD, $vA, $vB, $vC"), IIC_VecFP,
272 [(set Ty:$vD, (IntID Ty:$vA, Ty:$vB, Ty:$vC))]>;
274 // VA1a_Int_Ty2 - A VAForm_1a intrinsic definition where the type of the
275 // inputs doesn't match the type of the output.
276 class VA1a_Int_Ty2<bits<6> xo, string opc, Intrinsic IntID, ValueType OutTy,
278 : VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC),
279 !strconcat(opc, " $vD, $vA, $vB, $vC"), IIC_VecFP,
280 [(set OutTy:$vD, (IntID InTy:$vA, InTy:$vB, InTy:$vC))]>;
282 // VA1a_Int_Ty3 - A VAForm_1a intrinsic definition where there are two
283 // input types and an output type.
284 class VA1a_Int_Ty3<bits<6> xo, string opc, Intrinsic IntID, ValueType OutTy,
285 ValueType In1Ty, ValueType In2Ty>
286 : VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC),
287 !strconcat(opc, " $vD, $vA, $vB, $vC"), IIC_VecFP,
289 (IntID In1Ty:$vA, In1Ty:$vB, In2Ty:$vC))]>;
291 // VX1_Int_Ty - A VXForm_1 intrinsic definition of specific type.
292 class VX1_Int_Ty<bits<11> xo, string opc, Intrinsic IntID, ValueType Ty>
293 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
294 !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP,
295 [(set Ty:$vD, (IntID Ty:$vA, Ty:$vB))]>;
297 // VX1_Int_Ty2 - A VXForm_1 intrinsic definition where the type of the
298 // inputs doesn't match the type of the output.
299 class VX1_Int_Ty2<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy,
301 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
302 !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP,
303 [(set OutTy:$vD, (IntID InTy:$vA, InTy:$vB))]>;
305 // VX1_Int_Ty3 - A VXForm_1 intrinsic definition where there are two
306 // input types and an output type.
307 class VX1_Int_Ty3<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy,
308 ValueType In1Ty, ValueType In2Ty>
309 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
310 !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP,
311 [(set OutTy:$vD, (IntID In1Ty:$vA, In2Ty:$vB))]>;
313 // VX2_Int_SP - A VXForm_2 intrinsic definition of vector single-precision type.
314 class VX2_Int_SP<bits<11> xo, string opc, Intrinsic IntID>
315 : VXForm_2<xo, (outs vrrc:$vD), (ins vrrc:$vB),
316 !strconcat(opc, " $vD, $vB"), IIC_VecFP,
317 [(set v4f32:$vD, (IntID v4f32:$vB))]>;
319 // VX2_Int_Ty2 - A VXForm_2 intrinsic definition where the type of the
320 // inputs doesn't match the type of the output.
321 class VX2_Int_Ty2<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy,
323 : VXForm_2<xo, (outs vrrc:$vD), (ins vrrc:$vB),
324 !strconcat(opc, " $vD, $vB"), IIC_VecFP,
325 [(set OutTy:$vD, (IntID InTy:$vB))]>;
327 class VXBX_Int_Ty<bits<11> xo, string opc, Intrinsic IntID, ValueType Ty>
328 : VXForm_BX<xo, (outs vrrc:$vD), (ins vrrc:$vA),
329 !strconcat(opc, " $vD, $vA"), IIC_VecFP,
330 [(set Ty:$vD, (IntID Ty:$vA))]>;
332 class VXCR_Int_Ty<bits<11> xo, string opc, Intrinsic IntID, ValueType Ty>
333 : VXForm_CR<xo, (outs vrrc:$vD), (ins vrrc:$vA, u1imm:$ST, u4imm:$SIX),
334 !strconcat(opc, " $vD, $vA, $ST, $SIX"), IIC_VecFP,
335 [(set Ty:$vD, (IntID Ty:$vA, imm:$ST, imm:$SIX))]>;
337 //===----------------------------------------------------------------------===//
338 // Instruction Definitions.
340 def HasAltivec : Predicate<"PPCSubTarget->hasAltivec()">;
341 let Predicates = [HasAltivec] in {
343 def DSS : DSS_Form<0, 822, (outs), (ins u5imm:$STRM),
344 "dss $STRM", IIC_LdStLoad /*FIXME*/, [(int_ppc_altivec_dss imm:$STRM)]>,
345 Deprecated<DeprecatedDST> {
350 def DSSALL : DSS_Form<1, 822, (outs), (ins),
351 "dssall", IIC_LdStLoad /*FIXME*/, [(int_ppc_altivec_dssall)]>,
352 Deprecated<DeprecatedDST> {
358 def DST : DSS_Form<0, 342, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB),
359 "dst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
360 [(int_ppc_altivec_dst i32:$rA, i32:$rB, imm:$STRM)]>,
361 Deprecated<DeprecatedDST>;
363 def DSTT : DSS_Form<1, 342, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB),
364 "dstt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
365 [(int_ppc_altivec_dstt i32:$rA, i32:$rB, imm:$STRM)]>,
366 Deprecated<DeprecatedDST>;
368 def DSTST : DSS_Form<0, 374, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB),
369 "dstst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
370 [(int_ppc_altivec_dstst i32:$rA, i32:$rB, imm:$STRM)]>,
371 Deprecated<DeprecatedDST>;
373 def DSTSTT : DSS_Form<1, 374, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB),
374 "dststt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
375 [(int_ppc_altivec_dststt i32:$rA, i32:$rB, imm:$STRM)]>,
376 Deprecated<DeprecatedDST>;
378 let isCodeGenOnly = 1 in {
379 // The very same instructions as above, but formally matching 64bit registers.
380 def DST64 : DSS_Form<0, 342, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB),
381 "dst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
382 [(int_ppc_altivec_dst i64:$rA, i32:$rB, imm:$STRM)]>,
383 Deprecated<DeprecatedDST>;
385 def DSTT64 : DSS_Form<1, 342, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB),
386 "dstt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
387 [(int_ppc_altivec_dstt i64:$rA, i32:$rB, imm:$STRM)]>,
388 Deprecated<DeprecatedDST>;
390 def DSTST64 : DSS_Form<0, 374, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB),
391 "dstst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
392 [(int_ppc_altivec_dstst i64:$rA, i32:$rB,
394 Deprecated<DeprecatedDST>;
396 def DSTSTT64 : DSS_Form<1, 374, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB),
397 "dststt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
398 [(int_ppc_altivec_dststt i64:$rA, i32:$rB,
400 Deprecated<DeprecatedDST>;
403 def MFVSCR : VXForm_4<1540, (outs vrrc:$vD), (ins),
404 "mfvscr $vD", IIC_LdStStore,
405 [(set v8i16:$vD, (int_ppc_altivec_mfvscr))]>;
406 def MTVSCR : VXForm_5<1604, (outs), (ins vrrc:$vB),
407 "mtvscr $vB", IIC_LdStLoad,
408 [(int_ppc_altivec_mtvscr v4i32:$vB)]>;
410 let PPC970_Unit = 2, mayLoad = 1, mayStore = 0 in { // Loads.
411 def LVEBX: XForm_1<31, 7, (outs vrrc:$vD), (ins memrr:$src),
412 "lvebx $vD, $src", IIC_LdStLoad,
413 [(set v16i8:$vD, (int_ppc_altivec_lvebx xoaddr:$src))]>;
414 def LVEHX: XForm_1<31, 39, (outs vrrc:$vD), (ins memrr:$src),
415 "lvehx $vD, $src", IIC_LdStLoad,
416 [(set v8i16:$vD, (int_ppc_altivec_lvehx xoaddr:$src))]>;
417 def LVEWX: XForm_1<31, 71, (outs vrrc:$vD), (ins memrr:$src),
418 "lvewx $vD, $src", IIC_LdStLoad,
419 [(set v4i32:$vD, (int_ppc_altivec_lvewx xoaddr:$src))]>;
420 def LVX : XForm_1<31, 103, (outs vrrc:$vD), (ins memrr:$src),
421 "lvx $vD, $src", IIC_LdStLoad,
422 [(set v4i32:$vD, (int_ppc_altivec_lvx xoaddr:$src))]>;
423 def LVXL : XForm_1<31, 359, (outs vrrc:$vD), (ins memrr:$src),
424 "lvxl $vD, $src", IIC_LdStLoad,
425 [(set v4i32:$vD, (int_ppc_altivec_lvxl xoaddr:$src))]>;
428 def LVSL : XForm_1<31, 6, (outs vrrc:$vD), (ins memrr:$src),
429 "lvsl $vD, $src", IIC_LdStLoad,
430 [(set v16i8:$vD, (int_ppc_altivec_lvsl xoaddr:$src))]>,
432 def LVSR : XForm_1<31, 38, (outs vrrc:$vD), (ins memrr:$src),
433 "lvsr $vD, $src", IIC_LdStLoad,
434 [(set v16i8:$vD, (int_ppc_altivec_lvsr xoaddr:$src))]>,
437 let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { // Stores.
438 def STVEBX: XForm_8<31, 135, (outs), (ins vrrc:$rS, memrr:$dst),
439 "stvebx $rS, $dst", IIC_LdStStore,
440 [(int_ppc_altivec_stvebx v16i8:$rS, xoaddr:$dst)]>;
441 def STVEHX: XForm_8<31, 167, (outs), (ins vrrc:$rS, memrr:$dst),
442 "stvehx $rS, $dst", IIC_LdStStore,
443 [(int_ppc_altivec_stvehx v8i16:$rS, xoaddr:$dst)]>;
444 def STVEWX: XForm_8<31, 199, (outs), (ins vrrc:$rS, memrr:$dst),
445 "stvewx $rS, $dst", IIC_LdStStore,
446 [(int_ppc_altivec_stvewx v4i32:$rS, xoaddr:$dst)]>;
447 def STVX : XForm_8<31, 231, (outs), (ins vrrc:$rS, memrr:$dst),
448 "stvx $rS, $dst", IIC_LdStStore,
449 [(int_ppc_altivec_stvx v4i32:$rS, xoaddr:$dst)]>;
450 def STVXL : XForm_8<31, 487, (outs), (ins vrrc:$rS, memrr:$dst),
451 "stvxl $rS, $dst", IIC_LdStStore,
452 [(int_ppc_altivec_stvxl v4i32:$rS, xoaddr:$dst)]>;
455 let PPC970_Unit = 5 in { // VALU Operations.
456 // VA-Form instructions. 3-input AltiVec ops.
457 let isCommutable = 1 in {
458 def VMADDFP : VAForm_1<46, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vC, vrrc:$vB),
459 "vmaddfp $vD, $vA, $vC, $vB", IIC_VecFP,
461 (fma v4f32:$vA, v4f32:$vC, v4f32:$vB))]>;
463 // FIXME: The fma+fneg pattern won't match because fneg is not legal.
464 def VNMSUBFP: VAForm_1<47, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vC, vrrc:$vB),
465 "vnmsubfp $vD, $vA, $vC, $vB", IIC_VecFP,
466 [(set v4f32:$vD, (fneg (fma v4f32:$vA, v4f32:$vC,
467 (fneg v4f32:$vB))))]>;
469 def VMHADDSHS : VA1a_Int_Ty<32, "vmhaddshs", int_ppc_altivec_vmhaddshs, v8i16>;
470 def VMHRADDSHS : VA1a_Int_Ty<33, "vmhraddshs", int_ppc_altivec_vmhraddshs,
472 def VMLADDUHM : VA1a_Int_Ty<34, "vmladduhm", int_ppc_altivec_vmladduhm, v8i16>;
475 def VPERM : VA1a_Int_Ty3<43, "vperm", int_ppc_altivec_vperm,
476 v4i32, v4i32, v16i8>;
477 def VSEL : VA1a_Int_Ty<42, "vsel", int_ppc_altivec_vsel, v4i32>;
480 def VSLDOI : VAForm_2<44, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, u5imm:$SH),
481 "vsldoi $vD, $vA, $vB, $SH", IIC_VecFP,
483 (vsldoi_shuffle:$SH v16i8:$vA, v16i8:$vB))]>;
485 // VX-Form instructions. AltiVec arithmetic ops.
486 let isCommutable = 1 in {
487 def VADDFP : VXForm_1<10, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
488 "vaddfp $vD, $vA, $vB", IIC_VecFP,
489 [(set v4f32:$vD, (fadd v4f32:$vA, v4f32:$vB))]>;
491 def VADDUBM : VXForm_1<0, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
492 "vaddubm $vD, $vA, $vB", IIC_VecGeneral,
493 [(set v16i8:$vD, (add v16i8:$vA, v16i8:$vB))]>;
494 def VADDUHM : VXForm_1<64, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
495 "vadduhm $vD, $vA, $vB", IIC_VecGeneral,
496 [(set v8i16:$vD, (add v8i16:$vA, v8i16:$vB))]>;
497 def VADDUWM : VXForm_1<128, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
498 "vadduwm $vD, $vA, $vB", IIC_VecGeneral,
499 [(set v4i32:$vD, (add v4i32:$vA, v4i32:$vB))]>;
501 def VADDCUW : VX1_Int_Ty<384, "vaddcuw", int_ppc_altivec_vaddcuw, v4i32>;
502 def VADDSBS : VX1_Int_Ty<768, "vaddsbs", int_ppc_altivec_vaddsbs, v16i8>;
503 def VADDSHS : VX1_Int_Ty<832, "vaddshs", int_ppc_altivec_vaddshs, v8i16>;
504 def VADDSWS : VX1_Int_Ty<896, "vaddsws", int_ppc_altivec_vaddsws, v4i32>;
505 def VADDUBS : VX1_Int_Ty<512, "vaddubs", int_ppc_altivec_vaddubs, v16i8>;
506 def VADDUHS : VX1_Int_Ty<576, "vadduhs", int_ppc_altivec_vadduhs, v8i16>;
507 def VADDUWS : VX1_Int_Ty<640, "vadduws", int_ppc_altivec_vadduws, v4i32>;
510 let isCommutable = 1 in
511 def VAND : VXForm_1<1028, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
512 "vand $vD, $vA, $vB", IIC_VecFP,
513 [(set v4i32:$vD, (and v4i32:$vA, v4i32:$vB))]>;
514 def VANDC : VXForm_1<1092, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
515 "vandc $vD, $vA, $vB", IIC_VecFP,
516 [(set v4i32:$vD, (and v4i32:$vA,
517 (vnot_ppc v4i32:$vB)))]>;
519 def VCFSX : VXForm_1<842, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
520 "vcfsx $vD, $vB, $UIMM", IIC_VecFP,
522 (int_ppc_altivec_vcfsx v4i32:$vB, imm:$UIMM))]>;
523 def VCFUX : VXForm_1<778, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
524 "vcfux $vD, $vB, $UIMM", IIC_VecFP,
526 (int_ppc_altivec_vcfux v4i32:$vB, imm:$UIMM))]>;
527 def VCTSXS : VXForm_1<970, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
528 "vctsxs $vD, $vB, $UIMM", IIC_VecFP,
530 (int_ppc_altivec_vctsxs v4f32:$vB, imm:$UIMM))]>;
531 def VCTUXS : VXForm_1<906, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
532 "vctuxs $vD, $vB, $UIMM", IIC_VecFP,
534 (int_ppc_altivec_vctuxs v4f32:$vB, imm:$UIMM))]>;
536 // Defines with the UIM field set to 0 for floating-point
537 // to integer (fp_to_sint/fp_to_uint) conversions and integer
538 // to floating-point (sint_to_fp/uint_to_fp) conversions.
539 let isCodeGenOnly = 1, VA = 0 in {
540 def VCFSX_0 : VXForm_1<842, (outs vrrc:$vD), (ins vrrc:$vB),
541 "vcfsx $vD, $vB, 0", IIC_VecFP,
543 (int_ppc_altivec_vcfsx v4i32:$vB, 0))]>;
544 def VCTUXS_0 : VXForm_1<906, (outs vrrc:$vD), (ins vrrc:$vB),
545 "vctuxs $vD, $vB, 0", IIC_VecFP,
547 (int_ppc_altivec_vctuxs v4f32:$vB, 0))]>;
548 def VCFUX_0 : VXForm_1<778, (outs vrrc:$vD), (ins vrrc:$vB),
549 "vcfux $vD, $vB, 0", IIC_VecFP,
551 (int_ppc_altivec_vcfux v4i32:$vB, 0))]>;
552 def VCTSXS_0 : VXForm_1<970, (outs vrrc:$vD), (ins vrrc:$vB),
553 "vctsxs $vD, $vB, 0", IIC_VecFP,
555 (int_ppc_altivec_vctsxs v4f32:$vB, 0))]>;
557 def VEXPTEFP : VX2_Int_SP<394, "vexptefp", int_ppc_altivec_vexptefp>;
558 def VLOGEFP : VX2_Int_SP<458, "vlogefp", int_ppc_altivec_vlogefp>;
560 let isCommutable = 1 in {
561 def VAVGSB : VX1_Int_Ty<1282, "vavgsb", int_ppc_altivec_vavgsb, v16i8>;
562 def VAVGSH : VX1_Int_Ty<1346, "vavgsh", int_ppc_altivec_vavgsh, v8i16>;
563 def VAVGSW : VX1_Int_Ty<1410, "vavgsw", int_ppc_altivec_vavgsw, v4i32>;
564 def VAVGUB : VX1_Int_Ty<1026, "vavgub", int_ppc_altivec_vavgub, v16i8>;
565 def VAVGUH : VX1_Int_Ty<1090, "vavguh", int_ppc_altivec_vavguh, v8i16>;
566 def VAVGUW : VX1_Int_Ty<1154, "vavguw", int_ppc_altivec_vavguw, v4i32>;
568 def VMAXFP : VX1_Int_Ty<1034, "vmaxfp", int_ppc_altivec_vmaxfp, v4f32>;
569 def VMAXSB : VX1_Int_Ty< 258, "vmaxsb", int_ppc_altivec_vmaxsb, v16i8>;
570 def VMAXSH : VX1_Int_Ty< 322, "vmaxsh", int_ppc_altivec_vmaxsh, v8i16>;
571 def VMAXSW : VX1_Int_Ty< 386, "vmaxsw", int_ppc_altivec_vmaxsw, v4i32>;
572 def VMAXUB : VX1_Int_Ty< 2, "vmaxub", int_ppc_altivec_vmaxub, v16i8>;
573 def VMAXUH : VX1_Int_Ty< 66, "vmaxuh", int_ppc_altivec_vmaxuh, v8i16>;
574 def VMAXUW : VX1_Int_Ty< 130, "vmaxuw", int_ppc_altivec_vmaxuw, v4i32>;
575 def VMINFP : VX1_Int_Ty<1098, "vminfp", int_ppc_altivec_vminfp, v4f32>;
576 def VMINSB : VX1_Int_Ty< 770, "vminsb", int_ppc_altivec_vminsb, v16i8>;
577 def VMINSH : VX1_Int_Ty< 834, "vminsh", int_ppc_altivec_vminsh, v8i16>;
578 def VMINSW : VX1_Int_Ty< 898, "vminsw", int_ppc_altivec_vminsw, v4i32>;
579 def VMINUB : VX1_Int_Ty< 514, "vminub", int_ppc_altivec_vminub, v16i8>;
580 def VMINUH : VX1_Int_Ty< 578, "vminuh", int_ppc_altivec_vminuh, v8i16>;
581 def VMINUW : VX1_Int_Ty< 642, "vminuw", int_ppc_altivec_vminuw, v4i32>;
584 def VMRGHB : VXForm_1< 12, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
585 "vmrghb $vD, $vA, $vB", IIC_VecFP,
586 [(set v16i8:$vD, (vmrghb_shuffle v16i8:$vA, v16i8:$vB))]>;
587 def VMRGHH : VXForm_1< 76, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
588 "vmrghh $vD, $vA, $vB", IIC_VecFP,
589 [(set v16i8:$vD, (vmrghh_shuffle v16i8:$vA, v16i8:$vB))]>;
590 def VMRGHW : VXForm_1<140, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
591 "vmrghw $vD, $vA, $vB", IIC_VecFP,
592 [(set v16i8:$vD, (vmrghw_shuffle v16i8:$vA, v16i8:$vB))]>;
593 def VMRGLB : VXForm_1<268, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
594 "vmrglb $vD, $vA, $vB", IIC_VecFP,
595 [(set v16i8:$vD, (vmrglb_shuffle v16i8:$vA, v16i8:$vB))]>;
596 def VMRGLH : VXForm_1<332, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
597 "vmrglh $vD, $vA, $vB", IIC_VecFP,
598 [(set v16i8:$vD, (vmrglh_shuffle v16i8:$vA, v16i8:$vB))]>;
599 def VMRGLW : VXForm_1<396, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
600 "vmrglw $vD, $vA, $vB", IIC_VecFP,
601 [(set v16i8:$vD, (vmrglw_shuffle v16i8:$vA, v16i8:$vB))]>;
603 def VMSUMMBM : VA1a_Int_Ty3<37, "vmsummbm", int_ppc_altivec_vmsummbm,
604 v4i32, v16i8, v4i32>;
605 def VMSUMSHM : VA1a_Int_Ty3<40, "vmsumshm", int_ppc_altivec_vmsumshm,
606 v4i32, v8i16, v4i32>;
607 def VMSUMSHS : VA1a_Int_Ty3<41, "vmsumshs", int_ppc_altivec_vmsumshs,
608 v4i32, v8i16, v4i32>;
609 def VMSUMUBM : VA1a_Int_Ty3<36, "vmsumubm", int_ppc_altivec_vmsumubm,
610 v4i32, v16i8, v4i32>;
611 def VMSUMUHM : VA1a_Int_Ty3<38, "vmsumuhm", int_ppc_altivec_vmsumuhm,
612 v4i32, v8i16, v4i32>;
613 def VMSUMUHS : VA1a_Int_Ty3<39, "vmsumuhs", int_ppc_altivec_vmsumuhs,
614 v4i32, v8i16, v4i32>;
616 let isCommutable = 1 in {
617 def VMULESB : VX1_Int_Ty2<776, "vmulesb", int_ppc_altivec_vmulesb,
619 def VMULESH : VX1_Int_Ty2<840, "vmulesh", int_ppc_altivec_vmulesh,
621 def VMULEUB : VX1_Int_Ty2<520, "vmuleub", int_ppc_altivec_vmuleub,
623 def VMULEUH : VX1_Int_Ty2<584, "vmuleuh", int_ppc_altivec_vmuleuh,
625 def VMULOSB : VX1_Int_Ty2<264, "vmulosb", int_ppc_altivec_vmulosb,
627 def VMULOSH : VX1_Int_Ty2<328, "vmulosh", int_ppc_altivec_vmulosh,
629 def VMULOUB : VX1_Int_Ty2< 8, "vmuloub", int_ppc_altivec_vmuloub,
631 def VMULOUH : VX1_Int_Ty2< 72, "vmulouh", int_ppc_altivec_vmulouh,
635 def VREFP : VX2_Int_SP<266, "vrefp", int_ppc_altivec_vrefp>;
636 def VRFIM : VX2_Int_SP<714, "vrfim", int_ppc_altivec_vrfim>;
637 def VRFIN : VX2_Int_SP<522, "vrfin", int_ppc_altivec_vrfin>;
638 def VRFIP : VX2_Int_SP<650, "vrfip", int_ppc_altivec_vrfip>;
639 def VRFIZ : VX2_Int_SP<586, "vrfiz", int_ppc_altivec_vrfiz>;
640 def VRSQRTEFP : VX2_Int_SP<330, "vrsqrtefp", int_ppc_altivec_vrsqrtefp>;
642 def VSUBCUW : VX1_Int_Ty<1408, "vsubcuw", int_ppc_altivec_vsubcuw, v4i32>;
644 def VSUBFP : VXForm_1<74, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
645 "vsubfp $vD, $vA, $vB", IIC_VecGeneral,
646 [(set v4f32:$vD, (fsub v4f32:$vA, v4f32:$vB))]>;
647 def VSUBUBM : VXForm_1<1024, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
648 "vsububm $vD, $vA, $vB", IIC_VecGeneral,
649 [(set v16i8:$vD, (sub v16i8:$vA, v16i8:$vB))]>;
650 def VSUBUHM : VXForm_1<1088, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
651 "vsubuhm $vD, $vA, $vB", IIC_VecGeneral,
652 [(set v8i16:$vD, (sub v8i16:$vA, v8i16:$vB))]>;
653 def VSUBUWM : VXForm_1<1152, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
654 "vsubuwm $vD, $vA, $vB", IIC_VecGeneral,
655 [(set v4i32:$vD, (sub v4i32:$vA, v4i32:$vB))]>;
657 def VSUBSBS : VX1_Int_Ty<1792, "vsubsbs" , int_ppc_altivec_vsubsbs, v16i8>;
658 def VSUBSHS : VX1_Int_Ty<1856, "vsubshs" , int_ppc_altivec_vsubshs, v8i16>;
659 def VSUBSWS : VX1_Int_Ty<1920, "vsubsws" , int_ppc_altivec_vsubsws, v4i32>;
660 def VSUBUBS : VX1_Int_Ty<1536, "vsububs" , int_ppc_altivec_vsububs, v16i8>;
661 def VSUBUHS : VX1_Int_Ty<1600, "vsubuhs" , int_ppc_altivec_vsubuhs, v8i16>;
662 def VSUBUWS : VX1_Int_Ty<1664, "vsubuws" , int_ppc_altivec_vsubuws, v4i32>;
664 def VSUMSWS : VX1_Int_Ty<1928, "vsumsws" , int_ppc_altivec_vsumsws, v4i32>;
665 def VSUM2SWS: VX1_Int_Ty<1672, "vsum2sws", int_ppc_altivec_vsum2sws, v4i32>;
667 def VSUM4SBS: VX1_Int_Ty3<1800, "vsum4sbs", int_ppc_altivec_vsum4sbs,
668 v4i32, v16i8, v4i32>;
669 def VSUM4SHS: VX1_Int_Ty3<1608, "vsum4shs", int_ppc_altivec_vsum4shs,
670 v4i32, v8i16, v4i32>;
671 def VSUM4UBS: VX1_Int_Ty3<1544, "vsum4ubs", int_ppc_altivec_vsum4ubs,
672 v4i32, v16i8, v4i32>;
674 def VNOR : VXForm_1<1284, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
675 "vnor $vD, $vA, $vB", IIC_VecFP,
676 [(set v4i32:$vD, (vnot_ppc (or v4i32:$vA,
678 let isCommutable = 1 in {
679 def VOR : VXForm_1<1156, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
680 "vor $vD, $vA, $vB", IIC_VecFP,
681 [(set v4i32:$vD, (or v4i32:$vA, v4i32:$vB))]>;
682 def VXOR : VXForm_1<1220, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
683 "vxor $vD, $vA, $vB", IIC_VecFP,
684 [(set v4i32:$vD, (xor v4i32:$vA, v4i32:$vB))]>;
687 def VRLB : VX1_Int_Ty< 4, "vrlb", int_ppc_altivec_vrlb, v16i8>;
688 def VRLH : VX1_Int_Ty< 68, "vrlh", int_ppc_altivec_vrlh, v8i16>;
689 def VRLW : VX1_Int_Ty< 132, "vrlw", int_ppc_altivec_vrlw, v4i32>;
691 def VSL : VX1_Int_Ty< 452, "vsl" , int_ppc_altivec_vsl, v4i32 >;
692 def VSLO : VX1_Int_Ty<1036, "vslo", int_ppc_altivec_vslo, v4i32>;
694 def VSLB : VX1_Int_Ty< 260, "vslb", int_ppc_altivec_vslb, v16i8>;
695 def VSLH : VX1_Int_Ty< 324, "vslh", int_ppc_altivec_vslh, v8i16>;
696 def VSLW : VX1_Int_Ty< 388, "vslw", int_ppc_altivec_vslw, v4i32>;
698 def VSPLTB : VXForm_1<524, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
699 "vspltb $vD, $vB, $UIMM", IIC_VecPerm,
701 (vspltb_shuffle:$UIMM v16i8:$vB, (undef)))]>;
702 def VSPLTH : VXForm_1<588, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
703 "vsplth $vD, $vB, $UIMM", IIC_VecPerm,
705 (vsplth_shuffle:$UIMM v16i8:$vB, (undef)))]>;
706 def VSPLTW : VXForm_1<652, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
707 "vspltw $vD, $vB, $UIMM", IIC_VecPerm,
709 (vspltw_shuffle:$UIMM v16i8:$vB, (undef)))]>;
710 let isCodeGenOnly = 1 in {
711 def VSPLTBs : VXForm_1<524, (outs vrrc:$vD), (ins u5imm:$UIMM, vfrc:$vB),
712 "vspltb $vD, $vB, $UIMM", IIC_VecPerm, []>;
713 def VSPLTHs : VXForm_1<588, (outs vrrc:$vD), (ins u5imm:$UIMM, vfrc:$vB),
714 "vsplth $vD, $vB, $UIMM", IIC_VecPerm, []>;
717 def VSR : VX1_Int_Ty< 708, "vsr" , int_ppc_altivec_vsr, v4i32>;
718 def VSRO : VX1_Int_Ty<1100, "vsro" , int_ppc_altivec_vsro, v4i32>;
720 def VSRAB : VX1_Int_Ty< 772, "vsrab", int_ppc_altivec_vsrab, v16i8>;
721 def VSRAH : VX1_Int_Ty< 836, "vsrah", int_ppc_altivec_vsrah, v8i16>;
722 def VSRAW : VX1_Int_Ty< 900, "vsraw", int_ppc_altivec_vsraw, v4i32>;
723 def VSRB : VX1_Int_Ty< 516, "vsrb" , int_ppc_altivec_vsrb , v16i8>;
724 def VSRH : VX1_Int_Ty< 580, "vsrh" , int_ppc_altivec_vsrh , v8i16>;
725 def VSRW : VX1_Int_Ty< 644, "vsrw" , int_ppc_altivec_vsrw , v4i32>;
728 def VSPLTISB : VXForm_3<780, (outs vrrc:$vD), (ins s5imm:$SIMM),
729 "vspltisb $vD, $SIMM", IIC_VecPerm,
730 [(set v16i8:$vD, (v16i8 vecspltisb:$SIMM))]>;
731 def VSPLTISH : VXForm_3<844, (outs vrrc:$vD), (ins s5imm:$SIMM),
732 "vspltish $vD, $SIMM", IIC_VecPerm,
733 [(set v8i16:$vD, (v8i16 vecspltish:$SIMM))]>;
734 def VSPLTISW : VXForm_3<908, (outs vrrc:$vD), (ins s5imm:$SIMM),
735 "vspltisw $vD, $SIMM", IIC_VecPerm,
736 [(set v4i32:$vD, (v4i32 vecspltisw:$SIMM))]>;
739 def VPKPX : VX1_Int_Ty2<782, "vpkpx", int_ppc_altivec_vpkpx,
741 def VPKSHSS : VX1_Int_Ty2<398, "vpkshss", int_ppc_altivec_vpkshss,
743 def VPKSHUS : VX1_Int_Ty2<270, "vpkshus", int_ppc_altivec_vpkshus,
745 def VPKSWSS : VX1_Int_Ty2<462, "vpkswss", int_ppc_altivec_vpkswss,
747 def VPKSWUS : VX1_Int_Ty2<334, "vpkswus", int_ppc_altivec_vpkswus,
749 def VPKUHUM : VXForm_1<14, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
750 "vpkuhum $vD, $vA, $vB", IIC_VecFP,
752 (vpkuhum_shuffle v16i8:$vA, v16i8:$vB))]>;
753 def VPKUHUS : VX1_Int_Ty2<142, "vpkuhus", int_ppc_altivec_vpkuhus,
755 def VPKUWUM : VXForm_1<78, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
756 "vpkuwum $vD, $vA, $vB", IIC_VecFP,
758 (vpkuwum_shuffle v16i8:$vA, v16i8:$vB))]>;
759 def VPKUWUS : VX1_Int_Ty2<206, "vpkuwus", int_ppc_altivec_vpkuwus,
763 def VUPKHPX : VX2_Int_Ty2<846, "vupkhpx", int_ppc_altivec_vupkhpx,
765 def VUPKHSB : VX2_Int_Ty2<526, "vupkhsb", int_ppc_altivec_vupkhsb,
767 def VUPKHSH : VX2_Int_Ty2<590, "vupkhsh", int_ppc_altivec_vupkhsh,
769 def VUPKLPX : VX2_Int_Ty2<974, "vupklpx", int_ppc_altivec_vupklpx,
771 def VUPKLSB : VX2_Int_Ty2<654, "vupklsb", int_ppc_altivec_vupklsb,
773 def VUPKLSH : VX2_Int_Ty2<718, "vupklsh", int_ppc_altivec_vupklsh,
777 // Altivec Comparisons.
779 class VCMP<bits<10> xo, string asmstr, ValueType Ty>
780 : VXRForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), asmstr,
782 [(set Ty:$vD, (Ty (PPCvcmp Ty:$vA, Ty:$vB, xo)))]>;
783 class VCMPo<bits<10> xo, string asmstr, ValueType Ty>
784 : VXRForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), asmstr,
786 [(set Ty:$vD, (Ty (PPCvcmp_o Ty:$vA, Ty:$vB, xo)))]> {
791 // f32 element comparisons.0
792 def VCMPBFP : VCMP <966, "vcmpbfp $vD, $vA, $vB" , v4f32>;
793 def VCMPBFPo : VCMPo<966, "vcmpbfp. $vD, $vA, $vB" , v4f32>;
794 def VCMPEQFP : VCMP <198, "vcmpeqfp $vD, $vA, $vB" , v4f32>;
795 def VCMPEQFPo : VCMPo<198, "vcmpeqfp. $vD, $vA, $vB", v4f32>;
796 def VCMPGEFP : VCMP <454, "vcmpgefp $vD, $vA, $vB" , v4f32>;
797 def VCMPGEFPo : VCMPo<454, "vcmpgefp. $vD, $vA, $vB", v4f32>;
798 def VCMPGTFP : VCMP <710, "vcmpgtfp $vD, $vA, $vB" , v4f32>;
799 def VCMPGTFPo : VCMPo<710, "vcmpgtfp. $vD, $vA, $vB", v4f32>;
801 // i8 element comparisons.
802 def VCMPEQUB : VCMP < 6, "vcmpequb $vD, $vA, $vB" , v16i8>;
803 def VCMPEQUBo : VCMPo< 6, "vcmpequb. $vD, $vA, $vB", v16i8>;
804 def VCMPGTSB : VCMP <774, "vcmpgtsb $vD, $vA, $vB" , v16i8>;
805 def VCMPGTSBo : VCMPo<774, "vcmpgtsb. $vD, $vA, $vB", v16i8>;
806 def VCMPGTUB : VCMP <518, "vcmpgtub $vD, $vA, $vB" , v16i8>;
807 def VCMPGTUBo : VCMPo<518, "vcmpgtub. $vD, $vA, $vB", v16i8>;
809 // i16 element comparisons.
810 def VCMPEQUH : VCMP < 70, "vcmpequh $vD, $vA, $vB" , v8i16>;
811 def VCMPEQUHo : VCMPo< 70, "vcmpequh. $vD, $vA, $vB", v8i16>;
812 def VCMPGTSH : VCMP <838, "vcmpgtsh $vD, $vA, $vB" , v8i16>;
813 def VCMPGTSHo : VCMPo<838, "vcmpgtsh. $vD, $vA, $vB", v8i16>;
814 def VCMPGTUH : VCMP <582, "vcmpgtuh $vD, $vA, $vB" , v8i16>;
815 def VCMPGTUHo : VCMPo<582, "vcmpgtuh. $vD, $vA, $vB", v8i16>;
817 // i32 element comparisons.
818 def VCMPEQUW : VCMP <134, "vcmpequw $vD, $vA, $vB" , v4i32>;
819 def VCMPEQUWo : VCMPo<134, "vcmpequw. $vD, $vA, $vB", v4i32>;
820 def VCMPGTSW : VCMP <902, "vcmpgtsw $vD, $vA, $vB" , v4i32>;
821 def VCMPGTSWo : VCMPo<902, "vcmpgtsw. $vD, $vA, $vB", v4i32>;
822 def VCMPGTUW : VCMP <646, "vcmpgtuw $vD, $vA, $vB" , v4i32>;
823 def VCMPGTUWo : VCMPo<646, "vcmpgtuw. $vD, $vA, $vB", v4i32>;
825 let isCodeGenOnly = 1 in {
826 def V_SET0B : VXForm_setzero<1220, (outs vrrc:$vD), (ins),
827 "vxor $vD, $vD, $vD", IIC_VecFP,
828 [(set v16i8:$vD, (v16i8 immAllZerosV))]>;
829 def V_SET0H : VXForm_setzero<1220, (outs vrrc:$vD), (ins),
830 "vxor $vD, $vD, $vD", IIC_VecFP,
831 [(set v8i16:$vD, (v8i16 immAllZerosV))]>;
832 def V_SET0 : VXForm_setzero<1220, (outs vrrc:$vD), (ins),
833 "vxor $vD, $vD, $vD", IIC_VecFP,
834 [(set v4i32:$vD, (v4i32 immAllZerosV))]>;
837 def V_SETALLONESB : VXForm_3<908, (outs vrrc:$vD), (ins),
838 "vspltisw $vD, -1", IIC_VecFP,
839 [(set v16i8:$vD, (v16i8 immAllOnesV))]>;
840 def V_SETALLONESH : VXForm_3<908, (outs vrrc:$vD), (ins),
841 "vspltisw $vD, -1", IIC_VecFP,
842 [(set v8i16:$vD, (v8i16 immAllOnesV))]>;
843 def V_SETALLONES : VXForm_3<908, (outs vrrc:$vD), (ins),
844 "vspltisw $vD, -1", IIC_VecFP,
845 [(set v4i32:$vD, (v4i32 immAllOnesV))]>;
848 } // VALU Operations.
850 //===----------------------------------------------------------------------===//
851 // Additional Altivec Patterns
854 // Extended mnemonics
855 def : InstAlias<"vmr $vD, $vA", (VOR vrrc:$vD, vrrc:$vA, vrrc:$vA)>;
856 def : InstAlias<"vnot $vD, $vA", (VNOR vrrc:$vD, vrrc:$vA, vrrc:$vA)>;
859 def : Pat<(v4i32 (load xoaddr:$src)), (LVX xoaddr:$src)>;
862 def : Pat<(store v4i32:$rS, xoaddr:$dst),
863 (STVX $rS, xoaddr:$dst)>;
866 def : Pat<(v16i8 (bitconvert (v8i16 VRRC:$src))), (v16i8 VRRC:$src)>;
867 def : Pat<(v16i8 (bitconvert (v4i32 VRRC:$src))), (v16i8 VRRC:$src)>;
868 def : Pat<(v16i8 (bitconvert (v4f32 VRRC:$src))), (v16i8 VRRC:$src)>;
869 def : Pat<(v16i8 (bitconvert (v2i64 VRRC:$src))), (v16i8 VRRC:$src)>;
870 def : Pat<(v16i8 (bitconvert (v1i128 VRRC:$src))), (v16i8 VRRC:$src)>;
872 def : Pat<(v8i16 (bitconvert (v16i8 VRRC:$src))), (v8i16 VRRC:$src)>;
873 def : Pat<(v8i16 (bitconvert (v4i32 VRRC:$src))), (v8i16 VRRC:$src)>;
874 def : Pat<(v8i16 (bitconvert (v4f32 VRRC:$src))), (v8i16 VRRC:$src)>;
875 def : Pat<(v8i16 (bitconvert (v2i64 VRRC:$src))), (v8i16 VRRC:$src)>;
876 def : Pat<(v8i16 (bitconvert (v1i128 VRRC:$src))), (v8i16 VRRC:$src)>;
878 def : Pat<(v4i32 (bitconvert (v16i8 VRRC:$src))), (v4i32 VRRC:$src)>;
879 def : Pat<(v4i32 (bitconvert (v8i16 VRRC:$src))), (v4i32 VRRC:$src)>;
880 def : Pat<(v4i32 (bitconvert (v4f32 VRRC:$src))), (v4i32 VRRC:$src)>;
881 def : Pat<(v4i32 (bitconvert (v2i64 VRRC:$src))), (v4i32 VRRC:$src)>;
882 def : Pat<(v4i32 (bitconvert (v1i128 VRRC:$src))), (v4i32 VRRC:$src)>;
884 def : Pat<(v4f32 (bitconvert (v16i8 VRRC:$src))), (v4f32 VRRC:$src)>;
885 def : Pat<(v4f32 (bitconvert (v8i16 VRRC:$src))), (v4f32 VRRC:$src)>;
886 def : Pat<(v4f32 (bitconvert (v4i32 VRRC:$src))), (v4f32 VRRC:$src)>;
887 def : Pat<(v4f32 (bitconvert (v2i64 VRRC:$src))), (v4f32 VRRC:$src)>;
888 def : Pat<(v4f32 (bitconvert (v1i128 VRRC:$src))), (v4f32 VRRC:$src)>;
890 def : Pat<(v2i64 (bitconvert (v16i8 VRRC:$src))), (v2i64 VRRC:$src)>;
891 def : Pat<(v2i64 (bitconvert (v8i16 VRRC:$src))), (v2i64 VRRC:$src)>;
892 def : Pat<(v2i64 (bitconvert (v4i32 VRRC:$src))), (v2i64 VRRC:$src)>;
893 def : Pat<(v2i64 (bitconvert (v4f32 VRRC:$src))), (v2i64 VRRC:$src)>;
894 def : Pat<(v2i64 (bitconvert (v1i128 VRRC:$src))), (v2i64 VRRC:$src)>;
896 def : Pat<(v1i128 (bitconvert (v16i8 VRRC:$src))), (v1i128 VRRC:$src)>;
897 def : Pat<(v1i128 (bitconvert (v8i16 VRRC:$src))), (v1i128 VRRC:$src)>;
898 def : Pat<(v1i128 (bitconvert (v4i32 VRRC:$src))), (v1i128 VRRC:$src)>;
899 def : Pat<(v1i128 (bitconvert (v4f32 VRRC:$src))), (v1i128 VRRC:$src)>;
900 def : Pat<(v1i128 (bitconvert (v2i64 VRRC:$src))), (v1i128 VRRC:$src)>;
904 // Match vsldoi(x,x), vpkuwum(x,x), vpkuhum(x,x)
905 def:Pat<(vsldoi_unary_shuffle:$in v16i8:$vA, undef),
906 (VSLDOI $vA, $vA, (VSLDOI_unary_get_imm $in))>;
907 def:Pat<(vpkuwum_unary_shuffle v16i8:$vA, undef),
909 def:Pat<(vpkuhum_unary_shuffle v16i8:$vA, undef),
912 // Match vsldoi(y,x), vpkuwum(y,x), vpkuhum(y,x), i.e., swapped operands.
913 // These fragments are matched for little-endian, where the inputs must
914 // be swapped for correct semantics.
915 def:Pat<(vsldoi_swapped_shuffle:$in v16i8:$vA, v16i8:$vB),
916 (VSLDOI $vB, $vA, (VSLDOI_swapped_get_imm $in))>;
917 def:Pat<(vpkuwum_swapped_shuffle v16i8:$vA, v16i8:$vB),
919 def:Pat<(vpkuhum_swapped_shuffle v16i8:$vA, v16i8:$vB),
923 def:Pat<(vmrglb_unary_shuffle v16i8:$vA, undef),
925 def:Pat<(vmrglh_unary_shuffle v16i8:$vA, undef),
927 def:Pat<(vmrglw_unary_shuffle v16i8:$vA, undef),
929 def:Pat<(vmrghb_unary_shuffle v16i8:$vA, undef),
931 def:Pat<(vmrghh_unary_shuffle v16i8:$vA, undef),
933 def:Pat<(vmrghw_unary_shuffle v16i8:$vA, undef),
936 // Match vmrg*(y,x), i.e., swapped operands. These fragments
937 // are matched for little-endian, where the inputs must be
938 // swapped for correct semantics.
939 def:Pat<(vmrglb_swapped_shuffle v16i8:$vA, v16i8:$vB),
941 def:Pat<(vmrglh_swapped_shuffle v16i8:$vA, v16i8:$vB),
943 def:Pat<(vmrglw_swapped_shuffle v16i8:$vA, v16i8:$vB),
945 def:Pat<(vmrghb_swapped_shuffle v16i8:$vA, v16i8:$vB),
947 def:Pat<(vmrghh_swapped_shuffle v16i8:$vA, v16i8:$vB),
949 def:Pat<(vmrghw_swapped_shuffle v16i8:$vA, v16i8:$vB),
952 // Logical Operations
953 def : Pat<(vnot_ppc v4i32:$vA), (VNOR $vA, $vA)>;
955 def : Pat<(vnot_ppc (or v4i32:$A, v4i32:$B)),
957 def : Pat<(and v4i32:$A, (vnot_ppc v4i32:$B)),
960 def : Pat<(fmul v4f32:$vA, v4f32:$vB),
962 (v4i32 (VSLW (V_SETALLONES), (V_SETALLONES))))>;
964 // Fused multiply add and multiply sub for packed float. These are represented
965 // separately from the real instructions above, for operations that must have
966 // the additional precision, such as Newton-Rhapson (used by divide, sqrt)
967 def : Pat<(PPCvmaddfp v4f32:$A, v4f32:$B, v4f32:$C),
968 (VMADDFP $A, $B, $C)>;
969 def : Pat<(PPCvnmsubfp v4f32:$A, v4f32:$B, v4f32:$C),
970 (VNMSUBFP $A, $B, $C)>;
972 def : Pat<(int_ppc_altivec_vmaddfp v4f32:$A, v4f32:$B, v4f32:$C),
973 (VMADDFP $A, $B, $C)>;
974 def : Pat<(int_ppc_altivec_vnmsubfp v4f32:$A, v4f32:$B, v4f32:$C),
975 (VNMSUBFP $A, $B, $C)>;
977 def : Pat<(PPCvperm v16i8:$vA, v16i8:$vB, v16i8:$vC),
978 (VPERM $vA, $vB, $vC)>;
980 def : Pat<(PPCfre v4f32:$A), (VREFP $A)>;
981 def : Pat<(PPCfrsqrte v4f32:$A), (VRSQRTEFP $A)>;
984 def : Pat<(v16i8 (shl v16i8:$vA, v16i8:$vB)),
985 (v16i8 (VSLB $vA, $vB))>;
986 def : Pat<(v8i16 (shl v8i16:$vA, v8i16:$vB)),
987 (v8i16 (VSLH $vA, $vB))>;
988 def : Pat<(v4i32 (shl v4i32:$vA, v4i32:$vB)),
989 (v4i32 (VSLW $vA, $vB))>;
991 def : Pat<(v16i8 (srl v16i8:$vA, v16i8:$vB)),
992 (v16i8 (VSRB $vA, $vB))>;
993 def : Pat<(v8i16 (srl v8i16:$vA, v8i16:$vB)),
994 (v8i16 (VSRH $vA, $vB))>;
995 def : Pat<(v4i32 (srl v4i32:$vA, v4i32:$vB)),
996 (v4i32 (VSRW $vA, $vB))>;
998 def : Pat<(v16i8 (sra v16i8:$vA, v16i8:$vB)),
999 (v16i8 (VSRAB $vA, $vB))>;
1000 def : Pat<(v8i16 (sra v8i16:$vA, v8i16:$vB)),
1001 (v8i16 (VSRAH $vA, $vB))>;
1002 def : Pat<(v4i32 (sra v4i32:$vA, v4i32:$vB)),
1003 (v4i32 (VSRAW $vA, $vB))>;
1005 // Float to integer and integer to float conversions
1006 def : Pat<(v4i32 (fp_to_sint v4f32:$vA)),
1008 def : Pat<(v4i32 (fp_to_uint v4f32:$vA)),
1010 def : Pat<(v4f32 (sint_to_fp v4i32:$vA)),
1012 def : Pat<(v4f32 (uint_to_fp v4i32:$vA)),
1015 // Floating-point rounding
1016 def : Pat<(v4f32 (ffloor v4f32:$vA)),
1018 def : Pat<(v4f32 (fceil v4f32:$vA)),
1020 def : Pat<(v4f32 (ftrunc v4f32:$vA)),
1022 def : Pat<(v4f32 (fnearbyint v4f32:$vA)),
1027 def HasP8Altivec : Predicate<"PPCSubTarget->hasP8Altivec()">;
1028 def HasP8Crypto : Predicate<"PPCSubTarget->hasP8Crypto()">;
1029 let Predicates = [HasP8Altivec] in {
1031 let isCommutable = 1 in {
1032 def VMULESW : VX1_Int_Ty2<904, "vmulesw", int_ppc_altivec_vmulesw,
1034 def VMULEUW : VX1_Int_Ty2<648, "vmuleuw", int_ppc_altivec_vmuleuw,
1036 def VMULOSW : VX1_Int_Ty2<392, "vmulosw", int_ppc_altivec_vmulosw,
1038 def VMULOUW : VX1_Int_Ty2<136, "vmulouw", int_ppc_altivec_vmulouw,
1040 def VMULUWM : VXForm_1<137, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1041 "vmuluwm $vD, $vA, $vB", IIC_VecGeneral,
1042 [(set v4i32:$vD, (mul v4i32:$vA, v4i32:$vB))]>;
1043 def VMAXSD : VX1_Int_Ty<450, "vmaxsd", int_ppc_altivec_vmaxsd, v2i64>;
1044 def VMAXUD : VX1_Int_Ty<194, "vmaxud", int_ppc_altivec_vmaxud, v2i64>;
1045 def VMINSD : VX1_Int_Ty<962, "vminsd", int_ppc_altivec_vminsd, v2i64>;
1046 def VMINUD : VX1_Int_Ty<706, "vminud", int_ppc_altivec_vminud, v2i64>;
1050 def VMRGEW : VXForm_1<1932, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1051 "vmrgew $vD, $vA, $vB", IIC_VecFP,
1052 [(set v16i8:$vD, (vmrgew_shuffle v16i8:$vA, v16i8:$vB))]>;
1053 def VMRGOW : VXForm_1<1676, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1054 "vmrgow $vD, $vA, $vB", IIC_VecFP,
1055 [(set v16i8:$vD, (vmrgow_shuffle v16i8:$vA, v16i8:$vB))]>;
1057 // Match vmrgew(x,x) and vmrgow(x,x)
1058 def:Pat<(vmrgew_unary_shuffle v16i8:$vA, undef),
1060 def:Pat<(vmrgow_unary_shuffle v16i8:$vA, undef),
1063 // Match vmrgew(y,x) and vmrgow(y,x), i.e., swapped operands. These fragments
1064 // are matched for little-endian, where the inputs must be swapped for correct
1066 def:Pat<(vmrgew_swapped_shuffle v16i8:$vA, v16i8:$vB),
1068 def:Pat<(vmrgow_swapped_shuffle v16i8:$vA, v16i8:$vB),
1073 def VRLD : VX1_Int_Ty<196, "vrld", int_ppc_altivec_vrld, v2i64>;
1074 def VSLD : VXForm_1<1476, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1075 "vsld $vD, $vA, $vB", IIC_VecGeneral,
1076 [(set v2i64:$vD, (shl v2i64:$vA, v2i64:$vB))]>;
1077 def VSRD : VXForm_1<1732, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1078 "vsrd $vD, $vA, $vB", IIC_VecGeneral,
1079 [(set v2i64:$vD, (srl v2i64:$vA, v2i64:$vB))]>;
1080 def VSRAD : VXForm_1<964, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1081 "vsrad $vD, $vA, $vB", IIC_VecGeneral,
1082 [(set v2i64:$vD, (sra v2i64:$vA, v2i64:$vB))]>;
1084 // Vector Integer Arithmetic Instructions
1085 let isCommutable = 1 in {
1086 def VADDUDM : VXForm_1<192, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1087 "vaddudm $vD, $vA, $vB", IIC_VecGeneral,
1088 [(set v2i64:$vD, (add v2i64:$vA, v2i64:$vB))]>;
1089 def VADDUQM : VXForm_1<256, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1090 "vadduqm $vD, $vA, $vB", IIC_VecGeneral,
1091 [(set v1i128:$vD, (add v1i128:$vA, v1i128:$vB))]>;
1094 // Vector Quadword Add
1095 def VADDEUQM : VA1a_Int_Ty<60, "vaddeuqm", int_ppc_altivec_vaddeuqm, v1i128>;
1096 def VADDCUQ : VX1_Int_Ty<320, "vaddcuq", int_ppc_altivec_vaddcuq, v1i128>;
1097 def VADDECUQ : VA1a_Int_Ty<61, "vaddecuq", int_ppc_altivec_vaddecuq, v1i128>;
1099 // Vector Doubleword Subtract
1100 def VSUBUDM : VXForm_1<1216, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1101 "vsubudm $vD, $vA, $vB", IIC_VecGeneral,
1102 [(set v2i64:$vD, (sub v2i64:$vA, v2i64:$vB))]>;
1104 // Vector Quadword Subtract
1105 def VSUBUQM : VXForm_1<1280, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1106 "vsubuqm $vD, $vA, $vB", IIC_VecGeneral,
1107 [(set v1i128:$vD, (sub v1i128:$vA, v1i128:$vB))]>;
1108 def VSUBEUQM : VA1a_Int_Ty<62, "vsubeuqm", int_ppc_altivec_vsubeuqm, v1i128>;
1109 def VSUBCUQ : VX1_Int_Ty<1344, "vsubcuq", int_ppc_altivec_vsubcuq, v1i128>;
1110 def VSUBECUQ : VA1a_Int_Ty<63, "vsubecuq", int_ppc_altivec_vsubecuq, v1i128>;
1112 // Count Leading Zeros
1113 def VCLZB : VXForm_2<1794, (outs vrrc:$vD), (ins vrrc:$vB),
1114 "vclzb $vD, $vB", IIC_VecGeneral,
1115 [(set v16i8:$vD, (ctlz v16i8:$vB))]>;
1116 def VCLZH : VXForm_2<1858, (outs vrrc:$vD), (ins vrrc:$vB),
1117 "vclzh $vD, $vB", IIC_VecGeneral,
1118 [(set v8i16:$vD, (ctlz v8i16:$vB))]>;
1119 def VCLZW : VXForm_2<1922, (outs vrrc:$vD), (ins vrrc:$vB),
1120 "vclzw $vD, $vB", IIC_VecGeneral,
1121 [(set v4i32:$vD, (ctlz v4i32:$vB))]>;
1122 def VCLZD : VXForm_2<1986, (outs vrrc:$vD), (ins vrrc:$vB),
1123 "vclzd $vD, $vB", IIC_VecGeneral,
1124 [(set v2i64:$vD, (ctlz v2i64:$vB))]>;
1127 def VPOPCNTB : VXForm_2<1795, (outs vrrc:$vD), (ins vrrc:$vB),
1128 "vpopcntb $vD, $vB", IIC_VecGeneral,
1129 [(set v16i8:$vD, (ctpop v16i8:$vB))]>;
1130 def VPOPCNTH : VXForm_2<1859, (outs vrrc:$vD), (ins vrrc:$vB),
1131 "vpopcnth $vD, $vB", IIC_VecGeneral,
1132 [(set v8i16:$vD, (ctpop v8i16:$vB))]>;
1133 def VPOPCNTW : VXForm_2<1923, (outs vrrc:$vD), (ins vrrc:$vB),
1134 "vpopcntw $vD, $vB", IIC_VecGeneral,
1135 [(set v4i32:$vD, (ctpop v4i32:$vB))]>;
1136 def VPOPCNTD : VXForm_2<1987, (outs vrrc:$vD), (ins vrrc:$vB),
1137 "vpopcntd $vD, $vB", IIC_VecGeneral,
1138 [(set v2i64:$vD, (ctpop v2i64:$vB))]>;
1140 let isCommutable = 1 in {
1141 // FIXME: Use AddedComplexity > 400 to ensure these patterns match before the
1142 // VSX equivalents. We need to fix this up at some point. Two possible
1143 // solutions for this problem:
1144 // 1. Disable Altivec patterns that compete with VSX patterns using the
1145 // !HasVSX predicate. This essentially favours VSX over Altivec, in
1146 // hopes of reducing register pressure (larger register set using VSX
1147 // instructions than VMX instructions)
1148 // 2. Employ a more disciplined use of AddedComplexity, which would provide
1149 // more fine-grained control than option 1. This would be beneficial
1150 // if we find situations where Altivec is really preferred over VSX.
1151 def VEQV : VXForm_1<1668, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1152 "veqv $vD, $vA, $vB", IIC_VecGeneral,
1153 [(set v4i32:$vD, (vnot_ppc (xor v4i32:$vA, v4i32:$vB)))]>;
1154 def VNAND : VXForm_1<1412, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1155 "vnand $vD, $vA, $vB", IIC_VecGeneral,
1156 [(set v4i32:$vD, (vnot_ppc (and v4i32:$vA, v4i32:$vB)))]>;
1159 def VORC : VXForm_1<1348, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1160 "vorc $vD, $vA, $vB", IIC_VecGeneral,
1161 [(set v4i32:$vD, (or v4i32:$vA,
1162 (vnot_ppc v4i32:$vB)))]>;
1164 // i64 element comparisons.
1165 def VCMPEQUD : VCMP <199, "vcmpequd $vD, $vA, $vB" , v2i64>;
1166 def VCMPEQUDo : VCMPo<199, "vcmpequd. $vD, $vA, $vB", v2i64>;
1167 def VCMPGTSD : VCMP <967, "vcmpgtsd $vD, $vA, $vB" , v2i64>;
1168 def VCMPGTSDo : VCMPo<967, "vcmpgtsd. $vD, $vA, $vB", v2i64>;
1169 def VCMPGTUD : VCMP <711, "vcmpgtud $vD, $vA, $vB" , v2i64>;
1170 def VCMPGTUDo : VCMPo<711, "vcmpgtud. $vD, $vA, $vB", v2i64>;
1172 // The cryptography instructions that do not require Category:Vector.Crypto
1173 def VPMSUMB : VX1_Int_Ty<1032, "vpmsumb",
1174 int_ppc_altivec_crypto_vpmsumb, v16i8>;
1175 def VPMSUMH : VX1_Int_Ty<1096, "vpmsumh",
1176 int_ppc_altivec_crypto_vpmsumh, v8i16>;
1177 def VPMSUMW : VX1_Int_Ty<1160, "vpmsumw",
1178 int_ppc_altivec_crypto_vpmsumw, v4i32>;
1179 def VPMSUMD : VX1_Int_Ty<1224, "vpmsumd",
1180 int_ppc_altivec_crypto_vpmsumd, v2i64>;
1181 def VPERMXOR : VA1a_Int_Ty<45, "vpermxor",
1182 int_ppc_altivec_crypto_vpermxor, v16i8>;
1184 // Vector doubleword integer pack and unpack.
1185 def VPKSDSS : VX1_Int_Ty2<1486, "vpksdss", int_ppc_altivec_vpksdss,
1187 def VPKSDUS : VX1_Int_Ty2<1358, "vpksdus", int_ppc_altivec_vpksdus,
1189 def VPKUDUM : VXForm_1<1102, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1190 "vpkudum $vD, $vA, $vB", IIC_VecFP,
1192 (vpkudum_shuffle v16i8:$vA, v16i8:$vB))]>;
1193 def VPKUDUS : VX1_Int_Ty2<1230, "vpkudus", int_ppc_altivec_vpkudus,
1195 def VUPKHSW : VX2_Int_Ty2<1614, "vupkhsw", int_ppc_altivec_vupkhsw,
1197 def VUPKLSW : VX2_Int_Ty2<1742, "vupklsw", int_ppc_altivec_vupklsw,
1200 // Shuffle patterns for unary and swapped (LE) vector pack modulo.
1201 def:Pat<(vpkudum_unary_shuffle v16i8:$vA, undef),
1202 (VPKUDUM $vA, $vA)>;
1203 def:Pat<(vpkudum_swapped_shuffle v16i8:$vA, v16i8:$vB),
1204 (VPKUDUM $vB, $vA)>;
1206 def VGBBD : VX2_Int_Ty2<1292, "vgbbd", int_ppc_altivec_vgbbd, v16i8, v16i8>;
1207 def VBPERMQ : VX1_Int_Ty2<1356, "vbpermq", int_ppc_altivec_vbpermq,
1209 } // end HasP8Altivec
1211 // Crypto instructions (from builtins)
1212 let Predicates = [HasP8Crypto] in {
1213 def VSHASIGMAW : VXCR_Int_Ty<1666, "vshasigmaw",
1214 int_ppc_altivec_crypto_vshasigmaw, v4i32>;
1215 def VSHASIGMAD : VXCR_Int_Ty<1730, "vshasigmad",
1216 int_ppc_altivec_crypto_vshasigmad, v2i64>;
1217 def VCIPHER : VX1_Int_Ty<1288, "vcipher", int_ppc_altivec_crypto_vcipher,
1219 def VCIPHERLAST : VX1_Int_Ty<1289, "vcipherlast",
1220 int_ppc_altivec_crypto_vcipherlast, v2i64>;
1221 def VNCIPHER : VX1_Int_Ty<1352, "vncipher",
1222 int_ppc_altivec_crypto_vncipher, v2i64>;
1223 def VNCIPHERLAST : VX1_Int_Ty<1353, "vncipherlast",
1224 int_ppc_altivec_crypto_vncipherlast, v2i64>;
1225 def VSBOX : VXBX_Int_Ty<1480, "vsbox", int_ppc_altivec_crypto_vsbox, v2i64>;
1228 // The following altivec instructions were introduced in Power ISA 3.0
1229 def HasP9Altivec : Predicate<"PPCSubTarget->hasP9Altivec()">;
1230 let Predicates = [HasP9Altivec] in {
1232 // i8 element comparisons.
1233 def VCMPNEB : VCMP < 7, "vcmpneb $vD, $vA, $vB" , v16i8>;
1234 def VCMPNEBo : VCMPo < 7, "vcmpneb. $vD, $vA, $vB" , v16i8>;
1235 def VCMPNEZB : VCMP <263, "vcmpnezb $vD, $vA, $vB" , v16i8>;
1236 def VCMPNEZBo : VCMPo<263, "vcmpnezb. $vD, $vA, $vB", v16i8>;
1238 // i16 element comparisons.
1239 def VCMPNEH : VCMP < 71, "vcmpneh $vD, $vA, $vB" , v8i16>;
1240 def VCMPNEHo : VCMPo< 71, "vcmpneh. $vD, $vA, $vB" , v8i16>;
1241 def VCMPNEZH : VCMP <327, "vcmpnezh $vD, $vA, $vB" , v8i16>;
1242 def VCMPNEZHo : VCMPo<327, "vcmpnezh. $vD, $vA, $vB", v8i16>;
1244 // i32 element comparisons.
1245 def VCMPNEW : VCMP <135, "vcmpnew $vD, $vA, $vB" , v4i32>;
1246 def VCMPNEWo : VCMPo<135, "vcmpnew. $vD, $vA, $vB" , v4i32>;
1247 def VCMPNEZW : VCMP <391, "vcmpnezw $vD, $vA, $vB" , v4i32>;
1248 def VCMPNEZWo : VCMPo<391, "vcmpnezw. $vD, $vA, $vB", v4i32>;
1250 // VX-Form: [PO VRT / UIM VRB XO].
1251 // We use VXForm_1 to implement it, that is, we use "VRA" (5 bit) to represent
1252 // "/ UIM" (1 + 4 bit)
1253 class VX1_VT5_UIM5_VB5<bits<11> xo, string opc, list<dag> pattern>
1254 : VXForm_1<xo, (outs vrrc:$vD), (ins u4imm:$UIMM, vrrc:$vB),
1255 !strconcat(opc, " $vD, $vB, $UIMM"), IIC_VecGeneral, pattern>;
1257 class VX1_RT5_RA5_VB5<bits<11> xo, string opc, list<dag> pattern>
1258 : VXForm_1<xo, (outs g8rc:$rD), (ins g8rc:$rA, vrrc:$vB),
1259 !strconcat(opc, " $rD, $rA, $vB"), IIC_VecGeneral, pattern>;
1261 // Vector Extract Unsigned
1262 def VEXTRACTUB : VX1_VT5_UIM5_VB5<525, "vextractub", []>;
1263 def VEXTRACTUH : VX1_VT5_UIM5_VB5<589, "vextractuh", []>;
1264 def VEXTRACTUW : VX1_VT5_UIM5_VB5<653, "vextractuw", []>;
1265 def VEXTRACTD : VX1_VT5_UIM5_VB5<717, "vextractd" , []>;
1267 // Vector Extract Unsigned Byte/Halfword/Word Left/Right-Indexed
1268 def VEXTUBLX : VX1_RT5_RA5_VB5<1549, "vextublx", []>;
1269 def VEXTUBRX : VX1_RT5_RA5_VB5<1805, "vextubrx", []>;
1270 def VEXTUHLX : VX1_RT5_RA5_VB5<1613, "vextuhlx", []>;
1271 def VEXTUHRX : VX1_RT5_RA5_VB5<1869, "vextuhrx", []>;
1272 def VEXTUWLX : VX1_RT5_RA5_VB5<1677, "vextuwlx", []>;
1273 def VEXTUWRX : VX1_RT5_RA5_VB5<1933, "vextuwrx", []>;
1275 // Vector Insert Element Instructions
1276 def VINSERTB : VX1_VT5_UIM5_VB5<781, "vinsertb", []>;
1277 def VINSERTH : VX1_VT5_UIM5_VB5<845, "vinserth", []>;
1278 def VINSERTW : VX1_VT5_UIM5_VB5<909, "vinsertw", []>;
1279 def VINSERTD : VX1_VT5_UIM5_VB5<973, "vinsertd", []>;
1281 class VX_VT5_EO5_VB5<bits<11> xo, bits<5> eo, string opc, list<dag> pattern>
1282 : VXForm_RD5_XO5_RS5<xo, eo, (outs vrrc:$vD), (ins vrrc:$vB),
1283 !strconcat(opc, " $vD, $vB"), IIC_VecGeneral, pattern>;
1284 class VX_VT5_EO5_VB5s<bits<11> xo, bits<5> eo, string opc, list<dag> pattern>
1285 : VXForm_RD5_XO5_RS5<xo, eo, (outs vfrc:$vD), (ins vfrc:$vB),
1286 !strconcat(opc, " $vD, $vB"), IIC_VecGeneral, pattern>;
1288 // Vector Count Leading/Trailing Zero LSB. Result is placed into GPR[rD]
1289 def VCLZLSBB : VXForm_RD5_XO5_RS5<1538, 0, (outs gprc:$rD), (ins vrrc:$vB),
1290 "vclzlsbb $rD, $vB", IIC_VecGeneral,
1291 [(set i32:$rD, (int_ppc_altivec_vclzlsbb
1293 def VCTZLSBB : VXForm_RD5_XO5_RS5<1538, 1, (outs gprc:$rD), (ins vrrc:$vB),
1294 "vctzlsbb $rD, $vB", IIC_VecGeneral,
1295 [(set i32:$rD, (int_ppc_altivec_vctzlsbb
1297 // Vector Count Trailing Zeros
1298 def VCTZB : VX_VT5_EO5_VB5<1538, 28, "vctzb",
1299 [(set v16i8:$vD, (cttz v16i8:$vB))]>;
1300 def VCTZH : VX_VT5_EO5_VB5<1538, 29, "vctzh",
1301 [(set v8i16:$vD, (cttz v8i16:$vB))]>;
1302 def VCTZW : VX_VT5_EO5_VB5<1538, 30, "vctzw",
1303 [(set v4i32:$vD, (cttz v4i32:$vB))]>;
1304 def VCTZD : VX_VT5_EO5_VB5<1538, 31, "vctzd",
1305 [(set v2i64:$vD, (cttz v2i64:$vB))]>;
1307 // Vector Extend Sign
1308 def VEXTSB2W : VX_VT5_EO5_VB5<1538, 16, "vextsb2w", []>;
1309 def VEXTSH2W : VX_VT5_EO5_VB5<1538, 17, "vextsh2w", []>;
1310 def VEXTSB2D : VX_VT5_EO5_VB5<1538, 24, "vextsb2d", []>;
1311 def VEXTSH2D : VX_VT5_EO5_VB5<1538, 25, "vextsh2d", []>;
1312 def VEXTSW2D : VX_VT5_EO5_VB5<1538, 26, "vextsw2d", []>;
1313 let isCodeGenOnly = 1 in {
1314 def VEXTSB2Ws : VX_VT5_EO5_VB5s<1538, 16, "vextsb2w", []>;
1315 def VEXTSH2Ws : VX_VT5_EO5_VB5s<1538, 17, "vextsh2w", []>;
1316 def VEXTSB2Ds : VX_VT5_EO5_VB5s<1538, 24, "vextsb2d", []>;
1317 def VEXTSH2Ds : VX_VT5_EO5_VB5s<1538, 25, "vextsh2d", []>;
1318 def VEXTSW2Ds : VX_VT5_EO5_VB5s<1538, 26, "vextsw2d", []>;
1321 // Vector Integer Negate
1322 def VNEGW : VX_VT5_EO5_VB5<1538, 6, "vnegw",
1324 (sub (v4i32 immAllZerosV), v4i32:$vB))]>;
1326 def VNEGD : VX_VT5_EO5_VB5<1538, 7, "vnegd",
1328 (sub (v2i64 (bitconvert (v4i32 immAllZerosV))),
1331 // Vector Parity Byte
1332 def VPRTYBW : VX_VT5_EO5_VB5<1538, 8, "vprtybw", [(set v4i32:$vD,
1333 (int_ppc_altivec_vprtybw v4i32:$vB))]>;
1334 def VPRTYBD : VX_VT5_EO5_VB5<1538, 9, "vprtybd", [(set v2i64:$vD,
1335 (int_ppc_altivec_vprtybd v2i64:$vB))]>;
1336 def VPRTYBQ : VX_VT5_EO5_VB5<1538, 10, "vprtybq", [(set v1i128:$vD,
1337 (int_ppc_altivec_vprtybq v1i128:$vB))]>;
1339 // Vector (Bit) Permute (Right-indexed)
1340 def VBPERMD : VXForm_1<1484, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1341 "vbpermd $vD, $vA, $vB", IIC_VecFP, []>;
1342 def VPERMR : VAForm_1a<59, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC),
1343 "vpermr $vD, $vA, $vB, $vC", IIC_VecFP, []>;
1345 class VX1_VT5_VA5_VB5<bits<11> xo, string opc, list<dag> pattern>
1346 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1347 !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP, pattern>;
1349 // Vector Rotate Left Mask/Mask-Insert
1350 def VRLWNM : VX1_VT5_VA5_VB5<389, "vrlwnm",
1352 (int_ppc_altivec_vrlwnm v4i32:$vA,
1354 def VRLWMI : VXForm_1<133, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vDi),
1355 "vrlwmi $vD, $vA, $vB", IIC_VecFP,
1357 (int_ppc_altivec_vrlwmi v4i32:$vA, v4i32:$vB,
1359 RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">;
1360 def VRLDNM : VX1_VT5_VA5_VB5<453, "vrldnm",
1362 (int_ppc_altivec_vrldnm v2i64:$vA,
1364 def VRLDMI : VXForm_1<197, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vDi),
1365 "vrldmi $vD, $vA, $vB", IIC_VecFP,
1367 (int_ppc_altivec_vrldmi v2i64:$vA, v2i64:$vB,
1369 RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">;
1371 // Vector Shift Left/Right
1372 def VSLV : VX1_VT5_VA5_VB5<1860, "vslv",
1373 [(set v16i8 : $vD, (int_ppc_altivec_vslv v16i8 : $vA, v16i8 : $vB))]>;
1374 def VSRV : VX1_VT5_VA5_VB5<1796, "vsrv",
1375 [(set v16i8 : $vD, (int_ppc_altivec_vsrv v16i8 : $vA, v16i8 : $vB))]>;
1377 // Vector Multiply-by-10 (& Write Carry) Unsigned Quadword
1378 def VMUL10UQ : VXForm_BX<513, (outs vrrc:$vD), (ins vrrc:$vA),
1379 "vmul10uq $vD, $vA", IIC_VecFP, []>;
1380 def VMUL10CUQ : VXForm_BX< 1, (outs vrrc:$vD), (ins vrrc:$vA),
1381 "vmul10cuq $vD, $vA", IIC_VecFP, []>;
1383 // Vector Multiply-by-10 Extended (& Write Carry) Unsigned Quadword
1384 def VMUL10EUQ : VX1_VT5_VA5_VB5<577, "vmul10euq" , []>;
1385 def VMUL10ECUQ : VX1_VT5_VA5_VB5< 65, "vmul10ecuq", []>;
1387 // Decimal Integer Format Conversion Instructions
1389 // [PO VRT EO VRB 1 PS XO], "_o" means CR6 is set.
1390 class VX_VT5_EO5_VB5_PS1_XO9_o<bits<5> eo, bits<9> xo, string opc,
1392 : VX_RD5_EO5_RS5_PS1_XO9<eo, xo, (outs vrrc:$vD), (ins vrrc:$vB, u1imm:$PS),
1393 !strconcat(opc, " $vD, $vB, $PS"), IIC_VecFP, pattern> {
1397 // [PO VRT EO VRB 1 / XO]
1398 class VX_VT5_EO5_VB5_XO9_o<bits<5> eo, bits<9> xo, string opc,
1400 : VX_RD5_EO5_RS5_PS1_XO9<eo, xo, (outs vrrc:$vD), (ins vrrc:$vB),
1401 !strconcat(opc, " $vD, $vB"), IIC_VecFP, pattern> {
1406 // Decimal Convert From/to National/Zoned/Signed-QWord
1407 def BCDCFNo : VX_VT5_EO5_VB5_PS1_XO9_o<7, 385, "bcdcfn." , []>;
1408 def BCDCFZo : VX_VT5_EO5_VB5_PS1_XO9_o<6, 385, "bcdcfz." , []>;
1409 def BCDCTNo : VX_VT5_EO5_VB5_XO9_o <5, 385, "bcdctn." , []>;
1410 def BCDCTZo : VX_VT5_EO5_VB5_PS1_XO9_o<4, 385, "bcdctz." , []>;
1411 def BCDCFSQo : VX_VT5_EO5_VB5_PS1_XO9_o<2, 385, "bcdcfsq.", []>;
1412 def BCDCTSQo : VX_VT5_EO5_VB5_XO9_o <0, 385, "bcdctsq.", []>;
1414 // Decimal Copy-Sign/Set-Sign
1416 def BCDCPSGNo : VX1_VT5_VA5_VB5<833, "bcdcpsgn.", []>;
1418 def BCDSETSGNo : VX_VT5_EO5_VB5_PS1_XO9_o<31, 385, "bcdsetsgn.", []>;
1420 // [PO VRT VRA VRB 1 PS XO], "_o" means CR6 is set.
1421 class VX_VT5_VA5_VB5_PS1_XO9_o<bits<9> xo, string opc, list<dag> pattern>
1422 : VX_RD5_RSp5_PS1_XO9<xo,
1423 (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, u1imm:$PS),
1424 !strconcat(opc, " $vD, $vA, $vB, $PS"), IIC_VecFP, pattern> {
1428 // [PO VRT VRA VRB 1 / XO]
1429 class VX_VT5_VA5_VB5_XO9_o<bits<9> xo, string opc, list<dag> pattern>
1430 : VX_RD5_RSp5_PS1_XO9<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1431 !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP, pattern> {
1436 // Decimal Shift/Unsigned-Shift/Shift-and-Round
1437 def BCDSo : VX_VT5_VA5_VB5_PS1_XO9_o<193, "bcds." , []>;
1438 def BCDUSo : VX_VT5_VA5_VB5_XO9_o <129, "bcdus.", []>;
1439 def BCDSRo : VX_VT5_VA5_VB5_PS1_XO9_o<449, "bcdsr.", []>;
1441 // Decimal (Unsigned) Truncate
1442 def BCDTRUNCo : VX_VT5_VA5_VB5_PS1_XO9_o<257, "bcdtrunc." , []>;
1443 def BCDUTRUNCo : VX_VT5_VA5_VB5_XO9_o <321, "bcdutrunc.", []>;
1445 // Absolute Difference
1446 def VABSDUB : VXForm_1<1027, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1447 "vabsdub $vD, $vA, $vB", IIC_VecGeneral,
1448 [(set v16i8:$vD, (int_ppc_altivec_vabsdub v16i8:$vA, v16i8:$vB))]>;
1449 def VABSDUH : VXForm_1<1091, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1450 "vabsduh $vD, $vA, $vB", IIC_VecGeneral,
1451 [(set v8i16:$vD, (int_ppc_altivec_vabsduh v8i16:$vA, v8i16:$vB))]>;
1452 def VABSDUW : VXForm_1<1155, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1453 "vabsduw $vD, $vA, $vB", IIC_VecGeneral,
1454 [(set v4i32:$vD, (int_ppc_altivec_vabsduw v4i32:$vA, v4i32:$vB))]>;
1455 } // end HasP9Altivec