1 //===- PowerPCInstrFormats.td - PowerPC Instruction Formats --*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 // PowerPC instruction formats
14 class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin>
17 field bits<32> SoftFail = 0;
20 bit PPC64 = 0; // Default value, override with isPPC64
22 let Namespace = "PPC";
23 let Inst{0-5} = opcode;
24 let OutOperandList = OOL;
25 let InOperandList = IOL;
26 let AsmString = asmstr;
29 bits<1> PPC970_First = 0;
30 bits<1> PPC970_Single = 0;
31 bits<1> PPC970_Cracked = 0;
32 bits<3> PPC970_Unit = 0;
34 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to
35 /// these must be reflected there! See comments there for what these are.
36 let TSFlags{0} = PPC970_First;
37 let TSFlags{1} = PPC970_Single;
38 let TSFlags{2} = PPC970_Cracked;
39 let TSFlags{5-3} = PPC970_Unit;
41 /// Indicate that the VSX instruction is to use VSX numbering/encoding.
42 /// Since ISA 3.0, there are scalar instructions that use the upper
43 /// half of the VSX register set only. Rather than adding further complexity
44 /// to the register class set, the VSX registers just include the Altivec
45 /// registers and this flag decides the numbering to be used for them.
46 bits<1> UseVSXReg = 0;
47 let TSFlags{6} = UseVSXReg;
49 // Fields used for relation models.
52 // For cases where multiple instruction definitions really represent the
53 // same underlying instruction but with one definition for 64-bit arguments
54 // and one for 32-bit arguments, this bit breaks the degeneracy between
55 // the two forms and allows TableGen to generate mapping tables.
56 bit Interpretation64Bit = 0;
59 class PPC970_DGroup_First { bits<1> PPC970_First = 1; }
60 class PPC970_DGroup_Single { bits<1> PPC970_Single = 1; }
61 class PPC970_DGroup_Cracked { bits<1> PPC970_Cracked = 1; }
62 class PPC970_MicroCode;
64 class PPC970_Unit_Pseudo { bits<3> PPC970_Unit = 0; }
65 class PPC970_Unit_FXU { bits<3> PPC970_Unit = 1; }
66 class PPC970_Unit_LSU { bits<3> PPC970_Unit = 2; }
67 class PPC970_Unit_FPU { bits<3> PPC970_Unit = 3; }
68 class PPC970_Unit_CRU { bits<3> PPC970_Unit = 4; }
69 class PPC970_Unit_VALU { bits<3> PPC970_Unit = 5; }
70 class PPC970_Unit_VPERM { bits<3> PPC970_Unit = 6; }
71 class PPC970_Unit_BRU { bits<3> PPC970_Unit = 7; }
73 class UseVSXReg { bits<1> UseVSXReg = 1; }
75 // Two joined instructions; used to emit two adjacent instructions as one.
76 // The itinerary from the first instruction is used for scheduling and
78 class I2<bits<6> opcode1, bits<6> opcode2, dag OOL, dag IOL, string asmstr,
82 field bits<64> SoftFail = 0;
85 bit PPC64 = 0; // Default value, override with isPPC64
87 let Namespace = "PPC";
88 let Inst{0-5} = opcode1;
89 let Inst{32-37} = opcode2;
90 let OutOperandList = OOL;
91 let InOperandList = IOL;
92 let AsmString = asmstr;
95 bits<1> PPC970_First = 0;
96 bits<1> PPC970_Single = 0;
97 bits<1> PPC970_Cracked = 0;
98 bits<3> PPC970_Unit = 0;
100 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to
101 /// these must be reflected there! See comments there for what these are.
102 let TSFlags{0} = PPC970_First;
103 let TSFlags{1} = PPC970_Single;
104 let TSFlags{2} = PPC970_Cracked;
105 let TSFlags{5-3} = PPC970_Unit;
107 // Fields used for relation models.
108 string BaseName = "";
109 bit Interpretation64Bit = 0;
113 class IForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr,
114 InstrItinClass itin, list<dag> pattern>
115 : I<opcode, OOL, IOL, asmstr, itin> {
116 let Pattern = pattern;
125 class BForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr>
126 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
127 bits<7> BIBO; // 2 bits of BI and 5 bits of BO.
132 let BI{0-1} = BIBO{5-6};
133 let BI{2-4} = CR{0-2};
135 let Inst{6-10} = BIBO{4-0};
136 let Inst{11-15} = BI;
137 let Inst{16-29} = BD;
142 class BForm_1<bits<6> opcode, bits<5> bo, bit aa, bit lk, dag OOL, dag IOL,
144 : BForm<opcode, aa, lk, OOL, IOL, asmstr> {
150 class BForm_2<bits<6> opcode, bits<5> bo, bits<5> bi, bit aa, bit lk,
151 dag OOL, dag IOL, string asmstr>
152 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
156 let Inst{11-15} = bi;
157 let Inst{16-29} = BD;
162 class BForm_3<bits<6> opcode, bit aa, bit lk,
163 dag OOL, dag IOL, string asmstr>
164 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
170 let Inst{11-15} = BI;
171 let Inst{16-29} = BD;
176 class BForm_3_at<bits<6> opcode, bit aa, bit lk,
177 dag OOL, dag IOL, string asmstr>
178 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
184 let Inst{6-8} = BO{4-2};
186 let Inst{11-15} = BI;
187 let Inst{16-29} = BD;
192 class BForm_4<bits<6> opcode, bits<5> bo, bit aa, bit lk,
193 dag OOL, dag IOL, string asmstr>
194 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
199 let Inst{11-15} = BI;
200 let Inst{16-29} = BD;
206 class SCForm<bits<6> opcode, bits<1> xo,
207 dag OOL, dag IOL, string asmstr, InstrItinClass itin,
209 : I<opcode, OOL, IOL, asmstr, itin> {
212 let Pattern = pattern;
214 let Inst{20-26} = LEV;
219 class DForm_base<bits<6> opcode, dag OOL, dag IOL, string asmstr,
220 InstrItinClass itin, list<dag> pattern>
221 : I<opcode, OOL, IOL, asmstr, itin> {
226 let Pattern = pattern;
233 class DForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr,
234 InstrItinClass itin, list<dag> pattern>
235 : I<opcode, OOL, IOL, asmstr, itin> {
239 let Pattern = pattern;
242 let Inst{11-15} = Addr{20-16}; // Base Reg
243 let Inst{16-31} = Addr{15-0}; // Displacement
246 class DForm_1a<bits<6> opcode, dag OOL, dag IOL, string asmstr,
247 InstrItinClass itin, list<dag> pattern>
248 : I<opcode, OOL, IOL, asmstr, itin> {
253 let Pattern = pattern;
261 class DForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr,
262 InstrItinClass itin, list<dag> pattern>
263 : DForm_base<opcode, OOL, IOL, asmstr, itin, pattern> {
265 // Even though ADDICo does not really have an RC bit, provide
266 // the declaration of one here so that isDOT has something to set.
270 class DForm_2_r0<bits<6> opcode, dag OOL, dag IOL, string asmstr,
271 InstrItinClass itin, list<dag> pattern>
272 : I<opcode, OOL, IOL, asmstr, itin> {
276 let Pattern = pattern;
283 class DForm_4<bits<6> opcode, dag OOL, dag IOL, string asmstr,
284 InstrItinClass itin, list<dag> pattern>
285 : I<opcode, OOL, IOL, asmstr, itin> {
290 let Pattern = pattern;
297 class DForm_4_zero<bits<6> opcode, dag OOL, dag IOL, string asmstr,
298 InstrItinClass itin, list<dag> pattern>
299 : DForm_1<opcode, OOL, IOL, asmstr, itin, pattern> {
304 class DForm_4_fixedreg_zero<bits<6> opcode, bits<5> R, dag OOL, dag IOL,
305 string asmstr, InstrItinClass itin,
307 : DForm_4<opcode, OOL, IOL, asmstr, itin, pattern> {
313 class IForm_and_DForm_1<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
314 dag OOL, dag IOL, string asmstr,
315 InstrItinClass itin, list<dag> pattern>
316 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> {
320 let Pattern = pattern;
328 let Inst{43-47} = Addr{20-16}; // Base Reg
329 let Inst{48-63} = Addr{15-0}; // Displacement
332 // This is used to emit BL8+NOP.
333 class IForm_and_DForm_4_zero<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
334 dag OOL, dag IOL, string asmstr,
335 InstrItinClass itin, list<dag> pattern>
336 : IForm_and_DForm_1<opcode1, aa, lk, opcode2,
337 OOL, IOL, asmstr, itin, pattern> {
342 class DForm_5<bits<6> opcode, dag OOL, dag IOL, string asmstr,
344 : I<opcode, OOL, IOL, asmstr, itin> {
353 let Inst{11-15} = RA;
357 class DForm_5_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr,
359 : DForm_5<opcode, OOL, IOL, asmstr, itin> {
363 class DForm_6<bits<6> opcode, dag OOL, dag IOL, string asmstr,
365 : DForm_5<opcode, OOL, IOL, asmstr, itin>;
367 class DForm_6_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr,
369 : DForm_6<opcode, OOL, IOL, asmstr, itin> {
375 class DSForm_1<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr,
376 InstrItinClass itin, list<dag> pattern>
377 : I<opcode, OOL, IOL, asmstr, itin> {
381 let Pattern = pattern;
383 let Inst{6-10} = RST;
384 let Inst{11-15} = DS_RA{18-14}; // Register #
385 let Inst{16-29} = DS_RA{13-0}; // Displacement.
386 let Inst{30-31} = xo;
389 // DQ-Form: [PO T RA DQ TX XO] or [PO S RA DQ SX XO]
390 class DQ_RD6_RS5_DQ12<bits<6> opcode, bits<3> xo, dag OOL, dag IOL,
391 string asmstr, InstrItinClass itin, list<dag> pattern>
392 : I<opcode, OOL, IOL, asmstr, itin> {
396 let Pattern = pattern;
398 let Inst{6-10} = XT{4-0};
399 let Inst{11-15} = DS_RA{16-12}; // Register #
400 let Inst{16-27} = DS_RA{11-0}; // Displacement.
401 let Inst{28} = XT{5};
402 let Inst{29-31} = xo;
406 class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
407 InstrItinClass itin, list<dag> pattern>
408 : I<opcode, OOL, IOL, asmstr, itin> {
413 let Pattern = pattern;
415 bit RC = 0; // set by isDOT
417 let Inst{6-10} = RST;
420 let Inst{21-30} = xo;
424 class XForm_tlb<bits<10> xo, dag OOL, dag IOL, string asmstr,
425 InstrItinClass itin> : XForm_base_r3xo<31, xo, OOL, IOL, asmstr, itin, []> {
429 class XForm_attn<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
431 : I<opcode, OOL, IOL, asmstr, itin> {
432 let Inst{21-30} = xo;
435 // This is the same as XForm_base_r3xo, but the first two operands are swapped
436 // when code is emitted.
437 class XForm_base_r3xo_swapped
438 <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
440 : I<opcode, OOL, IOL, asmstr, itin> {
445 bit RC = 0; // set by isDOT
447 let Inst{6-10} = RST;
450 let Inst{21-30} = xo;
455 class XForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
456 InstrItinClass itin, list<dag> pattern>
457 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>;
459 class XForm_1a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
460 InstrItinClass itin, list<dag> pattern>
461 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
465 class XForm_rs<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
466 InstrItinClass itin, list<dag> pattern>
467 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
472 class XForm_tlbws<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
473 InstrItinClass itin, list<dag> pattern>
474 : I<opcode, OOL, IOL, asmstr, itin> {
479 let Pattern = pattern;
481 let Inst{6-10} = RST;
484 let Inst{21-30} = xo;
488 class XForm_6<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
489 InstrItinClass itin, list<dag> pattern>
490 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
491 let Pattern = pattern;
494 class XForm_8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
495 InstrItinClass itin, list<dag> pattern>
496 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>;
498 class XForm_10<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
499 InstrItinClass itin, list<dag> pattern>
500 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
501 let Pattern = pattern;
504 class XForm_11<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
505 InstrItinClass itin, list<dag> pattern>
506 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
508 let Pattern = pattern;
511 class XForm_16<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
513 : I<opcode, OOL, IOL, asmstr, itin> {
522 let Inst{11-15} = RA;
523 let Inst{16-20} = RB;
524 let Inst{21-30} = xo;
528 class XForm_icbt<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
530 : I<opcode, OOL, IOL, asmstr, itin> {
537 let Inst{11-15} = RA;
538 let Inst{16-20} = RB;
539 let Inst{21-30} = xo;
543 class XForm_sr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
545 : I<opcode, OOL, IOL, asmstr, itin> {
550 let Inst{12-15} = SR;
551 let Inst{21-30} = xo;
554 class XForm_mbar<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
556 : I<opcode, OOL, IOL, asmstr, itin> {
560 let Inst{21-30} = xo;
563 class XForm_srin<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
565 : I<opcode, OOL, IOL, asmstr, itin> {
570 let Inst{16-20} = RB;
571 let Inst{21-30} = xo;
574 class XForm_mtmsr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
576 : I<opcode, OOL, IOL, asmstr, itin> {
582 let Inst{21-30} = xo;
585 class XForm_16_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
587 : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> {
591 class XForm_17<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
593 : I<opcode, OOL, IOL, asmstr, itin> {
600 let Inst{11-15} = FRA;
601 let Inst{16-20} = FRB;
602 let Inst{21-30} = xo;
606 class XForm_17a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
608 : XForm_17<opcode, xo, OOL, IOL, asmstr, itin > {
613 class XForm_18<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
614 InstrItinClass itin, list<dag> pattern>
615 : I<opcode, OOL, IOL, asmstr, itin> {
620 let Pattern = pattern;
622 let Inst{6-10} = FRT;
623 let Inst{11-15} = FRA;
624 let Inst{16-20} = FRB;
625 let Inst{21-30} = xo;
629 class XForm_19<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
630 InstrItinClass itin, list<dag> pattern>
631 : XForm_18<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
635 class XForm_20<bits<6> opcode, bits<6> xo, dag OOL, dag IOL, string asmstr,
636 InstrItinClass itin, list<dag> pattern>
637 : I<opcode, OOL, IOL, asmstr, itin> {
643 let Pattern = pattern;
645 let Inst{6-10} = FRT;
646 let Inst{11-15} = FRA;
647 let Inst{16-20} = FRB;
648 let Inst{21-24} = tttt;
649 let Inst{25-30} = xo;
653 class XForm_24<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
654 InstrItinClass itin, list<dag> pattern>
655 : I<opcode, OOL, IOL, asmstr, itin> {
656 let Pattern = pattern;
660 let Inst{21-30} = xo;
664 class XForm_24_sync<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
665 string asmstr, InstrItinClass itin, list<dag> pattern>
666 : I<opcode, OOL, IOL, asmstr, itin> {
669 let Pattern = pattern;
674 let Inst{21-30} = xo;
678 class XForm_24_eieio<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
679 string asmstr, InstrItinClass itin, list<dag> pattern>
680 : XForm_24_sync<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
684 class XForm_25<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
685 InstrItinClass itin, list<dag> pattern>
686 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
689 class XForm_26<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
690 InstrItinClass itin, list<dag> pattern>
691 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
695 class XForm_28<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
696 InstrItinClass itin, list<dag> pattern>
697 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
700 // This is used for MFFS, MTFSB0, MTFSB1. 42 is arbitrary; this series of
701 // numbers presumably relates to some document, but I haven't found it.
702 class XForm_42<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
703 InstrItinClass itin, list<dag> pattern>
704 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
705 let Pattern = pattern;
707 bit RC = 0; // set by isDOT
709 let Inst{6-10} = RST;
711 let Inst{21-30} = xo;
714 class XForm_43<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
715 InstrItinClass itin, list<dag> pattern>
716 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
717 let Pattern = pattern;
720 bit RC = 0; // set by isDOT
724 let Inst{21-30} = xo;
728 class XForm_0<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
729 InstrItinClass itin, list<dag> pattern>
730 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
736 class XForm_16b<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
737 InstrItinClass itin, list<dag> pattern>
738 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
743 class XForm_htm0<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
744 string asmstr, InstrItinClass itin, list<dag> pattern>
745 : I<opcode, OOL, IOL, asmstr, itin> {
753 let Inst{21-30} = xo;
757 class XForm_htm1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
758 string asmstr, InstrItinClass itin, list<dag> pattern>
759 : I<opcode, OOL, IOL, asmstr, itin> {
766 let Inst{21-30} = xo;
770 class XForm_htm2<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
771 InstrItinClass itin, list<dag> pattern>
772 : I<opcode, OOL, IOL, asmstr, itin> {
775 bit RC = 0; // set by isDOT
780 let Inst{21-30} = xo;
784 class XForm_htm3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
785 InstrItinClass itin, list<dag> pattern>
786 : I<opcode, OOL, IOL, asmstr, itin> {
793 let Inst{21-30} = xo;
797 // [PO RT RA RB XO /]
798 class X_BF3_L1_RS5_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
799 string asmstr, InstrItinClass itin, list<dag> pattern>
800 : I<opcode, OOL, IOL, asmstr, itin> {
806 let Pattern = pattern;
811 let Inst{11-15} = RA;
812 let Inst{16-20} = RB;
813 let Inst{21-30} = xo;
817 // Same as XForm_17 but with GPR's and new naming convention
818 class X_BF3_RS5_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
819 string asmstr, InstrItinClass itin, list<dag> pattern>
820 : I<opcode, OOL, IOL, asmstr, itin> {
825 let Pattern = pattern;
829 let Inst{11-15} = RA;
830 let Inst{16-20} = RB;
831 let Inst{21-30} = xo;
835 // e.g. [PO VRT XO VRB XO /] or [PO VRT XO VRB XO RO]
836 class X_RD5_XO5_RS5<bits<6> opcode, bits<5> xo2, bits<10> xo, dag OOL, dag IOL,
837 string asmstr, InstrItinClass itin, list<dag> pattern>
838 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
842 class X_BF3_DCMX7_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
843 string asmstr, InstrItinClass itin, list<dag> pattern>
844 : I<opcode, OOL, IOL, asmstr, itin> {
849 let Pattern = pattern;
852 let Inst{9-15} = DCMX;
853 let Inst{16-20} = VB;
854 let Inst{21-30} = xo;
858 class X_RD6_IMM8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
859 string asmstr, InstrItinClass itin, list<dag> pattern>
860 : I<opcode, OOL, IOL, asmstr, itin> {
864 let Pattern = pattern;
866 let Inst{6-10} = XT{4-0};
868 let Inst{13-20} = IMM8;
869 let Inst{21-30} = xo;
870 let Inst{31} = XT{5};
873 // XForm_base_r3xo for instructions such as P9 atomics where we don't want
874 // to specify an SDAG pattern for matching.
875 class X_RD5_RS5_IM5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
876 string asmstr, InstrItinClass itin>
877 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, []> {
880 class X_BF3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
882 : XForm_17<opcode, xo, OOL, IOL, asmstr, itin> {
887 // [PO /// L RA RB XO /]
888 class X_L1_RS5_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
889 string asmstr, InstrItinClass itin, list<dag> pattern>
890 : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> {
892 let Pattern = pattern;
899 class XX1Form<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
900 InstrItinClass itin, list<dag> pattern>
901 : I<opcode, OOL, IOL, asmstr, itin> {
906 let Pattern = pattern;
908 let Inst{6-10} = XT{4-0};
911 let Inst{21-30} = xo;
912 let Inst{31} = XT{5};
915 class XX1_RS6_RD5_XO<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
916 string asmstr, InstrItinClass itin, list<dag> pattern>
917 : XX1Form<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
921 class XX2Form<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
922 InstrItinClass itin, list<dag> pattern>
923 : I<opcode, OOL, IOL, asmstr, itin> {
927 let Pattern = pattern;
929 let Inst{6-10} = XT{4-0};
931 let Inst{16-20} = XB{4-0};
932 let Inst{21-29} = xo;
933 let Inst{30} = XB{5};
934 let Inst{31} = XT{5};
937 class XX2Form_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
938 InstrItinClass itin, list<dag> pattern>
939 : I<opcode, OOL, IOL, asmstr, itin> {
943 let Pattern = pattern;
947 let Inst{16-20} = XB{4-0};
948 let Inst{21-29} = xo;
949 let Inst{30} = XB{5};
953 class XX2Form_2<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
954 InstrItinClass itin, list<dag> pattern>
955 : I<opcode, OOL, IOL, asmstr, itin> {
960 let Pattern = pattern;
962 let Inst{6-10} = XT{4-0};
965 let Inst{16-20} = XB{4-0};
966 let Inst{21-29} = xo;
967 let Inst{30} = XB{5};
968 let Inst{31} = XT{5};
971 class XX2_RD6_UIM5_RS6<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
972 string asmstr, InstrItinClass itin, list<dag> pattern>
973 : I<opcode, OOL, IOL, asmstr, itin> {
978 let Pattern = pattern;
980 let Inst{6-10} = XT{4-0};
981 let Inst{11-15} = UIM5;
982 let Inst{16-20} = XB{4-0};
983 let Inst{21-29} = xo;
984 let Inst{30} = XB{5};
985 let Inst{31} = XT{5};
988 // [PO T XO B XO BX /]
989 class XX2_RD5_XO5_RS6<bits<6> opcode, bits<5> xo2, bits<9> xo, dag OOL, dag IOL,
990 string asmstr, InstrItinClass itin, list<dag> pattern>
991 : I<opcode, OOL, IOL, asmstr, itin> {
995 let Pattern = pattern;
998 let Inst{11-15} = xo2;
999 let Inst{16-20} = XB{4-0};
1000 let Inst{21-29} = xo;
1001 let Inst{30} = XB{5};
1005 // [PO T XO B XO BX TX]
1006 class XX2_RD6_XO5_RS6<bits<6> opcode, bits<5> xo2, bits<9> xo, dag OOL, dag IOL,
1007 string asmstr, InstrItinClass itin, list<dag> pattern>
1008 : I<opcode, OOL, IOL, asmstr, itin> {
1012 let Pattern = pattern;
1014 let Inst{6-10} = XT{4-0};
1015 let Inst{11-15} = xo2;
1016 let Inst{16-20} = XB{4-0};
1017 let Inst{21-29} = xo;
1018 let Inst{30} = XB{5};
1019 let Inst{31} = XT{5};
1022 class XX2_BF3_DCMX7_RS6<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
1023 string asmstr, InstrItinClass itin, list<dag> pattern>
1024 : I<opcode, OOL, IOL, asmstr, itin> {
1029 let Pattern = pattern;
1032 let Inst{9-15} = DCMX;
1033 let Inst{16-20} = XB{4-0};
1034 let Inst{21-29} = xo;
1035 let Inst{30} = XB{5};
1039 class XX2_RD6_DCMX7_RS6<bits<6> opcode, bits<4> xo1, bits<3> xo2,
1040 dag OOL, dag IOL, string asmstr, InstrItinClass itin,
1042 : I<opcode, OOL, IOL, asmstr, itin> {
1047 let Pattern = pattern;
1049 let Inst{6-10} = XT{4-0};
1050 let Inst{11-15} = DCMX{4-0};
1051 let Inst{16-20} = XB{4-0};
1052 let Inst{21-24} = xo1;
1053 let Inst{25} = DCMX{5};
1054 let Inst{26-28} = xo2;
1055 let Inst{29} = DCMX{6};
1056 let Inst{30} = XB{5};
1057 let Inst{31} = XT{5};
1060 class XX3Form<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
1061 InstrItinClass itin, list<dag> pattern>
1062 : I<opcode, OOL, IOL, asmstr, itin> {
1067 let Pattern = pattern;
1069 let Inst{6-10} = XT{4-0};
1070 let Inst{11-15} = XA{4-0};
1071 let Inst{16-20} = XB{4-0};
1072 let Inst{21-28} = xo;
1073 let Inst{29} = XA{5};
1074 let Inst{30} = XB{5};
1075 let Inst{31} = XT{5};
1078 class XX3Form_Zero<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
1079 InstrItinClass itin, list<dag> pattern>
1080 : XX3Form<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
1085 class XX3Form_SetZero<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
1086 InstrItinClass itin, list<dag> pattern>
1087 : XX3Form<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
1092 class XX3Form_1<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
1093 InstrItinClass itin, list<dag> pattern>
1094 : I<opcode, OOL, IOL, asmstr, itin> {
1099 let Pattern = pattern;
1103 let Inst{11-15} = XA{4-0};
1104 let Inst{16-20} = XB{4-0};
1105 let Inst{21-28} = xo;
1106 let Inst{29} = XA{5};
1107 let Inst{30} = XB{5};
1111 class XX3Form_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
1112 InstrItinClass itin, list<dag> pattern>
1113 : I<opcode, OOL, IOL, asmstr, itin> {
1119 let Pattern = pattern;
1121 let Inst{6-10} = XT{4-0};
1122 let Inst{11-15} = XA{4-0};
1123 let Inst{16-20} = XB{4-0};
1125 let Inst{22-23} = D;
1126 let Inst{24-28} = xo;
1127 let Inst{29} = XA{5};
1128 let Inst{30} = XB{5};
1129 let Inst{31} = XT{5};
1132 class XX3Form_Rc<bits<6> opcode, bits<7> xo, dag OOL, dag IOL, string asmstr,
1133 InstrItinClass itin, list<dag> pattern>
1134 : I<opcode, OOL, IOL, asmstr, itin> {
1139 let Pattern = pattern;
1141 bit RC = 0; // set by isDOT
1143 let Inst{6-10} = XT{4-0};
1144 let Inst{11-15} = XA{4-0};
1145 let Inst{16-20} = XB{4-0};
1147 let Inst{22-28} = xo;
1148 let Inst{29} = XA{5};
1149 let Inst{30} = XB{5};
1150 let Inst{31} = XT{5};
1153 class XX4Form<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr,
1154 InstrItinClass itin, list<dag> pattern>
1155 : I<opcode, OOL, IOL, asmstr, itin> {
1161 let Pattern = pattern;
1163 let Inst{6-10} = XT{4-0};
1164 let Inst{11-15} = XA{4-0};
1165 let Inst{16-20} = XB{4-0};
1166 let Inst{21-25} = XC{4-0};
1167 let Inst{26-27} = xo;
1168 let Inst{28} = XC{5};
1169 let Inst{29} = XA{5};
1170 let Inst{30} = XB{5};
1171 let Inst{31} = XT{5};
1174 // DCB_Form - Form X instruction, used for dcb* instructions.
1175 class DCB_Form<bits<10> xo, bits<5> immfield, dag OOL, dag IOL, string asmstr,
1176 InstrItinClass itin, list<dag> pattern>
1177 : I<31, OOL, IOL, asmstr, itin> {
1181 let Pattern = pattern;
1183 let Inst{6-10} = immfield;
1184 let Inst{11-15} = A;
1185 let Inst{16-20} = B;
1186 let Inst{21-30} = xo;
1190 class DCB_Form_hint<bits<10> xo, dag OOL, dag IOL, string asmstr,
1191 InstrItinClass itin, list<dag> pattern>
1192 : I<31, OOL, IOL, asmstr, itin> {
1197 let Pattern = pattern;
1199 let Inst{6-10} = TH;
1200 let Inst{11-15} = A;
1201 let Inst{16-20} = B;
1202 let Inst{21-30} = xo;
1206 // DSS_Form - Form X instruction, used for altivec dss* instructions.
1207 class DSS_Form<bits<1> T, bits<10> xo, dag OOL, dag IOL, string asmstr,
1208 InstrItinClass itin, list<dag> pattern>
1209 : I<31, OOL, IOL, asmstr, itin> {
1214 let Pattern = pattern;
1218 let Inst{9-10} = STRM;
1219 let Inst{11-15} = A;
1220 let Inst{16-20} = B;
1221 let Inst{21-30} = xo;
1226 class XLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1227 InstrItinClass itin, list<dag> pattern>
1228 : I<opcode, OOL, IOL, asmstr, itin> {
1233 let Pattern = pattern;
1235 let Inst{6-10} = CRD;
1236 let Inst{11-15} = CRA;
1237 let Inst{16-20} = CRB;
1238 let Inst{21-30} = xo;
1242 class XLForm_1_np<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1243 InstrItinClass itin, list<dag> pattern>
1244 : XLForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
1250 class XLForm_1_gen<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1251 InstrItinClass itin, list<dag> pattern>
1252 : XLForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
1261 class XLForm_1_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1262 InstrItinClass itin, list<dag> pattern>
1263 : I<opcode, OOL, IOL, asmstr, itin> {
1266 let Pattern = pattern;
1268 let Inst{6-10} = CRD;
1269 let Inst{11-15} = CRD;
1270 let Inst{16-20} = CRD;
1271 let Inst{21-30} = xo;
1275 class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, dag OOL, dag IOL, string asmstr,
1276 InstrItinClass itin, list<dag> pattern>
1277 : I<opcode, OOL, IOL, asmstr, itin> {
1282 let Pattern = pattern;
1284 let Inst{6-10} = BO;
1285 let Inst{11-15} = BI;
1286 let Inst{16-18} = 0;
1287 let Inst{19-20} = BH;
1288 let Inst{21-30} = xo;
1292 class XLForm_2_br<bits<6> opcode, bits<10> xo, bit lk,
1293 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
1294 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
1295 bits<7> BIBO; // 2 bits of BI and 5 bits of BO.
1299 let BI{0-1} = BIBO{5-6};
1300 let BI{2-4} = CR{0-2};
1304 class XLForm_2_br2<bits<6> opcode, bits<10> xo, bits<5> bo, bit lk,
1305 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
1306 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
1311 class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo, bits<5> bi, bit lk,
1312 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
1313 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
1319 class XLForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1320 InstrItinClass itin>
1321 : I<opcode, OOL, IOL, asmstr, itin> {
1327 let Inst{11-13} = BFA;
1328 let Inst{14-15} = 0;
1329 let Inst{16-20} = 0;
1330 let Inst{21-30} = xo;
1334 class XLForm_4<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1335 InstrItinClass itin>
1336 : I<opcode, OOL, IOL, asmstr, itin> {
1345 let Inst{11-14} = 0;
1347 let Inst{16-19} = U;
1349 let Inst{21-30} = xo;
1353 class XLForm_S<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1354 InstrItinClass itin, list<dag> pattern>
1355 : I<opcode, OOL, IOL, asmstr, itin> {
1358 let Pattern = pattern;
1362 let Inst{21-30} = xo;
1366 class XLForm_2_and_DSForm_1<bits<6> opcode1, bits<10> xo1, bit lk,
1367 bits<6> opcode2, bits<2> xo2,
1368 dag OOL, dag IOL, string asmstr,
1369 InstrItinClass itin, list<dag> pattern>
1370 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> {
1378 let Pattern = pattern;
1380 let Inst{6-10} = BO;
1381 let Inst{11-15} = BI;
1382 let Inst{16-18} = 0;
1383 let Inst{19-20} = BH;
1384 let Inst{21-30} = xo1;
1387 let Inst{38-42} = RST;
1388 let Inst{43-47} = DS_RA{18-14}; // Register #
1389 let Inst{48-61} = DS_RA{13-0}; // Displacement.
1390 let Inst{62-63} = xo2;
1393 class XLForm_2_ext_and_DSForm_1<bits<6> opcode1, bits<10> xo1,
1394 bits<5> bo, bits<5> bi, bit lk,
1395 bits<6> opcode2, bits<2> xo2,
1396 dag OOL, dag IOL, string asmstr,
1397 InstrItinClass itin, list<dag> pattern>
1398 : XLForm_2_and_DSForm_1<opcode1, xo1, lk, opcode2, xo2,
1399 OOL, IOL, asmstr, itin, pattern> {
1406 class XFXForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1407 InstrItinClass itin>
1408 : I<opcode, OOL, IOL, asmstr, itin> {
1412 let Inst{6-10} = RT;
1413 let Inst{11} = SPR{4};
1414 let Inst{12} = SPR{3};
1415 let Inst{13} = SPR{2};
1416 let Inst{14} = SPR{1};
1417 let Inst{15} = SPR{0};
1418 let Inst{16} = SPR{9};
1419 let Inst{17} = SPR{8};
1420 let Inst{18} = SPR{7};
1421 let Inst{19} = SPR{6};
1422 let Inst{20} = SPR{5};
1423 let Inst{21-30} = xo;
1427 class XFXForm_1_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
1428 dag OOL, dag IOL, string asmstr, InstrItinClass itin>
1429 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin> {
1433 class XFXForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1434 InstrItinClass itin>
1435 : I<opcode, OOL, IOL, asmstr, itin> {
1438 let Inst{6-10} = RT;
1439 let Inst{11-20} = 0;
1440 let Inst{21-30} = xo;
1444 class XFXForm_3p<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1445 InstrItinClass itin, list<dag> pattern>
1446 : I<opcode, OOL, IOL, asmstr, itin> {
1449 let Pattern = pattern;
1451 let Inst{6-10} = RT;
1452 let Inst{11-20} = Entry;
1453 let Inst{21-30} = xo;
1457 class XFXForm_5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1458 InstrItinClass itin>
1459 : I<opcode, OOL, IOL, asmstr, itin> {
1463 let Inst{6-10} = rS;
1465 let Inst{12-19} = FXM;
1467 let Inst{21-30} = xo;
1471 class XFXForm_5a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1472 InstrItinClass itin>
1473 : I<opcode, OOL, IOL, asmstr, itin> {
1477 let Inst{6-10} = ST;
1479 let Inst{12-19} = FXM;
1481 let Inst{21-30} = xo;
1485 class XFXForm_7<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1486 InstrItinClass itin>
1487 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin>;
1489 class XFXForm_7_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
1490 dag OOL, dag IOL, string asmstr, InstrItinClass itin>
1491 : XFXForm_7<opcode, xo, OOL, IOL, asmstr, itin> {
1496 // This is probably 1.7.9, but I don't have the reference that uses this
1497 // numbering scheme...
1498 class XFLForm<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1499 InstrItinClass itin, list<dag>pattern>
1500 : I<opcode, OOL, IOL, asmstr, itin> {
1504 bit RC = 0; // set by isDOT
1505 let Pattern = pattern;
1508 let Inst{7-14} = FM;
1510 let Inst{16-20} = rT;
1511 let Inst{21-30} = xo;
1515 class XFLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1516 InstrItinClass itin, list<dag>pattern>
1517 : I<opcode, OOL, IOL, asmstr, itin> {
1523 bit RC = 0; // set by isDOT
1524 let Pattern = pattern;
1527 let Inst{7-14} = FLM;
1529 let Inst{16-20} = FRB;
1530 let Inst{21-30} = xo;
1534 // 1.7.10 XS-Form - SRADI.
1535 class XSForm_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
1536 InstrItinClass itin, list<dag> pattern>
1537 : I<opcode, OOL, IOL, asmstr, itin> {
1542 bit RC = 0; // set by isDOT
1543 let Pattern = pattern;
1545 let Inst{6-10} = RS;
1546 let Inst{11-15} = A;
1547 let Inst{16-20} = SH{4,3,2,1,0};
1548 let Inst{21-29} = xo;
1549 let Inst{30} = SH{5};
1554 class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, string asmstr,
1555 InstrItinClass itin, list<dag> pattern>
1556 : I<opcode, OOL, IOL, asmstr, itin> {
1561 let Pattern = pattern;
1563 bit RC = 0; // set by isDOT
1565 let Inst{6-10} = RT;
1566 let Inst{11-15} = RA;
1567 let Inst{16-20} = RB;
1569 let Inst{22-30} = xo;
1573 class XOForm_3<bits<6> opcode, bits<9> xo, bit oe,
1574 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
1575 : XOForm_1<opcode, xo, oe, OOL, IOL, asmstr, itin, pattern> {
1580 class AForm_1<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
1581 InstrItinClass itin, list<dag> pattern>
1582 : I<opcode, OOL, IOL, asmstr, itin> {
1588 let Pattern = pattern;
1590 bit RC = 0; // set by isDOT
1592 let Inst{6-10} = FRT;
1593 let Inst{11-15} = FRA;
1594 let Inst{16-20} = FRB;
1595 let Inst{21-25} = FRC;
1596 let Inst{26-30} = xo;
1600 class AForm_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
1601 InstrItinClass itin, list<dag> pattern>
1602 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
1606 class AForm_3<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
1607 InstrItinClass itin, list<dag> pattern>
1608 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
1612 class AForm_4<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
1613 InstrItinClass itin, list<dag> pattern>
1614 : I<opcode, OOL, IOL, asmstr, itin> {
1620 let Pattern = pattern;
1622 let Inst{6-10} = RT;
1623 let Inst{11-15} = RA;
1624 let Inst{16-20} = RB;
1625 let Inst{21-25} = COND;
1626 let Inst{26-30} = xo;
1631 class AForm_4a<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
1632 InstrItinClass itin, list<dag> pattern>
1633 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
1639 class MForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr,
1640 InstrItinClass itin, list<dag> pattern>
1641 : I<opcode, OOL, IOL, asmstr, itin> {
1648 let Pattern = pattern;
1650 bit RC = 0; // set by isDOT
1652 let Inst{6-10} = RS;
1653 let Inst{11-15} = RA;
1654 let Inst{16-20} = RB;
1655 let Inst{21-25} = MB;
1656 let Inst{26-30} = ME;
1660 class MForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr,
1661 InstrItinClass itin, list<dag> pattern>
1662 : MForm_1<opcode, OOL, IOL, asmstr, itin, pattern> {
1666 class MDForm_1<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, string asmstr,
1667 InstrItinClass itin, list<dag> pattern>
1668 : I<opcode, OOL, IOL, asmstr, itin> {
1674 let Pattern = pattern;
1676 bit RC = 0; // set by isDOT
1678 let Inst{6-10} = RS;
1679 let Inst{11-15} = RA;
1680 let Inst{16-20} = SH{4,3,2,1,0};
1681 let Inst{21-26} = MBE{4,3,2,1,0,5};
1682 let Inst{27-29} = xo;
1683 let Inst{30} = SH{5};
1687 class MDSForm_1<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, string asmstr,
1688 InstrItinClass itin, list<dag> pattern>
1689 : I<opcode, OOL, IOL, asmstr, itin> {
1695 let Pattern = pattern;
1697 bit RC = 0; // set by isDOT
1699 let Inst{6-10} = RS;
1700 let Inst{11-15} = RA;
1701 let Inst{16-20} = RB;
1702 let Inst{21-26} = MBE{4,3,2,1,0,5};
1703 let Inst{27-30} = xo;
1710 // VAForm_1 - DACB ordering.
1711 class VAForm_1<bits<6> xo, dag OOL, dag IOL, string asmstr,
1712 InstrItinClass itin, list<dag> pattern>
1713 : I<4, OOL, IOL, asmstr, itin> {
1719 let Pattern = pattern;
1721 let Inst{6-10} = VD;
1722 let Inst{11-15} = VA;
1723 let Inst{16-20} = VB;
1724 let Inst{21-25} = VC;
1725 let Inst{26-31} = xo;
1728 // VAForm_1a - DABC ordering.
1729 class VAForm_1a<bits<6> xo, dag OOL, dag IOL, string asmstr,
1730 InstrItinClass itin, list<dag> pattern>
1731 : I<4, OOL, IOL, asmstr, itin> {
1737 let Pattern = pattern;
1739 let Inst{6-10} = VD;
1740 let Inst{11-15} = VA;
1741 let Inst{16-20} = VB;
1742 let Inst{21-25} = VC;
1743 let Inst{26-31} = xo;
1746 class VAForm_2<bits<6> xo, dag OOL, dag IOL, string asmstr,
1747 InstrItinClass itin, list<dag> pattern>
1748 : I<4, OOL, IOL, asmstr, itin> {
1754 let Pattern = pattern;
1756 let Inst{6-10} = VD;
1757 let Inst{11-15} = VA;
1758 let Inst{16-20} = VB;
1760 let Inst{22-25} = SH;
1761 let Inst{26-31} = xo;
1765 class VXForm_1<bits<11> xo, dag OOL, dag IOL, string asmstr,
1766 InstrItinClass itin, list<dag> pattern>
1767 : I<4, OOL, IOL, asmstr, itin> {
1772 let Pattern = pattern;
1774 let Inst{6-10} = VD;
1775 let Inst{11-15} = VA;
1776 let Inst{16-20} = VB;
1777 let Inst{21-31} = xo;
1780 class VXForm_setzero<bits<11> xo, dag OOL, dag IOL, string asmstr,
1781 InstrItinClass itin, list<dag> pattern>
1782 : VXForm_1<xo, OOL, IOL, asmstr, itin, pattern> {
1788 class VXForm_2<bits<11> xo, dag OOL, dag IOL, string asmstr,
1789 InstrItinClass itin, list<dag> pattern>
1790 : I<4, OOL, IOL, asmstr, itin> {
1794 let Pattern = pattern;
1796 let Inst{6-10} = VD;
1797 let Inst{11-15} = 0;
1798 let Inst{16-20} = VB;
1799 let Inst{21-31} = xo;
1802 class VXForm_3<bits<11> xo, dag OOL, dag IOL, string asmstr,
1803 InstrItinClass itin, list<dag> pattern>
1804 : I<4, OOL, IOL, asmstr, itin> {
1808 let Pattern = pattern;
1810 let Inst{6-10} = VD;
1811 let Inst{11-15} = IMM;
1812 let Inst{16-20} = 0;
1813 let Inst{21-31} = xo;
1816 /// VXForm_4 - VX instructions with "VD,0,0" register fields, like mfvscr.
1817 class VXForm_4<bits<11> xo, dag OOL, dag IOL, string asmstr,
1818 InstrItinClass itin, list<dag> pattern>
1819 : I<4, OOL, IOL, asmstr, itin> {
1822 let Pattern = pattern;
1824 let Inst{6-10} = VD;
1825 let Inst{11-15} = 0;
1826 let Inst{16-20} = 0;
1827 let Inst{21-31} = xo;
1830 /// VXForm_5 - VX instructions with "0,0,VB" register fields, like mtvscr.
1831 class VXForm_5<bits<11> xo, dag OOL, dag IOL, string asmstr,
1832 InstrItinClass itin, list<dag> pattern>
1833 : I<4, OOL, IOL, asmstr, itin> {
1836 let Pattern = pattern;
1839 let Inst{11-15} = 0;
1840 let Inst{16-20} = VB;
1841 let Inst{21-31} = xo;
1844 // e.g. [PO VRT EO VRB XO]
1845 class VXForm_RD5_XO5_RS5<bits<11> xo, bits<5> eo, dag OOL, dag IOL,
1846 string asmstr, InstrItinClass itin, list<dag> pattern>
1847 : I<4, OOL, IOL, asmstr, itin> {
1851 let Pattern = pattern;
1853 let Inst{6-10} = RD;
1854 let Inst{11-15} = eo;
1855 let Inst{16-20} = VB;
1856 let Inst{21-31} = xo;
1859 /// VXForm_CR - VX crypto instructions with "VRT, VRA, ST, SIX"
1860 class VXForm_CR<bits<11> xo, dag OOL, dag IOL, string asmstr,
1861 InstrItinClass itin, list<dag> pattern>
1862 : I<4, OOL, IOL, asmstr, itin> {
1868 let Pattern = pattern;
1870 let Inst{6-10} = VD;
1871 let Inst{11-15} = VA;
1873 let Inst{17-20} = SIX;
1874 let Inst{21-31} = xo;
1877 /// VXForm_BX - VX crypto instructions with "VRT, VRA, 0 - like vsbox"
1878 class VXForm_BX<bits<11> xo, dag OOL, dag IOL, string asmstr,
1879 InstrItinClass itin, list<dag> pattern>
1880 : I<4, OOL, IOL, asmstr, itin> {
1884 let Pattern = pattern;
1886 let Inst{6-10} = VD;
1887 let Inst{11-15} = VA;
1888 let Inst{16-20} = 0;
1889 let Inst{21-31} = xo;
1893 class VXRForm_1<bits<10> xo, dag OOL, dag IOL, string asmstr,
1894 InstrItinClass itin, list<dag> pattern>
1895 : I<4, OOL, IOL, asmstr, itin> {
1901 let Pattern = pattern;
1903 let Inst{6-10} = VD;
1904 let Inst{11-15} = VA;
1905 let Inst{16-20} = VB;
1907 let Inst{22-31} = xo;
1910 // VX-Form: [PO VRT EO VRB 1 PS XO]
1911 class VX_RD5_EO5_RS5_PS1_XO9<bits<5> eo, bits<9> xo,
1912 dag OOL, dag IOL, string asmstr,
1913 InstrItinClass itin, list<dag> pattern>
1914 : I<4, OOL, IOL, asmstr, itin> {
1919 let Pattern = pattern;
1921 let Inst{6-10} = VD;
1922 let Inst{11-15} = eo;
1923 let Inst{16-20} = VB;
1926 let Inst{23-31} = xo;
1929 // VX-Form: [PO VRT VRA VRB 1 PS XO] or [PO VRT VRA VRB 1 / XO]
1930 class VX_RD5_RSp5_PS1_XO9<bits<9> xo, dag OOL, dag IOL, string asmstr,
1931 InstrItinClass itin, list<dag> pattern>
1932 : I<4, OOL, IOL, asmstr, itin> {
1938 let Pattern = pattern;
1940 let Inst{6-10} = VD;
1941 let Inst{11-15} = VA;
1942 let Inst{16-20} = VB;
1945 let Inst{23-31} = xo;
1948 // Z23-Form (used by QPX)
1949 class Z23Form_1<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
1950 InstrItinClass itin, list<dag> pattern>
1951 : I<opcode, OOL, IOL, asmstr, itin> {
1957 let Pattern = pattern;
1959 bit RC = 0; // set by isDOT
1961 let Inst{6-10} = FRT;
1962 let Inst{11-15} = FRA;
1963 let Inst{16-20} = FRB;
1964 let Inst{21-22} = idx;
1965 let Inst{23-30} = xo;
1969 class Z23Form_2<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
1970 InstrItinClass itin, list<dag> pattern>
1971 : Z23Form_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
1975 class Z23Form_3<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
1976 InstrItinClass itin, list<dag> pattern>
1977 : I<opcode, OOL, IOL, asmstr, itin> {
1981 let Pattern = pattern;
1983 bit RC = 0; // set by isDOT
1985 let Inst{6-10} = FRT;
1986 let Inst{11-22} = idx;
1987 let Inst{23-30} = xo;
1991 //===----------------------------------------------------------------------===//
1992 class Pseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern>
1993 : I<0, OOL, IOL, asmstr, NoItinerary> {
1994 let isCodeGenOnly = 1;
1996 let Pattern = pattern;