1 //===-- PPCInstrInfo.cpp - PowerPC Instruction Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCInstrInfo.h"
15 #include "MCTargetDesc/PPCPredicates.h"
17 #include "PPCHazardRecognizers.h"
18 #include "PPCInstrBuilder.h"
19 #include "PPCMachineFunctionInfo.h"
20 #include "PPCTargetMachine.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunctionPass.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineMemOperand.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/CodeGen/PseudoSourceValue.h"
30 #include "llvm/CodeGen/ScheduleDAG.h"
31 #include "llvm/CodeGen/SlotIndexes.h"
32 #include "llvm/CodeGen/StackMaps.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/MC/MCInst.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/Debug.h"
37 #include "llvm/Support/ErrorHandling.h"
38 #include "llvm/Support/TargetRegistry.h"
39 #include "llvm/Support/raw_ostream.h"
43 #define DEBUG_TYPE "ppc-instr-info"
45 #define GET_INSTRMAP_INFO
46 #define GET_INSTRINFO_CTOR_DTOR
47 #include "PPCGenInstrInfo.inc"
50 opt<bool> DisableCTRLoopAnal("disable-ppc-ctrloop-analysis", cl::Hidden,
51 cl::desc("Disable analysis for CTR loops"));
53 static cl::opt<bool> DisableCmpOpt("disable-ppc-cmp-opt",
54 cl::desc("Disable compare instruction optimization"), cl::Hidden);
56 static cl::opt<bool> VSXSelfCopyCrash("crash-on-ppc-vsx-self-copy",
57 cl::desc("Causes the backend to crash instead of generating a nop VSX copy"),
61 UseOldLatencyCalc("ppc-old-latency-calc", cl::Hidden,
62 cl::desc("Use the old (incorrect) instruction latency calculation"));
64 // Pin the vtable to this file.
65 void PPCInstrInfo::anchor() {}
67 PPCInstrInfo::PPCInstrInfo(PPCSubtarget &STI)
68 : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
69 Subtarget(STI), RI(STI.getTargetMachine()) {}
71 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
72 /// this target when scheduling the DAG.
73 ScheduleHazardRecognizer *
74 PPCInstrInfo::CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
75 const ScheduleDAG *DAG) const {
77 static_cast<const PPCSubtarget *>(STI)->getDarwinDirective();
78 if (Directive == PPC::DIR_440 || Directive == PPC::DIR_A2 ||
79 Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500) {
80 const InstrItineraryData *II =
81 static_cast<const PPCSubtarget *>(STI)->getInstrItineraryData();
82 return new ScoreboardHazardRecognizer(II, DAG);
85 return TargetInstrInfo::CreateTargetHazardRecognizer(STI, DAG);
88 /// CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer
89 /// to use for this target when scheduling the DAG.
90 ScheduleHazardRecognizer *
91 PPCInstrInfo::CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
92 const ScheduleDAG *DAG) const {
94 DAG->MF.getSubtarget<PPCSubtarget>().getDarwinDirective();
96 // FIXME: Leaving this as-is until we have POWER9 scheduling info
97 if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8)
98 return new PPCDispatchGroupSBHazardRecognizer(II, DAG);
100 // Most subtargets use a PPC970 recognizer.
101 if (Directive != PPC::DIR_440 && Directive != PPC::DIR_A2 &&
102 Directive != PPC::DIR_E500mc && Directive != PPC::DIR_E5500) {
103 assert(DAG->TII && "No InstrInfo?");
105 return new PPCHazardRecognizer970(*DAG);
108 return new ScoreboardHazardRecognizer(II, DAG);
111 unsigned PPCInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
112 const MachineInstr &MI,
113 unsigned *PredCost) const {
114 if (!ItinData || UseOldLatencyCalc)
115 return PPCGenInstrInfo::getInstrLatency(ItinData, MI, PredCost);
117 // The default implementation of getInstrLatency calls getStageLatency, but
118 // getStageLatency does not do the right thing for us. While we have
119 // itinerary, most cores are fully pipelined, and so the itineraries only
120 // express the first part of the pipeline, not every stage. Instead, we need
121 // to use the listed output operand cycle number (using operand 0 here, which
124 unsigned Latency = 1;
125 unsigned DefClass = MI.getDesc().getSchedClass();
126 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
127 const MachineOperand &MO = MI.getOperand(i);
128 if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
131 int Cycle = ItinData->getOperandCycle(DefClass, i);
135 Latency = std::max(Latency, (unsigned) Cycle);
141 int PPCInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
142 const MachineInstr &DefMI, unsigned DefIdx,
143 const MachineInstr &UseMI,
144 unsigned UseIdx) const {
145 int Latency = PPCGenInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx,
148 if (!DefMI.getParent())
151 const MachineOperand &DefMO = DefMI.getOperand(DefIdx);
152 unsigned Reg = DefMO.getReg();
155 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
156 const MachineRegisterInfo *MRI =
157 &DefMI.getParent()->getParent()->getRegInfo();
158 IsRegCR = MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRRCRegClass) ||
159 MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRBITRCRegClass);
161 IsRegCR = PPC::CRRCRegClass.contains(Reg) ||
162 PPC::CRBITRCRegClass.contains(Reg);
165 if (UseMI.isBranch() && IsRegCR) {
167 Latency = getInstrLatency(ItinData, DefMI);
169 // On some cores, there is an additional delay between writing to a condition
170 // register, and using it from a branch.
171 unsigned Directive = Subtarget.getDarwinDirective();
185 // FIXME: Is this needed for POWER9?
194 // This function does not list all associative and commutative operations, but
195 // only those worth feeding through the machine combiner in an attempt to
196 // reduce the critical path. Mostly, this means floating-point operations,
197 // because they have high latencies (compared to other operations, such and
198 // and/or, which are also associative and commutative, but have low latencies).
199 bool PPCInstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst) const {
200 switch (Inst.getOpcode()) {
233 bool PPCInstrInfo::getMachineCombinerPatterns(
235 SmallVectorImpl<MachineCombinerPattern> &Patterns) const {
236 // Using the machine combiner in this way is potentially expensive, so
237 // restrict to when aggressive optimizations are desired.
238 if (Subtarget.getTargetMachine().getOptLevel() != CodeGenOpt::Aggressive)
241 // FP reassociation is only legal when we don't need strict IEEE semantics.
242 if (!Root.getParent()->getParent()->getTarget().Options.UnsafeFPMath)
245 return TargetInstrInfo::getMachineCombinerPatterns(Root, Patterns);
248 // Detect 32 -> 64-bit extensions where we may reuse the low sub-register.
249 bool PPCInstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
250 unsigned &SrcReg, unsigned &DstReg,
251 unsigned &SubIdx) const {
252 switch (MI.getOpcode()) {
253 default: return false;
255 case PPC::EXTSW_32_64:
256 SrcReg = MI.getOperand(1).getReg();
257 DstReg = MI.getOperand(0).getReg();
258 SubIdx = PPC::sub_32;
263 unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
264 int &FrameIndex) const {
265 // Note: This list must be kept consistent with LoadRegFromStackSlot.
266 switch (MI.getOpcode()) {
272 case PPC::RESTORE_CR:
273 case PPC::RESTORE_CRBIT:
280 case PPC::RESTORE_VRSAVE:
281 // Check for the operands added by addFrameReference (the immediate is the
282 // offset which defaults to 0).
283 if (MI.getOperand(1).isImm() && !MI.getOperand(1).getImm() &&
284 MI.getOperand(2).isFI()) {
285 FrameIndex = MI.getOperand(2).getIndex();
286 return MI.getOperand(0).getReg();
293 unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
294 int &FrameIndex) const {
295 // Note: This list must be kept consistent with StoreRegToStackSlot.
296 switch (MI.getOpcode()) {
303 case PPC::SPILL_CRBIT:
310 case PPC::SPILL_VRSAVE:
311 // Check for the operands added by addFrameReference (the immediate is the
312 // offset which defaults to 0).
313 if (MI.getOperand(1).isImm() && !MI.getOperand(1).getImm() &&
314 MI.getOperand(2).isFI()) {
315 FrameIndex = MI.getOperand(2).getIndex();
316 return MI.getOperand(0).getReg();
323 MachineInstr *PPCInstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,
325 unsigned OpIdx2) const {
326 MachineFunction &MF = *MI.getParent()->getParent();
328 // Normal instructions can be commuted the obvious way.
329 if (MI.getOpcode() != PPC::RLWIMI && MI.getOpcode() != PPC::RLWIMIo)
330 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
331 // Note that RLWIMI can be commuted as a 32-bit instruction, but not as a
332 // 64-bit instruction (so we don't handle PPC::RLWIMI8 here), because
333 // changing the relative order of the mask operands might change what happens
334 // to the high-bits of the mask (and, thus, the result).
336 // Cannot commute if it has a non-zero rotate count.
337 if (MI.getOperand(3).getImm() != 0)
340 // If we have a zero rotate count, we have:
342 // Op0 = (Op1 & ~M) | (Op2 & M)
344 // M = mask((ME+1)&31, (MB-1)&31)
345 // Op0 = (Op2 & ~M) | (Op1 & M)
348 assert(((OpIdx1 == 1 && OpIdx2 == 2) || (OpIdx1 == 2 && OpIdx2 == 1)) &&
349 "Only the operands 1 and 2 can be swapped in RLSIMI/RLWIMIo.");
350 unsigned Reg0 = MI.getOperand(0).getReg();
351 unsigned Reg1 = MI.getOperand(1).getReg();
352 unsigned Reg2 = MI.getOperand(2).getReg();
353 unsigned SubReg1 = MI.getOperand(1).getSubReg();
354 unsigned SubReg2 = MI.getOperand(2).getSubReg();
355 bool Reg1IsKill = MI.getOperand(1).isKill();
356 bool Reg2IsKill = MI.getOperand(2).isKill();
357 bool ChangeReg0 = false;
358 // If machine instrs are no longer in two-address forms, update
359 // destination register as well.
361 // Must be two address instruction!
362 assert(MI.getDesc().getOperandConstraint(0, MCOI::TIED_TO) &&
363 "Expecting a two-address instruction!");
364 assert(MI.getOperand(0).getSubReg() == SubReg1 && "Tied subreg mismatch");
370 unsigned MB = MI.getOperand(4).getImm();
371 unsigned ME = MI.getOperand(5).getImm();
373 // We can't commute a trivial mask (there is no way to represent an all-zero
375 if (MB == 0 && ME == 31)
379 // Create a new instruction.
380 unsigned Reg0 = ChangeReg0 ? Reg2 : MI.getOperand(0).getReg();
381 bool Reg0IsDead = MI.getOperand(0).isDead();
382 return BuildMI(MF, MI.getDebugLoc(), MI.getDesc())
383 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
384 .addReg(Reg2, getKillRegState(Reg2IsKill))
385 .addReg(Reg1, getKillRegState(Reg1IsKill))
386 .addImm((ME + 1) & 31)
387 .addImm((MB - 1) & 31);
391 MI.getOperand(0).setReg(Reg2);
392 MI.getOperand(0).setSubReg(SubReg2);
394 MI.getOperand(2).setReg(Reg1);
395 MI.getOperand(1).setReg(Reg2);
396 MI.getOperand(2).setSubReg(SubReg1);
397 MI.getOperand(1).setSubReg(SubReg2);
398 MI.getOperand(2).setIsKill(Reg1IsKill);
399 MI.getOperand(1).setIsKill(Reg2IsKill);
401 // Swap the mask around.
402 MI.getOperand(4).setImm((ME + 1) & 31);
403 MI.getOperand(5).setImm((MB - 1) & 31);
407 bool PPCInstrInfo::findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
408 unsigned &SrcOpIdx2) const {
409 // For VSX A-Type FMA instructions, it is the first two operands that can be
410 // commuted, however, because the non-encoded tied input operand is listed
411 // first, the operands to swap are actually the second and third.
413 int AltOpc = PPC::getAltVSXFMAOpcode(MI.getOpcode());
415 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
417 // The commutable operand indices are 2 and 3. Return them in SrcOpIdx1
419 return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 2, 3);
422 void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
423 MachineBasicBlock::iterator MI) const {
424 // This function is used for scheduling, and the nop wanted here is the type
425 // that terminates dispatch groups on the POWER cores.
426 unsigned Directive = Subtarget.getDarwinDirective();
429 default: Opcode = PPC::NOP; break;
430 case PPC::DIR_PWR6: Opcode = PPC::NOP_GT_PWR6; break;
431 case PPC::DIR_PWR7: Opcode = PPC::NOP_GT_PWR7; break;
432 case PPC::DIR_PWR8: Opcode = PPC::NOP_GT_PWR7; break; /* FIXME: Update when P8 InstrScheduling model is ready */
433 // FIXME: Update when POWER9 scheduling model is ready.
434 case PPC::DIR_PWR9: Opcode = PPC::NOP_GT_PWR7; break;
438 BuildMI(MBB, MI, DL, get(Opcode));
441 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
442 void PPCInstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
443 NopInst.setOpcode(PPC::NOP);
447 // Note: If the condition register is set to CTR or CTR8 then this is a
448 // BDNZ (imm == 1) or BDZ (imm == 0) branch.
449 bool PPCInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
450 MachineBasicBlock *&TBB,
451 MachineBasicBlock *&FBB,
452 SmallVectorImpl<MachineOperand> &Cond,
453 bool AllowModify) const {
454 bool isPPC64 = Subtarget.isPPC64();
456 // If the block has no terminators, it just falls into the block after it.
457 MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
461 if (!isUnpredicatedTerminator(*I))
464 // Get the last instruction in the block.
465 MachineInstr &LastInst = *I;
467 // If there is only one terminator instruction, process it.
468 if (I == MBB.begin() || !isUnpredicatedTerminator(*--I)) {
469 if (LastInst.getOpcode() == PPC::B) {
470 if (!LastInst.getOperand(0).isMBB())
472 TBB = LastInst.getOperand(0).getMBB();
474 } else if (LastInst.getOpcode() == PPC::BCC) {
475 if (!LastInst.getOperand(2).isMBB())
477 // Block ends with fall-through condbranch.
478 TBB = LastInst.getOperand(2).getMBB();
479 Cond.push_back(LastInst.getOperand(0));
480 Cond.push_back(LastInst.getOperand(1));
482 } else if (LastInst.getOpcode() == PPC::BC) {
483 if (!LastInst.getOperand(1).isMBB())
485 // Block ends with fall-through condbranch.
486 TBB = LastInst.getOperand(1).getMBB();
487 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
488 Cond.push_back(LastInst.getOperand(0));
490 } else if (LastInst.getOpcode() == PPC::BCn) {
491 if (!LastInst.getOperand(1).isMBB())
493 // Block ends with fall-through condbranch.
494 TBB = LastInst.getOperand(1).getMBB();
495 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_UNSET));
496 Cond.push_back(LastInst.getOperand(0));
498 } else if (LastInst.getOpcode() == PPC::BDNZ8 ||
499 LastInst.getOpcode() == PPC::BDNZ) {
500 if (!LastInst.getOperand(0).isMBB())
502 if (DisableCTRLoopAnal)
504 TBB = LastInst.getOperand(0).getMBB();
505 Cond.push_back(MachineOperand::CreateImm(1));
506 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
509 } else if (LastInst.getOpcode() == PPC::BDZ8 ||
510 LastInst.getOpcode() == PPC::BDZ) {
511 if (!LastInst.getOperand(0).isMBB())
513 if (DisableCTRLoopAnal)
515 TBB = LastInst.getOperand(0).getMBB();
516 Cond.push_back(MachineOperand::CreateImm(0));
517 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
522 // Otherwise, don't know what this is.
526 // Get the instruction before it if it's a terminator.
527 MachineInstr &SecondLastInst = *I;
529 // If there are three terminators, we don't know what sort of block this is.
530 if (I != MBB.begin() && isUnpredicatedTerminator(*--I))
533 // If the block ends with PPC::B and PPC:BCC, handle it.
534 if (SecondLastInst.getOpcode() == PPC::BCC &&
535 LastInst.getOpcode() == PPC::B) {
536 if (!SecondLastInst.getOperand(2).isMBB() ||
537 !LastInst.getOperand(0).isMBB())
539 TBB = SecondLastInst.getOperand(2).getMBB();
540 Cond.push_back(SecondLastInst.getOperand(0));
541 Cond.push_back(SecondLastInst.getOperand(1));
542 FBB = LastInst.getOperand(0).getMBB();
544 } else if (SecondLastInst.getOpcode() == PPC::BC &&
545 LastInst.getOpcode() == PPC::B) {
546 if (!SecondLastInst.getOperand(1).isMBB() ||
547 !LastInst.getOperand(0).isMBB())
549 TBB = SecondLastInst.getOperand(1).getMBB();
550 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
551 Cond.push_back(SecondLastInst.getOperand(0));
552 FBB = LastInst.getOperand(0).getMBB();
554 } else if (SecondLastInst.getOpcode() == PPC::BCn &&
555 LastInst.getOpcode() == PPC::B) {
556 if (!SecondLastInst.getOperand(1).isMBB() ||
557 !LastInst.getOperand(0).isMBB())
559 TBB = SecondLastInst.getOperand(1).getMBB();
560 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_UNSET));
561 Cond.push_back(SecondLastInst.getOperand(0));
562 FBB = LastInst.getOperand(0).getMBB();
564 } else if ((SecondLastInst.getOpcode() == PPC::BDNZ8 ||
565 SecondLastInst.getOpcode() == PPC::BDNZ) &&
566 LastInst.getOpcode() == PPC::B) {
567 if (!SecondLastInst.getOperand(0).isMBB() ||
568 !LastInst.getOperand(0).isMBB())
570 if (DisableCTRLoopAnal)
572 TBB = SecondLastInst.getOperand(0).getMBB();
573 Cond.push_back(MachineOperand::CreateImm(1));
574 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
576 FBB = LastInst.getOperand(0).getMBB();
578 } else if ((SecondLastInst.getOpcode() == PPC::BDZ8 ||
579 SecondLastInst.getOpcode() == PPC::BDZ) &&
580 LastInst.getOpcode() == PPC::B) {
581 if (!SecondLastInst.getOperand(0).isMBB() ||
582 !LastInst.getOperand(0).isMBB())
584 if (DisableCTRLoopAnal)
586 TBB = SecondLastInst.getOperand(0).getMBB();
587 Cond.push_back(MachineOperand::CreateImm(0));
588 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
590 FBB = LastInst.getOperand(0).getMBB();
594 // If the block ends with two PPC:Bs, handle it. The second one is not
595 // executed, so remove it.
596 if (SecondLastInst.getOpcode() == PPC::B && LastInst.getOpcode() == PPC::B) {
597 if (!SecondLastInst.getOperand(0).isMBB())
599 TBB = SecondLastInst.getOperand(0).getMBB();
602 I->eraseFromParent();
606 // Otherwise, can't handle this.
610 unsigned PPCInstrInfo::removeBranch(MachineBasicBlock &MBB,
611 int *BytesRemoved) const {
612 assert(!BytesRemoved && "code size not handled");
614 MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
618 if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC &&
619 I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn &&
620 I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
621 I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
624 // Remove the branch.
625 I->eraseFromParent();
629 if (I == MBB.begin()) return 1;
631 if (I->getOpcode() != PPC::BCC &&
632 I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn &&
633 I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
634 I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
637 // Remove the branch.
638 I->eraseFromParent();
642 unsigned PPCInstrInfo::insertBranch(MachineBasicBlock &MBB,
643 MachineBasicBlock *TBB,
644 MachineBasicBlock *FBB,
645 ArrayRef<MachineOperand> Cond,
647 int *BytesAdded) const {
648 // Shouldn't be a fall through.
649 assert(TBB && "insertBranch must not be told to insert a fallthrough");
650 assert((Cond.size() == 2 || Cond.size() == 0) &&
651 "PPC branch conditions have two components!");
652 assert(!BytesAdded && "code size not handled");
654 bool isPPC64 = Subtarget.isPPC64();
658 if (Cond.empty()) // Unconditional branch
659 BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB);
660 else if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
661 BuildMI(&MBB, DL, get(Cond[0].getImm() ?
662 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
663 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
664 else if (Cond[0].getImm() == PPC::PRED_BIT_SET)
665 BuildMI(&MBB, DL, get(PPC::BC)).addOperand(Cond[1]).addMBB(TBB);
666 else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET)
667 BuildMI(&MBB, DL, get(PPC::BCn)).addOperand(Cond[1]).addMBB(TBB);
668 else // Conditional branch
669 BuildMI(&MBB, DL, get(PPC::BCC))
670 .addImm(Cond[0].getImm()).addOperand(Cond[1]).addMBB(TBB);
674 // Two-way Conditional Branch.
675 if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
676 BuildMI(&MBB, DL, get(Cond[0].getImm() ?
677 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
678 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
679 else if (Cond[0].getImm() == PPC::PRED_BIT_SET)
680 BuildMI(&MBB, DL, get(PPC::BC)).addOperand(Cond[1]).addMBB(TBB);
681 else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET)
682 BuildMI(&MBB, DL, get(PPC::BCn)).addOperand(Cond[1]).addMBB(TBB);
684 BuildMI(&MBB, DL, get(PPC::BCC))
685 .addImm(Cond[0].getImm()).addOperand(Cond[1]).addMBB(TBB);
686 BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB);
691 bool PPCInstrInfo::canInsertSelect(const MachineBasicBlock &MBB,
692 ArrayRef<MachineOperand> Cond,
693 unsigned TrueReg, unsigned FalseReg,
694 int &CondCycles, int &TrueCycles, int &FalseCycles) const {
695 if (!Subtarget.hasISEL())
698 if (Cond.size() != 2)
701 // If this is really a bdnz-like condition, then it cannot be turned into a
703 if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
706 // Check register classes.
707 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
708 const TargetRegisterClass *RC =
709 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
713 // isel is for regular integer GPRs only.
714 if (!PPC::GPRCRegClass.hasSubClassEq(RC) &&
715 !PPC::GPRC_NOR0RegClass.hasSubClassEq(RC) &&
716 !PPC::G8RCRegClass.hasSubClassEq(RC) &&
717 !PPC::G8RC_NOX0RegClass.hasSubClassEq(RC))
720 // FIXME: These numbers are for the A2, how well they work for other cores is
721 // an open question. On the A2, the isel instruction has a 2-cycle latency
722 // but single-cycle throughput. These numbers are used in combination with
723 // the MispredictPenalty setting from the active SchedMachineModel.
731 void PPCInstrInfo::insertSelect(MachineBasicBlock &MBB,
732 MachineBasicBlock::iterator MI,
733 const DebugLoc &dl, unsigned DestReg,
734 ArrayRef<MachineOperand> Cond, unsigned TrueReg,
735 unsigned FalseReg) const {
736 assert(Cond.size() == 2 &&
737 "PPC branch conditions have two components!");
739 assert(Subtarget.hasISEL() &&
740 "Cannot insert select on target without ISEL support");
742 // Get the register classes.
743 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
744 const TargetRegisterClass *RC =
745 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
746 assert(RC && "TrueReg and FalseReg must have overlapping register classes");
748 bool Is64Bit = PPC::G8RCRegClass.hasSubClassEq(RC) ||
749 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC);
751 PPC::GPRCRegClass.hasSubClassEq(RC) ||
752 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) &&
753 "isel is for regular integer GPRs only");
755 unsigned OpCode = Is64Bit ? PPC::ISEL8 : PPC::ISEL;
756 auto SelectPred = static_cast<PPC::Predicate>(Cond[0].getImm());
759 bool SwapOps = false;
760 switch (SelectPred) {
762 case PPC::PRED_EQ_MINUS:
763 case PPC::PRED_EQ_PLUS:
764 SubIdx = PPC::sub_eq; SwapOps = false; break;
766 case PPC::PRED_NE_MINUS:
767 case PPC::PRED_NE_PLUS:
768 SubIdx = PPC::sub_eq; SwapOps = true; break;
770 case PPC::PRED_LT_MINUS:
771 case PPC::PRED_LT_PLUS:
772 SubIdx = PPC::sub_lt; SwapOps = false; break;
774 case PPC::PRED_GE_MINUS:
775 case PPC::PRED_GE_PLUS:
776 SubIdx = PPC::sub_lt; SwapOps = true; break;
778 case PPC::PRED_GT_MINUS:
779 case PPC::PRED_GT_PLUS:
780 SubIdx = PPC::sub_gt; SwapOps = false; break;
782 case PPC::PRED_LE_MINUS:
783 case PPC::PRED_LE_PLUS:
784 SubIdx = PPC::sub_gt; SwapOps = true; break;
786 case PPC::PRED_UN_MINUS:
787 case PPC::PRED_UN_PLUS:
788 SubIdx = PPC::sub_un; SwapOps = false; break;
790 case PPC::PRED_NU_MINUS:
791 case PPC::PRED_NU_PLUS:
792 SubIdx = PPC::sub_un; SwapOps = true; break;
793 case PPC::PRED_BIT_SET: SubIdx = 0; SwapOps = false; break;
794 case PPC::PRED_BIT_UNSET: SubIdx = 0; SwapOps = true; break;
797 unsigned FirstReg = SwapOps ? FalseReg : TrueReg,
798 SecondReg = SwapOps ? TrueReg : FalseReg;
800 // The first input register of isel cannot be r0. If it is a member
801 // of a register class that can be r0, then copy it first (the
802 // register allocator should eliminate the copy).
803 if (MRI.getRegClass(FirstReg)->contains(PPC::R0) ||
804 MRI.getRegClass(FirstReg)->contains(PPC::X0)) {
805 const TargetRegisterClass *FirstRC =
806 MRI.getRegClass(FirstReg)->contains(PPC::X0) ?
807 &PPC::G8RC_NOX0RegClass : &PPC::GPRC_NOR0RegClass;
808 unsigned OldFirstReg = FirstReg;
809 FirstReg = MRI.createVirtualRegister(FirstRC);
810 BuildMI(MBB, MI, dl, get(TargetOpcode::COPY), FirstReg)
811 .addReg(OldFirstReg);
814 BuildMI(MBB, MI, dl, get(OpCode), DestReg)
815 .addReg(FirstReg).addReg(SecondReg)
816 .addReg(Cond[1].getReg(), 0, SubIdx);
819 static unsigned getCRBitValue(unsigned CRBit) {
821 if (CRBit == PPC::CR0LT || CRBit == PPC::CR1LT ||
822 CRBit == PPC::CR2LT || CRBit == PPC::CR3LT ||
823 CRBit == PPC::CR4LT || CRBit == PPC::CR5LT ||
824 CRBit == PPC::CR6LT || CRBit == PPC::CR7LT)
826 if (CRBit == PPC::CR0GT || CRBit == PPC::CR1GT ||
827 CRBit == PPC::CR2GT || CRBit == PPC::CR3GT ||
828 CRBit == PPC::CR4GT || CRBit == PPC::CR5GT ||
829 CRBit == PPC::CR6GT || CRBit == PPC::CR7GT)
831 if (CRBit == PPC::CR0EQ || CRBit == PPC::CR1EQ ||
832 CRBit == PPC::CR2EQ || CRBit == PPC::CR3EQ ||
833 CRBit == PPC::CR4EQ || CRBit == PPC::CR5EQ ||
834 CRBit == PPC::CR6EQ || CRBit == PPC::CR7EQ)
836 if (CRBit == PPC::CR0UN || CRBit == PPC::CR1UN ||
837 CRBit == PPC::CR2UN || CRBit == PPC::CR3UN ||
838 CRBit == PPC::CR4UN || CRBit == PPC::CR5UN ||
839 CRBit == PPC::CR6UN || CRBit == PPC::CR7UN)
842 assert(Ret != 4 && "Invalid CR bit register");
846 void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
847 MachineBasicBlock::iterator I,
848 const DebugLoc &DL, unsigned DestReg,
849 unsigned SrcReg, bool KillSrc) const {
850 // We can end up with self copies and similar things as a result of VSX copy
851 // legalization. Promote them here.
852 const TargetRegisterInfo *TRI = &getRegisterInfo();
853 if (PPC::F8RCRegClass.contains(DestReg) &&
854 PPC::VSRCRegClass.contains(SrcReg)) {
856 TRI->getMatchingSuperReg(DestReg, PPC::sub_64, &PPC::VSRCRegClass);
858 if (VSXSelfCopyCrash && SrcReg == SuperReg)
859 llvm_unreachable("nop VSX copy");
862 } else if (PPC::F8RCRegClass.contains(SrcReg) &&
863 PPC::VSRCRegClass.contains(DestReg)) {
865 TRI->getMatchingSuperReg(SrcReg, PPC::sub_64, &PPC::VSRCRegClass);
867 if (VSXSelfCopyCrash && DestReg == SuperReg)
868 llvm_unreachable("nop VSX copy");
873 // Different class register copy
874 if (PPC::CRBITRCRegClass.contains(SrcReg) &&
875 PPC::GPRCRegClass.contains(DestReg)) {
876 unsigned CRReg = getCRFromCRBit(SrcReg);
877 BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg).addReg(CRReg);
878 getKillRegState(KillSrc);
879 // Rotate the CR bit in the CR fields to be the least significant bit and
880 // then mask with 0x1 (MB = ME = 31).
881 BuildMI(MBB, I, DL, get(PPC::RLWINM), DestReg)
882 .addReg(DestReg, RegState::Kill)
883 .addImm(TRI->getEncodingValue(CRReg) * 4 + (4 - getCRBitValue(SrcReg)))
887 } else if (PPC::CRRCRegClass.contains(SrcReg) &&
888 PPC::G8RCRegClass.contains(DestReg)) {
889 BuildMI(MBB, I, DL, get(PPC::MFOCRF8), DestReg).addReg(SrcReg);
890 getKillRegState(KillSrc);
892 } else if (PPC::CRRCRegClass.contains(SrcReg) &&
893 PPC::GPRCRegClass.contains(DestReg)) {
894 BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg).addReg(SrcReg);
895 getKillRegState(KillSrc);
900 if (PPC::GPRCRegClass.contains(DestReg, SrcReg))
902 else if (PPC::G8RCRegClass.contains(DestReg, SrcReg))
904 else if (PPC::F4RCRegClass.contains(DestReg, SrcReg))
906 else if (PPC::CRRCRegClass.contains(DestReg, SrcReg))
908 else if (PPC::VRRCRegClass.contains(DestReg, SrcReg))
910 else if (PPC::VSRCRegClass.contains(DestReg, SrcReg))
911 // There are two different ways this can be done:
912 // 1. xxlor : This has lower latency (on the P7), 2 cycles, but can only
913 // issue in VSU pipeline 0.
914 // 2. xmovdp/xmovsp: This has higher latency (on the P7), 6 cycles, but
915 // can go to either pipeline.
916 // We'll always use xxlor here, because in practically all cases where
917 // copies are generated, they are close enough to some use that the
918 // lower-latency form is preferable.
920 else if (PPC::VSFRCRegClass.contains(DestReg, SrcReg) ||
921 PPC::VSSRCRegClass.contains(DestReg, SrcReg))
923 else if (PPC::QFRCRegClass.contains(DestReg, SrcReg))
925 else if (PPC::QSRCRegClass.contains(DestReg, SrcReg))
927 else if (PPC::QBRCRegClass.contains(DestReg, SrcReg))
929 else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg))
932 llvm_unreachable("Impossible reg-to-reg copy");
934 const MCInstrDesc &MCID = get(Opc);
935 if (MCID.getNumOperands() == 3)
936 BuildMI(MBB, I, DL, MCID, DestReg)
937 .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc));
939 BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
942 // This function returns true if a CR spill is necessary and false otherwise.
944 PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
945 unsigned SrcReg, bool isKill,
947 const TargetRegisterClass *RC,
948 SmallVectorImpl<MachineInstr*> &NewMIs,
949 bool &NonRI, bool &SpillsVRS) const{
950 // Note: If additional store instructions are added here,
951 // update isStoreToStackSlot.
954 if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
955 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) {
956 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
958 getKillRegState(isKill)),
960 } else if (PPC::G8RCRegClass.hasSubClassEq(RC) ||
961 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
962 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
964 getKillRegState(isKill)),
966 } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
967 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD))
969 getKillRegState(isKill)),
971 } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
972 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS))
974 getKillRegState(isKill)),
976 } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
977 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR))
979 getKillRegState(isKill)),
982 } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
983 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CRBIT))
985 getKillRegState(isKill)),
988 } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
989 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STVX))
991 getKillRegState(isKill)),
994 } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) {
995 unsigned Op = Subtarget.hasP9Vector() ? PPC::STXVX : PPC::STXVD2X;
996 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(Op))
998 getKillRegState(isKill)),
1001 } else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) {
1002 unsigned Opc = Subtarget.hasP9Vector() ? PPC::DFSTOREf64 : PPC::STXSDX;
1003 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(Opc))
1005 getKillRegState(isKill)),
1008 } else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) {
1009 unsigned Opc = Subtarget.hasP9Vector() ? PPC::DFSTOREf32 : PPC::STXSSPX;
1010 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(Opc))
1012 getKillRegState(isKill)),
1015 } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
1016 assert(Subtarget.isDarwin() &&
1017 "VRSAVE only needs spill/restore on Darwin");
1018 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_VRSAVE))
1020 getKillRegState(isKill)),
1023 } else if (PPC::QFRCRegClass.hasSubClassEq(RC)) {
1024 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVSTFDX))
1026 getKillRegState(isKill)),
1029 } else if (PPC::QSRCRegClass.hasSubClassEq(RC)) {
1030 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVSTFSXs))
1032 getKillRegState(isKill)),
1035 } else if (PPC::QBRCRegClass.hasSubClassEq(RC)) {
1036 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVSTFDXb))
1038 getKillRegState(isKill)),
1042 llvm_unreachable("Unknown regclass!");
1049 PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
1050 MachineBasicBlock::iterator MI,
1051 unsigned SrcReg, bool isKill, int FrameIdx,
1052 const TargetRegisterClass *RC,
1053 const TargetRegisterInfo *TRI) const {
1054 MachineFunction &MF = *MBB.getParent();
1055 SmallVector<MachineInstr*, 4> NewMIs;
1057 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1058 FuncInfo->setHasSpills();
1060 // We need to avoid a situation in which the value from a VRRC register is
1061 // spilled using an Altivec instruction and reloaded into a VSRC register
1062 // using a VSX instruction. The issue with this is that the VSX
1063 // load/store instructions swap the doublewords in the vector and the Altivec
1064 // ones don't. The register classes on the spill/reload may be different if
1065 // the register is defined using an Altivec instruction and is then used by a
1069 bool NonRI = false, SpillsVRS = false;
1070 if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs,
1072 FuncInfo->setSpillsCR();
1075 FuncInfo->setSpillsVRSAVE();
1078 FuncInfo->setHasNonRISpills();
1080 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
1081 MBB.insert(MI, NewMIs[i]);
1083 const MachineFrameInfo &MFI = MF.getFrameInfo();
1084 MachineMemOperand *MMO = MF.getMachineMemOperand(
1085 MachinePointerInfo::getFixedStack(MF, FrameIdx),
1086 MachineMemOperand::MOStore, MFI.getObjectSize(FrameIdx),
1087 MFI.getObjectAlignment(FrameIdx));
1088 NewMIs.back()->addMemOperand(MF, MMO);
1091 bool PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, const DebugLoc &DL,
1092 unsigned DestReg, int FrameIdx,
1093 const TargetRegisterClass *RC,
1094 SmallVectorImpl<MachineInstr *> &NewMIs,
1095 bool &NonRI, bool &SpillsVRS) const {
1096 // Note: If additional load instructions are added here,
1097 // update isLoadFromStackSlot.
1099 if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
1100 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) {
1101 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
1102 DestReg), FrameIdx));
1103 } else if (PPC::G8RCRegClass.hasSubClassEq(RC) ||
1104 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
1105 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), DestReg),
1107 } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
1108 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFD), DestReg),
1110 } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
1111 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFS), DestReg),
1113 } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
1114 NewMIs.push_back(addFrameReference(BuildMI(MF, DL,
1115 get(PPC::RESTORE_CR), DestReg),
1118 } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
1119 NewMIs.push_back(addFrameReference(BuildMI(MF, DL,
1120 get(PPC::RESTORE_CRBIT), DestReg),
1123 } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
1124 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LVX), DestReg),
1127 } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) {
1128 unsigned Op = Subtarget.hasP9Vector() ? PPC::LXVX : PPC::LXVD2X;
1129 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(Op), DestReg),
1132 } else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) {
1133 unsigned Opc = Subtarget.hasP9Vector() ? PPC::DFLOADf64 : PPC::LXSDX;
1134 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(Opc),
1135 DestReg), FrameIdx));
1137 } else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) {
1138 unsigned Opc = Subtarget.hasP9Vector() ? PPC::DFLOADf32 : PPC::LXSSPX;
1139 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(Opc),
1140 DestReg), FrameIdx));
1142 } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
1143 assert(Subtarget.isDarwin() &&
1144 "VRSAVE only needs spill/restore on Darwin");
1145 NewMIs.push_back(addFrameReference(BuildMI(MF, DL,
1146 get(PPC::RESTORE_VRSAVE),
1150 } else if (PPC::QFRCRegClass.hasSubClassEq(RC)) {
1151 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVLFDX), DestReg),
1154 } else if (PPC::QSRCRegClass.hasSubClassEq(RC)) {
1155 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVLFSXs), DestReg),
1158 } else if (PPC::QBRCRegClass.hasSubClassEq(RC)) {
1159 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVLFDXb), DestReg),
1163 llvm_unreachable("Unknown regclass!");
1170 PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
1171 MachineBasicBlock::iterator MI,
1172 unsigned DestReg, int FrameIdx,
1173 const TargetRegisterClass *RC,
1174 const TargetRegisterInfo *TRI) const {
1175 MachineFunction &MF = *MBB.getParent();
1176 SmallVector<MachineInstr*, 4> NewMIs;
1178 if (MI != MBB.end()) DL = MI->getDebugLoc();
1180 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1181 FuncInfo->setHasSpills();
1183 // We need to avoid a situation in which the value from a VRRC register is
1184 // spilled using an Altivec instruction and reloaded into a VSRC register
1185 // using a VSX instruction. The issue with this is that the VSX
1186 // load/store instructions swap the doublewords in the vector and the Altivec
1187 // ones don't. The register classes on the spill/reload may be different if
1188 // the register is defined using an Altivec instruction and is then used by a
1190 if (Subtarget.hasVSX() && RC == &PPC::VRRCRegClass)
1191 RC = &PPC::VSRCRegClass;
1193 bool NonRI = false, SpillsVRS = false;
1194 if (LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs,
1196 FuncInfo->setSpillsCR();
1199 FuncInfo->setSpillsVRSAVE();
1202 FuncInfo->setHasNonRISpills();
1204 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
1205 MBB.insert(MI, NewMIs[i]);
1207 const MachineFrameInfo &MFI = MF.getFrameInfo();
1208 MachineMemOperand *MMO = MF.getMachineMemOperand(
1209 MachinePointerInfo::getFixedStack(MF, FrameIdx),
1210 MachineMemOperand::MOLoad, MFI.getObjectSize(FrameIdx),
1211 MFI.getObjectAlignment(FrameIdx));
1212 NewMIs.back()->addMemOperand(MF, MMO);
1216 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
1217 assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
1218 if (Cond[1].getReg() == PPC::CTR8 || Cond[1].getReg() == PPC::CTR)
1219 Cond[0].setImm(Cond[0].getImm() == 0 ? 1 : 0);
1221 // Leave the CR# the same, but invert the condition.
1222 Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
1226 bool PPCInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
1227 unsigned Reg, MachineRegisterInfo *MRI) const {
1228 // For some instructions, it is legal to fold ZERO into the RA register field.
1229 // A zero immediate should always be loaded with a single li.
1230 unsigned DefOpc = DefMI.getOpcode();
1231 if (DefOpc != PPC::LI && DefOpc != PPC::LI8)
1233 if (!DefMI.getOperand(1).isImm())
1235 if (DefMI.getOperand(1).getImm() != 0)
1238 // Note that we cannot here invert the arguments of an isel in order to fold
1239 // a ZERO into what is presented as the second argument. All we have here
1240 // is the condition bit, and that might come from a CR-logical bit operation.
1242 const MCInstrDesc &UseMCID = UseMI.getDesc();
1244 // Only fold into real machine instructions.
1245 if (UseMCID.isPseudo())
1249 for (UseIdx = 0; UseIdx < UseMI.getNumOperands(); ++UseIdx)
1250 if (UseMI.getOperand(UseIdx).isReg() &&
1251 UseMI.getOperand(UseIdx).getReg() == Reg)
1254 assert(UseIdx < UseMI.getNumOperands() && "Cannot find Reg in UseMI");
1255 assert(UseIdx < UseMCID.getNumOperands() && "No operand description for Reg");
1257 const MCOperandInfo *UseInfo = &UseMCID.OpInfo[UseIdx];
1259 // We can fold the zero if this register requires a GPRC_NOR0/G8RC_NOX0
1260 // register (which might also be specified as a pointer class kind).
1261 if (UseInfo->isLookupPtrRegClass()) {
1262 if (UseInfo->RegClass /* Kind */ != 1)
1265 if (UseInfo->RegClass != PPC::GPRC_NOR0RegClassID &&
1266 UseInfo->RegClass != PPC::G8RC_NOX0RegClassID)
1270 // Make sure this is not tied to an output register (or otherwise
1271 // constrained). This is true for ST?UX registers, for example, which
1272 // are tied to their output registers.
1273 if (UseInfo->Constraints != 0)
1277 if (UseInfo->isLookupPtrRegClass()) {
1278 bool isPPC64 = Subtarget.isPPC64();
1279 ZeroReg = isPPC64 ? PPC::ZERO8 : PPC::ZERO;
1281 ZeroReg = UseInfo->RegClass == PPC::G8RC_NOX0RegClassID ?
1282 PPC::ZERO8 : PPC::ZERO;
1285 bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
1286 UseMI.getOperand(UseIdx).setReg(ZeroReg);
1289 DefMI.eraseFromParent();
1294 static bool MBBDefinesCTR(MachineBasicBlock &MBB) {
1295 for (MachineBasicBlock::iterator I = MBB.begin(), IE = MBB.end();
1297 if (I->definesRegister(PPC::CTR) || I->definesRegister(PPC::CTR8))
1302 // We should make sure that, if we're going to predicate both sides of a
1303 // condition (a diamond), that both sides don't define the counter register. We
1304 // can predicate counter-decrement-based branches, but while that predicates
1305 // the branching, it does not predicate the counter decrement. If we tried to
1306 // merge the triangle into one predicated block, we'd decrement the counter
1308 bool PPCInstrInfo::isProfitableToIfCvt(MachineBasicBlock &TMBB,
1309 unsigned NumT, unsigned ExtraT,
1310 MachineBasicBlock &FMBB,
1311 unsigned NumF, unsigned ExtraF,
1312 BranchProbability Probability) const {
1313 return !(MBBDefinesCTR(TMBB) && MBBDefinesCTR(FMBB));
1317 bool PPCInstrInfo::isPredicated(const MachineInstr &MI) const {
1318 // The predicated branches are identified by their type, not really by the
1319 // explicit presence of a predicate. Furthermore, some of them can be
1320 // predicated more than once. Because if conversion won't try to predicate
1321 // any instruction which already claims to be predicated (by returning true
1322 // here), always return false. In doing so, we let isPredicable() be the
1323 // final word on whether not the instruction can be (further) predicated.
1328 bool PPCInstrInfo::isUnpredicatedTerminator(const MachineInstr &MI) const {
1329 if (!MI.isTerminator())
1332 // Conditional branch is a special case.
1333 if (MI.isBranch() && !MI.isBarrier())
1336 return !isPredicated(MI);
1339 bool PPCInstrInfo::PredicateInstruction(MachineInstr &MI,
1340 ArrayRef<MachineOperand> Pred) const {
1341 unsigned OpC = MI.getOpcode();
1342 if (OpC == PPC::BLR || OpC == PPC::BLR8) {
1343 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
1344 bool isPPC64 = Subtarget.isPPC64();
1345 MI.setDesc(get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZLR8 : PPC::BDNZLR)
1346 : (isPPC64 ? PPC::BDZLR8 : PPC::BDZLR)));
1347 } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1348 MI.setDesc(get(PPC::BCLR));
1349 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
1350 .addReg(Pred[1].getReg());
1351 } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1352 MI.setDesc(get(PPC::BCLRn));
1353 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
1354 .addReg(Pred[1].getReg());
1356 MI.setDesc(get(PPC::BCCLR));
1357 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
1358 .addImm(Pred[0].getImm())
1359 .addReg(Pred[1].getReg());
1363 } else if (OpC == PPC::B) {
1364 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
1365 bool isPPC64 = Subtarget.isPPC64();
1366 MI.setDesc(get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ)
1367 : (isPPC64 ? PPC::BDZ8 : PPC::BDZ)));
1368 } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1369 MachineBasicBlock *MBB = MI.getOperand(0).getMBB();
1370 MI.RemoveOperand(0);
1372 MI.setDesc(get(PPC::BC));
1373 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
1374 .addReg(Pred[1].getReg())
1376 } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1377 MachineBasicBlock *MBB = MI.getOperand(0).getMBB();
1378 MI.RemoveOperand(0);
1380 MI.setDesc(get(PPC::BCn));
1381 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
1382 .addReg(Pred[1].getReg())
1385 MachineBasicBlock *MBB = MI.getOperand(0).getMBB();
1386 MI.RemoveOperand(0);
1388 MI.setDesc(get(PPC::BCC));
1389 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
1390 .addImm(Pred[0].getImm())
1391 .addReg(Pred[1].getReg())
1396 } else if (OpC == PPC::BCTR || OpC == PPC::BCTR8 ||
1397 OpC == PPC::BCTRL || OpC == PPC::BCTRL8) {
1398 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR)
1399 llvm_unreachable("Cannot predicate bctr[l] on the ctr register");
1401 bool setLR = OpC == PPC::BCTRL || OpC == PPC::BCTRL8;
1402 bool isPPC64 = Subtarget.isPPC64();
1404 if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1405 MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8 : PPC::BCCTR8)
1406 : (setLR ? PPC::BCCTRL : PPC::BCCTR)));
1407 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
1408 .addReg(Pred[1].getReg());
1410 } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1411 MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8n : PPC::BCCTR8n)
1412 : (setLR ? PPC::BCCTRLn : PPC::BCCTRn)));
1413 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
1414 .addReg(Pred[1].getReg());
1418 MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCCTRL8 : PPC::BCCCTR8)
1419 : (setLR ? PPC::BCCCTRL : PPC::BCCCTR)));
1420 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
1421 .addImm(Pred[0].getImm())
1422 .addReg(Pred[1].getReg());
1429 bool PPCInstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
1430 ArrayRef<MachineOperand> Pred2) const {
1431 assert(Pred1.size() == 2 && "Invalid PPC first predicate");
1432 assert(Pred2.size() == 2 && "Invalid PPC second predicate");
1434 if (Pred1[1].getReg() == PPC::CTR8 || Pred1[1].getReg() == PPC::CTR)
1436 if (Pred2[1].getReg() == PPC::CTR8 || Pred2[1].getReg() == PPC::CTR)
1439 // P1 can only subsume P2 if they test the same condition register.
1440 if (Pred1[1].getReg() != Pred2[1].getReg())
1443 PPC::Predicate P1 = (PPC::Predicate) Pred1[0].getImm();
1444 PPC::Predicate P2 = (PPC::Predicate) Pred2[0].getImm();
1449 // Does P1 subsume P2, e.g. GE subsumes GT.
1450 if (P1 == PPC::PRED_LE &&
1451 (P2 == PPC::PRED_LT || P2 == PPC::PRED_EQ))
1453 if (P1 == PPC::PRED_GE &&
1454 (P2 == PPC::PRED_GT || P2 == PPC::PRED_EQ))
1460 bool PPCInstrInfo::DefinesPredicate(MachineInstr &MI,
1461 std::vector<MachineOperand> &Pred) const {
1462 // Note: At the present time, the contents of Pred from this function is
1463 // unused by IfConversion. This implementation follows ARM by pushing the
1464 // CR-defining operand. Because the 'DZ' and 'DNZ' count as types of
1465 // predicate, instructions defining CTR or CTR8 are also included as
1466 // predicate-defining instructions.
1468 const TargetRegisterClass *RCs[] =
1469 { &PPC::CRRCRegClass, &PPC::CRBITRCRegClass,
1470 &PPC::CTRRCRegClass, &PPC::CTRRC8RegClass };
1473 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1474 const MachineOperand &MO = MI.getOperand(i);
1475 for (unsigned c = 0; c < array_lengthof(RCs) && !Found; ++c) {
1476 const TargetRegisterClass *RC = RCs[c];
1478 if (MO.isDef() && RC->contains(MO.getReg())) {
1482 } else if (MO.isRegMask()) {
1483 for (TargetRegisterClass::iterator I = RC->begin(),
1484 IE = RC->end(); I != IE; ++I)
1485 if (MO.clobbersPhysReg(*I)) {
1496 bool PPCInstrInfo::isPredicable(MachineInstr &MI) const {
1497 unsigned OpC = MI.getOpcode();
1512 bool PPCInstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
1513 unsigned &SrcReg2, int &Mask,
1515 unsigned Opc = MI.getOpcode();
1518 default: return false;
1523 SrcReg = MI.getOperand(1).getReg();
1525 Value = MI.getOperand(2).getImm();
1534 SrcReg = MI.getOperand(1).getReg();
1535 SrcReg2 = MI.getOperand(2).getReg();
1540 bool PPCInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
1541 unsigned SrcReg2, int Mask, int Value,
1542 const MachineRegisterInfo *MRI) const {
1546 int OpC = CmpInstr.getOpcode();
1547 unsigned CRReg = CmpInstr.getOperand(0).getReg();
1549 // FP record forms set CR1 based on the execption status bits, not a
1550 // comparison with zero.
1551 if (OpC == PPC::FCMPUS || OpC == PPC::FCMPUD)
1554 // The record forms set the condition register based on a signed comparison
1555 // with zero (so says the ISA manual). This is not as straightforward as it
1556 // seems, however, because this is always a 64-bit comparison on PPC64, even
1557 // for instructions that are 32-bit in nature (like slw for example).
1558 // So, on PPC32, for unsigned comparisons, we can use the record forms only
1559 // for equality checks (as those don't depend on the sign). On PPC64,
1560 // we are restricted to equality for unsigned 64-bit comparisons and for
1561 // signed 32-bit comparisons the applicability is more restricted.
1562 bool isPPC64 = Subtarget.isPPC64();
1563 bool is32BitSignedCompare = OpC == PPC::CMPWI || OpC == PPC::CMPW;
1564 bool is32BitUnsignedCompare = OpC == PPC::CMPLWI || OpC == PPC::CMPLW;
1565 bool is64BitUnsignedCompare = OpC == PPC::CMPLDI || OpC == PPC::CMPLD;
1567 // Get the unique definition of SrcReg.
1568 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
1569 if (!MI) return false;
1570 int MIOpC = MI->getOpcode();
1572 bool equalityOnly = false;
1575 if (is32BitSignedCompare) {
1576 // We can perform this optimization only if MI is sign-extending.
1577 if (MIOpC == PPC::SRAW || MIOpC == PPC::SRAWo ||
1578 MIOpC == PPC::SRAWI || MIOpC == PPC::SRAWIo ||
1579 MIOpC == PPC::EXTSB || MIOpC == PPC::EXTSBo ||
1580 MIOpC == PPC::EXTSH || MIOpC == PPC::EXTSHo ||
1581 MIOpC == PPC::EXTSW || MIOpC == PPC::EXTSWo) {
1585 } else if (is32BitUnsignedCompare) {
1586 // 32-bit rotate and mask instructions are zero extending only if MB <= ME
1587 bool isZeroExtendingRotate =
1588 (MIOpC == PPC::RLWINM || MIOpC == PPC::RLWINMo ||
1589 MIOpC == PPC::RLWNM || MIOpC == PPC::RLWNMo)
1590 && MI->getOperand(3).getImm() <= MI->getOperand(4).getImm();
1592 // We can perform this optimization, equality only, if MI is
1594 if (MIOpC == PPC::CNTLZW || MIOpC == PPC::CNTLZWo ||
1595 MIOpC == PPC::SLW || MIOpC == PPC::SLWo ||
1596 MIOpC == PPC::SRW || MIOpC == PPC::SRWo ||
1597 isZeroExtendingRotate) {
1599 equalityOnly = true;
1603 equalityOnly = is64BitUnsignedCompare;
1605 equalityOnly = is32BitUnsignedCompare;
1608 // We need to check the uses of the condition register in order to reject
1609 // non-equality comparisons.
1610 for (MachineRegisterInfo::use_instr_iterator I =MRI->use_instr_begin(CRReg),
1611 IE = MRI->use_instr_end(); I != IE; ++I) {
1612 MachineInstr *UseMI = &*I;
1613 if (UseMI->getOpcode() == PPC::BCC) {
1614 unsigned Pred = UseMI->getOperand(0).getImm();
1615 if (Pred != PPC::PRED_EQ && Pred != PPC::PRED_NE)
1617 } else if (UseMI->getOpcode() == PPC::ISEL ||
1618 UseMI->getOpcode() == PPC::ISEL8) {
1619 unsigned SubIdx = UseMI->getOperand(3).getSubReg();
1620 if (SubIdx != PPC::sub_eq)
1627 MachineBasicBlock::iterator I = CmpInstr;
1629 // Scan forward to find the first use of the compare.
1630 for (MachineBasicBlock::iterator EL = CmpInstr.getParent()->end(); I != EL;
1632 bool FoundUse = false;
1633 for (MachineRegisterInfo::use_instr_iterator J =MRI->use_instr_begin(CRReg),
1634 JE = MRI->use_instr_end(); J != JE; ++J)
1644 // There are two possible candidates which can be changed to set CR[01].
1645 // One is MI, the other is a SUB instruction.
1646 // For CMPrr(r1,r2), we are looking for SUB(r1,r2) or SUB(r2,r1).
1647 MachineInstr *Sub = nullptr;
1649 // MI is not a candidate for CMPrr.
1651 // FIXME: Conservatively refuse to convert an instruction which isn't in the
1652 // same BB as the comparison. This is to allow the check below to avoid calls
1653 // (and other explicit clobbers); instead we should really check for these
1654 // more explicitly (in at least a few predecessors).
1655 else if (MI->getParent() != CmpInstr.getParent() || Value != 0) {
1656 // PPC does not have a record-form SUBri.
1661 const TargetRegisterInfo *TRI = &getRegisterInfo();
1664 // Get ready to iterate backward from CmpInstr.
1665 MachineBasicBlock::iterator E = MI, B = CmpInstr.getParent()->begin();
1667 for (; I != E && !noSub; --I) {
1668 const MachineInstr &Instr = *I;
1669 unsigned IOpC = Instr.getOpcode();
1671 if (&*I != &CmpInstr && (Instr.modifiesRegister(PPC::CR0, TRI) ||
1672 Instr.readsRegister(PPC::CR0, TRI)))
1673 // This instruction modifies or uses the record condition register after
1674 // the one we want to change. While we could do this transformation, it
1675 // would likely not be profitable. This transformation removes one
1676 // instruction, and so even forcing RA to generate one move probably
1677 // makes it unprofitable.
1680 // Check whether CmpInstr can be made redundant by the current instruction.
1681 if ((OpC == PPC::CMPW || OpC == PPC::CMPLW ||
1682 OpC == PPC::CMPD || OpC == PPC::CMPLD) &&
1683 (IOpC == PPC::SUBF || IOpC == PPC::SUBF8) &&
1684 ((Instr.getOperand(1).getReg() == SrcReg &&
1685 Instr.getOperand(2).getReg() == SrcReg2) ||
1686 (Instr.getOperand(1).getReg() == SrcReg2 &&
1687 Instr.getOperand(2).getReg() == SrcReg))) {
1693 // The 'and' is below the comparison instruction.
1697 // Return false if no candidates exist.
1701 // The single candidate is called MI.
1705 MIOpC = MI->getOpcode();
1706 if (MIOpC == PPC::ANDIo || MIOpC == PPC::ANDIo8)
1709 NewOpC = PPC::getRecordFormOpcode(MIOpC);
1710 if (NewOpC == -1 && PPC::getNonRecordFormOpcode(MIOpC) != -1)
1714 // FIXME: On the non-embedded POWER architectures, only some of the record
1715 // forms are fast, and we should use only the fast ones.
1717 // The defining instruction has a record form (or is already a record
1718 // form). It is possible, however, that we'll need to reverse the condition
1719 // code of the users.
1723 SmallVector<std::pair<MachineOperand*, PPC::Predicate>, 4> PredsToUpdate;
1724 SmallVector<std::pair<MachineOperand*, unsigned>, 4> SubRegsToUpdate;
1726 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code based on CMP
1727 // needs to be updated to be based on SUB. Push the condition code
1728 // operands to OperandsToUpdate. If it is safe to remove CmpInstr, the
1729 // condition code of these operands will be modified.
1730 bool ShouldSwap = false;
1732 ShouldSwap = SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
1733 Sub->getOperand(2).getReg() == SrcReg;
1735 // The operands to subf are the opposite of sub, so only in the fixed-point
1736 // case, invert the order.
1737 ShouldSwap = !ShouldSwap;
1741 for (MachineRegisterInfo::use_instr_iterator
1742 I = MRI->use_instr_begin(CRReg), IE = MRI->use_instr_end();
1744 MachineInstr *UseMI = &*I;
1745 if (UseMI->getOpcode() == PPC::BCC) {
1746 PPC::Predicate Pred = (PPC::Predicate) UseMI->getOperand(0).getImm();
1747 assert((!equalityOnly ||
1748 Pred == PPC::PRED_EQ || Pred == PPC::PRED_NE) &&
1749 "Invalid predicate for equality-only optimization");
1750 PredsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(0)),
1751 PPC::getSwappedPredicate(Pred)));
1752 } else if (UseMI->getOpcode() == PPC::ISEL ||
1753 UseMI->getOpcode() == PPC::ISEL8) {
1754 unsigned NewSubReg = UseMI->getOperand(3).getSubReg();
1755 assert((!equalityOnly || NewSubReg == PPC::sub_eq) &&
1756 "Invalid CR bit for equality-only optimization");
1758 if (NewSubReg == PPC::sub_lt)
1759 NewSubReg = PPC::sub_gt;
1760 else if (NewSubReg == PPC::sub_gt)
1761 NewSubReg = PPC::sub_lt;
1763 SubRegsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(3)),
1765 } else // We need to abort on a user we don't understand.
1769 // Create a new virtual register to hold the value of the CR set by the
1770 // record-form instruction. If the instruction was not previously in
1771 // record form, then set the kill flag on the CR.
1772 CmpInstr.eraseFromParent();
1774 MachineBasicBlock::iterator MII = MI;
1775 BuildMI(*MI->getParent(), std::next(MII), MI->getDebugLoc(),
1776 get(TargetOpcode::COPY), CRReg)
1777 .addReg(PPC::CR0, MIOpC != NewOpC ? RegState::Kill : 0);
1779 // Even if CR0 register were dead before, it is alive now since the
1780 // instruction we just built uses it.
1781 MI->clearRegisterDeads(PPC::CR0);
1783 if (MIOpC != NewOpC) {
1784 // We need to be careful here: we're replacing one instruction with
1785 // another, and we need to make sure that we get all of the right
1786 // implicit uses and defs. On the other hand, the caller may be holding
1787 // an iterator to this instruction, and so we can't delete it (this is
1788 // specifically the case if this is the instruction directly after the
1791 const MCInstrDesc &NewDesc = get(NewOpC);
1792 MI->setDesc(NewDesc);
1794 if (NewDesc.ImplicitDefs)
1795 for (const MCPhysReg *ImpDefs = NewDesc.getImplicitDefs();
1796 *ImpDefs; ++ImpDefs)
1797 if (!MI->definesRegister(*ImpDefs))
1798 MI->addOperand(*MI->getParent()->getParent(),
1799 MachineOperand::CreateReg(*ImpDefs, true, true));
1800 if (NewDesc.ImplicitUses)
1801 for (const MCPhysReg *ImpUses = NewDesc.getImplicitUses();
1802 *ImpUses; ++ImpUses)
1803 if (!MI->readsRegister(*ImpUses))
1804 MI->addOperand(*MI->getParent()->getParent(),
1805 MachineOperand::CreateReg(*ImpUses, false, true));
1807 assert(MI->definesRegister(PPC::CR0) &&
1808 "Record-form instruction does not define cr0?");
1810 // Modify the condition code of operands in OperandsToUpdate.
1811 // Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to
1812 // be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
1813 for (unsigned i = 0, e = PredsToUpdate.size(); i < e; i++)
1814 PredsToUpdate[i].first->setImm(PredsToUpdate[i].second);
1816 for (unsigned i = 0, e = SubRegsToUpdate.size(); i < e; i++)
1817 SubRegsToUpdate[i].first->setSubReg(SubRegsToUpdate[i].second);
1822 /// GetInstSize - Return the number of bytes of code the specified
1823 /// instruction may be. This returns the maximum number of bytes.
1825 unsigned PPCInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
1826 unsigned Opcode = MI.getOpcode();
1828 if (Opcode == PPC::INLINEASM) {
1829 const MachineFunction *MF = MI.getParent()->getParent();
1830 const char *AsmStr = MI.getOperand(0).getSymbolName();
1831 return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
1832 } else if (Opcode == TargetOpcode::STACKMAP) {
1833 StackMapOpers Opers(&MI);
1834 return Opers.getNumPatchBytes();
1835 } else if (Opcode == TargetOpcode::PATCHPOINT) {
1836 PatchPointOpers Opers(&MI);
1837 return Opers.getNumPatchBytes();
1839 const MCInstrDesc &Desc = get(Opcode);
1840 return Desc.getSize();
1844 std::pair<unsigned, unsigned>
1845 PPCInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
1846 const unsigned Mask = PPCII::MO_ACCESS_MASK;
1847 return std::make_pair(TF & Mask, TF & ~Mask);
1850 ArrayRef<std::pair<unsigned, const char *>>
1851 PPCInstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
1852 using namespace PPCII;
1853 static const std::pair<unsigned, const char *> TargetFlags[] = {
1856 {MO_TPREL_LO, "ppc-tprel-lo"},
1857 {MO_TPREL_HA, "ppc-tprel-ha"},
1858 {MO_DTPREL_LO, "ppc-dtprel-lo"},
1859 {MO_TLSLD_LO, "ppc-tlsld-lo"},
1860 {MO_TOC_LO, "ppc-toc-lo"},
1861 {MO_TLS, "ppc-tls"}};
1862 return makeArrayRef(TargetFlags);
1865 ArrayRef<std::pair<unsigned, const char *>>
1866 PPCInstrInfo::getSerializableBitmaskMachineOperandTargetFlags() const {
1867 using namespace PPCII;
1868 static const std::pair<unsigned, const char *> TargetFlags[] = {
1869 {MO_PLT, "ppc-plt"},
1870 {MO_PIC_FLAG, "ppc-pic"},
1871 {MO_NLP_FLAG, "ppc-nlp"},
1872 {MO_NLP_HIDDEN_FLAG, "ppc-nlp-hidden"}};
1873 return makeArrayRef(TargetFlags);
1876 bool PPCInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
1877 switch (MI.getOpcode()) {
1878 case TargetOpcode::LOAD_STACK_GUARD: {
1879 assert(Subtarget.isTargetLinux() &&
1880 "Only Linux target is expected to contain LOAD_STACK_GUARD");
1881 const int64_t Offset = Subtarget.isPPC64() ? -0x7010 : -0x7008;
1882 const unsigned Reg = Subtarget.isPPC64() ? PPC::X13 : PPC::R2;
1883 MI.setDesc(get(Subtarget.isPPC64() ? PPC::LD : PPC::LWZ));
1884 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
1889 case PPC::DFLOADf32:
1890 case PPC::DFLOADf64:
1891 case PPC::DFSTOREf32:
1892 case PPC::DFSTOREf64: {
1893 assert(Subtarget.hasP9Vector() &&
1894 "Invalid D-Form Pseudo-ops on non-P9 target.");
1895 unsigned UpperOpcode, LowerOpcode;
1896 switch (MI.getOpcode()) {
1897 case PPC::DFLOADf32:
1898 UpperOpcode = PPC::LXSSP;
1899 LowerOpcode = PPC::LFS;
1901 case PPC::DFLOADf64:
1902 UpperOpcode = PPC::LXSD;
1903 LowerOpcode = PPC::LFD;
1905 case PPC::DFSTOREf32:
1906 UpperOpcode = PPC::STXSSP;
1907 LowerOpcode = PPC::STFS;
1909 case PPC::DFSTOREf64:
1910 UpperOpcode = PPC::STXSD;
1911 LowerOpcode = PPC::STFD;
1914 unsigned TargetReg = MI.getOperand(0).getReg();
1916 if ((TargetReg >= PPC::F0 && TargetReg <= PPC::F31) ||
1917 (TargetReg >= PPC::VSL0 && TargetReg <= PPC::VSL31))
1918 Opcode = LowerOpcode;
1920 Opcode = UpperOpcode;
1921 MI.setDesc(get(Opcode));
1928 const TargetRegisterClass *
1929 PPCInstrInfo::updatedRC(const TargetRegisterClass *RC) const {
1930 if (Subtarget.hasVSX() && RC == &PPC::VRRCRegClass)
1931 return &PPC::VSRCRegClass;