1 //===-- PPCInstrInfo.h - PowerPC Instruction Information --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H
15 #define LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H
18 #include "PPCRegisterInfo.h"
19 #include "llvm/Target/TargetInstrInfo.h"
21 #define GET_INSTRINFO_HEADER
22 #include "PPCGenInstrInfo.inc"
26 /// PPCII - This namespace holds all of the PowerPC target-specific
27 /// per-instruction flags. These must match the corresponding definitions in
28 /// PPC.td and PPCInstrFormats.td.
31 // PPC970 Instruction Flags. These flags describe the characteristics of the
32 // PowerPC 970 (aka G5) dispatch groups and how they are formed out of
33 // raw machine instructions.
35 /// PPC970_First - This instruction starts a new dispatch group, so it will
36 /// always be the first one in the group.
39 /// PPC970_Single - This instruction starts a new dispatch group and
40 /// terminates it, so it will be the sole instruction in the group.
43 /// PPC970_Cracked - This instruction is cracked into two pieces, requiring
44 /// two dispatch pipes to be available to issue.
47 /// PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that
48 /// an instruction is issued to.
50 PPC970_Mask = 0x07 << PPC970_Shift
53 /// These are the various PPC970 execution unit pipelines. Each instruction
55 PPC970_Pseudo = 0 << PPC970_Shift, // Pseudo instruction
56 PPC970_FXU = 1 << PPC970_Shift, // Fixed Point (aka Integer/ALU) Unit
57 PPC970_LSU = 2 << PPC970_Shift, // Load Store Unit
58 PPC970_FPU = 3 << PPC970_Shift, // Floating Point Unit
59 PPC970_CRU = 4 << PPC970_Shift, // Control Register Unit
60 PPC970_VALU = 5 << PPC970_Shift, // Vector ALU
61 PPC970_VPERM = 6 << PPC970_Shift, // Vector Permute Unit
62 PPC970_BRU = 7 << PPC970_Shift // Branch Unit
64 } // end namespace PPCII
67 class PPCInstrInfo : public PPCGenInstrInfo {
68 PPCSubtarget &Subtarget;
69 const PPCRegisterInfo RI;
71 bool StoreRegToStackSlot(MachineFunction &MF,
72 unsigned SrcReg, bool isKill, int FrameIdx,
73 const TargetRegisterClass *RC,
74 SmallVectorImpl<MachineInstr*> &NewMIs,
75 bool &NonRI, bool &SpillsVRS) const;
76 bool LoadRegFromStackSlot(MachineFunction &MF, const DebugLoc &DL,
77 unsigned DestReg, int FrameIdx,
78 const TargetRegisterClass *RC,
79 SmallVectorImpl<MachineInstr *> &NewMIs,
80 bool &NonRI, bool &SpillsVRS) const;
81 virtual void anchor();
84 /// Commutes the operands in the given instruction.
85 /// The commutable operands are specified by their indices OpIdx1 and OpIdx2.
87 /// Do not call this method for a non-commutable instruction or for
88 /// non-commutable pair of operand indices OpIdx1 and OpIdx2.
89 /// Even though the instruction is commutable, the method may still
90 /// fail to commute the operands, null pointer is returned in such cases.
92 /// For example, we can commute rlwimi instructions, but only if the
93 /// rotate amt is zero. We also have to munge the immediates a bit.
94 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
96 unsigned OpIdx2) const override;
99 explicit PPCInstrInfo(PPCSubtarget &STI);
101 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
102 /// such, whenever a client has an instance of instruction info, it should
103 /// always be able to get register info as well (through this method).
105 const PPCRegisterInfo &getRegisterInfo() const { return RI; }
107 ScheduleHazardRecognizer *
108 CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
109 const ScheduleDAG *DAG) const override;
110 ScheduleHazardRecognizer *
111 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
112 const ScheduleDAG *DAG) const override;
114 unsigned getInstrLatency(const InstrItineraryData *ItinData,
115 const MachineInstr &MI,
116 unsigned *PredCost = nullptr) const override;
118 int getOperandLatency(const InstrItineraryData *ItinData,
119 const MachineInstr &DefMI, unsigned DefIdx,
120 const MachineInstr &UseMI,
121 unsigned UseIdx) const override;
122 int getOperandLatency(const InstrItineraryData *ItinData,
123 SDNode *DefNode, unsigned DefIdx,
124 SDNode *UseNode, unsigned UseIdx) const override {
125 return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx,
129 bool hasLowDefLatency(const TargetSchedModel &SchedModel,
130 const MachineInstr &DefMI,
131 unsigned DefIdx) const override {
132 // Machine LICM should hoist all instructions in low-register-pressure
133 // situations; none are sufficiently free to justify leaving in a loop
138 bool useMachineCombiner() const override {
142 /// Return true when there is potentially a faster code sequence
143 /// for an instruction chain ending in <Root>. All potential patterns are
144 /// output in the <Pattern> array.
145 bool getMachineCombinerPatterns(
147 SmallVectorImpl<MachineCombinerPattern> &P) const override;
149 bool isAssociativeAndCommutative(const MachineInstr &Inst) const override;
151 bool isCoalescableExtInstr(const MachineInstr &MI,
152 unsigned &SrcReg, unsigned &DstReg,
153 unsigned &SubIdx) const override;
154 unsigned isLoadFromStackSlot(const MachineInstr &MI,
155 int &FrameIndex) const override;
156 unsigned isStoreToStackSlot(const MachineInstr &MI,
157 int &FrameIndex) const override;
159 bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
160 unsigned &SrcOpIdx2) const override;
162 void insertNoop(MachineBasicBlock &MBB,
163 MachineBasicBlock::iterator MI) const override;
167 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
168 MachineBasicBlock *&FBB,
169 SmallVectorImpl<MachineOperand> &Cond,
170 bool AllowModify) const override;
171 unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
172 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
173 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
174 const DebugLoc &DL) const override;
177 bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond,
178 unsigned, unsigned, int &, int &, int &) const override;
179 void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
180 const DebugLoc &DL, unsigned DstReg,
181 ArrayRef<MachineOperand> Cond, unsigned TrueReg,
182 unsigned FalseReg) const override;
184 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
185 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
186 bool KillSrc) const override;
188 void storeRegToStackSlot(MachineBasicBlock &MBB,
189 MachineBasicBlock::iterator MBBI,
190 unsigned SrcReg, bool isKill, int FrameIndex,
191 const TargetRegisterClass *RC,
192 const TargetRegisterInfo *TRI) const override;
194 void loadRegFromStackSlot(MachineBasicBlock &MBB,
195 MachineBasicBlock::iterator MBBI,
196 unsigned DestReg, int FrameIndex,
197 const TargetRegisterClass *RC,
198 const TargetRegisterInfo *TRI) const override;
201 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
203 bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg,
204 MachineRegisterInfo *MRI) const override;
206 // If conversion by predication (only supported by some branch instructions).
207 // All of the profitability checks always return true; it is always
208 // profitable to use the predicated branches.
209 bool isProfitableToIfCvt(MachineBasicBlock &MBB,
210 unsigned NumCycles, unsigned ExtraPredCycles,
211 BranchProbability Probability) const override {
215 bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
216 unsigned NumT, unsigned ExtraT,
217 MachineBasicBlock &FMBB,
218 unsigned NumF, unsigned ExtraF,
219 BranchProbability Probability) const override;
221 bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
222 BranchProbability Probability) const override {
226 bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
227 MachineBasicBlock &FMBB) const override {
231 // Predication support.
232 bool isPredicated(const MachineInstr &MI) const override;
234 bool isUnpredicatedTerminator(const MachineInstr &MI) const override;
236 bool PredicateInstruction(MachineInstr &MI,
237 ArrayRef<MachineOperand> Pred) const override;
239 bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
240 ArrayRef<MachineOperand> Pred2) const override;
242 bool DefinesPredicate(MachineInstr &MI,
243 std::vector<MachineOperand> &Pred) const override;
245 bool isPredicable(MachineInstr &MI) const override;
247 // Comparison optimization.
249 bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
250 unsigned &SrcReg2, int &Mask, int &Value) const override;
252 bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
253 unsigned SrcReg2, int Mask, int Value,
254 const MachineRegisterInfo *MRI) const override;
256 /// GetInstSize - Return the number of bytes of code the specified
257 /// instruction may be. This returns the maximum number of bytes.
259 unsigned GetInstSizeInBytes(const MachineInstr &MI) const;
261 void getNoopForMachoTarget(MCInst &NopInst) const override;
263 std::pair<unsigned, unsigned>
264 decomposeMachineOperandsTargetFlags(unsigned TF) const override;
266 ArrayRef<std::pair<unsigned, const char *>>
267 getSerializableDirectMachineOperandTargetFlags() const override;
269 ArrayRef<std::pair<unsigned, const char *>>
270 getSerializableBitmaskMachineOperandTargetFlags() const override;
272 // Lower pseudo instructions after register allocation.
273 bool expandPostRAPseudo(MachineInstr &MI) const override;