1 //===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific type constraints.
20 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21 SDTCisVT<0, f64>, SDTCisPtrTy<1>
23 def SDT_PPClfiwx : SDTypeProfile<1, 1, [ // lfiw[az]x
24 SDTCisVT<0, f64>, SDTCisPtrTy<1>
26 def SDT_PPCLxsizx : SDTypeProfile<1, 2, [
27 SDTCisVT<0, f64>, SDTCisPtrTy<1>, SDTCisPtrTy<2>
29 def SDT_PPCstxsix : SDTypeProfile<0, 3, [
30 SDTCisVT<0, f64>, SDTCisPtrTy<1>, SDTCisPtrTy<2>
32 def SDT_PPCVexts : SDTypeProfile<1, 2, [
33 SDTCisVT<0, f64>, SDTCisVT<1, f64>, SDTCisPtrTy<2>
36 def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
37 def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
39 def SDT_PPCvperm : SDTypeProfile<1, 3, [
40 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
43 def SDT_PPCVecSplat : SDTypeProfile<1, 2, [ SDTCisVec<0>,
44 SDTCisVec<1>, SDTCisInt<2>
47 def SDT_PPCVecShift : SDTypeProfile<1, 3, [ SDTCisVec<0>,
48 SDTCisVec<1>, SDTCisVec<2>, SDTCisInt<3>
51 def SDT_PPCVecInsert : SDTypeProfile<1, 3, [ SDTCisVec<0>,
52 SDTCisVec<1>, SDTCisVec<2>, SDTCisInt<3>
55 def SDT_PPCvcmp : SDTypeProfile<1, 3, [
56 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
59 def SDT_PPCcondbr : SDTypeProfile<0, 3, [
60 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT>
63 def SDT_PPClbrx : SDTypeProfile<1, 2, [
64 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
66 def SDT_PPCstbrx : SDTypeProfile<0, 3, [
67 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
70 def SDT_PPCTC_ret : SDTypeProfile<0, 2, [
71 SDTCisPtrTy<0>, SDTCisVT<1, i32>
74 def tocentry32 : Operand<iPTR> {
75 let MIOperandInfo = (ops i32imm:$imm);
78 def SDT_PPCqvfperm : SDTypeProfile<1, 3, [
79 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisVec<3>
81 def SDT_PPCqvgpci : SDTypeProfile<1, 1, [
82 SDTCisVec<0>, SDTCisInt<1>
84 def SDT_PPCqvaligni : SDTypeProfile<1, 3, [
85 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<3>
87 def SDT_PPCqvesplati : SDTypeProfile<1, 2, [
88 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisInt<2>
91 def SDT_PPCqbflt : SDTypeProfile<1, 1, [
92 SDTCisVec<0>, SDTCisVec<1>
95 def SDT_PPCqvlfsb : SDTypeProfile<1, 1, [
96 SDTCisVec<0>, SDTCisPtrTy<1>
99 //===----------------------------------------------------------------------===//
100 // PowerPC specific DAG Nodes.
103 def PPCfre : SDNode<"PPCISD::FRE", SDTFPUnaryOp, []>;
104 def PPCfrsqrte: SDNode<"PPCISD::FRSQRTE", SDTFPUnaryOp, []>;
106 def PPCfcfid : SDNode<"PPCISD::FCFID", SDTFPUnaryOp, []>;
107 def PPCfcfidu : SDNode<"PPCISD::FCFIDU", SDTFPUnaryOp, []>;
108 def PPCfcfids : SDNode<"PPCISD::FCFIDS", SDTFPRoundOp, []>;
109 def PPCfcfidus: SDNode<"PPCISD::FCFIDUS", SDTFPRoundOp, []>;
110 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
111 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
112 def PPCfctiduz: SDNode<"PPCISD::FCTIDUZ",SDTFPUnaryOp, []>;
113 def PPCfctiwuz: SDNode<"PPCISD::FCTIWUZ",SDTFPUnaryOp, []>;
114 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx,
115 [SDNPHasChain, SDNPMayStore]>;
116 def PPClfiwax : SDNode<"PPCISD::LFIWAX", SDT_PPClfiwx,
117 [SDNPHasChain, SDNPMayLoad]>;
118 def PPClfiwzx : SDNode<"PPCISD::LFIWZX", SDT_PPClfiwx,
119 [SDNPHasChain, SDNPMayLoad]>;
120 def PPClxsizx : SDNode<"PPCISD::LXSIZX", SDT_PPCLxsizx,
121 [SDNPHasChain, SDNPMayLoad]>;
122 def PPCstxsix : SDNode<"PPCISD::STXSIX", SDT_PPCstxsix,
123 [SDNPHasChain, SDNPMayStore]>;
124 def PPCVexts : SDNode<"PPCISD::VEXTS", SDT_PPCVexts, []>;
126 // Extract FPSCR (not modeled at the DAG level).
127 def PPCmffs : SDNode<"PPCISD::MFFS",
128 SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>, []>;
130 // Perform FADD in round-to-zero mode.
131 def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp, []>;
134 def PPCfsel : SDNode<"PPCISD::FSEL",
135 // Type constraint for fsel.
136 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
137 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
139 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
140 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
141 def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp,
142 [SDNPMayLoad, SDNPMemOperand]>;
143 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
144 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
146 def PPCppc32GOT : SDNode<"PPCISD::PPC32_GOT", SDTIntLeaf, []>;
148 def PPCaddisGotTprelHA : SDNode<"PPCISD::ADDIS_GOT_TPREL_HA", SDTIntBinOp>;
149 def PPCldGotTprelL : SDNode<"PPCISD::LD_GOT_TPREL_L", SDTIntBinOp,
151 def PPCaddTls : SDNode<"PPCISD::ADD_TLS", SDTIntBinOp, []>;
152 def PPCaddisTlsgdHA : SDNode<"PPCISD::ADDIS_TLSGD_HA", SDTIntBinOp>;
153 def PPCaddiTlsgdL : SDNode<"PPCISD::ADDI_TLSGD_L", SDTIntBinOp>;
154 def PPCgetTlsAddr : SDNode<"PPCISD::GET_TLS_ADDR", SDTIntBinOp>;
155 def PPCaddiTlsgdLAddr : SDNode<"PPCISD::ADDI_TLSGD_L_ADDR",
156 SDTypeProfile<1, 3, [
157 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
158 SDTCisSameAs<0, 3>, SDTCisInt<0> ]>>;
159 def PPCaddisTlsldHA : SDNode<"PPCISD::ADDIS_TLSLD_HA", SDTIntBinOp>;
160 def PPCaddiTlsldL : SDNode<"PPCISD::ADDI_TLSLD_L", SDTIntBinOp>;
161 def PPCgetTlsldAddr : SDNode<"PPCISD::GET_TLSLD_ADDR", SDTIntBinOp>;
162 def PPCaddiTlsldLAddr : SDNode<"PPCISD::ADDI_TLSLD_L_ADDR",
163 SDTypeProfile<1, 3, [
164 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
165 SDTCisSameAs<0, 3>, SDTCisInt<0> ]>>;
166 def PPCaddisDtprelHA : SDNode<"PPCISD::ADDIS_DTPREL_HA", SDTIntBinOp>;
167 def PPCaddiDtprelL : SDNode<"PPCISD::ADDI_DTPREL_L", SDTIntBinOp>;
169 def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
170 def PPCxxsplt : SDNode<"PPCISD::XXSPLT", SDT_PPCVecSplat, []>;
171 def PPCxxinsert : SDNode<"PPCISD::XXINSERT", SDT_PPCVecInsert, []>;
172 def PPCvecshl : SDNode<"PPCISD::VECSHL", SDT_PPCVecShift, []>;
174 def PPCqvfperm : SDNode<"PPCISD::QVFPERM", SDT_PPCqvfperm, []>;
175 def PPCqvgpci : SDNode<"PPCISD::QVGPCI", SDT_PPCqvgpci, []>;
176 def PPCqvaligni : SDNode<"PPCISD::QVALIGNI", SDT_PPCqvaligni, []>;
177 def PPCqvesplati : SDNode<"PPCISD::QVESPLATI", SDT_PPCqvesplati, []>;
179 def PPCqbflt : SDNode<"PPCISD::QBFLT", SDT_PPCqbflt, []>;
181 def PPCqvlfsb : SDNode<"PPCISD::QVLFSb", SDT_PPCqvlfsb,
182 [SDNPHasChain, SDNPMayLoad]>;
184 def PPCcmpb : SDNode<"PPCISD::CMPB", SDTIntBinOp, []>;
186 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
187 // amounts. These nodes are generated by the multi-precision shift code.
188 def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>;
189 def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>;
190 def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>;
192 // These are target-independent nodes, but have target-specific formats.
193 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart,
194 [SDNPHasChain, SDNPOutGlue]>;
195 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd,
196 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
198 def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
199 def PPCcall : SDNode<"PPCISD::CALL", SDT_PPCCall,
200 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
202 def PPCcall_nop : SDNode<"PPCISD::CALL_NOP", SDT_PPCCall,
203 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
205 def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
206 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
207 def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTNone,
208 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
210 def PPCbctrl_load_toc : SDNode<"PPCISD::BCTRL_LOAD_TOC",
211 SDTypeProfile<0, 1, []>,
212 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
215 def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone,
216 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
218 def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret,
219 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
221 def PPCeh_sjlj_setjmp : SDNode<"PPCISD::EH_SJLJ_SETJMP",
222 SDTypeProfile<1, 1, [SDTCisInt<0>,
224 [SDNPHasChain, SDNPSideEffect]>;
225 def PPCeh_sjlj_longjmp : SDNode<"PPCISD::EH_SJLJ_LONGJMP",
226 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
227 [SDNPHasChain, SDNPSideEffect]>;
229 def SDT_PPCsc : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
230 def PPCsc : SDNode<"PPCISD::SC", SDT_PPCsc,
231 [SDNPHasChain, SDNPSideEffect]>;
233 def PPCclrbhrb : SDNode<"PPCISD::CLRBHRB", SDTNone,
234 [SDNPHasChain, SDNPSideEffect]>;
235 def PPCmfbhrbe : SDNode<"PPCISD::MFBHRBE", SDTIntBinOp, [SDNPHasChain]>;
236 def PPCrfebb : SDNode<"PPCISD::RFEBB", SDT_PPCsc,
237 [SDNPHasChain, SDNPSideEffect]>;
239 def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
240 def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutGlue]>;
242 def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
243 [SDNPHasChain, SDNPOptInGlue]>;
245 def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx,
246 [SDNPHasChain, SDNPMayLoad]>;
247 def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
248 [SDNPHasChain, SDNPMayStore]>;
250 // Instructions to set/unset CR bit 6 for SVR4 vararg calls
251 def PPCcr6set : SDNode<"PPCISD::CR6SET", SDTNone,
252 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
253 def PPCcr6unset : SDNode<"PPCISD::CR6UNSET", SDTNone,
254 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
256 // Instructions to support dynamic alloca.
257 def SDTDynOp : SDTypeProfile<1, 2, []>;
258 def SDTDynAreaOp : SDTypeProfile<1, 1, []>;
259 def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;
260 def PPCdynareaoffset : SDNode<"PPCISD::DYNAREAOFFSET", SDTDynAreaOp, [SDNPHasChain]>;
262 //===----------------------------------------------------------------------===//
263 // PowerPC specific transformation functions and pattern fragments.
266 def SHL32 : SDNodeXForm<imm, [{
267 // Transformation function: 31 - imm
268 return getI32Imm(31 - N->getZExtValue(), SDLoc(N));
271 def SRL32 : SDNodeXForm<imm, [{
272 // Transformation function: 32 - imm
273 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue(), SDLoc(N))
274 : getI32Imm(0, SDLoc(N));
277 def LO16 : SDNodeXForm<imm, [{
278 // Transformation function: get the low 16 bits.
279 return getI32Imm((unsigned short)N->getZExtValue(), SDLoc(N));
282 def HI16 : SDNodeXForm<imm, [{
283 // Transformation function: shift the immediate value down into the low bits.
284 return getI32Imm((unsigned)N->getZExtValue() >> 16, SDLoc(N));
287 def HA16 : SDNodeXForm<imm, [{
288 // Transformation function: shift the immediate value down into the low bits.
289 int Val = N->getZExtValue();
290 return getI32Imm((Val - (signed short)Val) >> 16, SDLoc(N));
292 def MB : SDNodeXForm<imm, [{
293 // Transformation function: get the start bit of a mask
295 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
296 return getI32Imm(mb, SDLoc(N));
299 def ME : SDNodeXForm<imm, [{
300 // Transformation function: get the end bit of a mask
302 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
303 return getI32Imm(me, SDLoc(N));
305 def maskimm32 : PatLeaf<(imm), [{
306 // maskImm predicate - True if immediate is a run of ones.
308 if (N->getValueType(0) == MVT::i32)
309 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
314 def imm32SExt16 : Operand<i32>, ImmLeaf<i32, [{
315 // imm32SExt16 predicate - True if the i32 immediate fits in a 16-bit
316 // sign extended field. Used by instructions like 'addi'.
317 return (int32_t)Imm == (short)Imm;
319 def imm64SExt16 : Operand<i64>, ImmLeaf<i64, [{
320 // imm64SExt16 predicate - True if the i64 immediate fits in a 16-bit
321 // sign extended field. Used by instructions like 'addi'.
322 return (int64_t)Imm == (short)Imm;
324 def immZExt16 : PatLeaf<(imm), [{
325 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
326 // field. Used by instructions like 'ori'.
327 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
329 def immAnyExt8 : ImmLeaf<i32, [{ return isInt<8>(Imm) || isUInt<8>(Imm); }]>;
330 def immSExt5NonZero : ImmLeaf<i32, [{ return Imm && isInt<5>(Imm); }]>;
332 // imm16Shifted* - These match immediates where the low 16-bits are zero. There
333 // are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are
334 // identical in 32-bit mode, but in 64-bit mode, they return true if the
335 // immediate fits into a sign/zero extended 32-bit immediate (with the low bits
337 def imm16ShiftedZExt : PatLeaf<(imm), [{
338 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
339 // immediate are set. Used by instructions like 'xoris'.
340 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0;
343 def imm16ShiftedSExt : PatLeaf<(imm), [{
344 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
345 // immediate are set. Used by instructions like 'addis'. Identical to
346 // imm16ShiftedZExt in 32-bit mode.
347 if (N->getZExtValue() & 0xFFFF) return false;
348 if (N->getValueType(0) == MVT::i32)
350 // For 64-bit, make sure it is sext right.
351 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue();
354 def imm64ZExt32 : Operand<i64>, ImmLeaf<i64, [{
355 // imm64ZExt32 predicate - True if the i64 immediate fits in a 32-bit
356 // zero extended field.
357 return isUInt<32>(Imm);
360 // Some r+i load/store instructions (such as LD, STD, LDU, etc.) that require
361 // restricted memrix (4-aligned) constants are alignment sensitive. If these
362 // offsets are hidden behind TOC entries than the values of the lower-order
363 // bits cannot be checked directly. As a result, we need to also incorporate
364 // an alignment check into the relevant patterns.
366 def aligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
367 return cast<LoadSDNode>(N)->getAlignment() >= 4;
369 def aligned4store : PatFrag<(ops node:$val, node:$ptr),
370 (store node:$val, node:$ptr), [{
371 return cast<StoreSDNode>(N)->getAlignment() >= 4;
373 def aligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
374 return cast<LoadSDNode>(N)->getAlignment() >= 4;
376 def aligned4pre_store : PatFrag<
377 (ops node:$val, node:$base, node:$offset),
378 (pre_store node:$val, node:$base, node:$offset), [{
379 return cast<StoreSDNode>(N)->getAlignment() >= 4;
382 def unaligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
383 return cast<LoadSDNode>(N)->getAlignment() < 4;
385 def unaligned4store : PatFrag<(ops node:$val, node:$ptr),
386 (store node:$val, node:$ptr), [{
387 return cast<StoreSDNode>(N)->getAlignment() < 4;
389 def unaligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
390 return cast<LoadSDNode>(N)->getAlignment() < 4;
393 //===----------------------------------------------------------------------===//
394 // PowerPC Flag Definitions.
396 class isPPC64 { bit PPC64 = 1; }
397 class isDOT { bit RC = 1; }
399 class RegConstraint<string C> {
400 string Constraints = C;
402 class NoEncode<string E> {
403 string DisableEncoding = E;
407 //===----------------------------------------------------------------------===//
408 // PowerPC Operand Definitions.
410 // In the default PowerPC assembler syntax, registers are specified simply
411 // by number, so they cannot be distinguished from immediate values (without
412 // looking at the opcode). This means that the default operand matching logic
413 // for the asm parser does not work, and we need to specify custom matchers.
414 // Since those can only be specified with RegisterOperand classes and not
415 // directly on the RegisterClass, all instructions patterns used by the asm
416 // parser need to use a RegisterOperand (instead of a RegisterClass) for
417 // all their register operands.
418 // For this purpose, we define one RegisterOperand for each RegisterClass,
419 // using the same name as the class, just in lower case.
421 def PPCRegGPRCAsmOperand : AsmOperandClass {
422 let Name = "RegGPRC"; let PredicateMethod = "isRegNumber";
424 def gprc : RegisterOperand<GPRC> {
425 let ParserMatchClass = PPCRegGPRCAsmOperand;
427 def PPCRegG8RCAsmOperand : AsmOperandClass {
428 let Name = "RegG8RC"; let PredicateMethod = "isRegNumber";
430 def g8rc : RegisterOperand<G8RC> {
431 let ParserMatchClass = PPCRegG8RCAsmOperand;
433 def PPCRegGPRCNoR0AsmOperand : AsmOperandClass {
434 let Name = "RegGPRCNoR0"; let PredicateMethod = "isRegNumber";
436 def gprc_nor0 : RegisterOperand<GPRC_NOR0> {
437 let ParserMatchClass = PPCRegGPRCNoR0AsmOperand;
439 def PPCRegG8RCNoX0AsmOperand : AsmOperandClass {
440 let Name = "RegG8RCNoX0"; let PredicateMethod = "isRegNumber";
442 def g8rc_nox0 : RegisterOperand<G8RC_NOX0> {
443 let ParserMatchClass = PPCRegG8RCNoX0AsmOperand;
445 def PPCRegF8RCAsmOperand : AsmOperandClass {
446 let Name = "RegF8RC"; let PredicateMethod = "isRegNumber";
448 def f8rc : RegisterOperand<F8RC> {
449 let ParserMatchClass = PPCRegF8RCAsmOperand;
451 def PPCRegF4RCAsmOperand : AsmOperandClass {
452 let Name = "RegF4RC"; let PredicateMethod = "isRegNumber";
454 def f4rc : RegisterOperand<F4RC> {
455 let ParserMatchClass = PPCRegF4RCAsmOperand;
457 def PPCRegVRRCAsmOperand : AsmOperandClass {
458 let Name = "RegVRRC"; let PredicateMethod = "isRegNumber";
460 def vrrc : RegisterOperand<VRRC> {
461 let ParserMatchClass = PPCRegVRRCAsmOperand;
463 def PPCRegVFRCAsmOperand : AsmOperandClass {
464 let Name = "RegVFRC"; let PredicateMethod = "isRegNumber";
466 def vfrc : RegisterOperand<VFRC> {
467 let ParserMatchClass = PPCRegVFRCAsmOperand;
469 def PPCRegCRBITRCAsmOperand : AsmOperandClass {
470 let Name = "RegCRBITRC"; let PredicateMethod = "isCRBitNumber";
472 def crbitrc : RegisterOperand<CRBITRC> {
473 let ParserMatchClass = PPCRegCRBITRCAsmOperand;
475 def PPCRegCRRCAsmOperand : AsmOperandClass {
476 let Name = "RegCRRC"; let PredicateMethod = "isCCRegNumber";
478 def crrc : RegisterOperand<CRRC> {
479 let ParserMatchClass = PPCRegCRRCAsmOperand;
481 def crrc0 : RegisterOperand<CRRC0> {
482 let ParserMatchClass = PPCRegCRRCAsmOperand;
485 def PPCU1ImmAsmOperand : AsmOperandClass {
486 let Name = "U1Imm"; let PredicateMethod = "isU1Imm";
487 let RenderMethod = "addImmOperands";
489 def u1imm : Operand<i32> {
490 let PrintMethod = "printU1ImmOperand";
491 let ParserMatchClass = PPCU1ImmAsmOperand;
494 def PPCU2ImmAsmOperand : AsmOperandClass {
495 let Name = "U2Imm"; let PredicateMethod = "isU2Imm";
496 let RenderMethod = "addImmOperands";
498 def u2imm : Operand<i32> {
499 let PrintMethod = "printU2ImmOperand";
500 let ParserMatchClass = PPCU2ImmAsmOperand;
503 def PPCATBitsAsHintAsmOperand : AsmOperandClass {
504 let Name = "ATBitsAsHint"; let PredicateMethod = "isATBitsAsHint";
505 let RenderMethod = "addImmOperands"; // Irrelevant, predicate always fails.
507 def atimm : Operand<i32> {
508 let PrintMethod = "printATBitsAsHint";
509 let ParserMatchClass = PPCATBitsAsHintAsmOperand;
512 def PPCU3ImmAsmOperand : AsmOperandClass {
513 let Name = "U3Imm"; let PredicateMethod = "isU3Imm";
514 let RenderMethod = "addImmOperands";
516 def u3imm : Operand<i32> {
517 let PrintMethod = "printU3ImmOperand";
518 let ParserMatchClass = PPCU3ImmAsmOperand;
521 def PPCU4ImmAsmOperand : AsmOperandClass {
522 let Name = "U4Imm"; let PredicateMethod = "isU4Imm";
523 let RenderMethod = "addImmOperands";
525 def u4imm : Operand<i32> {
526 let PrintMethod = "printU4ImmOperand";
527 let ParserMatchClass = PPCU4ImmAsmOperand;
529 def PPCS5ImmAsmOperand : AsmOperandClass {
530 let Name = "S5Imm"; let PredicateMethod = "isS5Imm";
531 let RenderMethod = "addImmOperands";
533 def s5imm : Operand<i32> {
534 let PrintMethod = "printS5ImmOperand";
535 let ParserMatchClass = PPCS5ImmAsmOperand;
536 let DecoderMethod = "decodeSImmOperand<5>";
538 def PPCU5ImmAsmOperand : AsmOperandClass {
539 let Name = "U5Imm"; let PredicateMethod = "isU5Imm";
540 let RenderMethod = "addImmOperands";
542 def u5imm : Operand<i32> {
543 let PrintMethod = "printU5ImmOperand";
544 let ParserMatchClass = PPCU5ImmAsmOperand;
545 let DecoderMethod = "decodeUImmOperand<5>";
547 def PPCU6ImmAsmOperand : AsmOperandClass {
548 let Name = "U6Imm"; let PredicateMethod = "isU6Imm";
549 let RenderMethod = "addImmOperands";
551 def u6imm : Operand<i32> {
552 let PrintMethod = "printU6ImmOperand";
553 let ParserMatchClass = PPCU6ImmAsmOperand;
554 let DecoderMethod = "decodeUImmOperand<6>";
556 def PPCU7ImmAsmOperand : AsmOperandClass {
557 let Name = "U7Imm"; let PredicateMethod = "isU7Imm";
558 let RenderMethod = "addImmOperands";
560 def u7imm : Operand<i32> {
561 let PrintMethod = "printU7ImmOperand";
562 let ParserMatchClass = PPCU7ImmAsmOperand;
563 let DecoderMethod = "decodeUImmOperand<7>";
565 def PPCU8ImmAsmOperand : AsmOperandClass {
566 let Name = "U8Imm"; let PredicateMethod = "isU8Imm";
567 let RenderMethod = "addImmOperands";
569 def u8imm : Operand<i32> {
570 let PrintMethod = "printU8ImmOperand";
571 let ParserMatchClass = PPCU8ImmAsmOperand;
572 let DecoderMethod = "decodeUImmOperand<8>";
574 def PPCU10ImmAsmOperand : AsmOperandClass {
575 let Name = "U10Imm"; let PredicateMethod = "isU10Imm";
576 let RenderMethod = "addImmOperands";
578 def u10imm : Operand<i32> {
579 let PrintMethod = "printU10ImmOperand";
580 let ParserMatchClass = PPCU10ImmAsmOperand;
581 let DecoderMethod = "decodeUImmOperand<10>";
583 def PPCU12ImmAsmOperand : AsmOperandClass {
584 let Name = "U12Imm"; let PredicateMethod = "isU12Imm";
585 let RenderMethod = "addImmOperands";
587 def u12imm : Operand<i32> {
588 let PrintMethod = "printU12ImmOperand";
589 let ParserMatchClass = PPCU12ImmAsmOperand;
590 let DecoderMethod = "decodeUImmOperand<12>";
592 def PPCS16ImmAsmOperand : AsmOperandClass {
593 let Name = "S16Imm"; let PredicateMethod = "isS16Imm";
594 let RenderMethod = "addS16ImmOperands";
596 def s16imm : Operand<i32> {
597 let PrintMethod = "printS16ImmOperand";
598 let EncoderMethod = "getImm16Encoding";
599 let ParserMatchClass = PPCS16ImmAsmOperand;
600 let DecoderMethod = "decodeSImmOperand<16>";
602 def PPCU16ImmAsmOperand : AsmOperandClass {
603 let Name = "U16Imm"; let PredicateMethod = "isU16Imm";
604 let RenderMethod = "addU16ImmOperands";
606 def u16imm : Operand<i32> {
607 let PrintMethod = "printU16ImmOperand";
608 let EncoderMethod = "getImm16Encoding";
609 let ParserMatchClass = PPCU16ImmAsmOperand;
610 let DecoderMethod = "decodeUImmOperand<16>";
612 def PPCS17ImmAsmOperand : AsmOperandClass {
613 let Name = "S17Imm"; let PredicateMethod = "isS17Imm";
614 let RenderMethod = "addS16ImmOperands";
616 def s17imm : Operand<i32> {
617 // This operand type is used for addis/lis to allow the assembler parser
618 // to accept immediates in the range -65536..65535 for compatibility with
619 // the GNU assembler. The operand is treated as 16-bit otherwise.
620 let PrintMethod = "printS16ImmOperand";
621 let EncoderMethod = "getImm16Encoding";
622 let ParserMatchClass = PPCS17ImmAsmOperand;
623 let DecoderMethod = "decodeSImmOperand<16>";
626 def fpimm0 : PatLeaf<(fpimm), [{ return N->isExactlyValue(+0.0); }]>;
628 def PPCDirectBrAsmOperand : AsmOperandClass {
629 let Name = "DirectBr"; let PredicateMethod = "isDirectBr";
630 let RenderMethod = "addBranchTargetOperands";
632 def directbrtarget : Operand<OtherVT> {
633 let PrintMethod = "printBranchOperand";
634 let EncoderMethod = "getDirectBrEncoding";
635 let ParserMatchClass = PPCDirectBrAsmOperand;
637 def absdirectbrtarget : Operand<OtherVT> {
638 let PrintMethod = "printAbsBranchOperand";
639 let EncoderMethod = "getAbsDirectBrEncoding";
640 let ParserMatchClass = PPCDirectBrAsmOperand;
642 def PPCCondBrAsmOperand : AsmOperandClass {
643 let Name = "CondBr"; let PredicateMethod = "isCondBr";
644 let RenderMethod = "addBranchTargetOperands";
646 def condbrtarget : Operand<OtherVT> {
647 let PrintMethod = "printBranchOperand";
648 let EncoderMethod = "getCondBrEncoding";
649 let ParserMatchClass = PPCCondBrAsmOperand;
651 def abscondbrtarget : Operand<OtherVT> {
652 let PrintMethod = "printAbsBranchOperand";
653 let EncoderMethod = "getAbsCondBrEncoding";
654 let ParserMatchClass = PPCCondBrAsmOperand;
656 def calltarget : Operand<iPTR> {
657 let PrintMethod = "printBranchOperand";
658 let EncoderMethod = "getDirectBrEncoding";
659 let ParserMatchClass = PPCDirectBrAsmOperand;
661 def abscalltarget : Operand<iPTR> {
662 let PrintMethod = "printAbsBranchOperand";
663 let EncoderMethod = "getAbsDirectBrEncoding";
664 let ParserMatchClass = PPCDirectBrAsmOperand;
666 def PPCCRBitMaskOperand : AsmOperandClass {
667 let Name = "CRBitMask"; let PredicateMethod = "isCRBitMask";
669 def crbitm: Operand<i8> {
670 let PrintMethod = "printcrbitm";
671 let EncoderMethod = "get_crbitm_encoding";
672 let DecoderMethod = "decodeCRBitMOperand";
673 let ParserMatchClass = PPCCRBitMaskOperand;
676 // A version of ptr_rc which excludes R0 (or X0 in 64-bit mode).
677 def PPCRegGxRCNoR0Operand : AsmOperandClass {
678 let Name = "RegGxRCNoR0"; let PredicateMethod = "isRegNumber";
680 def ptr_rc_nor0 : Operand<iPTR>, PointerLikeRegClass<1> {
681 let ParserMatchClass = PPCRegGxRCNoR0Operand;
683 // A version of ptr_rc usable with the asm parser.
684 def PPCRegGxRCOperand : AsmOperandClass {
685 let Name = "RegGxRC"; let PredicateMethod = "isRegNumber";
687 def ptr_rc_idx : Operand<iPTR>, PointerLikeRegClass<0> {
688 let ParserMatchClass = PPCRegGxRCOperand;
691 def PPCDispRIOperand : AsmOperandClass {
692 let Name = "DispRI"; let PredicateMethod = "isS16Imm";
693 let RenderMethod = "addS16ImmOperands";
695 def dispRI : Operand<iPTR> {
696 let ParserMatchClass = PPCDispRIOperand;
698 def PPCDispRIXOperand : AsmOperandClass {
699 let Name = "DispRIX"; let PredicateMethod = "isS16ImmX4";
700 let RenderMethod = "addImmOperands";
702 def dispRIX : Operand<iPTR> {
703 let ParserMatchClass = PPCDispRIXOperand;
705 def PPCDispRIX16Operand : AsmOperandClass {
706 let Name = "DispRIX16"; let PredicateMethod = "isS16ImmX16";
707 let RenderMethod = "addImmOperands";
709 def dispRIX16 : Operand<iPTR> {
710 let ParserMatchClass = PPCDispRIX16Operand;
712 def PPCDispSPE8Operand : AsmOperandClass {
713 let Name = "DispSPE8"; let PredicateMethod = "isU8ImmX8";
714 let RenderMethod = "addImmOperands";
716 def dispSPE8 : Operand<iPTR> {
717 let ParserMatchClass = PPCDispSPE8Operand;
719 def PPCDispSPE4Operand : AsmOperandClass {
720 let Name = "DispSPE4"; let PredicateMethod = "isU7ImmX4";
721 let RenderMethod = "addImmOperands";
723 def dispSPE4 : Operand<iPTR> {
724 let ParserMatchClass = PPCDispSPE4Operand;
726 def PPCDispSPE2Operand : AsmOperandClass {
727 let Name = "DispSPE2"; let PredicateMethod = "isU6ImmX2";
728 let RenderMethod = "addImmOperands";
730 def dispSPE2 : Operand<iPTR> {
731 let ParserMatchClass = PPCDispSPE2Operand;
734 def memri : Operand<iPTR> {
735 let PrintMethod = "printMemRegImm";
736 let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg);
737 let EncoderMethod = "getMemRIEncoding";
738 let DecoderMethod = "decodeMemRIOperands";
740 def memrr : Operand<iPTR> {
741 let PrintMethod = "printMemRegReg";
742 let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg, ptr_rc_idx:$offreg);
744 def memrix : Operand<iPTR> { // memri where the imm is 4-aligned.
745 let PrintMethod = "printMemRegImm";
746 let MIOperandInfo = (ops dispRIX:$imm, ptr_rc_nor0:$reg);
747 let EncoderMethod = "getMemRIXEncoding";
748 let DecoderMethod = "decodeMemRIXOperands";
750 def memrix16 : Operand<iPTR> { // memri, imm is 16-aligned, 12-bit, Inst{16:27}
751 let PrintMethod = "printMemRegImm";
752 let MIOperandInfo = (ops dispRIX16:$imm, ptr_rc_nor0:$reg);
753 let EncoderMethod = "getMemRIX16Encoding";
754 let DecoderMethod = "decodeMemRIX16Operands";
756 def spe8dis : Operand<iPTR> { // SPE displacement where the imm is 8-aligned.
757 let PrintMethod = "printMemRegImm";
758 let MIOperandInfo = (ops dispSPE8:$imm, ptr_rc_nor0:$reg);
759 let EncoderMethod = "getSPE8DisEncoding";
761 def spe4dis : Operand<iPTR> { // SPE displacement where the imm is 4-aligned.
762 let PrintMethod = "printMemRegImm";
763 let MIOperandInfo = (ops dispSPE4:$imm, ptr_rc_nor0:$reg);
764 let EncoderMethod = "getSPE4DisEncoding";
766 def spe2dis : Operand<iPTR> { // SPE displacement where the imm is 2-aligned.
767 let PrintMethod = "printMemRegImm";
768 let MIOperandInfo = (ops dispSPE2:$imm, ptr_rc_nor0:$reg);
769 let EncoderMethod = "getSPE2DisEncoding";
772 // A single-register address. This is used with the SjLj
773 // pseudo-instructions.
774 def memr : Operand<iPTR> {
775 let MIOperandInfo = (ops ptr_rc:$ptrreg);
777 def PPCTLSRegOperand : AsmOperandClass {
778 let Name = "TLSReg"; let PredicateMethod = "isTLSReg";
779 let RenderMethod = "addTLSRegOperands";
781 def tlsreg32 : Operand<i32> {
782 let EncoderMethod = "getTLSRegEncoding";
783 let ParserMatchClass = PPCTLSRegOperand;
785 def tlsgd32 : Operand<i32> {}
786 def tlscall32 : Operand<i32> {
787 let PrintMethod = "printTLSCall";
788 let MIOperandInfo = (ops calltarget:$func, tlsgd32:$sym);
789 let EncoderMethod = "getTLSCallEncoding";
792 // PowerPC Predicate operand.
793 def pred : Operand<OtherVT> {
794 let PrintMethod = "printPredicateOperand";
795 let MIOperandInfo = (ops i32imm:$bibo, crrc:$reg);
798 // Define PowerPC specific addressing mode.
799 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>;
800 def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>;
801 def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
802 def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmX4", [], []>; // "std"
804 // The address in a single register. This is used with the SjLj
805 // pseudo-instructions.
806 def addr : ComplexPattern<iPTR, 1, "SelectAddr",[], []>;
808 /// This is just the offset part of iaddr, used for preinc.
809 def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
811 //===----------------------------------------------------------------------===//
812 // PowerPC Instruction Predicate Definitions.
813 def In32BitMode : Predicate<"!PPCSubTarget->isPPC64()">;
814 def In64BitMode : Predicate<"PPCSubTarget->isPPC64()">;
815 def IsBookE : Predicate<"PPCSubTarget->isBookE()">;
816 def IsNotBookE : Predicate<"!PPCSubTarget->isBookE()">;
817 def HasOnlyMSYNC : Predicate<"PPCSubTarget->hasOnlyMSYNC()">;
818 def HasSYNC : Predicate<"!PPCSubTarget->hasOnlyMSYNC()">;
819 def IsPPC4xx : Predicate<"PPCSubTarget->isPPC4xx()">;
820 def IsPPC6xx : Predicate<"PPCSubTarget->isPPC6xx()">;
821 def IsE500 : Predicate<"PPCSubTarget->isE500()">;
822 def HasSPE : Predicate<"PPCSubTarget->HasSPE()">;
823 def HasICBT : Predicate<"PPCSubTarget->hasICBT()">;
824 def HasPartwordAtomics : Predicate<"PPCSubTarget->hasPartwordAtomics()">;
825 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">;
826 def NaNsFPMath : Predicate<"!TM.Options.NoNaNsFPMath">;
827 def HasBPERMD : Predicate<"PPCSubTarget->hasBPERMD()">;
828 def HasExtDiv : Predicate<"PPCSubTarget->hasExtDiv()">;
829 def IsISA3_0 : Predicate<"PPCSubTarget->isISA3_0()">;
831 //===----------------------------------------------------------------------===//
832 // PowerPC Multiclass Definitions.
834 multiclass XForm_6r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
835 string asmbase, string asmstr, InstrItinClass itin,
837 let BaseName = asmbase in {
838 def NAME : XForm_6<opcode, xo, OOL, IOL,
839 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
840 pattern>, RecFormRel;
842 def o : XForm_6<opcode, xo, OOL, IOL,
843 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
844 []>, isDOT, RecFormRel;
848 multiclass XForm_6rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
849 string asmbase, string asmstr, InstrItinClass itin,
851 let BaseName = asmbase in {
852 let Defs = [CARRY] in
853 def NAME : XForm_6<opcode, xo, OOL, IOL,
854 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
855 pattern>, RecFormRel;
856 let Defs = [CARRY, CR0] in
857 def o : XForm_6<opcode, xo, OOL, IOL,
858 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
859 []>, isDOT, RecFormRel;
863 multiclass XForm_10rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
864 string asmbase, string asmstr, InstrItinClass itin,
866 let BaseName = asmbase in {
867 let Defs = [CARRY] in
868 def NAME : XForm_10<opcode, xo, OOL, IOL,
869 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
870 pattern>, RecFormRel;
871 let Defs = [CARRY, CR0] in
872 def o : XForm_10<opcode, xo, OOL, IOL,
873 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
874 []>, isDOT, RecFormRel;
878 multiclass XForm_11r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
879 string asmbase, string asmstr, InstrItinClass itin,
881 let BaseName = asmbase in {
882 def NAME : XForm_11<opcode, xo, OOL, IOL,
883 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
884 pattern>, RecFormRel;
886 def o : XForm_11<opcode, xo, OOL, IOL,
887 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
888 []>, isDOT, RecFormRel;
892 multiclass XOForm_1r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
893 string asmbase, string asmstr, InstrItinClass itin,
895 let BaseName = asmbase in {
896 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
897 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
898 pattern>, RecFormRel;
900 def o : XOForm_1<opcode, xo, oe, OOL, IOL,
901 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
902 []>, isDOT, RecFormRel;
906 // Multiclass for instructions for which the non record form is not cracked
907 // and the record form is cracked (i.e. divw, mullw, etc.)
908 multiclass XOForm_1rcr<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
909 string asmbase, string asmstr, InstrItinClass itin,
911 let BaseName = asmbase in {
912 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
913 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
914 pattern>, RecFormRel;
916 def o : XOForm_1<opcode, xo, oe, OOL, IOL,
917 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
918 []>, isDOT, RecFormRel, PPC970_DGroup_First,
919 PPC970_DGroup_Cracked;
923 multiclass XOForm_1rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
924 string asmbase, string asmstr, InstrItinClass itin,
926 let BaseName = asmbase in {
927 let Defs = [CARRY] in
928 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
929 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
930 pattern>, RecFormRel;
931 let Defs = [CARRY, CR0] in
932 def o : XOForm_1<opcode, xo, oe, OOL, IOL,
933 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
934 []>, isDOT, RecFormRel;
938 multiclass XOForm_3r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
939 string asmbase, string asmstr, InstrItinClass itin,
941 let BaseName = asmbase in {
942 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
943 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
944 pattern>, RecFormRel;
946 def o : XOForm_3<opcode, xo, oe, OOL, IOL,
947 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
948 []>, isDOT, RecFormRel;
952 multiclass XOForm_3rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
953 string asmbase, string asmstr, InstrItinClass itin,
955 let BaseName = asmbase in {
956 let Defs = [CARRY] in
957 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
958 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
959 pattern>, RecFormRel;
960 let Defs = [CARRY, CR0] in
961 def o : XOForm_3<opcode, xo, oe, OOL, IOL,
962 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
963 []>, isDOT, RecFormRel;
967 multiclass MForm_2r<bits<6> opcode, dag OOL, dag IOL,
968 string asmbase, string asmstr, InstrItinClass itin,
970 let BaseName = asmbase in {
971 def NAME : MForm_2<opcode, OOL, IOL,
972 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
973 pattern>, RecFormRel;
975 def o : MForm_2<opcode, OOL, IOL,
976 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
977 []>, isDOT, RecFormRel;
981 multiclass MDForm_1r<bits<6> opcode, bits<3> xo, dag OOL, dag IOL,
982 string asmbase, string asmstr, InstrItinClass itin,
984 let BaseName = asmbase in {
985 def NAME : MDForm_1<opcode, xo, OOL, IOL,
986 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
987 pattern>, RecFormRel;
989 def o : MDForm_1<opcode, xo, OOL, IOL,
990 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
991 []>, isDOT, RecFormRel;
995 multiclass MDSForm_1r<bits<6> opcode, bits<4> xo, dag OOL, dag IOL,
996 string asmbase, string asmstr, InstrItinClass itin,
998 let BaseName = asmbase in {
999 def NAME : MDSForm_1<opcode, xo, OOL, IOL,
1000 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
1001 pattern>, RecFormRel;
1003 def o : MDSForm_1<opcode, xo, OOL, IOL,
1004 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
1005 []>, isDOT, RecFormRel;
1009 multiclass XSForm_1rc<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
1010 string asmbase, string asmstr, InstrItinClass itin,
1011 list<dag> pattern> {
1012 let BaseName = asmbase in {
1013 let Defs = [CARRY] in
1014 def NAME : XSForm_1<opcode, xo, OOL, IOL,
1015 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
1016 pattern>, RecFormRel;
1017 let Defs = [CARRY, CR0] in
1018 def o : XSForm_1<opcode, xo, OOL, IOL,
1019 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
1020 []>, isDOT, RecFormRel;
1024 multiclass XForm_26r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
1025 string asmbase, string asmstr, InstrItinClass itin,
1026 list<dag> pattern> {
1027 let BaseName = asmbase in {
1028 def NAME : XForm_26<opcode, xo, OOL, IOL,
1029 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
1030 pattern>, RecFormRel;
1032 def o : XForm_26<opcode, xo, OOL, IOL,
1033 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
1034 []>, isDOT, RecFormRel;
1038 multiclass XForm_28r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
1039 string asmbase, string asmstr, InstrItinClass itin,
1040 list<dag> pattern> {
1041 let BaseName = asmbase in {
1042 def NAME : XForm_28<opcode, xo, OOL, IOL,
1043 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
1044 pattern>, RecFormRel;
1046 def o : XForm_28<opcode, xo, OOL, IOL,
1047 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
1048 []>, isDOT, RecFormRel;
1052 multiclass AForm_1r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
1053 string asmbase, string asmstr, InstrItinClass itin,
1054 list<dag> pattern> {
1055 let BaseName = asmbase in {
1056 def NAME : AForm_1<opcode, xo, OOL, IOL,
1057 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
1058 pattern>, RecFormRel;
1060 def o : AForm_1<opcode, xo, OOL, IOL,
1061 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
1062 []>, isDOT, RecFormRel;
1066 multiclass AForm_2r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
1067 string asmbase, string asmstr, InstrItinClass itin,
1068 list<dag> pattern> {
1069 let BaseName = asmbase in {
1070 def NAME : AForm_2<opcode, xo, OOL, IOL,
1071 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
1072 pattern>, RecFormRel;
1074 def o : AForm_2<opcode, xo, OOL, IOL,
1075 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
1076 []>, isDOT, RecFormRel;
1080 multiclass AForm_3r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
1081 string asmbase, string asmstr, InstrItinClass itin,
1082 list<dag> pattern> {
1083 let BaseName = asmbase in {
1084 def NAME : AForm_3<opcode, xo, OOL, IOL,
1085 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
1086 pattern>, RecFormRel;
1088 def o : AForm_3<opcode, xo, OOL, IOL,
1089 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
1090 []>, isDOT, RecFormRel;
1094 //===----------------------------------------------------------------------===//
1095 // PowerPC Instruction Definitions.
1097 // Pseudo-instructions:
1099 let hasCtrlDep = 1 in {
1100 let Defs = [R1], Uses = [R1] in {
1101 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "#ADJCALLSTACKDOWN $amt",
1102 [(callseq_start timm:$amt)]>;
1103 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "#ADJCALLSTACKUP $amt1 $amt2",
1104 [(callseq_end timm:$amt1, timm:$amt2)]>;
1107 def UPDATE_VRSAVE : Pseudo<(outs gprc:$rD), (ins gprc:$rS),
1108 "UPDATE_VRSAVE $rD, $rS", []>;
1111 let Defs = [R1], Uses = [R1] in
1112 def DYNALLOC : Pseudo<(outs gprc:$result), (ins gprc:$negsize, memri:$fpsi), "#DYNALLOC",
1114 (PPCdynalloc i32:$negsize, iaddr:$fpsi))]>;
1115 def DYNAREAOFFSET : Pseudo<(outs i32imm:$result), (ins memri:$fpsi), "#DYNAREAOFFSET",
1116 [(set i32:$result, (PPCdynareaoffset iaddr:$fpsi))]>;
1118 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
1119 // instruction selection into a branch sequence.
1120 let usesCustomInserter = 1, // Expanded after instruction selection.
1121 PPC970_Single = 1 in {
1122 // Note that SELECT_CC_I4 and SELECT_CC_I8 use the no-r0 register classes
1123 // because either operand might become the first operand in an isel, and
1124 // that operand cannot be r0.
1125 def SELECT_CC_I4 : Pseudo<(outs gprc:$dst), (ins crrc:$cond,
1126 gprc_nor0:$T, gprc_nor0:$F,
1127 i32imm:$BROPC), "#SELECT_CC_I4",
1129 def SELECT_CC_I8 : Pseudo<(outs g8rc:$dst), (ins crrc:$cond,
1130 g8rc_nox0:$T, g8rc_nox0:$F,
1131 i32imm:$BROPC), "#SELECT_CC_I8",
1133 def SELECT_CC_F4 : Pseudo<(outs f4rc:$dst), (ins crrc:$cond, f4rc:$T, f4rc:$F,
1134 i32imm:$BROPC), "#SELECT_CC_F4",
1136 def SELECT_CC_F8 : Pseudo<(outs f8rc:$dst), (ins crrc:$cond, f8rc:$T, f8rc:$F,
1137 i32imm:$BROPC), "#SELECT_CC_F8",
1139 def SELECT_CC_VRRC: Pseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F,
1140 i32imm:$BROPC), "#SELECT_CC_VRRC",
1143 // SELECT_* pseudo instructions, like SELECT_CC_* but taking condition
1144 // register bit directly.
1145 def SELECT_I4 : Pseudo<(outs gprc:$dst), (ins crbitrc:$cond,
1146 gprc_nor0:$T, gprc_nor0:$F), "#SELECT_I4",
1147 [(set i32:$dst, (select i1:$cond, i32:$T, i32:$F))]>;
1148 def SELECT_I8 : Pseudo<(outs g8rc:$dst), (ins crbitrc:$cond,
1149 g8rc_nox0:$T, g8rc_nox0:$F), "#SELECT_I8",
1150 [(set i64:$dst, (select i1:$cond, i64:$T, i64:$F))]>;
1151 def SELECT_F4 : Pseudo<(outs f4rc:$dst), (ins crbitrc:$cond,
1152 f4rc:$T, f4rc:$F), "#SELECT_F4",
1153 [(set f32:$dst, (select i1:$cond, f32:$T, f32:$F))]>;
1154 def SELECT_F8 : Pseudo<(outs f8rc:$dst), (ins crbitrc:$cond,
1155 f8rc:$T, f8rc:$F), "#SELECT_F8",
1156 [(set f64:$dst, (select i1:$cond, f64:$T, f64:$F))]>;
1157 def SELECT_VRRC: Pseudo<(outs vrrc:$dst), (ins crbitrc:$cond,
1158 vrrc:$T, vrrc:$F), "#SELECT_VRRC",
1160 (select i1:$cond, v4i32:$T, v4i32:$F))]>;
1163 // SPILL_CR - Indicate that we're dumping the CR register, so we'll need to
1164 // scavenge a register for it.
1165 let mayStore = 1 in {
1166 def SPILL_CR : Pseudo<(outs), (ins crrc:$cond, memri:$F),
1168 def SPILL_CRBIT : Pseudo<(outs), (ins crbitrc:$cond, memri:$F),
1169 "#SPILL_CRBIT", []>;
1172 // RESTORE_CR - Indicate that we're restoring the CR register (previously
1173 // spilled), so we'll need to scavenge a register for it.
1174 let mayLoad = 1 in {
1175 def RESTORE_CR : Pseudo<(outs crrc:$cond), (ins memri:$F),
1177 def RESTORE_CRBIT : Pseudo<(outs crbitrc:$cond), (ins memri:$F),
1178 "#RESTORE_CRBIT", []>;
1181 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
1182 let isReturn = 1, Uses = [LR, RM] in
1183 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB,
1184 [(retflag)]>, Requires<[In32BitMode]>;
1185 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in {
1186 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
1189 let isCodeGenOnly = 1 in {
1190 def BCCCTR : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond),
1191 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB,
1194 def BCCTR : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi),
1195 "bcctr 12, $bi, 0", IIC_BrB, []>;
1196 def BCCTRn : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi),
1197 "bcctr 4, $bi, 0", IIC_BrB, []>;
1203 def MovePCtoLR : Pseudo<(outs), (ins), "#MovePCtoLR", []>,
1206 def MoveGOTtoLR : Pseudo<(outs), (ins), "#MoveGOTtoLR", []>,
1209 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
1210 let isBarrier = 1 in {
1211 def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst),
1214 def BA : IForm<18, 1, 0, (outs), (ins absdirectbrtarget:$dst),
1215 "ba $dst", IIC_BrB, []>;
1218 // BCC represents an arbitrary conditional branch on a predicate.
1219 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use
1220 // a two-value operand where a dag node expects two operands. :(
1221 let isCodeGenOnly = 1 in {
1222 def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst),
1223 "b${cond:cc}${cond:pm} ${cond:reg}, $dst"
1224 /*[(PPCcondbranch crrc:$crS, imm:$opc, bb:$dst)]*/>;
1225 def BCCA : BForm<16, 1, 0, (outs), (ins pred:$cond, abscondbrtarget:$dst),
1226 "b${cond:cc}a${cond:pm} ${cond:reg}, $dst">;
1228 let isReturn = 1, Uses = [LR, RM] in
1229 def BCCLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$cond),
1230 "b${cond:cc}lr${cond:pm} ${cond:reg}", IIC_BrB, []>;
1233 let isCodeGenOnly = 1 in {
1234 let Pattern = [(brcond i1:$bi, bb:$dst)] in
1235 def BC : BForm_4<16, 12, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst),
1236 "bc 12, $bi, $dst">;
1238 let Pattern = [(brcond (not i1:$bi), bb:$dst)] in
1239 def BCn : BForm_4<16, 4, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst),
1242 let isReturn = 1, Uses = [LR, RM] in
1243 def BCLR : XLForm_2_br2<19, 16, 12, 0, (outs), (ins crbitrc:$bi),
1244 "bclr 12, $bi, 0", IIC_BrB, []>;
1245 def BCLRn : XLForm_2_br2<19, 16, 4, 0, (outs), (ins crbitrc:$bi),
1246 "bclr 4, $bi, 0", IIC_BrB, []>;
1249 let isReturn = 1, Defs = [CTR], Uses = [CTR, LR, RM] in {
1250 def BDZLR : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
1251 "bdzlr", IIC_BrB, []>;
1252 def BDNZLR : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
1253 "bdnzlr", IIC_BrB, []>;
1254 def BDZLRp : XLForm_2_ext<19, 16, 27, 0, 0, (outs), (ins),
1255 "bdzlr+", IIC_BrB, []>;
1256 def BDNZLRp: XLForm_2_ext<19, 16, 25, 0, 0, (outs), (ins),
1257 "bdnzlr+", IIC_BrB, []>;
1258 def BDZLRm : XLForm_2_ext<19, 16, 26, 0, 0, (outs), (ins),
1259 "bdzlr-", IIC_BrB, []>;
1260 def BDNZLRm: XLForm_2_ext<19, 16, 24, 0, 0, (outs), (ins),
1261 "bdnzlr-", IIC_BrB, []>;
1264 let Defs = [CTR], Uses = [CTR] in {
1265 def BDZ : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
1267 def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
1269 def BDZA : BForm_1<16, 18, 1, 0, (outs), (ins abscondbrtarget:$dst),
1271 def BDNZA : BForm_1<16, 16, 1, 0, (outs), (ins abscondbrtarget:$dst),
1273 def BDZp : BForm_1<16, 27, 0, 0, (outs), (ins condbrtarget:$dst),
1275 def BDNZp: BForm_1<16, 25, 0, 0, (outs), (ins condbrtarget:$dst),
1277 def BDZAp : BForm_1<16, 27, 1, 0, (outs), (ins abscondbrtarget:$dst),
1279 def BDNZAp: BForm_1<16, 25, 1, 0, (outs), (ins abscondbrtarget:$dst),
1281 def BDZm : BForm_1<16, 26, 0, 0, (outs), (ins condbrtarget:$dst),
1283 def BDNZm: BForm_1<16, 24, 0, 0, (outs), (ins condbrtarget:$dst),
1285 def BDZAm : BForm_1<16, 26, 1, 0, (outs), (ins abscondbrtarget:$dst),
1287 def BDNZAm: BForm_1<16, 24, 1, 0, (outs), (ins abscondbrtarget:$dst),
1292 // The unconditional BCL used by the SjLj setjmp code.
1293 let isCall = 1, hasCtrlDep = 1, isCodeGenOnly = 1, PPC970_Unit = 7 in {
1294 let Defs = [LR], Uses = [RM] in {
1295 def BCLalways : BForm_2<16, 20, 31, 0, 1, (outs), (ins condbrtarget:$dst),
1296 "bcl 20, 31, $dst">;
1300 let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
1301 // Convenient aliases for call instructions
1302 let Uses = [RM] in {
1303 def BL : IForm<18, 0, 1, (outs), (ins calltarget:$func),
1304 "bl $func", IIC_BrB, []>; // See Pat patterns below.
1305 def BLA : IForm<18, 1, 1, (outs), (ins abscalltarget:$func),
1306 "bla $func", IIC_BrB, [(PPCcall (i32 imm:$func))]>;
1308 let isCodeGenOnly = 1 in {
1309 def BL_TLS : IForm<18, 0, 1, (outs), (ins tlscall32:$func),
1310 "bl $func", IIC_BrB, []>;
1311 def BCCL : BForm<16, 0, 1, (outs), (ins pred:$cond, condbrtarget:$dst),
1312 "b${cond:cc}l${cond:pm} ${cond:reg}, $dst">;
1313 def BCCLA : BForm<16, 1, 1, (outs), (ins pred:$cond, abscondbrtarget:$dst),
1314 "b${cond:cc}la${cond:pm} ${cond:reg}, $dst">;
1316 def BCL : BForm_4<16, 12, 0, 1, (outs),
1317 (ins crbitrc:$bi, condbrtarget:$dst),
1318 "bcl 12, $bi, $dst">;
1319 def BCLn : BForm_4<16, 4, 0, 1, (outs),
1320 (ins crbitrc:$bi, condbrtarget:$dst),
1321 "bcl 4, $bi, $dst">;
1324 let Uses = [CTR, RM] in {
1325 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
1326 "bctrl", IIC_BrB, [(PPCbctrl)]>,
1327 Requires<[In32BitMode]>;
1329 let isCodeGenOnly = 1 in {
1330 def BCCCTRL : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond),
1331 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB,
1334 def BCCTRL : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi),
1335 "bcctrl 12, $bi, 0", IIC_BrB, []>;
1336 def BCCTRLn : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi),
1337 "bcctrl 4, $bi, 0", IIC_BrB, []>;
1340 let Uses = [LR, RM] in {
1341 def BLRL : XLForm_2_ext<19, 16, 20, 0, 1, (outs), (ins),
1342 "blrl", IIC_BrB, []>;
1344 let isCodeGenOnly = 1 in {
1345 def BCCLRL : XLForm_2_br<19, 16, 1, (outs), (ins pred:$cond),
1346 "b${cond:cc}lrl${cond:pm} ${cond:reg}", IIC_BrB,
1349 def BCLRL : XLForm_2_br2<19, 16, 12, 1, (outs), (ins crbitrc:$bi),
1350 "bclrl 12, $bi, 0", IIC_BrB, []>;
1351 def BCLRLn : XLForm_2_br2<19, 16, 4, 1, (outs), (ins crbitrc:$bi),
1352 "bclrl 4, $bi, 0", IIC_BrB, []>;
1355 let Defs = [CTR], Uses = [CTR, RM] in {
1356 def BDZL : BForm_1<16, 18, 0, 1, (outs), (ins condbrtarget:$dst),
1358 def BDNZL : BForm_1<16, 16, 0, 1, (outs), (ins condbrtarget:$dst),
1360 def BDZLA : BForm_1<16, 18, 1, 1, (outs), (ins abscondbrtarget:$dst),
1362 def BDNZLA : BForm_1<16, 16, 1, 1, (outs), (ins abscondbrtarget:$dst),
1364 def BDZLp : BForm_1<16, 27, 0, 1, (outs), (ins condbrtarget:$dst),
1366 def BDNZLp: BForm_1<16, 25, 0, 1, (outs), (ins condbrtarget:$dst),
1368 def BDZLAp : BForm_1<16, 27, 1, 1, (outs), (ins abscondbrtarget:$dst),
1370 def BDNZLAp: BForm_1<16, 25, 1, 1, (outs), (ins abscondbrtarget:$dst),
1372 def BDZLm : BForm_1<16, 26, 0, 1, (outs), (ins condbrtarget:$dst),
1374 def BDNZLm: BForm_1<16, 24, 0, 1, (outs), (ins condbrtarget:$dst),
1376 def BDZLAm : BForm_1<16, 26, 1, 1, (outs), (ins abscondbrtarget:$dst),
1378 def BDNZLAm: BForm_1<16, 24, 1, 1, (outs), (ins abscondbrtarget:$dst),
1381 let Defs = [CTR], Uses = [CTR, LR, RM] in {
1382 def BDZLRL : XLForm_2_ext<19, 16, 18, 0, 1, (outs), (ins),
1383 "bdzlrl", IIC_BrB, []>;
1384 def BDNZLRL : XLForm_2_ext<19, 16, 16, 0, 1, (outs), (ins),
1385 "bdnzlrl", IIC_BrB, []>;
1386 def BDZLRLp : XLForm_2_ext<19, 16, 27, 0, 1, (outs), (ins),
1387 "bdzlrl+", IIC_BrB, []>;
1388 def BDNZLRLp: XLForm_2_ext<19, 16, 25, 0, 1, (outs), (ins),
1389 "bdnzlrl+", IIC_BrB, []>;
1390 def BDZLRLm : XLForm_2_ext<19, 16, 26, 0, 1, (outs), (ins),
1391 "bdzlrl-", IIC_BrB, []>;
1392 def BDNZLRLm: XLForm_2_ext<19, 16, 24, 0, 1, (outs), (ins),
1393 "bdnzlrl-", IIC_BrB, []>;
1397 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1398 def TCRETURNdi :Pseudo< (outs),
1399 (ins calltarget:$dst, i32imm:$offset),
1400 "#TC_RETURNd $dst $offset",
1404 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1405 def TCRETURNai :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset),
1406 "#TC_RETURNa $func $offset",
1407 [(PPCtc_return (i32 imm:$func), imm:$offset)]>;
1409 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1410 def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset),
1411 "#TC_RETURNr $dst $offset",
1415 let isCodeGenOnly = 1 in {
1417 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
1418 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in
1419 def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
1420 []>, Requires<[In32BitMode]>;
1422 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
1423 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
1424 def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
1428 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
1429 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
1430 def TAILBA : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst),
1436 let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
1438 def EH_SjLj_SetJmp32 : Pseudo<(outs gprc:$dst), (ins memr:$buf),
1439 "#EH_SJLJ_SETJMP32",
1440 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
1441 Requires<[In32BitMode]>;
1442 let isTerminator = 1 in
1443 def EH_SjLj_LongJmp32 : Pseudo<(outs), (ins memr:$buf),
1444 "#EH_SJLJ_LONGJMP32",
1445 [(PPCeh_sjlj_longjmp addr:$buf)]>,
1446 Requires<[In32BitMode]>;
1449 // This pseudo is never removed from the function, as it serves as
1450 // a terminator. Size is set to 0 to prevent the builtin assembler
1451 // from emitting it.
1452 let isBranch = 1, isTerminator = 1, Size = 0 in {
1453 def EH_SjLj_Setup : Pseudo<(outs), (ins directbrtarget:$dst),
1454 "#EH_SjLj_Setup\t$dst", []>;
1458 let PPC970_Unit = 7 in {
1459 def SC : SCForm<17, 1, (outs), (ins i32imm:$lev),
1460 "sc $lev", IIC_BrB, [(PPCsc (i32 imm:$lev))]>;
1463 // Branch history rolling buffer.
1464 def CLRBHRB : XForm_0<31, 430, (outs), (ins), "clrbhrb", IIC_BrB,
1466 PPC970_DGroup_Single;
1467 // The $dmy argument used for MFBHRBE is not needed; however, including
1468 // it avoids automatic generation of PPCFastISel::fastEmit_i(), which
1469 // interferes with necessary special handling (see PPCFastISel.cpp).
1470 def MFBHRBE : XFXForm_3p<31, 302, (outs gprc:$rD),
1471 (ins u10imm:$imm, u10imm:$dmy),
1472 "mfbhrbe $rD, $imm", IIC_BrB,
1474 (PPCmfbhrbe imm:$imm, imm:$dmy))]>,
1475 PPC970_DGroup_First;
1477 def RFEBB : XLForm_S<19, 146, (outs), (ins u1imm:$imm), "rfebb $imm",
1478 IIC_BrB, [(PPCrfebb (i32 imm:$imm))]>,
1479 PPC970_DGroup_Single;
1481 // DCB* instructions.
1482 def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst), "dcba $dst",
1483 IIC_LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
1484 PPC970_DGroup_Single;
1485 def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst), "dcbi $dst",
1486 IIC_LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
1487 PPC970_DGroup_Single;
1488 def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst), "dcbst $dst",
1489 IIC_LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>,
1490 PPC970_DGroup_Single;
1491 def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst), "dcbz $dst",
1492 IIC_LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
1493 PPC970_DGroup_Single;
1494 def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst), "dcbzl $dst",
1495 IIC_LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
1496 PPC970_DGroup_Single;
1498 def DCBF : DCB_Form_hint<86, (outs), (ins u5imm:$TH, memrr:$dst),
1499 "dcbf $dst, $TH", IIC_LdStDCBF, []>,
1500 PPC970_DGroup_Single;
1502 let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in {
1503 def DCBT : DCB_Form_hint<278, (outs), (ins u5imm:$TH, memrr:$dst),
1504 "dcbt $dst, $TH", IIC_LdStDCBF, []>,
1505 PPC970_DGroup_Single;
1506 def DCBTST : DCB_Form_hint<246, (outs), (ins u5imm:$TH, memrr:$dst),
1507 "dcbtst $dst, $TH", IIC_LdStDCBF, []>,
1508 PPC970_DGroup_Single;
1509 } // hasSideEffects = 0
1511 def ICBLC : XForm_icbt<31, 230, (outs), (ins u4imm:$CT, memrr:$src),
1512 "icblc $CT, $src", IIC_LdStStore>, Requires<[HasICBT]>;
1513 def ICBLQ : XForm_icbt<31, 198, (outs), (ins u4imm:$CT, memrr:$src),
1514 "icblq. $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>;
1515 def ICBT : XForm_icbt<31, 22, (outs), (ins u4imm:$CT, memrr:$src),
1516 "icbt $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>;
1517 def ICBTLS : XForm_icbt<31, 486, (outs), (ins u4imm:$CT, memrr:$src),
1518 "icbtls $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>;
1520 def : Pat<(int_ppc_dcbt xoaddr:$dst),
1521 (DCBT 0, xoaddr:$dst)>;
1522 def : Pat<(int_ppc_dcbtst xoaddr:$dst),
1523 (DCBTST 0, xoaddr:$dst)>;
1524 def : Pat<(int_ppc_dcbf xoaddr:$dst),
1525 (DCBF 0, xoaddr:$dst)>;
1527 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)),
1528 (DCBT 0, xoaddr:$dst)>; // data prefetch for loads
1529 def : Pat<(prefetch xoaddr:$dst, (i32 1), imm, (i32 1)),
1530 (DCBTST 0, xoaddr:$dst)>; // data prefetch for stores
1531 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 0)),
1532 (ICBT 0, xoaddr:$dst)>, Requires<[HasICBT]>; // inst prefetch (for read)
1534 // Atomic operations
1535 let usesCustomInserter = 1 in {
1536 let Defs = [CR0] in {
1537 def ATOMIC_LOAD_ADD_I8 : Pseudo<
1538 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I8",
1539 [(set i32:$dst, (atomic_load_add_8 xoaddr:$ptr, i32:$incr))]>;
1540 def ATOMIC_LOAD_SUB_I8 : Pseudo<
1541 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I8",
1542 [(set i32:$dst, (atomic_load_sub_8 xoaddr:$ptr, i32:$incr))]>;
1543 def ATOMIC_LOAD_AND_I8 : Pseudo<
1544 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I8",
1545 [(set i32:$dst, (atomic_load_and_8 xoaddr:$ptr, i32:$incr))]>;
1546 def ATOMIC_LOAD_OR_I8 : Pseudo<
1547 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I8",
1548 [(set i32:$dst, (atomic_load_or_8 xoaddr:$ptr, i32:$incr))]>;
1549 def ATOMIC_LOAD_XOR_I8 : Pseudo<
1550 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "ATOMIC_LOAD_XOR_I8",
1551 [(set i32:$dst, (atomic_load_xor_8 xoaddr:$ptr, i32:$incr))]>;
1552 def ATOMIC_LOAD_NAND_I8 : Pseudo<
1553 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I8",
1554 [(set i32:$dst, (atomic_load_nand_8 xoaddr:$ptr, i32:$incr))]>;
1555 def ATOMIC_LOAD_MIN_I8 : Pseudo<
1556 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MIN_I8",
1557 [(set i32:$dst, (atomic_load_min_8 xoaddr:$ptr, i32:$incr))]>;
1558 def ATOMIC_LOAD_MAX_I8 : Pseudo<
1559 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MAX_I8",
1560 [(set i32:$dst, (atomic_load_max_8 xoaddr:$ptr, i32:$incr))]>;
1561 def ATOMIC_LOAD_UMIN_I8 : Pseudo<
1562 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMIN_I8",
1563 [(set i32:$dst, (atomic_load_umin_8 xoaddr:$ptr, i32:$incr))]>;
1564 def ATOMIC_LOAD_UMAX_I8 : Pseudo<
1565 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMAX_I8",
1566 [(set i32:$dst, (atomic_load_umax_8 xoaddr:$ptr, i32:$incr))]>;
1567 def ATOMIC_LOAD_ADD_I16 : Pseudo<
1568 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I16",
1569 [(set i32:$dst, (atomic_load_add_16 xoaddr:$ptr, i32:$incr))]>;
1570 def ATOMIC_LOAD_SUB_I16 : Pseudo<
1571 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I16",
1572 [(set i32:$dst, (atomic_load_sub_16 xoaddr:$ptr, i32:$incr))]>;
1573 def ATOMIC_LOAD_AND_I16 : Pseudo<
1574 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I16",
1575 [(set i32:$dst, (atomic_load_and_16 xoaddr:$ptr, i32:$incr))]>;
1576 def ATOMIC_LOAD_OR_I16 : Pseudo<
1577 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I16",
1578 [(set i32:$dst, (atomic_load_or_16 xoaddr:$ptr, i32:$incr))]>;
1579 def ATOMIC_LOAD_XOR_I16 : Pseudo<
1580 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I16",
1581 [(set i32:$dst, (atomic_load_xor_16 xoaddr:$ptr, i32:$incr))]>;
1582 def ATOMIC_LOAD_NAND_I16 : Pseudo<
1583 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I16",
1584 [(set i32:$dst, (atomic_load_nand_16 xoaddr:$ptr, i32:$incr))]>;
1585 def ATOMIC_LOAD_MIN_I16 : Pseudo<
1586 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MIN_I16",
1587 [(set i32:$dst, (atomic_load_min_16 xoaddr:$ptr, i32:$incr))]>;
1588 def ATOMIC_LOAD_MAX_I16 : Pseudo<
1589 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MAX_I16",
1590 [(set i32:$dst, (atomic_load_max_16 xoaddr:$ptr, i32:$incr))]>;
1591 def ATOMIC_LOAD_UMIN_I16 : Pseudo<
1592 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMIN_I16",
1593 [(set i32:$dst, (atomic_load_umin_16 xoaddr:$ptr, i32:$incr))]>;
1594 def ATOMIC_LOAD_UMAX_I16 : Pseudo<
1595 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMAX_I16",
1596 [(set i32:$dst, (atomic_load_umax_16 xoaddr:$ptr, i32:$incr))]>;
1597 def ATOMIC_LOAD_ADD_I32 : Pseudo<
1598 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I32",
1599 [(set i32:$dst, (atomic_load_add_32 xoaddr:$ptr, i32:$incr))]>;
1600 def ATOMIC_LOAD_SUB_I32 : Pseudo<
1601 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I32",
1602 [(set i32:$dst, (atomic_load_sub_32 xoaddr:$ptr, i32:$incr))]>;
1603 def ATOMIC_LOAD_AND_I32 : Pseudo<
1604 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I32",
1605 [(set i32:$dst, (atomic_load_and_32 xoaddr:$ptr, i32:$incr))]>;
1606 def ATOMIC_LOAD_OR_I32 : Pseudo<
1607 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I32",
1608 [(set i32:$dst, (atomic_load_or_32 xoaddr:$ptr, i32:$incr))]>;
1609 def ATOMIC_LOAD_XOR_I32 : Pseudo<
1610 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I32",
1611 [(set i32:$dst, (atomic_load_xor_32 xoaddr:$ptr, i32:$incr))]>;
1612 def ATOMIC_LOAD_NAND_I32 : Pseudo<
1613 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I32",
1614 [(set i32:$dst, (atomic_load_nand_32 xoaddr:$ptr, i32:$incr))]>;
1615 def ATOMIC_LOAD_MIN_I32 : Pseudo<
1616 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MIN_I32",
1617 [(set i32:$dst, (atomic_load_min_32 xoaddr:$ptr, i32:$incr))]>;
1618 def ATOMIC_LOAD_MAX_I32 : Pseudo<
1619 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MAX_I32",
1620 [(set i32:$dst, (atomic_load_max_32 xoaddr:$ptr, i32:$incr))]>;
1621 def ATOMIC_LOAD_UMIN_I32 : Pseudo<
1622 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMIN_I32",
1623 [(set i32:$dst, (atomic_load_umin_32 xoaddr:$ptr, i32:$incr))]>;
1624 def ATOMIC_LOAD_UMAX_I32 : Pseudo<
1625 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMAX_I32",
1626 [(set i32:$dst, (atomic_load_umax_32 xoaddr:$ptr, i32:$incr))]>;
1628 def ATOMIC_CMP_SWAP_I8 : Pseudo<
1629 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I8",
1630 [(set i32:$dst, (atomic_cmp_swap_8 xoaddr:$ptr, i32:$old, i32:$new))]>;
1631 def ATOMIC_CMP_SWAP_I16 : Pseudo<
1632 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I16 $dst $ptr $old $new",
1633 [(set i32:$dst, (atomic_cmp_swap_16 xoaddr:$ptr, i32:$old, i32:$new))]>;
1634 def ATOMIC_CMP_SWAP_I32 : Pseudo<
1635 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I32 $dst $ptr $old $new",
1636 [(set i32:$dst, (atomic_cmp_swap_32 xoaddr:$ptr, i32:$old, i32:$new))]>;
1638 def ATOMIC_SWAP_I8 : Pseudo<
1639 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_i8",
1640 [(set i32:$dst, (atomic_swap_8 xoaddr:$ptr, i32:$new))]>;
1641 def ATOMIC_SWAP_I16 : Pseudo<
1642 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I16",
1643 [(set i32:$dst, (atomic_swap_16 xoaddr:$ptr, i32:$new))]>;
1644 def ATOMIC_SWAP_I32 : Pseudo<
1645 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I32",
1646 [(set i32:$dst, (atomic_swap_32 xoaddr:$ptr, i32:$new))]>;
1650 // Instructions to support atomic operations
1651 let mayLoad = 1, hasSideEffects = 0 in {
1652 def LBARX : XForm_1<31, 52, (outs gprc:$rD), (ins memrr:$src),
1653 "lbarx $rD, $src", IIC_LdStLWARX, []>,
1654 Requires<[HasPartwordAtomics]>;
1656 def LHARX : XForm_1<31, 116, (outs gprc:$rD), (ins memrr:$src),
1657 "lharx $rD, $src", IIC_LdStLWARX, []>,
1658 Requires<[HasPartwordAtomics]>;
1660 def LWARX : XForm_1<31, 20, (outs gprc:$rD), (ins memrr:$src),
1661 "lwarx $rD, $src", IIC_LdStLWARX, []>;
1663 // Instructions to support lock versions of atomics
1664 // (EH=1 - see Power ISA 2.07 Book II 4.4.2)
1665 def LBARXL : XForm_1<31, 52, (outs gprc:$rD), (ins memrr:$src),
1666 "lbarx $rD, $src, 1", IIC_LdStLWARX, []>, isDOT,
1667 Requires<[HasPartwordAtomics]>;
1669 def LHARXL : XForm_1<31, 116, (outs gprc:$rD), (ins memrr:$src),
1670 "lharx $rD, $src, 1", IIC_LdStLWARX, []>, isDOT,
1671 Requires<[HasPartwordAtomics]>;
1673 def LWARXL : XForm_1<31, 20, (outs gprc:$rD), (ins memrr:$src),
1674 "lwarx $rD, $src, 1", IIC_LdStLWARX, []>, isDOT;
1676 // The atomic instructions use the destination register as well as the next one
1677 // or two registers in order (modulo 31).
1678 let hasExtraSrcRegAllocReq = 1 in
1679 def LWAT : X_RD5_RS5_IM5<31, 582, (outs gprc:$rD), (ins gprc:$rA, u5imm:$FC),
1680 "lwat $rD, $rA, $FC", IIC_LdStLoad>,
1681 Requires<[IsISA3_0]>;
1684 let Defs = [CR0], mayStore = 1, hasSideEffects = 0 in {
1685 def STBCX : XForm_1<31, 694, (outs), (ins gprc:$rS, memrr:$dst),
1686 "stbcx. $rS, $dst", IIC_LdStSTWCX, []>,
1687 isDOT, Requires<[HasPartwordAtomics]>;
1689 def STHCX : XForm_1<31, 726, (outs), (ins gprc:$rS, memrr:$dst),
1690 "sthcx. $rS, $dst", IIC_LdStSTWCX, []>,
1691 isDOT, Requires<[HasPartwordAtomics]>;
1693 def STWCX : XForm_1<31, 150, (outs), (ins gprc:$rS, memrr:$dst),
1694 "stwcx. $rS, $dst", IIC_LdStSTWCX, []>, isDOT;
1697 let mayStore = 1, hasSideEffects = 0 in
1698 def STWAT : X_RD5_RS5_IM5<31, 710, (outs), (ins gprc:$rS, gprc:$rA, u5imm:$FC),
1699 "stwat $rS, $rA, $FC", IIC_LdStStore>,
1700 Requires<[IsISA3_0]>;
1702 let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
1703 def TRAP : XForm_24<31, 4, (outs), (ins), "trap", IIC_LdStLoad, [(trap)]>;
1705 def TWI : DForm_base<3, (outs), (ins u5imm:$to, gprc:$rA, s16imm:$imm),
1706 "twi $to, $rA, $imm", IIC_IntTrapW, []>;
1707 def TW : XForm_1<31, 4, (outs), (ins u5imm:$to, gprc:$rA, gprc:$rB),
1708 "tw $to, $rA, $rB", IIC_IntTrapW, []>;
1709 def TDI : DForm_base<2, (outs), (ins u5imm:$to, g8rc:$rA, s16imm:$imm),
1710 "tdi $to, $rA, $imm", IIC_IntTrapD, []>;
1711 def TD : XForm_1<31, 68, (outs), (ins u5imm:$to, g8rc:$rA, g8rc:$rB),
1712 "td $to, $rA, $rB", IIC_IntTrapD, []>;
1714 //===----------------------------------------------------------------------===//
1715 // PPC32 Load Instructions.
1718 // Unindexed (r+i) Loads.
1719 let PPC970_Unit = 2 in {
1720 def LBZ : DForm_1<34, (outs gprc:$rD), (ins memri:$src),
1721 "lbz $rD, $src", IIC_LdStLoad,
1722 [(set i32:$rD, (zextloadi8 iaddr:$src))]>;
1723 def LHA : DForm_1<42, (outs gprc:$rD), (ins memri:$src),
1724 "lha $rD, $src", IIC_LdStLHA,
1725 [(set i32:$rD, (sextloadi16 iaddr:$src))]>,
1726 PPC970_DGroup_Cracked;
1727 def LHZ : DForm_1<40, (outs gprc:$rD), (ins memri:$src),
1728 "lhz $rD, $src", IIC_LdStLoad,
1729 [(set i32:$rD, (zextloadi16 iaddr:$src))]>;
1730 def LWZ : DForm_1<32, (outs gprc:$rD), (ins memri:$src),
1731 "lwz $rD, $src", IIC_LdStLoad,
1732 [(set i32:$rD, (load iaddr:$src))]>;
1734 def LFS : DForm_1<48, (outs f4rc:$rD), (ins memri:$src),
1735 "lfs $rD, $src", IIC_LdStLFD,
1736 [(set f32:$rD, (load iaddr:$src))]>;
1737 def LFD : DForm_1<50, (outs f8rc:$rD), (ins memri:$src),
1738 "lfd $rD, $src", IIC_LdStLFD,
1739 [(set f64:$rD, (load iaddr:$src))]>;
1742 // Unindexed (r+i) Loads with Update (preinc).
1743 let mayLoad = 1, hasSideEffects = 0 in {
1744 def LBZU : DForm_1<35, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1745 "lbzu $rD, $addr", IIC_LdStLoadUpd,
1746 []>, RegConstraint<"$addr.reg = $ea_result">,
1747 NoEncode<"$ea_result">;
1749 def LHAU : DForm_1<43, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1750 "lhau $rD, $addr", IIC_LdStLHAU,
1751 []>, RegConstraint<"$addr.reg = $ea_result">,
1752 NoEncode<"$ea_result">;
1754 def LHZU : DForm_1<41, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1755 "lhzu $rD, $addr", IIC_LdStLoadUpd,
1756 []>, RegConstraint<"$addr.reg = $ea_result">,
1757 NoEncode<"$ea_result">;
1759 def LWZU : DForm_1<33, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1760 "lwzu $rD, $addr", IIC_LdStLoadUpd,
1761 []>, RegConstraint<"$addr.reg = $ea_result">,
1762 NoEncode<"$ea_result">;
1764 def LFSU : DForm_1<49, (outs f4rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1765 "lfsu $rD, $addr", IIC_LdStLFDU,
1766 []>, RegConstraint<"$addr.reg = $ea_result">,
1767 NoEncode<"$ea_result">;
1769 def LFDU : DForm_1<51, (outs f8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1770 "lfdu $rD, $addr", IIC_LdStLFDU,
1771 []>, RegConstraint<"$addr.reg = $ea_result">,
1772 NoEncode<"$ea_result">;
1775 // Indexed (r+r) Loads with Update (preinc).
1776 def LBZUX : XForm_1<31, 119, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1778 "lbzux $rD, $addr", IIC_LdStLoadUpdX,
1779 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1780 NoEncode<"$ea_result">;
1782 def LHAUX : XForm_1<31, 375, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1784 "lhaux $rD, $addr", IIC_LdStLHAUX,
1785 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1786 NoEncode<"$ea_result">;
1788 def LHZUX : XForm_1<31, 311, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1790 "lhzux $rD, $addr", IIC_LdStLoadUpdX,
1791 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1792 NoEncode<"$ea_result">;
1794 def LWZUX : XForm_1<31, 55, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1796 "lwzux $rD, $addr", IIC_LdStLoadUpdX,
1797 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1798 NoEncode<"$ea_result">;
1800 def LFSUX : XForm_1<31, 567, (outs f4rc:$rD, ptr_rc_nor0:$ea_result),
1802 "lfsux $rD, $addr", IIC_LdStLFDUX,
1803 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1804 NoEncode<"$ea_result">;
1806 def LFDUX : XForm_1<31, 631, (outs f8rc:$rD, ptr_rc_nor0:$ea_result),
1808 "lfdux $rD, $addr", IIC_LdStLFDUX,
1809 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1810 NoEncode<"$ea_result">;
1814 // Indexed (r+r) Loads.
1816 let PPC970_Unit = 2 in {
1817 def LBZX : XForm_1<31, 87, (outs gprc:$rD), (ins memrr:$src),
1818 "lbzx $rD, $src", IIC_LdStLoad,
1819 [(set i32:$rD, (zextloadi8 xaddr:$src))]>;
1820 def LHAX : XForm_1<31, 343, (outs gprc:$rD), (ins memrr:$src),
1821 "lhax $rD, $src", IIC_LdStLHA,
1822 [(set i32:$rD, (sextloadi16 xaddr:$src))]>,
1823 PPC970_DGroup_Cracked;
1824 def LHZX : XForm_1<31, 279, (outs gprc:$rD), (ins memrr:$src),
1825 "lhzx $rD, $src", IIC_LdStLoad,
1826 [(set i32:$rD, (zextloadi16 xaddr:$src))]>;
1827 def LWZX : XForm_1<31, 23, (outs gprc:$rD), (ins memrr:$src),
1828 "lwzx $rD, $src", IIC_LdStLoad,
1829 [(set i32:$rD, (load xaddr:$src))]>;
1832 def LHBRX : XForm_1<31, 790, (outs gprc:$rD), (ins memrr:$src),
1833 "lhbrx $rD, $src", IIC_LdStLoad,
1834 [(set i32:$rD, (PPClbrx xoaddr:$src, i16))]>;
1835 def LWBRX : XForm_1<31, 534, (outs gprc:$rD), (ins memrr:$src),
1836 "lwbrx $rD, $src", IIC_LdStLoad,
1837 [(set i32:$rD, (PPClbrx xoaddr:$src, i32))]>;
1839 def LFSX : XForm_25<31, 535, (outs f4rc:$frD), (ins memrr:$src),
1840 "lfsx $frD, $src", IIC_LdStLFD,
1841 [(set f32:$frD, (load xaddr:$src))]>;
1842 def LFDX : XForm_25<31, 599, (outs f8rc:$frD), (ins memrr:$src),
1843 "lfdx $frD, $src", IIC_LdStLFD,
1844 [(set f64:$frD, (load xaddr:$src))]>;
1846 def LFIWAX : XForm_25<31, 855, (outs f8rc:$frD), (ins memrr:$src),
1847 "lfiwax $frD, $src", IIC_LdStLFD,
1848 [(set f64:$frD, (PPClfiwax xoaddr:$src))]>;
1849 def LFIWZX : XForm_25<31, 887, (outs f8rc:$frD), (ins memrr:$src),
1850 "lfiwzx $frD, $src", IIC_LdStLFD,
1851 [(set f64:$frD, (PPClfiwzx xoaddr:$src))]>;
1855 def LMW : DForm_1<46, (outs gprc:$rD), (ins memri:$src),
1856 "lmw $rD, $src", IIC_LdStLMW, []>;
1858 //===----------------------------------------------------------------------===//
1859 // PPC32 Store Instructions.
1862 // Unindexed (r+i) Stores.
1863 let PPC970_Unit = 2 in {
1864 def STB : DForm_1<38, (outs), (ins gprc:$rS, memri:$src),
1865 "stb $rS, $src", IIC_LdStStore,
1866 [(truncstorei8 i32:$rS, iaddr:$src)]>;
1867 def STH : DForm_1<44, (outs), (ins gprc:$rS, memri:$src),
1868 "sth $rS, $src", IIC_LdStStore,
1869 [(truncstorei16 i32:$rS, iaddr:$src)]>;
1870 def STW : DForm_1<36, (outs), (ins gprc:$rS, memri:$src),
1871 "stw $rS, $src", IIC_LdStStore,
1872 [(store i32:$rS, iaddr:$src)]>;
1873 def STFS : DForm_1<52, (outs), (ins f4rc:$rS, memri:$dst),
1874 "stfs $rS, $dst", IIC_LdStSTFD,
1875 [(store f32:$rS, iaddr:$dst)]>;
1876 def STFD : DForm_1<54, (outs), (ins f8rc:$rS, memri:$dst),
1877 "stfd $rS, $dst", IIC_LdStSTFD,
1878 [(store f64:$rS, iaddr:$dst)]>;
1881 // Unindexed (r+i) Stores with Update (preinc).
1882 let PPC970_Unit = 2, mayStore = 1 in {
1883 def STBU : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1884 "stbu $rS, $dst", IIC_LdStStoreUpd, []>,
1885 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1886 def STHU : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1887 "sthu $rS, $dst", IIC_LdStStoreUpd, []>,
1888 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1889 def STWU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1890 "stwu $rS, $dst", IIC_LdStStoreUpd, []>,
1891 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1892 def STFSU : DForm_1<53, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memri:$dst),
1893 "stfsu $rS, $dst", IIC_LdStSTFDU, []>,
1894 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1895 def STFDU : DForm_1<55, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memri:$dst),
1896 "stfdu $rS, $dst", IIC_LdStSTFDU, []>,
1897 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1900 // Patterns to match the pre-inc stores. We can't put the patterns on
1901 // the instruction definitions directly as ISel wants the address base
1902 // and offset to be separate operands, not a single complex operand.
1903 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1904 (STBU $rS, iaddroff:$ptroff, $ptrreg)>;
1905 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1906 (STHU $rS, iaddroff:$ptroff, $ptrreg)>;
1907 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1908 (STWU $rS, iaddroff:$ptroff, $ptrreg)>;
1909 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1910 (STFSU $rS, iaddroff:$ptroff, $ptrreg)>;
1911 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1912 (STFDU $rS, iaddroff:$ptroff, $ptrreg)>;
1914 // Indexed (r+r) Stores.
1915 let PPC970_Unit = 2 in {
1916 def STBX : XForm_8<31, 215, (outs), (ins gprc:$rS, memrr:$dst),
1917 "stbx $rS, $dst", IIC_LdStStore,
1918 [(truncstorei8 i32:$rS, xaddr:$dst)]>,
1919 PPC970_DGroup_Cracked;
1920 def STHX : XForm_8<31, 407, (outs), (ins gprc:$rS, memrr:$dst),
1921 "sthx $rS, $dst", IIC_LdStStore,
1922 [(truncstorei16 i32:$rS, xaddr:$dst)]>,
1923 PPC970_DGroup_Cracked;
1924 def STWX : XForm_8<31, 151, (outs), (ins gprc:$rS, memrr:$dst),
1925 "stwx $rS, $dst", IIC_LdStStore,
1926 [(store i32:$rS, xaddr:$dst)]>,
1927 PPC970_DGroup_Cracked;
1929 def STHBRX: XForm_8<31, 918, (outs), (ins gprc:$rS, memrr:$dst),
1930 "sthbrx $rS, $dst", IIC_LdStStore,
1931 [(PPCstbrx i32:$rS, xoaddr:$dst, i16)]>,
1932 PPC970_DGroup_Cracked;
1933 def STWBRX: XForm_8<31, 662, (outs), (ins gprc:$rS, memrr:$dst),
1934 "stwbrx $rS, $dst", IIC_LdStStore,
1935 [(PPCstbrx i32:$rS, xoaddr:$dst, i32)]>,
1936 PPC970_DGroup_Cracked;
1938 def STFIWX: XForm_28<31, 983, (outs), (ins f8rc:$frS, memrr:$dst),
1939 "stfiwx $frS, $dst", IIC_LdStSTFD,
1940 [(PPCstfiwx f64:$frS, xoaddr:$dst)]>;
1942 def STFSX : XForm_28<31, 663, (outs), (ins f4rc:$frS, memrr:$dst),
1943 "stfsx $frS, $dst", IIC_LdStSTFD,
1944 [(store f32:$frS, xaddr:$dst)]>;
1945 def STFDX : XForm_28<31, 727, (outs), (ins f8rc:$frS, memrr:$dst),
1946 "stfdx $frS, $dst", IIC_LdStSTFD,
1947 [(store f64:$frS, xaddr:$dst)]>;
1950 // Indexed (r+r) Stores with Update (preinc).
1951 let PPC970_Unit = 2, mayStore = 1 in {
1952 def STBUX : XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1953 "stbux $rS, $dst", IIC_LdStStoreUpd, []>,
1954 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1955 PPC970_DGroup_Cracked;
1956 def STHUX : XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1957 "sthux $rS, $dst", IIC_LdStStoreUpd, []>,
1958 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1959 PPC970_DGroup_Cracked;
1960 def STWUX : XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1961 "stwux $rS, $dst", IIC_LdStStoreUpd, []>,
1962 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1963 PPC970_DGroup_Cracked;
1964 def STFSUX: XForm_8<31, 695, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memrr:$dst),
1965 "stfsux $rS, $dst", IIC_LdStSTFDU, []>,
1966 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1967 PPC970_DGroup_Cracked;
1968 def STFDUX: XForm_8<31, 759, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memrr:$dst),
1969 "stfdux $rS, $dst", IIC_LdStSTFDU, []>,
1970 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1971 PPC970_DGroup_Cracked;
1974 // Patterns to match the pre-inc stores. We can't put the patterns on
1975 // the instruction definitions directly as ISel wants the address base
1976 // and offset to be separate operands, not a single complex operand.
1977 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1978 (STBUX $rS, $ptrreg, $ptroff)>;
1979 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1980 (STHUX $rS, $ptrreg, $ptroff)>;
1981 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1982 (STWUX $rS, $ptrreg, $ptroff)>;
1983 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1984 (STFSUX $rS, $ptrreg, $ptroff)>;
1985 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1986 (STFDUX $rS, $ptrreg, $ptroff)>;
1989 def STMW : DForm_1<47, (outs), (ins gprc:$rS, memri:$dst),
1990 "stmw $rS, $dst", IIC_LdStLMW, []>;
1992 def SYNC : XForm_24_sync<31, 598, (outs), (ins i32imm:$L),
1993 "sync $L", IIC_LdStSync, []>;
1995 let isCodeGenOnly = 1 in {
1996 def MSYNC : XForm_24_sync<31, 598, (outs), (ins),
1997 "msync", IIC_LdStSync, []> {
2002 def : Pat<(int_ppc_sync), (SYNC 0)>, Requires<[HasSYNC]>;
2003 def : Pat<(int_ppc_lwsync), (SYNC 1)>, Requires<[HasSYNC]>;
2004 def : Pat<(int_ppc_sync), (MSYNC)>, Requires<[HasOnlyMSYNC]>;
2005 def : Pat<(int_ppc_lwsync), (MSYNC)>, Requires<[HasOnlyMSYNC]>;
2007 //===----------------------------------------------------------------------===//
2008 // PPC32 Arithmetic Instructions.
2011 let PPC970_Unit = 1 in { // FXU Operations.
2012 def ADDI : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$imm),
2013 "addi $rD, $rA, $imm", IIC_IntSimple,
2014 [(set i32:$rD, (add i32:$rA, imm32SExt16:$imm))]>;
2015 let BaseName = "addic" in {
2016 let Defs = [CARRY] in
2017 def ADDIC : DForm_2<12, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
2018 "addic $rD, $rA, $imm", IIC_IntGeneral,
2019 [(set i32:$rD, (addc i32:$rA, imm32SExt16:$imm))]>,
2020 RecFormRel, PPC970_DGroup_Cracked;
2021 let Defs = [CARRY, CR0] in
2022 def ADDICo : DForm_2<13, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
2023 "addic. $rD, $rA, $imm", IIC_IntGeneral,
2024 []>, isDOT, RecFormRel;
2026 def ADDIS : DForm_2<15, (outs gprc:$rD), (ins gprc_nor0:$rA, s17imm:$imm),
2027 "addis $rD, $rA, $imm", IIC_IntSimple,
2028 [(set i32:$rD, (add i32:$rA, imm16ShiftedSExt:$imm))]>;
2029 let isCodeGenOnly = 1 in
2030 def LA : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$sym),
2031 "la $rD, $sym($rA)", IIC_IntGeneral,
2032 [(set i32:$rD, (add i32:$rA,
2033 (PPClo tglobaladdr:$sym, 0)))]>;
2034 def MULLI : DForm_2< 7, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
2035 "mulli $rD, $rA, $imm", IIC_IntMulLI,
2036 [(set i32:$rD, (mul i32:$rA, imm32SExt16:$imm))]>;
2037 let Defs = [CARRY] in
2038 def SUBFIC : DForm_2< 8, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
2039 "subfic $rD, $rA, $imm", IIC_IntGeneral,
2040 [(set i32:$rD, (subc imm32SExt16:$imm, i32:$rA))]>;
2042 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
2043 def LI : DForm_2_r0<14, (outs gprc:$rD), (ins s16imm:$imm),
2044 "li $rD, $imm", IIC_IntSimple,
2045 [(set i32:$rD, imm32SExt16:$imm)]>;
2046 def LIS : DForm_2_r0<15, (outs gprc:$rD), (ins s17imm:$imm),
2047 "lis $rD, $imm", IIC_IntSimple,
2048 [(set i32:$rD, imm16ShiftedSExt:$imm)]>;
2052 let PPC970_Unit = 1 in { // FXU Operations.
2053 let Defs = [CR0] in {
2054 def ANDIo : DForm_4<28, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
2055 "andi. $dst, $src1, $src2", IIC_IntGeneral,
2056 [(set i32:$dst, (and i32:$src1, immZExt16:$src2))]>,
2058 def ANDISo : DForm_4<29, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
2059 "andis. $dst, $src1, $src2", IIC_IntGeneral,
2060 [(set i32:$dst, (and i32:$src1, imm16ShiftedZExt:$src2))]>,
2063 def ORI : DForm_4<24, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
2064 "ori $dst, $src1, $src2", IIC_IntSimple,
2065 [(set i32:$dst, (or i32:$src1, immZExt16:$src2))]>;
2066 def ORIS : DForm_4<25, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
2067 "oris $dst, $src1, $src2", IIC_IntSimple,
2068 [(set i32:$dst, (or i32:$src1, imm16ShiftedZExt:$src2))]>;
2069 def XORI : DForm_4<26, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
2070 "xori $dst, $src1, $src2", IIC_IntSimple,
2071 [(set i32:$dst, (xor i32:$src1, immZExt16:$src2))]>;
2072 def XORIS : DForm_4<27, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
2073 "xoris $dst, $src1, $src2", IIC_IntSimple,
2074 [(set i32:$dst, (xor i32:$src1, imm16ShiftedZExt:$src2))]>;
2076 def NOP : DForm_4_zero<24, (outs), (ins), "nop", IIC_IntSimple,
2078 let isCodeGenOnly = 1 in {
2079 // The POWER6 and POWER7 have special group-terminating nops.
2080 def NOP_GT_PWR6 : DForm_4_fixedreg_zero<24, 1, (outs), (ins),
2081 "ori 1, 1, 0", IIC_IntSimple, []>;
2082 def NOP_GT_PWR7 : DForm_4_fixedreg_zero<24, 2, (outs), (ins),
2083 "ori 2, 2, 0", IIC_IntSimple, []>;
2086 let isCompare = 1, hasSideEffects = 0 in {
2087 def CMPWI : DForm_5_ext<11, (outs crrc:$crD), (ins gprc:$rA, s16imm:$imm),
2088 "cmpwi $crD, $rA, $imm", IIC_IntCompare>;
2089 def CMPLWI : DForm_6_ext<10, (outs crrc:$dst), (ins gprc:$src1, u16imm:$src2),
2090 "cmplwi $dst, $src1, $src2", IIC_IntCompare>;
2091 def CMPRB : X_BF3_L1_RS5_RS5<31, 192, (outs crbitrc:$BF),
2092 (ins u1imm:$L, g8rc:$rA, g8rc:$rB),
2093 "cmprb $BF, $L, $rA, $rB", IIC_IntCompare, []>,
2094 Requires<[IsISA3_0]>;
2098 let PPC970_Unit = 1, hasSideEffects = 0 in { // FXU Operations.
2099 let isCommutable = 1 in {
2100 defm NAND : XForm_6r<31, 476, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2101 "nand", "$rA, $rS, $rB", IIC_IntSimple,
2102 [(set i32:$rA, (not (and i32:$rS, i32:$rB)))]>;
2103 defm AND : XForm_6r<31, 28, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2104 "and", "$rA, $rS, $rB", IIC_IntSimple,
2105 [(set i32:$rA, (and i32:$rS, i32:$rB))]>;
2107 defm ANDC : XForm_6r<31, 60, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2108 "andc", "$rA, $rS, $rB", IIC_IntSimple,
2109 [(set i32:$rA, (and i32:$rS, (not i32:$rB)))]>;
2110 let isCommutable = 1 in {
2111 defm OR : XForm_6r<31, 444, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2112 "or", "$rA, $rS, $rB", IIC_IntSimple,
2113 [(set i32:$rA, (or i32:$rS, i32:$rB))]>;
2114 defm NOR : XForm_6r<31, 124, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2115 "nor", "$rA, $rS, $rB", IIC_IntSimple,
2116 [(set i32:$rA, (not (or i32:$rS, i32:$rB)))]>;
2118 defm ORC : XForm_6r<31, 412, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2119 "orc", "$rA, $rS, $rB", IIC_IntSimple,
2120 [(set i32:$rA, (or i32:$rS, (not i32:$rB)))]>;
2121 let isCommutable = 1 in {
2122 defm EQV : XForm_6r<31, 284, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2123 "eqv", "$rA, $rS, $rB", IIC_IntSimple,
2124 [(set i32:$rA, (not (xor i32:$rS, i32:$rB)))]>;
2125 defm XOR : XForm_6r<31, 316, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2126 "xor", "$rA, $rS, $rB", IIC_IntSimple,
2127 [(set i32:$rA, (xor i32:$rS, i32:$rB))]>;
2129 defm SLW : XForm_6r<31, 24, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2130 "slw", "$rA, $rS, $rB", IIC_IntGeneral,
2131 [(set i32:$rA, (PPCshl i32:$rS, i32:$rB))]>;
2132 defm SRW : XForm_6r<31, 536, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2133 "srw", "$rA, $rS, $rB", IIC_IntGeneral,
2134 [(set i32:$rA, (PPCsrl i32:$rS, i32:$rB))]>;
2135 defm SRAW : XForm_6rc<31, 792, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2136 "sraw", "$rA, $rS, $rB", IIC_IntShift,
2137 [(set i32:$rA, (PPCsra i32:$rS, i32:$rB))]>;
2140 let PPC970_Unit = 1 in { // FXU Operations.
2141 let hasSideEffects = 0 in {
2142 defm SRAWI : XForm_10rc<31, 824, (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH),
2143 "srawi", "$rA, $rS, $SH", IIC_IntShift,
2144 [(set i32:$rA, (sra i32:$rS, (i32 imm:$SH)))]>;
2145 defm CNTLZW : XForm_11r<31, 26, (outs gprc:$rA), (ins gprc:$rS),
2146 "cntlzw", "$rA, $rS", IIC_IntGeneral,
2147 [(set i32:$rA, (ctlz i32:$rS))]>;
2148 defm CNTTZW : XForm_11r<31, 538, (outs gprc:$rA), (ins gprc:$rS),
2149 "cnttzw", "$rA, $rS", IIC_IntGeneral,
2150 [(set i32:$rA, (cttz i32:$rS))]>, Requires<[IsISA3_0]>;
2151 defm EXTSB : XForm_11r<31, 954, (outs gprc:$rA), (ins gprc:$rS),
2152 "extsb", "$rA, $rS", IIC_IntSimple,
2153 [(set i32:$rA, (sext_inreg i32:$rS, i8))]>;
2154 defm EXTSH : XForm_11r<31, 922, (outs gprc:$rA), (ins gprc:$rS),
2155 "extsh", "$rA, $rS", IIC_IntSimple,
2156 [(set i32:$rA, (sext_inreg i32:$rS, i16))]>;
2158 let isCommutable = 1 in
2159 def CMPB : XForm_6<31, 508, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2160 "cmpb $rA, $rS, $rB", IIC_IntGeneral,
2161 [(set i32:$rA, (PPCcmpb i32:$rS, i32:$rB))]>;
2163 let isCompare = 1, hasSideEffects = 0 in {
2164 def CMPW : XForm_16_ext<31, 0, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
2165 "cmpw $crD, $rA, $rB", IIC_IntCompare>;
2166 def CMPLW : XForm_16_ext<31, 32, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
2167 "cmplw $crD, $rA, $rB", IIC_IntCompare>;
2170 let PPC970_Unit = 3 in { // FPU Operations.
2171 //def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB),
2172 // "fcmpo $crD, $fA, $fB", IIC_FPCompare>;
2173 let isCompare = 1, hasSideEffects = 0 in {
2174 def FCMPUS : XForm_17<63, 0, (outs crrc:$crD), (ins f4rc:$fA, f4rc:$fB),
2175 "fcmpu $crD, $fA, $fB", IIC_FPCompare>;
2176 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2177 def FCMPUD : XForm_17<63, 0, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB),
2178 "fcmpu $crD, $fA, $fB", IIC_FPCompare>;
2181 def FTDIV: XForm_17<63, 128, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB),
2182 "ftdiv $crD, $fA, $fB", IIC_FPCompare>;
2183 def FTSQRT: XForm_17a<63, 160, (outs crrc:$crD), (ins f8rc:$fB),
2184 "ftsqrt $crD, $fB", IIC_FPCompare>;
2186 let Uses = [RM] in {
2187 let hasSideEffects = 0 in {
2188 defm FCTIW : XForm_26r<63, 14, (outs f8rc:$frD), (ins f8rc:$frB),
2189 "fctiw", "$frD, $frB", IIC_FPGeneral,
2191 defm FCTIWU : XForm_26r<63, 142, (outs f8rc:$frD), (ins f8rc:$frB),
2192 "fctiwu", "$frD, $frB", IIC_FPGeneral,
2194 defm FCTIWZ : XForm_26r<63, 15, (outs f8rc:$frD), (ins f8rc:$frB),
2195 "fctiwz", "$frD, $frB", IIC_FPGeneral,
2196 [(set f64:$frD, (PPCfctiwz f64:$frB))]>;
2198 defm FRSP : XForm_26r<63, 12, (outs f4rc:$frD), (ins f8rc:$frB),
2199 "frsp", "$frD, $frB", IIC_FPGeneral,
2200 [(set f32:$frD, (fpround f64:$frB))]>;
2202 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2203 defm FRIND : XForm_26r<63, 392, (outs f8rc:$frD), (ins f8rc:$frB),
2204 "frin", "$frD, $frB", IIC_FPGeneral,
2205 [(set f64:$frD, (fround f64:$frB))]>;
2206 defm FRINS : XForm_26r<63, 392, (outs f4rc:$frD), (ins f4rc:$frB),
2207 "frin", "$frD, $frB", IIC_FPGeneral,
2208 [(set f32:$frD, (fround f32:$frB))]>;
2211 let hasSideEffects = 0 in {
2212 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2213 defm FRIPD : XForm_26r<63, 456, (outs f8rc:$frD), (ins f8rc:$frB),
2214 "frip", "$frD, $frB", IIC_FPGeneral,
2215 [(set f64:$frD, (fceil f64:$frB))]>;
2216 defm FRIPS : XForm_26r<63, 456, (outs f4rc:$frD), (ins f4rc:$frB),
2217 "frip", "$frD, $frB", IIC_FPGeneral,
2218 [(set f32:$frD, (fceil f32:$frB))]>;
2219 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2220 defm FRIZD : XForm_26r<63, 424, (outs f8rc:$frD), (ins f8rc:$frB),
2221 "friz", "$frD, $frB", IIC_FPGeneral,
2222 [(set f64:$frD, (ftrunc f64:$frB))]>;
2223 defm FRIZS : XForm_26r<63, 424, (outs f4rc:$frD), (ins f4rc:$frB),
2224 "friz", "$frD, $frB", IIC_FPGeneral,
2225 [(set f32:$frD, (ftrunc f32:$frB))]>;
2226 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2227 defm FRIMD : XForm_26r<63, 488, (outs f8rc:$frD), (ins f8rc:$frB),
2228 "frim", "$frD, $frB", IIC_FPGeneral,
2229 [(set f64:$frD, (ffloor f64:$frB))]>;
2230 defm FRIMS : XForm_26r<63, 488, (outs f4rc:$frD), (ins f4rc:$frB),
2231 "frim", "$frD, $frB", IIC_FPGeneral,
2232 [(set f32:$frD, (ffloor f32:$frB))]>;
2234 defm FSQRT : XForm_26r<63, 22, (outs f8rc:$frD), (ins f8rc:$frB),
2235 "fsqrt", "$frD, $frB", IIC_FPSqrtD,
2236 [(set f64:$frD, (fsqrt f64:$frB))]>;
2237 defm FSQRTS : XForm_26r<59, 22, (outs f4rc:$frD), (ins f4rc:$frB),
2238 "fsqrts", "$frD, $frB", IIC_FPSqrtS,
2239 [(set f32:$frD, (fsqrt f32:$frB))]>;
2244 /// Note that FMR is defined as pseudo-ops on the PPC970 because they are
2245 /// often coalesced away and we don't want the dispatch group builder to think
2246 /// that they will fill slots (which could cause the load of a LSU reject to
2247 /// sneak into a d-group with a store).
2248 let hasSideEffects = 0 in
2249 defm FMR : XForm_26r<63, 72, (outs f4rc:$frD), (ins f4rc:$frB),
2250 "fmr", "$frD, $frB", IIC_FPGeneral,
2251 []>, // (set f32:$frD, f32:$frB)
2254 let PPC970_Unit = 3, hasSideEffects = 0 in { // FPU Operations.
2255 // These are artificially split into two different forms, for 4/8 byte FP.
2256 defm FABSS : XForm_26r<63, 264, (outs f4rc:$frD), (ins f4rc:$frB),
2257 "fabs", "$frD, $frB", IIC_FPGeneral,
2258 [(set f32:$frD, (fabs f32:$frB))]>;
2259 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2260 defm FABSD : XForm_26r<63, 264, (outs f8rc:$frD), (ins f8rc:$frB),
2261 "fabs", "$frD, $frB", IIC_FPGeneral,
2262 [(set f64:$frD, (fabs f64:$frB))]>;
2263 defm FNABSS : XForm_26r<63, 136, (outs f4rc:$frD), (ins f4rc:$frB),
2264 "fnabs", "$frD, $frB", IIC_FPGeneral,
2265 [(set f32:$frD, (fneg (fabs f32:$frB)))]>;
2266 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2267 defm FNABSD : XForm_26r<63, 136, (outs f8rc:$frD), (ins f8rc:$frB),
2268 "fnabs", "$frD, $frB", IIC_FPGeneral,
2269 [(set f64:$frD, (fneg (fabs f64:$frB)))]>;
2270 defm FNEGS : XForm_26r<63, 40, (outs f4rc:$frD), (ins f4rc:$frB),
2271 "fneg", "$frD, $frB", IIC_FPGeneral,
2272 [(set f32:$frD, (fneg f32:$frB))]>;
2273 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2274 defm FNEGD : XForm_26r<63, 40, (outs f8rc:$frD), (ins f8rc:$frB),
2275 "fneg", "$frD, $frB", IIC_FPGeneral,
2276 [(set f64:$frD, (fneg f64:$frB))]>;
2278 defm FCPSGNS : XForm_28r<63, 8, (outs f4rc:$frD), (ins f4rc:$frA, f4rc:$frB),
2279 "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral,
2280 [(set f32:$frD, (fcopysign f32:$frB, f32:$frA))]>;
2281 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2282 defm FCPSGND : XForm_28r<63, 8, (outs f8rc:$frD), (ins f8rc:$frA, f8rc:$frB),
2283 "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral,
2284 [(set f64:$frD, (fcopysign f64:$frB, f64:$frA))]>;
2286 // Reciprocal estimates.
2287 defm FRE : XForm_26r<63, 24, (outs f8rc:$frD), (ins f8rc:$frB),
2288 "fre", "$frD, $frB", IIC_FPGeneral,
2289 [(set f64:$frD, (PPCfre f64:$frB))]>;
2290 defm FRES : XForm_26r<59, 24, (outs f4rc:$frD), (ins f4rc:$frB),
2291 "fres", "$frD, $frB", IIC_FPGeneral,
2292 [(set f32:$frD, (PPCfre f32:$frB))]>;
2293 defm FRSQRTE : XForm_26r<63, 26, (outs f8rc:$frD), (ins f8rc:$frB),
2294 "frsqrte", "$frD, $frB", IIC_FPGeneral,
2295 [(set f64:$frD, (PPCfrsqrte f64:$frB))]>;
2296 defm FRSQRTES : XForm_26r<59, 26, (outs f4rc:$frD), (ins f4rc:$frB),
2297 "frsqrtes", "$frD, $frB", IIC_FPGeneral,
2298 [(set f32:$frD, (PPCfrsqrte f32:$frB))]>;
2301 // XL-Form instructions. condition register logical ops.
2303 let hasSideEffects = 0 in
2304 def MCRF : XLForm_3<19, 0, (outs crrc:$BF), (ins crrc:$BFA),
2305 "mcrf $BF, $BFA", IIC_BrMCR>,
2306 PPC970_DGroup_First, PPC970_Unit_CRU;
2308 // FIXME: According to the ISA (section 2.5.1 of version 2.06), the
2309 // condition-register logical instructions have preferred forms. Specifically,
2310 // it is preferred that the bit specified by the BT field be in the same
2311 // condition register as that specified by the bit BB. We might want to account
2312 // for this via hinting the register allocator and anti-dep breakers, or we
2313 // could constrain the register class to force this constraint and then loosen
2314 // it during register allocation via convertToThreeAddress or some similar
2317 let isCommutable = 1 in {
2318 def CRAND : XLForm_1<19, 257, (outs crbitrc:$CRD),
2319 (ins crbitrc:$CRA, crbitrc:$CRB),
2320 "crand $CRD, $CRA, $CRB", IIC_BrCR,
2321 [(set i1:$CRD, (and i1:$CRA, i1:$CRB))]>;
2323 def CRNAND : XLForm_1<19, 225, (outs crbitrc:$CRD),
2324 (ins crbitrc:$CRA, crbitrc:$CRB),
2325 "crnand $CRD, $CRA, $CRB", IIC_BrCR,
2326 [(set i1:$CRD, (not (and i1:$CRA, i1:$CRB)))]>;
2328 def CROR : XLForm_1<19, 449, (outs crbitrc:$CRD),
2329 (ins crbitrc:$CRA, crbitrc:$CRB),
2330 "cror $CRD, $CRA, $CRB", IIC_BrCR,
2331 [(set i1:$CRD, (or i1:$CRA, i1:$CRB))]>;
2333 def CRXOR : XLForm_1<19, 193, (outs crbitrc:$CRD),
2334 (ins crbitrc:$CRA, crbitrc:$CRB),
2335 "crxor $CRD, $CRA, $CRB", IIC_BrCR,
2336 [(set i1:$CRD, (xor i1:$CRA, i1:$CRB))]>;
2338 def CRNOR : XLForm_1<19, 33, (outs crbitrc:$CRD),
2339 (ins crbitrc:$CRA, crbitrc:$CRB),
2340 "crnor $CRD, $CRA, $CRB", IIC_BrCR,
2341 [(set i1:$CRD, (not (or i1:$CRA, i1:$CRB)))]>;
2343 def CREQV : XLForm_1<19, 289, (outs crbitrc:$CRD),
2344 (ins crbitrc:$CRA, crbitrc:$CRB),
2345 "creqv $CRD, $CRA, $CRB", IIC_BrCR,
2346 [(set i1:$CRD, (not (xor i1:$CRA, i1:$CRB)))]>;
2349 def CRANDC : XLForm_1<19, 129, (outs crbitrc:$CRD),
2350 (ins crbitrc:$CRA, crbitrc:$CRB),
2351 "crandc $CRD, $CRA, $CRB", IIC_BrCR,
2352 [(set i1:$CRD, (and i1:$CRA, (not i1:$CRB)))]>;
2354 def CRORC : XLForm_1<19, 417, (outs crbitrc:$CRD),
2355 (ins crbitrc:$CRA, crbitrc:$CRB),
2356 "crorc $CRD, $CRA, $CRB", IIC_BrCR,
2357 [(set i1:$CRD, (or i1:$CRA, (not i1:$CRB)))]>;
2359 let isCodeGenOnly = 1 in {
2360 def CRSET : XLForm_1_ext<19, 289, (outs crbitrc:$dst), (ins),
2361 "creqv $dst, $dst, $dst", IIC_BrCR,
2362 [(set i1:$dst, 1)]>;
2364 def CRUNSET: XLForm_1_ext<19, 193, (outs crbitrc:$dst), (ins),
2365 "crxor $dst, $dst, $dst", IIC_BrCR,
2366 [(set i1:$dst, 0)]>;
2368 let Defs = [CR1EQ], CRD = 6 in {
2369 def CR6SET : XLForm_1_ext<19, 289, (outs), (ins),
2370 "creqv 6, 6, 6", IIC_BrCR,
2373 def CR6UNSET: XLForm_1_ext<19, 193, (outs), (ins),
2374 "crxor 6, 6, 6", IIC_BrCR,
2379 // XFX-Form instructions. Instructions that deal with SPRs.
2382 def MFSPR : XFXForm_1<31, 339, (outs gprc:$RT), (ins i32imm:$SPR),
2383 "mfspr $RT, $SPR", IIC_SprMFSPR>;
2384 def MTSPR : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, gprc:$RT),
2385 "mtspr $SPR, $RT", IIC_SprMTSPR>;
2387 def MFTB : XFXForm_1<31, 371, (outs gprc:$RT), (ins i32imm:$SPR),
2388 "mftb $RT, $SPR", IIC_SprMFTB>;
2390 def MFPMR : XFXForm_1<31, 334, (outs gprc:$RT), (ins i32imm:$SPR),
2391 "mfpmr $RT, $SPR", IIC_SprMFPMR>;
2393 def MTPMR : XFXForm_1<31, 462, (outs), (ins i32imm:$SPR, gprc:$RT),
2394 "mtpmr $SPR, $RT", IIC_SprMTPMR>;
2397 // A pseudo-instruction used to implement the read of the 64-bit cycle counter
2398 // on a 32-bit target.
2399 let hasSideEffects = 1, usesCustomInserter = 1 in
2400 def ReadTB : Pseudo<(outs gprc:$lo, gprc:$hi), (ins),
2403 let Uses = [CTR] in {
2404 def MFCTR : XFXForm_1_ext<31, 339, 9, (outs gprc:$rT), (ins),
2405 "mfctr $rT", IIC_SprMFSPR>,
2406 PPC970_DGroup_First, PPC970_Unit_FXU;
2408 let Defs = [CTR], Pattern = [(PPCmtctr i32:$rS)] in {
2409 def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
2410 "mtctr $rS", IIC_SprMTSPR>,
2411 PPC970_DGroup_First, PPC970_Unit_FXU;
2413 let hasSideEffects = 1, isCodeGenOnly = 1, Defs = [CTR] in {
2414 let Pattern = [(int_ppc_mtctr i32:$rS)] in
2415 def MTCTRloop : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
2416 "mtctr $rS", IIC_SprMTSPR>,
2417 PPC970_DGroup_First, PPC970_Unit_FXU;
2420 let Defs = [LR] in {
2421 def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins gprc:$rS),
2422 "mtlr $rS", IIC_SprMTSPR>,
2423 PPC970_DGroup_First, PPC970_Unit_FXU;
2425 let Uses = [LR] in {
2426 def MFLR : XFXForm_1_ext<31, 339, 8, (outs gprc:$rT), (ins),
2427 "mflr $rT", IIC_SprMFSPR>,
2428 PPC970_DGroup_First, PPC970_Unit_FXU;
2431 let isCodeGenOnly = 1 in {
2432 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed
2433 // like a GPR on the PPC970. As such, copies in and out have the same
2434 // performance characteristics as an OR instruction.
2435 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins gprc:$rS),
2436 "mtspr 256, $rS", IIC_IntGeneral>,
2437 PPC970_DGroup_Single, PPC970_Unit_FXU;
2438 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT), (ins),
2439 "mfspr $rT, 256", IIC_IntGeneral>,
2440 PPC970_DGroup_First, PPC970_Unit_FXU;
2442 def MTVRSAVEv : XFXForm_7_ext<31, 467, 256,
2443 (outs VRSAVERC:$reg), (ins gprc:$rS),
2444 "mtspr 256, $rS", IIC_IntGeneral>,
2445 PPC970_DGroup_Single, PPC970_Unit_FXU;
2446 def MFVRSAVEv : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT),
2447 (ins VRSAVERC:$reg),
2448 "mfspr $rT, 256", IIC_IntGeneral>,
2449 PPC970_DGroup_First, PPC970_Unit_FXU;
2452 // Aliases for mtvrsave/mfvrsave to mfspr/mtspr.
2453 def : InstAlias<"mtvrsave $rS", (MTVRSAVE gprc:$rS)>;
2454 def : InstAlias<"mfvrsave $rS", (MFVRSAVE gprc:$rS)>;
2456 // SPILL_VRSAVE - Indicate that we're dumping the VRSAVE register,
2457 // so we'll need to scavenge a register for it.
2459 def SPILL_VRSAVE : Pseudo<(outs), (ins VRSAVERC:$vrsave, memri:$F),
2460 "#SPILL_VRSAVE", []>;
2462 // RESTORE_VRSAVE - Indicate that we're restoring the VRSAVE register (previously
2463 // spilled), so we'll need to scavenge a register for it.
2465 def RESTORE_VRSAVE : Pseudo<(outs VRSAVERC:$vrsave), (ins memri:$F),
2466 "#RESTORE_VRSAVE", []>;
2468 let hasSideEffects = 0 in {
2469 // mtocrf's input needs to be prepared by shifting by an amount dependent
2470 // on the cr register selected. Thus, post-ra anti-dep breaking must not
2471 // later change that register assignment.
2472 let hasExtraDefRegAllocReq = 1 in {
2473 def MTOCRF: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins gprc:$ST),
2474 "mtocrf $FXM, $ST", IIC_BrMCRX>,
2475 PPC970_DGroup_First, PPC970_Unit_CRU;
2477 // Similarly to mtocrf, the mask for mtcrf must be prepared in a way that
2478 // is dependent on the cr fields being set.
2479 def MTCRF : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, gprc:$rS),
2480 "mtcrf $FXM, $rS", IIC_BrMCRX>,
2481 PPC970_MicroCode, PPC970_Unit_CRU;
2482 } // hasExtraDefRegAllocReq = 1
2484 // mfocrf's input needs to be prepared by shifting by an amount dependent
2485 // on the cr register selected. Thus, post-ra anti-dep breaking must not
2486 // later change that register assignment.
2487 let hasExtraSrcRegAllocReq = 1 in {
2488 def MFOCRF: XFXForm_5a<31, 19, (outs gprc:$rT), (ins crbitm:$FXM),
2489 "mfocrf $rT, $FXM", IIC_SprMFCRF>,
2490 PPC970_DGroup_First, PPC970_Unit_CRU;
2492 // Similarly to mfocrf, the mask for mfcrf must be prepared in a way that
2493 // is dependent on the cr fields being copied.
2494 def MFCR : XFXForm_3<31, 19, (outs gprc:$rT), (ins),
2495 "mfcr $rT", IIC_SprMFCR>,
2496 PPC970_MicroCode, PPC970_Unit_CRU;
2497 } // hasExtraSrcRegAllocReq = 1
2499 def MCRXRX : X_BF3<31, 576, (outs crrc:$BF), (ins),
2500 "mcrxrx $BF", IIC_BrMCRX>, Requires<[IsISA3_0]>;
2501 } // hasSideEffects = 0
2503 // Pseudo instruction to perform FADD in round-to-zero mode.
2504 let usesCustomInserter = 1, Uses = [RM] in {
2505 def FADDrtz: Pseudo<(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), "",
2506 [(set f64:$FRT, (PPCfaddrtz f64:$FRA, f64:$FRB))]>;
2509 // The above pseudo gets expanded to make use of the following instructions
2510 // to manipulate FPSCR. Note that FPSCR is not modeled at the DAG level.
2511 let Uses = [RM], Defs = [RM] in {
2512 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),
2513 "mtfsb0 $FM", IIC_IntMTFSB0, []>,
2514 PPC970_DGroup_Single, PPC970_Unit_FPU;
2515 def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),
2516 "mtfsb1 $FM", IIC_IntMTFSB0, []>,
2517 PPC970_DGroup_Single, PPC970_Unit_FPU;
2518 let isCodeGenOnly = 1 in
2519 def MTFSFb : XFLForm<63, 711, (outs), (ins i32imm:$FM, f8rc:$rT),
2520 "mtfsf $FM, $rT", IIC_IntMTFSB0, []>,
2521 PPC970_DGroup_Single, PPC970_Unit_FPU;
2523 let Uses = [RM] in {
2524 def MFFS : XForm_42<63, 583, (outs f8rc:$rT), (ins),
2525 "mffs $rT", IIC_IntMFFS,
2526 [(set f64:$rT, (PPCmffs))]>,
2527 PPC970_DGroup_Single, PPC970_Unit_FPU;
2530 def MFFSo : XForm_42<63, 583, (outs f8rc:$rT), (ins),
2531 "mffs. $rT", IIC_IntMFFS, []>, isDOT;
2535 let PPC970_Unit = 1, hasSideEffects = 0 in { // FXU Operations.
2536 // XO-Form instructions. Arithmetic instructions that can set overflow bit
2537 let isCommutable = 1 in
2538 defm ADD4 : XOForm_1r<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2539 "add", "$rT, $rA, $rB", IIC_IntSimple,
2540 [(set i32:$rT, (add i32:$rA, i32:$rB))]>;
2541 let isCodeGenOnly = 1 in
2542 def ADD4TLS : XOForm_1<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, tlsreg32:$rB),
2543 "add $rT, $rA, $rB", IIC_IntSimple,
2544 [(set i32:$rT, (add i32:$rA, tglobaltlsaddr:$rB))]>;
2545 let isCommutable = 1 in
2546 defm ADDC : XOForm_1rc<31, 10, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2547 "addc", "$rT, $rA, $rB", IIC_IntGeneral,
2548 [(set i32:$rT, (addc i32:$rA, i32:$rB))]>,
2549 PPC970_DGroup_Cracked;
2551 defm DIVW : XOForm_1rcr<31, 491, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2552 "divw", "$rT, $rA, $rB", IIC_IntDivW,
2553 [(set i32:$rT, (sdiv i32:$rA, i32:$rB))]>;
2554 defm DIVWU : XOForm_1rcr<31, 459, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2555 "divwu", "$rT, $rA, $rB", IIC_IntDivW,
2556 [(set i32:$rT, (udiv i32:$rA, i32:$rB))]>;
2557 def DIVWE : XOForm_1<31, 427, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2558 "divwe $rT, $rA, $rB", IIC_IntDivW,
2559 [(set i32:$rT, (int_ppc_divwe gprc:$rA, gprc:$rB))]>,
2560 Requires<[HasExtDiv]>;
2562 def DIVWEo : XOForm_1<31, 427, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2563 "divwe. $rT, $rA, $rB", IIC_IntDivW,
2564 []>, isDOT, PPC970_DGroup_Cracked, PPC970_DGroup_First,
2565 Requires<[HasExtDiv]>;
2566 def DIVWEU : XOForm_1<31, 395, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2567 "divweu $rT, $rA, $rB", IIC_IntDivW,
2568 [(set i32:$rT, (int_ppc_divweu gprc:$rA, gprc:$rB))]>,
2569 Requires<[HasExtDiv]>;
2571 def DIVWEUo : XOForm_1<31, 395, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2572 "divweu. $rT, $rA, $rB", IIC_IntDivW,
2573 []>, isDOT, PPC970_DGroup_Cracked, PPC970_DGroup_First,
2574 Requires<[HasExtDiv]>;
2575 let isCommutable = 1 in {
2576 defm MULHW : XOForm_1r<31, 75, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2577 "mulhw", "$rT, $rA, $rB", IIC_IntMulHW,
2578 [(set i32:$rT, (mulhs i32:$rA, i32:$rB))]>;
2579 defm MULHWU : XOForm_1r<31, 11, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2580 "mulhwu", "$rT, $rA, $rB", IIC_IntMulHWU,
2581 [(set i32:$rT, (mulhu i32:$rA, i32:$rB))]>;
2582 defm MULLW : XOForm_1r<31, 235, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2583 "mullw", "$rT, $rA, $rB", IIC_IntMulHW,
2584 [(set i32:$rT, (mul i32:$rA, i32:$rB))]>;
2586 defm SUBF : XOForm_1r<31, 40, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2587 "subf", "$rT, $rA, $rB", IIC_IntGeneral,
2588 [(set i32:$rT, (sub i32:$rB, i32:$rA))]>;
2589 defm SUBFC : XOForm_1rc<31, 8, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2590 "subfc", "$rT, $rA, $rB", IIC_IntGeneral,
2591 [(set i32:$rT, (subc i32:$rB, i32:$rA))]>,
2592 PPC970_DGroup_Cracked;
2593 defm NEG : XOForm_3r<31, 104, 0, (outs gprc:$rT), (ins gprc:$rA),
2594 "neg", "$rT, $rA", IIC_IntSimple,
2595 [(set i32:$rT, (ineg i32:$rA))]>;
2596 let Uses = [CARRY] in {
2597 let isCommutable = 1 in
2598 defm ADDE : XOForm_1rc<31, 138, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2599 "adde", "$rT, $rA, $rB", IIC_IntGeneral,
2600 [(set i32:$rT, (adde i32:$rA, i32:$rB))]>;
2601 defm ADDME : XOForm_3rc<31, 234, 0, (outs gprc:$rT), (ins gprc:$rA),
2602 "addme", "$rT, $rA", IIC_IntGeneral,
2603 [(set i32:$rT, (adde i32:$rA, -1))]>;
2604 defm ADDZE : XOForm_3rc<31, 202, 0, (outs gprc:$rT), (ins gprc:$rA),
2605 "addze", "$rT, $rA", IIC_IntGeneral,
2606 [(set i32:$rT, (adde i32:$rA, 0))]>;
2607 defm SUBFE : XOForm_1rc<31, 136, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2608 "subfe", "$rT, $rA, $rB", IIC_IntGeneral,
2609 [(set i32:$rT, (sube i32:$rB, i32:$rA))]>;
2610 defm SUBFME : XOForm_3rc<31, 232, 0, (outs gprc:$rT), (ins gprc:$rA),
2611 "subfme", "$rT, $rA", IIC_IntGeneral,
2612 [(set i32:$rT, (sube -1, i32:$rA))]>;
2613 defm SUBFZE : XOForm_3rc<31, 200, 0, (outs gprc:$rT), (ins gprc:$rA),
2614 "subfze", "$rT, $rA", IIC_IntGeneral,
2615 [(set i32:$rT, (sube 0, i32:$rA))]>;
2619 // A-Form instructions. Most of the instructions executed in the FPU are of
2622 let PPC970_Unit = 3, hasSideEffects = 0 in { // FPU Operations.
2623 let Uses = [RM] in {
2624 let isCommutable = 1 in {
2625 defm FMADD : AForm_1r<63, 29,
2626 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2627 "fmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2628 [(set f64:$FRT, (fma f64:$FRA, f64:$FRC, f64:$FRB))]>;
2629 defm FMADDS : AForm_1r<59, 29,
2630 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2631 "fmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2632 [(set f32:$FRT, (fma f32:$FRA, f32:$FRC, f32:$FRB))]>;
2633 defm FMSUB : AForm_1r<63, 28,
2634 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2635 "fmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2637 (fma f64:$FRA, f64:$FRC, (fneg f64:$FRB)))]>;
2638 defm FMSUBS : AForm_1r<59, 28,
2639 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2640 "fmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2642 (fma f32:$FRA, f32:$FRC, (fneg f32:$FRB)))]>;
2643 defm FNMADD : AForm_1r<63, 31,
2644 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2645 "fnmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2647 (fneg (fma f64:$FRA, f64:$FRC, f64:$FRB)))]>;
2648 defm FNMADDS : AForm_1r<59, 31,
2649 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2650 "fnmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2652 (fneg (fma f32:$FRA, f32:$FRC, f32:$FRB)))]>;
2653 defm FNMSUB : AForm_1r<63, 30,
2654 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2655 "fnmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2656 [(set f64:$FRT, (fneg (fma f64:$FRA, f64:$FRC,
2657 (fneg f64:$FRB))))]>;
2658 defm FNMSUBS : AForm_1r<59, 30,
2659 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2660 "fnmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2661 [(set f32:$FRT, (fneg (fma f32:$FRA, f32:$FRC,
2662 (fneg f32:$FRB))))]>;
2665 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
2666 // having 4 of these, force the comparison to always be an 8-byte double (code
2667 // should use an FMRSD if the input comparison value really wants to be a float)
2668 // and 4/8 byte forms for the result and operand type..
2669 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2670 defm FSELD : AForm_1r<63, 23,
2671 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2672 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2673 [(set f64:$FRT, (PPCfsel f64:$FRA, f64:$FRC, f64:$FRB))]>;
2674 defm FSELS : AForm_1r<63, 23,
2675 (outs f4rc:$FRT), (ins f8rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2676 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2677 [(set f32:$FRT, (PPCfsel f64:$FRA, f32:$FRC, f32:$FRB))]>;
2678 let Uses = [RM] in {
2679 let isCommutable = 1 in {
2680 defm FADD : AForm_2r<63, 21,
2681 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2682 "fadd", "$FRT, $FRA, $FRB", IIC_FPAddSub,
2683 [(set f64:$FRT, (fadd f64:$FRA, f64:$FRB))]>;
2684 defm FADDS : AForm_2r<59, 21,
2685 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2686 "fadds", "$FRT, $FRA, $FRB", IIC_FPGeneral,
2687 [(set f32:$FRT, (fadd f32:$FRA, f32:$FRB))]>;
2689 defm FDIV : AForm_2r<63, 18,
2690 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2691 "fdiv", "$FRT, $FRA, $FRB", IIC_FPDivD,
2692 [(set f64:$FRT, (fdiv f64:$FRA, f64:$FRB))]>;
2693 defm FDIVS : AForm_2r<59, 18,
2694 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2695 "fdivs", "$FRT, $FRA, $FRB", IIC_FPDivS,
2696 [(set f32:$FRT, (fdiv f32:$FRA, f32:$FRB))]>;
2697 let isCommutable = 1 in {
2698 defm FMUL : AForm_3r<63, 25,
2699 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC),
2700 "fmul", "$FRT, $FRA, $FRC", IIC_FPFused,
2701 [(set f64:$FRT, (fmul f64:$FRA, f64:$FRC))]>;
2702 defm FMULS : AForm_3r<59, 25,
2703 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC),
2704 "fmuls", "$FRT, $FRA, $FRC", IIC_FPGeneral,
2705 [(set f32:$FRT, (fmul f32:$FRA, f32:$FRC))]>;
2707 defm FSUB : AForm_2r<63, 20,
2708 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2709 "fsub", "$FRT, $FRA, $FRB", IIC_FPAddSub,
2710 [(set f64:$FRT, (fsub f64:$FRA, f64:$FRB))]>;
2711 defm FSUBS : AForm_2r<59, 20,
2712 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2713 "fsubs", "$FRT, $FRA, $FRB", IIC_FPGeneral,
2714 [(set f32:$FRT, (fsub f32:$FRA, f32:$FRB))]>;
2718 let hasSideEffects = 0 in {
2719 let PPC970_Unit = 1 in { // FXU Operations.
2721 def ISEL : AForm_4<31, 15,
2722 (outs gprc:$rT), (ins gprc_nor0:$rA, gprc:$rB, crbitrc:$cond),
2723 "isel $rT, $rA, $rB, $cond", IIC_IntISEL,
2727 let PPC970_Unit = 1 in { // FXU Operations.
2728 // M-Form instructions. rotate and mask instructions.
2730 let isCommutable = 1 in {
2731 // RLWIMI can be commuted if the rotate amount is zero.
2732 defm RLWIMI : MForm_2r<20, (outs gprc:$rA),
2733 (ins gprc:$rSi, gprc:$rS, u5imm:$SH, u5imm:$MB,
2734 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME",
2735 IIC_IntRotate, []>, PPC970_DGroup_Cracked,
2736 RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">;
2738 let BaseName = "rlwinm" in {
2739 def RLWINM : MForm_2<21,
2740 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
2741 "rlwinm $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
2744 def RLWINMo : MForm_2<21,
2745 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
2746 "rlwinm. $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
2747 []>, isDOT, RecFormRel, PPC970_DGroup_Cracked;
2749 defm RLWNM : MForm_2r<23, (outs gprc:$rA),
2750 (ins gprc:$rS, gprc:$rB, u5imm:$MB, u5imm:$ME),
2751 "rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral,
2754 } // hasSideEffects = 0
2756 //===----------------------------------------------------------------------===//
2757 // PowerPC Instruction Patterns
2760 // Arbitrary immediate support. Implement in terms of LIS/ORI.
2761 def : Pat<(i32 imm:$imm),
2762 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
2764 // Implement the 'not' operation with the NOR instruction.
2765 def i32not : OutPatFrag<(ops node:$in),
2767 def : Pat<(not i32:$in),
2770 // ADD an arbitrary immediate.
2771 def : Pat<(add i32:$in, imm:$imm),
2772 (ADDIS (ADDI $in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
2773 // OR an arbitrary immediate.
2774 def : Pat<(or i32:$in, imm:$imm),
2775 (ORIS (ORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
2776 // XOR an arbitrary immediate.
2777 def : Pat<(xor i32:$in, imm:$imm),
2778 (XORIS (XORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
2780 def : Pat<(sub imm32SExt16:$imm, i32:$in),
2781 (SUBFIC $in, imm:$imm)>;
2784 def : Pat<(shl i32:$in, (i32 imm:$imm)),
2785 (RLWINM $in, imm:$imm, 0, (SHL32 imm:$imm))>;
2786 def : Pat<(srl i32:$in, (i32 imm:$imm)),
2787 (RLWINM $in, (SRL32 imm:$imm), imm:$imm, 31)>;
2790 def : Pat<(rotl i32:$in, i32:$sh),
2791 (RLWNM $in, $sh, 0, 31)>;
2792 def : Pat<(rotl i32:$in, (i32 imm:$imm)),
2793 (RLWINM $in, imm:$imm, 0, 31)>;
2796 def : Pat<(and (rotl i32:$in, i32:$sh), maskimm32:$imm),
2797 (RLWNM $in, $sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
2800 def : Pat<(PPCcall (i32 tglobaladdr:$dst)),
2801 (BL tglobaladdr:$dst)>;
2802 def : Pat<(PPCcall (i32 texternalsym:$dst)),
2803 (BL texternalsym:$dst)>;
2805 def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm),
2806 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>;
2808 def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm),
2809 (TCRETURNdi texternalsym:$dst, imm:$imm)>;
2811 def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm),
2812 (TCRETURNri CTRRC:$dst, imm:$imm)>;
2816 // Hi and Lo for Darwin Global Addresses.
2817 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
2818 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
2819 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
2820 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
2821 def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
2822 def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
2823 def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>;
2824 def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>;
2825 def : Pat<(PPChi tglobaltlsaddr:$g, i32:$in),
2826 (ADDIS $in, tglobaltlsaddr:$g)>;
2827 def : Pat<(PPClo tglobaltlsaddr:$g, i32:$in),
2828 (ADDI $in, tglobaltlsaddr:$g)>;
2829 def : Pat<(add i32:$in, (PPChi tglobaladdr:$g, 0)),
2830 (ADDIS $in, tglobaladdr:$g)>;
2831 def : Pat<(add i32:$in, (PPChi tconstpool:$g, 0)),
2832 (ADDIS $in, tconstpool:$g)>;
2833 def : Pat<(add i32:$in, (PPChi tjumptable:$g, 0)),
2834 (ADDIS $in, tjumptable:$g)>;
2835 def : Pat<(add i32:$in, (PPChi tblockaddress:$g, 0)),
2836 (ADDIS $in, tblockaddress:$g)>;
2838 // Support for thread-local storage.
2839 def PPC32GOT: Pseudo<(outs gprc:$rD), (ins), "#PPC32GOT",
2840 [(set i32:$rD, (PPCppc32GOT))]>;
2842 // Get the _GLOBAL_OFFSET_TABLE_ in PIC mode.
2843 // This uses two output registers, the first as the real output, the second as a
2844 // temporary register, used internally in code generation.
2845 def PPC32PICGOT: Pseudo<(outs gprc:$rD, gprc:$rT), (ins), "#PPC32PICGOT",
2846 []>, NoEncode<"$rT">;
2848 def LDgotTprelL32: Pseudo<(outs gprc:$rD), (ins s16imm:$disp, gprc_nor0:$reg),
2851 (PPCldGotTprelL tglobaltlsaddr:$disp, i32:$reg))]>;
2852 def : Pat<(PPCaddTls i32:$in, tglobaltlsaddr:$g),
2853 (ADD4TLS $in, tglobaltlsaddr:$g)>;
2855 def ADDItlsgdL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2858 (PPCaddiTlsgdL i32:$reg, tglobaltlsaddr:$disp))]>;
2859 // LR is a true define, while the rest of the Defs are clobbers. R3 is
2860 // explicitly defined when this op is created, so not mentioned here.
2861 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
2862 Defs = [R0,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in
2863 def GETtlsADDR32 : Pseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym),
2866 (PPCgetTlsAddr i32:$reg, tglobaltlsaddr:$sym))]>;
2867 // Combined op for ADDItlsgdL32 and GETtlsADDR32, late expanded. R3 and LR
2868 // are true defines while the rest of the Defs are clobbers.
2869 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
2870 Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in
2871 def ADDItlsgdLADDR32 : Pseudo<(outs gprc:$rD),
2872 (ins gprc_nor0:$reg, s16imm:$disp, tlsgd32:$sym),
2873 "#ADDItlsgdLADDR32",
2875 (PPCaddiTlsgdLAddr i32:$reg,
2876 tglobaltlsaddr:$disp,
2877 tglobaltlsaddr:$sym))]>;
2878 def ADDItlsldL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2881 (PPCaddiTlsldL i32:$reg, tglobaltlsaddr:$disp))]>;
2882 // LR is a true define, while the rest of the Defs are clobbers. R3 is
2883 // explicitly defined when this op is created, so not mentioned here.
2884 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
2885 Defs = [R0,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in
2886 def GETtlsldADDR32 : Pseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym),
2889 (PPCgetTlsldAddr i32:$reg,
2890 tglobaltlsaddr:$sym))]>;
2891 // Combined op for ADDItlsldL32 and GETtlsADDR32, late expanded. R3 and LR
2892 // are true defines while the rest of the Defs are clobbers.
2893 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
2894 Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in
2895 def ADDItlsldLADDR32 : Pseudo<(outs gprc:$rD),
2896 (ins gprc_nor0:$reg, s16imm:$disp, tlsgd32:$sym),
2897 "#ADDItlsldLADDR32",
2899 (PPCaddiTlsldLAddr i32:$reg,
2900 tglobaltlsaddr:$disp,
2901 tglobaltlsaddr:$sym))]>;
2902 def ADDIdtprelL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2905 (PPCaddiDtprelL i32:$reg, tglobaltlsaddr:$disp))]>;
2906 def ADDISdtprelHA32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2909 (PPCaddisDtprelHA i32:$reg,
2910 tglobaltlsaddr:$disp))]>;
2912 // Support for Position-independent code
2913 def LWZtoc : Pseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc:$reg),
2916 (PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>;
2917 // Get Global (GOT) Base Register offset, from the word immediately preceding
2918 // the function label.
2919 def UpdateGBR : Pseudo<(outs gprc:$rD, gprc:$rT), (ins gprc:$rI), "#UpdateGBR", []>;
2922 // Standard shifts. These are represented separately from the real shifts above
2923 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
2925 def : Pat<(sra i32:$rS, i32:$rB),
2927 def : Pat<(srl i32:$rS, i32:$rB),
2929 def : Pat<(shl i32:$rS, i32:$rB),
2932 def : Pat<(zextloadi1 iaddr:$src),
2934 def : Pat<(zextloadi1 xaddr:$src),
2936 def : Pat<(extloadi1 iaddr:$src),
2938 def : Pat<(extloadi1 xaddr:$src),
2940 def : Pat<(extloadi8 iaddr:$src),
2942 def : Pat<(extloadi8 xaddr:$src),
2944 def : Pat<(extloadi16 iaddr:$src),
2946 def : Pat<(extloadi16 xaddr:$src),
2948 def : Pat<(f64 (extloadf32 iaddr:$src)),
2949 (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>;
2950 def : Pat<(f64 (extloadf32 xaddr:$src)),
2951 (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>;
2953 def : Pat<(f64 (fpextend f32:$src)),
2954 (COPY_TO_REGCLASS $src, F8RC)>;
2956 // Only seq_cst fences require the heavyweight sync (SYNC 0).
2957 // All others can use the lightweight sync (SYNC 1).
2958 // source: http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
2959 // The rule for seq_cst is duplicated to work with both 64 bits and 32 bits
2960 // versions of Power.
2961 def : Pat<(atomic_fence (i64 7), (imm)), (SYNC 0)>, Requires<[HasSYNC]>;
2962 def : Pat<(atomic_fence (i32 7), (imm)), (SYNC 0)>, Requires<[HasSYNC]>;
2963 def : Pat<(atomic_fence (imm), (imm)), (SYNC 1)>, Requires<[HasSYNC]>;
2964 def : Pat<(atomic_fence (imm), (imm)), (MSYNC)>, Requires<[HasOnlyMSYNC]>;
2966 // Additional FNMSUB patterns: -a*c + b == -(a*c - b)
2967 def : Pat<(fma (fneg f64:$A), f64:$C, f64:$B),
2968 (FNMSUB $A, $C, $B)>;
2969 def : Pat<(fma f64:$A, (fneg f64:$C), f64:$B),
2970 (FNMSUB $A, $C, $B)>;
2971 def : Pat<(fma (fneg f32:$A), f32:$C, f32:$B),
2972 (FNMSUBS $A, $C, $B)>;
2973 def : Pat<(fma f32:$A, (fneg f32:$C), f32:$B),
2974 (FNMSUBS $A, $C, $B)>;
2976 // FCOPYSIGN's operand types need not agree.
2977 def : Pat<(fcopysign f64:$frB, f32:$frA),
2978 (FCPSGND (COPY_TO_REGCLASS $frA, F8RC), $frB)>;
2979 def : Pat<(fcopysign f32:$frB, f64:$frA),
2980 (FCPSGNS (COPY_TO_REGCLASS $frA, F4RC), $frB)>;
2982 include "PPCInstrAltivec.td"
2983 include "PPCInstrSPE.td"
2984 include "PPCInstr64Bit.td"
2985 include "PPCInstrVSX.td"
2986 include "PPCInstrQPX.td"
2987 include "PPCInstrHTM.td"
2989 def crnot : OutPatFrag<(ops node:$in),
2991 def : Pat<(not i1:$in),
2994 // Patterns for arithmetic i1 operations.
2995 def : Pat<(add i1:$a, i1:$b),
2997 def : Pat<(sub i1:$a, i1:$b),
2999 def : Pat<(mul i1:$a, i1:$b),
3002 // We're sometimes asked to materialize i1 -1, which is just 1 in this case
3003 // (-1 is used to mean all bits set).
3004 def : Pat<(i1 -1), (CRSET)>;
3006 // i1 extensions, implemented in terms of isel.
3007 def : Pat<(i32 (zext i1:$in)),
3008 (SELECT_I4 $in, (LI 1), (LI 0))>;
3009 def : Pat<(i32 (sext i1:$in)),
3010 (SELECT_I4 $in, (LI -1), (LI 0))>;
3012 def : Pat<(i64 (zext i1:$in)),
3013 (SELECT_I8 $in, (LI8 1), (LI8 0))>;
3014 def : Pat<(i64 (sext i1:$in)),
3015 (SELECT_I8 $in, (LI8 -1), (LI8 0))>;
3017 // FIXME: We should choose either a zext or a sext based on other constants
3019 def : Pat<(i32 (anyext i1:$in)),
3020 (SELECT_I4 $in, (LI 1), (LI 0))>;
3021 def : Pat<(i64 (anyext i1:$in)),
3022 (SELECT_I8 $in, (LI8 1), (LI8 0))>;
3024 // match setcc on i1 variables.
3042 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLT)),
3044 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULT)),
3063 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLE)),
3065 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULE)),
3068 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETEQ)),
3082 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGE)),
3084 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGE)),
3098 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGT)),
3100 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGT)),
3103 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETNE)),
3106 // match setcc on non-i1 (non-vector) variables. Note that SETUEQ, SETOGE,
3107 // SETOLE, SETONE, SETULT and SETUGT should be expanded by legalize for
3108 // floating-point types.
3110 multiclass CRNotPat<dag pattern, dag result> {
3111 def : Pat<pattern, (crnot result)>;
3112 def : Pat<(not pattern), result>;
3114 // We can also fold the crnot into an extension:
3115 def : Pat<(i32 (zext pattern)),
3116 (SELECT_I4 result, (LI 0), (LI 1))>;
3117 def : Pat<(i32 (sext pattern)),
3118 (SELECT_I4 result, (LI 0), (LI -1))>;
3120 // We can also fold the crnot into an extension:
3121 def : Pat<(i64 (zext pattern)),
3122 (SELECT_I8 result, (LI8 0), (LI8 1))>;
3123 def : Pat<(i64 (sext pattern)),
3124 (SELECT_I8 result, (LI8 0), (LI8 -1))>;
3126 // FIXME: We should choose either a zext or a sext based on other constants
3128 def : Pat<(i32 (anyext pattern)),
3129 (SELECT_I4 result, (LI 0), (LI 1))>;
3131 def : Pat<(i64 (anyext pattern)),
3132 (SELECT_I8 result, (LI8 0), (LI8 1))>;
3135 // FIXME: Because of what seems like a bug in TableGen's type-inference code,
3136 // we need to write imm:$imm in the output patterns below, not just $imm, or
3137 // else the resulting matcher will not correctly add the immediate operand
3138 // (making it a register operand instead).
3141 multiclass ExtSetCCPat<CondCode cc, PatFrag pfrag,
3142 OutPatFrag rfrag, OutPatFrag rfrag8> {
3143 def : Pat<(i32 (zext (i1 (pfrag i32:$s1, cc)))),
3145 def : Pat<(i64 (zext (i1 (pfrag i64:$s1, cc)))),
3147 def : Pat<(i64 (zext (i1 (pfrag i32:$s1, cc)))),
3148 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>;
3149 def : Pat<(i32 (zext (i1 (pfrag i64:$s1, cc)))),
3150 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>;
3152 def : Pat<(i32 (anyext (i1 (pfrag i32:$s1, cc)))),
3154 def : Pat<(i64 (anyext (i1 (pfrag i64:$s1, cc)))),
3156 def : Pat<(i64 (anyext (i1 (pfrag i32:$s1, cc)))),
3157 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>;
3158 def : Pat<(i32 (anyext (i1 (pfrag i64:$s1, cc)))),
3159 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>;
3162 // Note that we do all inversions below with i(32|64)not, instead of using
3163 // (xori x, 1) because on the A2 nor has single-cycle latency while xori
3164 // has 2-cycle latency.
3166 defm : ExtSetCCPat<SETEQ,
3167 PatFrag<(ops node:$in, node:$cc),
3168 (setcc $in, 0, $cc)>,
3169 OutPatFrag<(ops node:$in),
3170 (RLWINM (CNTLZW $in), 27, 31, 31)>,
3171 OutPatFrag<(ops node:$in),
3172 (RLDICL (CNTLZD $in), 58, 63)> >;
3174 defm : ExtSetCCPat<SETNE,
3175 PatFrag<(ops node:$in, node:$cc),
3176 (setcc $in, 0, $cc)>,
3177 OutPatFrag<(ops node:$in),
3178 (RLWINM (i32not (CNTLZW $in)), 27, 31, 31)>,
3179 OutPatFrag<(ops node:$in),
3180 (RLDICL (i64not (CNTLZD $in)), 58, 63)> >;
3182 defm : ExtSetCCPat<SETLT,
3183 PatFrag<(ops node:$in, node:$cc),
3184 (setcc $in, 0, $cc)>,
3185 OutPatFrag<(ops node:$in),
3186 (RLWINM $in, 1, 31, 31)>,
3187 OutPatFrag<(ops node:$in),
3188 (RLDICL $in, 1, 63)> >;
3190 defm : ExtSetCCPat<SETGE,
3191 PatFrag<(ops node:$in, node:$cc),
3192 (setcc $in, 0, $cc)>,
3193 OutPatFrag<(ops node:$in),
3194 (RLWINM (i32not $in), 1, 31, 31)>,
3195 OutPatFrag<(ops node:$in),
3196 (RLDICL (i64not $in), 1, 63)> >;
3198 defm : ExtSetCCPat<SETGT,
3199 PatFrag<(ops node:$in, node:$cc),
3200 (setcc $in, 0, $cc)>,
3201 OutPatFrag<(ops node:$in),
3202 (RLWINM (ANDC (NEG $in), $in), 1, 31, 31)>,
3203 OutPatFrag<(ops node:$in),
3204 (RLDICL (ANDC8 (NEG8 $in), $in), 1, 63)> >;
3206 defm : ExtSetCCPat<SETLE,
3207 PatFrag<(ops node:$in, node:$cc),
3208 (setcc $in, 0, $cc)>,
3209 OutPatFrag<(ops node:$in),
3210 (RLWINM (ORC $in, (NEG $in)), 1, 31, 31)>,
3211 OutPatFrag<(ops node:$in),
3212 (RLDICL (ORC8 $in, (NEG8 $in)), 1, 63)> >;
3214 defm : ExtSetCCPat<SETLT,
3215 PatFrag<(ops node:$in, node:$cc),
3216 (setcc $in, -1, $cc)>,
3217 OutPatFrag<(ops node:$in),
3218 (RLWINM (AND $in, (ADDI $in, 1)), 1, 31, 31)>,
3219 OutPatFrag<(ops node:$in),
3220 (RLDICL (AND8 $in, (ADDI8 $in, 1)), 1, 63)> >;
3222 defm : ExtSetCCPat<SETGE,
3223 PatFrag<(ops node:$in, node:$cc),
3224 (setcc $in, -1, $cc)>,
3225 OutPatFrag<(ops node:$in),
3226 (RLWINM (NAND $in, (ADDI $in, 1)), 1, 31, 31)>,
3227 OutPatFrag<(ops node:$in),
3228 (RLDICL (NAND8 $in, (ADDI8 $in, 1)), 1, 63)> >;
3230 defm : ExtSetCCPat<SETGT,
3231 PatFrag<(ops node:$in, node:$cc),
3232 (setcc $in, -1, $cc)>,
3233 OutPatFrag<(ops node:$in),
3234 (RLWINM (i32not $in), 1, 31, 31)>,
3235 OutPatFrag<(ops node:$in),
3236 (RLDICL (i64not $in), 1, 63)> >;
3238 defm : ExtSetCCPat<SETLE,
3239 PatFrag<(ops node:$in, node:$cc),
3240 (setcc $in, -1, $cc)>,
3241 OutPatFrag<(ops node:$in),
3242 (RLWINM $in, 1, 31, 31)>,
3243 OutPatFrag<(ops node:$in),
3244 (RLDICL $in, 1, 63)> >;
3246 // An extended SETCC with shift amount.
3247 multiclass ExtSetCCShiftPat<CondCode cc, PatFrag pfrag,
3248 OutPatFrag rfrag, OutPatFrag rfrag8> {
3249 def : Pat<(i32 (zext (i1 (pfrag i32:$s1, i32:$sa, cc)))),
3251 def : Pat<(i64 (zext (i1 (pfrag i64:$s1, i32:$sa, cc)))),
3253 def : Pat<(i64 (zext (i1 (pfrag i32:$s1, i32:$sa, cc)))),
3254 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1, $sa), sub_32)>;
3255 def : Pat<(i32 (zext (i1 (pfrag i64:$s1, i32:$sa, cc)))),
3256 (EXTRACT_SUBREG (rfrag8 $s1, $sa), sub_32)>;
3258 def : Pat<(i32 (anyext (i1 (pfrag i32:$s1, i32:$sa, cc)))),
3260 def : Pat<(i64 (anyext (i1 (pfrag i64:$s1, i32:$sa, cc)))),
3262 def : Pat<(i64 (anyext (i1 (pfrag i32:$s1, i32:$sa, cc)))),
3263 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1, $sa), sub_32)>;
3264 def : Pat<(i32 (anyext (i1 (pfrag i64:$s1, i32:$sa, cc)))),
3265 (EXTRACT_SUBREG (rfrag8 $s1, $sa), sub_32)>;
3268 defm : ExtSetCCShiftPat<SETNE,
3269 PatFrag<(ops node:$in, node:$sa, node:$cc),
3270 (setcc (and $in, (shl 1, $sa)), 0, $cc)>,
3271 OutPatFrag<(ops node:$in, node:$sa),
3272 (RLWNM $in, (SUBFIC $sa, 32), 31, 31)>,
3273 OutPatFrag<(ops node:$in, node:$sa),
3274 (RLDCL $in, (SUBFIC $sa, 64), 63)> >;
3276 defm : ExtSetCCShiftPat<SETEQ,
3277 PatFrag<(ops node:$in, node:$sa, node:$cc),
3278 (setcc (and $in, (shl 1, $sa)), 0, $cc)>,
3279 OutPatFrag<(ops node:$in, node:$sa),
3280 (RLWNM (i32not $in),
3281 (SUBFIC $sa, 32), 31, 31)>,
3282 OutPatFrag<(ops node:$in, node:$sa),
3283 (RLDCL (i64not $in),
3284 (SUBFIC $sa, 64), 63)> >;
3287 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULT)),
3288 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>;
3289 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLT)),
3290 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>;
3291 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGT)),
3292 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>;
3293 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGT)),
3294 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>;
3295 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETEQ)),
3296 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>;
3297 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETEQ)),
3298 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>;
3300 // For non-equality comparisons, the default code would materialize the
3301 // constant, then compare against it, like this:
3303 // ori r2, r2, 22136
3306 // Since we are just comparing for equality, we can emit this instead:
3307 // xoris r0,r3,0x1234
3308 // cmplwi cr0,r0,0x5678
3311 def : Pat<(i1 (setcc i32:$s1, imm:$imm, SETEQ)),
3312 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)),
3313 (LO16 imm:$imm)), sub_eq)>;
3315 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGE)),
3316 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>;
3317 defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGE)),
3318 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>;
3319 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULE)),
3320 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>;
3321 defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLE)),
3322 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>;
3323 defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETNE)),
3324 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>;
3325 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETNE)),
3326 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>;
3328 defm : CRNotPat<(i1 (setcc i32:$s1, imm:$imm, SETNE)),
3329 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)),
3330 (LO16 imm:$imm)), sub_eq)>;
3332 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETULT)),
3333 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>;
3334 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETLT)),
3335 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>;
3336 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETUGT)),
3337 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>;
3338 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETGT)),
3339 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>;
3340 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETEQ)),
3341 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>;
3343 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETUGE)),
3344 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>;
3345 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETGE)),
3346 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>;
3347 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETULE)),
3348 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>;
3349 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETLE)),
3350 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>;
3351 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETNE)),
3352 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>;
3355 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULT)),
3356 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>;
3357 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLT)),
3358 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>;
3359 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGT)),
3360 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>;
3361 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGT)),
3362 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>;
3363 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETEQ)),
3364 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>;
3365 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETEQ)),
3366 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>;
3368 // For non-equality comparisons, the default code would materialize the
3369 // constant, then compare against it, like this:
3371 // ori r2, r2, 22136
3374 // Since we are just comparing for equality, we can emit this instead:
3375 // xoris r0,r3,0x1234
3376 // cmpldi cr0,r0,0x5678
3379 def : Pat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETEQ)),
3380 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)),
3381 (LO16 imm:$imm)), sub_eq)>;
3383 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGE)),
3384 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>;
3385 defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGE)),
3386 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>;
3387 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULE)),
3388 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>;
3389 defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLE)),
3390 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>;
3391 defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETNE)),
3392 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>;
3393 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETNE)),
3394 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>;
3396 defm : CRNotPat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETNE)),
3397 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)),
3398 (LO16 imm:$imm)), sub_eq)>;
3400 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETULT)),
3401 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>;
3402 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETLT)),
3403 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>;
3404 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETUGT)),
3405 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>;
3406 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETGT)),
3407 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>;
3408 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETEQ)),
3409 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>;
3411 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETUGE)),
3412 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>;
3413 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETGE)),
3414 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>;
3415 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETULE)),
3416 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>;
3417 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETLE)),
3418 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>;
3419 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETNE)),
3420 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>;
3423 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOLT)),
3424 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
3425 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETLT)),
3426 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
3427 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOGT)),
3428 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
3429 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETGT)),
3430 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
3431 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOEQ)),
3432 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
3433 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETEQ)),
3434 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
3435 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETUO)),
3436 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_un)>;
3438 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUGE)),
3439 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
3440 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETGE)),
3441 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
3442 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETULE)),
3443 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
3444 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETLE)),
3445 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
3446 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUNE)),
3447 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
3448 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETNE)),
3449 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
3450 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETO)),
3451 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_un)>;
3454 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOLT)),
3455 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
3456 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETLT)),
3457 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
3458 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOGT)),
3459 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
3460 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETGT)),
3461 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
3462 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOEQ)),
3463 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
3464 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETEQ)),
3465 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
3466 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETUO)),
3467 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un)>;
3469 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUGE)),
3470 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
3471 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETGE)),
3472 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
3473 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETULE)),
3474 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
3475 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETLE)),
3476 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
3477 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUNE)),
3478 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
3479 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETNE)),
3480 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
3481 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETO)),
3482 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un)>;
3484 // match select on i1 variables:
3485 def : Pat<(i1 (select i1:$cond, i1:$tval, i1:$fval)),
3486 (CROR (CRAND $cond , $tval),
3487 (CRAND (crnot $cond), $fval))>;
3489 // match selectcc on i1 variables:
3490 // select (lhs == rhs), tval, fval is:
3491 // ((lhs == rhs) & tval) | (!(lhs == rhs) & fval)
3492 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLT)),
3493 (CROR (CRAND (CRANDC $lhs, $rhs), $tval),
3494 (CRAND (CRORC $rhs, $lhs), $fval))>;
3495 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETULT)),
3496 (CROR (CRAND (CRANDC $rhs, $lhs), $tval),
3497 (CRAND (CRORC $lhs, $rhs), $fval))>;
3498 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLE)),
3499 (CROR (CRAND (CRORC $lhs, $rhs), $tval),
3500 (CRAND (CRANDC $rhs, $lhs), $fval))>;
3501 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETULE)),
3502 (CROR (CRAND (CRORC $rhs, $lhs), $tval),
3503 (CRAND (CRANDC $lhs, $rhs), $fval))>;
3504 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETEQ)),
3505 (CROR (CRAND (CREQV $lhs, $rhs), $tval),
3506 (CRAND (CRXOR $lhs, $rhs), $fval))>;
3507 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGE)),
3508 (CROR (CRAND (CRORC $rhs, $lhs), $tval),
3509 (CRAND (CRANDC $lhs, $rhs), $fval))>;
3510 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETUGE)),
3511 (CROR (CRAND (CRORC $lhs, $rhs), $tval),
3512 (CRAND (CRANDC $rhs, $lhs), $fval))>;
3513 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGT)),
3514 (CROR (CRAND (CRANDC $rhs, $lhs), $tval),
3515 (CRAND (CRORC $lhs, $rhs), $fval))>;
3516 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETUGT)),
3517 (CROR (CRAND (CRANDC $lhs, $rhs), $tval),
3518 (CRAND (CRORC $rhs, $lhs), $fval))>;
3519 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETNE)),
3520 (CROR (CRAND (CREQV $lhs, $rhs), $fval),
3521 (CRAND (CRXOR $lhs, $rhs), $tval))>;
3523 // match selectcc on i1 variables with non-i1 output.
3524 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLT)),
3525 (SELECT_I4 (CRANDC $lhs, $rhs), $tval, $fval)>;
3526 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETULT)),
3527 (SELECT_I4 (CRANDC $rhs, $lhs), $tval, $fval)>;
3528 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLE)),
3529 (SELECT_I4 (CRORC $lhs, $rhs), $tval, $fval)>;
3530 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETULE)),
3531 (SELECT_I4 (CRORC $rhs, $lhs), $tval, $fval)>;
3532 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETEQ)),
3533 (SELECT_I4 (CREQV $lhs, $rhs), $tval, $fval)>;
3534 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGE)),
3535 (SELECT_I4 (CRORC $rhs, $lhs), $tval, $fval)>;
3536 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETUGE)),
3537 (SELECT_I4 (CRORC $lhs, $rhs), $tval, $fval)>;
3538 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGT)),
3539 (SELECT_I4 (CRANDC $rhs, $lhs), $tval, $fval)>;
3540 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETUGT)),
3541 (SELECT_I4 (CRANDC $lhs, $rhs), $tval, $fval)>;
3542 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETNE)),
3543 (SELECT_I4 (CRXOR $lhs, $rhs), $tval, $fval)>;
3545 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLT)),
3546 (SELECT_I8 (CRANDC $lhs, $rhs), $tval, $fval)>;
3547 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETULT)),
3548 (SELECT_I8 (CRANDC $rhs, $lhs), $tval, $fval)>;
3549 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLE)),
3550 (SELECT_I8 (CRORC $lhs, $rhs), $tval, $fval)>;
3551 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETULE)),
3552 (SELECT_I8 (CRORC $rhs, $lhs), $tval, $fval)>;
3553 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETEQ)),
3554 (SELECT_I8 (CREQV $lhs, $rhs), $tval, $fval)>;
3555 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGE)),
3556 (SELECT_I8 (CRORC $rhs, $lhs), $tval, $fval)>;
3557 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETUGE)),
3558 (SELECT_I8 (CRORC $lhs, $rhs), $tval, $fval)>;
3559 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGT)),
3560 (SELECT_I8 (CRANDC $rhs, $lhs), $tval, $fval)>;
3561 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETUGT)),
3562 (SELECT_I8 (CRANDC $lhs, $rhs), $tval, $fval)>;
3563 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETNE)),
3564 (SELECT_I8 (CRXOR $lhs, $rhs), $tval, $fval)>;
3566 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLT)),
3567 (SELECT_F4 (CRANDC $lhs, $rhs), $tval, $fval)>;
3568 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULT)),
3569 (SELECT_F4 (CRANDC $rhs, $lhs), $tval, $fval)>;
3570 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLE)),
3571 (SELECT_F4 (CRORC $lhs, $rhs), $tval, $fval)>;
3572 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULE)),
3573 (SELECT_F4 (CRORC $rhs, $lhs), $tval, $fval)>;
3574 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETEQ)),
3575 (SELECT_F4 (CREQV $lhs, $rhs), $tval, $fval)>;
3576 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGE)),
3577 (SELECT_F4 (CRORC $rhs, $lhs), $tval, $fval)>;
3578 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGE)),
3579 (SELECT_F4 (CRORC $lhs, $rhs), $tval, $fval)>;
3580 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGT)),
3581 (SELECT_F4 (CRANDC $rhs, $lhs), $tval, $fval)>;
3582 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGT)),
3583 (SELECT_F4 (CRANDC $lhs, $rhs), $tval, $fval)>;
3584 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETNE)),
3585 (SELECT_F4 (CRXOR $lhs, $rhs), $tval, $fval)>;
3587 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLT)),
3588 (SELECT_F8 (CRANDC $lhs, $rhs), $tval, $fval)>;
3589 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULT)),
3590 (SELECT_F8 (CRANDC $rhs, $lhs), $tval, $fval)>;
3591 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLE)),
3592 (SELECT_F8 (CRORC $lhs, $rhs), $tval, $fval)>;
3593 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULE)),
3594 (SELECT_F8 (CRORC $rhs, $lhs), $tval, $fval)>;
3595 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETEQ)),
3596 (SELECT_F8 (CREQV $lhs, $rhs), $tval, $fval)>;
3597 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGE)),
3598 (SELECT_F8 (CRORC $rhs, $lhs), $tval, $fval)>;
3599 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGE)),
3600 (SELECT_F8 (CRORC $lhs, $rhs), $tval, $fval)>;
3601 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGT)),
3602 (SELECT_F8 (CRANDC $rhs, $lhs), $tval, $fval)>;
3603 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGT)),
3604 (SELECT_F8 (CRANDC $lhs, $rhs), $tval, $fval)>;
3605 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETNE)),
3606 (SELECT_F8 (CRXOR $lhs, $rhs), $tval, $fval)>;
3608 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLT)),
3609 (SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>;
3610 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETULT)),
3611 (SELECT_VRRC (CRANDC $rhs, $lhs), $tval, $fval)>;
3612 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLE)),
3613 (SELECT_VRRC (CRORC $lhs, $rhs), $tval, $fval)>;
3614 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETULE)),
3615 (SELECT_VRRC (CRORC $rhs, $lhs), $tval, $fval)>;
3616 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETEQ)),
3617 (SELECT_VRRC (CREQV $lhs, $rhs), $tval, $fval)>;
3618 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGE)),
3619 (SELECT_VRRC (CRORC $rhs, $lhs), $tval, $fval)>;
3620 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETUGE)),
3621 (SELECT_VRRC (CRORC $lhs, $rhs), $tval, $fval)>;
3622 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGT)),
3623 (SELECT_VRRC (CRANDC $rhs, $lhs), $tval, $fval)>;
3624 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETUGT)),
3625 (SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>;
3626 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETNE)),
3627 (SELECT_VRRC (CRXOR $lhs, $rhs), $tval, $fval)>;
3629 let usesCustomInserter = 1 in {
3630 def ANDIo_1_EQ_BIT : Pseudo<(outs crbitrc:$dst), (ins gprc:$in),
3632 [(set i1:$dst, (trunc (not i32:$in)))]>;
3633 def ANDIo_1_GT_BIT : Pseudo<(outs crbitrc:$dst), (ins gprc:$in),
3635 [(set i1:$dst, (trunc i32:$in))]>;
3637 def ANDIo_1_EQ_BIT8 : Pseudo<(outs crbitrc:$dst), (ins g8rc:$in),
3639 [(set i1:$dst, (trunc (not i64:$in)))]>;
3640 def ANDIo_1_GT_BIT8 : Pseudo<(outs crbitrc:$dst), (ins g8rc:$in),
3642 [(set i1:$dst, (trunc i64:$in))]>;
3645 def : Pat<(i1 (not (trunc i32:$in))),
3646 (ANDIo_1_EQ_BIT $in)>;
3647 def : Pat<(i1 (not (trunc i64:$in))),
3648 (ANDIo_1_EQ_BIT8 $in)>;
3650 //===----------------------------------------------------------------------===//
3651 // PowerPC Instructions used for assembler/disassembler only
3654 // FIXME: For B=0 or B > 8, the registers following RT are used.
3655 // WARNING: Do not add patterns for this instruction without fixing this.
3656 def LSWI : XForm_base_r3xo<31, 597, (outs gprc:$RT), (ins gprc:$A, u5imm:$B),
3657 "lswi $RT, $A, $B", IIC_LdStLoad, []>;
3659 // FIXME: For B=0 or B > 8, the registers following RT are used.
3660 // WARNING: Do not add patterns for this instruction without fixing this.
3661 def STSWI : XForm_base_r3xo<31, 725, (outs), (ins gprc:$RT, gprc:$A, u5imm:$B),
3662 "stswi $RT, $A, $B", IIC_LdStLoad, []>;
3664 def ISYNC : XLForm_2_ext<19, 150, 0, 0, 0, (outs), (ins),
3665 "isync", IIC_SprISYNC, []>;
3667 def ICBI : XForm_1a<31, 982, (outs), (ins memrr:$src),
3668 "icbi $src", IIC_LdStICBI, []>;
3670 // We used to have EIEIO as value but E[0-9A-Z] is a reserved name
3671 def EnforceIEIO : XForm_24_eieio<31, 854, (outs), (ins),
3672 "eieio", IIC_LdStLoad, []>;
3674 def WAIT : XForm_24_sync<31, 62, (outs), (ins i32imm:$L),
3675 "wait $L", IIC_LdStLoad, []>;
3677 def MBAR : XForm_mbar<31, 854, (outs), (ins u5imm:$MO),
3678 "mbar $MO", IIC_LdStLoad>, Requires<[IsBookE]>;
3680 def MTSR: XForm_sr<31, 210, (outs), (ins gprc:$RS, u4imm:$SR),
3681 "mtsr $SR, $RS", IIC_SprMTSR>;
3683 def MFSR: XForm_sr<31, 595, (outs gprc:$RS), (ins u4imm:$SR),
3684 "mfsr $RS, $SR", IIC_SprMFSR>;
3686 def MTSRIN: XForm_srin<31, 242, (outs), (ins gprc:$RS, gprc:$RB),
3687 "mtsrin $RS, $RB", IIC_SprMTSR>;
3689 def MFSRIN: XForm_srin<31, 659, (outs gprc:$RS), (ins gprc:$RB),
3690 "mfsrin $RS, $RB", IIC_SprMFSR>;
3692 def MTMSR: XForm_mtmsr<31, 146, (outs), (ins gprc:$RS, i32imm:$L),
3693 "mtmsr $RS, $L", IIC_SprMTMSR>;
3695 def WRTEE: XForm_mtmsr<31, 131, (outs), (ins gprc:$RS),
3696 "wrtee $RS", IIC_SprMTMSR>, Requires<[IsBookE]> {
3700 def WRTEEI: I<31, (outs), (ins i1imm:$E), "wrteei $E", IIC_SprMTMSR>,
3701 Requires<[IsBookE]> {
3705 let Inst{21-30} = 163;
3708 def DCCCI : XForm_tlb<454, (outs), (ins gprc:$A, gprc:$B),
3709 "dccci $A, $B", IIC_LdStLoad>, Requires<[IsPPC4xx]>;
3710 def ICCCI : XForm_tlb<966, (outs), (ins gprc:$A, gprc:$B),
3711 "iccci $A, $B", IIC_LdStLoad>, Requires<[IsPPC4xx]>;
3713 def : InstAlias<"dci 0", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>;
3714 def : InstAlias<"dccci", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>;
3715 def : InstAlias<"ici 0", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>;
3716 def : InstAlias<"iccci", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>;
3718 def MFMSR : XForm_rs<31, 83, (outs gprc:$RT), (ins),
3719 "mfmsr $RT", IIC_SprMFMSR, []>;
3721 def MTMSRD : XForm_mtmsr<31, 178, (outs), (ins gprc:$RS, i32imm:$L),
3722 "mtmsrd $RS, $L", IIC_SprMTMSRD>;
3724 def MCRFS : XLForm_3<63, 64, (outs crrc:$BF), (ins crrc:$BFA),
3725 "mcrfs $BF, $BFA", IIC_BrMCR>;
3727 def MTFSFI : XLForm_4<63, 134, (outs crrc:$BF), (ins i32imm:$U, i32imm:$W),
3728 "mtfsfi $BF, $U, $W", IIC_IntMFFS>;
3730 def MTFSFIo : XLForm_4<63, 134, (outs crrc:$BF), (ins i32imm:$U, i32imm:$W),
3731 "mtfsfi. $BF, $U, $W", IIC_IntMFFS>, isDOT;
3733 def : InstAlias<"mtfsfi $BF, $U", (MTFSFI crrc:$BF, i32imm:$U, 0)>;
3734 def : InstAlias<"mtfsfi. $BF, $U", (MTFSFIo crrc:$BF, i32imm:$U, 0)>;
3736 def MTFSF : XFLForm_1<63, 711, (outs),
3737 (ins i32imm:$FLM, f8rc:$FRB, i32imm:$L, i32imm:$W),
3738 "mtfsf $FLM, $FRB, $L, $W", IIC_IntMFFS, []>;
3739 def MTFSFo : XFLForm_1<63, 711, (outs),
3740 (ins i32imm:$FLM, f8rc:$FRB, i32imm:$L, i32imm:$W),
3741 "mtfsf. $FLM, $FRB, $L, $W", IIC_IntMFFS, []>, isDOT;
3743 def : InstAlias<"mtfsf $FLM, $FRB", (MTFSF i32imm:$FLM, f8rc:$FRB, 0, 0)>;
3744 def : InstAlias<"mtfsf. $FLM, $FRB", (MTFSFo i32imm:$FLM, f8rc:$FRB, 0, 0)>;
3746 def SLBIE : XForm_16b<31, 434, (outs), (ins gprc:$RB),
3747 "slbie $RB", IIC_SprSLBIE, []>;
3749 def SLBMTE : XForm_26<31, 402, (outs), (ins gprc:$RS, gprc:$RB),
3750 "slbmte $RS, $RB", IIC_SprSLBMTE, []>;
3752 def SLBMFEE : XForm_26<31, 915, (outs gprc:$RT), (ins gprc:$RB),
3753 "slbmfee $RT, $RB", IIC_SprSLBMFEE, []>;
3755 def SLBMFEV : XLForm_1_gen<31, 851, (outs gprc:$RT), (ins gprc:$RB),
3756 "slbmfev $RT, $RB", IIC_SprSLBMFEV, []>;
3758 def SLBIA : XForm_0<31, 498, (outs), (ins), "slbia", IIC_SprSLBIA, []>;
3760 def TLBIA : XForm_0<31, 370, (outs), (ins),
3761 "tlbia", IIC_SprTLBIA, []>;
3763 def TLBSYNC : XForm_0<31, 566, (outs), (ins),
3764 "tlbsync", IIC_SprTLBSYNC, []>;
3766 def TLBIEL : XForm_16b<31, 274, (outs), (ins gprc:$RB),
3767 "tlbiel $RB", IIC_SprTLBIEL, []>;
3769 def TLBLD : XForm_16b<31, 978, (outs), (ins gprc:$RB),
3770 "tlbld $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>;
3771 def TLBLI : XForm_16b<31, 1010, (outs), (ins gprc:$RB),
3772 "tlbli $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>;
3774 def TLBIE : XForm_26<31, 306, (outs), (ins gprc:$RS, gprc:$RB),
3775 "tlbie $RB,$RS", IIC_SprTLBIE, []>;
3777 def TLBSX : XForm_tlb<914, (outs), (ins gprc:$A, gprc:$B), "tlbsx $A, $B",
3778 IIC_LdStLoad>, Requires<[IsBookE]>;
3780 def TLBIVAX : XForm_tlb<786, (outs), (ins gprc:$A, gprc:$B), "tlbivax $A, $B",
3781 IIC_LdStLoad>, Requires<[IsBookE]>;
3783 def TLBRE : XForm_24_eieio<31, 946, (outs), (ins),
3784 "tlbre", IIC_LdStLoad, []>, Requires<[IsBookE]>;
3786 def TLBWE : XForm_24_eieio<31, 978, (outs), (ins),
3787 "tlbwe", IIC_LdStLoad, []>, Requires<[IsBookE]>;
3789 def TLBRE2 : XForm_tlbws<31, 946, (outs gprc:$RS), (ins gprc:$A, i1imm:$WS),
3790 "tlbre $RS, $A, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>;
3792 def TLBWE2 : XForm_tlbws<31, 978, (outs), (ins gprc:$RS, gprc:$A, i1imm:$WS),
3793 "tlbwe $RS, $A, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>;
3795 def TLBSX2 : XForm_base_r3xo<31, 914, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3796 "tlbsx $RST, $A, $B", IIC_LdStLoad, []>,
3797 Requires<[IsPPC4xx]>;
3798 def TLBSX2D : XForm_base_r3xo<31, 914, (outs),
3799 (ins gprc:$RST, gprc:$A, gprc:$B),
3800 "tlbsx. $RST, $A, $B", IIC_LdStLoad, []>,
3801 Requires<[IsPPC4xx]>, isDOT;
3803 def RFID : XForm_0<19, 18, (outs), (ins), "rfid", IIC_IntRFID, []>;
3805 def RFI : XForm_0<19, 50, (outs), (ins), "rfi", IIC_SprRFI, []>,
3806 Requires<[IsBookE]>;
3807 def RFCI : XForm_0<19, 51, (outs), (ins), "rfci", IIC_BrB, []>,
3808 Requires<[IsBookE]>;
3810 def RFDI : XForm_0<19, 39, (outs), (ins), "rfdi", IIC_BrB, []>,
3812 def RFMCI : XForm_0<19, 38, (outs), (ins), "rfmci", IIC_BrB, []>,
3815 def MFDCR : XFXForm_1<31, 323, (outs gprc:$RT), (ins i32imm:$SPR),
3816 "mfdcr $RT, $SPR", IIC_SprMFSPR>, Requires<[IsPPC4xx]>;
3817 def MTDCR : XFXForm_1<31, 451, (outs), (ins gprc:$RT, i32imm:$SPR),
3818 "mtdcr $SPR, $RT", IIC_SprMTSPR>, Requires<[IsPPC4xx]>;
3820 def HRFID : XLForm_1_np<19, 274, (outs), (ins), "hrfid", IIC_BrB, []>;
3821 def NAP : XLForm_1_np<19, 434, (outs), (ins), "nap", IIC_BrB, []>;
3823 def ATTN : XForm_attn<0, 256, (outs), (ins), "attn", IIC_BrB>;
3825 def LBZCIX : XForm_base_r3xo<31, 853, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
3826 "lbzcix $RST, $A, $B", IIC_LdStLoad, []>;
3827 def LHZCIX : XForm_base_r3xo<31, 821, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
3828 "lhzcix $RST, $A, $B", IIC_LdStLoad, []>;
3829 def LWZCIX : XForm_base_r3xo<31, 789, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
3830 "lwzcix $RST, $A, $B", IIC_LdStLoad, []>;
3831 def LDCIX : XForm_base_r3xo<31, 885, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
3832 "ldcix $RST, $A, $B", IIC_LdStLoad, []>;
3834 def STBCIX : XForm_base_r3xo<31, 981, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3835 "stbcix $RST, $A, $B", IIC_LdStLoad, []>;
3836 def STHCIX : XForm_base_r3xo<31, 949, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3837 "sthcix $RST, $A, $B", IIC_LdStLoad, []>;
3838 def STWCIX : XForm_base_r3xo<31, 917, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3839 "stwcix $RST, $A, $B", IIC_LdStLoad, []>;
3840 def STDCIX : XForm_base_r3xo<31, 1013, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3841 "stdcix $RST, $A, $B", IIC_LdStLoad, []>;
3843 //===----------------------------------------------------------------------===//
3844 // PowerPC Assembler Instruction Aliases
3847 // Pseudo-instructions for alternate assembly syntax (never used by codegen).
3848 // These are aliases that require C++ handling to convert to the target
3849 // instruction, while InstAliases can be handled directly by tblgen.
3850 class PPCAsmPseudo<string asm, dag iops>
3852 let Namespace = "PPC";
3853 bit PPC64 = 0; // Default value, override with isPPC64
3855 let OutOperandList = (outs);
3856 let InOperandList = iops;
3858 let AsmString = asm;
3859 let isAsmParserOnly = 1;
3863 def : InstAlias<"sc", (SC 0)>;
3865 def : InstAlias<"sync", (SYNC 0)>, Requires<[HasSYNC]>;
3866 def : InstAlias<"msync", (SYNC 0), 0>, Requires<[HasSYNC]>;
3867 def : InstAlias<"lwsync", (SYNC 1)>, Requires<[HasSYNC]>;
3868 def : InstAlias<"ptesync", (SYNC 2)>, Requires<[HasSYNC]>;
3870 def : InstAlias<"wait", (WAIT 0)>;
3871 def : InstAlias<"waitrsv", (WAIT 1)>;
3872 def : InstAlias<"waitimpl", (WAIT 2)>;
3874 def : InstAlias<"mbar", (MBAR 0)>, Requires<[IsBookE]>;
3876 def DCBTx : PPCAsmPseudo<"dcbt $dst", (ins memrr:$dst)>;
3877 def DCBTSTx : PPCAsmPseudo<"dcbtst $dst", (ins memrr:$dst)>;
3879 def DCBTCT : PPCAsmPseudo<"dcbtct $dst, $TH", (ins memrr:$dst, u5imm:$TH)>;
3880 def DCBTDS : PPCAsmPseudo<"dcbtds $dst, $TH", (ins memrr:$dst, u5imm:$TH)>;
3881 def DCBTT : PPCAsmPseudo<"dcbtt $dst", (ins memrr:$dst)>;
3883 def DCBTSTCT : PPCAsmPseudo<"dcbtstct $dst, $TH", (ins memrr:$dst, u5imm:$TH)>;
3884 def DCBTSTDS : PPCAsmPseudo<"dcbtstds $dst, $TH", (ins memrr:$dst, u5imm:$TH)>;
3885 def DCBTSTT : PPCAsmPseudo<"dcbtstt $dst", (ins memrr:$dst)>;
3887 def DCBFx : PPCAsmPseudo<"dcbf $dst", (ins memrr:$dst)>;
3888 def DCBFL : PPCAsmPseudo<"dcbfl $dst", (ins memrr:$dst)>;
3889 def DCBFLP : PPCAsmPseudo<"dcbflp $dst", (ins memrr:$dst)>;
3891 def : InstAlias<"crset $bx", (CREQV crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
3892 def : InstAlias<"crclr $bx", (CRXOR crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
3893 def : InstAlias<"crmove $bx, $by", (CROR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
3894 def : InstAlias<"crnot $bx, $by", (CRNOR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
3896 def : InstAlias<"mtxer $Rx", (MTSPR 1, gprc:$Rx)>;
3897 def : InstAlias<"mfxer $Rx", (MFSPR gprc:$Rx, 1)>;
3899 def : InstAlias<"mfrtcu $Rx", (MFSPR gprc:$Rx, 4)>;
3900 def : InstAlias<"mfrtcl $Rx", (MFSPR gprc:$Rx, 5)>;
3902 def : InstAlias<"mtdscr $Rx", (MTSPR 17, gprc:$Rx)>;
3903 def : InstAlias<"mfdscr $Rx", (MFSPR gprc:$Rx, 17)>;
3905 def : InstAlias<"mtdsisr $Rx", (MTSPR 18, gprc:$Rx)>;
3906 def : InstAlias<"mfdsisr $Rx", (MFSPR gprc:$Rx, 18)>;
3908 def : InstAlias<"mtdar $Rx", (MTSPR 19, gprc:$Rx)>;
3909 def : InstAlias<"mfdar $Rx", (MFSPR gprc:$Rx, 19)>;
3911 def : InstAlias<"mtdec $Rx", (MTSPR 22, gprc:$Rx)>;
3912 def : InstAlias<"mfdec $Rx", (MFSPR gprc:$Rx, 22)>;
3914 def : InstAlias<"mtsdr1 $Rx", (MTSPR 25, gprc:$Rx)>;
3915 def : InstAlias<"mfsdr1 $Rx", (MFSPR gprc:$Rx, 25)>;
3917 def : InstAlias<"mtsrr0 $Rx", (MTSPR 26, gprc:$Rx)>;
3918 def : InstAlias<"mfsrr0 $Rx", (MFSPR gprc:$Rx, 26)>;
3920 def : InstAlias<"mtsrr1 $Rx", (MTSPR 27, gprc:$Rx)>;
3921 def : InstAlias<"mfsrr1 $Rx", (MFSPR gprc:$Rx, 27)>;
3923 def : InstAlias<"mtsrr2 $Rx", (MTSPR 990, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3924 def : InstAlias<"mfsrr2 $Rx", (MFSPR gprc:$Rx, 990)>, Requires<[IsPPC4xx]>;
3926 def : InstAlias<"mtsrr3 $Rx", (MTSPR 991, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3927 def : InstAlias<"mfsrr3 $Rx", (MFSPR gprc:$Rx, 991)>, Requires<[IsPPC4xx]>;
3929 def : InstAlias<"mtcfar $Rx", (MTSPR 28, gprc:$Rx)>;
3930 def : InstAlias<"mfcfar $Rx", (MFSPR gprc:$Rx, 28)>;
3932 def : InstAlias<"mtamr $Rx", (MTSPR 29, gprc:$Rx)>;
3933 def : InstAlias<"mfamr $Rx", (MFSPR gprc:$Rx, 29)>;
3935 def : InstAlias<"mtpid $Rx", (MTSPR 48, gprc:$Rx)>, Requires<[IsBookE]>;
3936 def : InstAlias<"mfpid $Rx", (MFSPR gprc:$Rx, 48)>, Requires<[IsBookE]>;
3938 def : InstAlias<"mftb $Rx", (MFTB gprc:$Rx, 268)>;
3939 def : InstAlias<"mftbl $Rx", (MFTB gprc:$Rx, 268)>;
3940 def : InstAlias<"mftbu $Rx", (MFTB gprc:$Rx, 269)>;
3942 def : InstAlias<"mttbl $Rx", (MTSPR 284, gprc:$Rx)>;
3943 def : InstAlias<"mttbu $Rx", (MTSPR 285, gprc:$Rx)>;
3945 def : InstAlias<"mftblo $Rx", (MFSPR gprc:$Rx, 989)>, Requires<[IsPPC4xx]>;
3946 def : InstAlias<"mttblo $Rx", (MTSPR 989, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3947 def : InstAlias<"mftbhi $Rx", (MFSPR gprc:$Rx, 988)>, Requires<[IsPPC4xx]>;
3948 def : InstAlias<"mttbhi $Rx", (MTSPR 988, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3950 def : InstAlias<"xnop", (XORI R0, R0, 0)>;
3952 def : InstAlias<"mr $rA, $rB", (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3953 def : InstAlias<"mr. $rA, $rB", (OR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3955 def : InstAlias<"not $rA, $rB", (NOR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3956 def : InstAlias<"not. $rA, $rB", (NOR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3958 def : InstAlias<"mtcr $rA", (MTCRF8 255, g8rc:$rA)>;
3960 foreach BATR = 0-3 in {
3961 def : InstAlias<"mtdbatu "#BATR#", $Rx",
3962 (MTSPR !add(BATR, !add(BATR, 536)), gprc:$Rx)>,
3963 Requires<[IsPPC6xx]>;
3964 def : InstAlias<"mfdbatu $Rx, "#BATR,
3965 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 536)))>,
3966 Requires<[IsPPC6xx]>;
3967 def : InstAlias<"mtdbatl "#BATR#", $Rx",
3968 (MTSPR !add(BATR, !add(BATR, 537)), gprc:$Rx)>,
3969 Requires<[IsPPC6xx]>;
3970 def : InstAlias<"mfdbatl $Rx, "#BATR,
3971 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 537)))>,
3972 Requires<[IsPPC6xx]>;
3973 def : InstAlias<"mtibatu "#BATR#", $Rx",
3974 (MTSPR !add(BATR, !add(BATR, 528)), gprc:$Rx)>,
3975 Requires<[IsPPC6xx]>;
3976 def : InstAlias<"mfibatu $Rx, "#BATR,
3977 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 528)))>,
3978 Requires<[IsPPC6xx]>;
3979 def : InstAlias<"mtibatl "#BATR#", $Rx",
3980 (MTSPR !add(BATR, !add(BATR, 529)), gprc:$Rx)>,
3981 Requires<[IsPPC6xx]>;
3982 def : InstAlias<"mfibatl $Rx, "#BATR,
3983 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 529)))>,
3984 Requires<[IsPPC6xx]>;
3987 foreach BR = 0-7 in {
3988 def : InstAlias<"mfbr"#BR#" $Rx",
3989 (MFDCR gprc:$Rx, !add(BR, 0x80))>,
3990 Requires<[IsPPC4xx]>;
3991 def : InstAlias<"mtbr"#BR#" $Rx",
3992 (MTDCR gprc:$Rx, !add(BR, 0x80))>,
3993 Requires<[IsPPC4xx]>;
3996 def : InstAlias<"mtdccr $Rx", (MTSPR 1018, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3997 def : InstAlias<"mfdccr $Rx", (MFSPR gprc:$Rx, 1018)>, Requires<[IsPPC4xx]>;
3999 def : InstAlias<"mticcr $Rx", (MTSPR 1019, gprc:$Rx)>, Requires<[IsPPC4xx]>;
4000 def : InstAlias<"mficcr $Rx", (MFSPR gprc:$Rx, 1019)>, Requires<[IsPPC4xx]>;
4002 def : InstAlias<"mtdear $Rx", (MTSPR 981, gprc:$Rx)>, Requires<[IsPPC4xx]>;
4003 def : InstAlias<"mfdear $Rx", (MFSPR gprc:$Rx, 981)>, Requires<[IsPPC4xx]>;
4005 def : InstAlias<"mtesr $Rx", (MTSPR 980, gprc:$Rx)>, Requires<[IsPPC4xx]>;
4006 def : InstAlias<"mfesr $Rx", (MFSPR gprc:$Rx, 980)>, Requires<[IsPPC4xx]>;
4008 def : InstAlias<"mfspefscr $Rx", (MFSPR gprc:$Rx, 512)>;
4009 def : InstAlias<"mtspefscr $Rx", (MTSPR 512, gprc:$Rx)>;
4011 def : InstAlias<"mttcr $Rx", (MTSPR 986, gprc:$Rx)>, Requires<[IsPPC4xx]>;
4012 def : InstAlias<"mftcr $Rx", (MFSPR gprc:$Rx, 986)>, Requires<[IsPPC4xx]>;
4014 def LAx : PPCAsmPseudo<"la $rA, $addr", (ins gprc:$rA, memri:$addr)>;
4016 def SUBI : PPCAsmPseudo<"subi $rA, $rB, $imm",
4017 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
4018 def SUBIS : PPCAsmPseudo<"subis $rA, $rB, $imm",
4019 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
4020 def SUBIC : PPCAsmPseudo<"subic $rA, $rB, $imm",
4021 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
4022 def SUBICo : PPCAsmPseudo<"subic. $rA, $rB, $imm",
4023 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
4025 def : InstAlias<"sub $rA, $rB, $rC", (SUBF8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
4026 def : InstAlias<"sub. $rA, $rB, $rC", (SUBF8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
4027 def : InstAlias<"subc $rA, $rB, $rC", (SUBFC8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
4028 def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
4030 def : InstAlias<"mtmsrd $RS", (MTMSRD gprc:$RS, 0)>;
4031 def : InstAlias<"mtmsr $RS", (MTMSR gprc:$RS, 0)>;
4033 def : InstAlias<"mfasr $RT", (MFSPR gprc:$RT, 280)>;
4034 def : InstAlias<"mtasr $RT", (MTSPR 280, gprc:$RT)>;
4036 foreach SPRG = 0-3 in {
4037 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 272))>;
4038 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 272))>;
4039 def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>;
4040 def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>;
4042 foreach SPRG = 4-7 in {
4043 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 256))>,
4044 Requires<[IsBookE]>;
4045 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 256))>,
4046 Requires<[IsBookE]>;
4047 def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>,
4048 Requires<[IsBookE]>;
4049 def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>,
4050 Requires<[IsBookE]>;
4053 def : InstAlias<"mtasr $RS", (MTSPR 280, gprc:$RS)>;
4055 def : InstAlias<"mfdec $RT", (MFSPR gprc:$RT, 22)>;
4056 def : InstAlias<"mtdec $RT", (MTSPR 22, gprc:$RT)>;
4058 def : InstAlias<"mfpvr $RT", (MFSPR gprc:$RT, 287)>;
4060 def : InstAlias<"mfsdr1 $RT", (MFSPR gprc:$RT, 25)>;
4061 def : InstAlias<"mtsdr1 $RT", (MTSPR 25, gprc:$RT)>;
4063 def : InstAlias<"mfsrr0 $RT", (MFSPR gprc:$RT, 26)>;
4064 def : InstAlias<"mfsrr1 $RT", (MFSPR gprc:$RT, 27)>;
4065 def : InstAlias<"mtsrr0 $RT", (MTSPR 26, gprc:$RT)>;
4066 def : InstAlias<"mtsrr1 $RT", (MTSPR 27, gprc:$RT)>;
4068 def : InstAlias<"tlbie $RB", (TLBIE R0, gprc:$RB)>;
4070 def : InstAlias<"tlbrehi $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 0)>,
4071 Requires<[IsPPC4xx]>;
4072 def : InstAlias<"tlbrelo $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 1)>,
4073 Requires<[IsPPC4xx]>;
4074 def : InstAlias<"tlbwehi $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 0)>,
4075 Requires<[IsPPC4xx]>;
4076 def : InstAlias<"tlbwelo $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 1)>,
4077 Requires<[IsPPC4xx]>;
4079 def EXTLWI : PPCAsmPseudo<"extlwi $rA, $rS, $n, $b",
4080 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
4081 def EXTLWIo : PPCAsmPseudo<"extlwi. $rA, $rS, $n, $b",
4082 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
4083 def EXTRWI : PPCAsmPseudo<"extrwi $rA, $rS, $n, $b",
4084 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
4085 def EXTRWIo : PPCAsmPseudo<"extrwi. $rA, $rS, $n, $b",
4086 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
4087 def INSLWI : PPCAsmPseudo<"inslwi $rA, $rS, $n, $b",
4088 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
4089 def INSLWIo : PPCAsmPseudo<"inslwi. $rA, $rS, $n, $b",
4090 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
4091 def INSRWI : PPCAsmPseudo<"insrwi $rA, $rS, $n, $b",
4092 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
4093 def INSRWIo : PPCAsmPseudo<"insrwi. $rA, $rS, $n, $b",
4094 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
4095 def ROTRWI : PPCAsmPseudo<"rotrwi $rA, $rS, $n",
4096 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
4097 def ROTRWIo : PPCAsmPseudo<"rotrwi. $rA, $rS, $n",
4098 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
4099 def SLWI : PPCAsmPseudo<"slwi $rA, $rS, $n",
4100 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
4101 def SLWIo : PPCAsmPseudo<"slwi. $rA, $rS, $n",
4102 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
4103 def SRWI : PPCAsmPseudo<"srwi $rA, $rS, $n",
4104 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
4105 def SRWIo : PPCAsmPseudo<"srwi. $rA, $rS, $n",
4106 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
4107 def CLRRWI : PPCAsmPseudo<"clrrwi $rA, $rS, $n",
4108 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
4109 def CLRRWIo : PPCAsmPseudo<"clrrwi. $rA, $rS, $n",
4110 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
4111 def CLRLSLWI : PPCAsmPseudo<"clrlslwi $rA, $rS, $b, $n",
4112 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
4113 def CLRLSLWIo : PPCAsmPseudo<"clrlslwi. $rA, $rS, $b, $n",
4114 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
4116 def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
4117 def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
4118 def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
4119 def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNMo gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
4120 def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
4121 def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
4123 def : InstAlias<"cntlzw $rA, $rS", (CNTLZW gprc:$rA, gprc:$rS)>;
4124 def : InstAlias<"cntlzw. $rA, $rS", (CNTLZWo gprc:$rA, gprc:$rS)>;
4125 // The POWER variant
4126 def : MnemonicAlias<"cntlz", "cntlzw">;
4127 def : MnemonicAlias<"cntlz.", "cntlzw.">;
4129 def EXTLDI : PPCAsmPseudo<"extldi $rA, $rS, $n, $b",
4130 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
4131 def EXTLDIo : PPCAsmPseudo<"extldi. $rA, $rS, $n, $b",
4132 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
4133 def EXTRDI : PPCAsmPseudo<"extrdi $rA, $rS, $n, $b",
4134 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
4135 def EXTRDIo : PPCAsmPseudo<"extrdi. $rA, $rS, $n, $b",
4136 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
4137 def INSRDI : PPCAsmPseudo<"insrdi $rA, $rS, $n, $b",
4138 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
4139 def INSRDIo : PPCAsmPseudo<"insrdi. $rA, $rS, $n, $b",
4140 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
4141 def ROTRDI : PPCAsmPseudo<"rotrdi $rA, $rS, $n",
4142 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
4143 def ROTRDIo : PPCAsmPseudo<"rotrdi. $rA, $rS, $n",
4144 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
4145 def SLDI : PPCAsmPseudo<"sldi $rA, $rS, $n",
4146 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
4147 def SLDIo : PPCAsmPseudo<"sldi. $rA, $rS, $n",
4148 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
4149 def SRDI : PPCAsmPseudo<"srdi $rA, $rS, $n",
4150 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
4151 def SRDIo : PPCAsmPseudo<"srdi. $rA, $rS, $n",
4152 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
4153 def CLRRDI : PPCAsmPseudo<"clrrdi $rA, $rS, $n",
4154 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
4155 def CLRRDIo : PPCAsmPseudo<"clrrdi. $rA, $rS, $n",
4156 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
4157 def CLRLSLDI : PPCAsmPseudo<"clrlsldi $rA, $rS, $b, $n",
4158 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
4159 def CLRLSLDIo : PPCAsmPseudo<"clrlsldi. $rA, $rS, $b, $n",
4160 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
4162 def : InstAlias<"rotldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
4163 def : InstAlias<"rotldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
4164 def : InstAlias<"rotld $rA, $rS, $rB", (RLDCL g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
4165 def : InstAlias<"rotld. $rA, $rS, $rB", (RLDCLo g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
4166 def : InstAlias<"clrldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
4167 def : InstAlias<"clrldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
4169 def RLWINMbm : PPCAsmPseudo<"rlwinm $rA, $rS, $n, $b",
4170 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
4171 def RLWINMobm : PPCAsmPseudo<"rlwinm. $rA, $rS, $n, $b",
4172 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
4173 def RLWIMIbm : PPCAsmPseudo<"rlwimi $rA, $rS, $n, $b",
4174 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
4175 def RLWIMIobm : PPCAsmPseudo<"rlwimi. $rA, $rS, $n, $b",
4176 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
4177 def RLWNMbm : PPCAsmPseudo<"rlwnm $rA, $rS, $n, $b",
4178 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
4179 def RLWNMobm : PPCAsmPseudo<"rlwnm. $rA, $rS, $n, $b",
4180 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
4182 // These generic branch instruction forms are used for the assembler parser only.
4183 // Defs and Uses are conservative, since we don't know the BO value.
4184 let PPC970_Unit = 7 in {
4185 let Defs = [CTR], Uses = [CTR, RM] in {
4186 def gBC : BForm_3<16, 0, 0, (outs),
4187 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst),
4188 "bc $bo, $bi, $dst">;
4189 def gBCA : BForm_3<16, 1, 0, (outs),
4190 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst),
4191 "bca $bo, $bi, $dst">;
4192 let isAsmParserOnly = 1 in {
4193 def gBCat : BForm_3_at<16, 0, 0, (outs),
4194 (ins u5imm:$bo, atimm:$at, crbitrc:$bi,
4196 "bc$at $bo, $bi, $dst">;
4197 def gBCAat : BForm_3_at<16, 1, 0, (outs),
4198 (ins u5imm:$bo, atimm:$at, crbitrc:$bi,
4199 abscondbrtarget:$dst),
4200 "bca$at $bo, $bi, $dst">;
4201 } // isAsmParserOnly = 1
4203 let Defs = [LR, CTR], Uses = [CTR, RM] in {
4204 def gBCL : BForm_3<16, 0, 1, (outs),
4205 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst),
4206 "bcl $bo, $bi, $dst">;
4207 def gBCLA : BForm_3<16, 1, 1, (outs),
4208 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst),
4209 "bcla $bo, $bi, $dst">;
4210 let isAsmParserOnly = 1 in {
4211 def gBCLat : BForm_3_at<16, 0, 1, (outs),
4212 (ins u5imm:$bo, atimm:$at, crbitrc:$bi,
4214 "bcl$at $bo, $bi, $dst">;
4215 def gBCLAat : BForm_3_at<16, 1, 1, (outs),
4216 (ins u5imm:$bo, atimm:$at, crbitrc:$bi,
4217 abscondbrtarget:$dst),
4218 "bcla$at $bo, $bi, $dst">;
4219 } // // isAsmParserOnly = 1
4221 let Defs = [CTR], Uses = [CTR, LR, RM] in
4222 def gBCLR : XLForm_2<19, 16, 0, (outs),
4223 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
4224 "bclr $bo, $bi, $bh", IIC_BrB, []>;
4225 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in
4226 def gBCLRL : XLForm_2<19, 16, 1, (outs),
4227 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
4228 "bclrl $bo, $bi, $bh", IIC_BrB, []>;
4229 let Defs = [CTR], Uses = [CTR, LR, RM] in
4230 def gBCCTR : XLForm_2<19, 528, 0, (outs),
4231 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
4232 "bcctr $bo, $bi, $bh", IIC_BrB, []>;
4233 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in
4234 def gBCCTRL : XLForm_2<19, 528, 1, (outs),
4235 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
4236 "bcctrl $bo, $bi, $bh", IIC_BrB, []>;
4239 multiclass BranchSimpleMnemonicAT<string pm, int at> {
4240 def : InstAlias<"bc"#pm#" $bo, $bi, $dst", (gBCat u5imm:$bo, at, crbitrc:$bi,
4241 condbrtarget:$dst)>;
4242 def : InstAlias<"bca"#pm#" $bo, $bi, $dst", (gBCAat u5imm:$bo, at, crbitrc:$bi,
4243 condbrtarget:$dst)>;
4244 def : InstAlias<"bcl"#pm#" $bo, $bi, $dst", (gBCLat u5imm:$bo, at, crbitrc:$bi,
4245 condbrtarget:$dst)>;
4246 def : InstAlias<"bcla"#pm#" $bo, $bi, $dst", (gBCLAat u5imm:$bo, at, crbitrc:$bi,
4247 condbrtarget:$dst)>;
4249 defm : BranchSimpleMnemonicAT<"+", 3>;
4250 defm : BranchSimpleMnemonicAT<"-", 2>;
4252 def : InstAlias<"bclr $bo, $bi", (gBCLR u5imm:$bo, crbitrc:$bi, 0)>;
4253 def : InstAlias<"bclrl $bo, $bi", (gBCLRL u5imm:$bo, crbitrc:$bi, 0)>;
4254 def : InstAlias<"bcctr $bo, $bi", (gBCCTR u5imm:$bo, crbitrc:$bi, 0)>;
4255 def : InstAlias<"bcctrl $bo, $bi", (gBCCTRL u5imm:$bo, crbitrc:$bi, 0)>;
4257 multiclass BranchSimpleMnemonic1<string name, string pm, int bo> {
4258 def : InstAlias<"b"#name#pm#" $bi, $dst", (gBC bo, crbitrc:$bi, condbrtarget:$dst)>;
4259 def : InstAlias<"b"#name#"a"#pm#" $bi, $dst", (gBCA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
4260 def : InstAlias<"b"#name#"lr"#pm#" $bi", (gBCLR bo, crbitrc:$bi, 0)>;
4261 def : InstAlias<"b"#name#"l"#pm#" $bi, $dst", (gBCL bo, crbitrc:$bi, condbrtarget:$dst)>;
4262 def : InstAlias<"b"#name#"la"#pm#" $bi, $dst", (gBCLA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
4263 def : InstAlias<"b"#name#"lrl"#pm#" $bi", (gBCLRL bo, crbitrc:$bi, 0)>;
4265 multiclass BranchSimpleMnemonic2<string name, string pm, int bo>
4266 : BranchSimpleMnemonic1<name, pm, bo> {
4267 def : InstAlias<"b"#name#"ctr"#pm#" $bi", (gBCCTR bo, crbitrc:$bi, 0)>;
4268 def : InstAlias<"b"#name#"ctrl"#pm#" $bi", (gBCCTRL bo, crbitrc:$bi, 0)>;
4270 defm : BranchSimpleMnemonic2<"t", "", 12>;
4271 defm : BranchSimpleMnemonic2<"f", "", 4>;
4272 defm : BranchSimpleMnemonic2<"t", "-", 14>;
4273 defm : BranchSimpleMnemonic2<"f", "-", 6>;
4274 defm : BranchSimpleMnemonic2<"t", "+", 15>;
4275 defm : BranchSimpleMnemonic2<"f", "+", 7>;
4276 defm : BranchSimpleMnemonic1<"dnzt", "", 8>;
4277 defm : BranchSimpleMnemonic1<"dnzf", "", 0>;
4278 defm : BranchSimpleMnemonic1<"dzt", "", 10>;
4279 defm : BranchSimpleMnemonic1<"dzf", "", 2>;
4281 multiclass BranchExtendedMnemonicPM<string name, string pm, int bibo> {
4282 def : InstAlias<"b"#name#pm#" $cc, $dst",
4283 (BCC bibo, crrc:$cc, condbrtarget:$dst)>;
4284 def : InstAlias<"b"#name#pm#" $dst",
4285 (BCC bibo, CR0, condbrtarget:$dst)>;
4287 def : InstAlias<"b"#name#"a"#pm#" $cc, $dst",
4288 (BCCA bibo, crrc:$cc, abscondbrtarget:$dst)>;
4289 def : InstAlias<"b"#name#"a"#pm#" $dst",
4290 (BCCA bibo, CR0, abscondbrtarget:$dst)>;
4292 def : InstAlias<"b"#name#"lr"#pm#" $cc",
4293 (BCCLR bibo, crrc:$cc)>;
4294 def : InstAlias<"b"#name#"lr"#pm,
4297 def : InstAlias<"b"#name#"ctr"#pm#" $cc",
4298 (BCCCTR bibo, crrc:$cc)>;
4299 def : InstAlias<"b"#name#"ctr"#pm,
4300 (BCCCTR bibo, CR0)>;
4302 def : InstAlias<"b"#name#"l"#pm#" $cc, $dst",
4303 (BCCL bibo, crrc:$cc, condbrtarget:$dst)>;
4304 def : InstAlias<"b"#name#"l"#pm#" $dst",
4305 (BCCL bibo, CR0, condbrtarget:$dst)>;
4307 def : InstAlias<"b"#name#"la"#pm#" $cc, $dst",
4308 (BCCLA bibo, crrc:$cc, abscondbrtarget:$dst)>;
4309 def : InstAlias<"b"#name#"la"#pm#" $dst",
4310 (BCCLA bibo, CR0, abscondbrtarget:$dst)>;
4312 def : InstAlias<"b"#name#"lrl"#pm#" $cc",
4313 (BCCLRL bibo, crrc:$cc)>;
4314 def : InstAlias<"b"#name#"lrl"#pm,
4315 (BCCLRL bibo, CR0)>;
4317 def : InstAlias<"b"#name#"ctrl"#pm#" $cc",
4318 (BCCCTRL bibo, crrc:$cc)>;
4319 def : InstAlias<"b"#name#"ctrl"#pm,
4320 (BCCCTRL bibo, CR0)>;
4322 multiclass BranchExtendedMnemonic<string name, int bibo> {
4323 defm : BranchExtendedMnemonicPM<name, "", bibo>;
4324 defm : BranchExtendedMnemonicPM<name, "-", !add(bibo, 2)>;
4325 defm : BranchExtendedMnemonicPM<name, "+", !add(bibo, 3)>;
4327 defm : BranchExtendedMnemonic<"lt", 12>;
4328 defm : BranchExtendedMnemonic<"gt", 44>;
4329 defm : BranchExtendedMnemonic<"eq", 76>;
4330 defm : BranchExtendedMnemonic<"un", 108>;
4331 defm : BranchExtendedMnemonic<"so", 108>;
4332 defm : BranchExtendedMnemonic<"ge", 4>;
4333 defm : BranchExtendedMnemonic<"nl", 4>;
4334 defm : BranchExtendedMnemonic<"le", 36>;
4335 defm : BranchExtendedMnemonic<"ng", 36>;
4336 defm : BranchExtendedMnemonic<"ne", 68>;
4337 defm : BranchExtendedMnemonic<"nu", 100>;
4338 defm : BranchExtendedMnemonic<"ns", 100>;
4340 def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>;
4341 def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>;
4342 def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>;
4343 def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>;
4344 def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm64:$imm)>;
4345 def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>;
4346 def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm64:$imm)>;
4347 def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>;
4349 def : InstAlias<"cmpi $bf, 0, $rA, $imm", (CMPWI crrc:$bf, gprc:$rA, s16imm:$imm)>;
4350 def : InstAlias<"cmp $bf, 0, $rA, $rB", (CMPW crrc:$bf, gprc:$rA, gprc:$rB)>;
4351 def : InstAlias<"cmpli $bf, 0, $rA, $imm", (CMPLWI crrc:$bf, gprc:$rA, u16imm:$imm)>;
4352 def : InstAlias<"cmpl $bf, 0, $rA, $rB", (CMPLW crrc:$bf, gprc:$rA, gprc:$rB)>;
4353 def : InstAlias<"cmpi $bf, 1, $rA, $imm", (CMPDI crrc:$bf, g8rc:$rA, s16imm64:$imm)>;
4354 def : InstAlias<"cmp $bf, 1, $rA, $rB", (CMPD crrc:$bf, g8rc:$rA, g8rc:$rB)>;
4355 def : InstAlias<"cmpli $bf, 1, $rA, $imm", (CMPLDI crrc:$bf, g8rc:$rA, u16imm64:$imm)>;
4356 def : InstAlias<"cmpl $bf, 1, $rA, $rB", (CMPLD crrc:$bf, g8rc:$rA, g8rc:$rB)>;
4358 multiclass TrapExtendedMnemonic<string name, int to> {
4359 def : InstAlias<"td"#name#"i $rA, $imm", (TDI to, g8rc:$rA, s16imm:$imm)>;
4360 def : InstAlias<"td"#name#" $rA, $rB", (TD to, g8rc:$rA, g8rc:$rB)>;
4361 def : InstAlias<"tw"#name#"i $rA, $imm", (TWI to, gprc:$rA, s16imm:$imm)>;
4362 def : InstAlias<"tw"#name#" $rA, $rB", (TW to, gprc:$rA, gprc:$rB)>;
4364 defm : TrapExtendedMnemonic<"lt", 16>;
4365 defm : TrapExtendedMnemonic<"le", 20>;
4366 defm : TrapExtendedMnemonic<"eq", 4>;
4367 defm : TrapExtendedMnemonic<"ge", 12>;
4368 defm : TrapExtendedMnemonic<"gt", 8>;
4369 defm : TrapExtendedMnemonic<"nl", 12>;
4370 defm : TrapExtendedMnemonic<"ne", 24>;
4371 defm : TrapExtendedMnemonic<"ng", 20>;
4372 defm : TrapExtendedMnemonic<"llt", 2>;
4373 defm : TrapExtendedMnemonic<"lle", 6>;
4374 defm : TrapExtendedMnemonic<"lge", 5>;
4375 defm : TrapExtendedMnemonic<"lgt", 1>;
4376 defm : TrapExtendedMnemonic<"lnl", 5>;
4377 defm : TrapExtendedMnemonic<"lng", 6>;
4378 defm : TrapExtendedMnemonic<"u", 31>;
4381 def : Pat<(atomic_load_8 iaddr:$src), (LBZ memri:$src)>;
4382 def : Pat<(atomic_load_16 iaddr:$src), (LHZ memri:$src)>;
4383 def : Pat<(atomic_load_32 iaddr:$src), (LWZ memri:$src)>;
4384 def : Pat<(atomic_load_8 xaddr:$src), (LBZX memrr:$src)>;
4385 def : Pat<(atomic_load_16 xaddr:$src), (LHZX memrr:$src)>;
4386 def : Pat<(atomic_load_32 xaddr:$src), (LWZX memrr:$src)>;
4389 def : Pat<(atomic_store_8 iaddr:$ptr, i32:$val), (STB gprc:$val, memri:$ptr)>;
4390 def : Pat<(atomic_store_16 iaddr:$ptr, i32:$val), (STH gprc:$val, memri:$ptr)>;
4391 def : Pat<(atomic_store_32 iaddr:$ptr, i32:$val), (STW gprc:$val, memri:$ptr)>;
4392 def : Pat<(atomic_store_8 xaddr:$ptr, i32:$val), (STBX gprc:$val, memrr:$ptr)>;
4393 def : Pat<(atomic_store_16 xaddr:$ptr, i32:$val), (STHX gprc:$val, memrr:$ptr)>;
4394 def : Pat<(atomic_store_32 xaddr:$ptr, i32:$val), (STWX gprc:$val, memrr:$ptr)>;
4396 let Predicates = [IsISA3_0] in {
4398 // Copy-Paste Facility
4399 // We prefix 'CP' to COPY due to name conflict in Target.td. We also prefix to
4400 // PASTE for naming consistency.
4402 def CP_COPY : X_L1_RA5_RB5<31, 774, "copy" , gprc, IIC_LdStCOPY, []>;
4405 def CP_PASTE : X_L1_RA5_RB5<31, 902, "paste" , gprc, IIC_LdStPASTE, []>;
4407 let mayStore = 1, Defs = [CR0] in
4408 def CP_PASTEo : X_L1_RA5_RB5<31, 902, "paste.", gprc, IIC_LdStPASTE, []>, isDOT;
4410 def CP_COPYx : PPCAsmPseudo<"copy $rA, $rB" , (ins gprc:$rA, gprc:$rB)>;
4411 def CP_PASTEx : PPCAsmPseudo<"paste $rA, $rB", (ins gprc:$rA, gprc:$rB)>;
4412 def CP_COPY_FIRST : PPCAsmPseudo<"copy_first $rA, $rB",
4413 (ins gprc:$rA, gprc:$rB)>;
4414 def CP_PASTE_LAST : PPCAsmPseudo<"paste_last $rA, $rB",
4415 (ins gprc:$rA, gprc:$rB)>;
4416 def CP_ABORT : XForm_0<31, 838, (outs), (ins), "cp_abort", IIC_SprABORT, []>;
4418 // Message Synchronize
4419 def MSGSYNC : XForm_0<31, 886, (outs), (ins), "msgsync", IIC_SprMSGSYNC, []>;
4421 // Power-Saving Mode Instruction:
4422 def STOP : XForm_0<19, 370, (outs), (ins), "stop", IIC_SprSTOP, []>;