1 //===-------------- PPCMIPeephole.cpp - MI Peephole Cleanups -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===---------------------------------------------------------------------===//
10 // This pass performs peephole optimizations to clean up ugly code
11 // sequences at the MachineInstruction layer. It runs at the end of
12 // the SSA phases, following VSX swap removal. A pass of dead code
13 // elimination follows this one for quick clean-up of any dead
14 // instructions introduced here. Although we could do this as callbacks
15 // from the generic peephole pass, this would have a couple of bad
16 // effects: it might remove optimization opportunities for VSX swap
17 // removal, and it would miss cleanups made possible following VSX
20 //===---------------------------------------------------------------------===//
23 #include "PPCInstrBuilder.h"
24 #include "PPCInstrInfo.h"
25 #include "PPCTargetMachine.h"
26 #include "llvm/CodeGen/MachineFunctionPass.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/Support/Debug.h"
33 #define DEBUG_TYPE "ppc-mi-peepholes"
36 void initializePPCMIPeepholePass(PassRegistry&);
41 struct PPCMIPeephole : public MachineFunctionPass {
44 const PPCInstrInfo *TII;
46 MachineRegisterInfo *MRI;
48 PPCMIPeephole() : MachineFunctionPass(ID) {
49 initializePPCMIPeepholePass(*PassRegistry::getPassRegistry());
53 // Initialize class variables.
54 void initialize(MachineFunction &MFParm);
57 bool simplifyCode(void);
59 // Find the "true" register represented by SrcReg (following chains
60 // of copies and subreg_to_reg operations).
61 unsigned lookThruCopyLike(unsigned SrcReg);
64 // Main entry point for this pass.
65 bool runOnMachineFunction(MachineFunction &MF) override {
66 if (skipFunction(*MF.getFunction()))
69 return simplifyCode();
73 // Initialize class variables.
74 void PPCMIPeephole::initialize(MachineFunction &MFParm) {
76 MRI = &MF->getRegInfo();
77 TII = MF->getSubtarget<PPCSubtarget>().getInstrInfo();
78 DEBUG(dbgs() << "*** PowerPC MI peephole pass ***\n\n");
82 // Perform peephole optimizations.
83 bool PPCMIPeephole::simplifyCode(void) {
84 bool Simplified = false;
85 MachineInstr* ToErase = nullptr;
87 for (MachineBasicBlock &MBB : *MF) {
88 for (MachineInstr &MI : MBB) {
90 // If the previous instruction was marked for elimination,
93 ToErase->eraseFromParent();
97 // Ignore debug instructions.
98 if (MI.isDebugValue())
101 // Per-opcode peepholes.
102 switch (MI.getOpcode()) {
107 case PPC::XXPERMDI: {
108 // Perform simplifications of 2x64 vector swaps and splats.
109 // A swap is identified by an immediate value of 2, and a splat
110 // is identified by an immediate value of 0 or 3.
111 int Immed = MI.getOperand(3).getImm();
115 // For each of these simplifications, we need the two source
116 // regs to match. Unfortunately, MachineCSE ignores COPY and
117 // SUBREG_TO_REG, so for example we can see
118 // XXPERMDI t, SUBREG_TO_REG(s), SUBREG_TO_REG(s), immed.
119 // We have to look through chains of COPY and SUBREG_TO_REG
120 // to find the real source values for comparison.
121 unsigned TrueReg1 = lookThruCopyLike(MI.getOperand(1).getReg());
122 unsigned TrueReg2 = lookThruCopyLike(MI.getOperand(2).getReg());
124 if (TrueReg1 == TrueReg2
125 && TargetRegisterInfo::isVirtualRegister(TrueReg1)) {
126 MachineInstr *DefMI = MRI->getVRegDef(TrueReg1);
127 unsigned DefOpc = DefMI ? DefMI->getOpcode() : 0;
129 // If this is a splat fed by a splatting load, the splat is
130 // redundant. Replace with a copy. This doesn't happen directly due
131 // to code in PPCDAGToDAGISel.cpp, but it can happen when converting
132 // a load of a double to a vector of 64-bit integers.
133 auto isConversionOfLoadAndSplat = [=]() -> bool {
134 if (DefOpc != PPC::XVCVDPSXDS && DefOpc != PPC::XVCVDPUXDS)
136 unsigned DefReg = lookThruCopyLike(DefMI->getOperand(1).getReg());
137 if (TargetRegisterInfo::isVirtualRegister(DefReg)) {
138 MachineInstr *LoadMI = MRI->getVRegDef(DefReg);
139 if (LoadMI && LoadMI->getOpcode() == PPC::LXVDSX)
144 if (DefMI && (Immed == 0 || Immed == 3)) {
145 if (DefOpc == PPC::LXVDSX || isConversionOfLoadAndSplat()) {
147 << "Optimizing load-and-splat/splat "
148 "to load-and-splat/copy: ");
150 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY),
151 MI.getOperand(0).getReg())
152 .add(MI.getOperand(1));
158 // If this is a splat or a swap fed by another splat, we
159 // can replace it with a copy.
160 if (DefOpc == PPC::XXPERMDI) {
161 unsigned FeedImmed = DefMI->getOperand(3).getImm();
163 = lookThruCopyLike(DefMI->getOperand(1).getReg());
165 = lookThruCopyLike(DefMI->getOperand(2).getReg());
167 if ((FeedImmed == 0 || FeedImmed == 3) && FeedReg1 == FeedReg2) {
169 << "Optimizing splat/swap or splat/splat "
172 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY),
173 MI.getOperand(0).getReg())
174 .add(MI.getOperand(1));
179 // If this is a splat fed by a swap, we can simplify modify
180 // the splat to splat the other value from the swap's input
182 else if ((Immed == 0 || Immed == 3)
183 && FeedImmed == 2 && FeedReg1 == FeedReg2) {
184 DEBUG(dbgs() << "Optimizing swap/splat => splat: ");
186 MI.getOperand(1).setReg(DefMI->getOperand(1).getReg());
187 MI.getOperand(2).setReg(DefMI->getOperand(2).getReg());
188 MI.getOperand(3).setImm(3 - Immed);
192 // If this is a swap fed by a swap, we can replace it
193 // with a copy from the first swap's input.
194 else if (Immed == 2 && FeedImmed == 2 && FeedReg1 == FeedReg2) {
195 DEBUG(dbgs() << "Optimizing swap/swap => copy: ");
197 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY),
198 MI.getOperand(0).getReg())
199 .add(DefMI->getOperand(1));
203 } else if ((Immed == 0 || Immed == 3) && DefOpc == PPC::XXPERMDIs &&
204 (DefMI->getOperand(2).getImm() == 0 ||
205 DefMI->getOperand(2).getImm() == 3)) {
206 // Splat fed by another splat - switch the output of the first
207 // and remove the second.
208 DefMI->getOperand(0).setReg(MI.getOperand(0).getReg());
211 DEBUG(dbgs() << "Removing redundant splat: ");
221 unsigned MyOpcode = MI.getOpcode();
222 unsigned OpNo = MyOpcode == PPC::XXSPLTW ? 1 : 2;
223 unsigned TrueReg = lookThruCopyLike(MI.getOperand(OpNo).getReg());
224 if (!TargetRegisterInfo::isVirtualRegister(TrueReg))
226 MachineInstr *DefMI = MRI->getVRegDef(TrueReg);
229 unsigned DefOpcode = DefMI->getOpcode();
230 auto isConvertOfSplat = [=]() -> bool {
231 if (DefOpcode != PPC::XVCVSPSXWS && DefOpcode != PPC::XVCVSPUXWS)
233 unsigned ConvReg = DefMI->getOperand(1).getReg();
234 if (!TargetRegisterInfo::isVirtualRegister(ConvReg))
236 MachineInstr *Splt = MRI->getVRegDef(ConvReg);
237 return Splt && (Splt->getOpcode() == PPC::LXVWSX ||
238 Splt->getOpcode() == PPC::XXSPLTW);
240 bool AlreadySplat = (MyOpcode == DefOpcode) ||
241 (MyOpcode == PPC::VSPLTB && DefOpcode == PPC::VSPLTBs) ||
242 (MyOpcode == PPC::VSPLTH && DefOpcode == PPC::VSPLTHs) ||
243 (MyOpcode == PPC::XXSPLTW && DefOpcode == PPC::XXSPLTWs) ||
244 (MyOpcode == PPC::XXSPLTW && DefOpcode == PPC::LXVWSX) ||
245 (MyOpcode == PPC::XXSPLTW && DefOpcode == PPC::MTVSRWS)||
246 (MyOpcode == PPC::XXSPLTW && isConvertOfSplat());
247 // If the instruction[s] that feed this splat have already splat
248 // the value, this splat is redundant.
250 DEBUG(dbgs() << "Changing redundant splat to a copy: ");
252 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY),
253 MI.getOperand(0).getReg())
254 .add(MI.getOperand(OpNo));
258 // Splat fed by a shift. Usually when we align value to splat into
259 // vector element zero.
260 if (DefOpcode == PPC::XXSLDWI) {
261 unsigned ShiftRes = DefMI->getOperand(0).getReg();
262 unsigned ShiftOp1 = DefMI->getOperand(1).getReg();
263 unsigned ShiftOp2 = DefMI->getOperand(2).getReg();
264 unsigned ShiftImm = DefMI->getOperand(3).getImm();
265 unsigned SplatImm = MI.getOperand(2).getImm();
266 if (ShiftOp1 == ShiftOp2) {
267 unsigned NewElem = (SplatImm + ShiftImm) & 0x3;
268 if (MRI->hasOneNonDBGUse(ShiftRes)) {
269 DEBUG(dbgs() << "Removing redundant shift: ");
270 DEBUG(DefMI->dump());
274 DEBUG(dbgs() << "Changing splat immediate from " << SplatImm <<
275 " to " << NewElem << " in instruction: ");
277 MI.getOperand(1).setReg(ShiftOp1);
278 MI.getOperand(2).setImm(NewElem);
283 case PPC::XVCVDPSP: {
284 // If this is a DP->SP conversion fed by an FRSP, the FRSP is redundant.
285 unsigned TrueReg = lookThruCopyLike(MI.getOperand(1).getReg());
286 if (!TargetRegisterInfo::isVirtualRegister(TrueReg))
288 MachineInstr *DefMI = MRI->getVRegDef(TrueReg);
290 // This can occur when building a vector of single precision or integer
292 if (DefMI && DefMI->getOpcode() == PPC::XXPERMDI) {
293 unsigned DefsReg1 = lookThruCopyLike(DefMI->getOperand(1).getReg());
294 unsigned DefsReg2 = lookThruCopyLike(DefMI->getOperand(2).getReg());
295 if (!TargetRegisterInfo::isVirtualRegister(DefsReg1) ||
296 !TargetRegisterInfo::isVirtualRegister(DefsReg2))
298 MachineInstr *P1 = MRI->getVRegDef(DefsReg1);
299 MachineInstr *P2 = MRI->getVRegDef(DefsReg2);
304 // Remove the passed FRSP instruction if it only feeds this MI and
305 // set any uses of that FRSP (in this MI) to the source of the FRSP.
306 auto removeFRSPIfPossible = [&](MachineInstr *RoundInstr) {
307 if (RoundInstr->getOpcode() == PPC::FRSP &&
308 MRI->hasOneNonDBGUse(RoundInstr->getOperand(0).getReg())) {
310 unsigned ConvReg1 = RoundInstr->getOperand(1).getReg();
311 unsigned FRSPDefines = RoundInstr->getOperand(0).getReg();
312 MachineInstr &Use = *(MRI->use_instr_begin(FRSPDefines));
313 for (int i = 0, e = Use.getNumOperands(); i < e; ++i)
314 if (Use.getOperand(i).isReg() &&
315 Use.getOperand(i).getReg() == FRSPDefines)
316 Use.getOperand(i).setReg(ConvReg1);
317 DEBUG(dbgs() << "Removing redundant FRSP:\n");
318 DEBUG(RoundInstr->dump());
319 DEBUG(dbgs() << "As it feeds instruction:\n");
321 DEBUG(dbgs() << "Through instruction:\n");
322 DEBUG(DefMI->dump());
323 RoundInstr->eraseFromParent();
327 // If the input to XVCVDPSP is a vector that was built (even
328 // partially) out of FRSP's, the FRSP(s) can safely be removed
329 // since this instruction performs the same operation.
331 removeFRSPIfPossible(P1);
332 removeFRSPIfPossible(P2);
335 removeFRSPIfPossible(P1);
341 // If the last instruction was marked for elimination,
344 ToErase->eraseFromParent();
352 // This is used to find the "true" source register for an
353 // XXPERMDI instruction, since MachineCSE does not handle the
354 // "copy-like" operations (Copy and SubregToReg). Returns
355 // the original SrcReg unless it is the target of a copy-like
356 // operation, in which case we chain backwards through all
357 // such operations to the ultimate source register. If a
358 // physical register is encountered, we stop the search.
359 unsigned PPCMIPeephole::lookThruCopyLike(unsigned SrcReg) {
363 MachineInstr *MI = MRI->getVRegDef(SrcReg);
364 if (!MI->isCopyLike())
369 CopySrcReg = MI->getOperand(1).getReg();
371 assert(MI->isSubregToReg() && "bad opcode for lookThruCopyLike");
372 CopySrcReg = MI->getOperand(2).getReg();
375 if (!TargetRegisterInfo::isVirtualRegister(CopySrcReg))
382 } // end default namespace
384 INITIALIZE_PASS_BEGIN(PPCMIPeephole, DEBUG_TYPE,
385 "PowerPC MI Peephole Optimization", false, false)
386 INITIALIZE_PASS_END(PPCMIPeephole, DEBUG_TYPE,
387 "PowerPC MI Peephole Optimization", false, false)
389 char PPCMIPeephole::ID = 0;
391 llvm::createPPCMIPeepholePass() { return new PPCMIPeephole(); }