1 //===-- PPCRegisterInfo.cpp - PowerPC Register Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the TargetRegisterInfo
13 //===----------------------------------------------------------------------===//
15 #include "PPCRegisterInfo.h"
17 #include "PPCFrameLowering.h"
18 #include "PPCInstrBuilder.h"
19 #include "PPCMachineFunctionInfo.h"
20 #include "PPCSubtarget.h"
21 #include "PPCTargetMachine.h"
22 #include "llvm/ADT/BitVector.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineModuleInfo.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/CodeGen/RegisterScavenging.h"
30 #include "llvm/IR/CallingConv.h"
31 #include "llvm/IR/Constants.h"
32 #include "llvm/IR/Function.h"
33 #include "llvm/IR/Type.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/MathExtras.h"
38 #include "llvm/Support/raw_ostream.h"
39 #include "llvm/Target/TargetFrameLowering.h"
40 #include "llvm/Target/TargetInstrInfo.h"
41 #include "llvm/Target/TargetMachine.h"
42 #include "llvm/Target/TargetOptions.h"
47 #define DEBUG_TYPE "reginfo"
49 #define GET_REGINFO_TARGET_DESC
50 #include "PPCGenRegisterInfo.inc"
53 EnableBasePointer("ppc-use-base-pointer", cl::Hidden, cl::init(true),
54 cl::desc("Enable use of a base pointer for complex stack frames"));
57 AlwaysBasePointer("ppc-always-use-base-pointer", cl::Hidden, cl::init(false),
58 cl::desc("Force the use of a base pointer in every function"));
60 PPCRegisterInfo::PPCRegisterInfo(const PPCTargetMachine &TM)
61 : PPCGenRegisterInfo(TM.isPPC64() ? PPC::LR8 : PPC::LR,
63 TM.isPPC64() ? 0 : 1),
65 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
66 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
67 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
68 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
69 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
70 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
71 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
72 ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
73 ImmToIdxMap[PPC::LWA_32] = PPC::LWAX_32;
76 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8;
77 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8;
78 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8;
79 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX;
80 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8;
83 ImmToIdxMap[PPC::DFLOADf32] = PPC::LXSSPX;
84 ImmToIdxMap[PPC::DFLOADf64] = PPC::LXSDX;
85 ImmToIdxMap[PPC::DFSTOREf32] = PPC::STXSSPX;
86 ImmToIdxMap[PPC::DFSTOREf64] = PPC::STXSDX;
87 ImmToIdxMap[PPC::LXV] = PPC::LXVX;
88 ImmToIdxMap[PPC::LXSD] = PPC::LXSDX;
89 ImmToIdxMap[PPC::LXSSP] = PPC::LXSSPX;
90 ImmToIdxMap[PPC::STXV] = PPC::STXVX;
91 ImmToIdxMap[PPC::STXSD] = PPC::STXSDX;
92 ImmToIdxMap[PPC::STXSSP] = PPC::STXSSPX;
95 /// getPointerRegClass - Return the register class to use to hold pointers.
96 /// This is used for addressing modes.
97 const TargetRegisterClass *
98 PPCRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
100 // Note that PPCInstrInfo::FoldImmediate also directly uses this Kind value
101 // when it checks for ZERO folding.
104 return &PPC::G8RC_NOX0RegClass;
105 return &PPC::GPRC_NOR0RegClass;
109 return &PPC::G8RCRegClass;
110 return &PPC::GPRCRegClass;
114 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
115 const PPCSubtarget &Subtarget = MF->getSubtarget<PPCSubtarget>();
116 if (MF->getFunction()->getCallingConv() == CallingConv::AnyReg) {
117 if (Subtarget.hasVSX())
118 return CSR_64_AllRegs_VSX_SaveList;
119 if (Subtarget.hasAltivec())
120 return CSR_64_AllRegs_Altivec_SaveList;
121 return CSR_64_AllRegs_SaveList;
124 if (Subtarget.isDarwinABI())
126 ? (Subtarget.hasAltivec() ? CSR_Darwin64_Altivec_SaveList
127 : CSR_Darwin64_SaveList)
128 : (Subtarget.hasAltivec() ? CSR_Darwin32_Altivec_SaveList
129 : CSR_Darwin32_SaveList);
131 if (TM.isPPC64() && MF->getInfo<PPCFunctionInfo>()->isSplitCSR())
132 return CSR_SRV464_TLS_PE_SaveList;
134 // On PPC64, we might need to save r2 (but only if it is not reserved).
135 bool SaveR2 = MF->getRegInfo().isAllocatable(PPC::X2);
138 ? (Subtarget.hasAltivec()
139 ? (SaveR2 ? CSR_SVR464_R2_Altivec_SaveList
140 : CSR_SVR464_Altivec_SaveList)
141 : (SaveR2 ? CSR_SVR464_R2_SaveList : CSR_SVR464_SaveList))
142 : (Subtarget.hasAltivec() ? CSR_SVR432_Altivec_SaveList
143 : CSR_SVR432_SaveList);
147 PPCRegisterInfo::getCalleeSavedRegsViaCopy(const MachineFunction *MF) const {
148 assert(MF && "Invalid MachineFunction pointer.");
149 const PPCSubtarget &Subtarget = MF->getSubtarget<PPCSubtarget>();
150 if (Subtarget.isDarwinABI())
154 if (MF->getFunction()->getCallingConv() != CallingConv::CXX_FAST_TLS)
156 if (!MF->getInfo<PPCFunctionInfo>()->isSplitCSR())
159 // On PPC64, we might need to save r2 (but only if it is not reserved).
160 bool SaveR2 = !getReservedRegs(*MF).test(PPC::X2);
161 if (Subtarget.hasAltivec())
163 ? CSR_SVR464_R2_Altivec_ViaCopy_SaveList
164 : CSR_SVR464_Altivec_ViaCopy_SaveList;
167 ? CSR_SVR464_R2_ViaCopy_SaveList
168 : CSR_SVR464_ViaCopy_SaveList;
172 PPCRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
173 CallingConv::ID CC) const {
174 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
175 if (CC == CallingConv::AnyReg) {
176 if (Subtarget.hasVSX())
177 return CSR_64_AllRegs_VSX_RegMask;
178 if (Subtarget.hasAltivec())
179 return CSR_64_AllRegs_Altivec_RegMask;
180 return CSR_64_AllRegs_RegMask;
183 if (Subtarget.isDarwinABI())
184 return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_Darwin64_Altivec_RegMask
185 : CSR_Darwin64_RegMask)
186 : (Subtarget.hasAltivec() ? CSR_Darwin32_Altivec_RegMask
187 : CSR_Darwin32_RegMask);
189 return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_SVR464_Altivec_RegMask
190 : CSR_SVR464_RegMask)
191 : (Subtarget.hasAltivec() ? CSR_SVR432_Altivec_RegMask
192 : CSR_SVR432_RegMask);
196 PPCRegisterInfo::getNoPreservedMask() const {
197 return CSR_NoRegs_RegMask;
200 void PPCRegisterInfo::adjustStackMapLiveOutMask(uint32_t *Mask) const {
201 for (unsigned PseudoReg : {PPC::ZERO, PPC::ZERO8, PPC::RM})
202 Mask[PseudoReg / 32] &= ~(1u << (PseudoReg % 32));
205 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
206 BitVector Reserved(getNumRegs());
207 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
208 const PPCFrameLowering *TFI = getFrameLowering(MF);
210 // The ZERO register is not really a register, but the representation of r0
211 // when used in instructions that treat r0 as the constant 0.
212 markSuperRegs(Reserved, PPC::ZERO);
214 // The FP register is also not really a register, but is the representation
215 // of the frame pointer register used by ISD::FRAMEADDR.
216 markSuperRegs(Reserved, PPC::FP);
218 // The BP register is also not really a register, but is the representation
219 // of the base pointer register used by setjmp.
220 markSuperRegs(Reserved, PPC::BP);
222 // The counter registers must be reserved so that counter-based loops can
223 // be correctly formed (and the mtctr instructions are not DCE'd).
224 markSuperRegs(Reserved, PPC::CTR);
225 markSuperRegs(Reserved, PPC::CTR8);
227 markSuperRegs(Reserved, PPC::R1);
228 markSuperRegs(Reserved, PPC::LR);
229 markSuperRegs(Reserved, PPC::LR8);
230 markSuperRegs(Reserved, PPC::RM);
232 if (!Subtarget.isDarwinABI() || !Subtarget.hasAltivec())
233 markSuperRegs(Reserved, PPC::VRSAVE);
235 // The SVR4 ABI reserves r2 and r13
236 if (Subtarget.isSVR4ABI()) {
237 // We only reserve r2 if we need to use the TOC pointer. If we have no
238 // explicit uses of the TOC pointer (meaning we're a leaf function with
239 // no constant-pool loads, etc.) and we have no potential uses inside an
240 // inline asm block, then we can treat r2 has an ordinary callee-saved
242 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
243 if (!TM.isPPC64() || FuncInfo->usesTOCBasePtr() || MF.hasInlineAsm())
244 markSuperRegs(Reserved, PPC::R2); // System-reserved register
245 markSuperRegs(Reserved, PPC::R13); // Small Data Area pointer register
248 // On PPC64, r13 is the thread pointer. Never allocate this register.
250 markSuperRegs(Reserved, PPC::R13);
252 if (TFI->needsFP(MF))
253 markSuperRegs(Reserved, PPC::R31);
255 bool IsPositionIndependent = TM.isPositionIndependent();
256 if (hasBasePointer(MF)) {
257 if (Subtarget.isSVR4ABI() && !TM.isPPC64() && IsPositionIndependent)
258 markSuperRegs(Reserved, PPC::R29);
260 markSuperRegs(Reserved, PPC::R30);
263 if (Subtarget.isSVR4ABI() && !TM.isPPC64() && IsPositionIndependent)
264 markSuperRegs(Reserved, PPC::R30);
266 // Reserve Altivec registers when Altivec is unavailable.
267 if (!Subtarget.hasAltivec())
268 for (TargetRegisterClass::iterator I = PPC::VRRCRegClass.begin(),
269 IE = PPC::VRRCRegClass.end(); I != IE; ++I)
270 markSuperRegs(Reserved, *I);
272 assert(checkAllSuperRegsMarked(Reserved));
276 unsigned PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
277 MachineFunction &MF) const {
278 const PPCFrameLowering *TFI = getFrameLowering(MF);
279 const unsigned DefaultSafety = 1;
281 switch (RC->getID()) {
284 case PPC::G8RC_NOX0RegClassID:
285 case PPC::GPRC_NOR0RegClassID:
286 case PPC::G8RCRegClassID:
287 case PPC::GPRCRegClassID: {
288 unsigned FP = TFI->hasFP(MF) ? 1 : 0;
289 return 32 - FP - DefaultSafety;
291 case PPC::F8RCRegClassID:
292 case PPC::F4RCRegClassID:
293 case PPC::QFRCRegClassID:
294 case PPC::QSRCRegClassID:
295 case PPC::QBRCRegClassID:
296 case PPC::VRRCRegClassID:
297 case PPC::VFRCRegClassID:
298 case PPC::VSLRCRegClassID:
299 return 32 - DefaultSafety;
300 case PPC::VSRCRegClassID:
301 case PPC::VSFRCRegClassID:
302 case PPC::VSSRCRegClassID:
303 return 64 - DefaultSafety;
304 case PPC::CRRCRegClassID:
305 return 8 - DefaultSafety;
309 const TargetRegisterClass *
310 PPCRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
311 const MachineFunction &MF) const {
312 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
313 if (Subtarget.hasVSX()) {
314 // With VSX, we can inflate various sub-register classes to the full VSX
317 if (RC == &PPC::F8RCRegClass)
318 return &PPC::VSFRCRegClass;
319 else if (RC == &PPC::VRRCRegClass)
320 return &PPC::VSRCRegClass;
321 else if (RC == &PPC::F4RCRegClass && Subtarget.hasP8Vector())
322 return &PPC::VSSRCRegClass;
325 return TargetRegisterInfo::getLargestLegalSuperClass(RC, MF);
328 //===----------------------------------------------------------------------===//
329 // Stack Frame Processing methods
330 //===----------------------------------------------------------------------===//
332 /// lowerDynamicAlloc - Generate the code for allocating an object in the
333 /// current frame. The sequence of code will be in the general form
335 /// addi R0, SP, \#frameSize ; get the address of the previous frame
336 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size
337 /// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation
339 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II) const {
340 // Get the instruction.
341 MachineInstr &MI = *II;
342 // Get the instruction's basic block.
343 MachineBasicBlock &MBB = *MI.getParent();
344 // Get the basic block's function.
345 MachineFunction &MF = *MBB.getParent();
346 // Get the frame info.
347 MachineFrameInfo &MFI = MF.getFrameInfo();
348 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
349 // Get the instruction info.
350 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
351 // Determine whether 64-bit pointers are used.
352 bool LP64 = TM.isPPC64();
353 DebugLoc dl = MI.getDebugLoc();
355 // Get the maximum call stack size.
356 unsigned maxCallFrameSize = MFI.getMaxCallFrameSize();
357 // Get the total frame size.
358 unsigned FrameSize = MFI.getStackSize();
360 // Get stack alignments.
361 const PPCFrameLowering *TFI = getFrameLowering(MF);
362 unsigned TargetAlign = TFI->getStackAlignment();
363 unsigned MaxAlign = MFI.getMaxAlignment();
364 assert((maxCallFrameSize & (MaxAlign-1)) == 0 &&
365 "Maximum call-frame size not sufficiently aligned");
367 // Determine the previous frame's address. If FrameSize can't be
368 // represented as 16 bits or we need special alignment, then we load the
369 // previous frame's address from 0(SP). Why not do an addis of the hi?
370 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero.
371 // Constructing the constant and adding would take 3 instructions.
372 // Fortunately, a frame greater than 32K is rare.
373 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
374 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
375 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
377 if (MaxAlign < TargetAlign && isInt<16>(FrameSize)) {
378 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg)
382 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg)
386 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg)
391 bool KillNegSizeReg = MI.getOperand(1).isKill();
392 unsigned NegSizeReg = MI.getOperand(1).getReg();
394 // Grow the stack and update the stack pointer link, then determine the
395 // address of new allocated space.
397 if (MaxAlign > TargetAlign) {
398 unsigned UnalNegSizeReg = NegSizeReg;
399 NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC);
401 // Unfortunately, there is no andi, only andi., and we can't insert that
402 // here because we might clobber cr0 while it is live.
403 BuildMI(MBB, II, dl, TII.get(PPC::LI8), NegSizeReg)
404 .addImm(~(MaxAlign-1));
406 unsigned NegSizeReg1 = NegSizeReg;
407 NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC);
408 BuildMI(MBB, II, dl, TII.get(PPC::AND8), NegSizeReg)
409 .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg))
410 .addReg(NegSizeReg1, RegState::Kill);
411 KillNegSizeReg = true;
414 BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1)
415 .addReg(Reg, RegState::Kill)
417 .addReg(NegSizeReg, getKillRegState(KillNegSizeReg));
418 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
420 .addImm(maxCallFrameSize);
422 if (MaxAlign > TargetAlign) {
423 unsigned UnalNegSizeReg = NegSizeReg;
424 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC);
426 // Unfortunately, there is no andi, only andi., and we can't insert that
427 // here because we might clobber cr0 while it is live.
428 BuildMI(MBB, II, dl, TII.get(PPC::LI), NegSizeReg)
429 .addImm(~(MaxAlign-1));
431 unsigned NegSizeReg1 = NegSizeReg;
432 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC);
433 BuildMI(MBB, II, dl, TII.get(PPC::AND), NegSizeReg)
434 .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg))
435 .addReg(NegSizeReg1, RegState::Kill);
436 KillNegSizeReg = true;
439 BuildMI(MBB, II, dl, TII.get(PPC::STWUX), PPC::R1)
440 .addReg(Reg, RegState::Kill)
442 .addReg(NegSizeReg, getKillRegState(KillNegSizeReg));
443 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
445 .addImm(maxCallFrameSize);
448 // Discard the DYNALLOC instruction.
452 void PPCRegisterInfo::lowerDynamicAreaOffset(
453 MachineBasicBlock::iterator II) const {
454 // Get the instruction.
455 MachineInstr &MI = *II;
456 // Get the instruction's basic block.
457 MachineBasicBlock &MBB = *MI.getParent();
458 // Get the basic block's function.
459 MachineFunction &MF = *MBB.getParent();
460 // Get the frame info.
461 MachineFrameInfo &MFI = MF.getFrameInfo();
462 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
463 // Get the instruction info.
464 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
466 unsigned maxCallFrameSize = MFI.getMaxCallFrameSize();
467 DebugLoc dl = MI.getDebugLoc();
468 BuildMI(MBB, II, dl, TII.get(PPC::LI), MI.getOperand(0).getReg())
469 .addImm(maxCallFrameSize);
473 /// lowerCRSpilling - Generate the code for spilling a CR register. Instead of
474 /// reserving a whole register (R0), we scrounge for one here. This generates
477 /// mfcr rA ; Move the conditional register into GPR rA.
478 /// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot.
479 /// stw rA, FI ; Store rA to the frame.
481 void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II,
482 unsigned FrameIndex) const {
483 // Get the instruction.
484 MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset>
485 // Get the instruction's basic block.
486 MachineBasicBlock &MBB = *MI.getParent();
487 MachineFunction &MF = *MBB.getParent();
488 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
489 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
490 DebugLoc dl = MI.getDebugLoc();
492 bool LP64 = TM.isPPC64();
493 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
494 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
496 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
497 unsigned SrcReg = MI.getOperand(0).getReg();
499 // We need to store the CR in the low 4-bits of the saved value. First, issue
500 // an MFOCRF to save all of the CRBits and, if needed, kill the SrcReg.
501 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg)
502 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
504 // If the saved register wasn't CR0, shift the bits left so that they are in
506 if (SrcReg != PPC::CR0) {
508 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
510 // rlwinm rA, rA, ShiftBits, 0, 31.
511 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
512 .addReg(Reg1, RegState::Kill)
513 .addImm(getEncodingValue(SrcReg) * 4)
518 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW))
519 .addReg(Reg, RegState::Kill),
522 // Discard the pseudo instruction.
526 void PPCRegisterInfo::lowerCRRestore(MachineBasicBlock::iterator II,
527 unsigned FrameIndex) const {
528 // Get the instruction.
529 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CR <offset>
530 // Get the instruction's basic block.
531 MachineBasicBlock &MBB = *MI.getParent();
532 MachineFunction &MF = *MBB.getParent();
533 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
534 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
535 DebugLoc dl = MI.getDebugLoc();
537 bool LP64 = TM.isPPC64();
538 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
539 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
541 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
542 unsigned DestReg = MI.getOperand(0).getReg();
543 assert(MI.definesRegister(DestReg) &&
544 "RESTORE_CR does not define its destination");
546 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ),
549 // If the reloaded register isn't CR0, shift the bits right so that they are
550 // in the right CR's slot.
551 if (DestReg != PPC::CR0) {
553 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
555 unsigned ShiftBits = getEncodingValue(DestReg)*4;
556 // rlwinm r11, r11, 32-ShiftBits, 0, 31.
557 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
558 .addReg(Reg1, RegState::Kill).addImm(32-ShiftBits).addImm(0)
562 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF), DestReg)
563 .addReg(Reg, RegState::Kill);
565 // Discard the pseudo instruction.
569 void PPCRegisterInfo::lowerCRBitSpilling(MachineBasicBlock::iterator II,
570 unsigned FrameIndex) const {
571 // Get the instruction.
572 MachineInstr &MI = *II; // ; SPILL_CRBIT <SrcReg>, <offset>
573 // Get the instruction's basic block.
574 MachineBasicBlock &MBB = *MI.getParent();
575 MachineFunction &MF = *MBB.getParent();
576 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
577 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
578 DebugLoc dl = MI.getDebugLoc();
580 bool LP64 = TM.isPPC64();
581 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
582 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
584 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
585 unsigned SrcReg = MI.getOperand(0).getReg();
587 BuildMI(MBB, II, dl, TII.get(TargetOpcode::KILL),
588 getCRFromCRBit(SrcReg))
589 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
591 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg)
592 .addReg(getCRFromCRBit(SrcReg));
594 // If the saved register wasn't CR0LT, shift the bits left so that the bit to
595 // store is the first one. Mask all but that bit.
597 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
599 // rlwinm rA, rA, ShiftBits, 0, 0.
600 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
601 .addReg(Reg1, RegState::Kill)
602 .addImm(getEncodingValue(SrcReg))
603 .addImm(0).addImm(0);
605 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW))
606 .addReg(Reg, RegState::Kill),
609 // Discard the pseudo instruction.
613 void PPCRegisterInfo::lowerCRBitRestore(MachineBasicBlock::iterator II,
614 unsigned FrameIndex) const {
615 // Get the instruction.
616 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CRBIT <offset>
617 // Get the instruction's basic block.
618 MachineBasicBlock &MBB = *MI.getParent();
619 MachineFunction &MF = *MBB.getParent();
620 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
621 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
622 DebugLoc dl = MI.getDebugLoc();
624 bool LP64 = TM.isPPC64();
625 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
626 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
628 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
629 unsigned DestReg = MI.getOperand(0).getReg();
630 assert(MI.definesRegister(DestReg) &&
631 "RESTORE_CRBIT does not define its destination");
633 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ),
636 BuildMI(MBB, II, dl, TII.get(TargetOpcode::IMPLICIT_DEF), DestReg);
638 unsigned RegO = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
639 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), RegO)
640 .addReg(getCRFromCRBit(DestReg));
642 unsigned ShiftBits = getEncodingValue(DestReg);
643 // rlwimi r11, r10, 32-ShiftBits, ..., ...
644 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWIMI8 : PPC::RLWIMI), RegO)
645 .addReg(RegO, RegState::Kill)
646 .addReg(Reg, RegState::Kill)
647 .addImm(ShiftBits ? 32 - ShiftBits : 0)
651 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF),
652 getCRFromCRBit(DestReg))
653 .addReg(RegO, RegState::Kill)
654 // Make sure we have a use dependency all the way through this
655 // sequence of instructions. We can't have the other bits in the CR
656 // modified in between the mfocrf and the mtocrf.
657 .addReg(getCRFromCRBit(DestReg), RegState::Implicit);
659 // Discard the pseudo instruction.
663 void PPCRegisterInfo::lowerVRSAVESpilling(MachineBasicBlock::iterator II,
664 unsigned FrameIndex) const {
665 // Get the instruction.
666 MachineInstr &MI = *II; // ; SPILL_VRSAVE <SrcReg>, <offset>
667 // Get the instruction's basic block.
668 MachineBasicBlock &MBB = *MI.getParent();
669 MachineFunction &MF = *MBB.getParent();
670 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
671 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
672 DebugLoc dl = MI.getDebugLoc();
674 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
675 unsigned Reg = MF.getRegInfo().createVirtualRegister(GPRC);
676 unsigned SrcReg = MI.getOperand(0).getReg();
678 BuildMI(MBB, II, dl, TII.get(PPC::MFVRSAVEv), Reg)
679 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
682 BuildMI(MBB, II, dl, TII.get(PPC::STW)).addReg(Reg, RegState::Kill),
685 // Discard the pseudo instruction.
689 void PPCRegisterInfo::lowerVRSAVERestore(MachineBasicBlock::iterator II,
690 unsigned FrameIndex) const {
691 // Get the instruction.
692 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_VRSAVE <offset>
693 // Get the instruction's basic block.
694 MachineBasicBlock &MBB = *MI.getParent();
695 MachineFunction &MF = *MBB.getParent();
696 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
697 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
698 DebugLoc dl = MI.getDebugLoc();
700 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
701 unsigned Reg = MF.getRegInfo().createVirtualRegister(GPRC);
702 unsigned DestReg = MI.getOperand(0).getReg();
703 assert(MI.definesRegister(DestReg) &&
704 "RESTORE_VRSAVE does not define its destination");
706 addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::LWZ),
709 BuildMI(MBB, II, dl, TII.get(PPC::MTVRSAVEv), DestReg)
710 .addReg(Reg, RegState::Kill);
712 // Discard the pseudo instruction.
716 bool PPCRegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
717 unsigned Reg, int &FrameIdx) const {
718 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
719 // For the nonvolatile condition registers (CR2, CR3, CR4) in an SVR4
720 // ABI, return true to prevent allocating an additional frame slot.
721 // For 64-bit, the CR save area is at SP+8; the value of FrameIdx = 0
722 // is arbitrary and will be subsequently ignored. For 32-bit, we have
723 // previously created the stack slot if needed, so return its FrameIdx.
724 if (Subtarget.isSVR4ABI() && PPC::CR2 <= Reg && Reg <= PPC::CR4) {
728 const PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
729 FrameIdx = FI->getCRSpillFrameIndex();
736 // Figure out if the offset in the instruction must be a multiple of 4.
737 // This is true for instructions like "STD".
738 static bool usesIXAddr(const MachineInstr &MI) {
739 unsigned OpC = MI.getOpcode();
752 // Return the OffsetOperandNo given the FIOperandNum (and the instruction).
753 static unsigned getOffsetONFromFION(const MachineInstr &MI,
754 unsigned FIOperandNum) {
755 // Take into account whether it's an add or mem instruction
756 unsigned OffsetOperandNo = (FIOperandNum == 2) ? 1 : 2;
757 if (MI.isInlineAsm())
758 OffsetOperandNo = FIOperandNum - 1;
759 else if (MI.getOpcode() == TargetOpcode::STACKMAP ||
760 MI.getOpcode() == TargetOpcode::PATCHPOINT)
761 OffsetOperandNo = FIOperandNum + 1;
763 return OffsetOperandNo;
767 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
768 int SPAdj, unsigned FIOperandNum,
769 RegScavenger *RS) const {
770 assert(SPAdj == 0 && "Unexpected");
772 // Get the instruction.
773 MachineInstr &MI = *II;
774 // Get the instruction's basic block.
775 MachineBasicBlock &MBB = *MI.getParent();
776 // Get the basic block's function.
777 MachineFunction &MF = *MBB.getParent();
778 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
779 // Get the instruction info.
780 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
781 // Get the frame info.
782 MachineFrameInfo &MFI = MF.getFrameInfo();
783 DebugLoc dl = MI.getDebugLoc();
785 unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum);
787 // Get the frame index.
788 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
790 // Get the frame pointer save index. Users of this index are primarily
791 // DYNALLOC instructions.
792 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
793 int FPSI = FI->getFramePointerSaveIndex();
794 // Get the instruction opcode.
795 unsigned OpC = MI.getOpcode();
797 if ((OpC == PPC::DYNAREAOFFSET || OpC == PPC::DYNAREAOFFSET8)) {
798 lowerDynamicAreaOffset(II);
802 // Special case for dynamic alloca.
803 if (FPSI && FrameIndex == FPSI &&
804 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) {
805 lowerDynamicAlloc(II);
809 // Special case for pseudo-ops SPILL_CR and RESTORE_CR, etc.
810 if (OpC == PPC::SPILL_CR) {
811 lowerCRSpilling(II, FrameIndex);
813 } else if (OpC == PPC::RESTORE_CR) {
814 lowerCRRestore(II, FrameIndex);
816 } else if (OpC == PPC::SPILL_CRBIT) {
817 lowerCRBitSpilling(II, FrameIndex);
819 } else if (OpC == PPC::RESTORE_CRBIT) {
820 lowerCRBitRestore(II, FrameIndex);
822 } else if (OpC == PPC::SPILL_VRSAVE) {
823 lowerVRSAVESpilling(II, FrameIndex);
825 } else if (OpC == PPC::RESTORE_VRSAVE) {
826 lowerVRSAVERestore(II, FrameIndex);
830 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
831 MI.getOperand(FIOperandNum).ChangeToRegister(
832 FrameIndex < 0 ? getBaseRegister(MF) : getFrameRegister(MF), false);
834 // Figure out if the offset in the instruction is shifted right two bits.
835 bool isIXAddr = usesIXAddr(MI);
837 // If the instruction is not present in ImmToIdxMap, then it has no immediate
838 // form (and must be r+r).
839 bool noImmForm = !MI.isInlineAsm() && OpC != TargetOpcode::STACKMAP &&
840 OpC != TargetOpcode::PATCHPOINT && !ImmToIdxMap.count(OpC);
842 // Now add the frame object offset to the offset from r1.
843 int Offset = MFI.getObjectOffset(FrameIndex);
844 Offset += MI.getOperand(OffsetOperandNo).getImm();
846 // If we're not using a Frame Pointer that has been set to the value of the
847 // SP before having the stack size subtracted from it, then add the stack size
848 // to Offset to get the correct offset.
849 // Naked functions have stack size 0, although getStackSize may not reflect
850 // that because we didn't call all the pieces that compute it for naked
852 if (!MF.getFunction()->hasFnAttribute(Attribute::Naked)) {
853 if (!(hasBasePointer(MF) && FrameIndex < 0))
854 Offset += MFI.getStackSize();
857 // If we can, encode the offset directly into the instruction. If this is a
858 // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If
859 // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits
860 // clear can be encoded. This is extremely uncommon, because normally you
861 // only "std" to a stack slot that is at least 4-byte aligned, but it can
862 // happen in invalid code.
863 assert(OpC != PPC::DBG_VALUE &&
864 "This should be handled in a target-independent way");
865 if (!noImmForm && ((isInt<16>(Offset) && (!isIXAddr || (Offset & 3) == 0)) ||
866 OpC == TargetOpcode::STACKMAP ||
867 OpC == TargetOpcode::PATCHPOINT)) {
868 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
872 // The offset doesn't fit into a single register, scavenge one to build the
875 bool is64Bit = TM.isPPC64();
876 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
877 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
878 const TargetRegisterClass *RC = is64Bit ? G8RC : GPRC;
879 unsigned SRegHi = MF.getRegInfo().createVirtualRegister(RC),
880 SReg = MF.getRegInfo().createVirtualRegister(RC);
882 // Insert a set of rA with the full offset value before the ld, st, or add
883 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LIS8 : PPC::LIS), SRegHi)
884 .addImm(Offset >> 16);
885 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg)
886 .addReg(SRegHi, RegState::Kill)
889 // Convert into indexed form of the instruction:
891 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
892 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
893 unsigned OperandBase;
897 else if (OpC != TargetOpcode::INLINEASM) {
898 assert(ImmToIdxMap.count(OpC) &&
899 "No indexed form of load or store available!");
900 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second;
901 MI.setDesc(TII.get(NewOpcode));
904 OperandBase = OffsetOperandNo;
907 unsigned StackReg = MI.getOperand(FIOperandNum).getReg();
908 MI.getOperand(OperandBase).ChangeToRegister(StackReg, false);
909 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false, false, true);
912 unsigned PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
913 const PPCFrameLowering *TFI = getFrameLowering(MF);
916 return TFI->hasFP(MF) ? PPC::R31 : PPC::R1;
918 return TFI->hasFP(MF) ? PPC::X31 : PPC::X1;
921 unsigned PPCRegisterInfo::getBaseRegister(const MachineFunction &MF) const {
922 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
923 if (!hasBasePointer(MF))
924 return getFrameRegister(MF);
929 if (Subtarget.isSVR4ABI() && TM.isPositionIndependent())
935 bool PPCRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
936 if (!EnableBasePointer)
938 if (AlwaysBasePointer)
941 // If we need to realign the stack, then the stack pointer can no longer
942 // serve as an offset into the caller's stack space. As a result, we need a
944 return needsStackRealignment(MF);
947 /// Returns true if the instruction's frame index
948 /// reference would be better served by a base register other than FP
949 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
950 /// references it should create new base registers for.
951 bool PPCRegisterInfo::
952 needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
953 assert(Offset < 0 && "Local offset must be negative");
955 // It's the load/store FI references that cause issues, as it can be difficult
956 // to materialize the offset if it won't fit in the literal field. Estimate
957 // based on the size of the local frame and some conservative assumptions
958 // about the rest of the stack frame (note, this is pre-regalloc, so
959 // we don't know everything for certain yet) whether this offset is likely
960 // to be out of range of the immediate. Return true if so.
962 // We only generate virtual base registers for loads and stores that have
963 // an r+i form. Return false for everything else.
964 unsigned OpC = MI->getOpcode();
965 if (!ImmToIdxMap.count(OpC))
968 // Don't generate a new virtual base register just to add zero to it.
969 if ((OpC == PPC::ADDI || OpC == PPC::ADDI8) &&
970 MI->getOperand(2).getImm() == 0)
973 MachineBasicBlock &MBB = *MI->getParent();
974 MachineFunction &MF = *MBB.getParent();
975 const PPCFrameLowering *TFI = getFrameLowering(MF);
976 unsigned StackEst = TFI->determineFrameLayout(MF, false, true);
978 // If we likely don't need a stack frame, then we probably don't need a
979 // virtual base register either.
983 // Estimate an offset from the stack pointer.
984 // The incoming offset is relating to the SP at the start of the function,
985 // but when we access the local it'll be relative to the SP after local
986 // allocation, so adjust our SP-relative offset by that allocation size.
989 // The frame pointer will point to the end of the stack, so estimate the
990 // offset as the difference between the object offset and the FP location.
991 return !isFrameOffsetLegal(MI, getBaseRegister(MF), Offset);
994 /// Insert defining instruction(s) for BaseReg to
995 /// be a pointer to FrameIdx at the beginning of the basic block.
996 void PPCRegisterInfo::
997 materializeFrameBaseRegister(MachineBasicBlock *MBB,
998 unsigned BaseReg, int FrameIdx,
999 int64_t Offset) const {
1000 unsigned ADDriOpc = TM.isPPC64() ? PPC::ADDI8 : PPC::ADDI;
1002 MachineBasicBlock::iterator Ins = MBB->begin();
1003 DebugLoc DL; // Defaults to "unknown"
1004 if (Ins != MBB->end())
1005 DL = Ins->getDebugLoc();
1007 const MachineFunction &MF = *MBB->getParent();
1008 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1009 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1010 const MCInstrDesc &MCID = TII.get(ADDriOpc);
1011 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
1012 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
1014 BuildMI(*MBB, Ins, DL, MCID, BaseReg)
1015 .addFrameIndex(FrameIdx).addImm(Offset);
1018 void PPCRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
1019 int64_t Offset) const {
1020 unsigned FIOperandNum = 0;
1021 while (!MI.getOperand(FIOperandNum).isFI()) {
1023 assert(FIOperandNum < MI.getNumOperands() &&
1024 "Instr doesn't have FrameIndex operand!");
1027 MI.getOperand(FIOperandNum).ChangeToRegister(BaseReg, false);
1028 unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum);
1029 Offset += MI.getOperand(OffsetOperandNo).getImm();
1030 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
1032 MachineBasicBlock &MBB = *MI.getParent();
1033 MachineFunction &MF = *MBB.getParent();
1034 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1035 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1036 const MCInstrDesc &MCID = MI.getDesc();
1037 MachineRegisterInfo &MRI = MF.getRegInfo();
1038 MRI.constrainRegClass(BaseReg,
1039 TII.getRegClass(MCID, FIOperandNum, this, MF));
1042 bool PPCRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
1044 int64_t Offset) const {
1045 unsigned FIOperandNum = 0;
1046 while (!MI->getOperand(FIOperandNum).isFI()) {
1048 assert(FIOperandNum < MI->getNumOperands() &&
1049 "Instr doesn't have FrameIndex operand!");
1052 unsigned OffsetOperandNo = getOffsetONFromFION(*MI, FIOperandNum);
1053 Offset += MI->getOperand(OffsetOperandNo).getImm();
1055 return MI->getOpcode() == PPC::DBG_VALUE || // DBG_VALUE is always Reg+Imm
1056 MI->getOpcode() == TargetOpcode::STACKMAP ||
1057 MI->getOpcode() == TargetOpcode::PATCHPOINT ||
1058 (isInt<16>(Offset) && (!usesIXAddr(*MI) || (Offset & 3) == 0));