1 //===-- PPCRegisterInfo.cpp - PowerPC Register Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the TargetRegisterInfo
13 //===----------------------------------------------------------------------===//
15 #include "PPCRegisterInfo.h"
17 #include "PPCFrameLowering.h"
18 #include "PPCInstrBuilder.h"
19 #include "PPCMachineFunctionInfo.h"
20 #include "PPCSubtarget.h"
21 #include "PPCTargetMachine.h"
22 #include "llvm/ADT/BitVector.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineModuleInfo.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/CodeGen/RegisterScavenging.h"
30 #include "llvm/IR/CallingConv.h"
31 #include "llvm/IR/Constants.h"
32 #include "llvm/IR/Function.h"
33 #include "llvm/IR/Type.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/MathExtras.h"
38 #include "llvm/Support/raw_ostream.h"
39 #include "llvm/Target/TargetFrameLowering.h"
40 #include "llvm/Target/TargetInstrInfo.h"
41 #include "llvm/Target/TargetMachine.h"
42 #include "llvm/Target/TargetOptions.h"
47 #define DEBUG_TYPE "reginfo"
49 #define GET_REGINFO_TARGET_DESC
50 #include "PPCGenRegisterInfo.inc"
53 EnableBasePointer("ppc-use-base-pointer", cl::Hidden, cl::init(true),
54 cl::desc("Enable use of a base pointer for complex stack frames"));
57 AlwaysBasePointer("ppc-always-use-base-pointer", cl::Hidden, cl::init(false),
58 cl::desc("Force the use of a base pointer in every function"));
60 PPCRegisterInfo::PPCRegisterInfo(const PPCTargetMachine &TM)
61 : PPCGenRegisterInfo(TM.isPPC64() ? PPC::LR8 : PPC::LR,
63 TM.isPPC64() ? 0 : 1),
65 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
66 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
67 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
68 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
69 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
70 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
71 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
72 ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
73 ImmToIdxMap[PPC::LWA_32] = PPC::LWAX_32;
76 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8;
77 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8;
78 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8;
79 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX;
80 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8;
83 ImmToIdxMap[PPC::DFLOADf32] = PPC::LXSSPX;
84 ImmToIdxMap[PPC::DFLOADf64] = PPC::LXSDX;
85 ImmToIdxMap[PPC::DFSTOREf32] = PPC::STXSSPX;
86 ImmToIdxMap[PPC::DFSTOREf64] = PPC::STXSDX;
87 ImmToIdxMap[PPC::LXV] = PPC::LXVX;
88 ImmToIdxMap[PPC::LXSD] = PPC::LXSDX;
89 ImmToIdxMap[PPC::LXSSP] = PPC::LXSSPX;
90 ImmToIdxMap[PPC::STXV] = PPC::STXVX;
91 ImmToIdxMap[PPC::STXSD] = PPC::STXSDX;
92 ImmToIdxMap[PPC::STXSSP] = PPC::STXSSPX;
95 /// getPointerRegClass - Return the register class to use to hold pointers.
96 /// This is used for addressing modes.
97 const TargetRegisterClass *
98 PPCRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
100 // Note that PPCInstrInfo::FoldImmediate also directly uses this Kind value
101 // when it checks for ZERO folding.
104 return &PPC::G8RC_NOX0RegClass;
105 return &PPC::GPRC_NOR0RegClass;
109 return &PPC::G8RCRegClass;
110 return &PPC::GPRCRegClass;
114 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
115 const PPCSubtarget &Subtarget = MF->getSubtarget<PPCSubtarget>();
116 if (MF->getFunction()->getCallingConv() == CallingConv::AnyReg) {
117 if (Subtarget.hasVSX())
118 return CSR_64_AllRegs_VSX_SaveList;
119 if (Subtarget.hasAltivec())
120 return CSR_64_AllRegs_Altivec_SaveList;
121 return CSR_64_AllRegs_SaveList;
124 if (Subtarget.isDarwinABI())
126 ? (Subtarget.hasAltivec() ? CSR_Darwin64_Altivec_SaveList
127 : CSR_Darwin64_SaveList)
128 : (Subtarget.hasAltivec() ? CSR_Darwin32_Altivec_SaveList
129 : CSR_Darwin32_SaveList);
131 if (TM.isPPC64() && MF->getInfo<PPCFunctionInfo>()->isSplitCSR())
132 return CSR_SRV464_TLS_PE_SaveList;
134 // On PPC64, we might need to save r2 (but only if it is not reserved).
135 bool SaveR2 = MF->getRegInfo().isAllocatable(PPC::X2);
138 ? (Subtarget.hasAltivec()
139 ? (SaveR2 ? CSR_SVR464_R2_Altivec_SaveList
140 : CSR_SVR464_Altivec_SaveList)
141 : (SaveR2 ? CSR_SVR464_R2_SaveList : CSR_SVR464_SaveList))
142 : (Subtarget.hasAltivec() ? CSR_SVR432_Altivec_SaveList
143 : CSR_SVR432_SaveList);
147 PPCRegisterInfo::getCalleeSavedRegsViaCopy(const MachineFunction *MF) const {
148 assert(MF && "Invalid MachineFunction pointer.");
149 const PPCSubtarget &Subtarget = MF->getSubtarget<PPCSubtarget>();
150 if (Subtarget.isDarwinABI())
154 if (MF->getFunction()->getCallingConv() != CallingConv::CXX_FAST_TLS)
156 if (!MF->getInfo<PPCFunctionInfo>()->isSplitCSR())
159 // On PPC64, we might need to save r2 (but only if it is not reserved).
160 bool SaveR2 = !getReservedRegs(*MF).test(PPC::X2);
161 if (Subtarget.hasAltivec())
163 ? CSR_SVR464_R2_Altivec_ViaCopy_SaveList
164 : CSR_SVR464_Altivec_ViaCopy_SaveList;
167 ? CSR_SVR464_R2_ViaCopy_SaveList
168 : CSR_SVR464_ViaCopy_SaveList;
172 PPCRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
173 CallingConv::ID CC) const {
174 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
175 if (CC == CallingConv::AnyReg) {
176 if (Subtarget.hasVSX())
177 return CSR_64_AllRegs_VSX_RegMask;
178 if (Subtarget.hasAltivec())
179 return CSR_64_AllRegs_Altivec_RegMask;
180 return CSR_64_AllRegs_RegMask;
183 if (Subtarget.isDarwinABI())
184 return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_Darwin64_Altivec_RegMask
185 : CSR_Darwin64_RegMask)
186 : (Subtarget.hasAltivec() ? CSR_Darwin32_Altivec_RegMask
187 : CSR_Darwin32_RegMask);
189 return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_SVR464_Altivec_RegMask
190 : CSR_SVR464_RegMask)
191 : (Subtarget.hasAltivec() ? CSR_SVR432_Altivec_RegMask
192 : CSR_SVR432_RegMask);
196 PPCRegisterInfo::getNoPreservedMask() const {
197 return CSR_NoRegs_RegMask;
200 void PPCRegisterInfo::adjustStackMapLiveOutMask(uint32_t *Mask) const {
201 for (unsigned PseudoReg : {PPC::ZERO, PPC::ZERO8, PPC::RM})
202 Mask[PseudoReg / 32] &= ~(1u << (PseudoReg % 32));
205 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
206 BitVector Reserved(getNumRegs());
207 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
208 const PPCFrameLowering *TFI = getFrameLowering(MF);
210 // The ZERO register is not really a register, but the representation of r0
211 // when used in instructions that treat r0 as the constant 0.
212 Reserved.set(PPC::ZERO);
213 Reserved.set(PPC::ZERO8);
215 // The FP register is also not really a register, but is the representation
216 // of the frame pointer register used by ISD::FRAMEADDR.
217 Reserved.set(PPC::FP);
218 Reserved.set(PPC::FP8);
220 // The BP register is also not really a register, but is the representation
221 // of the base pointer register used by setjmp.
222 Reserved.set(PPC::BP);
223 Reserved.set(PPC::BP8);
225 // The counter registers must be reserved so that counter-based loops can
226 // be correctly formed (and the mtctr instructions are not DCE'd).
227 Reserved.set(PPC::CTR);
228 Reserved.set(PPC::CTR8);
230 Reserved.set(PPC::R1);
231 Reserved.set(PPC::LR);
232 Reserved.set(PPC::LR8);
233 Reserved.set(PPC::RM);
235 if (!Subtarget.isDarwinABI() || !Subtarget.hasAltivec())
236 Reserved.set(PPC::VRSAVE);
238 // The SVR4 ABI reserves r2 and r13
239 if (Subtarget.isSVR4ABI()) {
240 Reserved.set(PPC::R2); // System-reserved register
241 Reserved.set(PPC::R13); // Small Data Area pointer register
244 // On PPC64, r13 is the thread pointer. Never allocate this register.
246 Reserved.set(PPC::R13);
248 Reserved.set(PPC::X1);
249 Reserved.set(PPC::X13);
251 if (TFI->needsFP(MF))
252 Reserved.set(PPC::X31);
254 if (hasBasePointer(MF))
255 Reserved.set(PPC::X30);
257 // The 64-bit SVR4 ABI reserves r2 for the TOC pointer.
258 if (Subtarget.isSVR4ABI()) {
259 // We only reserve r2 if we need to use the TOC pointer. If we have no
260 // explicit uses of the TOC pointer (meaning we're a leaf function with
261 // no constant-pool loads, etc.) and we have no potential uses inside an
262 // inline asm block, then we can treat r2 has an ordinary callee-saved
264 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
265 if (FuncInfo->usesTOCBasePtr() || MF.hasInlineAsm())
266 Reserved.set(PPC::X2);
268 Reserved.reset(PPC::R2);
272 if (TFI->needsFP(MF))
273 Reserved.set(PPC::R31);
275 bool IsPositionIndependent = TM.isPositionIndependent();
276 if (hasBasePointer(MF)) {
277 if (Subtarget.isSVR4ABI() && !TM.isPPC64() && IsPositionIndependent)
278 Reserved.set(PPC::R29);
280 Reserved.set(PPC::R30);
283 if (Subtarget.isSVR4ABI() && !TM.isPPC64() && IsPositionIndependent)
284 Reserved.set(PPC::R30);
286 // Reserve Altivec registers when Altivec is unavailable.
287 if (!Subtarget.hasAltivec())
288 for (TargetRegisterClass::iterator I = PPC::VRRCRegClass.begin(),
289 IE = PPC::VRRCRegClass.end(); I != IE; ++I)
295 unsigned PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
296 MachineFunction &MF) const {
297 const PPCFrameLowering *TFI = getFrameLowering(MF);
298 const unsigned DefaultSafety = 1;
300 switch (RC->getID()) {
303 case PPC::G8RC_NOX0RegClassID:
304 case PPC::GPRC_NOR0RegClassID:
305 case PPC::G8RCRegClassID:
306 case PPC::GPRCRegClassID: {
307 unsigned FP = TFI->hasFP(MF) ? 1 : 0;
308 return 32 - FP - DefaultSafety;
310 case PPC::F8RCRegClassID:
311 case PPC::F4RCRegClassID:
312 case PPC::QFRCRegClassID:
313 case PPC::QSRCRegClassID:
314 case PPC::QBRCRegClassID:
315 case PPC::VRRCRegClassID:
316 case PPC::VFRCRegClassID:
317 case PPC::VSLRCRegClassID:
318 return 32 - DefaultSafety;
319 case PPC::VSRCRegClassID:
320 case PPC::VSFRCRegClassID:
321 case PPC::VSSRCRegClassID:
322 return 64 - DefaultSafety;
323 case PPC::CRRCRegClassID:
324 return 8 - DefaultSafety;
328 const TargetRegisterClass *
329 PPCRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
330 const MachineFunction &MF) const {
331 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
332 if (Subtarget.hasVSX()) {
333 // With VSX, we can inflate various sub-register classes to the full VSX
336 if (RC == &PPC::F8RCRegClass)
337 return &PPC::VSFRCRegClass;
338 else if (RC == &PPC::VRRCRegClass)
339 return &PPC::VSRCRegClass;
340 else if (RC == &PPC::F4RCRegClass && Subtarget.hasP8Vector())
341 return &PPC::VSSRCRegClass;
344 return TargetRegisterInfo::getLargestLegalSuperClass(RC, MF);
347 //===----------------------------------------------------------------------===//
348 // Stack Frame Processing methods
349 //===----------------------------------------------------------------------===//
351 /// lowerDynamicAlloc - Generate the code for allocating an object in the
352 /// current frame. The sequence of code will be in the general form
354 /// addi R0, SP, \#frameSize ; get the address of the previous frame
355 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size
356 /// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation
358 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II) const {
359 // Get the instruction.
360 MachineInstr &MI = *II;
361 // Get the instruction's basic block.
362 MachineBasicBlock &MBB = *MI.getParent();
363 // Get the basic block's function.
364 MachineFunction &MF = *MBB.getParent();
365 // Get the frame info.
366 MachineFrameInfo &MFI = MF.getFrameInfo();
367 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
368 // Get the instruction info.
369 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
370 // Determine whether 64-bit pointers are used.
371 bool LP64 = TM.isPPC64();
372 DebugLoc dl = MI.getDebugLoc();
374 // Get the maximum call stack size.
375 unsigned maxCallFrameSize = MFI.getMaxCallFrameSize();
376 // Get the total frame size.
377 unsigned FrameSize = MFI.getStackSize();
379 // Get stack alignments.
380 const PPCFrameLowering *TFI = getFrameLowering(MF);
381 unsigned TargetAlign = TFI->getStackAlignment();
382 unsigned MaxAlign = MFI.getMaxAlignment();
383 assert((maxCallFrameSize & (MaxAlign-1)) == 0 &&
384 "Maximum call-frame size not sufficiently aligned");
386 // Determine the previous frame's address. If FrameSize can't be
387 // represented as 16 bits or we need special alignment, then we load the
388 // previous frame's address from 0(SP). Why not do an addis of the hi?
389 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero.
390 // Constructing the constant and adding would take 3 instructions.
391 // Fortunately, a frame greater than 32K is rare.
392 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
393 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
394 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
396 if (MaxAlign < TargetAlign && isInt<16>(FrameSize)) {
397 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg)
401 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg)
405 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg)
410 bool KillNegSizeReg = MI.getOperand(1).isKill();
411 unsigned NegSizeReg = MI.getOperand(1).getReg();
413 // Grow the stack and update the stack pointer link, then determine the
414 // address of new allocated space.
416 if (MaxAlign > TargetAlign) {
417 unsigned UnalNegSizeReg = NegSizeReg;
418 NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC);
420 // Unfortunately, there is no andi, only andi., and we can't insert that
421 // here because we might clobber cr0 while it is live.
422 BuildMI(MBB, II, dl, TII.get(PPC::LI8), NegSizeReg)
423 .addImm(~(MaxAlign-1));
425 unsigned NegSizeReg1 = NegSizeReg;
426 NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC);
427 BuildMI(MBB, II, dl, TII.get(PPC::AND8), NegSizeReg)
428 .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg))
429 .addReg(NegSizeReg1, RegState::Kill);
430 KillNegSizeReg = true;
433 BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1)
434 .addReg(Reg, RegState::Kill)
436 .addReg(NegSizeReg, getKillRegState(KillNegSizeReg));
437 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
439 .addImm(maxCallFrameSize);
441 if (MaxAlign > TargetAlign) {
442 unsigned UnalNegSizeReg = NegSizeReg;
443 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC);
445 // Unfortunately, there is no andi, only andi., and we can't insert that
446 // here because we might clobber cr0 while it is live.
447 BuildMI(MBB, II, dl, TII.get(PPC::LI), NegSizeReg)
448 .addImm(~(MaxAlign-1));
450 unsigned NegSizeReg1 = NegSizeReg;
451 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC);
452 BuildMI(MBB, II, dl, TII.get(PPC::AND), NegSizeReg)
453 .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg))
454 .addReg(NegSizeReg1, RegState::Kill);
455 KillNegSizeReg = true;
458 BuildMI(MBB, II, dl, TII.get(PPC::STWUX), PPC::R1)
459 .addReg(Reg, RegState::Kill)
461 .addReg(NegSizeReg, getKillRegState(KillNegSizeReg));
462 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
464 .addImm(maxCallFrameSize);
467 // Discard the DYNALLOC instruction.
471 void PPCRegisterInfo::lowerDynamicAreaOffset(
472 MachineBasicBlock::iterator II) const {
473 // Get the instruction.
474 MachineInstr &MI = *II;
475 // Get the instruction's basic block.
476 MachineBasicBlock &MBB = *MI.getParent();
477 // Get the basic block's function.
478 MachineFunction &MF = *MBB.getParent();
479 // Get the frame info.
480 MachineFrameInfo &MFI = MF.getFrameInfo();
481 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
482 // Get the instruction info.
483 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
485 unsigned maxCallFrameSize = MFI.getMaxCallFrameSize();
486 DebugLoc dl = MI.getDebugLoc();
487 BuildMI(MBB, II, dl, TII.get(PPC::LI), MI.getOperand(0).getReg())
488 .addImm(maxCallFrameSize);
492 /// lowerCRSpilling - Generate the code for spilling a CR register. Instead of
493 /// reserving a whole register (R0), we scrounge for one here. This generates
496 /// mfcr rA ; Move the conditional register into GPR rA.
497 /// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot.
498 /// stw rA, FI ; Store rA to the frame.
500 void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II,
501 unsigned FrameIndex) const {
502 // Get the instruction.
503 MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset>
504 // Get the instruction's basic block.
505 MachineBasicBlock &MBB = *MI.getParent();
506 MachineFunction &MF = *MBB.getParent();
507 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
508 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
509 DebugLoc dl = MI.getDebugLoc();
511 bool LP64 = TM.isPPC64();
512 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
513 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
515 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
516 unsigned SrcReg = MI.getOperand(0).getReg();
518 // We need to store the CR in the low 4-bits of the saved value. First, issue
519 // an MFOCRF to save all of the CRBits and, if needed, kill the SrcReg.
520 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg)
521 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
523 // If the saved register wasn't CR0, shift the bits left so that they are in
525 if (SrcReg != PPC::CR0) {
527 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
529 // rlwinm rA, rA, ShiftBits, 0, 31.
530 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
531 .addReg(Reg1, RegState::Kill)
532 .addImm(getEncodingValue(SrcReg) * 4)
537 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW))
538 .addReg(Reg, RegState::Kill),
541 // Discard the pseudo instruction.
545 void PPCRegisterInfo::lowerCRRestore(MachineBasicBlock::iterator II,
546 unsigned FrameIndex) const {
547 // Get the instruction.
548 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CR <offset>
549 // Get the instruction's basic block.
550 MachineBasicBlock &MBB = *MI.getParent();
551 MachineFunction &MF = *MBB.getParent();
552 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
553 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
554 DebugLoc dl = MI.getDebugLoc();
556 bool LP64 = TM.isPPC64();
557 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
558 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
560 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
561 unsigned DestReg = MI.getOperand(0).getReg();
562 assert(MI.definesRegister(DestReg) &&
563 "RESTORE_CR does not define its destination");
565 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ),
568 // If the reloaded register isn't CR0, shift the bits right so that they are
569 // in the right CR's slot.
570 if (DestReg != PPC::CR0) {
572 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
574 unsigned ShiftBits = getEncodingValue(DestReg)*4;
575 // rlwinm r11, r11, 32-ShiftBits, 0, 31.
576 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
577 .addReg(Reg1, RegState::Kill).addImm(32-ShiftBits).addImm(0)
581 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF), DestReg)
582 .addReg(Reg, RegState::Kill);
584 // Discard the pseudo instruction.
588 void PPCRegisterInfo::lowerCRBitSpilling(MachineBasicBlock::iterator II,
589 unsigned FrameIndex) const {
590 // Get the instruction.
591 MachineInstr &MI = *II; // ; SPILL_CRBIT <SrcReg>, <offset>
592 // Get the instruction's basic block.
593 MachineBasicBlock &MBB = *MI.getParent();
594 MachineFunction &MF = *MBB.getParent();
595 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
596 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
597 DebugLoc dl = MI.getDebugLoc();
599 bool LP64 = TM.isPPC64();
600 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
601 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
603 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
604 unsigned SrcReg = MI.getOperand(0).getReg();
606 BuildMI(MBB, II, dl, TII.get(TargetOpcode::KILL),
607 getCRFromCRBit(SrcReg))
608 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
610 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg)
611 .addReg(getCRFromCRBit(SrcReg));
613 // If the saved register wasn't CR0LT, shift the bits left so that the bit to
614 // store is the first one. Mask all but that bit.
616 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
618 // rlwinm rA, rA, ShiftBits, 0, 0.
619 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
620 .addReg(Reg1, RegState::Kill)
621 .addImm(getEncodingValue(SrcReg))
622 .addImm(0).addImm(0);
624 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW))
625 .addReg(Reg, RegState::Kill),
628 // Discard the pseudo instruction.
632 void PPCRegisterInfo::lowerCRBitRestore(MachineBasicBlock::iterator II,
633 unsigned FrameIndex) const {
634 // Get the instruction.
635 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CRBIT <offset>
636 // Get the instruction's basic block.
637 MachineBasicBlock &MBB = *MI.getParent();
638 MachineFunction &MF = *MBB.getParent();
639 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
640 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
641 DebugLoc dl = MI.getDebugLoc();
643 bool LP64 = TM.isPPC64();
644 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
645 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
647 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
648 unsigned DestReg = MI.getOperand(0).getReg();
649 assert(MI.definesRegister(DestReg) &&
650 "RESTORE_CRBIT does not define its destination");
652 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ),
655 BuildMI(MBB, II, dl, TII.get(TargetOpcode::IMPLICIT_DEF), DestReg);
657 unsigned RegO = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
658 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), RegO)
659 .addReg(getCRFromCRBit(DestReg));
661 unsigned ShiftBits = getEncodingValue(DestReg);
662 // rlwimi r11, r10, 32-ShiftBits, ..., ...
663 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWIMI8 : PPC::RLWIMI), RegO)
664 .addReg(RegO, RegState::Kill)
665 .addReg(Reg, RegState::Kill)
666 .addImm(ShiftBits ? 32 - ShiftBits : 0)
670 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF),
671 getCRFromCRBit(DestReg))
672 .addReg(RegO, RegState::Kill)
673 // Make sure we have a use dependency all the way through this
674 // sequence of instructions. We can't have the other bits in the CR
675 // modified in between the mfocrf and the mtocrf.
676 .addReg(getCRFromCRBit(DestReg), RegState::Implicit);
678 // Discard the pseudo instruction.
682 void PPCRegisterInfo::lowerVRSAVESpilling(MachineBasicBlock::iterator II,
683 unsigned FrameIndex) const {
684 // Get the instruction.
685 MachineInstr &MI = *II; // ; SPILL_VRSAVE <SrcReg>, <offset>
686 // Get the instruction's basic block.
687 MachineBasicBlock &MBB = *MI.getParent();
688 MachineFunction &MF = *MBB.getParent();
689 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
690 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
691 DebugLoc dl = MI.getDebugLoc();
693 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
694 unsigned Reg = MF.getRegInfo().createVirtualRegister(GPRC);
695 unsigned SrcReg = MI.getOperand(0).getReg();
697 BuildMI(MBB, II, dl, TII.get(PPC::MFVRSAVEv), Reg)
698 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
701 BuildMI(MBB, II, dl, TII.get(PPC::STW)).addReg(Reg, RegState::Kill),
704 // Discard the pseudo instruction.
708 void PPCRegisterInfo::lowerVRSAVERestore(MachineBasicBlock::iterator II,
709 unsigned FrameIndex) const {
710 // Get the instruction.
711 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_VRSAVE <offset>
712 // Get the instruction's basic block.
713 MachineBasicBlock &MBB = *MI.getParent();
714 MachineFunction &MF = *MBB.getParent();
715 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
716 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
717 DebugLoc dl = MI.getDebugLoc();
719 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
720 unsigned Reg = MF.getRegInfo().createVirtualRegister(GPRC);
721 unsigned DestReg = MI.getOperand(0).getReg();
722 assert(MI.definesRegister(DestReg) &&
723 "RESTORE_VRSAVE does not define its destination");
725 addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::LWZ),
728 BuildMI(MBB, II, dl, TII.get(PPC::MTVRSAVEv), DestReg)
729 .addReg(Reg, RegState::Kill);
731 // Discard the pseudo instruction.
735 bool PPCRegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
736 unsigned Reg, int &FrameIdx) const {
737 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
738 // For the nonvolatile condition registers (CR2, CR3, CR4) in an SVR4
739 // ABI, return true to prevent allocating an additional frame slot.
740 // For 64-bit, the CR save area is at SP+8; the value of FrameIdx = 0
741 // is arbitrary and will be subsequently ignored. For 32-bit, we have
742 // previously created the stack slot if needed, so return its FrameIdx.
743 if (Subtarget.isSVR4ABI() && PPC::CR2 <= Reg && Reg <= PPC::CR4) {
747 const PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
748 FrameIdx = FI->getCRSpillFrameIndex();
755 // Figure out if the offset in the instruction must be a multiple of 4.
756 // This is true for instructions like "STD".
757 static bool usesIXAddr(const MachineInstr &MI) {
758 unsigned OpC = MI.getOpcode();
771 // Return the OffsetOperandNo given the FIOperandNum (and the instruction).
772 static unsigned getOffsetONFromFION(const MachineInstr &MI,
773 unsigned FIOperandNum) {
774 // Take into account whether it's an add or mem instruction
775 unsigned OffsetOperandNo = (FIOperandNum == 2) ? 1 : 2;
776 if (MI.isInlineAsm())
777 OffsetOperandNo = FIOperandNum - 1;
778 else if (MI.getOpcode() == TargetOpcode::STACKMAP ||
779 MI.getOpcode() == TargetOpcode::PATCHPOINT)
780 OffsetOperandNo = FIOperandNum + 1;
782 return OffsetOperandNo;
786 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
787 int SPAdj, unsigned FIOperandNum,
788 RegScavenger *RS) const {
789 assert(SPAdj == 0 && "Unexpected");
791 // Get the instruction.
792 MachineInstr &MI = *II;
793 // Get the instruction's basic block.
794 MachineBasicBlock &MBB = *MI.getParent();
795 // Get the basic block's function.
796 MachineFunction &MF = *MBB.getParent();
797 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
798 // Get the instruction info.
799 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
800 // Get the frame info.
801 MachineFrameInfo &MFI = MF.getFrameInfo();
802 DebugLoc dl = MI.getDebugLoc();
804 unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum);
806 // Get the frame index.
807 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
809 // Get the frame pointer save index. Users of this index are primarily
810 // DYNALLOC instructions.
811 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
812 int FPSI = FI->getFramePointerSaveIndex();
813 // Get the instruction opcode.
814 unsigned OpC = MI.getOpcode();
816 if ((OpC == PPC::DYNAREAOFFSET || OpC == PPC::DYNAREAOFFSET8)) {
817 lowerDynamicAreaOffset(II);
821 // Special case for dynamic alloca.
822 if (FPSI && FrameIndex == FPSI &&
823 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) {
824 lowerDynamicAlloc(II);
828 // Special case for pseudo-ops SPILL_CR and RESTORE_CR, etc.
829 if (OpC == PPC::SPILL_CR) {
830 lowerCRSpilling(II, FrameIndex);
832 } else if (OpC == PPC::RESTORE_CR) {
833 lowerCRRestore(II, FrameIndex);
835 } else if (OpC == PPC::SPILL_CRBIT) {
836 lowerCRBitSpilling(II, FrameIndex);
838 } else if (OpC == PPC::RESTORE_CRBIT) {
839 lowerCRBitRestore(II, FrameIndex);
841 } else if (OpC == PPC::SPILL_VRSAVE) {
842 lowerVRSAVESpilling(II, FrameIndex);
844 } else if (OpC == PPC::RESTORE_VRSAVE) {
845 lowerVRSAVERestore(II, FrameIndex);
849 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
850 MI.getOperand(FIOperandNum).ChangeToRegister(
851 FrameIndex < 0 ? getBaseRegister(MF) : getFrameRegister(MF), false);
853 // Figure out if the offset in the instruction is shifted right two bits.
854 bool isIXAddr = usesIXAddr(MI);
856 // If the instruction is not present in ImmToIdxMap, then it has no immediate
857 // form (and must be r+r).
858 bool noImmForm = !MI.isInlineAsm() && OpC != TargetOpcode::STACKMAP &&
859 OpC != TargetOpcode::PATCHPOINT && !ImmToIdxMap.count(OpC);
861 // Now add the frame object offset to the offset from r1.
862 int Offset = MFI.getObjectOffset(FrameIndex);
863 Offset += MI.getOperand(OffsetOperandNo).getImm();
865 // If we're not using a Frame Pointer that has been set to the value of the
866 // SP before having the stack size subtracted from it, then add the stack size
867 // to Offset to get the correct offset.
868 // Naked functions have stack size 0, although getStackSize may not reflect
869 // that because we didn't call all the pieces that compute it for naked
871 if (!MF.getFunction()->hasFnAttribute(Attribute::Naked)) {
872 if (!(hasBasePointer(MF) && FrameIndex < 0))
873 Offset += MFI.getStackSize();
876 // If we can, encode the offset directly into the instruction. If this is a
877 // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If
878 // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits
879 // clear can be encoded. This is extremely uncommon, because normally you
880 // only "std" to a stack slot that is at least 4-byte aligned, but it can
881 // happen in invalid code.
882 assert(OpC != PPC::DBG_VALUE &&
883 "This should be handled in a target-independent way");
884 if (!noImmForm && ((isInt<16>(Offset) && (!isIXAddr || (Offset & 3) == 0)) ||
885 OpC == TargetOpcode::STACKMAP ||
886 OpC == TargetOpcode::PATCHPOINT)) {
887 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
891 // The offset doesn't fit into a single register, scavenge one to build the
894 bool is64Bit = TM.isPPC64();
895 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
896 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
897 const TargetRegisterClass *RC = is64Bit ? G8RC : GPRC;
898 unsigned SRegHi = MF.getRegInfo().createVirtualRegister(RC),
899 SReg = MF.getRegInfo().createVirtualRegister(RC);
901 // Insert a set of rA with the full offset value before the ld, st, or add
902 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LIS8 : PPC::LIS), SRegHi)
903 .addImm(Offset >> 16);
904 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg)
905 .addReg(SRegHi, RegState::Kill)
908 // Convert into indexed form of the instruction:
910 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
911 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
912 unsigned OperandBase;
916 else if (OpC != TargetOpcode::INLINEASM) {
917 assert(ImmToIdxMap.count(OpC) &&
918 "No indexed form of load or store available!");
919 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second;
920 MI.setDesc(TII.get(NewOpcode));
923 OperandBase = OffsetOperandNo;
926 unsigned StackReg = MI.getOperand(FIOperandNum).getReg();
927 MI.getOperand(OperandBase).ChangeToRegister(StackReg, false);
928 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false, false, true);
931 unsigned PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
932 const PPCFrameLowering *TFI = getFrameLowering(MF);
935 return TFI->hasFP(MF) ? PPC::R31 : PPC::R1;
937 return TFI->hasFP(MF) ? PPC::X31 : PPC::X1;
940 unsigned PPCRegisterInfo::getBaseRegister(const MachineFunction &MF) const {
941 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
942 if (!hasBasePointer(MF))
943 return getFrameRegister(MF);
948 if (Subtarget.isSVR4ABI() && TM.isPositionIndependent())
954 bool PPCRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
955 if (!EnableBasePointer)
957 if (AlwaysBasePointer)
960 // If we need to realign the stack, then the stack pointer can no longer
961 // serve as an offset into the caller's stack space. As a result, we need a
963 return needsStackRealignment(MF);
966 /// Returns true if the instruction's frame index
967 /// reference would be better served by a base register other than FP
968 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
969 /// references it should create new base registers for.
970 bool PPCRegisterInfo::
971 needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
972 assert(Offset < 0 && "Local offset must be negative");
974 // It's the load/store FI references that cause issues, as it can be difficult
975 // to materialize the offset if it won't fit in the literal field. Estimate
976 // based on the size of the local frame and some conservative assumptions
977 // about the rest of the stack frame (note, this is pre-regalloc, so
978 // we don't know everything for certain yet) whether this offset is likely
979 // to be out of range of the immediate. Return true if so.
981 // We only generate virtual base registers for loads and stores that have
982 // an r+i form. Return false for everything else.
983 unsigned OpC = MI->getOpcode();
984 if (!ImmToIdxMap.count(OpC))
987 // Don't generate a new virtual base register just to add zero to it.
988 if ((OpC == PPC::ADDI || OpC == PPC::ADDI8) &&
989 MI->getOperand(2).getImm() == 0)
992 MachineBasicBlock &MBB = *MI->getParent();
993 MachineFunction &MF = *MBB.getParent();
994 const PPCFrameLowering *TFI = getFrameLowering(MF);
995 unsigned StackEst = TFI->determineFrameLayout(MF, false, true);
997 // If we likely don't need a stack frame, then we probably don't need a
998 // virtual base register either.
1002 // Estimate an offset from the stack pointer.
1003 // The incoming offset is relating to the SP at the start of the function,
1004 // but when we access the local it'll be relative to the SP after local
1005 // allocation, so adjust our SP-relative offset by that allocation size.
1008 // The frame pointer will point to the end of the stack, so estimate the
1009 // offset as the difference between the object offset and the FP location.
1010 return !isFrameOffsetLegal(MI, getBaseRegister(MF), Offset);
1013 /// Insert defining instruction(s) for BaseReg to
1014 /// be a pointer to FrameIdx at the beginning of the basic block.
1015 void PPCRegisterInfo::
1016 materializeFrameBaseRegister(MachineBasicBlock *MBB,
1017 unsigned BaseReg, int FrameIdx,
1018 int64_t Offset) const {
1019 unsigned ADDriOpc = TM.isPPC64() ? PPC::ADDI8 : PPC::ADDI;
1021 MachineBasicBlock::iterator Ins = MBB->begin();
1022 DebugLoc DL; // Defaults to "unknown"
1023 if (Ins != MBB->end())
1024 DL = Ins->getDebugLoc();
1026 const MachineFunction &MF = *MBB->getParent();
1027 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1028 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1029 const MCInstrDesc &MCID = TII.get(ADDriOpc);
1030 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
1031 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
1033 BuildMI(*MBB, Ins, DL, MCID, BaseReg)
1034 .addFrameIndex(FrameIdx).addImm(Offset);
1037 void PPCRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
1038 int64_t Offset) const {
1039 unsigned FIOperandNum = 0;
1040 while (!MI.getOperand(FIOperandNum).isFI()) {
1042 assert(FIOperandNum < MI.getNumOperands() &&
1043 "Instr doesn't have FrameIndex operand!");
1046 MI.getOperand(FIOperandNum).ChangeToRegister(BaseReg, false);
1047 unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum);
1048 Offset += MI.getOperand(OffsetOperandNo).getImm();
1049 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
1051 MachineBasicBlock &MBB = *MI.getParent();
1052 MachineFunction &MF = *MBB.getParent();
1053 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1054 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1055 const MCInstrDesc &MCID = MI.getDesc();
1056 MachineRegisterInfo &MRI = MF.getRegInfo();
1057 MRI.constrainRegClass(BaseReg,
1058 TII.getRegClass(MCID, FIOperandNum, this, MF));
1061 bool PPCRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
1063 int64_t Offset) const {
1064 unsigned FIOperandNum = 0;
1065 while (!MI->getOperand(FIOperandNum).isFI()) {
1067 assert(FIOperandNum < MI->getNumOperands() &&
1068 "Instr doesn't have FrameIndex operand!");
1071 unsigned OffsetOperandNo = getOffsetONFromFION(*MI, FIOperandNum);
1072 Offset += MI->getOperand(OffsetOperandNo).getImm();
1074 return MI->getOpcode() == PPC::DBG_VALUE || // DBG_VALUE is always Reg+Imm
1075 MI->getOpcode() == TargetOpcode::STACKMAP ||
1076 MI->getOpcode() == TargetOpcode::PATCHPOINT ||
1077 (isInt<16>(Offset) && (!usesIXAddr(*MI) || (Offset & 3) == 0));