contrib/llvm/lib/Target/PowerPC/PPCScheduleP7.td

   1 //===-- PPCScheduleP7.td - PPC P7 Scheduling Definitions ---*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the itinerary class data for the POWER7 processor.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 // Primary reference:
  15 // IBM POWER7 multicore server processor
  16 // B. Sinharoy, et al.
  17 // IBM J. Res. & Dev. (55) 3. May/June 2011.
  18
  19 // Scheduling for the P7 involves tracking two types of resources:
  20 //  1. The dispatch bundle slots
  21 //  2. The functional unit resources
  22
  23 // Dispatch units:
  24 def P7_DU1    : FuncUnit;
  25 def P7_DU2    : FuncUnit;
  26 def P7_DU3    : FuncUnit;
  27 def P7_DU4    : FuncUnit;
  28 def P7_DU5    : FuncUnit;
  29 def P7_DU6    : FuncUnit;
  30
  31 def P7_LS1    : FuncUnit; // Load/Store pipeline 1
  32 def P7_LS2    : FuncUnit; // Load/Store pipeline 2
  33
  34 def P7_FX1    : FuncUnit; // FX pipeline 1
  35 def P7_FX2    : FuncUnit; // FX pipeline 2
  36
  37 // VS pipeline 1 (vector integer ops. always here)
  38 def P7_VS1    : FuncUnit; // VS pipeline 1
  39 // VS pipeline 2 (128-bit stores and perms. here)
  40 def P7_VS2    : FuncUnit; // VS pipeline 2
  41
  42 def P7_CRU    : FuncUnit; // CR unit (CR logicals and move-from-SPRs)
  43 def P7_BRU    : FuncUnit; // BR unit
  44
  45 // Notes:
  46 // Each LSU pipeline can also execute FX add and logical instructions.
  47 // Each LSU pipeline can complete a load or store in one cycle.
  48 //
  49 // Each store is broken into two parts, AGEN goes to the LSU while a
  50 // "data steering" op. goes to the FXU or VSU.
  51 //
  52 // FX loads have a two cycle load-to-use latency (so one "bubble" cycle).
  53 // VSU loads have a three cycle load-to-use latency (so two "bubble" cycle).
  54 //
  55 // Frequent FX ops. take only one cycle and results can be used again in the
  56 // next cycle (there is a self-bypass). Getting results from the other FX
  57 // pipeline takes an additional cycle.
  58 //
  59 // The VSU XS is similar to the POWER6, but with a pipeline length of 2 cycles
  60 // (instead of 3 cycles on the POWER6). VSU XS handles vector FX-style ops.
  61 // Dispatch of an instruction to VS1 that uses four single prec. inputs
  62 // (either to a float or XC op). prevents dispatch in that cycle to VS2 of any
  63 // floating point instruction.
  64 //
  65 // The VSU PM is similar to the POWER6, but with a pipeline length of 3 cycles
  66 // (instead of 4 cycles on the POWER6). vsel is handled by the PM pipeline
  67 // (unlike on the POWER6).
  68 //
  69 // FMA from the VSUs can forward results in 6 cycles. VS1 XS and vector FP
  70 // share the same write-back, and have a 5-cycle latency difference, so the
  71 // IFU/IDU will not dispatch an XS instructon 5 cycles after a vector FP
  72 // op. has been dispatched to VS1.
  73 //
  74 // Three cycles after an L1 cache hit, a dependent VSU instruction can issue.
  75 //
  76 // Instruction dispatch groups have (at most) four non-branch instructions, and
  77 // two branches. Unlike on the POWER4/5, a branch does not automatically
  78 // end the dispatch group, but a second branch must be the last in the group.
  79
  80 def P7Itineraries : ProcessorItineraries<
  81   [P7_DU1, P7_DU2, P7_DU3, P7_DU4, P7_DU5, P7_DU6,
  82    P7_LS1, P7_LS2, P7_FX1, P7_FX2, P7_VS1, P7_VS2, P7_CRU, P7_BRU], [], [
  83   InstrItinData<IIC_IntSimple   , [InstrStage<1, [P7_DU1, P7_DU2,
  84                                                   P7_DU3, P7_DU4], 0>,
  85                                    InstrStage<1, [P7_FX1, P7_FX2,
  86                                                   P7_LS1, P7_LS2]>],
  87                                   [1, 1, 1]>,
  88   InstrItinData<IIC_IntGeneral  , [InstrStage<1, [P7_DU1, P7_DU2,
  89                                                   P7_DU3, P7_DU4], 0>,
  90                                    InstrStage<1, [P7_FX1, P7_FX2]>],
  91                                   [1, 1, 1]>,
  92   InstrItinData<IIC_IntISEL,      [InstrStage<1, [P7_DU1], 0>,
  93                                    InstrStage<1, [P7_FX1, P7_FX2], 0>,
  94                                    InstrStage<1, [P7_BRU]>],
  95                                   [1, 1, 1, 1]>,
  96   InstrItinData<IIC_IntCompare  , [InstrStage<1, [P7_DU1, P7_DU2,
  97                                                   P7_DU3, P7_DU4], 0>,
  98                                    InstrStage<1, [P7_FX1, P7_FX2]>],
  99                                   [1, 1, 1]>,
 100   // FIXME: Add record-form itinerary data.
 101   InstrItinData<IIC_IntDivW     , [InstrStage<1, [P7_DU1], 0>,
 102                                    InstrStage<1, [P7_DU2], 0>,
 103                                    InstrStage<36, [P7_FX1, P7_FX2]>],
 104                                   [36, 1, 1]>,
 105   InstrItinData<IIC_IntDivD     , [InstrStage<1, [P7_DU1], 0>,
 106                                    InstrStage<1, [P7_DU2], 0>,
 107                                    InstrStage<68, [P7_FX1, P7_FX2]>],
 108                                   [68, 1, 1]>,
 109   InstrItinData<IIC_IntMulHW    , [InstrStage<1, [P7_DU1, P7_DU2,
 110                                                   P7_DU3, P7_DU4], 0>,
 111                                    InstrStage<1, [P7_FX1, P7_FX2]>],
 112                                   [4, 1, 1]>,
 113   InstrItinData<IIC_IntMulHWU   , [InstrStage<1, [P7_DU1, P7_DU2,
 114                                                   P7_DU3, P7_DU4], 0>,
 115                                    InstrStage<1, [P7_FX1, P7_FX2]>],
 116                                   [4, 1, 1]>,
 117   InstrItinData<IIC_IntMulHD    , [InstrStage<1, [P7_DU1, P7_DU2,
 118                                                   P7_DU3, P7_DU4], 0>,
 119                                    InstrStage<1, [P7_FX1, P7_FX2]>],
 120                                   [4, 1, 1]>,
 121   InstrItinData<IIC_IntMulLI    , [InstrStage<1, [P7_DU1, P7_DU2,
 122                                                   P7_DU3, P7_DU4], 0>,
 123                                    InstrStage<1, [P7_FX1, P7_FX2]>],
 124                                   [4, 1, 1]>,
 125   InstrItinData<IIC_IntRotate   , [InstrStage<1, [P7_DU1, P7_DU2,
 126                                                   P7_DU3, P7_DU4], 0>,
 127                                    InstrStage<1, [P7_FX1, P7_FX2]>],
 128                                    [1, 1, 1]>,
 129   InstrItinData<IIC_IntRotateD  , [InstrStage<1, [P7_DU1, P7_DU2,
 130                                                   P7_DU3, P7_DU4], 0>,
 131                                    InstrStage<1, [P7_FX1, P7_FX2]>],
 132                                    [1, 1, 1]>,
 133   InstrItinData<IIC_IntRotateDI , [InstrStage<1, [P7_DU1, P7_DU2,
 134                                                   P7_DU3, P7_DU4], 0>,
 135                                    InstrStage<1, [P7_FX1, P7_FX2]>],
 136                                    [1, 1, 1]>,
 137   InstrItinData<IIC_IntShift    , [InstrStage<1, [P7_DU1, P7_DU2,
 138                                                   P7_DU3, P7_DU4], 0>,
 139                                    InstrStage<1, [P7_FX1, P7_FX2]>],
 140                                   [1, 1, 1]>,
 141   InstrItinData<IIC_IntTrapW    , [InstrStage<1, [P7_DU1, P7_DU2,
 142                                                   P7_DU3, P7_DU4], 0>,
 143                                    InstrStage<1, [P7_FX1, P7_FX2]>],
 144                                   [1, 1]>,
 145   InstrItinData<IIC_IntTrapD    , [InstrStage<1, [P7_DU1, P7_DU2,
 146                                                   P7_DU3, P7_DU4], 0>,
 147                                    InstrStage<1, [P7_FX1, P7_FX2]>],
 148                                   [1, 1]>,
 149   InstrItinData<IIC_BrB         , [InstrStage<1, [P7_DU5, P7_DU6], 0>,
 150                                    InstrStage<1, [P7_BRU]>],
 151                                   [3, 1, 1]>,
 152   InstrItinData<IIC_BrCR        , [InstrStage<1, [P7_DU1], 0>,
 153                                    InstrStage<1, [P7_CRU]>],
 154                                   [3, 1, 1]>,
 155   InstrItinData<IIC_BrMCR       , [InstrStage<1, [P7_DU5, P7_DU6], 0>,
 156                                    InstrStage<1, [P7_BRU]>],
 157                                   [3, 1, 1]>,
 158   InstrItinData<IIC_BrMCRX      , [InstrStage<1, [P7_DU5, P7_DU6], 0>,
 159                                    InstrStage<1, [P7_BRU]>],
 160                                   [3, 1, 1]>,
 161   InstrItinData<IIC_LdStLoad    , [InstrStage<1, [P7_DU1, P7_DU2,
 162                                                   P7_DU3, P7_DU4], 0>,
 163                                    InstrStage<1, [P7_LS1, P7_LS2]>],
 164                                   [2, 1, 1]>,
 165   InstrItinData<IIC_LdStLoadUpd , [InstrStage<1, [P7_DU1], 0>,
 166                                    InstrStage<1, [P7_DU2], 0>,
 167                                    InstrStage<1, [P7_LS1, P7_LS2], 0>,
 168                                    InstrStage<1, [P7_FX1, P7_FX2]>],
 169                                   [2, 2, 1, 1]>,
 170   InstrItinData<IIC_LdStLoadUpdX, [InstrStage<1, [P7_DU1], 0>,
 171                                    InstrStage<1, [P7_DU2], 0>,
 172                                    InstrStage<1, [P7_DU3], 0>,
 173                                    InstrStage<1, [P7_DU4], 0>,
 174                                    InstrStage<1, [P7_FX1, P7_FX2]>,
 175                                    InstrStage<1, [P7_LS1, P7_LS2], 0>,
 176                                    InstrStage<1, [P7_FX1, P7_FX2]>],
 177                                   [3, 3, 1, 1]>,
 178   InstrItinData<IIC_LdStLD      , [InstrStage<1, [P7_DU1, P7_DU2,
 179                                                   P7_DU3, P7_DU4], 0>,
 180                                    InstrStage<1, [P7_LS1, P7_LS2]>],
 181                                   [2, 1, 1]>,
 182   InstrItinData<IIC_LdStLDU     , [InstrStage<1, [P7_DU1], 0>,
 183                                    InstrStage<1, [P7_DU2], 0>,
 184                                    InstrStage<1, [P7_LS1, P7_LS2], 0>,
 185                                    InstrStage<1, [P7_FX1, P7_FX2]>],
 186                                   [2, 2, 1, 1]>,
 187   InstrItinData<IIC_LdStLDUX    , [InstrStage<1, [P7_DU1], 0>,
 188                                    InstrStage<1, [P7_DU2], 0>,
 189                                    InstrStage<1, [P7_DU3], 0>,
 190                                    InstrStage<1, [P7_DU4], 0>,
 191                                    InstrStage<1, [P7_FX1, P7_FX2]>,
 192                                    InstrStage<1, [P7_LS1, P7_LS2], 0>,
 193                                    InstrStage<1, [P7_FX1, P7_FX2]>],
 194                                   [3, 3, 1, 1]>,
 195   InstrItinData<IIC_LdStLFD     , [InstrStage<1, [P7_DU1, P7_DU2,
 196                                                   P7_DU3, P7_DU4], 0>,
 197                                    InstrStage<1, [P7_LS1, P7_LS2]>],
 198                                   [3, 1, 1]>,
 199   InstrItinData<IIC_LdStLVecX   , [InstrStage<1, [P7_DU1, P7_DU2,
 200                                                   P7_DU3, P7_DU4], 0>,
 201                                    InstrStage<1, [P7_LS1, P7_LS2]>],
 202                                   [3, 1, 1]>,
 203   InstrItinData<IIC_LdStLFDU    , [InstrStage<1, [P7_DU1], 0>,
 204                                    InstrStage<1, [P7_DU2], 0>,
 205                                    InstrStage<1, [P7_LS1, P7_LS2], 0>,
 206                                    InstrStage<1, [P7_FX1, P7_FX2]>],
 207                                   [3, 3, 1, 1]>,
 208   InstrItinData<IIC_LdStLFDUX   , [InstrStage<1, [P7_DU1], 0>,
 209                                    InstrStage<1, [P7_DU2], 0>,
 210                                    InstrStage<1, [P7_LS1, P7_LS2], 0>,
 211                                    InstrStage<1, [P7_FX1, P7_FX2]>],
 212                                   [3, 3, 1, 1]>,
 213   InstrItinData<IIC_LdStLHA     , [InstrStage<1, [P7_DU1], 0>,
 214                                    InstrStage<1, [P7_DU2], 0>,
 215                                    InstrStage<1, [P7_LS1, P7_LS2]>,
 216                                    InstrStage<1, [P7_FX1, P7_FX2]>],
 217                                   [3, 1, 1]>,
 218   InstrItinData<IIC_LdStLHAU    , [InstrStage<1, [P7_DU1], 0>,
 219                                    InstrStage<1, [P7_DU2], 0>,
 220                                    InstrStage<1, [P7_LS1, P7_LS2], 0>,
 221                                    InstrStage<1, [P7_FX1, P7_FX2]>,
 222                                    InstrStage<1, [P7_FX1, P7_FX2]>],
 223                                   [4, 4, 1, 1]>,
 224   InstrItinData<IIC_LdStLHAUX   , [InstrStage<1, [P7_DU1], 0>,
 225                                    InstrStage<1, [P7_DU2], 0>,
 226                                    InstrStage<1, [P7_DU3], 0>,
 227                                    InstrStage<1, [P7_DU4], 0>,
 228                                    InstrStage<1, [P7_FX1, P7_FX2]>,
 229                                    InstrStage<1, [P7_LS1, P7_LS2], 0>,
 230                                    InstrStage<1, [P7_FX1, P7_FX2]>,
 231                                    InstrStage<1, [P7_FX1, P7_FX2]>],
 232                                   [4, 4, 1, 1]>,
 233   InstrItinData<IIC_LdStLWA     , [InstrStage<1, [P7_DU1], 0>,
 234                                    InstrStage<1, [P7_DU2], 0>,
 235                                    InstrStage<1, [P7_LS1, P7_LS2]>,
 236                                    InstrStage<1, [P7_FX1, P7_FX2]>],
 237                                   [3, 1, 1]>,
 238   InstrItinData<IIC_LdStLWARX,    [InstrStage<1, [P7_DU1], 0>,
 239                                    InstrStage<1, [P7_DU2], 0>,
 240                                    InstrStage<1, [P7_DU3], 0>,
 241                                    InstrStage<1, [P7_DU4], 0>,
 242                                    InstrStage<1, [P7_LS1, P7_LS2]>],
 243                                   [3, 1, 1]>,
 244   InstrItinData<IIC_LdStLDARX,    [InstrStage<1, [P7_DU1], 0>,
 245                                    InstrStage<1, [P7_DU2], 0>,
 246                                    InstrStage<1, [P7_DU3], 0>,
 247                                    InstrStage<1, [P7_DU4], 0>,
 248                                    InstrStage<1, [P7_LS1, P7_LS2]>],
 249                                   [3, 1, 1]>,
 250   InstrItinData<IIC_LdStLMW     , [InstrStage<1, [P7_DU1, P7_DU2,
 251                                                   P7_DU3, P7_DU4], 0>,
 252                                    InstrStage<1, [P7_LS1, P7_LS2]>],
 253                                   [2, 1, 1]>,
 254   InstrItinData<IIC_LdStStore   , [InstrStage<1, [P7_DU1, P7_DU2,
 255                                                   P7_DU3, P7_DU4], 0>,
 256                                    InstrStage<1, [P7_LS1, P7_LS2], 0>,
 257                                    InstrStage<1, [P7_FX1, P7_FX2]>],
 258                                   [1, 1, 1]>,
 259   InstrItinData<IIC_LdStSTD     , [InstrStage<1, [P7_DU1, P7_DU2,
 260                                                   P7_DU3, P7_DU4], 0>,
 261                                    InstrStage<1, [P7_LS1, P7_LS2], 0>,
 262                                    InstrStage<1, [P7_FX1, P7_FX2]>],
 263                                   [1, 1, 1]>,
 264   InstrItinData<IIC_LdStSTU     , [InstrStage<1, [P7_DU1], 0>,
 265                                    InstrStage<1, [P7_DU2], 0>,
 266                                    InstrStage<1, [P7_LS1, P7_LS2], 0>,
 267                                    InstrStage<1, [P7_FX1, P7_FX2]>,
 268                                    InstrStage<1, [P7_FX1, P7_FX2]>],
 269                                   [2, 1, 1, 1]>,
 270   InstrItinData<IIC_LdStSTUX    , [InstrStage<1, [P7_DU1], 0>,
 271                                    InstrStage<1, [P7_DU2], 0>,
 272                                    InstrStage<1, [P7_DU3], 0>,
 273                                    InstrStage<1, [P7_DU4], 0>,
 274                                    InstrStage<1, [P7_LS1, P7_LS2], 0>,
 275                                    InstrStage<1, [P7_FX1, P7_FX2]>,
 276                                    InstrStage<1, [P7_FX1, P7_FX2]>],
 277                                   [2, 1, 1, 1]>,
 278   InstrItinData<IIC_LdStSTFD    , [InstrStage<1, [P7_DU1, P7_DU2,
 279                                                   P7_DU3, P7_DU4], 0>,
 280                                    InstrStage<1, [P7_LS1, P7_LS2], 0>,
 281                                    InstrStage<1, [P7_VS1, P7_VS2]>],
 282                                   [1, 1, 1]>,
 283   InstrItinData<IIC_LdStSTFDU   , [InstrStage<1, [P7_DU1], 0>,
 284                                    InstrStage<1, [P7_DU2], 0>,
 285                                    InstrStage<1, [P7_LS1, P7_LS2], 0>,
 286                                    InstrStage<1, [P7_FX1, P7_FX2], 0>,
 287                                    InstrStage<1, [P7_VS1, P7_VS2]>],
 288                                   [2, 1, 1, 1]>,
 289   InstrItinData<IIC_LdStSTVEBX  , [InstrStage<1, [P7_DU1, P7_DU2,
 290                                                   P7_DU3, P7_DU4], 0>,
 291                                    InstrStage<1, [P7_LS1, P7_LS2], 0>,
 292                                    InstrStage<1, [P7_VS2]>],
 293                                   [1, 1, 1]>,
 294   InstrItinData<IIC_LdStSTDCX   , [InstrStage<1, [P7_DU1], 0>,
 295                                    InstrStage<1, [P7_DU2], 0>,
 296                                    InstrStage<1, [P7_DU3], 0>,
 297                                    InstrStage<1, [P7_DU4], 0>,
 298                                    InstrStage<1, [P7_LS1, P7_LS2]>],
 299                                   [1, 1, 1]>,
 300   InstrItinData<IIC_LdStSTWCX   , [InstrStage<1, [P7_DU1], 0>,
 301                                    InstrStage<1, [P7_DU2], 0>,
 302                                    InstrStage<1, [P7_DU3], 0>,
 303                                    InstrStage<1, [P7_DU4], 0>,
 304                                    InstrStage<1, [P7_LS1, P7_LS2]>],
 305                                   [1, 1, 1]>,
 306   InstrItinData<IIC_BrMCRX      , [InstrStage<1, [P7_DU1], 0>,
 307                                    InstrStage<1, [P7_DU2], 0>,
 308                                    InstrStage<1, [P7_DU3], 0>,
 309                                    InstrStage<1, [P7_DU4], 0>,
 310                                    InstrStage<1, [P7_CRU]>,
 311                                    InstrStage<1, [P7_FX1, P7_FX2]>],
 312                                   [3, 1]>, // mtcr
 313   InstrItinData<IIC_SprMFCR     , [InstrStage<1, [P7_DU1], 0>,
 314                                    InstrStage<1, [P7_CRU]>],
 315                                   [6, 1]>,
 316   InstrItinData<IIC_SprMFCRF    , [InstrStage<1, [P7_DU1], 0>,
 317                                    InstrStage<1, [P7_CRU]>],
 318                                   [3, 1]>,
 319   InstrItinData<IIC_SprMTSPR    , [InstrStage<1, [P7_DU1], 0>,
 320                                    InstrStage<1, [P7_FX1]>],
 321                                   [4, 1]>, // mtctr
 322   InstrItinData<IIC_FPGeneral   , [InstrStage<1, [P7_DU1, P7_DU2,
 323                                                   P7_DU3, P7_DU4], 0>,
 324                                    InstrStage<1, [P7_VS1, P7_VS2]>],
 325                                   [5, 1, 1]>,
 326   InstrItinData<IIC_FPAddSub    , [InstrStage<1, [P7_DU1, P7_DU2,
 327                                                   P7_DU3, P7_DU4], 0>,
 328                                    InstrStage<1, [P7_VS1, P7_VS2]>],
 329                                   [5, 1, 1]>,
 330   InstrItinData<IIC_FPCompare   , [InstrStage<1, [P7_DU1, P7_DU2,
 331                                                   P7_DU3, P7_DU4], 0>,
 332                                    InstrStage<1, [P7_VS1, P7_VS2]>],
 333                                   [8, 1, 1]>,
 334   InstrItinData<IIC_FPDivD      , [InstrStage<1, [P7_DU1, P7_DU2,
 335                                                   P7_DU3, P7_DU4], 0>,
 336                                    InstrStage<1, [P7_VS1, P7_VS2]>],
 337                                   [33, 1, 1]>,
 338   InstrItinData<IIC_FPDivS      , [InstrStage<1, [P7_DU1, P7_DU2,
 339                                                   P7_DU3, P7_DU4], 0>,
 340                                    InstrStage<1, [P7_VS1, P7_VS2]>],
 341                                   [27, 1, 1]>,
 342   InstrItinData<IIC_FPSqrtD     , [InstrStage<1, [P7_DU1, P7_DU2,
 343                                                   P7_DU3, P7_DU4], 0>,
 344                                    InstrStage<1, [P7_VS1, P7_VS2]>],
 345                                   [44, 1, 1]>,
 346   InstrItinData<IIC_FPSqrtS     , [InstrStage<1, [P7_DU1, P7_DU2,
 347                                                   P7_DU3, P7_DU4], 0>,
 348                                    InstrStage<1, [P7_VS1, P7_VS2]>],
 349                                   [32, 1, 1]>,
 350   InstrItinData<IIC_FPFused     , [InstrStage<1, [P7_DU1, P7_DU2,
 351                                                   P7_DU3, P7_DU4], 0>,
 352                                    InstrStage<1, [P7_VS1, P7_VS2]>],
 353                                   [5, 1, 1, 1]>,
 354   InstrItinData<IIC_FPRes       , [InstrStage<1, [P7_DU1, P7_DU2,
 355                                                   P7_DU3, P7_DU4], 0>,
 356                                    InstrStage<1, [P7_VS1, P7_VS2]>],
 357                                   [5, 1, 1]>,
 358   InstrItinData<IIC_VecGeneral  , [InstrStage<1, [P7_DU1], 0>,
 359                                    InstrStage<1, [P7_VS1]>],
 360                                   [2, 1, 1]>,
 361   InstrItinData<IIC_VecVSL      , [InstrStage<1, [P7_DU1], 0>,
 362                                    InstrStage<1, [P7_VS1]>],
 363                                   [2, 1, 1]>,
 364   InstrItinData<IIC_VecVSR      , [InstrStage<1, [P7_DU1], 0>,
 365                                    InstrStage<1, [P7_VS1]>],
 366                                   [2, 1, 1]>,
 367   InstrItinData<IIC_VecFP       , [InstrStage<1, [P7_DU1], 0>,
 368                                    InstrStage<1, [P7_VS1, P7_VS2]>],
 369                                   [6, 1, 1]>,
 370   InstrItinData<IIC_VecFPCompare, [InstrStage<1, [P7_DU1], 0>,
 371                                    InstrStage<1, [P7_VS1, P7_VS2]>],
 372                                   [6, 1, 1]>,
 373   InstrItinData<IIC_VecFPRound  , [InstrStage<1, [P7_DU1], 0>,
 374                                    InstrStage<1, [P7_VS1, P7_VS2]>],
 375                                   [6, 1, 1]>,
 376   InstrItinData<IIC_VecComplex  , [InstrStage<1, [P7_DU1], 0>,
 377                                    InstrStage<1, [P7_VS1]>],
 378                                   [7, 1, 1]>,
 379   InstrItinData<IIC_VecPerm     , [InstrStage<1, [P7_DU1, P7_DU2], 0>,
 380                                    InstrStage<1, [P7_VS2]>],
 381                                   [3, 1, 1]>
 382 ]>;
 383
 384 // ===---------------------------------------------------------------------===//
 385 // P7 machine model for scheduling and other instruction cost heuristics.
 386
 387 def P7Model : SchedMachineModel {
 388   let IssueWidth = 6;  // 4 (non-branch) instructions are dispatched per cycle.
 389                        // Note that the dispatch bundle size is 6 (including
 390                        // branches), but the total internal issue bandwidth per
 391                        // cycle (from all queues) is 8.
 392
 393   let LoadLatency = 3; // Optimistic load latency assuming bypass.
 394                        // This is overriden by OperandCycles if the
 395                        // Itineraries are queried instead.
 396   let MispredictPenalty = 16;
 397
 398   // Try to make sure we have at least 10 dispatch groups in a loop.
 399   let LoopMicroOpBufferSize = 40;
 400
 401   let CompleteModel = 0;
 402
 403   let Itineraries = P7Itineraries;
 404 }
 405