1 //===-- PPCScheduleP9.td - PPC P9 Scheduling Definitions ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the itinerary class data for the POWER9 processor.
12 //===----------------------------------------------------------------------===//
13 include "PPCInstrInfo.td"
15 def P9Model : SchedMachineModel {
20 let MispredictPenalty = 16;
22 // Try to make sure we have at least 10 dispatch groups in a loop.
23 let LoopMicroOpBufferSize = 60;
25 let CompleteModel = 0;
29 let SchedModel = P9Model in {
31 // ***************** Processor Resources *****************
34 def DISPATCHER : ProcResource<12>;
37 def IP_AGEN : ProcResource<4>;
38 def IP_EXEC : ProcResource<4>;
39 def IP_EXECE : ProcResource<2> {
43 def IP_EXECO : ProcResource<2> {
49 def ALU : ProcResource<4>;
50 def ALUE : ProcResource<2> {
54 def ALUO : ProcResource<2> {
58 def DIV : ProcResource<2>;
59 def DP : ProcResource<4>;
60 def DPE : ProcResource<2> {
64 def DPO : ProcResource<2> {
68 def LS : ProcResource<4>;
69 def PM : ProcResource<2>;
70 def DFU : ProcResource<1>;
72 def TestGroup : ProcResGroup<[ALU, DP]>;
74 // ***************** SchedWriteRes Definitions *****************
77 def DISP_1C : SchedWriteRes<[DISPATCHER]> {
83 def IP_AGEN_1C : SchedWriteRes<[IP_AGEN]> {
88 def IP_EXEC_1C : SchedWriteRes<[IP_EXEC]> {
93 def IP_EXECE_1C : SchedWriteRes<[IP_EXECE]> {
98 def IP_EXECO_1C : SchedWriteRes<[IP_EXECO]> {
104 def P9_ALU_2C : SchedWriteRes<[ALU]> {
108 def P9_ALUE_2C : SchedWriteRes<[ALUE]> {
112 def P9_ALUO_2C : SchedWriteRes<[ALUO]> {
116 def P9_ALU_3C : SchedWriteRes<[ALU]> {
120 def P9_ALUE_3C : SchedWriteRes<[ALUE]> {
124 def P9_ALUO_3C : SchedWriteRes<[ALUO]> {
128 def P9_ALU_4C : SchedWriteRes<[ALU]> {
132 def P9_ALUE_4C : SchedWriteRes<[ALUE]> {
136 def P9_ALUO_4C : SchedWriteRes<[ALUO]> {
140 def P9_ALU_5C : SchedWriteRes<[ALU]> {
144 def P9_ALU_6C : SchedWriteRes<[ALU]> {
148 def P9_DIV_16C_8 : SchedWriteRes<[DIV]> {
149 let ResourceCycles = [8];
153 def P9_DIV_24C_8 : SchedWriteRes<[DIV]> {
154 let ResourceCycles = [8];
158 def P9_DIV_40C_8 : SchedWriteRes<[DIV]> {
159 let ResourceCycles = [8];
163 def P9_DP_2C : SchedWriteRes<[DP]> {
167 def P9_DP_5C : SchedWriteRes<[DP]> {
171 def P9_DP_7C : SchedWriteRes<[DP]> {
175 def P9_DPE_7C : SchedWriteRes<[DPE]> {
179 def P9_DPO_7C : SchedWriteRes<[DPO]> {
183 def P9_DP_22C_5 : SchedWriteRes<[DP]> {
184 let ResourceCycles = [5];
188 def P9_DP_24C_8 : SchedWriteRes<[DP]> {
189 let ResourceCycles = [8];
193 def P9_DP_26C_5 : SchedWriteRes<[DP]> {
194 let ResourceCycles = [5];
198 def P9_DP_27C_7 : SchedWriteRes<[DP]> {
199 let ResourceCycles = [7];
203 def P9_DP_33C_8 : SchedWriteRes<[DP]> {
204 let ResourceCycles = [8];
208 def P9_DP_36C_10 : SchedWriteRes<[DP]> {
209 let ResourceCycles = [10];
213 def P9_PM_3C : SchedWriteRes<[PM]> {
217 def P9_PM_7C : SchedWriteRes<[PM]> {
221 def P9_LS_1C : SchedWriteRes<[LS]> {
225 def P9_LS_4C : SchedWriteRes<[LS]> {
229 def P9_LS_5C : SchedWriteRes<[LS]> {
233 def P9_DFU_12C : SchedWriteRes<[DFU]> {
237 def P9_DFU_24C : SchedWriteRes<[DFU]> {
239 let ResourceCycles = [12];
242 def P9_DFU_58C : SchedWriteRes<[DFU]> {
244 let ResourceCycles = [44];
247 def P9_DFU_76C : SchedWriteRes<[TestGroup, DFU]> {
249 let ResourceCycles = [62];
251 // ***************** WriteSeq Definitions *****************
253 def P9_LoadAndALUOp_6C : WriteSequence<[P9_LS_4C, P9_ALU_2C]>;
254 def P9_LoadAndALUOp_7C : WriteSequence<[P9_LS_5C, P9_ALU_2C]>;
255 def P9_LoadAndPMOp_8C : WriteSequence<[P9_LS_5C, P9_PM_3C]>;
256 def P9_IntDivAndALUOp_26C_8 : WriteSequence<[P9_DIV_24C_8, P9_ALU_2C]>;
257 def P9_IntDivAndALUOp_42C_8 : WriteSequence<[P9_DIV_40C_8, P9_ALU_2C]>;
258 def P9_StoreAndALUOp_4C : WriteSequence<[P9_LS_1C, P9_ALU_3C]>;
259 def P9_ALUOpAndALUOp_4C : WriteSequence<[P9_ALU_2C, P9_ALU_2C]>;
261 // ***************** Defining Itinerary Class Resources *****************
263 def : ItinRW<[P9_ALU_2C, IP_EXEC_1C, DISP_1C, DISP_1C],
264 [IIC_IntSimple, IIC_IntGeneral]>;
266 def : ItinRW<[P9_ALU_2C, IP_EXEC_1C, DISP_1C, DISP_1C, DISP_1C],
267 [IIC_IntISEL, IIC_IntRotate, IIC_IntShift]>;
269 def : ItinRW<[P9_ALU_2C, IP_EXEC_1C, DISP_1C, DISP_1C], [IIC_IntCompare]>;
271 def : ItinRW<[P9_DP_5C, IP_EXEC_1C, DISP_1C, DISP_1C, DISP_1C],
272 [IIC_IntMulHW, IIC_IntMulHWU, IIC_IntMulLI]>;
274 def : ItinRW<[P9_LS_5C, IP_EXEC_1C, DISP_1C, DISP_1C],
275 [IIC_LdStLoad, IIC_LdStLD]>;
277 def : ItinRW<[P9_LS_4C, P9_ALU_2C, IP_EXEC_1C, IP_EXEC_1C,
278 DISP_1C, DISP_1C, DISP_1C, DISP_1C],
279 [IIC_LdStLoadUpd, IIC_LdStLDU]>;
281 def : ItinRW<[P9_LS_4C, P9_ALU_2C, IP_EXECE_1C, IP_EXECO_1C,
282 DISP_1C, DISP_1C, DISP_1C, DISP_1C],
283 [IIC_LdStLoadUpdX, IIC_LdStLDUX]>;
285 def : ItinRW<[P9_LS_1C, P9_ALU_2C, IP_EXEC_1C, IP_EXEC_1C, IP_AGEN_1C,
286 DISP_1C, DISP_1C, DISP_1C, DISP_1C, DISP_1C],
289 def : ItinRW<[P9_LoadAndALUOp_6C,
290 IP_AGEN_1C, IP_EXEC_1C, DISP_1C, DISP_1C, DISP_1C, DISP_1C],
291 [IIC_LdStLHA, IIC_LdStLWA]>;
293 def : ItinRW<[P9_LoadAndALUOp_6C, P9_ALU_2C,
294 IP_AGEN_1C, IP_EXEC_1C, IP_EXEC_1C,
295 DISP_1C, DISP_1C, DISP_1C, DISP_1C, DISP_1C, DISP_1C],
296 [IIC_LdStLHAU, IIC_LdStLHAUX]>;
298 // IIC_LdStLMW contains two microcoded insns. This is not accurate, but
299 // those insns are not used that much, if at all.
300 def : ItinRW<[P9_LS_4C, IP_EXEC_1C, DISP_1C, DISP_1C],
301 [IIC_LdStLWARX, IIC_LdStLDARX, IIC_LdStLMW]>;
303 def : ItinRW<[P9_LS_1C, IP_EXEC_1C, IP_AGEN_1C, DISP_1C, DISP_1C, DISP_1C],
304 [IIC_LdStSTFD, IIC_LdStSTD, IIC_LdStStore]>;
306 def : ItinRW<[P9_LS_1C, P9_ALU_2C, IP_EXEC_1C, IP_EXEC_1C, IP_AGEN_1C,
307 DISP_1C, DISP_1C, DISP_1C, DISP_1C, DISP_1C],
308 [IIC_LdStSTDU, IIC_LdStSTDUX]>;
310 def : ItinRW<[P9_StoreAndALUOp_4C, IP_EXEC_1C, IP_EXEC_1C, IP_AGEN_1C,
311 DISP_1C, DISP_1C, DISP_1C, DISP_1C, DISP_1C],
312 [IIC_LdStSTDCX, IIC_LdStSTWCX]>;
314 def : ItinRW<[P9_ALU_5C, IP_EXEC_1C, DISP_1C, DISP_1C, DISP_1C],
315 [IIC_BrCR, IIC_IntMTFSB0]>;
317 def : ItinRW<[P9_ALUOpAndALUOp_4C, P9_ALU_2C, IP_EXEC_1C, IP_EXEC_1C,
318 IP_EXEC_1C, DISP_1C, DISP_1C, DISP_1C, DISP_1C, DISP_1C, DISP_1C,
319 DISP_1C, DISP_1C, DISP_1C], [IIC_SprMFCR, IIC_SprMFCRF]>;
321 // This class should be broken down to instruction level, once some missing
323 def : ItinRW<[P9_LoadAndALUOp_6C, IP_EXEC_1C, IP_AGEN_1C,
324 DISP_1C, DISP_1C, DISP_1C], [IIC_SprMTSPR]>;
326 def : ItinRW<[P9_DP_7C, IP_EXEC_1C,
327 DISP_1C, DISP_1C, DISP_1C], [IIC_FPGeneral, IIC_FPAddSub]>;
329 def : ItinRW<[P9_DP_36C_10, IP_EXEC_1C], [IIC_FPSqrtD]>;
330 def : ItinRW<[P9_DP_26C_5, P9_DP_26C_5, IP_EXEC_1C, IP_EXEC_1C], [IIC_FPSqrtS]>;
332 include "P9InstrResources.td"