1 //===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPC specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #include "PPCSubtarget.h"
16 #include "PPCRegisterInfo.h"
17 #include "PPCTargetMachine.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineScheduler.h"
20 #include "llvm/IR/Attributes.h"
21 #include "llvm/IR/Function.h"
22 #include "llvm/IR/GlobalValue.h"
23 #include "llvm/Support/CommandLine.h"
24 #include "llvm/Support/TargetRegistry.h"
25 #include "llvm/Target/TargetMachine.h"
30 #define DEBUG_TYPE "ppc-subtarget"
32 #define GET_SUBTARGETINFO_TARGET_DESC
33 #define GET_SUBTARGETINFO_CTOR
34 #include "PPCGenSubtargetInfo.inc"
36 static cl::opt<bool> UseSubRegLiveness("ppc-track-subreg-liveness",
37 cl::desc("Enable subregister liveness tracking for PPC"), cl::Hidden);
39 static cl::opt<bool> QPXStackUnaligned("qpx-stack-unaligned",
40 cl::desc("Even when QPX is enabled the stack is not 32-byte aligned"),
43 PPCSubtarget &PPCSubtarget::initializeSubtargetDependencies(StringRef CPU,
45 initializeEnvironment();
46 initSubtargetFeatures(CPU, FS);
50 PPCSubtarget::PPCSubtarget(const Triple &TT, const std::string &CPU,
51 const std::string &FS, const PPCTargetMachine &TM)
52 : PPCGenSubtargetInfo(TT, CPU, FS), TargetTriple(TT),
53 IsPPC64(TargetTriple.getArch() == Triple::ppc64 ||
54 TargetTriple.getArch() == Triple::ppc64le),
55 TM(TM), FrameLowering(initializeSubtargetDependencies(CPU, FS)),
56 InstrInfo(*this), TLInfo(TM, *this) {}
58 void PPCSubtarget::initializeEnvironment() {
60 DarwinDirective = PPC::DIR_NONE;
62 Has64BitSupport = false;
97 DeprecatedDST = false;
98 HasLazyResolverStubs = false;
100 HasInvariantFunctionDescriptors = false;
101 HasPartwordAtomics = false;
102 HasDirectMove = false;
103 IsQPXStackUnaligned = false;
108 UseLongCalls = false;
110 HasPOPCNTD = POPCNTD_Unavailable;
113 void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
114 // Determine default and user specified characteristics
115 std::string CPUName = CPU;
116 if (CPUName.empty() || CPU == "generic") {
117 // If cross-compiling with -march=ppc64le without -mcpu
118 if (TargetTriple.getArch() == Triple::ppc64le)
124 // Initialize scheduling itinerary for the specified CPU.
125 InstrItins = getInstrItineraryForCPU(CPUName);
127 // Parse features string.
128 ParseSubtargetFeatures(CPUName, FS);
130 // If the user requested use of 64-bit regs, but the cpu selected doesn't
131 // support it, ignore.
132 if (IsPPC64 && has64BitSupport())
135 // Set up darwin-specific properties.
137 HasLazyResolverStubs = true;
139 // QPX requires a 32-byte aligned stack. Note that we need to do this if
140 // we're compiling for a BG/Q system regardless of whether or not QPX
141 // is enabled because external functions will assume this alignment.
142 IsQPXStackUnaligned = QPXStackUnaligned;
143 StackAlignment = getPlatformStackAlignment();
145 // Determine endianness.
146 // FIXME: Part of the TargetMachine.
147 IsLittleEndian = (TargetTriple.getArch() == Triple::ppc64le);
150 /// Return true if accesses to the specified global have to go through a dyld
151 /// lazy resolution stub. This means that an extra load is required to get the
152 /// address of the global.
153 bool PPCSubtarget::hasLazyResolverStub(const GlobalValue *GV) const {
154 if (!HasLazyResolverStubs)
156 if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
158 // 32 bit macho has no relocation for a-b if a is undefined, even if b is in
159 // the section that is being relocated. This means we have to use o load even
160 // for GVs that are known to be local to the dso.
161 if (GV->isDeclarationForLinker() || GV->hasCommonLinkage())
166 // Embedded cores need aggressive scheduling (and some others also benefit).
167 static bool needsAggressiveScheduling(unsigned Directive) {
169 default: return false;
172 case PPC::DIR_E500mc:
176 // FIXME: Same as P8 until POWER9 scheduling info is available
182 bool PPCSubtarget::enableMachineScheduler() const {
183 // Enable MI scheduling for the embedded cores.
184 // FIXME: Enable this for all cores (some additional modeling
185 // may be necessary).
186 return needsAggressiveScheduling(DarwinDirective);
189 // This overrides the PostRAScheduler bit in the SchedModel for each CPU.
190 bool PPCSubtarget::enablePostRAScheduler() const { return true; }
192 PPCGenSubtargetInfo::AntiDepBreakMode PPCSubtarget::getAntiDepBreakMode() const {
193 return TargetSubtargetInfo::ANTIDEP_ALL;
196 void PPCSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
197 CriticalPathRCs.clear();
198 CriticalPathRCs.push_back(isPPC64() ?
199 &PPC::G8RCRegClass : &PPC::GPRCRegClass);
202 void PPCSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
203 unsigned NumRegionInstrs) const {
204 if (needsAggressiveScheduling(DarwinDirective)) {
205 Policy.OnlyTopDown = false;
206 Policy.OnlyBottomUp = false;
209 // Spilling is generally expensive on all PPC cores, so always enable
210 // register-pressure tracking.
211 Policy.ShouldTrackPressure = true;
214 bool PPCSubtarget::useAA() const {
215 // Use AA during code generation for the embedded cores.
216 return needsAggressiveScheduling(DarwinDirective);
219 bool PPCSubtarget::enableSubRegLiveness() const {
220 return UseSubRegLiveness;
223 unsigned char PPCSubtarget::classifyGlobalReference(
224 const GlobalValue *GV) const {
225 // Note that currently we don't generate non-pic references.
226 // If a caller wants that, this will have to be updated.
228 // Large code model always uses the TOC even for local symbols.
229 if (TM.getCodeModel() == CodeModel::Large)
230 return PPCII::MO_PIC_FLAG | PPCII::MO_NLP_FLAG;
232 unsigned char flags = PPCII::MO_PIC_FLAG;
234 // Only if the relocation mode is PIC do we have to worry about
235 // interposition. In all other cases we can use a slightly looser standard to
236 // decide how to access the symbol.
237 if (TM.getRelocationModel() == Reloc::PIC_) {
238 // If it's local, or it's non-default, it can't be interposed.
239 if (!GV->hasLocalLinkage() &&
240 GV->hasDefaultVisibility()) {
241 flags |= PPCII::MO_NLP_FLAG;
246 if (GV->isStrongDefinitionForLinker())
248 return flags | PPCII::MO_NLP_FLAG;
251 bool PPCSubtarget::isELFv2ABI() const { return TM.isELFv2ABI(); }
252 bool PPCSubtarget::isPPC64() const { return TM.isPPC64(); }