1 //===-- PPCSubtarget.h - Define Subtarget for the PPC ----------*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the PowerPC specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_POWERPC_PPCSUBTARGET_H
15 #define LLVM_LIB_TARGET_POWERPC_PPCSUBTARGET_H
17 #include "PPCFrameLowering.h"
18 #include "PPCISelLowering.h"
19 #include "PPCInstrInfo.h"
20 #include "llvm/ADT/Triple.h"
21 #include "llvm/CodeGen/SelectionDAGTargetInfo.h"
22 #include "llvm/IR/DataLayout.h"
23 #include "llvm/MC/MCInstrItineraries.h"
24 #include "llvm/Target/TargetSubtargetInfo.h"
27 #define GET_SUBTARGETINFO_HEADER
28 #include "PPCGenSubtargetInfo.inc"
30 // GCC #defines PPC on Linux but we use it as our namespace name
37 // -m directive values.
67 class PPCSubtarget : public PPCGenSubtargetInfo {
76 /// TargetTriple - What processor and OS we're targeting.
79 /// stackAlignment - The minimum alignment known to hold of the stack frame on
80 /// entry to the function and which must be maintained by every function.
81 unsigned StackAlignment;
83 /// Selected instruction itineraries (one entry per itinerary class.)
84 InstrItineraryData InstrItins;
86 /// Which cpu directive was used.
87 unsigned DarwinDirective;
89 /// Used by the ISel to turn in optimizations for POWER4-derived architectures
107 bool HasFRE, HasFRES, HasFRSQRTE, HasFRSQRTES;
125 bool HasLazyResolverStubs;
128 bool HasInvariantFunctionDescriptors;
129 bool HasPartwordAtomics;
137 POPCNTDKind HasPOPCNTD;
139 /// When targeting QPX running a stock PPC64 Linux kernel where the stack
140 /// alignment has not been changed, we need to keep the 16-byte alignment
142 bool IsQPXStackUnaligned;
144 const PPCTargetMachine &TM;
145 PPCFrameLowering FrameLowering;
146 PPCInstrInfo InstrInfo;
147 PPCTargetLowering TLInfo;
148 SelectionDAGTargetInfo TSInfo;
151 /// This constructor initializes the data members to match that
152 /// of the specified triple.
154 PPCSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
155 const PPCTargetMachine &TM);
157 /// ParseSubtargetFeatures - Parses features string setting specified
158 /// subtarget options. Definition of function is auto generated by tblgen.
159 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
161 /// getStackAlignment - Returns the minimum alignment known to hold of the
162 /// stack frame on entry to the function and which must be maintained by every
163 /// function for this subtarget.
164 unsigned getStackAlignment() const { return StackAlignment; }
166 /// getDarwinDirective - Returns the -m directive specified for the cpu.
168 unsigned getDarwinDirective() const { return DarwinDirective; }
170 /// getInstrItins - Return the instruction itineraries based on subtarget
172 const InstrItineraryData *getInstrItineraryData() const override {
176 const PPCFrameLowering *getFrameLowering() const override {
177 return &FrameLowering;
179 const PPCInstrInfo *getInstrInfo() const override { return &InstrInfo; }
180 const PPCTargetLowering *getTargetLowering() const override {
183 const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
186 const PPCRegisterInfo *getRegisterInfo() const override {
187 return &getInstrInfo()->getRegisterInfo();
189 const PPCTargetMachine &getTargetMachine() const { return TM; }
191 /// initializeSubtargetDependencies - Initializes using a CPU and feature string
192 /// so that we can use initializer lists for subtarget initialization.
193 PPCSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
196 void initializeEnvironment();
197 void initSubtargetFeatures(StringRef CPU, StringRef FS);
200 /// isPPC64 - Return true if we are generating code for 64-bit pointer mode.
202 bool isPPC64() const;
204 /// has64BitSupport - Return true if the selected CPU supports 64-bit
205 /// instructions, regardless of whether we are in 32-bit or 64-bit mode.
206 bool has64BitSupport() const { return Has64BitSupport; }
207 // useSoftFloat - Return true if soft-float option is turned on.
208 bool useSoftFloat() const { return !HasHardFloat; }
210 /// use64BitRegs - Return true if in 64-bit mode or if we should use 64-bit
211 /// registers in 32-bit mode when possible. This can only true if
212 /// has64BitSupport() returns true.
213 bool use64BitRegs() const { return Use64BitRegs; }
215 /// useCRBits - Return true if we should store and manipulate i1 values in
216 /// the individual condition register bits.
217 bool useCRBits() const { return UseCRBits; }
219 /// hasLazyResolverStub - Return true if accesses to the specified global have
220 /// to go through a dyld lazy resolution stub. This means that an extra load
221 /// is required to get the address of the global.
222 bool hasLazyResolverStub(const GlobalValue *GV) const;
224 // isLittleEndian - True if generating little-endian code
225 bool isLittleEndian() const { return IsLittleEndian; }
227 // Specific obvious features.
228 bool hasFCPSGN() const { return HasFCPSGN; }
229 bool hasFSQRT() const { return HasFSQRT; }
230 bool hasFRE() const { return HasFRE; }
231 bool hasFRES() const { return HasFRES; }
232 bool hasFRSQRTE() const { return HasFRSQRTE; }
233 bool hasFRSQRTES() const { return HasFRSQRTES; }
234 bool hasRecipPrec() const { return HasRecipPrec; }
235 bool hasSTFIWX() const { return HasSTFIWX; }
236 bool hasLFIWAX() const { return HasLFIWAX; }
237 bool hasFPRND() const { return HasFPRND; }
238 bool hasFPCVT() const { return HasFPCVT; }
239 bool hasAltivec() const { return HasAltivec; }
240 bool hasSPE() const { return HasSPE; }
241 bool hasQPX() const { return HasQPX; }
242 bool hasVSX() const { return HasVSX; }
243 bool hasP8Vector() const { return HasP8Vector; }
244 bool hasP8Altivec() const { return HasP8Altivec; }
245 bool hasP8Crypto() const { return HasP8Crypto; }
246 bool hasP9Vector() const { return HasP9Vector; }
247 bool hasP9Altivec() const { return HasP9Altivec; }
248 bool hasMFOCRF() const { return HasMFOCRF; }
249 bool hasISEL() const { return HasISEL; }
250 bool hasBPERMD() const { return HasBPERMD; }
251 bool hasExtDiv() const { return HasExtDiv; }
252 bool hasCMPB() const { return HasCMPB; }
253 bool hasLDBRX() const { return HasLDBRX; }
254 bool isBookE() const { return IsBookE; }
255 bool hasOnlyMSYNC() const { return HasOnlyMSYNC; }
256 bool isPPC4xx() const { return IsPPC4xx; }
257 bool isPPC6xx() const { return IsPPC6xx; }
258 bool isE500() const { return IsE500; }
259 bool isFeatureMFTB() const { return FeatureMFTB; }
260 bool isDeprecatedDST() const { return DeprecatedDST; }
261 bool hasICBT() const { return HasICBT; }
262 bool hasInvariantFunctionDescriptors() const {
263 return HasInvariantFunctionDescriptors;
265 bool hasPartwordAtomics() const { return HasPartwordAtomics; }
266 bool hasDirectMove() const { return HasDirectMove; }
268 bool isQPXStackUnaligned() const { return IsQPXStackUnaligned; }
269 unsigned getPlatformStackAlignment() const {
270 if ((hasQPX() || isBGQ()) && !isQPXStackUnaligned())
275 bool hasHTM() const { return HasHTM; }
276 bool hasFusion() const { return HasFusion; }
277 bool hasFloat128() const { return HasFloat128; }
278 bool isISA3_0() const { return IsISA3_0; }
279 bool useLongCalls() const { return UseLongCalls; }
281 POPCNTDKind hasPOPCNTD() const { return HasPOPCNTD; }
283 const Triple &getTargetTriple() const { return TargetTriple; }
285 /// isDarwin - True if this is any darwin platform.
286 bool isDarwin() const { return TargetTriple.isMacOSX(); }
287 /// isBGQ - True if this is a BG/Q platform.
288 bool isBGQ() const { return TargetTriple.getVendor() == Triple::BGQ; }
290 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
291 bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
292 bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
294 bool isDarwinABI() const { return isTargetMachO() || isDarwin(); }
295 bool isSVR4ABI() const { return !isDarwinABI(); }
296 bool isELFv2ABI() const;
298 bool enableEarlyIfConversion() const override { return hasISEL(); }
300 // Scheduling customization.
301 bool enableMachineScheduler() const override;
302 // This overrides the PostRAScheduler bit in the SchedModel for each CPU.
303 bool enablePostRAScheduler() const override;
304 AntiDepBreakMode getAntiDepBreakMode() const override;
305 void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
307 void overrideSchedPolicy(MachineSchedPolicy &Policy,
308 unsigned NumRegionInstrs) const override;
309 bool useAA() const override;
311 bool enableSubRegLiveness() const override;
313 /// classifyGlobalReference - Classify a global variable reference for the
314 /// current subtarget accourding to how we should reference it.
315 unsigned char classifyGlobalReference(const GlobalValue *GV) const;
317 } // End llvm namespace