1 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Top-level implementation for the PowerPC target.
12 //===----------------------------------------------------------------------===//
14 #include "MCTargetDesc/PPCMCTargetDesc.h"
16 #include "PPCSubtarget.h"
17 #include "PPCTargetObjectFile.h"
18 #include "PPCTargetMachine.h"
19 #include "PPCTargetTransformInfo.h"
20 #include "llvm/ADT/Optional.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/StringRef.h"
23 #include "llvm/ADT/Triple.h"
24 #include "llvm/Analysis/TargetTransformInfo.h"
25 #include "llvm/CodeGen/Passes.h"
26 #include "llvm/CodeGen/TargetPassConfig.h"
27 #include "llvm/IR/Attributes.h"
28 #include "llvm/IR/DataLayout.h"
29 #include "llvm/IR/Function.h"
30 #include "llvm/Pass.h"
31 #include "llvm/Support/CodeGen.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/TargetRegistry.h"
34 #include "llvm/Target/TargetLoweringObjectFile.h"
35 #include "llvm/Target/TargetOptions.h"
36 #include "llvm/Transforms/Scalar.h"
44 opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
45 cl::desc("Disable CTR loops for PPC"));
48 opt<bool> DisablePreIncPrep("disable-ppc-preinc-prep", cl::Hidden,
49 cl::desc("Disable PPC loop preinc prep"));
52 VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early",
53 cl::Hidden, cl::desc("Schedule VSX FMA instruction mutation early"));
56 opt<bool> DisableVSXSwapRemoval("disable-ppc-vsx-swap-removal", cl::Hidden,
57 cl::desc("Disable VSX Swap Removal for PPC"));
60 opt<bool> DisableQPXLoadSplat("disable-ppc-qpx-load-splat", cl::Hidden,
61 cl::desc("Disable QPX load splat simplification"));
64 opt<bool> DisableMIPeephole("disable-ppc-peephole", cl::Hidden,
65 cl::desc("Disable machine peepholes for PPC"));
68 EnableGEPOpt("ppc-gep-opt", cl::Hidden,
69 cl::desc("Enable optimizations on complex GEPs"),
73 EnablePrefetch("enable-ppc-prefetching",
74 cl::desc("disable software prefetching on PPC"),
75 cl::init(false), cl::Hidden);
78 EnableExtraTOCRegDeps("enable-ppc-extra-toc-reg-deps",
79 cl::desc("Add extra TOC register dependencies"),
80 cl::init(true), cl::Hidden);
83 EnableMachineCombinerPass("ppc-machine-combiner",
84 cl::desc("Enable the machine combiner pass"),
85 cl::init(true), cl::Hidden);
87 extern "C" void LLVMInitializePowerPCTarget() {
88 // Register the targets
89 RegisterTargetMachine<PPC32TargetMachine> A(getThePPC32Target());
90 RegisterTargetMachine<PPC64TargetMachine> B(getThePPC64Target());
91 RegisterTargetMachine<PPC64TargetMachine> C(getThePPC64LETarget());
93 PassRegistry &PR = *PassRegistry::getPassRegistry();
94 initializePPCBoolRetToIntPass(PR);
95 initializePPCExpandISELPass(PR);
98 /// Return the datalayout string of a subtarget.
99 static std::string getDataLayoutString(const Triple &T) {
100 bool is64Bit = T.getArch() == Triple::ppc64 || T.getArch() == Triple::ppc64le;
103 // Most PPC* platforms are big endian, PPC64LE is little endian.
104 if (T.getArch() == Triple::ppc64le)
109 Ret += DataLayout::getManglingComponent(T);
111 // PPC32 has 32 bit pointers. The PS3 (OS Lv2) is a PPC64 machine with 32 bit
113 if (!is64Bit || T.getOS() == Triple::Lv2)
116 // Note, the alignment values for f64 and i64 on ppc64 in Darwin
117 // documentation are wrong; these are correct (i.e. "what gcc does").
118 if (is64Bit || !T.isOSDarwin())
123 // PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones.
132 static std::string computeFSAdditions(StringRef FS, CodeGenOpt::Level OL,
134 std::string FullFS = FS;
136 // Make sure 64-bit features are available when CPUname is generic
137 if (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le) {
139 FullFS = "+64bit," + FullFS;
144 if (OL >= CodeGenOpt::Default) {
146 FullFS = "+crbits," + FullFS;
151 if (OL != CodeGenOpt::None) {
153 FullFS = "+invariant-function-descriptors," + FullFS;
155 FullFS = "+invariant-function-descriptors";
161 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
162 // If it isn't a Mach-O file then it's going to be a linux ELF
165 return llvm::make_unique<TargetLoweringObjectFileMachO>();
167 return llvm::make_unique<PPC64LinuxTargetObjectFile>();
170 static PPCTargetMachine::PPCABI computeTargetABI(const Triple &TT,
171 const TargetOptions &Options) {
172 if (Options.MCOptions.getABIName().startswith("elfv1"))
173 return PPCTargetMachine::PPC_ABI_ELFv1;
174 else if (Options.MCOptions.getABIName().startswith("elfv2"))
175 return PPCTargetMachine::PPC_ABI_ELFv2;
177 assert(Options.MCOptions.getABIName().empty() &&
178 "Unknown target-abi option!");
180 if (!TT.isMacOSX()) {
181 switch (TT.getArch()) {
182 case Triple::ppc64le:
183 return PPCTargetMachine::PPC_ABI_ELFv2;
185 return PPCTargetMachine::PPC_ABI_ELFv1;
191 return PPCTargetMachine::PPC_ABI_UNKNOWN;
194 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
195 Optional<Reloc::Model> RM) {
196 if (!RM.hasValue()) {
197 if (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le) {
198 if (!TT.isOSBinFormatMachO() && !TT.isMacOSX())
202 return Reloc::DynamicNoPIC;
203 return Reloc::Static;
208 // The FeatureString here is a little subtle. We are modifying the feature
209 // string with what are (currently) non-function specific overrides as it goes
210 // into the LLVMTargetMachine constructor and then using the stored value in the
211 // Subtarget constructor below it.
212 PPCTargetMachine::PPCTargetMachine(const Target &T, const Triple &TT,
213 StringRef CPU, StringRef FS,
214 const TargetOptions &Options,
215 Optional<Reloc::Model> RM,
216 CodeModel::Model CM, CodeGenOpt::Level OL)
217 : LLVMTargetMachine(T, getDataLayoutString(TT), TT, CPU,
218 computeFSAdditions(FS, OL, TT), Options,
219 getEffectiveRelocModel(TT, RM), CM, OL),
220 TLOF(createTLOF(getTargetTriple())),
221 TargetABI(computeTargetABI(TT, Options)) {
225 PPCTargetMachine::~PPCTargetMachine() = default;
227 void PPC32TargetMachine::anchor() {}
229 PPC32TargetMachine::PPC32TargetMachine(const Target &T, const Triple &TT,
230 StringRef CPU, StringRef FS,
231 const TargetOptions &Options,
232 Optional<Reloc::Model> RM,
234 CodeGenOpt::Level OL)
235 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
237 void PPC64TargetMachine::anchor() {}
239 PPC64TargetMachine::PPC64TargetMachine(const Target &T, const Triple &TT,
240 StringRef CPU, StringRef FS,
241 const TargetOptions &Options,
242 Optional<Reloc::Model> RM,
244 CodeGenOpt::Level OL)
245 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
248 PPCTargetMachine::getSubtargetImpl(const Function &F) const {
249 Attribute CPUAttr = F.getFnAttribute("target-cpu");
250 Attribute FSAttr = F.getFnAttribute("target-features");
252 std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
253 ? CPUAttr.getValueAsString().str()
255 std::string FS = !FSAttr.hasAttribute(Attribute::None)
256 ? FSAttr.getValueAsString().str()
259 // FIXME: This is related to the code below to reset the target options,
260 // we need to know whether or not the soft float flag is set on the
261 // function before we can generate a subtarget. We also need to use
262 // it as a key for the subtarget since that can be the only difference
263 // between two functions.
265 F.getFnAttribute("use-soft-float").getValueAsString() == "true";
266 // If the soft float attribute is set on the function turn on the soft float
267 // subtarget feature.
269 FS += FS.empty() ? "-hard-float" : ",-hard-float";
271 auto &I = SubtargetMap[CPU + FS];
273 // This needs to be done before we create a new subtarget since any
274 // creation will depend on the TM and the code generation flags on the
275 // function that reside in TargetOptions.
276 resetTargetOptions(F);
277 I = llvm::make_unique<PPCSubtarget>(
279 // FIXME: It would be good to have the subtarget additions here
280 // not necessary. Anything that turns them on/off (overrides) ends
281 // up being put at the end of the feature string, but the defaults
282 // shouldn't require adding them. Fixing this means pulling Feature64Bit
283 // out of most of the target cpus in the .td file and making it set only
284 // as part of initialization via the TargetTriple.
285 computeFSAdditions(FS, getOptLevel(), getTargetTriple()), *this);
290 //===----------------------------------------------------------------------===//
291 // Pass Pipeline Configuration
292 //===----------------------------------------------------------------------===//
296 /// PPC Code Generator Pass Configuration Options.
297 class PPCPassConfig : public TargetPassConfig {
299 PPCPassConfig(PPCTargetMachine *TM, PassManagerBase &PM)
300 : TargetPassConfig(TM, PM) {}
302 PPCTargetMachine &getPPCTargetMachine() const {
303 return getTM<PPCTargetMachine>();
306 void addIRPasses() override;
307 bool addPreISel() override;
308 bool addILPOpts() override;
309 bool addInstSelector() override;
310 void addMachineSSAOptimization() override;
311 void addPreRegAlloc() override;
312 void addPreSched2() override;
313 void addPreEmitPass() override;
316 } // end anonymous namespace
318 TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
319 return new PPCPassConfig(this, PM);
322 void PPCPassConfig::addIRPasses() {
323 if (TM->getOptLevel() != CodeGenOpt::None)
324 addPass(createPPCBoolRetToIntPass());
325 addPass(createAtomicExpandPass());
327 // For the BG/Q (or if explicitly requested), add explicit data prefetch
329 bool UsePrefetching = TM->getTargetTriple().getVendor() == Triple::BGQ &&
330 getOptLevel() != CodeGenOpt::None;
331 if (EnablePrefetch.getNumOccurrences() > 0)
332 UsePrefetching = EnablePrefetch;
334 addPass(createLoopDataPrefetchPass());
336 if (TM->getOptLevel() >= CodeGenOpt::Default && EnableGEPOpt) {
337 // Call SeparateConstOffsetFromGEP pass to extract constants within indices
338 // and lower a GEP with multiple indices to either arithmetic operations or
339 // multiple GEPs with single index.
340 addPass(createSeparateConstOffsetFromGEPPass(TM, true));
341 // Call EarlyCSE pass to find and remove subexpressions in the lowered
343 addPass(createEarlyCSEPass());
344 // Do loop invariant code motion in case part of the lowered result is
346 addPass(createLICMPass());
349 TargetPassConfig::addIRPasses();
352 bool PPCPassConfig::addPreISel() {
353 if (!DisablePreIncPrep && getOptLevel() != CodeGenOpt::None)
354 addPass(createPPCLoopPreIncPrepPass(getPPCTargetMachine()));
356 if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
357 addPass(createPPCCTRLoops(getPPCTargetMachine()));
362 bool PPCPassConfig::addILPOpts() {
363 addPass(&EarlyIfConverterID);
365 if (EnableMachineCombinerPass)
366 addPass(&MachineCombinerID);
371 bool PPCPassConfig::addInstSelector() {
372 // Install an instruction selector.
373 addPass(createPPCISelDag(getPPCTargetMachine()));
376 if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
377 addPass(createPPCCTRLoopsVerify());
380 addPass(createPPCVSXCopyPass());
384 void PPCPassConfig::addMachineSSAOptimization() {
385 TargetPassConfig::addMachineSSAOptimization();
386 // For little endian, remove where possible the vector swap instructions
387 // introduced at code generation to normalize vector element order.
388 if (TM->getTargetTriple().getArch() == Triple::ppc64le &&
389 !DisableVSXSwapRemoval)
390 addPass(createPPCVSXSwapRemovalPass());
391 // Target-specific peephole cleanups performed after instruction
393 if (!DisableMIPeephole) {
394 addPass(createPPCMIPeepholePass());
395 addPass(&DeadMachineInstructionElimID);
399 void PPCPassConfig::addPreRegAlloc() {
400 if (getOptLevel() != CodeGenOpt::None) {
401 initializePPCVSXFMAMutatePass(*PassRegistry::getPassRegistry());
402 insertPass(VSXFMAMutateEarly ? &RegisterCoalescerID : &MachineSchedulerID,
406 // FIXME: We probably don't need to run these for -fPIE.
407 if (getPPCTargetMachine().isPositionIndependent()) {
408 // FIXME: LiveVariables should not be necessary here!
409 // PPCTLSDYnamicCallPass uses LiveIntervals which previously dependet on
410 // LiveVariables. This (unnecessary) dependency has been removed now,
411 // however a stage-2 clang build fails without LiveVariables computed here.
412 addPass(&LiveVariablesID, false);
413 addPass(createPPCTLSDynamicCallPass());
415 if (EnableExtraTOCRegDeps)
416 addPass(createPPCTOCRegDepsPass());
419 void PPCPassConfig::addPreSched2() {
420 if (getOptLevel() != CodeGenOpt::None) {
421 addPass(&IfConverterID);
423 // This optimization must happen after anything that might do store-to-load
424 // forwarding. Here we're after RA (and, thus, when spills are inserted)
425 // but before post-RA scheduling.
426 if (!DisableQPXLoadSplat)
427 addPass(createPPCQPXLoadSplatPass());
431 void PPCPassConfig::addPreEmitPass() {
432 addPass(createPPCExpandISELPass());
434 if (getOptLevel() != CodeGenOpt::None)
435 addPass(createPPCEarlyReturnPass(), false);
436 // Must run branch selection immediately preceding the asm printer.
437 addPass(createPPCBranchSelectionPass(), false);
440 TargetIRAnalysis PPCTargetMachine::getTargetIRAnalysis() {
441 return TargetIRAnalysis([this](const Function &F) {
442 return TargetTransformInfo(PPCTTIImpl(this, F));