1 //===-- AMDILISelDAGToDAG.cpp - A dag to dag inst selector for AMDIL ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //==-----------------------------------------------------------------------===//
11 /// \brief Defines an instruction selector for the AMDGPU target.
13 //===----------------------------------------------------------------------===//
14 #include "AMDGPUInstrInfo.h"
15 #include "AMDGPUISelLowering.h" // For AMDGPUISD
16 #include "AMDGPURegisterInfo.h"
17 #include "AMDILDevices.h"
18 #include "R600InstrInfo.h"
19 #include "SIISelLowering.h"
20 #include "llvm/ADT/ValueMap.h"
21 #include "llvm/CodeGen/PseudoSourceValue.h"
22 #include "llvm/CodeGen/SelectionDAGISel.h"
23 #include "llvm/Support/Compiler.h"
24 #include "llvm/CodeGen/SelectionDAG.h"
30 //===----------------------------------------------------------------------===//
31 // Instruction Selector Implementation
32 //===----------------------------------------------------------------------===//
35 /// AMDGPU specific code to select AMDGPU machine instructions for
36 /// SelectionDAG operations.
37 class AMDGPUDAGToDAGISel : public SelectionDAGISel {
38 // Subtarget - Keep a pointer to the AMDGPU Subtarget around so that we can
39 // make the right decision when generating code for different targets.
40 const AMDGPUSubtarget &Subtarget;
42 AMDGPUDAGToDAGISel(TargetMachine &TM);
43 virtual ~AMDGPUDAGToDAGISel();
45 SDNode *Select(SDNode *N);
46 virtual const char *getPassName() const;
47 virtual void PostprocessISelDAG();
50 inline SDValue getSmallIPtrImm(unsigned Imm);
51 bool FoldOperands(unsigned, const R600InstrInfo *, std::vector<SDValue> &);
53 // Complex pattern selectors
54 bool SelectADDRParam(SDValue Addr, SDValue& R1, SDValue& R2);
55 bool SelectADDR(SDValue N, SDValue &R1, SDValue &R2);
56 bool SelectADDR64(SDValue N, SDValue &R1, SDValue &R2);
58 static bool checkType(const Value *ptr, unsigned int addrspace);
59 static const Value *getBasePointerValue(const Value *V);
61 static bool isGlobalStore(const StoreSDNode *N);
62 static bool isPrivateStore(const StoreSDNode *N);
63 static bool isLocalStore(const StoreSDNode *N);
64 static bool isRegionStore(const StoreSDNode *N);
66 static bool isCPLoad(const LoadSDNode *N);
67 static bool isConstantLoad(const LoadSDNode *N, int cbID);
68 static bool isGlobalLoad(const LoadSDNode *N);
69 static bool isParamLoad(const LoadSDNode *N);
70 static bool isPrivateLoad(const LoadSDNode *N);
71 static bool isLocalLoad(const LoadSDNode *N);
72 static bool isRegionLoad(const LoadSDNode *N);
74 bool SelectGlobalValueConstantOffset(SDValue Addr, SDValue& IntPtr);
75 bool SelectGlobalValueVariableOffset(SDValue Addr,
76 SDValue &BaseReg, SDValue& Offset);
77 bool SelectADDRVTX_READ(SDValue Addr, SDValue &Base, SDValue &Offset);
78 bool SelectADDRIndirect(SDValue Addr, SDValue &Base, SDValue &Offset);
80 // Include the pieces autogenerated from the target description.
81 #include "AMDGPUGenDAGISel.inc"
83 } // end anonymous namespace
85 /// \brief This pass converts a legalized DAG into a AMDGPU-specific
86 // DAG, ready for instruction scheduling.
87 FunctionPass *llvm::createAMDGPUISelDag(TargetMachine &TM
89 return new AMDGPUDAGToDAGISel(TM);
92 AMDGPUDAGToDAGISel::AMDGPUDAGToDAGISel(TargetMachine &TM
94 : SelectionDAGISel(TM), Subtarget(TM.getSubtarget<AMDGPUSubtarget>()) {
97 AMDGPUDAGToDAGISel::~AMDGPUDAGToDAGISel() {
100 SDValue AMDGPUDAGToDAGISel::getSmallIPtrImm(unsigned int Imm) {
101 return CurDAG->getTargetConstant(Imm, MVT::i32);
104 bool AMDGPUDAGToDAGISel::SelectADDRParam(
105 SDValue Addr, SDValue& R1, SDValue& R2) {
107 if (Addr.getOpcode() == ISD::FrameIndex) {
108 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
109 R1 = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
110 R2 = CurDAG->getTargetConstant(0, MVT::i32);
113 R2 = CurDAG->getTargetConstant(0, MVT::i32);
115 } else if (Addr.getOpcode() == ISD::ADD) {
116 R1 = Addr.getOperand(0);
117 R2 = Addr.getOperand(1);
120 R2 = CurDAG->getTargetConstant(0, MVT::i32);
125 bool AMDGPUDAGToDAGISel::SelectADDR(SDValue Addr, SDValue& R1, SDValue& R2) {
126 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
127 Addr.getOpcode() == ISD::TargetGlobalAddress) {
130 return SelectADDRParam(Addr, R1, R2);
134 bool AMDGPUDAGToDAGISel::SelectADDR64(SDValue Addr, SDValue& R1, SDValue& R2) {
135 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
136 Addr.getOpcode() == ISD::TargetGlobalAddress) {
140 if (Addr.getOpcode() == ISD::FrameIndex) {
141 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
142 R1 = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i64);
143 R2 = CurDAG->getTargetConstant(0, MVT::i64);
146 R2 = CurDAG->getTargetConstant(0, MVT::i64);
148 } else if (Addr.getOpcode() == ISD::ADD) {
149 R1 = Addr.getOperand(0);
150 R2 = Addr.getOperand(1);
153 R2 = CurDAG->getTargetConstant(0, MVT::i64);
158 SDNode *AMDGPUDAGToDAGISel::Select(SDNode *N) {
159 unsigned int Opc = N->getOpcode();
160 if (N->isMachineOpcode()) {
162 return NULL; // Already selected.
166 case ISD::BUILD_VECTOR: {
167 const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
168 if (ST.device()->getGeneration() > AMDGPUDeviceInfo::HD6XXX) {
171 // BUILD_VECTOR is usually lowered into an IMPLICIT_DEF + 4 INSERT_SUBREG
172 // that adds a 128 bits reg copy when going through TwoAddressInstructions
173 // pass. We want to avoid 128 bits copies as much as possible because they
174 // can't be bundled by our scheduler.
175 SDValue RegSeqArgs[9] = {
176 CurDAG->getTargetConstant(AMDGPU::R600_Reg128RegClassID, MVT::i32),
177 SDValue(), CurDAG->getTargetConstant(AMDGPU::sub0, MVT::i32),
178 SDValue(), CurDAG->getTargetConstant(AMDGPU::sub1, MVT::i32),
179 SDValue(), CurDAG->getTargetConstant(AMDGPU::sub2, MVT::i32),
180 SDValue(), CurDAG->getTargetConstant(AMDGPU::sub3, MVT::i32)
182 bool IsRegSeq = true;
183 for (unsigned i = 0; i < N->getNumOperands(); i++) {
184 if (dyn_cast<RegisterSDNode>(N->getOperand(i))) {
188 RegSeqArgs[2 * i + 1] = N->getOperand(i);
192 return CurDAG->SelectNodeTo(N, AMDGPU::REG_SEQUENCE, N->getVTList(),
193 RegSeqArgs, 2 * N->getNumOperands() + 1);
195 case ISD::BUILD_PAIR: {
196 SDValue RC, SubReg0, SubReg1;
197 const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
198 if (ST.device()->getGeneration() <= AMDGPUDeviceInfo::HD6XXX) {
201 if (N->getValueType(0) == MVT::i128) {
202 RC = CurDAG->getTargetConstant(AMDGPU::SReg_128RegClassID, MVT::i32);
203 SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0_sub1, MVT::i32);
204 SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub2_sub3, MVT::i32);
205 } else if (N->getValueType(0) == MVT::i64) {
206 RC = CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, MVT::i32);
207 SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0, MVT::i32);
208 SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub1, MVT::i32);
210 llvm_unreachable("Unhandled value type for BUILD_PAIR");
212 const SDValue Ops[] = { RC, N->getOperand(0), SubReg0,
213 N->getOperand(1), SubReg1 };
214 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE,
215 N->getDebugLoc(), N->getValueType(0), Ops);
218 case ISD::ConstantFP:
219 case ISD::Constant: {
220 const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
221 // XXX: Custom immediate lowering not implemented yet. Instead we use
222 // pseudo instructions defined in SIInstructions.td
223 if (ST.device()->getGeneration() > AMDGPUDeviceInfo::HD6XXX) {
226 const R600InstrInfo *TII = static_cast<const R600InstrInfo*>(TM.getInstrInfo());
228 uint64_t ImmValue = 0;
229 unsigned ImmReg = AMDGPU::ALU_LITERAL_X;
231 if (N->getOpcode() == ISD::ConstantFP) {
232 // XXX: 64-bit Immediates not supported yet
233 assert(N->getValueType(0) != MVT::f64);
235 ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N);
236 APFloat Value = C->getValueAPF();
237 float FloatValue = Value.convertToFloat();
238 if (FloatValue == 0.0) {
239 ImmReg = AMDGPU::ZERO;
240 } else if (FloatValue == 0.5) {
241 ImmReg = AMDGPU::HALF;
242 } else if (FloatValue == 1.0) {
243 ImmReg = AMDGPU::ONE;
245 ImmValue = Value.bitcastToAPInt().getZExtValue();
248 // XXX: 64-bit Immediates not supported yet
249 assert(N->getValueType(0) != MVT::i64);
251 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
252 if (C->getZExtValue() == 0) {
253 ImmReg = AMDGPU::ZERO;
254 } else if (C->getZExtValue() == 1) {
255 ImmReg = AMDGPU::ONE_INT;
257 ImmValue = C->getZExtValue();
261 for (SDNode::use_iterator Use = N->use_begin(), Next = llvm::next(Use);
262 Use != SDNode::use_end(); Use = Next) {
263 Next = llvm::next(Use);
264 std::vector<SDValue> Ops;
265 for (unsigned i = 0; i < Use->getNumOperands(); ++i) {
266 Ops.push_back(Use->getOperand(i));
269 if (!Use->isMachineOpcode()) {
270 if (ImmReg == AMDGPU::ALU_LITERAL_X) {
271 // We can only use literal constants (e.g. AMDGPU::ZERO,
272 // AMDGPU::ONE, etc) in machine opcodes.
276 if (!TII->isALUInstr(Use->getMachineOpcode()) ||
277 (TII->get(Use->getMachineOpcode()).TSFlags &
278 R600_InstFlag::VECTOR)) {
282 int ImmIdx = TII->getOperandIdx(Use->getMachineOpcode(), R600Operands::IMM);
283 assert(ImmIdx != -1);
285 // subtract one from ImmIdx, because the DST operand is usually index
286 // 0 for MachineInstrs, but we have no DST in the Ops vector.
289 // Check that we aren't already using an immediate.
290 // XXX: It's possible for an instruction to have more than one
291 // immediate operand, but this is not supported yet.
292 if (ImmReg == AMDGPU::ALU_LITERAL_X) {
293 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Use->getOperand(ImmIdx));
296 if (C->getZExtValue() != 0) {
297 // This instruction is already using an immediate.
301 // Set the immediate value
302 Ops[ImmIdx] = CurDAG->getTargetConstant(ImmValue, MVT::i32);
305 // Set the immediate register
306 Ops[Use.getOperandNo()] = CurDAG->getRegister(ImmReg, MVT::i32);
308 CurDAG->UpdateNodeOperands(*Use, Ops.data(), Use->getNumOperands());
313 SDNode *Result = SelectCode(N);
315 // Fold operands of selected node
317 const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
318 if (ST.device()->getGeneration() <= AMDGPUDeviceInfo::HD6XXX) {
319 const R600InstrInfo *TII =
320 static_cast<const R600InstrInfo*>(TM.getInstrInfo());
321 if (Result && Result->isMachineOpcode() &&
322 !(TII->get(Result->getMachineOpcode()).TSFlags & R600_InstFlag::VECTOR)
323 && TII->isALUInstr(Result->getMachineOpcode())) {
324 // Fold FNEG/FABS/CONST_ADDRESS
325 // TODO: Isel can generate multiple MachineInst, we need to recursively
327 bool IsModified = false;
329 std::vector<SDValue> Ops;
330 for(SDNode::op_iterator I = Result->op_begin(), E = Result->op_end();
333 IsModified = FoldOperands(Result->getMachineOpcode(), TII, Ops);
335 Result = CurDAG->UpdateNodeOperands(Result, Ops.data(), Ops.size());
337 } while (IsModified);
339 // If node has a single use which is CLAMP_R600, folds it
340 if (Result->hasOneUse() && Result->isMachineOpcode()) {
341 SDNode *PotentialClamp = *Result->use_begin();
342 if (PotentialClamp->isMachineOpcode() &&
343 PotentialClamp->getMachineOpcode() == AMDGPU::CLAMP_R600) {
345 TII->getOperandIdx(Result->getMachineOpcode(), R600Operands::CLAMP);
346 std::vector<SDValue> Ops;
347 unsigned NumOp = Result->getNumOperands();
348 for (unsigned i = 0; i < NumOp; ++i) {
349 Ops.push_back(Result->getOperand(i));
351 Ops[ClampIdx - 1] = CurDAG->getTargetConstant(1, MVT::i32);
352 Result = CurDAG->SelectNodeTo(PotentialClamp,
353 Result->getMachineOpcode(), PotentialClamp->getVTList(),
363 bool AMDGPUDAGToDAGISel::FoldOperands(unsigned Opcode,
364 const R600InstrInfo *TII, std::vector<SDValue> &Ops) {
366 TII->getOperandIdx(Opcode, R600Operands::SRC0),
367 TII->getOperandIdx(Opcode, R600Operands::SRC1),
368 TII->getOperandIdx(Opcode, R600Operands::SRC2)
371 TII->getOperandIdx(Opcode, R600Operands::SRC0_SEL),
372 TII->getOperandIdx(Opcode, R600Operands::SRC1_SEL),
373 TII->getOperandIdx(Opcode, R600Operands::SRC2_SEL)
376 TII->getOperandIdx(Opcode, R600Operands::SRC0_NEG),
377 TII->getOperandIdx(Opcode, R600Operands::SRC1_NEG),
378 TII->getOperandIdx(Opcode, R600Operands::SRC2_NEG)
381 TII->getOperandIdx(Opcode, R600Operands::SRC0_ABS),
382 TII->getOperandIdx(Opcode, R600Operands::SRC1_ABS),
386 for (unsigned i = 0; i < 3; i++) {
387 if (OperandIdx[i] < 0)
389 SDValue Operand = Ops[OperandIdx[i] - 1];
390 switch (Operand.getOpcode()) {
391 case AMDGPUISD::CONST_ADDRESS: {
393 if (Operand.getValueType().isVector() ||
394 !SelectGlobalValueConstantOffset(Operand.getOperand(0), CstOffset))
397 // Gather others constants values
398 std::vector<unsigned> Consts;
399 for (unsigned j = 0; j < 3; j++) {
400 int SrcIdx = OperandIdx[j];
403 if (RegisterSDNode *Reg = dyn_cast<RegisterSDNode>(Ops[SrcIdx - 1])) {
404 if (Reg->getReg() == AMDGPU::ALU_CONST) {
405 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Ops[SelIdx[j] - 1]);
406 Consts.push_back(Cst->getZExtValue());
411 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(CstOffset);
412 Consts.push_back(Cst->getZExtValue());
413 if (!TII->fitsConstReadLimitations(Consts))
416 Ops[OperandIdx[i] - 1] = CurDAG->getRegister(AMDGPU::ALU_CONST, MVT::f32);
417 Ops[SelIdx[i] - 1] = CstOffset;
423 Ops[OperandIdx[i] - 1] = Operand.getOperand(0);
424 Ops[NegIdx[i] - 1] = CurDAG->getTargetConstant(1, MVT::i32);
429 Ops[OperandIdx[i] - 1] = Operand.getOperand(0);
430 Ops[AbsIdx[i] - 1] = CurDAG->getTargetConstant(1, MVT::i32);
433 Ops[OperandIdx[i] - 1] = Operand.getOperand(0);
442 bool AMDGPUDAGToDAGISel::checkType(const Value *ptr, unsigned int addrspace) {
446 Type *ptrType = ptr->getType();
447 return dyn_cast<PointerType>(ptrType)->getAddressSpace() == addrspace;
450 const Value * AMDGPUDAGToDAGISel::getBasePointerValue(const Value *V) {
454 const Value *ret = NULL;
455 ValueMap<const Value *, bool> ValueBitMap;
456 std::queue<const Value *, std::list<const Value *> > ValueQueue;
458 while (!ValueQueue.empty()) {
459 V = ValueQueue.front();
460 if (ValueBitMap.find(V) == ValueBitMap.end()) {
461 ValueBitMap[V] = true;
462 if (dyn_cast<Argument>(V) && dyn_cast<PointerType>(V->getType())) {
465 } else if (dyn_cast<GlobalVariable>(V)) {
468 } else if (dyn_cast<Constant>(V)) {
469 const ConstantExpr *CE = dyn_cast<ConstantExpr>(V);
471 ValueQueue.push(CE->getOperand(0));
473 } else if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
476 } else if (const Instruction *I = dyn_cast<Instruction>(V)) {
477 uint32_t numOps = I->getNumOperands();
478 for (uint32_t x = 0; x < numOps; ++x) {
479 ValueQueue.push(I->getOperand(x));
482 assert(!"Found a Value that we didn't know how to handle!");
490 bool AMDGPUDAGToDAGISel::isGlobalStore(const StoreSDNode *N) {
491 return checkType(N->getSrcValue(), AMDGPUAS::GLOBAL_ADDRESS);
494 bool AMDGPUDAGToDAGISel::isPrivateStore(const StoreSDNode *N) {
495 return (!checkType(N->getSrcValue(), AMDGPUAS::LOCAL_ADDRESS)
496 && !checkType(N->getSrcValue(), AMDGPUAS::GLOBAL_ADDRESS)
497 && !checkType(N->getSrcValue(), AMDGPUAS::REGION_ADDRESS));
500 bool AMDGPUDAGToDAGISel::isLocalStore(const StoreSDNode *N) {
501 return checkType(N->getSrcValue(), AMDGPUAS::LOCAL_ADDRESS);
504 bool AMDGPUDAGToDAGISel::isRegionStore(const StoreSDNode *N) {
505 return checkType(N->getSrcValue(), AMDGPUAS::REGION_ADDRESS);
508 bool AMDGPUDAGToDAGISel::isConstantLoad(const LoadSDNode *N, int cbID) {
509 if (checkType(N->getSrcValue(), AMDGPUAS::CONSTANT_ADDRESS)) {
512 MachineMemOperand *MMO = N->getMemOperand();
513 const Value *V = MMO->getValue();
514 const Value *BV = getBasePointerValue(V);
517 && ((V && dyn_cast<GlobalValue>(V))
518 || (BV && dyn_cast<GlobalValue>(
519 getBasePointerValue(MMO->getValue()))))) {
520 return checkType(N->getSrcValue(), AMDGPUAS::PRIVATE_ADDRESS);
526 bool AMDGPUDAGToDAGISel::isGlobalLoad(const LoadSDNode *N) {
527 return checkType(N->getSrcValue(), AMDGPUAS::GLOBAL_ADDRESS);
530 bool AMDGPUDAGToDAGISel::isParamLoad(const LoadSDNode *N) {
531 return checkType(N->getSrcValue(), AMDGPUAS::PARAM_I_ADDRESS);
534 bool AMDGPUDAGToDAGISel::isLocalLoad(const LoadSDNode *N) {
535 return checkType(N->getSrcValue(), AMDGPUAS::LOCAL_ADDRESS);
538 bool AMDGPUDAGToDAGISel::isRegionLoad(const LoadSDNode *N) {
539 return checkType(N->getSrcValue(), AMDGPUAS::REGION_ADDRESS);
542 bool AMDGPUDAGToDAGISel::isCPLoad(const LoadSDNode *N) {
543 MachineMemOperand *MMO = N->getMemOperand();
544 if (checkType(N->getSrcValue(), AMDGPUAS::PRIVATE_ADDRESS)) {
546 const Value *V = MMO->getValue();
547 const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V);
548 if (PSV && PSV == PseudoSourceValue::getConstantPool()) {
556 bool AMDGPUDAGToDAGISel::isPrivateLoad(const LoadSDNode *N) {
557 if (checkType(N->getSrcValue(), AMDGPUAS::PRIVATE_ADDRESS)) {
558 // Check to make sure we are not a constant pool load or a constant load
559 // that is marked as a private load
560 if (isCPLoad(N) || isConstantLoad(N, -1)) {
564 if (!checkType(N->getSrcValue(), AMDGPUAS::LOCAL_ADDRESS)
565 && !checkType(N->getSrcValue(), AMDGPUAS::GLOBAL_ADDRESS)
566 && !checkType(N->getSrcValue(), AMDGPUAS::REGION_ADDRESS)
567 && !checkType(N->getSrcValue(), AMDGPUAS::CONSTANT_ADDRESS)
568 && !checkType(N->getSrcValue(), AMDGPUAS::PARAM_D_ADDRESS)
569 && !checkType(N->getSrcValue(), AMDGPUAS::PARAM_I_ADDRESS)) {
575 const char *AMDGPUDAGToDAGISel::getPassName() const {
576 return "AMDGPU DAG->DAG Pattern Instruction Selection";
584 ///==== AMDGPU Functions ====///
586 bool AMDGPUDAGToDAGISel::SelectGlobalValueConstantOffset(SDValue Addr,
588 if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Addr)) {
589 IntPtr = CurDAG->getIntPtrConstant(Cst->getZExtValue() / 4, true);
595 bool AMDGPUDAGToDAGISel::SelectGlobalValueVariableOffset(SDValue Addr,
596 SDValue& BaseReg, SDValue &Offset) {
597 if (!dyn_cast<ConstantSDNode>(Addr)) {
599 Offset = CurDAG->getIntPtrConstant(0, true);
605 bool AMDGPUDAGToDAGISel::SelectADDRVTX_READ(SDValue Addr, SDValue &Base,
607 ConstantSDNode * IMMOffset;
609 if (Addr.getOpcode() == ISD::ADD
610 && (IMMOffset = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
611 && isInt<16>(IMMOffset->getZExtValue())) {
613 Base = Addr.getOperand(0);
614 Offset = CurDAG->getTargetConstant(IMMOffset->getZExtValue(), MVT::i32);
616 // If the pointer address is constant, we can move it to the offset field.
617 } else if ((IMMOffset = dyn_cast<ConstantSDNode>(Addr))
618 && isInt<16>(IMMOffset->getZExtValue())) {
619 Base = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
620 CurDAG->getEntryNode().getDebugLoc(),
621 AMDGPU::ZERO, MVT::i32);
622 Offset = CurDAG->getTargetConstant(IMMOffset->getZExtValue(), MVT::i32);
626 // Default case, no offset
628 Offset = CurDAG->getTargetConstant(0, MVT::i32);
632 bool AMDGPUDAGToDAGISel::SelectADDRIndirect(SDValue Addr, SDValue &Base,
636 if ((C = dyn_cast<ConstantSDNode>(Addr))) {
637 Base = CurDAG->getRegister(AMDGPU::INDIRECT_BASE_ADDR, MVT::i32);
638 Offset = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i32);
639 } else if ((Addr.getOpcode() == ISD::ADD || Addr.getOpcode() == ISD::OR) &&
640 (C = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))) {
641 Base = Addr.getOperand(0);
642 Offset = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i32);
645 Offset = CurDAG->getTargetConstant(0, MVT::i32);
651 void AMDGPUDAGToDAGISel::PostprocessISelDAG() {
653 // Go over all selected nodes and try to fold them a bit more
654 const AMDGPUTargetLowering& Lowering = ((const AMDGPUTargetLowering&)TLI);
655 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
656 E = CurDAG->allnodes_end(); I != E; ++I) {
658 MachineSDNode *Node = dyn_cast<MachineSDNode>(I);
662 SDNode *ResNode = Lowering.PostISelFolding(Node, *CurDAG);
664 ReplaceUses(Node, ResNode);