contrib/llvm/lib/Target/RISCV/RISCV.td

   1 //===-- RISCV.td - Describe the RISCV Target Machine -------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9
  10 include "llvm/Target/Target.td"
  11
  12 //===----------------------------------------------------------------------===//
  13 // RISC-V subtarget features and instruction predicates.
  14 //===----------------------------------------------------------------------===//
  15
  16 def FeatureStdExtM
  17     : SubtargetFeature<"m", "HasStdExtM", "true",
  18                        "'M' (Integer Multiplication and Division)">;
  19 def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">,
  20                            AssemblerPredicate<"FeatureStdExtM">;
  21
  22 def FeatureStdExtA
  23     : SubtargetFeature<"a", "HasStdExtA", "true",
  24                        "'A' (Atomic Instructions)">;
  25 def HasStdExtA : Predicate<"Subtarget->hasStdExtA()">,
  26                            AssemblerPredicate<"FeatureStdExtA">;
  27
  28 def FeatureStdExtF
  29     : SubtargetFeature<"f", "HasStdExtF", "true",
  30                        "'F' (Single-Precision Floating-Point)">;
  31 def HasStdExtF : Predicate<"Subtarget->hasStdExtF()">,
  32                            AssemblerPredicate<"FeatureStdExtF">;
  33
  34 def FeatureStdExtD
  35     : SubtargetFeature<"d", "HasStdExtD", "true",
  36                        "'D' (Double-Precision Floating-Point)",
  37                        [FeatureStdExtF]>;
  38 def HasStdExtD : Predicate<"Subtarget->hasStdExtD()">,
  39                            AssemblerPredicate<"FeatureStdExtD">;
  40
  41 def FeatureStdExtC
  42     : SubtargetFeature<"c", "HasStdExtC", "true",
  43                        "'C' (Compressed Instructions)">;
  44 def HasStdExtC : Predicate<"Subtarget->hasStdExtC()">,
  45                            AssemblerPredicate<"FeatureStdExtC">;
  46
  47
  48 def Feature64Bit
  49     : SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">;
  50 def IsRV64 : Predicate<"Subtarget->is64Bit()">,
  51                        AssemblerPredicate<"Feature64Bit">;
  52 def IsRV32 : Predicate<"!Subtarget->is64Bit()">,
  53                        AssemblerPredicate<"!Feature64Bit">;
  54
  55 def RV64           : HwMode<"+64bit">;
  56 def RV32           : HwMode<"-64bit">;
  57
  58 def FeatureRelax
  59     : SubtargetFeature<"relax", "EnableLinkerRelax", "true",
  60                        "Enable Linker relaxation.">;
  61
  62 //===----------------------------------------------------------------------===//
  63 // Registers, calling conventions, instruction descriptions.
  64 //===----------------------------------------------------------------------===//
  65
  66 include "RISCVRegisterInfo.td"
  67 include "RISCVCallingConv.td"
  68 include "RISCVInstrInfo.td"
  69
  70 //===----------------------------------------------------------------------===//
  71 // RISC-V processors supported.
  72 //===----------------------------------------------------------------------===//
  73
  74 def : ProcessorModel<"generic-rv32", NoSchedModel, []>;
  75
  76 def : ProcessorModel<"generic-rv64", NoSchedModel, [Feature64Bit]>;
  77
  78 //===----------------------------------------------------------------------===//
  79 // Define the RISC-V target.
  80 //===----------------------------------------------------------------------===//
  81
  82 def RISCVInstrInfo : InstrInfo {
  83   let guessInstructionProperties = 0;
  84 }
  85
  86 def RISCVAsmParser : AsmParser {
  87   let ShouldEmitMatchRegisterAltName = 1;
  88   let AllowDuplicateRegisterNames = 1;
  89 }
  90
  91 def RISCVAsmWriter : AsmWriter {
  92   int PassSubtarget = 1;
  93 }
  94
  95 def RISCV : Target {
  96   let InstructionSet = RISCVInstrInfo;
  97   let AssemblyParsers = [RISCVAsmParser];
  98   let AssemblyWriters = [RISCVAsmWriter];
  99   let AllowRegisterRenaming = 1;
 100 }