1 //===-- RISCVInstrInfoA.td - RISC-V 'A' instructions -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the RISC-V instructions from the standard 'A', Atomic
11 // Instructions extension.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Instruction class templates
17 //===----------------------------------------------------------------------===//
19 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
20 class LR_r<bit aq, bit rl, bits<3> funct3, string opcodestr>
21 : RVInstRAtomic<0b00010, aq, rl, funct3, OPC_AMO,
22 (outs GPR:$rd), (ins GPR:$rs1),
23 opcodestr, "$rd, (${rs1})"> {
27 multiclass LR_r_aq_rl<bits<3> funct3, string opcodestr> {
28 def "" : LR_r<0, 0, funct3, opcodestr>;
29 def _AQ : LR_r<1, 0, funct3, opcodestr # ".aq">;
30 def _RL : LR_r<0, 1, funct3, opcodestr # ".rl">;
31 def _AQ_RL : LR_r<1, 1, funct3, opcodestr # ".aqrl">;
34 let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in
35 class AMO_rr<bits<5> funct5, bit aq, bit rl, bits<3> funct3, string opcodestr>
36 : RVInstRAtomic<funct5, aq, rl, funct3, OPC_AMO,
37 (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
38 opcodestr, "$rd, $rs2, (${rs1})">;
40 multiclass AMO_rr_aq_rl<bits<5> funct5, bits<3> funct3, string opcodestr> {
41 def "" : AMO_rr<funct5, 0, 0, funct3, opcodestr>;
42 def _AQ : AMO_rr<funct5, 1, 0, funct3, opcodestr # ".aq">;
43 def _RL : AMO_rr<funct5, 0, 1, funct3, opcodestr # ".rl">;
44 def _AQ_RL : AMO_rr<funct5, 1, 1, funct3, opcodestr # ".aqrl">;
47 //===----------------------------------------------------------------------===//
49 //===----------------------------------------------------------------------===//
51 let Predicates = [HasStdExtA] in {
52 defm LR_W : LR_r_aq_rl<0b010, "lr.w">;
53 defm SC_W : AMO_rr_aq_rl<0b00011, 0b010, "sc.w">;
54 defm AMOSWAP_W : AMO_rr_aq_rl<0b00001, 0b010, "amoswap.w">;
55 defm AMOADD_W : AMO_rr_aq_rl<0b00000, 0b010, "amoadd.w">;
56 defm AMOXOR_W : AMO_rr_aq_rl<0b00100, 0b010, "amoxor.w">;
57 defm AMOAND_W : AMO_rr_aq_rl<0b01100, 0b010, "amoand.w">;
58 defm AMOOR_W : AMO_rr_aq_rl<0b01000, 0b010, "amoor.w">;
59 defm AMOMIN_W : AMO_rr_aq_rl<0b10000, 0b010, "amomin.w">;
60 defm AMOMAX_W : AMO_rr_aq_rl<0b10100, 0b010, "amomax.w">;
61 defm AMOMINU_W : AMO_rr_aq_rl<0b11000, 0b010, "amominu.w">;
62 defm AMOMAXU_W : AMO_rr_aq_rl<0b11100, 0b010, "amomaxu.w">;
63 } // Predicates = [HasStdExtA]
65 let Predicates = [HasStdExtA, IsRV64] in {
66 defm LR_D : LR_r_aq_rl<0b011, "lr.d">;
67 defm SC_D : AMO_rr_aq_rl<0b00011, 0b011, "sc.d">;
68 defm AMOSWAP_D : AMO_rr_aq_rl<0b00001, 0b011, "amoswap.d">;
69 defm AMOADD_D : AMO_rr_aq_rl<0b00000, 0b011, "amoadd.d">;
70 defm AMOXOR_D : AMO_rr_aq_rl<0b00100, 0b011, "amoxor.d">;
71 defm AMOAND_D : AMO_rr_aq_rl<0b01100, 0b011, "amoand.d">;
72 defm AMOOR_D : AMO_rr_aq_rl<0b01000, 0b011, "amoor.d">;
73 defm AMOMIN_D : AMO_rr_aq_rl<0b10000, 0b011, "amomin.d">;
74 defm AMOMAX_D : AMO_rr_aq_rl<0b10100, 0b011, "amomax.d">;
75 defm AMOMINU_D : AMO_rr_aq_rl<0b11000, 0b011, "amominu.d">;
76 defm AMOMAXU_D : AMO_rr_aq_rl<0b11100, 0b011, "amomaxu.d">;
77 } // Predicates = [HasStedExtA, IsRV64]
79 //===----------------------------------------------------------------------===//
80 // Pseudo-instructions and codegen patterns
81 //===----------------------------------------------------------------------===//
83 let Predicates = [HasStdExtA] in {
85 /// Atomic loads and stores
87 // Fences will be inserted for atomic load/stores according to the logic in
88 // RISCVTargetLowering::{emitLeadingFence,emitTrailingFence}.
90 defm : LdPat<atomic_load_8, LB>;
91 defm : LdPat<atomic_load_16, LH>;
92 defm : LdPat<atomic_load_32, LW>;
94 defm : StPat<atomic_store_8, SB, GPR>;
95 defm : StPat<atomic_store_16, SH, GPR>;
96 defm : StPat<atomic_store_32, SW, GPR>;
97 } // Predicates = [HasStdExtF]