1 //===-- RISCVInstrInfoM.td - RISC-V 'M' instructions -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the RISC-V instructions from the standard 'M', Integer
11 // Multiplication and Division instruction set extension.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
19 let Predicates = [HasStdExtM] in {
20 def MUL : ALU_rr<0b0000001, 0b000, "mul">;
21 def MULH : ALU_rr<0b0000001, 0b001, "mulh">;
22 def MULHSU : ALU_rr<0b0000001, 0b010, "mulhsu">;
23 def MULHU : ALU_rr<0b0000001, 0b011, "mulhu">;
24 def DIV : ALU_rr<0b0000001, 0b100, "div">;
25 def DIVU : ALU_rr<0b0000001, 0b101, "divu">;
26 def REM : ALU_rr<0b0000001, 0b110, "rem">;
27 def REMU : ALU_rr<0b0000001, 0b111, "remu">;
28 } // Predicates = [HasStdExtM]
30 let Predicates = [HasStdExtM, IsRV64] in {
31 def MULW : ALUW_rr<0b0000001, 0b000, "mulw">;
32 def DIVW : ALUW_rr<0b0000001, 0b100, "divw">;
33 def DIVUW : ALUW_rr<0b0000001, 0b101, "divuw">;
34 def REMW : ALUW_rr<0b0000001, 0b110, "remw">;
35 def REMUW : ALUW_rr<0b0000001, 0b111, "remuw">;
36 } // Predicates = [HasStdExtM, IsRV64]
38 //===----------------------------------------------------------------------===//
39 // Pseudo-instructions and codegen patterns
40 //===----------------------------------------------------------------------===//
42 let Predicates = [HasStdExtM] in {
43 def : PatGprGpr<mul, MUL>;
44 def : PatGprGpr<mulhs, MULH>;
45 def : PatGprGpr<mulhu, MULHU>;
46 // No ISDOpcode for mulhsu
47 def : PatGprGpr<sdiv, DIV>;
48 def : PatGprGpr<udiv, DIVU>;
49 def : PatGprGpr<srem, REM>;
50 def : PatGprGpr<urem, REMU>;
51 } // Predicates = [HasStdExtM]