1 //===-- RISCVBaseInfo.h - Top level definitions for RISCV MC ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains small standalone enum definitions for the RISCV target
11 // useful for the compiler back-end and the MC libraries.
13 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
15 #define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
17 #include "MCTargetDesc/RISCVMCTargetDesc.h"
18 #include "llvm/ADT/StringRef.h"
19 #include "llvm/ADT/StringSwitch.h"
20 #include "llvm/MC/SubtargetFeature.h"
24 // RISCVII - This namespace holds all of the target specific flags that
25 // instruction info tracks. All definitions must match RISCVInstrFormats.td.
56 } // namespace RISCVII
58 // Describes the predecessor/successor bits used in the FENCE instruction.
59 namespace RISCVFenceField {
68 // Describes the supported floating point rounding mode encodings.
69 namespace RISCVFPRndMode {
80 inline static StringRef roundingModeToString(RoundingMode RndMode) {
83 llvm_unreachable("Unknown floating point rounding mode");
84 case RISCVFPRndMode::RNE:
86 case RISCVFPRndMode::RTZ:
88 case RISCVFPRndMode::RDN:
90 case RISCVFPRndMode::RUP:
92 case RISCVFPRndMode::RMM:
94 case RISCVFPRndMode::DYN:
99 inline static RoundingMode stringToRoundingMode(StringRef Str) {
100 return StringSwitch<RoundingMode>(Str)
101 .Case("rne", RISCVFPRndMode::RNE)
102 .Case("rtz", RISCVFPRndMode::RTZ)
103 .Case("rdn", RISCVFPRndMode::RDN)
104 .Case("rup", RISCVFPRndMode::RUP)
105 .Case("rmm", RISCVFPRndMode::RMM)
106 .Case("dyn", RISCVFPRndMode::DYN)
107 .Default(RISCVFPRndMode::Invalid);
110 inline static bool isValidRoundingMode(unsigned Mode) {
114 case RISCVFPRndMode::RNE:
115 case RISCVFPRndMode::RTZ:
116 case RISCVFPRndMode::RDN:
117 case RISCVFPRndMode::RUP:
118 case RISCVFPRndMode::RMM:
119 case RISCVFPRndMode::DYN:
123 } // namespace RISCVFPRndMode
125 namespace RISCVSysReg {
129 // FIXME: add these additional fields when needed.
130 // Privilege Access: Read, Write, Read-Only.
131 // unsigned ReadWrite;
132 // Privilege Mode: User, System or Machine.
136 // Register number without the privilege bits.
138 FeatureBitset FeaturesRequired;
141 bool haveRequiredFeatures(FeatureBitset ActiveFeatures) const {
142 // Not in 32-bit mode.
143 if (isRV32Only && ActiveFeatures[RISCV::Feature64Bit])
145 // No required feature associated with the system register.
146 if (FeaturesRequired.none())
148 return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
152 #define GET_SysRegsList_DECL
153 #include "RISCVGenSystemOperands.inc"
154 } // end namespace RISCVSysReg