1 //===-- SparcISelDAGToDAG.cpp - A dag to dag inst selector for Sparc ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the SPARC target.
12 //===----------------------------------------------------------------------===//
14 #include "SparcTargetMachine.h"
15 #include "llvm/CodeGen/MachineRegisterInfo.h"
16 #include "llvm/CodeGen/SelectionDAGISel.h"
17 #include "llvm/IR/Intrinsics.h"
18 #include "llvm/Support/Debug.h"
19 #include "llvm/Support/ErrorHandling.h"
20 #include "llvm/Support/raw_ostream.h"
23 //===----------------------------------------------------------------------===//
24 // Instruction Selector Implementation
25 //===----------------------------------------------------------------------===//
27 //===--------------------------------------------------------------------===//
28 /// SparcDAGToDAGISel - SPARC specific code to select SPARC machine
29 /// instructions for SelectionDAG operations.
32 class SparcDAGToDAGISel : public SelectionDAGISel {
33 /// Subtarget - Keep a pointer to the Sparc Subtarget around so that we can
34 /// make the right decision when generating code for different targets.
35 const SparcSubtarget *Subtarget;
37 explicit SparcDAGToDAGISel(SparcTargetMachine &tm) : SelectionDAGISel(tm) {}
39 bool runOnMachineFunction(MachineFunction &MF) override {
40 Subtarget = &MF.getSubtarget<SparcSubtarget>();
41 return SelectionDAGISel::runOnMachineFunction(MF);
44 void Select(SDNode *N) override;
46 // Complex Pattern Selectors.
47 bool SelectADDRrr(SDValue N, SDValue &R1, SDValue &R2);
48 bool SelectADDRri(SDValue N, SDValue &Base, SDValue &Offset);
50 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
51 /// inline asm expressions.
52 bool SelectInlineAsmMemoryOperand(const SDValue &Op,
53 unsigned ConstraintID,
54 std::vector<SDValue> &OutOps) override;
56 StringRef getPassName() const override {
57 return "SPARC DAG->DAG Pattern Instruction Selection";
60 // Include the pieces autogenerated from the target description.
61 #include "SparcGenDAGISel.inc"
64 SDNode* getGlobalBaseReg();
65 bool tryInlineAsm(SDNode *N);
67 } // end anonymous namespace
69 SDNode* SparcDAGToDAGISel::getGlobalBaseReg() {
70 unsigned GlobalBaseReg = Subtarget->getInstrInfo()->getGlobalBaseReg(MF);
71 return CurDAG->getRegister(GlobalBaseReg,
72 TLI->getPointerTy(CurDAG->getDataLayout()))
76 bool SparcDAGToDAGISel::SelectADDRri(SDValue Addr,
77 SDValue &Base, SDValue &Offset) {
78 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
79 Base = CurDAG->getTargetFrameIndex(
80 FIN->getIndex(), TLI->getPointerTy(CurDAG->getDataLayout()));
81 Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32);
84 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
85 Addr.getOpcode() == ISD::TargetGlobalAddress ||
86 Addr.getOpcode() == ISD::TargetGlobalTLSAddress)
87 return false; // direct calls.
89 if (Addr.getOpcode() == ISD::ADD) {
90 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
91 if (isInt<13>(CN->getSExtValue())) {
92 if (FrameIndexSDNode *FIN =
93 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
94 // Constant offset from frame ref.
95 Base = CurDAG->getTargetFrameIndex(
96 FIN->getIndex(), TLI->getPointerTy(CurDAG->getDataLayout()));
98 Base = Addr.getOperand(0);
100 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), SDLoc(Addr),
105 if (Addr.getOperand(0).getOpcode() == SPISD::Lo) {
106 Base = Addr.getOperand(1);
107 Offset = Addr.getOperand(0).getOperand(0);
110 if (Addr.getOperand(1).getOpcode() == SPISD::Lo) {
111 Base = Addr.getOperand(0);
112 Offset = Addr.getOperand(1).getOperand(0);
117 Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32);
121 bool SparcDAGToDAGISel::SelectADDRrr(SDValue Addr, SDValue &R1, SDValue &R2) {
122 if (Addr.getOpcode() == ISD::FrameIndex) return false;
123 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
124 Addr.getOpcode() == ISD::TargetGlobalAddress ||
125 Addr.getOpcode() == ISD::TargetGlobalTLSAddress)
126 return false; // direct calls.
128 if (Addr.getOpcode() == ISD::ADD) {
129 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
130 if (isInt<13>(CN->getSExtValue()))
131 return false; // Let the reg+imm pattern catch this!
132 if (Addr.getOperand(0).getOpcode() == SPISD::Lo ||
133 Addr.getOperand(1).getOpcode() == SPISD::Lo)
134 return false; // Let the reg+imm pattern catch this!
135 R1 = Addr.getOperand(0);
136 R2 = Addr.getOperand(1);
141 R2 = CurDAG->getRegister(SP::G0, TLI->getPointerTy(CurDAG->getDataLayout()));
146 // Re-assemble i64 arguments split up in SelectionDAGBuilder's
147 // visitInlineAsm / GetRegistersForValue functions.
149 // Note: This function was copied from, and is essentially identical
150 // to ARMISelDAGToDAG::SelectInlineAsm. It is very unfortunate that
151 // such hacking-up is necessary; a rethink of how inline asm operands
152 // are handled may be in order to make doing this more sane.
154 // TODO: fix inline asm support so I can simply tell it that 'i64'
155 // inputs to asm need to be allocated to the IntPair register type,
156 // and have that work. Then, delete this function.
157 bool SparcDAGToDAGISel::tryInlineAsm(SDNode *N){
158 std::vector<SDValue> AsmNodeOperands;
160 bool Changed = false;
161 unsigned NumOps = N->getNumOperands();
163 // Normally, i64 data is bounded to two arbitrary GPRs for "%r"
164 // constraint. However, some instructions (e.g. ldd/std) require
165 // (even/even+1) GPRs.
167 // So, here, we check for this case, and mutate the inlineasm to use
168 // a single IntPair register instead, which guarantees such even/odd
172 SDValue Glue = N->getGluedNode() ? N->getOperand(NumOps-1)
173 : SDValue(nullptr,0);
175 SmallVector<bool, 8> OpChanged;
176 // Glue node will be appended late.
177 for(unsigned i = 0, e = N->getGluedNode() ? NumOps - 1 : NumOps; i < e; ++i) {
178 SDValue op = N->getOperand(i);
179 AsmNodeOperands.push_back(op);
181 if (i < InlineAsm::Op_FirstOperand)
184 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(i))) {
185 Flag = C->getZExtValue();
186 Kind = InlineAsm::getKind(Flag);
191 // Immediate operands to inline asm in the SelectionDAG are modeled with
192 // two operands. The first is a constant of value InlineAsm::Kind_Imm, and
193 // the second is a constant with the value of the immediate. If we get here
194 // and we have a Kind_Imm, skip the next operand, and continue.
195 if (Kind == InlineAsm::Kind_Imm) {
196 SDValue op = N->getOperand(++i);
197 AsmNodeOperands.push_back(op);
201 unsigned NumRegs = InlineAsm::getNumOperandRegisters(Flag);
203 OpChanged.push_back(false);
206 bool IsTiedToChangedOp = false;
207 // If it's a use that is tied with a previous def, it has no
208 // reg class constraint.
209 if (Changed && InlineAsm::isUseOperandTiedToDef(Flag, DefIdx))
210 IsTiedToChangedOp = OpChanged[DefIdx];
212 if (Kind != InlineAsm::Kind_RegUse && Kind != InlineAsm::Kind_RegDef
213 && Kind != InlineAsm::Kind_RegDefEarlyClobber)
217 bool HasRC = InlineAsm::hasRegClassConstraint(Flag, RC);
218 if ((!IsTiedToChangedOp && (!HasRC || RC != SP::IntRegsRegClassID))
222 assert((i+2 < NumOps) && "Invalid number of operands in inline asm");
223 SDValue V0 = N->getOperand(i+1);
224 SDValue V1 = N->getOperand(i+2);
225 unsigned Reg0 = cast<RegisterSDNode>(V0)->getReg();
226 unsigned Reg1 = cast<RegisterSDNode>(V1)->getReg();
228 MachineRegisterInfo &MRI = MF->getRegInfo();
230 if (Kind == InlineAsm::Kind_RegDef ||
231 Kind == InlineAsm::Kind_RegDefEarlyClobber) {
232 // Replace the two GPRs with 1 GPRPair and copy values from GPRPair to
233 // the original GPRs.
235 unsigned GPVR = MRI.createVirtualRegister(&SP::IntPairRegClass);
236 PairedReg = CurDAG->getRegister(GPVR, MVT::v2i32);
237 SDValue Chain = SDValue(N,0);
239 SDNode *GU = N->getGluedUser();
240 SDValue RegCopy = CurDAG->getCopyFromReg(Chain, dl, GPVR, MVT::v2i32,
243 // Extract values from a GPRPair reg and copy to the original GPR reg.
244 SDValue Sub0 = CurDAG->getTargetExtractSubreg(SP::sub_even, dl, MVT::i32,
246 SDValue Sub1 = CurDAG->getTargetExtractSubreg(SP::sub_odd, dl, MVT::i32,
248 SDValue T0 = CurDAG->getCopyToReg(Sub0, dl, Reg0, Sub0,
249 RegCopy.getValue(1));
250 SDValue T1 = CurDAG->getCopyToReg(Sub1, dl, Reg1, Sub1, T0.getValue(1));
252 // Update the original glue user.
253 std::vector<SDValue> Ops(GU->op_begin(), GU->op_end()-1);
254 Ops.push_back(T1.getValue(1));
255 CurDAG->UpdateNodeOperands(GU, Ops);
258 // For Kind == InlineAsm::Kind_RegUse, we first copy two GPRs into a
259 // GPRPair and then pass the GPRPair to the inline asm.
260 SDValue Chain = AsmNodeOperands[InlineAsm::Op_InputChain];
262 // As REG_SEQ doesn't take RegisterSDNode, we copy them first.
263 SDValue T0 = CurDAG->getCopyFromReg(Chain, dl, Reg0, MVT::i32,
265 SDValue T1 = CurDAG->getCopyFromReg(Chain, dl, Reg1, MVT::i32,
267 SDValue Pair = SDValue(
268 CurDAG->getMachineNode(
269 TargetOpcode::REG_SEQUENCE, dl, MVT::v2i32,
271 CurDAG->getTargetConstant(SP::IntPairRegClassID, dl,
274 CurDAG->getTargetConstant(SP::sub_even, dl, MVT::i32),
276 CurDAG->getTargetConstant(SP::sub_odd, dl, MVT::i32),
280 // Copy REG_SEQ into a GPRPair-typed VR and replace the original two
281 // i32 VRs of inline asm with it.
282 unsigned GPVR = MRI.createVirtualRegister(&SP::IntPairRegClass);
283 PairedReg = CurDAG->getRegister(GPVR, MVT::v2i32);
284 Chain = CurDAG->getCopyToReg(T1, dl, GPVR, Pair, T1.getValue(1));
286 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
287 Glue = Chain.getValue(1);
292 if(PairedReg.getNode()) {
293 OpChanged[OpChanged.size() -1 ] = true;
294 Flag = InlineAsm::getFlagWord(Kind, 1 /* RegNum*/);
295 if (IsTiedToChangedOp)
296 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, DefIdx);
298 Flag = InlineAsm::getFlagWordForRegClass(Flag, SP::IntPairRegClassID);
299 // Replace the current flag.
300 AsmNodeOperands[AsmNodeOperands.size() -1] = CurDAG->getTargetConstant(
302 // Add the new register node and skip the original two GPRs.
303 AsmNodeOperands.push_back(PairedReg);
304 // Skip the next two GPRs.
310 AsmNodeOperands.push_back(Glue);
314 SDValue New = CurDAG->getNode(ISD::INLINEASM, SDLoc(N),
315 CurDAG->getVTList(MVT::Other, MVT::Glue), AsmNodeOperands);
317 ReplaceNode(N, New.getNode());
321 void SparcDAGToDAGISel::Select(SDNode *N) {
323 if (N->isMachineOpcode()) {
325 return; // Already selected.
328 switch (N->getOpcode()) {
330 case ISD::INLINEASM: {
335 case SPISD::GLOBAL_BASE_REG:
336 ReplaceNode(N, getGlobalBaseReg());
341 // sdivx / udivx handle 64-bit divides.
342 if (N->getValueType(0) == MVT::i64)
344 // FIXME: should use a custom expander to expose the SRA to the dag.
345 SDValue DivLHS = N->getOperand(0);
346 SDValue DivRHS = N->getOperand(1);
348 // Set the Y register to the high-part.
350 if (N->getOpcode() == ISD::SDIV) {
351 TopPart = SDValue(CurDAG->getMachineNode(SP::SRAri, dl, MVT::i32, DivLHS,
352 CurDAG->getTargetConstant(31, dl, MVT::i32)),
355 TopPart = CurDAG->getRegister(SP::G0, MVT::i32);
357 TopPart = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, SP::Y, TopPart,
361 // FIXME: Handle div by immediate.
362 unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
363 // SDIV is a hardware erratum on some LEON2 processors. Replace it with SDIVcc here.
364 if (((SparcTargetMachine&)TM).getSubtargetImpl()->performSDIVReplace()
366 Opcode == SP::SDIVrr) {
367 Opcode = SP::SDIVCCrr;
369 CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, TopPart);
378 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
379 /// inline asm expressions.
381 SparcDAGToDAGISel::SelectInlineAsmMemoryOperand(const SDValue &Op,
382 unsigned ConstraintID,
383 std::vector<SDValue> &OutOps) {
385 switch (ConstraintID) {
386 default: return true;
387 case InlineAsm::Constraint_i:
388 case InlineAsm::Constraint_o:
389 case InlineAsm::Constraint_m: // memory
390 if (!SelectADDRrr(Op, Op0, Op1))
391 SelectADDRri(Op, Op0, Op1);
395 OutOps.push_back(Op0);
396 OutOps.push_back(Op1);
400 /// createSparcISelDag - This pass converts a legalized DAG into a
401 /// SPARC-specific DAG, ready for instruction scheduling.
403 FunctionPass *llvm::createSparcISelDag(SparcTargetMachine &TM) {
404 return new SparcDAGToDAGISel(TM);