1 //===-- SparcInstrInfo.td - Target Description for Sparc Target -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Sparc instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Instruction format superclass
16 //===----------------------------------------------------------------------===//
18 include "SparcInstrFormats.td"
20 //===----------------------------------------------------------------------===//
21 // Feature predicates.
22 //===----------------------------------------------------------------------===//
24 // True when generating 32-bit code.
25 def Is32Bit : Predicate<"!Subtarget->is64Bit()">;
27 // True when generating 64-bit code. This also implies HasV9.
28 def Is64Bit : Predicate<"Subtarget->is64Bit()">;
30 def UseSoftMulDiv : Predicate<"Subtarget->useSoftMulDiv()">,
31 AssemblerPredicate<"FeatureSoftMulDiv">;
33 // HasV9 - This predicate is true when the target processor supports V9
34 // instructions. Note that the machine may be running in 32-bit mode.
35 def HasV9 : Predicate<"Subtarget->isV9()">,
36 AssemblerPredicate<"FeatureV9">;
38 // HasNoV9 - This predicate is true when the target doesn't have V9
39 // instructions. Use of this is just a hack for the isel not having proper
40 // costs for V8 instructions that are more expensive than their V9 ones.
41 def HasNoV9 : Predicate<"!Subtarget->isV9()">;
43 // HasVIS - This is true when the target processor has VIS extensions.
44 def HasVIS : Predicate<"Subtarget->isVIS()">,
45 AssemblerPredicate<"FeatureVIS">;
46 def HasVIS2 : Predicate<"Subtarget->isVIS2()">,
47 AssemblerPredicate<"FeatureVIS2">;
48 def HasVIS3 : Predicate<"Subtarget->isVIS3()">,
49 AssemblerPredicate<"FeatureVIS3">;
51 // HasHardQuad - This is true when the target processor supports quad floating
52 // point instructions.
53 def HasHardQuad : Predicate<"Subtarget->hasHardQuad()">;
55 // HasLeonCASA - This is true when the target processor supports the CASA
57 def HasLeonCASA : Predicate<"Subtarget->hasLeonCasa()">;
59 // HasUMAC_SMAC - This is true when the target processor supports the
60 // UMAC and SMAC instructions
61 def HasUMAC_SMAC : Predicate<"Subtarget->hasUmacSmac()">;
63 def HasNoFdivSqrtFix : Predicate<"!Subtarget->fixAllFDIVSQRT()">;
64 def HasNoFmulsFix : Predicate<"!Subtarget->replaceFMULS()">;
65 def HasNoFsmuldFix : Predicate<"!Subtarget->fixFSMULD()">;
67 // UseDeprecatedInsts - This predicate is true when the target processor is a
68 // V8, or when it is V9 but the V8 deprecated instructions are efficient enough
69 // to use when appropriate. In either of these cases, the instruction selector
70 // will pick deprecated instructions.
71 def UseDeprecatedInsts : Predicate<"Subtarget->useDeprecatedV8Instructions()">;
73 //===----------------------------------------------------------------------===//
74 // Instruction Pattern Stuff
75 //===----------------------------------------------------------------------===//
77 def simm11 : PatLeaf<(imm), [{ return isInt<11>(N->getSExtValue()); }]>;
79 def simm13 : PatLeaf<(imm), [{ return isInt<13>(N->getSExtValue()); }]>;
81 def LO10 : SDNodeXForm<imm, [{
82 return CurDAG->getTargetConstant((unsigned)N->getZExtValue() & 1023, SDLoc(N),
86 def HI22 : SDNodeXForm<imm, [{
87 // Transformation function: shift the immediate value down into the low bits.
88 return CurDAG->getTargetConstant((unsigned)N->getZExtValue() >> 10, SDLoc(N),
92 def SETHIimm : PatLeaf<(imm), [{
93 return isShiftedUInt<22, 10>(N->getZExtValue());
97 def ADDRrr : ComplexPattern<iPTR, 2, "SelectADDRrr", [], []>;
98 def ADDRri : ComplexPattern<iPTR, 2, "SelectADDRri", [frameindex], []>;
101 def SparcMEMrrAsmOperand : AsmOperandClass {
103 let ParserMethod = "parseMEMOperand";
106 def SparcMEMriAsmOperand : AsmOperandClass {
108 let ParserMethod = "parseMEMOperand";
111 def MEMrr : Operand<iPTR> {
112 let PrintMethod = "printMemOperand";
113 let MIOperandInfo = (ops ptr_rc, ptr_rc);
114 let ParserMatchClass = SparcMEMrrAsmOperand;
116 def MEMri : Operand<iPTR> {
117 let PrintMethod = "printMemOperand";
118 let MIOperandInfo = (ops ptr_rc, i32imm);
119 let ParserMatchClass = SparcMEMriAsmOperand;
122 def TLSSym : Operand<iPTR>;
124 // Branch targets have OtherVT type.
125 def brtarget : Operand<OtherVT> {
126 let EncoderMethod = "getBranchTargetOpValue";
129 def bprtarget : Operand<OtherVT> {
130 let EncoderMethod = "getBranchPredTargetOpValue";
133 def bprtarget16 : Operand<OtherVT> {
134 let EncoderMethod = "getBranchOnRegTargetOpValue";
137 def calltarget : Operand<i32> {
138 let EncoderMethod = "getCallTargetOpValue";
139 let DecoderMethod = "DecodeCall";
142 def simm13Op : Operand<i32> {
143 let DecoderMethod = "DecodeSIMM13";
146 // Operand for printing out a condition code.
147 let PrintMethod = "printCCOperand" in
148 def CCOp : Operand<i32>;
151 SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
153 SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisSameAs<0, 1>]>;
155 SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
157 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>]>;
159 SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
161 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
163 SDTypeProfile<1, 1, [SDTCisVT<0, f64>, SDTCisFP<1>]>;
165 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f64>]>;
168 SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, SDTCisPtrTy<2>]>;
170 SDTypeProfile<1, 2, [SDTCisPtrTy<0>, SDTCisPtrTy<1>]>;
172 def SDTSPeh_sjlj_setjmp : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
173 def SDTSPeh_sjlj_longjmp: SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
175 def SPcmpicc : SDNode<"SPISD::CMPICC", SDTSPcmpicc, [SDNPOutGlue]>;
176 def SPcmpfcc : SDNode<"SPISD::CMPFCC", SDTSPcmpfcc, [SDNPOutGlue]>;
177 def SPbricc : SDNode<"SPISD::BRICC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
178 def SPbrxcc : SDNode<"SPISD::BRXCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
179 def SPbrfcc : SDNode<"SPISD::BRFCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
181 def SPhi : SDNode<"SPISD::Hi", SDTIntUnaryOp>;
182 def SPlo : SDNode<"SPISD::Lo", SDTIntUnaryOp>;
184 def SPftoi : SDNode<"SPISD::FTOI", SDTSPFTOI>;
185 def SPitof : SDNode<"SPISD::ITOF", SDTSPITOF>;
186 def SPftox : SDNode<"SPISD::FTOX", SDTSPFTOX>;
187 def SPxtof : SDNode<"SPISD::XTOF", SDTSPXTOF>;
189 def SPselecticc : SDNode<"SPISD::SELECT_ICC", SDTSPselectcc, [SDNPInGlue]>;
190 def SPselectxcc : SDNode<"SPISD::SELECT_XCC", SDTSPselectcc, [SDNPInGlue]>;
191 def SPselectfcc : SDNode<"SPISD::SELECT_FCC", SDTSPselectcc, [SDNPInGlue]>;
193 def SPsjlj_setjmp: SDNode<"SPISD::EH_SJLJ_SETJMP",
195 [SDNPHasChain, SDNPSideEffect]>;
196 def SPsjlj_longjmp: SDNode<"SPISD::EH_SJLJ_LONGJMP",
197 SDTSPeh_sjlj_longjmp,
198 [SDNPHasChain, SDNPSideEffect]>;
200 // These are target-independent nodes, but have target-specific formats.
201 def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32>,
203 def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
206 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart,
207 [SDNPHasChain, SDNPOutGlue]>;
208 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd,
209 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
211 def SDT_SPCall : SDTypeProfile<0, -1, [SDTCisVT<0, i32>]>;
212 def call : SDNode<"SPISD::CALL", SDT_SPCall,
213 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
216 def SDT_SPRet : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
217 def retflag : SDNode<"SPISD::RET_FLAG", SDT_SPRet,
218 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
220 def flushw : SDNode<"SPISD::FLUSHW", SDTNone,
221 [SDNPHasChain, SDNPSideEffect, SDNPMayStore]>;
223 def tlsadd : SDNode<"SPISD::TLS_ADD", SDTSPtlsadd>;
224 def tlsld : SDNode<"SPISD::TLS_LD", SDTSPtlsld>;
225 def tlscall : SDNode<"SPISD::TLS_CALL", SDT_SPCall,
226 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
229 def getPCX : Operand<iPTR> {
230 let PrintMethod = "printGetPCX";
233 //===----------------------------------------------------------------------===//
234 // SPARC Flag Conditions
235 //===----------------------------------------------------------------------===//
237 // Note that these values must be kept in sync with the CCOp::CondCode enum
239 class ICC_VAL<int N> : PatLeaf<(i32 N)>;
240 def ICC_NE : ICC_VAL< 9>; // Not Equal
241 def ICC_E : ICC_VAL< 1>; // Equal
242 def ICC_G : ICC_VAL<10>; // Greater
243 def ICC_LE : ICC_VAL< 2>; // Less or Equal
244 def ICC_GE : ICC_VAL<11>; // Greater or Equal
245 def ICC_L : ICC_VAL< 3>; // Less
246 def ICC_GU : ICC_VAL<12>; // Greater Unsigned
247 def ICC_LEU : ICC_VAL< 4>; // Less or Equal Unsigned
248 def ICC_CC : ICC_VAL<13>; // Carry Clear/Great or Equal Unsigned
249 def ICC_CS : ICC_VAL< 5>; // Carry Set/Less Unsigned
250 def ICC_POS : ICC_VAL<14>; // Positive
251 def ICC_NEG : ICC_VAL< 6>; // Negative
252 def ICC_VC : ICC_VAL<15>; // Overflow Clear
253 def ICC_VS : ICC_VAL< 7>; // Overflow Set
255 class FCC_VAL<int N> : PatLeaf<(i32 N)>;
256 def FCC_U : FCC_VAL<23>; // Unordered
257 def FCC_G : FCC_VAL<22>; // Greater
258 def FCC_UG : FCC_VAL<21>; // Unordered or Greater
259 def FCC_L : FCC_VAL<20>; // Less
260 def FCC_UL : FCC_VAL<19>; // Unordered or Less
261 def FCC_LG : FCC_VAL<18>; // Less or Greater
262 def FCC_NE : FCC_VAL<17>; // Not Equal
263 def FCC_E : FCC_VAL<25>; // Equal
264 def FCC_UE : FCC_VAL<26>; // Unordered or Equal
265 def FCC_GE : FCC_VAL<27>; // Greater or Equal
266 def FCC_UGE : FCC_VAL<28>; // Unordered or Greater or Equal
267 def FCC_LE : FCC_VAL<29>; // Less or Equal
268 def FCC_ULE : FCC_VAL<30>; // Unordered or Less or Equal
269 def FCC_O : FCC_VAL<31>; // Ordered
271 class CPCC_VAL<int N> : PatLeaf<(i32 N)>;
272 def CPCC_3 : CPCC_VAL<39>; // 3
273 def CPCC_2 : CPCC_VAL<38>; // 2
274 def CPCC_23 : CPCC_VAL<37>; // 2 or 3
275 def CPCC_1 : CPCC_VAL<36>; // 1
276 def CPCC_13 : CPCC_VAL<35>; // 1 or 3
277 def CPCC_12 : CPCC_VAL<34>; // 1 or 2
278 def CPCC_123 : CPCC_VAL<33>; // 1 or 2 or 3
279 def CPCC_0 : CPCC_VAL<41>; // 0
280 def CPCC_03 : CPCC_VAL<42>; // 0 or 3
281 def CPCC_02 : CPCC_VAL<43>; // 0 or 2
282 def CPCC_023 : CPCC_VAL<44>; // 0 or 2 or 3
283 def CPCC_01 : CPCC_VAL<45>; // 0 or 1
284 def CPCC_013 : CPCC_VAL<46>; // 0 or 1 or 3
285 def CPCC_012 : CPCC_VAL<47>; // 0 or 1 or 2
287 //===----------------------------------------------------------------------===//
288 // Instruction Class Templates
289 //===----------------------------------------------------------------------===//
291 /// F3_12 multiclass - Define a normal F3_1/F3_2 pattern in one shot.
292 multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode,
293 RegisterClass RC, ValueType Ty, Operand immOp,
294 InstrItinClass itin = IIC_iu_instr> {
295 def rr : F3_1<2, Op3Val,
296 (outs RC:$rd), (ins RC:$rs1, RC:$rs2),
297 !strconcat(OpcStr, " $rs1, $rs2, $rd"),
298 [(set Ty:$rd, (OpNode Ty:$rs1, Ty:$rs2))],
300 def ri : F3_2<2, Op3Val,
301 (outs RC:$rd), (ins RC:$rs1, immOp:$simm13),
302 !strconcat(OpcStr, " $rs1, $simm13, $rd"),
303 [(set Ty:$rd, (OpNode Ty:$rs1, (Ty simm13:$simm13)))],
307 /// F3_12np multiclass - Define a normal F3_1/F3_2 pattern in one shot, with no
309 multiclass F3_12np<string OpcStr, bits<6> Op3Val, InstrItinClass itin = IIC_iu_instr> {
310 def rr : F3_1<2, Op3Val,
311 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
312 !strconcat(OpcStr, " $rs1, $rs2, $rd"), [],
314 def ri : F3_2<2, Op3Val,
315 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
316 !strconcat(OpcStr, " $rs1, $simm13, $rd"), [],
320 // Load multiclass - Define both Reg+Reg/Reg+Imm patterns in one shot.
321 multiclass Load<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode,
322 RegisterClass RC, ValueType Ty, InstrItinClass itin = IIC_iu_instr> {
323 def rr : F3_1<3, Op3Val,
324 (outs RC:$dst), (ins MEMrr:$addr),
325 !strconcat(OpcStr, " [$addr], $dst"),
326 [(set Ty:$dst, (OpNode ADDRrr:$addr))],
328 def ri : F3_2<3, Op3Val,
329 (outs RC:$dst), (ins MEMri:$addr),
330 !strconcat(OpcStr, " [$addr], $dst"),
331 [(set Ty:$dst, (OpNode ADDRri:$addr))],
335 // TODO: Instructions of the LoadASI class are currently asm only; hooking up
336 // CodeGen's address spaces to use these is a future task.
337 class LoadASI<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode,
338 RegisterClass RC, ValueType Ty, InstrItinClass itin = NoItinerary> :
339 F3_1_asi<3, Op3Val, (outs RC:$dst), (ins MEMrr:$addr, i8imm:$asi),
340 !strconcat(OpcStr, "a [$addr] $asi, $dst"),
343 // LoadA multiclass - As above, but also define alternate address space variant
344 multiclass LoadA<string OpcStr, bits<6> Op3Val, bits<6> LoadAOp3Val,
345 SDPatternOperator OpNode, RegisterClass RC, ValueType Ty,
346 InstrItinClass itin = NoItinerary> :
347 Load<OpcStr, Op3Val, OpNode, RC, Ty, itin> {
348 def Arr : LoadASI<OpcStr, LoadAOp3Val, OpNode, RC, Ty>;
351 // The LDSTUB instruction is supported for asm only.
352 // It is unlikely that general-purpose code could make use of it.
353 // CAS is preferred for sparc v9.
354 def LDSTUBrr : F3_1<3, 0b001101, (outs IntRegs:$dst), (ins MEMrr:$addr),
355 "ldstub [$addr], $dst", []>;
356 def LDSTUBri : F3_2<3, 0b001101, (outs IntRegs:$dst), (ins MEMri:$addr),
357 "ldstub [$addr], $dst", []>;
358 def LDSTUBArr : F3_1_asi<3, 0b011101, (outs IntRegs:$dst),
359 (ins MEMrr:$addr, i8imm:$asi),
360 "ldstuba [$addr] $asi, $dst", []>;
362 // Store multiclass - Define both Reg+Reg/Reg+Imm patterns in one shot.
363 multiclass Store<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode,
364 RegisterClass RC, ValueType Ty, InstrItinClass itin = IIC_st> {
365 def rr : F3_1<3, Op3Val,
366 (outs), (ins MEMrr:$addr, RC:$rd),
367 !strconcat(OpcStr, " $rd, [$addr]"),
368 [(OpNode Ty:$rd, ADDRrr:$addr)],
370 def ri : F3_2<3, Op3Val,
371 (outs), (ins MEMri:$addr, RC:$rd),
372 !strconcat(OpcStr, " $rd, [$addr]"),
373 [(OpNode Ty:$rd, ADDRri:$addr)],
377 // TODO: Instructions of the StoreASI class are currently asm only; hooking up
378 // CodeGen's address spaces to use these is a future task.
379 class StoreASI<string OpcStr, bits<6> Op3Val,
380 SDPatternOperator OpNode, RegisterClass RC, ValueType Ty,
381 InstrItinClass itin = IIC_st> :
382 F3_1_asi<3, Op3Val, (outs), (ins MEMrr:$addr, RC:$rd, i8imm:$asi),
383 !strconcat(OpcStr, "a $rd, [$addr] $asi"),
387 multiclass StoreA<string OpcStr, bits<6> Op3Val, bits<6> StoreAOp3Val,
388 SDPatternOperator OpNode, RegisterClass RC, ValueType Ty,
389 InstrItinClass itin = IIC_st> :
390 Store<OpcStr, Op3Val, OpNode, RC, Ty> {
391 def Arr : StoreASI<OpcStr, StoreAOp3Val, OpNode, RC, Ty, itin>;
394 //===----------------------------------------------------------------------===//
396 //===----------------------------------------------------------------------===//
398 // Pseudo instructions.
399 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
400 : InstSP<outs, ins, asmstr, pattern> {
401 let isCodeGenOnly = 1;
407 def GETPCX : Pseudo<(outs getPCX:$getpcseq), (ins), "$getpcseq", [] >;
410 let Defs = [O6], Uses = [O6] in {
411 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
412 "!ADJCALLSTACKDOWN $amt1, $amt2",
413 [(callseq_start timm:$amt1, timm:$amt2)]>;
414 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
415 "!ADJCALLSTACKUP $amt1",
416 [(callseq_end timm:$amt1, timm:$amt2)]>;
419 let hasSideEffects = 1, mayStore = 1 in {
420 let rd = 0, rs1 = 0, rs2 = 0 in
421 def FLUSHW : F3_1<0b10, 0b101011, (outs), (ins),
423 [(flushw)]>, Requires<[HasV9]>;
424 let rd = 0, rs1 = 1, simm13 = 3 in
425 def TA3 : F3_2<0b10, 0b111010, (outs), (ins),
430 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
431 // instruction selection into a branch sequence. This has to handle all
432 // permutations of selection between i32/f32/f64 on ICC and FCC.
433 // Expanded after instruction selection.
434 let Uses = [ICC], usesCustomInserter = 1 in {
435 def SELECT_CC_Int_ICC
436 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
437 "; SELECT_CC_Int_ICC PSEUDO!",
438 [(set i32:$dst, (SPselecticc i32:$T, i32:$F, imm:$Cond))]>;
440 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),
441 "; SELECT_CC_FP_ICC PSEUDO!",
442 [(set f32:$dst, (SPselecticc f32:$T, f32:$F, imm:$Cond))]>;
444 def SELECT_CC_DFP_ICC
445 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
446 "; SELECT_CC_DFP_ICC PSEUDO!",
447 [(set f64:$dst, (SPselecticc f64:$T, f64:$F, imm:$Cond))]>;
449 def SELECT_CC_QFP_ICC
450 : Pseudo<(outs QFPRegs:$dst), (ins QFPRegs:$T, QFPRegs:$F, i32imm:$Cond),
451 "; SELECT_CC_QFP_ICC PSEUDO!",
452 [(set f128:$dst, (SPselecticc f128:$T, f128:$F, imm:$Cond))]>;
455 let usesCustomInserter = 1, Uses = [FCC0] in {
457 def SELECT_CC_Int_FCC
458 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
459 "; SELECT_CC_Int_FCC PSEUDO!",
460 [(set i32:$dst, (SPselectfcc i32:$T, i32:$F, imm:$Cond))]>;
463 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),
464 "; SELECT_CC_FP_FCC PSEUDO!",
465 [(set f32:$dst, (SPselectfcc f32:$T, f32:$F, imm:$Cond))]>;
466 def SELECT_CC_DFP_FCC
467 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
468 "; SELECT_CC_DFP_FCC PSEUDO!",
469 [(set f64:$dst, (SPselectfcc f64:$T, f64:$F, imm:$Cond))]>;
470 def SELECT_CC_QFP_FCC
471 : Pseudo<(outs QFPRegs:$dst), (ins QFPRegs:$T, QFPRegs:$F, i32imm:$Cond),
472 "; SELECT_CC_QFP_FCC PSEUDO!",
473 [(set f128:$dst, (SPselectfcc f128:$T, f128:$F, imm:$Cond))]>;
476 let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
478 def EH_SJLJ_SETJMP32ri : Pseudo<(outs IntRegs:$dst), (ins MEMri:$buf),
480 [(set i32:$dst, (SPsjlj_setjmp ADDRri:$buf))]>,
482 def EH_SJLJ_SETJMP32rr : Pseudo<(outs IntRegs:$dst), (ins MEMrr:$buf),
484 [(set i32:$dst, (SPsjlj_setjmp ADDRrr:$buf))]>,
486 let isTerminator = 1 in
487 def EH_SJLJ_LONGJMP32ri : Pseudo<(outs), (ins MEMri:$buf),
488 "#EH_SJLJ_LONGJMP32",
489 [(SPsjlj_longjmp ADDRri:$buf)]>,
491 def EH_SJLJ_LONGJMP32rr : Pseudo<(outs), (ins MEMrr:$buf),
492 "#EH_SJLJ_LONGJMP32",
493 [(SPsjlj_longjmp ADDRrr:$buf)]>,
497 // Section B.1 - Load Integer Instructions, p. 90
498 let DecoderMethod = "DecodeLoadInt" in {
499 defm LDSB : LoadA<"ldsb", 0b001001, 0b011001, sextloadi8, IntRegs, i32>;
500 defm LDSH : LoadA<"ldsh", 0b001010, 0b011010, sextloadi16, IntRegs, i32>;
501 defm LDUB : LoadA<"ldub", 0b000001, 0b010001, zextloadi8, IntRegs, i32>;
502 defm LDUH : LoadA<"lduh", 0b000010, 0b010010, zextloadi16, IntRegs, i32>;
503 defm LD : LoadA<"ld", 0b000000, 0b010000, load, IntRegs, i32>;
506 let DecoderMethod = "DecodeLoadIntPair" in
507 defm LDD : LoadA<"ldd", 0b000011, 0b010011, load, IntPair, v2i32, IIC_ldd>;
509 // Section B.2 - Load Floating-point Instructions, p. 92
510 let DecoderMethod = "DecodeLoadFP" in {
511 defm LDF : Load<"ld", 0b100000, load, FPRegs, f32, IIC_iu_or_fpu_instr>;
512 def LDFArr : LoadASI<"ld", 0b110000, load, FPRegs, f32, IIC_iu_or_fpu_instr>,
515 let DecoderMethod = "DecodeLoadDFP" in {
516 defm LDDF : Load<"ldd", 0b100011, load, DFPRegs, f64, IIC_ldd>;
517 def LDDFArr : LoadASI<"ldd", 0b110011, load, DFPRegs, f64>,
520 let DecoderMethod = "DecodeLoadQFP" in
521 defm LDQF : LoadA<"ldq", 0b100010, 0b110010, load, QFPRegs, f128>,
522 Requires<[HasV9, HasHardQuad]>;
524 let DecoderMethod = "DecodeLoadCP" in
525 defm LDC : Load<"ld", 0b110000, load, CoprocRegs, i32>;
526 let DecoderMethod = "DecodeLoadCPPair" in
527 defm LDDC : Load<"ldd", 0b110011, load, CoprocPair, v2i32, IIC_ldd>;
529 let DecoderMethod = "DecodeLoadCP", Defs = [CPSR] in {
531 def LDCSRrr : F3_1<3, 0b110001, (outs), (ins MEMrr:$addr),
532 "ld [$addr], %csr", []>;
533 def LDCSRri : F3_2<3, 0b110001, (outs), (ins MEMri:$addr),
534 "ld [$addr], %csr", []>;
538 let DecoderMethod = "DecodeLoadFP" in
539 let Defs = [FSR] in {
541 def LDFSRrr : F3_1<3, 0b100001, (outs), (ins MEMrr:$addr),
542 "ld [$addr], %fsr", [], IIC_iu_or_fpu_instr>;
543 def LDFSRri : F3_2<3, 0b100001, (outs), (ins MEMri:$addr),
544 "ld [$addr], %fsr", [], IIC_iu_or_fpu_instr>;
547 def LDXFSRrr : F3_1<3, 0b100001, (outs), (ins MEMrr:$addr),
548 "ldx [$addr], %fsr", []>, Requires<[HasV9]>;
549 def LDXFSRri : F3_2<3, 0b100001, (outs), (ins MEMri:$addr),
550 "ldx [$addr], %fsr", []>, Requires<[HasV9]>;
554 // Section B.4 - Store Integer Instructions, p. 95
555 let DecoderMethod = "DecodeStoreInt" in {
556 defm STB : StoreA<"stb", 0b000101, 0b010101, truncstorei8, IntRegs, i32>;
557 defm STH : StoreA<"sth", 0b000110, 0b010110, truncstorei16, IntRegs, i32>;
558 defm ST : StoreA<"st", 0b000100, 0b010100, store, IntRegs, i32>;
561 let DecoderMethod = "DecodeStoreIntPair" in
562 defm STD : StoreA<"std", 0b000111, 0b010111, store, IntPair, v2i32, IIC_std>;
564 // Section B.5 - Store Floating-point Instructions, p. 97
565 let DecoderMethod = "DecodeStoreFP" in {
566 defm STF : Store<"st", 0b100100, store, FPRegs, f32>;
567 def STFArr : StoreASI<"st", 0b110100, store, FPRegs, f32>,
570 let DecoderMethod = "DecodeStoreDFP" in {
571 defm STDF : Store<"std", 0b100111, store, DFPRegs, f64, IIC_std>;
572 def STDFArr : StoreASI<"std", 0b110111, store, DFPRegs, f64>,
575 let DecoderMethod = "DecodeStoreQFP" in
576 defm STQF : StoreA<"stq", 0b100110, 0b110110, store, QFPRegs, f128>,
577 Requires<[HasV9, HasHardQuad]>;
579 let DecoderMethod = "DecodeStoreCP" in
580 defm STC : Store<"st", 0b110100, store, CoprocRegs, i32>;
582 let DecoderMethod = "DecodeStoreCPPair" in
583 defm STDC : Store<"std", 0b110111, store, CoprocPair, v2i32, IIC_std>;
585 let DecoderMethod = "DecodeStoreCP", rd = 0 in {
586 let Defs = [CPSR] in {
587 def STCSRrr : F3_1<3, 0b110101, (outs MEMrr:$addr), (ins),
588 "st %csr, [$addr]", [], IIC_st>;
589 def STCSRri : F3_2<3, 0b110101, (outs MEMri:$addr), (ins),
590 "st %csr, [$addr]", [], IIC_st>;
592 let Defs = [CPQ] in {
593 def STDCQrr : F3_1<3, 0b110110, (outs MEMrr:$addr), (ins),
594 "std %cq, [$addr]", [], IIC_std>;
595 def STDCQri : F3_2<3, 0b110110, (outs MEMri:$addr), (ins),
596 "std %cq, [$addr]", [], IIC_std>;
600 let DecoderMethod = "DecodeStoreFP" in {
602 let Defs = [FSR] in {
603 def STFSRrr : F3_1<3, 0b100101, (outs MEMrr:$addr), (ins),
604 "st %fsr, [$addr]", [], IIC_st>;
605 def STFSRri : F3_2<3, 0b100101, (outs MEMri:$addr), (ins),
606 "st %fsr, [$addr]", [], IIC_st>;
609 def STDFQrr : F3_1<3, 0b100110, (outs MEMrr:$addr), (ins),
610 "std %fq, [$addr]", [], IIC_std>;
611 def STDFQri : F3_2<3, 0b100110, (outs MEMri:$addr), (ins),
612 "std %fq, [$addr]", [], IIC_std>;
615 let rd = 1, Defs = [FSR] in {
616 def STXFSRrr : F3_1<3, 0b100101, (outs MEMrr:$addr), (ins),
617 "stx %fsr, [$addr]", []>, Requires<[HasV9]>;
618 def STXFSRri : F3_2<3, 0b100101, (outs MEMri:$addr), (ins),
619 "stx %fsr, [$addr]", []>, Requires<[HasV9]>;
623 // Section B.8 - SWAP Register with Memory Instruction
625 let Constraints = "$val = $dst", DecoderMethod = "DecodeSWAP" in {
626 def SWAPrr : F3_1<3, 0b001111,
627 (outs IntRegs:$dst), (ins MEMrr:$addr, IntRegs:$val),
628 "swap [$addr], $dst",
629 [(set i32:$dst, (atomic_swap_32 ADDRrr:$addr, i32:$val))]>;
630 def SWAPri : F3_2<3, 0b001111,
631 (outs IntRegs:$dst), (ins MEMri:$addr, IntRegs:$val),
632 "swap [$addr], $dst",
633 [(set i32:$dst, (atomic_swap_32 ADDRri:$addr, i32:$val))]>;
634 def SWAPArr : F3_1_asi<3, 0b011111,
635 (outs IntRegs:$dst), (ins MEMrr:$addr, i8imm:$asi, IntRegs:$val),
636 "swapa [$addr] $asi, $dst",
637 [/*FIXME: pattern?*/]>;
641 // Section B.9 - SETHI Instruction, p. 104
642 def SETHIi: F2_1<0b100,
643 (outs IntRegs:$rd), (ins i32imm:$imm22),
645 [(set i32:$rd, SETHIimm:$imm22)],
648 // Section B.10 - NOP Instruction, p. 105
649 // (It's a special case of SETHI)
650 let rd = 0, imm22 = 0 in
651 def NOP : F2_1<0b100, (outs), (ins), "nop", []>;
653 // Section B.11 - Logical Instructions, p. 106
654 defm AND : F3_12<"and", 0b000001, and, IntRegs, i32, simm13Op>;
656 def ANDNrr : F3_1<2, 0b000101,
657 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
658 "andn $rs1, $rs2, $rd",
659 [(set i32:$rd, (and i32:$rs1, (not i32:$rs2)))]>;
660 def ANDNri : F3_2<2, 0b000101,
661 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
662 "andn $rs1, $simm13, $rd", []>;
664 defm OR : F3_12<"or", 0b000010, or, IntRegs, i32, simm13Op>;
666 def ORNrr : F3_1<2, 0b000110,
667 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
668 "orn $rs1, $rs2, $rd",
669 [(set i32:$rd, (or i32:$rs1, (not i32:$rs2)))]>;
670 def ORNri : F3_2<2, 0b000110,
671 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
672 "orn $rs1, $simm13, $rd", []>;
673 defm XOR : F3_12<"xor", 0b000011, xor, IntRegs, i32, simm13Op>;
675 def XNORrr : F3_1<2, 0b000111,
676 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
677 "xnor $rs1, $rs2, $rd",
678 [(set i32:$rd, (not (xor i32:$rs1, i32:$rs2)))]>;
679 def XNORri : F3_2<2, 0b000111,
680 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
681 "xnor $rs1, $simm13, $rd", []>;
683 let Defs = [ICC] in {
684 defm ANDCC : F3_12np<"andcc", 0b010001>;
685 defm ANDNCC : F3_12np<"andncc", 0b010101>;
686 defm ORCC : F3_12np<"orcc", 0b010010>;
687 defm ORNCC : F3_12np<"orncc", 0b010110>;
688 defm XORCC : F3_12np<"xorcc", 0b010011>;
689 defm XNORCC : F3_12np<"xnorcc", 0b010111>;
692 // Section B.12 - Shift Instructions, p. 107
693 defm SLL : F3_12<"sll", 0b100101, shl, IntRegs, i32, simm13Op>;
694 defm SRL : F3_12<"srl", 0b100110, srl, IntRegs, i32, simm13Op>;
695 defm SRA : F3_12<"sra", 0b100111, sra, IntRegs, i32, simm13Op>;
697 // Section B.13 - Add Instructions, p. 108
698 defm ADD : F3_12<"add", 0b000000, add, IntRegs, i32, simm13Op>;
700 // "LEA" forms of add (patterns to make tblgen happy)
701 let Predicates = [Is32Bit], isCodeGenOnly = 1 in
702 def LEA_ADDri : F3_2<2, 0b000000,
703 (outs IntRegs:$dst), (ins MEMri:$addr),
704 "add ${addr:arith}, $dst",
705 [(set iPTR:$dst, ADDRri:$addr)]>;
708 defm ADDCC : F3_12<"addcc", 0b010000, addc, IntRegs, i32, simm13Op>;
711 defm ADDC : F3_12np<"addx", 0b001000>;
713 let Uses = [ICC], Defs = [ICC] in
714 defm ADDE : F3_12<"addxcc", 0b011000, adde, IntRegs, i32, simm13Op>;
716 // Section B.15 - Subtract Instructions, p. 110
717 defm SUB : F3_12 <"sub" , 0b000100, sub, IntRegs, i32, simm13Op>;
718 let Uses = [ICC], Defs = [ICC] in
719 defm SUBE : F3_12 <"subxcc" , 0b011100, sube, IntRegs, i32, simm13Op>;
722 defm SUBCC : F3_12 <"subcc", 0b010100, subc, IntRegs, i32, simm13Op>;
725 defm SUBC : F3_12np <"subx", 0b001100>;
727 // cmp (from Section A.3) is a specialized alias for subcc
728 let Defs = [ICC], rd = 0 in {
729 def CMPrr : F3_1<2, 0b010100,
730 (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
732 [(SPcmpicc i32:$rs1, i32:$rs2)]>;
733 def CMPri : F3_2<2, 0b010100,
734 (outs), (ins IntRegs:$rs1, simm13Op:$simm13),
736 [(SPcmpicc i32:$rs1, (i32 simm13:$simm13))]>;
739 // Section B.18 - Multiply Instructions, p. 113
741 defm UMUL : F3_12<"umul", 0b001010, umullohi, IntRegs, i32, simm13Op, IIC_iu_umul>;
742 defm SMUL : F3_12<"smul", 0b001011, smullohi, IntRegs, i32, simm13Op, IIC_iu_smul>;
745 let Defs = [Y, ICC] in {
746 defm UMULCC : F3_12np<"umulcc", 0b011010, IIC_iu_umul>;
747 defm SMULCC : F3_12np<"smulcc", 0b011011, IIC_iu_smul>;
750 let Defs = [Y, ICC], Uses = [Y, ICC] in {
751 defm MULSCC : F3_12np<"mulscc", 0b100100>;
754 // Section B.19 - Divide Instructions, p. 115
755 let Uses = [Y], Defs = [Y] in {
756 defm UDIV : F3_12np<"udiv", 0b001110, IIC_iu_div>;
757 defm SDIV : F3_12np<"sdiv", 0b001111, IIC_iu_div>;
760 let Uses = [Y], Defs = [Y, ICC] in {
761 defm UDIVCC : F3_12np<"udivcc", 0b011110, IIC_iu_div>;
762 defm SDIVCC : F3_12np<"sdivcc", 0b011111, IIC_iu_div>;
765 // Section B.20 - SAVE and RESTORE, p. 117
766 defm SAVE : F3_12np<"save" , 0b111100>;
767 defm RESTORE : F3_12np<"restore", 0b111101>;
769 // Section B.21 - Branch on Integer Condition Codes Instructions, p. 119
771 // unconditional branch class.
772 class BranchAlways<dag ins, string asmstr, list<dag> pattern>
773 : F2_2<0b010, 0, (outs), ins, asmstr, pattern> {
775 let isTerminator = 1;
776 let hasDelaySlot = 1;
781 def BA : BranchAlways<(ins brtarget:$imm22), "ba $imm22", [(br bb:$imm22)]>;
784 let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 in {
786 // conditional branch class:
787 class BranchSP<dag ins, string asmstr, list<dag> pattern>
788 : F2_2<0b010, 0, (outs), ins, asmstr, pattern, IIC_iu_instr>;
790 // conditional branch with annul class:
791 class BranchSPA<dag ins, string asmstr, list<dag> pattern>
792 : F2_2<0b010, 1, (outs), ins, asmstr, pattern, IIC_iu_instr>;
794 // Conditional branch class on %icc|%xcc with predication:
795 multiclass IPredBranch<string regstr, list<dag> CCPattern> {
796 def CC : F2_3<0b001, 0, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond),
797 !strconcat("b$cond ", !strconcat(regstr, ", $imm19")),
800 def CCA : F2_3<0b001, 1, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond),
801 !strconcat("b$cond,a ", !strconcat(regstr, ", $imm19")),
804 def CCNT : F2_3<0b001, 0, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond),
805 !strconcat("b$cond,pn ", !strconcat(regstr, ", $imm19")),
808 def CCANT : F2_3<0b001, 1, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond),
809 !strconcat("b$cond,a,pn ", !strconcat(regstr, ", $imm19")),
814 } // let isBranch = 1, isTerminator = 1, hasDelaySlot = 1
817 // Indirect branch instructions.
818 let isTerminator = 1, isBarrier = 1, hasDelaySlot = 1, isBranch =1,
819 isIndirectBranch = 1, rd = 0, isCodeGenOnly = 1 in {
820 def BINDrr : F3_1<2, 0b111000,
821 (outs), (ins MEMrr:$ptr),
823 [(brind ADDRrr:$ptr)]>;
824 def BINDri : F3_2<2, 0b111000,
825 (outs), (ins MEMri:$ptr),
827 [(brind ADDRri:$ptr)]>;
830 let Uses = [ICC] in {
831 def BCOND : BranchSP<(ins brtarget:$imm22, CCOp:$cond),
833 [(SPbricc bb:$imm22, imm:$cond)]>;
834 def BCONDA : BranchSPA<(ins brtarget:$imm22, CCOp:$cond),
835 "b$cond,a $imm22", []>;
837 let Predicates = [HasV9], cc = 0b00 in
838 defm BPI : IPredBranch<"%icc", []>;
841 // Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121
843 let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 in {
845 // floating-point conditional branch class:
846 class FPBranchSP<dag ins, string asmstr, list<dag> pattern>
847 : F2_2<0b110, 0, (outs), ins, asmstr, pattern, IIC_fpu_normal_instr>;
849 // floating-point conditional branch with annul class:
850 class FPBranchSPA<dag ins, string asmstr, list<dag> pattern>
851 : F2_2<0b110, 1, (outs), ins, asmstr, pattern, IIC_fpu_normal_instr>;
853 // Conditional branch class on %fcc0-%fcc3 with predication:
854 multiclass FPredBranch {
855 def CC : F2_3<0b101, 0, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond,
857 "fb$cond $cc, $imm19", [], IIC_fpu_normal_instr>;
858 def CCA : F2_3<0b101, 1, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond,
860 "fb$cond,a $cc, $imm19", [], IIC_fpu_normal_instr>;
861 def CCNT : F2_3<0b101, 0, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond,
863 "fb$cond,pn $cc, $imm19", [], IIC_fpu_normal_instr>;
864 def CCANT : F2_3<0b101, 1, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond,
866 "fb$cond,a,pn $cc, $imm19", [], IIC_fpu_normal_instr>;
868 } // let isBranch = 1, isTerminator = 1, hasDelaySlot = 1
870 let Uses = [FCC0] in {
871 def FBCOND : FPBranchSP<(ins brtarget:$imm22, CCOp:$cond),
873 [(SPbrfcc bb:$imm22, imm:$cond)]>;
874 def FBCONDA : FPBranchSPA<(ins brtarget:$imm22, CCOp:$cond),
875 "fb$cond,a $imm22", []>;
878 let Predicates = [HasV9] in
879 defm BPF : FPredBranch;
881 // Section B.22 - Branch on Co-processor Condition Codes Instructions, p. 123
882 let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 in {
884 // co-processor conditional branch class:
885 class CPBranchSP<dag ins, string asmstr, list<dag> pattern>
886 : F2_2<0b111, 0, (outs), ins, asmstr, pattern>;
888 // co-processor conditional branch with annul class:
889 class CPBranchSPA<dag ins, string asmstr, list<dag> pattern>
890 : F2_2<0b111, 1, (outs), ins, asmstr, pattern>;
892 } // let isBranch = 1, isTerminator = 1, hasDelaySlot = 1
894 def CBCOND : CPBranchSP<(ins brtarget:$imm22, CCOp:$cond),
896 [(SPbrfcc bb:$imm22, imm:$cond)]>;
897 def CBCONDA : CPBranchSPA<(ins brtarget:$imm22, CCOp:$cond),
898 "cb$cond,a $imm22", []>;
900 // Section B.24 - Call and Link Instruction, p. 125
901 // This is the only Format 1 instruction
903 hasDelaySlot = 1, isCall = 1 in {
904 def CALL : InstSP<(outs), (ins calltarget:$disp, variable_ops),
910 let Inst{29-0} = disp;
913 // indirect calls: special cases of JMPL.
914 let isCodeGenOnly = 1, rd = 15 in {
915 def CALLrr : F3_1<2, 0b111000,
916 (outs), (ins MEMrr:$ptr, variable_ops),
918 [(call ADDRrr:$ptr)],
920 def CALLri : F3_2<2, 0b111000,
921 (outs), (ins MEMri:$ptr, variable_ops),
923 [(call ADDRri:$ptr)],
928 // Section B.25 - Jump and Link Instruction
931 let isTerminator = 1, hasDelaySlot = 1, isBarrier = 1,
932 DecoderMethod = "DecodeJMPL" in {
933 def JMPLrr: F3_1<2, 0b111000,
934 (outs IntRegs:$dst), (ins MEMrr:$addr),
938 def JMPLri: F3_2<2, 0b111000,
939 (outs IntRegs:$dst), (ins MEMri:$addr),
945 // Section A.3 - Synthetic Instructions, p. 85
946 // special cases of JMPL:
947 let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, isBarrier = 1,
948 isCodeGenOnly = 1 in {
949 let rd = 0, rs1 = 15 in
950 def RETL: F3_2<2, 0b111000,
951 (outs), (ins i32imm:$val),
953 [(retflag simm13:$val)],
956 let rd = 0, rs1 = 31 in
957 def RET: F3_2<2, 0b111000,
958 (outs), (ins i32imm:$val),
964 // Section B.26 - Return from Trap Instruction
965 let isReturn = 1, isTerminator = 1, hasDelaySlot = 1,
966 isBarrier = 1, rd = 0, DecoderMethod = "DecodeReturn" in {
967 def RETTrr : F3_1<2, 0b111001,
968 (outs), (ins MEMrr:$addr),
972 def RETTri : F3_2<2, 0b111001,
973 (outs), (ins MEMri:$addr),
980 // Section B.27 - Trap on Integer Condition Codes Instruction
981 // conditional branch class:
982 let DecoderNamespace = "SparcV8", DecoderMethod = "DecodeTRAP", hasSideEffects = 1, Uses = [ICC], cc = 0b00 in
984 def TRAPrr : TRAPSPrr<0b111010,
985 (outs), (ins IntRegs:$rs1, IntRegs:$rs2, CCOp:$cond),
986 "t$cond $rs1 + $rs2",
988 def TRAPri : TRAPSPri<0b111010,
989 (outs), (ins IntRegs:$rs1, i32imm:$imm, CCOp:$cond),
990 "t$cond $rs1 + $imm",
994 multiclass TRAP<string regStr> {
995 def rr : TRAPSPrr<0b111010,
996 (outs), (ins IntRegs:$rs1, IntRegs:$rs2, CCOp:$cond),
997 !strconcat(!strconcat("t$cond ", regStr), ", $rs1 + $rs2"),
999 def ri : TRAPSPri<0b111010,
1000 (outs), (ins IntRegs:$rs1, i32imm:$imm, CCOp:$cond),
1001 !strconcat(!strconcat("t$cond ", regStr), ", $rs1 + $imm"),
1005 let DecoderNamespace = "SparcV9", DecoderMethod = "DecodeTRAP", Predicates = [HasV9], hasSideEffects = 1, Uses = [ICC], cc = 0b00 in
1006 defm TICC : TRAP<"%icc">;
1009 let isBarrier = 1, isTerminator = 1, rd = 0b01000, rs1 = 0, simm13 = 5 in
1010 def TA5 : F3_2<0b10, 0b111010, (outs), (ins), "ta 5", [(trap)]>;
1012 // Section B.28 - Read State Register Instructions
1014 def RDASR : F3_1<2, 0b101000,
1015 (outs IntRegs:$rd), (ins ASRRegs:$rs1),
1016 "rd $rs1, $rd", []>;
1018 // PSR, WIM, and TBR don't exist on the SparcV9, only the V8.
1019 let Predicates = [HasNoV9] in {
1020 let rs2 = 0, rs1 = 0, Uses=[PSR] in
1021 def RDPSR : F3_1<2, 0b101001,
1022 (outs IntRegs:$rd), (ins),
1023 "rd %psr, $rd", []>;
1025 let rs2 = 0, rs1 = 0, Uses=[WIM] in
1026 def RDWIM : F3_1<2, 0b101010,
1027 (outs IntRegs:$rd), (ins),
1028 "rd %wim, $rd", []>;
1030 let rs2 = 0, rs1 = 0, Uses=[TBR] in
1031 def RDTBR : F3_1<2, 0b101011,
1032 (outs IntRegs:$rd), (ins),
1033 "rd %tbr, $rd", []>;
1036 // Section B.29 - Write State Register Instructions
1037 def WRASRrr : F3_1<2, 0b110000,
1038 (outs ASRRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
1039 "wr $rs1, $rs2, $rd", []>;
1040 def WRASRri : F3_2<2, 0b110000,
1041 (outs ASRRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
1042 "wr $rs1, $simm13, $rd", []>;
1044 // PSR, WIM, and TBR don't exist on the SparcV9, only the V8.
1045 let Predicates = [HasNoV9] in {
1046 let Defs = [PSR], rd=0 in {
1047 def WRPSRrr : F3_1<2, 0b110001,
1048 (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
1049 "wr $rs1, $rs2, %psr", []>;
1050 def WRPSRri : F3_2<2, 0b110001,
1051 (outs), (ins IntRegs:$rs1, simm13Op:$simm13),
1052 "wr $rs1, $simm13, %psr", []>;
1055 let Defs = [WIM], rd=0 in {
1056 def WRWIMrr : F3_1<2, 0b110010,
1057 (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
1058 "wr $rs1, $rs2, %wim", []>;
1059 def WRWIMri : F3_2<2, 0b110010,
1060 (outs), (ins IntRegs:$rs1, simm13Op:$simm13),
1061 "wr $rs1, $simm13, %wim", []>;
1064 let Defs = [TBR], rd=0 in {
1065 def WRTBRrr : F3_1<2, 0b110011,
1066 (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
1067 "wr $rs1, $rs2, %tbr", []>;
1068 def WRTBRri : F3_2<2, 0b110011,
1069 (outs), (ins IntRegs:$rs1, simm13Op:$simm13),
1070 "wr $rs1, $simm13, %tbr", []>;
1074 // Section B.30 - STBAR Instruction
1075 let hasSideEffects = 1, rd = 0, rs1 = 0b01111, rs2 = 0 in
1076 def STBAR : F3_1<2, 0b101000, (outs), (ins), "stbar", []>;
1079 // Section B.31 - Unimplmented Instruction
1081 def UNIMP : F2_1<0b000, (outs), (ins i32imm:$imm22),
1082 "unimp $imm22", []>;
1084 // Section B.32 - Flush Instruction Memory
1086 def FLUSHrr : F3_1<2, 0b111011, (outs), (ins MEMrr:$addr),
1088 def FLUSHri : F3_2<2, 0b111011, (outs), (ins MEMri:$addr),
1091 // The no-arg FLUSH is only here for the benefit of the InstAlias
1092 // "flush", which cannot seem to use FLUSHrr, due to the inability
1093 // to construct a MEMrr with fixed G0 registers.
1094 let rs1 = 0, rs2 = 0 in
1095 def FLUSH : F3_1<2, 0b111011, (outs), (ins), "flush %g0", []>;
1098 // Section B.33 - Floating-point Operate (FPop) Instructions
1100 // Convert Integer to Floating-point Instructions, p. 141
1101 def FITOS : F3_3u<2, 0b110100, 0b011000100,
1102 (outs FPRegs:$rd), (ins FPRegs:$rs2),
1104 [(set FPRegs:$rd, (SPitof FPRegs:$rs2))],
1105 IIC_fpu_fast_instr>;
1106 def FITOD : F3_3u<2, 0b110100, 0b011001000,
1107 (outs DFPRegs:$rd), (ins FPRegs:$rs2),
1109 [(set DFPRegs:$rd, (SPitof FPRegs:$rs2))],
1110 IIC_fpu_fast_instr>;
1111 def FITOQ : F3_3u<2, 0b110100, 0b011001100,
1112 (outs QFPRegs:$rd), (ins FPRegs:$rs2),
1114 [(set QFPRegs:$rd, (SPitof FPRegs:$rs2))]>,
1115 Requires<[HasHardQuad]>;
1117 // Convert Floating-point to Integer Instructions, p. 142
1118 def FSTOI : F3_3u<2, 0b110100, 0b011010001,
1119 (outs FPRegs:$rd), (ins FPRegs:$rs2),
1121 [(set FPRegs:$rd, (SPftoi FPRegs:$rs2))],
1122 IIC_fpu_fast_instr>;
1123 def FDTOI : F3_3u<2, 0b110100, 0b011010010,
1124 (outs FPRegs:$rd), (ins DFPRegs:$rs2),
1126 [(set FPRegs:$rd, (SPftoi DFPRegs:$rs2))],
1127 IIC_fpu_fast_instr>;
1128 def FQTOI : F3_3u<2, 0b110100, 0b011010011,
1129 (outs FPRegs:$rd), (ins QFPRegs:$rs2),
1131 [(set FPRegs:$rd, (SPftoi QFPRegs:$rs2))]>,
1132 Requires<[HasHardQuad]>;
1134 // Convert between Floating-point Formats Instructions, p. 143
1135 def FSTOD : F3_3u<2, 0b110100, 0b011001001,
1136 (outs DFPRegs:$rd), (ins FPRegs:$rs2),
1138 [(set f64:$rd, (fpextend f32:$rs2))],
1140 def FSTOQ : F3_3u<2, 0b110100, 0b011001101,
1141 (outs QFPRegs:$rd), (ins FPRegs:$rs2),
1143 [(set f128:$rd, (fpextend f32:$rs2))]>,
1144 Requires<[HasHardQuad]>;
1145 def FDTOS : F3_3u<2, 0b110100, 0b011000110,
1146 (outs FPRegs:$rd), (ins DFPRegs:$rs2),
1148 [(set f32:$rd, (fpround f64:$rs2))],
1149 IIC_fpu_fast_instr>;
1150 def FDTOQ : F3_3u<2, 0b110100, 0b011001110,
1151 (outs QFPRegs:$rd), (ins DFPRegs:$rs2),
1153 [(set f128:$rd, (fpextend f64:$rs2))]>,
1154 Requires<[HasHardQuad]>;
1155 def FQTOS : F3_3u<2, 0b110100, 0b011000111,
1156 (outs FPRegs:$rd), (ins QFPRegs:$rs2),
1158 [(set f32:$rd, (fpround f128:$rs2))]>,
1159 Requires<[HasHardQuad]>;
1160 def FQTOD : F3_3u<2, 0b110100, 0b011001011,
1161 (outs DFPRegs:$rd), (ins QFPRegs:$rs2),
1163 [(set f64:$rd, (fpround f128:$rs2))]>,
1164 Requires<[HasHardQuad]>;
1166 // Floating-point Move Instructions, p. 144
1167 def FMOVS : F3_3u<2, 0b110100, 0b000000001,
1168 (outs FPRegs:$rd), (ins FPRegs:$rs2),
1169 "fmovs $rs2, $rd", []>;
1170 def FNEGS : F3_3u<2, 0b110100, 0b000000101,
1171 (outs FPRegs:$rd), (ins FPRegs:$rs2),
1173 [(set f32:$rd, (fneg f32:$rs2))],
1175 def FABSS : F3_3u<2, 0b110100, 0b000001001,
1176 (outs FPRegs:$rd), (ins FPRegs:$rs2),
1178 [(set f32:$rd, (fabs f32:$rs2))],
1182 // Floating-point Square Root Instructions, p.145
1183 // FSQRTS generates an erratum on LEON processors, so by disabling this instruction
1184 // this will be promoted to use FSQRTD with doubles instead.
1185 let Predicates = [HasNoFdivSqrtFix] in
1186 def FSQRTS : F3_3u<2, 0b110100, 0b000101001,
1187 (outs FPRegs:$rd), (ins FPRegs:$rs2),
1189 [(set f32:$rd, (fsqrt f32:$rs2))],
1191 def FSQRTD : F3_3u<2, 0b110100, 0b000101010,
1192 (outs DFPRegs:$rd), (ins DFPRegs:$rs2),
1194 [(set f64:$rd, (fsqrt f64:$rs2))],
1196 def FSQRTQ : F3_3u<2, 0b110100, 0b000101011,
1197 (outs QFPRegs:$rd), (ins QFPRegs:$rs2),
1199 [(set f128:$rd, (fsqrt f128:$rs2))]>,
1200 Requires<[HasHardQuad]>;
1204 // Floating-point Add and Subtract Instructions, p. 146
1205 def FADDS : F3_3<2, 0b110100, 0b001000001,
1206 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
1207 "fadds $rs1, $rs2, $rd",
1208 [(set f32:$rd, (fadd f32:$rs1, f32:$rs2))],
1209 IIC_fpu_fast_instr>;
1210 def FADDD : F3_3<2, 0b110100, 0b001000010,
1211 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1212 "faddd $rs1, $rs2, $rd",
1213 [(set f64:$rd, (fadd f64:$rs1, f64:$rs2))],
1214 IIC_fpu_fast_instr>;
1215 def FADDQ : F3_3<2, 0b110100, 0b001000011,
1216 (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
1217 "faddq $rs1, $rs2, $rd",
1218 [(set f128:$rd, (fadd f128:$rs1, f128:$rs2))]>,
1219 Requires<[HasHardQuad]>;
1221 def FSUBS : F3_3<2, 0b110100, 0b001000101,
1222 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
1223 "fsubs $rs1, $rs2, $rd",
1224 [(set f32:$rd, (fsub f32:$rs1, f32:$rs2))],
1225 IIC_fpu_fast_instr>;
1226 def FSUBD : F3_3<2, 0b110100, 0b001000110,
1227 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1228 "fsubd $rs1, $rs2, $rd",
1229 [(set f64:$rd, (fsub f64:$rs1, f64:$rs2))],
1230 IIC_fpu_fast_instr>;
1231 def FSUBQ : F3_3<2, 0b110100, 0b001000111,
1232 (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
1233 "fsubq $rs1, $rs2, $rd",
1234 [(set f128:$rd, (fsub f128:$rs1, f128:$rs2))]>,
1235 Requires<[HasHardQuad]>;
1238 // Floating-point Multiply and Divide Instructions, p. 147
1239 // FMULS generates an erratum on LEON processors, so by disabling this instruction
1240 // this will be promoted to use FMULD with doubles instead.
1241 let Predicates = [HasNoFmulsFix] in
1242 def FMULS : F3_3<2, 0b110100, 0b001001001,
1243 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
1244 "fmuls $rs1, $rs2, $rd",
1245 [(set f32:$rd, (fmul f32:$rs1, f32:$rs2))],
1247 def FMULD : F3_3<2, 0b110100, 0b001001010,
1248 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1249 "fmuld $rs1, $rs2, $rd",
1250 [(set f64:$rd, (fmul f64:$rs1, f64:$rs2))],
1252 def FMULQ : F3_3<2, 0b110100, 0b001001011,
1253 (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
1254 "fmulq $rs1, $rs2, $rd",
1255 [(set f128:$rd, (fmul f128:$rs1, f128:$rs2))]>,
1256 Requires<[HasHardQuad]>;
1258 let Predicates = [HasNoFsmuldFix] in
1259 def FSMULD : F3_3<2, 0b110100, 0b001101001,
1260 (outs DFPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
1261 "fsmuld $rs1, $rs2, $rd",
1262 [(set f64:$rd, (fmul (fpextend f32:$rs1),
1263 (fpextend f32:$rs2)))],
1265 def FDMULQ : F3_3<2, 0b110100, 0b001101110,
1266 (outs QFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1267 "fdmulq $rs1, $rs2, $rd",
1268 [(set f128:$rd, (fmul (fpextend f64:$rs1),
1269 (fpextend f64:$rs2)))]>,
1270 Requires<[HasHardQuad]>;
1272 // FDIVS generates an erratum on LEON processors, so by disabling this instruction
1273 // this will be promoted to use FDIVD with doubles instead.
1274 def FDIVS : F3_3<2, 0b110100, 0b001001101,
1275 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
1276 "fdivs $rs1, $rs2, $rd",
1277 [(set f32:$rd, (fdiv f32:$rs1, f32:$rs2))],
1279 def FDIVD : F3_3<2, 0b110100, 0b001001110,
1280 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1281 "fdivd $rs1, $rs2, $rd",
1282 [(set f64:$rd, (fdiv f64:$rs1, f64:$rs2))],
1284 def FDIVQ : F3_3<2, 0b110100, 0b001001111,
1285 (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
1286 "fdivq $rs1, $rs2, $rd",
1287 [(set f128:$rd, (fdiv f128:$rs1, f128:$rs2))]>,
1288 Requires<[HasHardQuad]>;
1290 // Floating-point Compare Instructions, p. 148
1291 // Note: the 2nd template arg is different for these guys.
1292 // Note 2: the result of a FCMP is not available until the 2nd cycle
1293 // after the instr is retired, but there is no interlock in Sparc V8.
1294 // This behavior is modeled with a forced noop after the instruction in
1297 let Defs = [FCC0], rd = 0, isCodeGenOnly = 1 in {
1298 def FCMPS : F3_3c<2, 0b110101, 0b001010001,
1299 (outs), (ins FPRegs:$rs1, FPRegs:$rs2),
1301 [(SPcmpfcc f32:$rs1, f32:$rs2)],
1302 IIC_fpu_fast_instr>;
1303 def FCMPD : F3_3c<2, 0b110101, 0b001010010,
1304 (outs), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1306 [(SPcmpfcc f64:$rs1, f64:$rs2)],
1307 IIC_fpu_fast_instr>;
1308 def FCMPQ : F3_3c<2, 0b110101, 0b001010011,
1309 (outs), (ins QFPRegs:$rs1, QFPRegs:$rs2),
1311 [(SPcmpfcc f128:$rs1, f128:$rs2)]>,
1312 Requires<[HasHardQuad]>;
1315 //===----------------------------------------------------------------------===//
1316 // Instructions for Thread Local Storage(TLS).
1317 //===----------------------------------------------------------------------===//
1318 let isCodeGenOnly = 1, isAsmParserOnly = 1 in {
1319 def TLS_ADDrr : F3_1<2, 0b000000,
1321 (ins IntRegs:$rs1, IntRegs:$rs2, TLSSym:$sym),
1322 "add $rs1, $rs2, $rd, $sym",
1324 (tlsadd i32:$rs1, i32:$rs2, tglobaltlsaddr:$sym))]>;
1327 def TLS_LDrr : F3_1<3, 0b000000,
1328 (outs IntRegs:$dst), (ins MEMrr:$addr, TLSSym:$sym),
1329 "ld [$addr], $dst, $sym",
1331 (tlsld ADDRrr:$addr, tglobaltlsaddr:$sym))]>;
1333 let Uses = [O6], isCall = 1, hasDelaySlot = 1 in
1334 def TLS_CALL : InstSP<(outs),
1335 (ins calltarget:$disp, TLSSym:$sym, variable_ops),
1337 [(tlscall texternalsym:$disp, tglobaltlsaddr:$sym)],
1341 let Inst{29-0} = disp;
1345 //===----------------------------------------------------------------------===//
1347 //===----------------------------------------------------------------------===//
1349 // V9 Conditional Moves.
1350 let Predicates = [HasV9], Constraints = "$f = $rd" in {
1351 // Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual.
1352 let Uses = [ICC], intcc = 1, cc = 0b00 in {
1354 : F4_1<0b101100, (outs IntRegs:$rd),
1355 (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
1356 "mov$cond %icc, $rs2, $rd",
1357 [(set i32:$rd, (SPselecticc i32:$rs2, i32:$f, imm:$cond))]>;
1360 : F4_2<0b101100, (outs IntRegs:$rd),
1361 (ins i32imm:$simm11, IntRegs:$f, CCOp:$cond),
1362 "mov$cond %icc, $simm11, $rd",
1364 (SPselecticc simm11:$simm11, i32:$f, imm:$cond))]>;
1367 let Uses = [FCC0], intcc = 0, cc = 0b00 in {
1369 : F4_1<0b101100, (outs IntRegs:$rd),
1370 (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
1371 "mov$cond %fcc0, $rs2, $rd",
1372 [(set i32:$rd, (SPselectfcc i32:$rs2, i32:$f, imm:$cond))]>;
1374 : F4_2<0b101100, (outs IntRegs:$rd),
1375 (ins i32imm:$simm11, IntRegs:$f, CCOp:$cond),
1376 "mov$cond %fcc0, $simm11, $rd",
1378 (SPselectfcc simm11:$simm11, i32:$f, imm:$cond))]>;
1381 let Uses = [ICC], intcc = 1, opf_cc = 0b00 in {
1383 : F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
1384 (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
1385 "fmovs$cond %icc, $rs2, $rd",
1386 [(set f32:$rd, (SPselecticc f32:$rs2, f32:$f, imm:$cond))]>;
1388 : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd),
1389 (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
1390 "fmovd$cond %icc, $rs2, $rd",
1391 [(set f64:$rd, (SPselecticc f64:$rs2, f64:$f, imm:$cond))]>;
1393 : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
1394 (ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
1395 "fmovq$cond %icc, $rs2, $rd",
1396 [(set f128:$rd, (SPselecticc f128:$rs2, f128:$f, imm:$cond))]>,
1397 Requires<[HasHardQuad]>;
1400 let Uses = [FCC0], intcc = 0, opf_cc = 0b00 in {
1402 : F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
1403 (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
1404 "fmovs$cond %fcc0, $rs2, $rd",
1405 [(set f32:$rd, (SPselectfcc f32:$rs2, f32:$f, imm:$cond))]>;
1407 : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd),
1408 (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
1409 "fmovd$cond %fcc0, $rs2, $rd",
1410 [(set f64:$rd, (SPselectfcc f64:$rs2, f64:$f, imm:$cond))]>;
1412 : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
1413 (ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
1414 "fmovq$cond %fcc0, $rs2, $rd",
1415 [(set f128:$rd, (SPselectfcc f128:$rs2, f128:$f, imm:$cond))]>,
1416 Requires<[HasHardQuad]>;
1421 // Floating-Point Move Instructions, p. 164 of the V9 manual.
1422 let Predicates = [HasV9] in {
1423 def FMOVD : F3_3u<2, 0b110100, 0b000000010,
1424 (outs DFPRegs:$rd), (ins DFPRegs:$rs2),
1425 "fmovd $rs2, $rd", []>;
1426 def FMOVQ : F3_3u<2, 0b110100, 0b000000011,
1427 (outs QFPRegs:$rd), (ins QFPRegs:$rs2),
1428 "fmovq $rs2, $rd", []>,
1429 Requires<[HasHardQuad]>;
1430 def FNEGD : F3_3u<2, 0b110100, 0b000000110,
1431 (outs DFPRegs:$rd), (ins DFPRegs:$rs2),
1433 [(set f64:$rd, (fneg f64:$rs2))]>;
1434 def FNEGQ : F3_3u<2, 0b110100, 0b000000111,
1435 (outs QFPRegs:$rd), (ins QFPRegs:$rs2),
1437 [(set f128:$rd, (fneg f128:$rs2))]>,
1438 Requires<[HasHardQuad]>;
1439 def FABSD : F3_3u<2, 0b110100, 0b000001010,
1440 (outs DFPRegs:$rd), (ins DFPRegs:$rs2),
1442 [(set f64:$rd, (fabs f64:$rs2))]>;
1443 def FABSQ : F3_3u<2, 0b110100, 0b000001011,
1444 (outs QFPRegs:$rd), (ins QFPRegs:$rs2),
1446 [(set f128:$rd, (fabs f128:$rs2))]>,
1447 Requires<[HasHardQuad]>;
1450 // Floating-point compare instruction with %fcc0-%fcc3.
1451 def V9FCMPS : F3_3c<2, 0b110101, 0b001010001,
1452 (outs FCCRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
1453 "fcmps $rd, $rs1, $rs2", []>;
1454 def V9FCMPD : F3_3c<2, 0b110101, 0b001010010,
1455 (outs FCCRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1456 "fcmpd $rd, $rs1, $rs2", []>;
1457 def V9FCMPQ : F3_3c<2, 0b110101, 0b001010011,
1458 (outs FCCRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
1459 "fcmpq $rd, $rs1, $rs2", []>,
1460 Requires<[HasHardQuad]>;
1462 let hasSideEffects = 1 in {
1463 def V9FCMPES : F3_3c<2, 0b110101, 0b001010101,
1464 (outs FCCRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
1465 "fcmpes $rd, $rs1, $rs2", []>;
1466 def V9FCMPED : F3_3c<2, 0b110101, 0b001010110,
1467 (outs FCCRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1468 "fcmped $rd, $rs1, $rs2", []>;
1469 def V9FCMPEQ : F3_3c<2, 0b110101, 0b001010111,
1470 (outs FCCRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
1471 "fcmpeq $rd, $rs1, $rs2", []>,
1472 Requires<[HasHardQuad]>;
1475 // Floating point conditional move instrucitons with %fcc0-%fcc3.
1476 let Predicates = [HasV9] in {
1477 let Constraints = "$f = $rd", intcc = 0 in {
1479 : F4_1<0b101100, (outs IntRegs:$rd),
1480 (ins FCCRegs:$cc, IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
1481 "mov$cond $cc, $rs2, $rd", []>;
1483 : F4_2<0b101100, (outs IntRegs:$rd),
1484 (ins FCCRegs:$cc, i32imm:$simm11, IntRegs:$f, CCOp:$cond),
1485 "mov$cond $cc, $simm11, $rd", []>;
1487 : F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
1488 (ins FCCRegs:$opf_cc, FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
1489 "fmovs$cond $opf_cc, $rs2, $rd", []>;
1491 : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd),
1492 (ins FCCRegs:$opf_cc, DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
1493 "fmovd$cond $opf_cc, $rs2, $rd", []>;
1495 : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
1496 (ins FCCRegs:$opf_cc, QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
1497 "fmovq$cond $opf_cc, $rs2, $rd", []>,
1498 Requires<[HasHardQuad]>;
1499 } // Constraints = "$f = $rd", ...
1500 } // let Predicates = [hasV9]
1503 // POPCrr - This does a ctpop of a 64-bit register. As such, we have to clear
1504 // the top 32-bits before using it. To do this clearing, we use a SRLri X,0.
1506 def POPCrr : F3_1<2, 0b101110,
1507 (outs IntRegs:$rd), (ins IntRegs:$rs2),
1508 "popc $rs2, $rd", []>, Requires<[HasV9]>;
1509 def : Pat<(ctpop i32:$src),
1510 (POPCrr (SRLri $src, 0))>;
1512 let Predicates = [HasV9], hasSideEffects = 1, rd = 0, rs1 = 0b01111 in
1513 def MEMBARi : F3_2<2, 0b101000, (outs), (ins simm13Op:$simm13),
1514 "membar $simm13", []>;
1516 // The CAS instruction, unlike other instructions, only comes in a
1517 // form which requires an ASI be provided. The ASI value hardcoded
1518 // here is ASI_PRIMARY, the default unprivileged ASI for SparcV9.
1519 let Predicates = [HasV9], Constraints = "$swap = $rd", asi = 0b10000000 in
1520 def CASrr: F3_1_asi<3, 0b111100,
1521 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,
1523 "cas [$rs1], $rs2, $rd",
1525 (atomic_cmp_swap_32 iPTR:$rs1, i32:$rs2, i32:$swap))]>;
1528 // CASA is supported as an instruction on some LEON3 and all LEON4 processors.
1529 // This version can be automatically lowered from C code, selecting ASI 10
1530 let Predicates = [HasLeonCASA], Constraints = "$swap = $rd", asi = 0b00001010 in
1531 def CASAasi10: F3_1_asi<3, 0b111100,
1532 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,
1534 "casa [$rs1] 10, $rs2, $rd",
1536 (atomic_cmp_swap_32 iPTR:$rs1, i32:$rs2, i32:$swap))]>;
1538 // CASA supported on some LEON3 and all LEON4 processors. Same pattern as
1539 // CASrr, above, but with a different ASI. This version is supported for
1540 // inline assembly lowering only.
1541 let Predicates = [HasLeonCASA], Constraints = "$swap = $rd" in
1542 def CASArr: F3_1_asi<3, 0b111100,
1543 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,
1544 IntRegs:$swap, i8imm:$asi),
1545 "casa [$rs1] $asi, $rs2, $rd", []>;
1547 // TODO: Add DAG sequence to lower these instructions. Currently, only provided
1548 // as inline assembler-supported instructions.
1549 let Predicates = [HasUMAC_SMAC], Defs = [Y, ASR18], Uses = [Y, ASR18] in {
1550 def SMACrr : F3_1<2, 0b111111,
1551 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2, ASRRegs:$asr18),
1552 "smac $rs1, $rs2, $rd",
1555 def SMACri : F3_2<2, 0b111111,
1556 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13, ASRRegs:$asr18),
1557 "smac $rs1, $simm13, $rd",
1560 def UMACrr : F3_1<2, 0b111110,
1561 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2, ASRRegs:$asr18),
1562 "umac $rs1, $rs2, $rd",
1565 def UMACri : F3_2<2, 0b111110,
1566 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13, ASRRegs:$asr18),
1567 "umac $rs1, $simm13, $rd",
1571 let Defs = [ICC] in {
1572 defm TADDCC : F3_12np<"taddcc", 0b100000>;
1573 defm TSUBCC : F3_12np<"tsubcc", 0b100001>;
1575 let hasSideEffects = 1 in {
1576 defm TADDCCTV : F3_12np<"taddcctv", 0b100010>;
1577 defm TSUBCCTV : F3_12np<"tsubcctv", 0b100011>;
1582 // Section A.43 - Read Privileged Register Instructions
1583 let Predicates = [HasV9] in {
1585 def RDPR : F3_1<2, 0b101010,
1586 (outs IntRegs:$rd), (ins PRRegs:$rs1),
1587 "rdpr $rs1, $rd", []>;
1590 // Section A.62 - Write Privileged Register Instructions
1591 let Predicates = [HasV9] in {
1592 def WRPRrr : F3_1<2, 0b110010,
1593 (outs PRRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
1594 "wrpr $rs1, $rs2, $rd", []>;
1595 def WRPRri : F3_2<2, 0b110010,
1596 (outs PRRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
1597 "wrpr $rs1, $simm13, $rd", []>;
1600 //===----------------------------------------------------------------------===//
1601 // Non-Instruction Patterns
1602 //===----------------------------------------------------------------------===//
1604 // Small immediates.
1605 def : Pat<(i32 simm13:$val),
1606 (ORri (i32 G0), imm:$val)>;
1607 // Arbitrary immediates.
1608 def : Pat<(i32 imm:$val),
1609 (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;
1612 // Global addresses, constant pool entries
1613 let Predicates = [Is32Bit] in {
1615 def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>;
1616 def : Pat<(SPlo tglobaladdr:$in), (ORri (i32 G0), tglobaladdr:$in)>;
1617 def : Pat<(SPhi tconstpool:$in), (SETHIi tconstpool:$in)>;
1618 def : Pat<(SPlo tconstpool:$in), (ORri (i32 G0), tconstpool:$in)>;
1620 // GlobalTLS addresses
1621 def : Pat<(SPhi tglobaltlsaddr:$in), (SETHIi tglobaltlsaddr:$in)>;
1622 def : Pat<(SPlo tglobaltlsaddr:$in), (ORri (i32 G0), tglobaltlsaddr:$in)>;
1623 def : Pat<(add (SPhi tglobaltlsaddr:$in1), (SPlo tglobaltlsaddr:$in2)),
1624 (ADDri (SETHIi tglobaltlsaddr:$in1), (tglobaltlsaddr:$in2))>;
1625 def : Pat<(xor (SPhi tglobaltlsaddr:$in1), (SPlo tglobaltlsaddr:$in2)),
1626 (XORri (SETHIi tglobaltlsaddr:$in1), (tglobaltlsaddr:$in2))>;
1629 def : Pat<(SPhi tblockaddress:$in), (SETHIi tblockaddress:$in)>;
1630 def : Pat<(SPlo tblockaddress:$in), (ORri (i32 G0), tblockaddress:$in)>;
1632 // Add reg, lo. This is used when taking the addr of a global/constpool entry.
1633 def : Pat<(add iPTR:$r, (SPlo tglobaladdr:$in)), (ADDri $r, tglobaladdr:$in)>;
1634 def : Pat<(add iPTR:$r, (SPlo tconstpool:$in)), (ADDri $r, tconstpool:$in)>;
1635 def : Pat<(add iPTR:$r, (SPlo tblockaddress:$in)),
1636 (ADDri $r, tblockaddress:$in)>;
1640 def : Pat<(call tglobaladdr:$dst),
1641 (CALL tglobaladdr:$dst)>;
1642 def : Pat<(call texternalsym:$dst),
1643 (CALL texternalsym:$dst)>;
1645 // Map integer extload's to zextloads.
1646 def : Pat<(i32 (extloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
1647 def : Pat<(i32 (extloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>;
1648 def : Pat<(i32 (extloadi8 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
1649 def : Pat<(i32 (extloadi8 ADDRri:$src)), (LDUBri ADDRri:$src)>;
1650 def : Pat<(i32 (extloadi16 ADDRrr:$src)), (LDUHrr ADDRrr:$src)>;
1651 def : Pat<(i32 (extloadi16 ADDRri:$src)), (LDUHri ADDRri:$src)>;
1653 // zextload bool -> zextload byte
1654 def : Pat<(i32 (zextloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
1655 def : Pat<(i32 (zextloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>;
1657 // store 0, addr -> store %g0, addr
1658 def : Pat<(store (i32 0), ADDRrr:$dst), (STrr ADDRrr:$dst, (i32 G0))>;
1659 def : Pat<(store (i32 0), ADDRri:$dst), (STri ADDRri:$dst, (i32 G0))>;
1661 // store bar for all atomic_fence in V8.
1662 let Predicates = [HasNoV9] in
1663 def : Pat<(atomic_fence imm, imm), (STBAR)>;
1665 // atomic_load addr -> load addr
1666 def : Pat<(i32 (atomic_load_8 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
1667 def : Pat<(i32 (atomic_load_8 ADDRri:$src)), (LDUBri ADDRri:$src)>;
1668 def : Pat<(i32 (atomic_load_16 ADDRrr:$src)), (LDUHrr ADDRrr:$src)>;
1669 def : Pat<(i32 (atomic_load_16 ADDRri:$src)), (LDUHri ADDRri:$src)>;
1670 def : Pat<(i32 (atomic_load_32 ADDRrr:$src)), (LDrr ADDRrr:$src)>;
1671 def : Pat<(i32 (atomic_load_32 ADDRri:$src)), (LDri ADDRri:$src)>;
1673 // atomic_store val, addr -> store val, addr
1674 def : Pat<(atomic_store_8 ADDRrr:$dst, i32:$val), (STBrr ADDRrr:$dst, $val)>;
1675 def : Pat<(atomic_store_8 ADDRri:$dst, i32:$val), (STBri ADDRri:$dst, $val)>;
1676 def : Pat<(atomic_store_16 ADDRrr:$dst, i32:$val), (STHrr ADDRrr:$dst, $val)>;
1677 def : Pat<(atomic_store_16 ADDRri:$dst, i32:$val), (STHri ADDRri:$dst, $val)>;
1678 def : Pat<(atomic_store_32 ADDRrr:$dst, i32:$val), (STrr ADDRrr:$dst, $val)>;
1679 def : Pat<(atomic_store_32 ADDRri:$dst, i32:$val), (STri ADDRri:$dst, $val)>;
1682 def : Pat<(extractelt (v2i32 IntPair:$Rn), 0),
1683 (i32 (EXTRACT_SUBREG IntPair:$Rn, sub_even))>;
1684 def : Pat<(extractelt (v2i32 IntPair:$Rn), 1),
1685 (i32 (EXTRACT_SUBREG IntPair:$Rn, sub_odd))>;
1688 def : Pat<(build_vector (i32 IntRegs:$a1), (i32 IntRegs:$a2)),
1690 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)), (i32 IntRegs:$a1), sub_even),
1691 (i32 IntRegs:$a2), sub_odd)>;
1694 include "SparcInstr64Bit.td"
1695 include "SparcInstrVIS.td"
1696 include "SparcInstrAliases.td"