1 //===-- SparcInstrInfo.td - Target Description for Sparc Target -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Sparc instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Instruction format superclass
16 //===----------------------------------------------------------------------===//
18 include "SparcInstrFormats.td"
20 //===----------------------------------------------------------------------===//
21 // Feature predicates.
22 //===----------------------------------------------------------------------===//
24 // True when generating 32-bit code.
25 def Is32Bit : Predicate<"!Subtarget->is64Bit()">;
27 // True when generating 64-bit code. This also implies HasV9.
28 def Is64Bit : Predicate<"Subtarget->is64Bit()">;
30 // HasV9 - This predicate is true when the target processor supports V9
31 // instructions. Note that the machine may be running in 32-bit mode.
32 def HasV9 : Predicate<"Subtarget->isV9()">,
33 AssemblerPredicate<"FeatureV9">;
35 // HasNoV9 - This predicate is true when the target doesn't have V9
36 // instructions. Use of this is just a hack for the isel not having proper
37 // costs for V8 instructions that are more expensive than their V9 ones.
38 def HasNoV9 : Predicate<"!Subtarget->isV9()">;
40 // HasVIS - This is true when the target processor has VIS extensions.
41 def HasVIS : Predicate<"Subtarget->isVIS()">,
42 AssemblerPredicate<"FeatureVIS">;
43 def HasVIS2 : Predicate<"Subtarget->isVIS2()">,
44 AssemblerPredicate<"FeatureVIS2">;
45 def HasVIS3 : Predicate<"Subtarget->isVIS3()">,
46 AssemblerPredicate<"FeatureVIS3">;
48 // HasHardQuad - This is true when the target processor supports quad floating
49 // point instructions.
50 def HasHardQuad : Predicate<"Subtarget->hasHardQuad()">;
52 // HasLeonCASA - This is true when the target processor supports the CASA
54 def HasLeonCASA : Predicate<"Subtarget->hasLeonCasa()">;
56 // HasUMAC_SMAC - This is true when the target processor supports the
57 // UMAC and SMAC instructions
58 def HasUMAC_SMAC : Predicate<"Subtarget->hasUmacSmac()">;
60 def HasNoFdivSqrtFix : Predicate<"!Subtarget->fixAllFDIVSQRT()">;
61 def HasNoFmulsFix : Predicate<"!Subtarget->replaceFMULS()">;
62 def HasNoFsmuldFix : Predicate<"!Subtarget->fixFSMULD()">;
64 // UseDeprecatedInsts - This predicate is true when the target processor is a
65 // V8, or when it is V9 but the V8 deprecated instructions are efficient enough
66 // to use when appropriate. In either of these cases, the instruction selector
67 // will pick deprecated instructions.
68 def UseDeprecatedInsts : Predicate<"Subtarget->useDeprecatedV8Instructions()">;
70 //===----------------------------------------------------------------------===//
71 // Instruction Pattern Stuff
72 //===----------------------------------------------------------------------===//
74 def simm11 : PatLeaf<(imm), [{ return isInt<11>(N->getSExtValue()); }]>;
76 def simm13 : PatLeaf<(imm), [{ return isInt<13>(N->getSExtValue()); }]>;
78 def LO10 : SDNodeXForm<imm, [{
79 return CurDAG->getTargetConstant((unsigned)N->getZExtValue() & 1023, SDLoc(N),
83 def HI22 : SDNodeXForm<imm, [{
84 // Transformation function: shift the immediate value down into the low bits.
85 return CurDAG->getTargetConstant((unsigned)N->getZExtValue() >> 10, SDLoc(N),
89 def SETHIimm : PatLeaf<(imm), [{
90 return isShiftedUInt<22, 10>(N->getZExtValue());
94 def ADDRrr : ComplexPattern<iPTR, 2, "SelectADDRrr", [], []>;
95 def ADDRri : ComplexPattern<iPTR, 2, "SelectADDRri", [frameindex], []>;
98 def SparcMEMrrAsmOperand : AsmOperandClass {
100 let ParserMethod = "parseMEMOperand";
103 def SparcMEMriAsmOperand : AsmOperandClass {
105 let ParserMethod = "parseMEMOperand";
108 def MEMrr : Operand<iPTR> {
109 let PrintMethod = "printMemOperand";
110 let MIOperandInfo = (ops ptr_rc, ptr_rc);
111 let ParserMatchClass = SparcMEMrrAsmOperand;
113 def MEMri : Operand<iPTR> {
114 let PrintMethod = "printMemOperand";
115 let MIOperandInfo = (ops ptr_rc, i32imm);
116 let ParserMatchClass = SparcMEMriAsmOperand;
119 def TLSSym : Operand<iPTR>;
121 // Branch targets have OtherVT type.
122 def brtarget : Operand<OtherVT> {
123 let EncoderMethod = "getBranchTargetOpValue";
126 def bprtarget : Operand<OtherVT> {
127 let EncoderMethod = "getBranchPredTargetOpValue";
130 def bprtarget16 : Operand<OtherVT> {
131 let EncoderMethod = "getBranchOnRegTargetOpValue";
134 def calltarget : Operand<i32> {
135 let EncoderMethod = "getCallTargetOpValue";
136 let DecoderMethod = "DecodeCall";
139 def simm13Op : Operand<i32> {
140 let DecoderMethod = "DecodeSIMM13";
143 // Operand for printing out a condition code.
144 let PrintMethod = "printCCOperand" in
145 def CCOp : Operand<i32>;
148 SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
150 SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisSameAs<0, 1>]>;
152 SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
154 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>]>;
156 SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
158 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
160 SDTypeProfile<1, 1, [SDTCisVT<0, f64>, SDTCisFP<1>]>;
162 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f64>]>;
165 SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, SDTCisPtrTy<2>]>;
167 SDTypeProfile<1, 2, [SDTCisPtrTy<0>, SDTCisPtrTy<1>]>;
169 def SDTSPeh_sjlj_setjmp : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
170 def SDTSPeh_sjlj_longjmp: SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
172 def SPcmpicc : SDNode<"SPISD::CMPICC", SDTSPcmpicc, [SDNPOutGlue]>;
173 def SPcmpfcc : SDNode<"SPISD::CMPFCC", SDTSPcmpfcc, [SDNPOutGlue]>;
174 def SPbricc : SDNode<"SPISD::BRICC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
175 def SPbrxcc : SDNode<"SPISD::BRXCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
176 def SPbrfcc : SDNode<"SPISD::BRFCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
178 def SPhi : SDNode<"SPISD::Hi", SDTIntUnaryOp>;
179 def SPlo : SDNode<"SPISD::Lo", SDTIntUnaryOp>;
181 def SPftoi : SDNode<"SPISD::FTOI", SDTSPFTOI>;
182 def SPitof : SDNode<"SPISD::ITOF", SDTSPITOF>;
183 def SPftox : SDNode<"SPISD::FTOX", SDTSPFTOX>;
184 def SPxtof : SDNode<"SPISD::XTOF", SDTSPXTOF>;
186 def SPselecticc : SDNode<"SPISD::SELECT_ICC", SDTSPselectcc, [SDNPInGlue]>;
187 def SPselectxcc : SDNode<"SPISD::SELECT_XCC", SDTSPselectcc, [SDNPInGlue]>;
188 def SPselectfcc : SDNode<"SPISD::SELECT_FCC", SDTSPselectcc, [SDNPInGlue]>;
190 def SPsjlj_setjmp: SDNode<"SPISD::EH_SJLJ_SETJMP",
192 [SDNPHasChain, SDNPSideEffect]>;
193 def SPsjlj_longjmp: SDNode<"SPISD::EH_SJLJ_LONGJMP",
194 SDTSPeh_sjlj_longjmp,
195 [SDNPHasChain, SDNPSideEffect]>;
197 // These are target-independent nodes, but have target-specific formats.
198 def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
199 def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
202 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart,
203 [SDNPHasChain, SDNPOutGlue]>;
204 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd,
205 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
207 def SDT_SPCall : SDTypeProfile<0, -1, [SDTCisVT<0, i32>]>;
208 def call : SDNode<"SPISD::CALL", SDT_SPCall,
209 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
212 def SDT_SPRet : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
213 def retflag : SDNode<"SPISD::RET_FLAG", SDT_SPRet,
214 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
216 def flushw : SDNode<"SPISD::FLUSHW", SDTNone,
217 [SDNPHasChain, SDNPSideEffect, SDNPMayStore]>;
219 def tlsadd : SDNode<"SPISD::TLS_ADD", SDTSPtlsadd>;
220 def tlsld : SDNode<"SPISD::TLS_LD", SDTSPtlsld>;
221 def tlscall : SDNode<"SPISD::TLS_CALL", SDT_SPCall,
222 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
225 def getPCX : Operand<iPTR> {
226 let PrintMethod = "printGetPCX";
229 //===----------------------------------------------------------------------===//
230 // SPARC Flag Conditions
231 //===----------------------------------------------------------------------===//
233 // Note that these values must be kept in sync with the CCOp::CondCode enum
235 class ICC_VAL<int N> : PatLeaf<(i32 N)>;
236 def ICC_NE : ICC_VAL< 9>; // Not Equal
237 def ICC_E : ICC_VAL< 1>; // Equal
238 def ICC_G : ICC_VAL<10>; // Greater
239 def ICC_LE : ICC_VAL< 2>; // Less or Equal
240 def ICC_GE : ICC_VAL<11>; // Greater or Equal
241 def ICC_L : ICC_VAL< 3>; // Less
242 def ICC_GU : ICC_VAL<12>; // Greater Unsigned
243 def ICC_LEU : ICC_VAL< 4>; // Less or Equal Unsigned
244 def ICC_CC : ICC_VAL<13>; // Carry Clear/Great or Equal Unsigned
245 def ICC_CS : ICC_VAL< 5>; // Carry Set/Less Unsigned
246 def ICC_POS : ICC_VAL<14>; // Positive
247 def ICC_NEG : ICC_VAL< 6>; // Negative
248 def ICC_VC : ICC_VAL<15>; // Overflow Clear
249 def ICC_VS : ICC_VAL< 7>; // Overflow Set
251 class FCC_VAL<int N> : PatLeaf<(i32 N)>;
252 def FCC_U : FCC_VAL<23>; // Unordered
253 def FCC_G : FCC_VAL<22>; // Greater
254 def FCC_UG : FCC_VAL<21>; // Unordered or Greater
255 def FCC_L : FCC_VAL<20>; // Less
256 def FCC_UL : FCC_VAL<19>; // Unordered or Less
257 def FCC_LG : FCC_VAL<18>; // Less or Greater
258 def FCC_NE : FCC_VAL<17>; // Not Equal
259 def FCC_E : FCC_VAL<25>; // Equal
260 def FCC_UE : FCC_VAL<26>; // Unordered or Equal
261 def FCC_GE : FCC_VAL<27>; // Greater or Equal
262 def FCC_UGE : FCC_VAL<28>; // Unordered or Greater or Equal
263 def FCC_LE : FCC_VAL<29>; // Less or Equal
264 def FCC_ULE : FCC_VAL<30>; // Unordered or Less or Equal
265 def FCC_O : FCC_VAL<31>; // Ordered
267 class CPCC_VAL<int N> : PatLeaf<(i32 N)>;
268 def CPCC_3 : CPCC_VAL<39>; // 3
269 def CPCC_2 : CPCC_VAL<38>; // 2
270 def CPCC_23 : CPCC_VAL<37>; // 2 or 3
271 def CPCC_1 : CPCC_VAL<36>; // 1
272 def CPCC_13 : CPCC_VAL<35>; // 1 or 3
273 def CPCC_12 : CPCC_VAL<34>; // 1 or 2
274 def CPCC_123 : CPCC_VAL<33>; // 1 or 2 or 3
275 def CPCC_0 : CPCC_VAL<41>; // 0
276 def CPCC_03 : CPCC_VAL<42>; // 0 or 3
277 def CPCC_02 : CPCC_VAL<43>; // 0 or 2
278 def CPCC_023 : CPCC_VAL<44>; // 0 or 2 or 3
279 def CPCC_01 : CPCC_VAL<45>; // 0 or 1
280 def CPCC_013 : CPCC_VAL<46>; // 0 or 1 or 3
281 def CPCC_012 : CPCC_VAL<47>; // 0 or 1 or 2
283 //===----------------------------------------------------------------------===//
284 // Instruction Class Templates
285 //===----------------------------------------------------------------------===//
287 /// F3_12 multiclass - Define a normal F3_1/F3_2 pattern in one shot.
288 multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode,
289 RegisterClass RC, ValueType Ty, Operand immOp,
290 InstrItinClass itin = IIC_iu_instr> {
291 def rr : F3_1<2, Op3Val,
292 (outs RC:$rd), (ins RC:$rs1, RC:$rs2),
293 !strconcat(OpcStr, " $rs1, $rs2, $rd"),
294 [(set Ty:$rd, (OpNode Ty:$rs1, Ty:$rs2))],
296 def ri : F3_2<2, Op3Val,
297 (outs RC:$rd), (ins RC:$rs1, immOp:$simm13),
298 !strconcat(OpcStr, " $rs1, $simm13, $rd"),
299 [(set Ty:$rd, (OpNode Ty:$rs1, (Ty simm13:$simm13)))],
303 /// F3_12np multiclass - Define a normal F3_1/F3_2 pattern in one shot, with no
305 multiclass F3_12np<string OpcStr, bits<6> Op3Val, InstrItinClass itin = IIC_iu_instr> {
306 def rr : F3_1<2, Op3Val,
307 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
308 !strconcat(OpcStr, " $rs1, $rs2, $rd"), [],
310 def ri : F3_2<2, Op3Val,
311 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
312 !strconcat(OpcStr, " $rs1, $simm13, $rd"), [],
316 // Load multiclass - Define both Reg+Reg/Reg+Imm patterns in one shot.
317 multiclass Load<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode,
318 RegisterClass RC, ValueType Ty, InstrItinClass itin = IIC_iu_instr> {
319 def rr : F3_1<3, Op3Val,
320 (outs RC:$dst), (ins MEMrr:$addr),
321 !strconcat(OpcStr, " [$addr], $dst"),
322 [(set Ty:$dst, (OpNode ADDRrr:$addr))],
324 def ri : F3_2<3, Op3Val,
325 (outs RC:$dst), (ins MEMri:$addr),
326 !strconcat(OpcStr, " [$addr], $dst"),
327 [(set Ty:$dst, (OpNode ADDRri:$addr))],
331 // TODO: Instructions of the LoadASI class are currently asm only; hooking up
332 // CodeGen's address spaces to use these is a future task.
333 class LoadASI<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode,
334 RegisterClass RC, ValueType Ty, InstrItinClass itin = NoItinerary> :
335 F3_1_asi<3, Op3Val, (outs RC:$dst), (ins MEMrr:$addr, i8imm:$asi),
336 !strconcat(OpcStr, "a [$addr] $asi, $dst"),
339 // LoadA multiclass - As above, but also define alternate address space variant
340 multiclass LoadA<string OpcStr, bits<6> Op3Val, bits<6> LoadAOp3Val,
341 SDPatternOperator OpNode, RegisterClass RC, ValueType Ty,
342 InstrItinClass itin = NoItinerary> :
343 Load<OpcStr, Op3Val, OpNode, RC, Ty, itin> {
344 def Arr : LoadASI<OpcStr, LoadAOp3Val, OpNode, RC, Ty>;
347 // The LDSTUB instruction is supported for asm only.
348 // It is unlikely that general-purpose code could make use of it.
349 // CAS is preferred for sparc v9.
350 def LDSTUBrr : F3_1<3, 0b001101, (outs IntRegs:$dst), (ins MEMrr:$addr),
351 "ldstub [$addr], $dst", []>;
352 def LDSTUBri : F3_2<3, 0b001101, (outs IntRegs:$dst), (ins MEMri:$addr),
353 "ldstub [$addr], $dst", []>;
354 def LDSTUBArr : F3_1_asi<3, 0b011101, (outs IntRegs:$dst),
355 (ins MEMrr:$addr, i8imm:$asi),
356 "ldstuba [$addr] $asi, $dst", []>;
358 // Store multiclass - Define both Reg+Reg/Reg+Imm patterns in one shot.
359 multiclass Store<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode,
360 RegisterClass RC, ValueType Ty, InstrItinClass itin = IIC_st> {
361 def rr : F3_1<3, Op3Val,
362 (outs), (ins MEMrr:$addr, RC:$rd),
363 !strconcat(OpcStr, " $rd, [$addr]"),
364 [(OpNode Ty:$rd, ADDRrr:$addr)],
366 def ri : F3_2<3, Op3Val,
367 (outs), (ins MEMri:$addr, RC:$rd),
368 !strconcat(OpcStr, " $rd, [$addr]"),
369 [(OpNode Ty:$rd, ADDRri:$addr)],
373 // TODO: Instructions of the StoreASI class are currently asm only; hooking up
374 // CodeGen's address spaces to use these is a future task.
375 class StoreASI<string OpcStr, bits<6> Op3Val,
376 SDPatternOperator OpNode, RegisterClass RC, ValueType Ty,
377 InstrItinClass itin = IIC_st> :
378 F3_1_asi<3, Op3Val, (outs), (ins MEMrr:$addr, RC:$rd, i8imm:$asi),
379 !strconcat(OpcStr, "a $rd, [$addr] $asi"),
383 multiclass StoreA<string OpcStr, bits<6> Op3Val, bits<6> StoreAOp3Val,
384 SDPatternOperator OpNode, RegisterClass RC, ValueType Ty,
385 InstrItinClass itin = IIC_st> :
386 Store<OpcStr, Op3Val, OpNode, RC, Ty> {
387 def Arr : StoreASI<OpcStr, StoreAOp3Val, OpNode, RC, Ty, itin>;
390 //===----------------------------------------------------------------------===//
392 //===----------------------------------------------------------------------===//
394 // Pseudo instructions.
395 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
396 : InstSP<outs, ins, asmstr, pattern> {
397 let isCodeGenOnly = 1;
403 def GETPCX : Pseudo<(outs getPCX:$getpcseq), (ins), "$getpcseq", [] >;
406 let Defs = [O6], Uses = [O6] in {
407 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
408 "!ADJCALLSTACKDOWN $amt",
409 [(callseq_start timm:$amt)]>;
410 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
411 "!ADJCALLSTACKUP $amt1",
412 [(callseq_end timm:$amt1, timm:$amt2)]>;
415 let hasSideEffects = 1, mayStore = 1 in {
416 let rd = 0, rs1 = 0, rs2 = 0 in
417 def FLUSHW : F3_1<0b10, 0b101011, (outs), (ins),
419 [(flushw)]>, Requires<[HasV9]>;
420 let rd = 0, rs1 = 1, simm13 = 3 in
421 def TA3 : F3_2<0b10, 0b111010, (outs), (ins),
426 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
427 // instruction selection into a branch sequence. This has to handle all
428 // permutations of selection between i32/f32/f64 on ICC and FCC.
429 // Expanded after instruction selection.
430 let Uses = [ICC], usesCustomInserter = 1 in {
431 def SELECT_CC_Int_ICC
432 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
433 "; SELECT_CC_Int_ICC PSEUDO!",
434 [(set i32:$dst, (SPselecticc i32:$T, i32:$F, imm:$Cond))]>;
436 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),
437 "; SELECT_CC_FP_ICC PSEUDO!",
438 [(set f32:$dst, (SPselecticc f32:$T, f32:$F, imm:$Cond))]>;
440 def SELECT_CC_DFP_ICC
441 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
442 "; SELECT_CC_DFP_ICC PSEUDO!",
443 [(set f64:$dst, (SPselecticc f64:$T, f64:$F, imm:$Cond))]>;
445 def SELECT_CC_QFP_ICC
446 : Pseudo<(outs QFPRegs:$dst), (ins QFPRegs:$T, QFPRegs:$F, i32imm:$Cond),
447 "; SELECT_CC_QFP_ICC PSEUDO!",
448 [(set f128:$dst, (SPselecticc f128:$T, f128:$F, imm:$Cond))]>;
451 let usesCustomInserter = 1, Uses = [FCC0] in {
453 def SELECT_CC_Int_FCC
454 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
455 "; SELECT_CC_Int_FCC PSEUDO!",
456 [(set i32:$dst, (SPselectfcc i32:$T, i32:$F, imm:$Cond))]>;
459 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),
460 "; SELECT_CC_FP_FCC PSEUDO!",
461 [(set f32:$dst, (SPselectfcc f32:$T, f32:$F, imm:$Cond))]>;
462 def SELECT_CC_DFP_FCC
463 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
464 "; SELECT_CC_DFP_FCC PSEUDO!",
465 [(set f64:$dst, (SPselectfcc f64:$T, f64:$F, imm:$Cond))]>;
466 def SELECT_CC_QFP_FCC
467 : Pseudo<(outs QFPRegs:$dst), (ins QFPRegs:$T, QFPRegs:$F, i32imm:$Cond),
468 "; SELECT_CC_QFP_FCC PSEUDO!",
469 [(set f128:$dst, (SPselectfcc f128:$T, f128:$F, imm:$Cond))]>;
472 let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
474 def EH_SJLJ_SETJMP32ri : Pseudo<(outs IntRegs:$dst), (ins MEMri:$buf),
476 [(set i32:$dst, (SPsjlj_setjmp ADDRri:$buf))]>,
478 def EH_SJLJ_SETJMP32rr : Pseudo<(outs IntRegs:$dst), (ins MEMrr:$buf),
480 [(set i32:$dst, (SPsjlj_setjmp ADDRrr:$buf))]>,
482 let isTerminator = 1 in
483 def EH_SJLJ_LONGJMP32ri : Pseudo<(outs), (ins MEMri:$buf),
484 "#EH_SJLJ_LONGJMP32",
485 [(SPsjlj_longjmp ADDRri:$buf)]>,
487 def EH_SJLJ_LONGJMP32rr : Pseudo<(outs), (ins MEMrr:$buf),
488 "#EH_SJLJ_LONGJMP32",
489 [(SPsjlj_longjmp ADDRrr:$buf)]>,
493 // Section B.1 - Load Integer Instructions, p. 90
494 let DecoderMethod = "DecodeLoadInt" in {
495 defm LDSB : LoadA<"ldsb", 0b001001, 0b011001, sextloadi8, IntRegs, i32>;
496 defm LDSH : LoadA<"ldsh", 0b001010, 0b011010, sextloadi16, IntRegs, i32>;
497 defm LDUB : LoadA<"ldub", 0b000001, 0b010001, zextloadi8, IntRegs, i32>;
498 defm LDUH : LoadA<"lduh", 0b000010, 0b010010, zextloadi16, IntRegs, i32>;
499 defm LD : LoadA<"ld", 0b000000, 0b010000, load, IntRegs, i32>;
502 let DecoderMethod = "DecodeLoadIntPair" in
503 defm LDD : LoadA<"ldd", 0b000011, 0b010011, load, IntPair, v2i32, IIC_ldd>;
505 // Section B.2 - Load Floating-point Instructions, p. 92
506 let DecoderMethod = "DecodeLoadFP" in {
507 defm LDF : Load<"ld", 0b100000, load, FPRegs, f32, IIC_iu_or_fpu_instr>;
508 def LDFArr : LoadASI<"ld", 0b110000, load, FPRegs, f32, IIC_iu_or_fpu_instr>,
511 let DecoderMethod = "DecodeLoadDFP" in {
512 defm LDDF : Load<"ldd", 0b100011, load, DFPRegs, f64, IIC_ldd>;
513 def LDDFArr : LoadASI<"ldd", 0b110011, load, DFPRegs, f64>,
516 let DecoderMethod = "DecodeLoadQFP" in
517 defm LDQF : LoadA<"ldq", 0b100010, 0b110010, load, QFPRegs, f128>,
518 Requires<[HasV9, HasHardQuad]>;
520 let DecoderMethod = "DecodeLoadCP" in
521 defm LDC : Load<"ld", 0b110000, load, CoprocRegs, i32>;
522 let DecoderMethod = "DecodeLoadCPPair" in
523 defm LDDC : Load<"ldd", 0b110011, load, CoprocPair, v2i32, IIC_ldd>;
525 let DecoderMethod = "DecodeLoadCP", Defs = [CPSR] in {
527 def LDCSRrr : F3_1<3, 0b110001, (outs), (ins MEMrr:$addr),
528 "ld [$addr], %csr", []>;
529 def LDCSRri : F3_2<3, 0b110001, (outs), (ins MEMri:$addr),
530 "ld [$addr], %csr", []>;
534 let DecoderMethod = "DecodeLoadFP" in
535 let Defs = [FSR] in {
537 def LDFSRrr : F3_1<3, 0b100001, (outs), (ins MEMrr:$addr),
538 "ld [$addr], %fsr", [], IIC_iu_or_fpu_instr>;
539 def LDFSRri : F3_2<3, 0b100001, (outs), (ins MEMri:$addr),
540 "ld [$addr], %fsr", [], IIC_iu_or_fpu_instr>;
543 def LDXFSRrr : F3_1<3, 0b100001, (outs), (ins MEMrr:$addr),
544 "ldx [$addr], %fsr", []>, Requires<[HasV9]>;
545 def LDXFSRri : F3_2<3, 0b100001, (outs), (ins MEMri:$addr),
546 "ldx [$addr], %fsr", []>, Requires<[HasV9]>;
550 // Section B.4 - Store Integer Instructions, p. 95
551 let DecoderMethod = "DecodeStoreInt" in {
552 defm STB : StoreA<"stb", 0b000101, 0b010101, truncstorei8, IntRegs, i32>;
553 defm STH : StoreA<"sth", 0b000110, 0b010110, truncstorei16, IntRegs, i32>;
554 defm ST : StoreA<"st", 0b000100, 0b010100, store, IntRegs, i32>;
557 let DecoderMethod = "DecodeStoreIntPair" in
558 defm STD : StoreA<"std", 0b000111, 0b010111, store, IntPair, v2i32, IIC_std>;
560 // Section B.5 - Store Floating-point Instructions, p. 97
561 let DecoderMethod = "DecodeStoreFP" in {
562 defm STF : Store<"st", 0b100100, store, FPRegs, f32>;
563 def STFArr : StoreASI<"st", 0b110100, store, FPRegs, f32>,
566 let DecoderMethod = "DecodeStoreDFP" in {
567 defm STDF : Store<"std", 0b100111, store, DFPRegs, f64, IIC_std>;
568 def STDFArr : StoreASI<"std", 0b110111, store, DFPRegs, f64>,
571 let DecoderMethod = "DecodeStoreQFP" in
572 defm STQF : StoreA<"stq", 0b100110, 0b110110, store, QFPRegs, f128>,
573 Requires<[HasV9, HasHardQuad]>;
575 let DecoderMethod = "DecodeStoreCP" in
576 defm STC : Store<"st", 0b110100, store, CoprocRegs, i32>;
578 let DecoderMethod = "DecodeStoreCPPair" in
579 defm STDC : Store<"std", 0b110111, store, CoprocPair, v2i32, IIC_std>;
581 let DecoderMethod = "DecodeStoreCP", rd = 0 in {
582 let Defs = [CPSR] in {
583 def STCSRrr : F3_1<3, 0b110101, (outs MEMrr:$addr), (ins),
584 "st %csr, [$addr]", [], IIC_st>;
585 def STCSRri : F3_2<3, 0b110101, (outs MEMri:$addr), (ins),
586 "st %csr, [$addr]", [], IIC_st>;
588 let Defs = [CPQ] in {
589 def STDCQrr : F3_1<3, 0b110110, (outs MEMrr:$addr), (ins),
590 "std %cq, [$addr]", [], IIC_std>;
591 def STDCQri : F3_2<3, 0b110110, (outs MEMri:$addr), (ins),
592 "std %cq, [$addr]", [], IIC_std>;
596 let DecoderMethod = "DecodeStoreFP" in {
598 let Defs = [FSR] in {
599 def STFSRrr : F3_1<3, 0b100101, (outs MEMrr:$addr), (ins),
600 "st %fsr, [$addr]", [], IIC_st>;
601 def STFSRri : F3_2<3, 0b100101, (outs MEMri:$addr), (ins),
602 "st %fsr, [$addr]", [], IIC_st>;
605 def STDFQrr : F3_1<3, 0b100110, (outs MEMrr:$addr), (ins),
606 "std %fq, [$addr]", [], IIC_std>;
607 def STDFQri : F3_2<3, 0b100110, (outs MEMri:$addr), (ins),
608 "std %fq, [$addr]", [], IIC_std>;
611 let rd = 1, Defs = [FSR] in {
612 def STXFSRrr : F3_1<3, 0b100101, (outs MEMrr:$addr), (ins),
613 "stx %fsr, [$addr]", []>, Requires<[HasV9]>;
614 def STXFSRri : F3_2<3, 0b100101, (outs MEMri:$addr), (ins),
615 "stx %fsr, [$addr]", []>, Requires<[HasV9]>;
619 // Section B.8 - SWAP Register with Memory Instruction
621 let Constraints = "$val = $dst", DecoderMethod = "DecodeSWAP" in {
622 def SWAPrr : F3_1<3, 0b001111,
623 (outs IntRegs:$dst), (ins MEMrr:$addr, IntRegs:$val),
624 "swap [$addr], $dst",
625 [(set i32:$dst, (atomic_swap_32 ADDRrr:$addr, i32:$val))]>;
626 def SWAPri : F3_2<3, 0b001111,
627 (outs IntRegs:$dst), (ins MEMri:$addr, IntRegs:$val),
628 "swap [$addr], $dst",
629 [(set i32:$dst, (atomic_swap_32 ADDRri:$addr, i32:$val))]>;
630 def SWAPArr : F3_1_asi<3, 0b011111,
631 (outs IntRegs:$dst), (ins MEMrr:$addr, i8imm:$asi, IntRegs:$val),
632 "swapa [$addr] $asi, $dst",
633 [/*FIXME: pattern?*/]>;
637 // Section B.9 - SETHI Instruction, p. 104
638 def SETHIi: F2_1<0b100,
639 (outs IntRegs:$rd), (ins i32imm:$imm22),
641 [(set i32:$rd, SETHIimm:$imm22)],
644 // Section B.10 - NOP Instruction, p. 105
645 // (It's a special case of SETHI)
646 let rd = 0, imm22 = 0 in
647 def NOP : F2_1<0b100, (outs), (ins), "nop", []>;
649 // Section B.11 - Logical Instructions, p. 106
650 defm AND : F3_12<"and", 0b000001, and, IntRegs, i32, simm13Op>;
652 def ANDNrr : F3_1<2, 0b000101,
653 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
654 "andn $rs1, $rs2, $rd",
655 [(set i32:$rd, (and i32:$rs1, (not i32:$rs2)))]>;
656 def ANDNri : F3_2<2, 0b000101,
657 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
658 "andn $rs1, $simm13, $rd", []>;
660 defm OR : F3_12<"or", 0b000010, or, IntRegs, i32, simm13Op>;
662 def ORNrr : F3_1<2, 0b000110,
663 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
664 "orn $rs1, $rs2, $rd",
665 [(set i32:$rd, (or i32:$rs1, (not i32:$rs2)))]>;
666 def ORNri : F3_2<2, 0b000110,
667 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
668 "orn $rs1, $simm13, $rd", []>;
669 defm XOR : F3_12<"xor", 0b000011, xor, IntRegs, i32, simm13Op>;
671 def XNORrr : F3_1<2, 0b000111,
672 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
673 "xnor $rs1, $rs2, $rd",
674 [(set i32:$rd, (not (xor i32:$rs1, i32:$rs2)))]>;
675 def XNORri : F3_2<2, 0b000111,
676 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
677 "xnor $rs1, $simm13, $rd", []>;
679 let Defs = [ICC] in {
680 defm ANDCC : F3_12np<"andcc", 0b010001>;
681 defm ANDNCC : F3_12np<"andncc", 0b010101>;
682 defm ORCC : F3_12np<"orcc", 0b010010>;
683 defm ORNCC : F3_12np<"orncc", 0b010110>;
684 defm XORCC : F3_12np<"xorcc", 0b010011>;
685 defm XNORCC : F3_12np<"xnorcc", 0b010111>;
688 // Section B.12 - Shift Instructions, p. 107
689 defm SLL : F3_12<"sll", 0b100101, shl, IntRegs, i32, simm13Op>;
690 defm SRL : F3_12<"srl", 0b100110, srl, IntRegs, i32, simm13Op>;
691 defm SRA : F3_12<"sra", 0b100111, sra, IntRegs, i32, simm13Op>;
693 // Section B.13 - Add Instructions, p. 108
694 defm ADD : F3_12<"add", 0b000000, add, IntRegs, i32, simm13Op>;
696 // "LEA" forms of add (patterns to make tblgen happy)
697 let Predicates = [Is32Bit], isCodeGenOnly = 1 in
698 def LEA_ADDri : F3_2<2, 0b000000,
699 (outs IntRegs:$dst), (ins MEMri:$addr),
700 "add ${addr:arith}, $dst",
701 [(set iPTR:$dst, ADDRri:$addr)]>;
704 defm ADDCC : F3_12<"addcc", 0b010000, addc, IntRegs, i32, simm13Op>;
707 defm ADDC : F3_12np<"addx", 0b001000>;
709 let Uses = [ICC], Defs = [ICC] in
710 defm ADDE : F3_12<"addxcc", 0b011000, adde, IntRegs, i32, simm13Op>;
712 // Section B.15 - Subtract Instructions, p. 110
713 defm SUB : F3_12 <"sub" , 0b000100, sub, IntRegs, i32, simm13Op>;
714 let Uses = [ICC], Defs = [ICC] in
715 defm SUBE : F3_12 <"subxcc" , 0b011100, sube, IntRegs, i32, simm13Op>;
718 defm SUBCC : F3_12 <"subcc", 0b010100, subc, IntRegs, i32, simm13Op>;
721 defm SUBC : F3_12np <"subx", 0b001100>;
723 // cmp (from Section A.3) is a specialized alias for subcc
724 let Defs = [ICC], rd = 0 in {
725 def CMPrr : F3_1<2, 0b010100,
726 (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
728 [(SPcmpicc i32:$rs1, i32:$rs2)]>;
729 def CMPri : F3_2<2, 0b010100,
730 (outs), (ins IntRegs:$rs1, simm13Op:$simm13),
732 [(SPcmpicc i32:$rs1, (i32 simm13:$simm13))]>;
735 // Section B.18 - Multiply Instructions, p. 113
737 defm UMUL : F3_12<"umul", 0b001010, umullohi, IntRegs, i32, simm13Op, IIC_iu_umul>;
738 defm SMUL : F3_12<"smul", 0b001011, smullohi, IntRegs, i32, simm13Op, IIC_iu_smul>;
741 let Defs = [Y, ICC] in {
742 defm UMULCC : F3_12np<"umulcc", 0b011010, IIC_iu_umul>;
743 defm SMULCC : F3_12np<"smulcc", 0b011011, IIC_iu_smul>;
746 let Defs = [Y, ICC], Uses = [Y, ICC] in {
747 defm MULSCC : F3_12np<"mulscc", 0b100100>;
750 // Section B.19 - Divide Instructions, p. 115
751 let Uses = [Y], Defs = [Y] in {
752 defm UDIV : F3_12np<"udiv", 0b001110, IIC_iu_div>;
753 defm SDIV : F3_12np<"sdiv", 0b001111, IIC_iu_div>;
756 let Uses = [Y], Defs = [Y, ICC] in {
757 defm UDIVCC : F3_12np<"udivcc", 0b011110, IIC_iu_div>;
758 defm SDIVCC : F3_12np<"sdivcc", 0b011111, IIC_iu_div>;
761 // Section B.20 - SAVE and RESTORE, p. 117
762 defm SAVE : F3_12np<"save" , 0b111100>;
763 defm RESTORE : F3_12np<"restore", 0b111101>;
765 // Section B.21 - Branch on Integer Condition Codes Instructions, p. 119
767 // unconditional branch class.
768 class BranchAlways<dag ins, string asmstr, list<dag> pattern>
769 : F2_2<0b010, 0, (outs), ins, asmstr, pattern> {
771 let isTerminator = 1;
772 let hasDelaySlot = 1;
777 def BA : BranchAlways<(ins brtarget:$imm22), "ba $imm22", [(br bb:$imm22)]>;
780 let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 in {
782 // conditional branch class:
783 class BranchSP<dag ins, string asmstr, list<dag> pattern>
784 : F2_2<0b010, 0, (outs), ins, asmstr, pattern, IIC_iu_instr>;
786 // conditional branch with annul class:
787 class BranchSPA<dag ins, string asmstr, list<dag> pattern>
788 : F2_2<0b010, 1, (outs), ins, asmstr, pattern, IIC_iu_instr>;
790 // Conditional branch class on %icc|%xcc with predication:
791 multiclass IPredBranch<string regstr, list<dag> CCPattern> {
792 def CC : F2_3<0b001, 0, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond),
793 !strconcat("b$cond ", !strconcat(regstr, ", $imm19")),
796 def CCA : F2_3<0b001, 1, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond),
797 !strconcat("b$cond,a ", !strconcat(regstr, ", $imm19")),
800 def CCNT : F2_3<0b001, 0, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond),
801 !strconcat("b$cond,pn ", !strconcat(regstr, ", $imm19")),
804 def CCANT : F2_3<0b001, 1, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond),
805 !strconcat("b$cond,a,pn ", !strconcat(regstr, ", $imm19")),
810 } // let isBranch = 1, isTerminator = 1, hasDelaySlot = 1
813 // Indirect branch instructions.
814 let isTerminator = 1, isBarrier = 1, hasDelaySlot = 1, isBranch =1,
815 isIndirectBranch = 1, rd = 0, isCodeGenOnly = 1 in {
816 def BINDrr : F3_1<2, 0b111000,
817 (outs), (ins MEMrr:$ptr),
819 [(brind ADDRrr:$ptr)]>;
820 def BINDri : F3_2<2, 0b111000,
821 (outs), (ins MEMri:$ptr),
823 [(brind ADDRri:$ptr)]>;
826 let Uses = [ICC] in {
827 def BCOND : BranchSP<(ins brtarget:$imm22, CCOp:$cond),
829 [(SPbricc bb:$imm22, imm:$cond)]>;
830 def BCONDA : BranchSPA<(ins brtarget:$imm22, CCOp:$cond),
831 "b$cond,a $imm22", []>;
833 let Predicates = [HasV9], cc = 0b00 in
834 defm BPI : IPredBranch<"%icc", []>;
837 // Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121
839 let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 in {
841 // floating-point conditional branch class:
842 class FPBranchSP<dag ins, string asmstr, list<dag> pattern>
843 : F2_2<0b110, 0, (outs), ins, asmstr, pattern, IIC_fpu_normal_instr>;
845 // floating-point conditional branch with annul class:
846 class FPBranchSPA<dag ins, string asmstr, list<dag> pattern>
847 : F2_2<0b110, 1, (outs), ins, asmstr, pattern, IIC_fpu_normal_instr>;
849 // Conditional branch class on %fcc0-%fcc3 with predication:
850 multiclass FPredBranch {
851 def CC : F2_3<0b101, 0, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond,
853 "fb$cond $cc, $imm19", [], IIC_fpu_normal_instr>;
854 def CCA : F2_3<0b101, 1, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond,
856 "fb$cond,a $cc, $imm19", [], IIC_fpu_normal_instr>;
857 def CCNT : F2_3<0b101, 0, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond,
859 "fb$cond,pn $cc, $imm19", [], IIC_fpu_normal_instr>;
860 def CCANT : F2_3<0b101, 1, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond,
862 "fb$cond,a,pn $cc, $imm19", [], IIC_fpu_normal_instr>;
864 } // let isBranch = 1, isTerminator = 1, hasDelaySlot = 1
866 let Uses = [FCC0] in {
867 def FBCOND : FPBranchSP<(ins brtarget:$imm22, CCOp:$cond),
869 [(SPbrfcc bb:$imm22, imm:$cond)]>;
870 def FBCONDA : FPBranchSPA<(ins brtarget:$imm22, CCOp:$cond),
871 "fb$cond,a $imm22", []>;
874 let Predicates = [HasV9] in
875 defm BPF : FPredBranch;
877 // Section B.22 - Branch on Co-processor Condition Codes Instructions, p. 123
878 let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 in {
880 // co-processor conditional branch class:
881 class CPBranchSP<dag ins, string asmstr, list<dag> pattern>
882 : F2_2<0b111, 0, (outs), ins, asmstr, pattern>;
884 // co-processor conditional branch with annul class:
885 class CPBranchSPA<dag ins, string asmstr, list<dag> pattern>
886 : F2_2<0b111, 1, (outs), ins, asmstr, pattern>;
888 } // let isBranch = 1, isTerminator = 1, hasDelaySlot = 1
890 def CBCOND : CPBranchSP<(ins brtarget:$imm22, CCOp:$cond),
892 [(SPbrfcc bb:$imm22, imm:$cond)]>;
893 def CBCONDA : CPBranchSPA<(ins brtarget:$imm22, CCOp:$cond),
894 "cb$cond,a $imm22", []>;
896 // Section B.24 - Call and Link Instruction, p. 125
897 // This is the only Format 1 instruction
899 hasDelaySlot = 1, isCall = 1 in {
900 def CALL : InstSP<(outs), (ins calltarget:$disp, variable_ops),
906 let Inst{29-0} = disp;
909 // indirect calls: special cases of JMPL.
910 let isCodeGenOnly = 1, rd = 15 in {
911 def CALLrr : F3_1<2, 0b111000,
912 (outs), (ins MEMrr:$ptr, variable_ops),
914 [(call ADDRrr:$ptr)],
916 def CALLri : F3_2<2, 0b111000,
917 (outs), (ins MEMri:$ptr, variable_ops),
919 [(call ADDRri:$ptr)],
924 // Section B.25 - Jump and Link Instruction
927 let isTerminator = 1, hasDelaySlot = 1, isBarrier = 1,
928 DecoderMethod = "DecodeJMPL" in {
929 def JMPLrr: F3_1<2, 0b111000,
930 (outs IntRegs:$dst), (ins MEMrr:$addr),
934 def JMPLri: F3_2<2, 0b111000,
935 (outs IntRegs:$dst), (ins MEMri:$addr),
941 // Section A.3 - Synthetic Instructions, p. 85
942 // special cases of JMPL:
943 let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, isBarrier = 1,
944 isCodeGenOnly = 1 in {
945 let rd = 0, rs1 = 15 in
946 def RETL: F3_2<2, 0b111000,
947 (outs), (ins i32imm:$val),
949 [(retflag simm13:$val)],
952 let rd = 0, rs1 = 31 in
953 def RET: F3_2<2, 0b111000,
954 (outs), (ins i32imm:$val),
960 // Section B.26 - Return from Trap Instruction
961 let isReturn = 1, isTerminator = 1, hasDelaySlot = 1,
962 isBarrier = 1, rd = 0, DecoderMethod = "DecodeReturn" in {
963 def RETTrr : F3_1<2, 0b111001,
964 (outs), (ins MEMrr:$addr),
968 def RETTri : F3_2<2, 0b111001,
969 (outs), (ins MEMri:$addr),
976 // Section B.27 - Trap on Integer Condition Codes Instruction
977 // conditional branch class:
978 let DecoderNamespace = "SparcV8", DecoderMethod = "DecodeTRAP", hasSideEffects = 1, Uses = [ICC], cc = 0b00 in
980 def TRAPrr : TRAPSPrr<0b111010,
981 (outs), (ins IntRegs:$rs1, IntRegs:$rs2, CCOp:$cond),
982 "t$cond $rs1 + $rs2",
984 def TRAPri : TRAPSPri<0b111010,
985 (outs), (ins IntRegs:$rs1, i32imm:$imm, CCOp:$cond),
986 "t$cond $rs1 + $imm",
990 multiclass TRAP<string regStr> {
991 def rr : TRAPSPrr<0b111010,
992 (outs), (ins IntRegs:$rs1, IntRegs:$rs2, CCOp:$cond),
993 !strconcat(!strconcat("t$cond ", regStr), ", $rs1 + $rs2"),
995 def ri : TRAPSPri<0b111010,
996 (outs), (ins IntRegs:$rs1, i32imm:$imm, CCOp:$cond),
997 !strconcat(!strconcat("t$cond ", regStr), ", $rs1 + $imm"),
1001 let DecoderNamespace = "SparcV9", DecoderMethod = "DecodeTRAP", Predicates = [HasV9], hasSideEffects = 1, Uses = [ICC], cc = 0b00 in
1002 defm TICC : TRAP<"%icc">;
1005 let isBarrier = 1, isTerminator = 1, rd = 0b01000, rs1 = 0, simm13 = 5 in
1006 def TA5 : F3_2<0b10, 0b111010, (outs), (ins), "ta 5", [(trap)]>;
1008 // Section B.28 - Read State Register Instructions
1010 def RDASR : F3_1<2, 0b101000,
1011 (outs IntRegs:$rd), (ins ASRRegs:$rs1),
1012 "rd $rs1, $rd", []>;
1014 // PSR, WIM, and TBR don't exist on the SparcV9, only the V8.
1015 let Predicates = [HasNoV9] in {
1016 let rs2 = 0, rs1 = 0, Uses=[PSR] in
1017 def RDPSR : F3_1<2, 0b101001,
1018 (outs IntRegs:$rd), (ins),
1019 "rd %psr, $rd", []>;
1021 let rs2 = 0, rs1 = 0, Uses=[WIM] in
1022 def RDWIM : F3_1<2, 0b101010,
1023 (outs IntRegs:$rd), (ins),
1024 "rd %wim, $rd", []>;
1026 let rs2 = 0, rs1 = 0, Uses=[TBR] in
1027 def RDTBR : F3_1<2, 0b101011,
1028 (outs IntRegs:$rd), (ins),
1029 "rd %tbr, $rd", []>;
1032 // Section B.29 - Write State Register Instructions
1033 def WRASRrr : F3_1<2, 0b110000,
1034 (outs ASRRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
1035 "wr $rs1, $rs2, $rd", []>;
1036 def WRASRri : F3_2<2, 0b110000,
1037 (outs ASRRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
1038 "wr $rs1, $simm13, $rd", []>;
1040 // PSR, WIM, and TBR don't exist on the SparcV9, only the V8.
1041 let Predicates = [HasNoV9] in {
1042 let Defs = [PSR], rd=0 in {
1043 def WRPSRrr : F3_1<2, 0b110001,
1044 (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
1045 "wr $rs1, $rs2, %psr", []>;
1046 def WRPSRri : F3_2<2, 0b110001,
1047 (outs), (ins IntRegs:$rs1, simm13Op:$simm13),
1048 "wr $rs1, $simm13, %psr", []>;
1051 let Defs = [WIM], rd=0 in {
1052 def WRWIMrr : F3_1<2, 0b110010,
1053 (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
1054 "wr $rs1, $rs2, %wim", []>;
1055 def WRWIMri : F3_2<2, 0b110010,
1056 (outs), (ins IntRegs:$rs1, simm13Op:$simm13),
1057 "wr $rs1, $simm13, %wim", []>;
1060 let Defs = [TBR], rd=0 in {
1061 def WRTBRrr : F3_1<2, 0b110011,
1062 (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
1063 "wr $rs1, $rs2, %tbr", []>;
1064 def WRTBRri : F3_2<2, 0b110011,
1065 (outs), (ins IntRegs:$rs1, simm13Op:$simm13),
1066 "wr $rs1, $simm13, %tbr", []>;
1070 // Section B.30 - STBAR Instruction
1071 let hasSideEffects = 1, rd = 0, rs1 = 0b01111, rs2 = 0 in
1072 def STBAR : F3_1<2, 0b101000, (outs), (ins), "stbar", []>;
1075 // Section B.31 - Unimplmented Instruction
1077 def UNIMP : F2_1<0b000, (outs), (ins i32imm:$imm22),
1078 "unimp $imm22", []>;
1080 // Section B.32 - Flush Instruction Memory
1082 def FLUSHrr : F3_1<2, 0b111011, (outs), (ins MEMrr:$addr),
1084 def FLUSHri : F3_2<2, 0b111011, (outs), (ins MEMri:$addr),
1087 // The no-arg FLUSH is only here for the benefit of the InstAlias
1088 // "flush", which cannot seem to use FLUSHrr, due to the inability
1089 // to construct a MEMrr with fixed G0 registers.
1090 let rs1 = 0, rs2 = 0 in
1091 def FLUSH : F3_1<2, 0b111011, (outs), (ins), "flush %g0", []>;
1094 // Section B.33 - Floating-point Operate (FPop) Instructions
1096 // Convert Integer to Floating-point Instructions, p. 141
1097 def FITOS : F3_3u<2, 0b110100, 0b011000100,
1098 (outs FPRegs:$rd), (ins FPRegs:$rs2),
1100 [(set FPRegs:$rd, (SPitof FPRegs:$rs2))],
1101 IIC_fpu_fast_instr>;
1102 def FITOD : F3_3u<2, 0b110100, 0b011001000,
1103 (outs DFPRegs:$rd), (ins FPRegs:$rs2),
1105 [(set DFPRegs:$rd, (SPitof FPRegs:$rs2))],
1106 IIC_fpu_fast_instr>;
1107 def FITOQ : F3_3u<2, 0b110100, 0b011001100,
1108 (outs QFPRegs:$rd), (ins FPRegs:$rs2),
1110 [(set QFPRegs:$rd, (SPitof FPRegs:$rs2))]>,
1111 Requires<[HasHardQuad]>;
1113 // Convert Floating-point to Integer Instructions, p. 142
1114 def FSTOI : F3_3u<2, 0b110100, 0b011010001,
1115 (outs FPRegs:$rd), (ins FPRegs:$rs2),
1117 [(set FPRegs:$rd, (SPftoi FPRegs:$rs2))],
1118 IIC_fpu_fast_instr>;
1119 def FDTOI : F3_3u<2, 0b110100, 0b011010010,
1120 (outs FPRegs:$rd), (ins DFPRegs:$rs2),
1122 [(set FPRegs:$rd, (SPftoi DFPRegs:$rs2))],
1123 IIC_fpu_fast_instr>;
1124 def FQTOI : F3_3u<2, 0b110100, 0b011010011,
1125 (outs FPRegs:$rd), (ins QFPRegs:$rs2),
1127 [(set FPRegs:$rd, (SPftoi QFPRegs:$rs2))]>,
1128 Requires<[HasHardQuad]>;
1130 // Convert between Floating-point Formats Instructions, p. 143
1131 def FSTOD : F3_3u<2, 0b110100, 0b011001001,
1132 (outs DFPRegs:$rd), (ins FPRegs:$rs2),
1134 [(set f64:$rd, (fpextend f32:$rs2))],
1136 def FSTOQ : F3_3u<2, 0b110100, 0b011001101,
1137 (outs QFPRegs:$rd), (ins FPRegs:$rs2),
1139 [(set f128:$rd, (fpextend f32:$rs2))]>,
1140 Requires<[HasHardQuad]>;
1141 def FDTOS : F3_3u<2, 0b110100, 0b011000110,
1142 (outs FPRegs:$rd), (ins DFPRegs:$rs2),
1144 [(set f32:$rd, (fpround f64:$rs2))],
1145 IIC_fpu_fast_instr>;
1146 def FDTOQ : F3_3u<2, 0b110100, 0b011001110,
1147 (outs QFPRegs:$rd), (ins DFPRegs:$rs2),
1149 [(set f128:$rd, (fpextend f64:$rs2))]>,
1150 Requires<[HasHardQuad]>;
1151 def FQTOS : F3_3u<2, 0b110100, 0b011000111,
1152 (outs FPRegs:$rd), (ins QFPRegs:$rs2),
1154 [(set f32:$rd, (fpround f128:$rs2))]>,
1155 Requires<[HasHardQuad]>;
1156 def FQTOD : F3_3u<2, 0b110100, 0b011001011,
1157 (outs DFPRegs:$rd), (ins QFPRegs:$rs2),
1159 [(set f64:$rd, (fpround f128:$rs2))]>,
1160 Requires<[HasHardQuad]>;
1162 // Floating-point Move Instructions, p. 144
1163 def FMOVS : F3_3u<2, 0b110100, 0b000000001,
1164 (outs FPRegs:$rd), (ins FPRegs:$rs2),
1165 "fmovs $rs2, $rd", []>;
1166 def FNEGS : F3_3u<2, 0b110100, 0b000000101,
1167 (outs FPRegs:$rd), (ins FPRegs:$rs2),
1169 [(set f32:$rd, (fneg f32:$rs2))],
1171 def FABSS : F3_3u<2, 0b110100, 0b000001001,
1172 (outs FPRegs:$rd), (ins FPRegs:$rs2),
1174 [(set f32:$rd, (fabs f32:$rs2))],
1178 // Floating-point Square Root Instructions, p.145
1179 // FSQRTS generates an erratum on LEON processors, so by disabling this instruction
1180 // this will be promoted to use FSQRTD with doubles instead.
1181 let Predicates = [HasNoFdivSqrtFix] in
1182 def FSQRTS : F3_3u<2, 0b110100, 0b000101001,
1183 (outs FPRegs:$rd), (ins FPRegs:$rs2),
1185 [(set f32:$rd, (fsqrt f32:$rs2))],
1187 def FSQRTD : F3_3u<2, 0b110100, 0b000101010,
1188 (outs DFPRegs:$rd), (ins DFPRegs:$rs2),
1190 [(set f64:$rd, (fsqrt f64:$rs2))],
1192 def FSQRTQ : F3_3u<2, 0b110100, 0b000101011,
1193 (outs QFPRegs:$rd), (ins QFPRegs:$rs2),
1195 [(set f128:$rd, (fsqrt f128:$rs2))]>,
1196 Requires<[HasHardQuad]>;
1200 // Floating-point Add and Subtract Instructions, p. 146
1201 def FADDS : F3_3<2, 0b110100, 0b001000001,
1202 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
1203 "fadds $rs1, $rs2, $rd",
1204 [(set f32:$rd, (fadd f32:$rs1, f32:$rs2))],
1205 IIC_fpu_fast_instr>;
1206 def FADDD : F3_3<2, 0b110100, 0b001000010,
1207 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1208 "faddd $rs1, $rs2, $rd",
1209 [(set f64:$rd, (fadd f64:$rs1, f64:$rs2))],
1210 IIC_fpu_fast_instr>;
1211 def FADDQ : F3_3<2, 0b110100, 0b001000011,
1212 (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
1213 "faddq $rs1, $rs2, $rd",
1214 [(set f128:$rd, (fadd f128:$rs1, f128:$rs2))]>,
1215 Requires<[HasHardQuad]>;
1217 def FSUBS : F3_3<2, 0b110100, 0b001000101,
1218 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
1219 "fsubs $rs1, $rs2, $rd",
1220 [(set f32:$rd, (fsub f32:$rs1, f32:$rs2))],
1221 IIC_fpu_fast_instr>;
1222 def FSUBD : F3_3<2, 0b110100, 0b001000110,
1223 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1224 "fsubd $rs1, $rs2, $rd",
1225 [(set f64:$rd, (fsub f64:$rs1, f64:$rs2))],
1226 IIC_fpu_fast_instr>;
1227 def FSUBQ : F3_3<2, 0b110100, 0b001000111,
1228 (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
1229 "fsubq $rs1, $rs2, $rd",
1230 [(set f128:$rd, (fsub f128:$rs1, f128:$rs2))]>,
1231 Requires<[HasHardQuad]>;
1234 // Floating-point Multiply and Divide Instructions, p. 147
1235 // FMULS generates an erratum on LEON processors, so by disabling this instruction
1236 // this will be promoted to use FMULD with doubles instead.
1237 let Predicates = [HasNoFmulsFix] in
1238 def FMULS : F3_3<2, 0b110100, 0b001001001,
1239 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
1240 "fmuls $rs1, $rs2, $rd",
1241 [(set f32:$rd, (fmul f32:$rs1, f32:$rs2))],
1243 def FMULD : F3_3<2, 0b110100, 0b001001010,
1244 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1245 "fmuld $rs1, $rs2, $rd",
1246 [(set f64:$rd, (fmul f64:$rs1, f64:$rs2))],
1248 def FMULQ : F3_3<2, 0b110100, 0b001001011,
1249 (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
1250 "fmulq $rs1, $rs2, $rd",
1251 [(set f128:$rd, (fmul f128:$rs1, f128:$rs2))]>,
1252 Requires<[HasHardQuad]>;
1254 let Predicates = [HasNoFsmuldFix] in
1255 def FSMULD : F3_3<2, 0b110100, 0b001101001,
1256 (outs DFPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
1257 "fsmuld $rs1, $rs2, $rd",
1258 [(set f64:$rd, (fmul (fpextend f32:$rs1),
1259 (fpextend f32:$rs2)))],
1261 def FDMULQ : F3_3<2, 0b110100, 0b001101110,
1262 (outs QFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1263 "fdmulq $rs1, $rs2, $rd",
1264 [(set f128:$rd, (fmul (fpextend f64:$rs1),
1265 (fpextend f64:$rs2)))]>,
1266 Requires<[HasHardQuad]>;
1268 // FDIVS generates an erratum on LEON processors, so by disabling this instruction
1269 // this will be promoted to use FDIVD with doubles instead.
1270 def FDIVS : F3_3<2, 0b110100, 0b001001101,
1271 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
1272 "fdivs $rs1, $rs2, $rd",
1273 [(set f32:$rd, (fdiv f32:$rs1, f32:$rs2))],
1275 def FDIVD : F3_3<2, 0b110100, 0b001001110,
1276 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1277 "fdivd $rs1, $rs2, $rd",
1278 [(set f64:$rd, (fdiv f64:$rs1, f64:$rs2))],
1280 def FDIVQ : F3_3<2, 0b110100, 0b001001111,
1281 (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
1282 "fdivq $rs1, $rs2, $rd",
1283 [(set f128:$rd, (fdiv f128:$rs1, f128:$rs2))]>,
1284 Requires<[HasHardQuad]>;
1286 // Floating-point Compare Instructions, p. 148
1287 // Note: the 2nd template arg is different for these guys.
1288 // Note 2: the result of a FCMP is not available until the 2nd cycle
1289 // after the instr is retired, but there is no interlock in Sparc V8.
1290 // This behavior is modeled with a forced noop after the instruction in
1293 let Defs = [FCC0], rd = 0, isCodeGenOnly = 1 in {
1294 def FCMPS : F3_3c<2, 0b110101, 0b001010001,
1295 (outs), (ins FPRegs:$rs1, FPRegs:$rs2),
1297 [(SPcmpfcc f32:$rs1, f32:$rs2)],
1298 IIC_fpu_fast_instr>;
1299 def FCMPD : F3_3c<2, 0b110101, 0b001010010,
1300 (outs), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1302 [(SPcmpfcc f64:$rs1, f64:$rs2)],
1303 IIC_fpu_fast_instr>;
1304 def FCMPQ : F3_3c<2, 0b110101, 0b001010011,
1305 (outs), (ins QFPRegs:$rs1, QFPRegs:$rs2),
1307 [(SPcmpfcc f128:$rs1, f128:$rs2)]>,
1308 Requires<[HasHardQuad]>;
1311 //===----------------------------------------------------------------------===//
1312 // Instructions for Thread Local Storage(TLS).
1313 //===----------------------------------------------------------------------===//
1314 let isCodeGenOnly = 1, isAsmParserOnly = 1 in {
1315 def TLS_ADDrr : F3_1<2, 0b000000,
1317 (ins IntRegs:$rs1, IntRegs:$rs2, TLSSym:$sym),
1318 "add $rs1, $rs2, $rd, $sym",
1320 (tlsadd i32:$rs1, i32:$rs2, tglobaltlsaddr:$sym))]>;
1323 def TLS_LDrr : F3_1<3, 0b000000,
1324 (outs IntRegs:$dst), (ins MEMrr:$addr, TLSSym:$sym),
1325 "ld [$addr], $dst, $sym",
1327 (tlsld ADDRrr:$addr, tglobaltlsaddr:$sym))]>;
1329 let Uses = [O6], isCall = 1, hasDelaySlot = 1 in
1330 def TLS_CALL : InstSP<(outs),
1331 (ins calltarget:$disp, TLSSym:$sym, variable_ops),
1333 [(tlscall texternalsym:$disp, tglobaltlsaddr:$sym)],
1337 let Inst{29-0} = disp;
1341 //===----------------------------------------------------------------------===//
1343 //===----------------------------------------------------------------------===//
1345 // V9 Conditional Moves.
1346 let Predicates = [HasV9], Constraints = "$f = $rd" in {
1347 // Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual.
1348 let Uses = [ICC], intcc = 1, cc = 0b00 in {
1350 : F4_1<0b101100, (outs IntRegs:$rd),
1351 (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
1352 "mov$cond %icc, $rs2, $rd",
1353 [(set i32:$rd, (SPselecticc i32:$rs2, i32:$f, imm:$cond))]>;
1356 : F4_2<0b101100, (outs IntRegs:$rd),
1357 (ins i32imm:$simm11, IntRegs:$f, CCOp:$cond),
1358 "mov$cond %icc, $simm11, $rd",
1360 (SPselecticc simm11:$simm11, i32:$f, imm:$cond))]>;
1363 let Uses = [FCC0], intcc = 0, cc = 0b00 in {
1365 : F4_1<0b101100, (outs IntRegs:$rd),
1366 (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
1367 "mov$cond %fcc0, $rs2, $rd",
1368 [(set i32:$rd, (SPselectfcc i32:$rs2, i32:$f, imm:$cond))]>;
1370 : F4_2<0b101100, (outs IntRegs:$rd),
1371 (ins i32imm:$simm11, IntRegs:$f, CCOp:$cond),
1372 "mov$cond %fcc0, $simm11, $rd",
1374 (SPselectfcc simm11:$simm11, i32:$f, imm:$cond))]>;
1377 let Uses = [ICC], intcc = 1, opf_cc = 0b00 in {
1379 : F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
1380 (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
1381 "fmovs$cond %icc, $rs2, $rd",
1382 [(set f32:$rd, (SPselecticc f32:$rs2, f32:$f, imm:$cond))]>;
1384 : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd),
1385 (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
1386 "fmovd$cond %icc, $rs2, $rd",
1387 [(set f64:$rd, (SPselecticc f64:$rs2, f64:$f, imm:$cond))]>;
1389 : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
1390 (ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
1391 "fmovq$cond %icc, $rs2, $rd",
1392 [(set f128:$rd, (SPselecticc f128:$rs2, f128:$f, imm:$cond))]>,
1393 Requires<[HasHardQuad]>;
1396 let Uses = [FCC0], intcc = 0, opf_cc = 0b00 in {
1398 : F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
1399 (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
1400 "fmovs$cond %fcc0, $rs2, $rd",
1401 [(set f32:$rd, (SPselectfcc f32:$rs2, f32:$f, imm:$cond))]>;
1403 : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd),
1404 (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
1405 "fmovd$cond %fcc0, $rs2, $rd",
1406 [(set f64:$rd, (SPselectfcc f64:$rs2, f64:$f, imm:$cond))]>;
1408 : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
1409 (ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
1410 "fmovq$cond %fcc0, $rs2, $rd",
1411 [(set f128:$rd, (SPselectfcc f128:$rs2, f128:$f, imm:$cond))]>,
1412 Requires<[HasHardQuad]>;
1417 // Floating-Point Move Instructions, p. 164 of the V9 manual.
1418 let Predicates = [HasV9] in {
1419 def FMOVD : F3_3u<2, 0b110100, 0b000000010,
1420 (outs DFPRegs:$rd), (ins DFPRegs:$rs2),
1421 "fmovd $rs2, $rd", []>;
1422 def FMOVQ : F3_3u<2, 0b110100, 0b000000011,
1423 (outs QFPRegs:$rd), (ins QFPRegs:$rs2),
1424 "fmovq $rs2, $rd", []>,
1425 Requires<[HasHardQuad]>;
1426 def FNEGD : F3_3u<2, 0b110100, 0b000000110,
1427 (outs DFPRegs:$rd), (ins DFPRegs:$rs2),
1429 [(set f64:$rd, (fneg f64:$rs2))]>;
1430 def FNEGQ : F3_3u<2, 0b110100, 0b000000111,
1431 (outs QFPRegs:$rd), (ins QFPRegs:$rs2),
1433 [(set f128:$rd, (fneg f128:$rs2))]>,
1434 Requires<[HasHardQuad]>;
1435 def FABSD : F3_3u<2, 0b110100, 0b000001010,
1436 (outs DFPRegs:$rd), (ins DFPRegs:$rs2),
1438 [(set f64:$rd, (fabs f64:$rs2))]>;
1439 def FABSQ : F3_3u<2, 0b110100, 0b000001011,
1440 (outs QFPRegs:$rd), (ins QFPRegs:$rs2),
1442 [(set f128:$rd, (fabs f128:$rs2))]>,
1443 Requires<[HasHardQuad]>;
1446 // Floating-point compare instruction with %fcc0-%fcc3.
1447 def V9FCMPS : F3_3c<2, 0b110101, 0b001010001,
1448 (outs FCCRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
1449 "fcmps $rd, $rs1, $rs2", []>;
1450 def V9FCMPD : F3_3c<2, 0b110101, 0b001010010,
1451 (outs FCCRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1452 "fcmpd $rd, $rs1, $rs2", []>;
1453 def V9FCMPQ : F3_3c<2, 0b110101, 0b001010011,
1454 (outs FCCRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
1455 "fcmpq $rd, $rs1, $rs2", []>,
1456 Requires<[HasHardQuad]>;
1458 let hasSideEffects = 1 in {
1459 def V9FCMPES : F3_3c<2, 0b110101, 0b001010101,
1460 (outs FCCRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
1461 "fcmpes $rd, $rs1, $rs2", []>;
1462 def V9FCMPED : F3_3c<2, 0b110101, 0b001010110,
1463 (outs FCCRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1464 "fcmped $rd, $rs1, $rs2", []>;
1465 def V9FCMPEQ : F3_3c<2, 0b110101, 0b001010111,
1466 (outs FCCRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
1467 "fcmpeq $rd, $rs1, $rs2", []>,
1468 Requires<[HasHardQuad]>;
1471 // Floating point conditional move instrucitons with %fcc0-%fcc3.
1472 let Predicates = [HasV9] in {
1473 let Constraints = "$f = $rd", intcc = 0 in {
1475 : F4_1<0b101100, (outs IntRegs:$rd),
1476 (ins FCCRegs:$cc, IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
1477 "mov$cond $cc, $rs2, $rd", []>;
1479 : F4_2<0b101100, (outs IntRegs:$rd),
1480 (ins FCCRegs:$cc, i32imm:$simm11, IntRegs:$f, CCOp:$cond),
1481 "mov$cond $cc, $simm11, $rd", []>;
1483 : F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
1484 (ins FCCRegs:$opf_cc, FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
1485 "fmovs$cond $opf_cc, $rs2, $rd", []>;
1487 : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd),
1488 (ins FCCRegs:$opf_cc, DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
1489 "fmovd$cond $opf_cc, $rs2, $rd", []>;
1491 : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
1492 (ins FCCRegs:$opf_cc, QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
1493 "fmovq$cond $opf_cc, $rs2, $rd", []>,
1494 Requires<[HasHardQuad]>;
1495 } // Constraints = "$f = $rd", ...
1496 } // let Predicates = [hasV9]
1499 // POPCrr - This does a ctpop of a 64-bit register. As such, we have to clear
1500 // the top 32-bits before using it. To do this clearing, we use a SRLri X,0.
1502 def POPCrr : F3_1<2, 0b101110,
1503 (outs IntRegs:$rd), (ins IntRegs:$rs2),
1504 "popc $rs2, $rd", []>, Requires<[HasV9]>;
1505 def : Pat<(ctpop i32:$src),
1506 (POPCrr (SRLri $src, 0))>;
1508 let Predicates = [HasV9], hasSideEffects = 1, rd = 0, rs1 = 0b01111 in
1509 def MEMBARi : F3_2<2, 0b101000, (outs), (ins simm13Op:$simm13),
1510 "membar $simm13", []>;
1512 // The CAS instruction, unlike other instructions, only comes in a
1513 // form which requires an ASI be provided. The ASI value hardcoded
1514 // here is ASI_PRIMARY, the default unprivileged ASI for SparcV9.
1515 let Predicates = [HasV9], Constraints = "$swap = $rd", asi = 0b10000000 in
1516 def CASrr: F3_1_asi<3, 0b111100,
1517 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,
1519 "cas [$rs1], $rs2, $rd",
1521 (atomic_cmp_swap_32 iPTR:$rs1, i32:$rs2, i32:$swap))]>;
1524 // CASA is supported as an instruction on some LEON3 and all LEON4 processors.
1525 // This version can be automatically lowered from C code, selecting ASI 10
1526 let Predicates = [HasLeonCASA], Constraints = "$swap = $rd", asi = 0b00001010 in
1527 def CASAasi10: F3_1_asi<3, 0b111100,
1528 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,
1530 "casa [$rs1] 10, $rs2, $rd",
1532 (atomic_cmp_swap_32 iPTR:$rs1, i32:$rs2, i32:$swap))]>;
1534 // CASA supported on some LEON3 and all LEON4 processors. Same pattern as
1535 // CASrr, above, but with a different ASI. This version is supported for
1536 // inline assembly lowering only.
1537 let Predicates = [HasLeonCASA], Constraints = "$swap = $rd" in
1538 def CASArr: F3_1_asi<3, 0b111100,
1539 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,
1540 IntRegs:$swap, i8imm:$asi),
1541 "casa [$rs1] $asi, $rs2, $rd", []>;
1543 // TODO: Add DAG sequence to lower these instructions. Currently, only provided
1544 // as inline assembler-supported instructions.
1545 let Predicates = [HasUMAC_SMAC], Defs = [Y, ASR18], Uses = [Y, ASR18] in {
1546 def SMACrr : F3_1<2, 0b111111,
1547 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2, ASRRegs:$asr18),
1548 "smac $rs1, $rs2, $rd",
1551 def SMACri : F3_2<2, 0b111111,
1552 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13, ASRRegs:$asr18),
1553 "smac $rs1, $simm13, $rd",
1556 def UMACrr : F3_1<2, 0b111110,
1557 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2, ASRRegs:$asr18),
1558 "umac $rs1, $rs2, $rd",
1561 def UMACri : F3_2<2, 0b111110,
1562 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13, ASRRegs:$asr18),
1563 "umac $rs1, $simm13, $rd",
1567 let Defs = [ICC] in {
1568 defm TADDCC : F3_12np<"taddcc", 0b100000>;
1569 defm TSUBCC : F3_12np<"tsubcc", 0b100001>;
1571 let hasSideEffects = 1 in {
1572 defm TADDCCTV : F3_12np<"taddcctv", 0b100010>;
1573 defm TSUBCCTV : F3_12np<"tsubcctv", 0b100011>;
1578 // Section A.43 - Read Privileged Register Instructions
1579 let Predicates = [HasV9] in {
1581 def RDPR : F3_1<2, 0b101010,
1582 (outs IntRegs:$rd), (ins PRRegs:$rs1),
1583 "rdpr $rs1, $rd", []>;
1586 // Section A.62 - Write Privileged Register Instructions
1587 let Predicates = [HasV9] in {
1588 def WRPRrr : F3_1<2, 0b110010,
1589 (outs PRRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
1590 "wrpr $rs1, $rs2, $rd", []>;
1591 def WRPRri : F3_2<2, 0b110010,
1592 (outs PRRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
1593 "wrpr $rs1, $simm13, $rd", []>;
1596 //===----------------------------------------------------------------------===//
1597 // Non-Instruction Patterns
1598 //===----------------------------------------------------------------------===//
1600 // Small immediates.
1601 def : Pat<(i32 simm13:$val),
1602 (ORri (i32 G0), imm:$val)>;
1603 // Arbitrary immediates.
1604 def : Pat<(i32 imm:$val),
1605 (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;
1608 // Global addresses, constant pool entries
1609 let Predicates = [Is32Bit] in {
1611 def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>;
1612 def : Pat<(SPlo tglobaladdr:$in), (ORri (i32 G0), tglobaladdr:$in)>;
1613 def : Pat<(SPhi tconstpool:$in), (SETHIi tconstpool:$in)>;
1614 def : Pat<(SPlo tconstpool:$in), (ORri (i32 G0), tconstpool:$in)>;
1616 // GlobalTLS addresses
1617 def : Pat<(SPhi tglobaltlsaddr:$in), (SETHIi tglobaltlsaddr:$in)>;
1618 def : Pat<(SPlo tglobaltlsaddr:$in), (ORri (i32 G0), tglobaltlsaddr:$in)>;
1619 def : Pat<(add (SPhi tglobaltlsaddr:$in1), (SPlo tglobaltlsaddr:$in2)),
1620 (ADDri (SETHIi tglobaltlsaddr:$in1), (tglobaltlsaddr:$in2))>;
1621 def : Pat<(xor (SPhi tglobaltlsaddr:$in1), (SPlo tglobaltlsaddr:$in2)),
1622 (XORri (SETHIi tglobaltlsaddr:$in1), (tglobaltlsaddr:$in2))>;
1625 def : Pat<(SPhi tblockaddress:$in), (SETHIi tblockaddress:$in)>;
1626 def : Pat<(SPlo tblockaddress:$in), (ORri (i32 G0), tblockaddress:$in)>;
1628 // Add reg, lo. This is used when taking the addr of a global/constpool entry.
1629 def : Pat<(add iPTR:$r, (SPlo tglobaladdr:$in)), (ADDri $r, tglobaladdr:$in)>;
1630 def : Pat<(add iPTR:$r, (SPlo tconstpool:$in)), (ADDri $r, tconstpool:$in)>;
1631 def : Pat<(add iPTR:$r, (SPlo tblockaddress:$in)),
1632 (ADDri $r, tblockaddress:$in)>;
1636 def : Pat<(call tglobaladdr:$dst),
1637 (CALL tglobaladdr:$dst)>;
1638 def : Pat<(call texternalsym:$dst),
1639 (CALL texternalsym:$dst)>;
1641 // Map integer extload's to zextloads.
1642 def : Pat<(i32 (extloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
1643 def : Pat<(i32 (extloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>;
1644 def : Pat<(i32 (extloadi8 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
1645 def : Pat<(i32 (extloadi8 ADDRri:$src)), (LDUBri ADDRri:$src)>;
1646 def : Pat<(i32 (extloadi16 ADDRrr:$src)), (LDUHrr ADDRrr:$src)>;
1647 def : Pat<(i32 (extloadi16 ADDRri:$src)), (LDUHri ADDRri:$src)>;
1649 // zextload bool -> zextload byte
1650 def : Pat<(i32 (zextloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
1651 def : Pat<(i32 (zextloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>;
1653 // store 0, addr -> store %g0, addr
1654 def : Pat<(store (i32 0), ADDRrr:$dst), (STrr ADDRrr:$dst, (i32 G0))>;
1655 def : Pat<(store (i32 0), ADDRri:$dst), (STri ADDRri:$dst, (i32 G0))>;
1657 // store bar for all atomic_fence in V8.
1658 let Predicates = [HasNoV9] in
1659 def : Pat<(atomic_fence imm, imm), (STBAR)>;
1661 // atomic_load addr -> load addr
1662 def : Pat<(i32 (atomic_load_8 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
1663 def : Pat<(i32 (atomic_load_8 ADDRri:$src)), (LDUBri ADDRri:$src)>;
1664 def : Pat<(i32 (atomic_load_16 ADDRrr:$src)), (LDUHrr ADDRrr:$src)>;
1665 def : Pat<(i32 (atomic_load_16 ADDRri:$src)), (LDUHri ADDRri:$src)>;
1666 def : Pat<(i32 (atomic_load_32 ADDRrr:$src)), (LDrr ADDRrr:$src)>;
1667 def : Pat<(i32 (atomic_load_32 ADDRri:$src)), (LDri ADDRri:$src)>;
1669 // atomic_store val, addr -> store val, addr
1670 def : Pat<(atomic_store_8 ADDRrr:$dst, i32:$val), (STBrr ADDRrr:$dst, $val)>;
1671 def : Pat<(atomic_store_8 ADDRri:$dst, i32:$val), (STBri ADDRri:$dst, $val)>;
1672 def : Pat<(atomic_store_16 ADDRrr:$dst, i32:$val), (STHrr ADDRrr:$dst, $val)>;
1673 def : Pat<(atomic_store_16 ADDRri:$dst, i32:$val), (STHri ADDRri:$dst, $val)>;
1674 def : Pat<(atomic_store_32 ADDRrr:$dst, i32:$val), (STrr ADDRrr:$dst, $val)>;
1675 def : Pat<(atomic_store_32 ADDRri:$dst, i32:$val), (STri ADDRri:$dst, $val)>;
1678 def : Pat<(extractelt (v2i32 IntPair:$Rn), 0),
1679 (i32 (EXTRACT_SUBREG IntPair:$Rn, sub_even))>;
1680 def : Pat<(extractelt (v2i32 IntPair:$Rn), 1),
1681 (i32 (EXTRACT_SUBREG IntPair:$Rn, sub_odd))>;
1684 def : Pat<(build_vector (i32 IntRegs:$a1), (i32 IntRegs:$a2)),
1686 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)), (i32 IntRegs:$a1), sub_even),
1687 (i32 IntRegs:$a2), sub_odd)>;
1690 include "SparcInstr64Bit.td"
1691 include "SparcInstrVIS.td"
1692 include "SparcInstrAliases.td"