1 //===- SparcRegisterInfo.cpp - SPARC Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the SPARC implementation of the TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "SparcRegisterInfo.h"
16 #include "SparcSubtarget.h"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineLocation.h"
21 #include "llvm/Support/ErrorHandling.h"
22 #include "llvm/Target/TargetInstrInfo.h"
23 #include "llvm/Type.h"
24 #include "llvm/ADT/BitVector.h"
25 #include "llvm/ADT/STLExtras.h"
28 SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st,
29 const TargetInstrInfo &tii)
30 : SparcGenRegisterInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP),
31 Subtarget(st), TII(tii) {
34 const unsigned* SparcRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
36 static const unsigned CalleeSavedRegs[] = { 0 };
37 return CalleeSavedRegs;
40 BitVector SparcRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
41 BitVector Reserved(getNumRegs());
42 // FIXME: G1 reserved for now for large imm generation by frame code.
57 void SparcRegisterInfo::
58 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
59 MachineBasicBlock::iterator I) const {
60 MachineInstr &MI = *I;
61 DebugLoc dl = MI.getDebugLoc();
62 int Size = MI.getOperand(0).getImm();
63 if (MI.getOpcode() == SP::ADJCALLSTACKDOWN)
66 BuildMI(MBB, I, dl, TII.get(SP::ADDri), SP::O6).addReg(SP::O6).addImm(Size);
71 SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
72 int SPAdj, RegScavenger *RS) const {
73 assert(SPAdj == 0 && "Unexpected");
76 MachineInstr &MI = *II;
77 DebugLoc dl = MI.getDebugLoc();
78 while (!MI.getOperand(i).isFI()) {
80 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
83 int FrameIndex = MI.getOperand(i).getIndex();
85 // Addressable stack objects are accessed using neg. offsets from %fp
86 MachineFunction &MF = *MI.getParent()->getParent();
87 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
88 MI.getOperand(i+1).getImm();
90 // Replace frame index with a frame pointer reference.
91 if (Offset >= -4096 && Offset <= 4095) {
92 // If the offset is small enough to fit in the immediate field, directly
94 MI.getOperand(i).ChangeToRegister(SP::I6, false);
95 MI.getOperand(i+1).ChangeToImmediate(Offset);
97 // Otherwise, emit a G1 = SETHI %hi(offset). FIXME: it would be better to
98 // scavenge a register here instead of reserving G1 all of the time.
99 unsigned OffHi = (unsigned)Offset >> 10U;
100 BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
102 BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
104 // Insert: G1+%lo(offset) into the user.
105 MI.getOperand(i).ChangeToRegister(SP::G1, false);
106 MI.getOperand(i+1).ChangeToImmediate(Offset & ((1 << 10)-1));
110 void SparcRegisterInfo::
111 processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
113 unsigned SparcRegisterInfo::getRARegister() const {
117 unsigned SparcRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
121 unsigned SparcRegisterInfo::getEHExceptionRegister() const {
122 llvm_unreachable("What is the exception register");
126 unsigned SparcRegisterInfo::getEHHandlerRegister() const {
127 llvm_unreachable("What is the exception handler register");
131 int SparcRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
132 return SparcGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
135 int SparcRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const {
136 return SparcGenRegisterInfo::getLLVMRegNumFull(DwarfRegNo,0);
139 #include "SparcGenRegisterInfo.inc"