1 //===-- SparcTargetMachine.cpp - Define TargetMachine for Sparc -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 #include "SparcTargetMachine.h"
14 #include "SparcTargetObjectFile.h"
16 #include "LeonPasses.h"
17 #include "llvm/CodeGen/Passes.h"
18 #include "llvm/CodeGen/TargetPassConfig.h"
19 #include "llvm/IR/LegacyPassManager.h"
20 #include "llvm/Support/TargetRegistry.h"
23 extern "C" void LLVMInitializeSparcTarget() {
24 // Register the target.
25 RegisterTargetMachine<SparcV8TargetMachine> X(getTheSparcTarget());
26 RegisterTargetMachine<SparcV9TargetMachine> Y(getTheSparcV9Target());
27 RegisterTargetMachine<SparcelTargetMachine> Z(getTheSparcelTarget());
30 static std::string computeDataLayout(const Triple &T, bool is64Bit) {
31 // Sparc is typically big endian, but some are little.
32 std::string Ret = T.getArch() == Triple::sparcel ? "e" : "E";
35 // Some ABIs have 32bit pointers.
39 // Alignments for 64 bit integers.
42 // On SparcV9 128 floats are aligned to 128 bits, on others only to 64.
43 // On SparcV9 registers can hold 64 or 32 bits, on others only 32.
47 Ret += "-f128:64-n32";
57 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
63 /// Create an ILP32 architecture model
64 SparcTargetMachine::SparcTargetMachine(const Target &T, const Triple &TT,
65 StringRef CPU, StringRef FS,
66 const TargetOptions &Options,
67 Optional<Reloc::Model> RM,
69 CodeGenOpt::Level OL, bool is64bit)
70 : LLVMTargetMachine(T, computeDataLayout(TT, is64bit), TT, CPU, FS, Options,
71 getEffectiveRelocModel(RM), CM, OL),
72 TLOF(make_unique<SparcELFTargetObjectFile>()),
73 Subtarget(TT, CPU, FS, *this, is64bit), is64Bit(is64bit) {
77 SparcTargetMachine::~SparcTargetMachine() {}
79 const SparcSubtarget *
80 SparcTargetMachine::getSubtargetImpl(const Function &F) const {
81 Attribute CPUAttr = F.getFnAttribute("target-cpu");
82 Attribute FSAttr = F.getFnAttribute("target-features");
84 std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
85 ? CPUAttr.getValueAsString().str()
87 std::string FS = !FSAttr.hasAttribute(Attribute::None)
88 ? FSAttr.getValueAsString().str()
91 // FIXME: This is related to the code below to reset the target options,
92 // we need to know whether or not the soft float flag is set on the
93 // function, so we can enable it as a subtarget feature.
95 F.hasFnAttribute("use-soft-float") &&
96 F.getFnAttribute("use-soft-float").getValueAsString() == "true";
99 FS += FS.empty() ? "+soft-float" : ",+soft-float";
101 auto &I = SubtargetMap[CPU + FS];
103 // This needs to be done before we create a new subtarget since any
104 // creation will depend on the TM and the code generation flags on the
105 // function that reside in TargetOptions.
106 resetTargetOptions(F);
107 I = llvm::make_unique<SparcSubtarget>(TargetTriple, CPU, FS, *this,
114 /// Sparc Code Generator Pass Configuration Options.
115 class SparcPassConfig : public TargetPassConfig {
117 SparcPassConfig(SparcTargetMachine *TM, PassManagerBase &PM)
118 : TargetPassConfig(TM, PM) {}
120 SparcTargetMachine &getSparcTargetMachine() const {
121 return getTM<SparcTargetMachine>();
124 void addIRPasses() override;
125 bool addInstSelector() override;
126 void addPreEmitPass() override;
130 TargetPassConfig *SparcTargetMachine::createPassConfig(PassManagerBase &PM) {
131 return new SparcPassConfig(this, PM);
134 void SparcPassConfig::addIRPasses() {
135 addPass(createAtomicExpandPass(&getSparcTargetMachine()));
137 TargetPassConfig::addIRPasses();
140 bool SparcPassConfig::addInstSelector() {
141 addPass(createSparcISelDag(getSparcTargetMachine()));
145 void SparcPassConfig::addPreEmitPass(){
146 addPass(createSparcDelaySlotFillerPass(getSparcTargetMachine()));
148 if (this->getSparcTargetMachine().getSubtargetImpl()->insertNOPLoad())
150 addPass(new InsertNOPLoad(getSparcTargetMachine()));
152 if (this->getSparcTargetMachine().getSubtargetImpl()->fixFSMULD())
154 addPass(new FixFSMULD(getSparcTargetMachine()));
156 if (this->getSparcTargetMachine().getSubtargetImpl()->replaceFMULS())
158 addPass(new ReplaceFMULS(getSparcTargetMachine()));
160 if (this->getSparcTargetMachine().getSubtargetImpl()->detectRoundChange()) {
161 addPass(new DetectRoundChange(getSparcTargetMachine()));
163 if (this->getSparcTargetMachine().getSubtargetImpl()->fixAllFDIVSQRT())
165 addPass(new FixAllFDIVSQRT(getSparcTargetMachine()));
169 void SparcV8TargetMachine::anchor() { }
171 SparcV8TargetMachine::SparcV8TargetMachine(const Target &T, const Triple &TT,
172 StringRef CPU, StringRef FS,
173 const TargetOptions &Options,
174 Optional<Reloc::Model> RM,
176 CodeGenOpt::Level OL)
177 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
179 void SparcV9TargetMachine::anchor() { }
181 SparcV9TargetMachine::SparcV9TargetMachine(const Target &T, const Triple &TT,
182 StringRef CPU, StringRef FS,
183 const TargetOptions &Options,
184 Optional<Reloc::Model> RM,
186 CodeGenOpt::Level OL)
187 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
189 void SparcelTargetMachine::anchor() {}
191 SparcelTargetMachine::SparcelTargetMachine(const Target &T, const Triple &TT,
192 StringRef CPU, StringRef FS,
193 const TargetOptions &Options,
194 Optional<Reloc::Model> RM,
196 CodeGenOpt::Level OL)
197 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}