1 //===-- SystemZAsmParser.cpp - Parse SystemZ assembly instructions --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "InstPrinter/SystemZInstPrinter.h"
11 #include "MCTargetDesc/SystemZMCTargetDesc.h"
12 #include "llvm/ADT/STLExtras.h"
13 #include "llvm/ADT/SmallVector.h"
14 #include "llvm/ADT/StringRef.h"
15 #include "llvm/MC/MCContext.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/MC/MCInstBuilder.h"
19 #include "llvm/MC/MCParser/MCAsmLexer.h"
20 #include "llvm/MC/MCParser/MCAsmParser.h"
21 #include "llvm/MC/MCParser/MCAsmParserExtension.h"
22 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
23 #include "llvm/MC/MCParser/MCTargetAsmParser.h"
24 #include "llvm/MC/MCStreamer.h"
25 #include "llvm/MC/MCSubtargetInfo.h"
26 #include "llvm/Support/Casting.h"
27 #include "llvm/Support/ErrorHandling.h"
28 #include "llvm/Support/SMLoc.h"
29 #include "llvm/Support/TargetRegistry.h"
40 // Return true if Expr is in the range [MinValue, MaxValue].
41 static bool inRange(const MCExpr *Expr, int64_t MinValue, int64_t MaxValue) {
42 if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
43 int64_t Value = CE->getValue();
44 return Value >= MinValue && Value <= MaxValue;
76 class SystemZOperand : public MCParsedAsmOperand {
88 SMLoc StartLoc, EndLoc;
90 // A string of length Length, starting at Data.
96 // LLVM register Num, which has kind Kind. In some ways it might be
97 // easier for this class to have a register bank (general, floating-point
98 // or access) and a raw register number (0-15). This would postpone the
99 // interpretation of the operand to the add*() methods and avoid the need
100 // for context-dependent parsing. However, we do things the current way
101 // because of the virtual getReg() method, which needs to distinguish
102 // between (say) %r0 used as a single register and %r0 used as a pair.
103 // Context-dependent parsing can also give us slightly better error
104 // messages when invalid pairs like %r1 are used.
110 // Base + Disp + Index, where Base and Index are LLVM registers or 0.
111 // MemKind says what type of memory this is and RegKind says what type
112 // the base register has (ADDR32Reg or ADDR64Reg). Length is the operand
113 // length for D(L,B)-style operands, otherwise it is null.
117 unsigned MemKind : 4;
118 unsigned RegKind : 4;
126 // Imm is an immediate operand, and Sym is an optional TLS symbol
127 // for use with a __tls_get_offset marker relocation.
141 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
142 // Add as immediates when possible. Null MCExpr = 0.
144 Inst.addOperand(MCOperand::createImm(0));
145 else if (auto *CE = dyn_cast<MCConstantExpr>(Expr))
146 Inst.addOperand(MCOperand::createImm(CE->getValue()));
148 Inst.addOperand(MCOperand::createExpr(Expr));
152 SystemZOperand(OperandKind kind, SMLoc startLoc, SMLoc endLoc)
153 : Kind(kind), StartLoc(startLoc), EndLoc(endLoc) {}
155 // Create particular kinds of operand.
156 static std::unique_ptr<SystemZOperand> createInvalid(SMLoc StartLoc,
158 return make_unique<SystemZOperand>(KindInvalid, StartLoc, EndLoc);
161 static std::unique_ptr<SystemZOperand> createToken(StringRef Str, SMLoc Loc) {
162 auto Op = make_unique<SystemZOperand>(KindToken, Loc, Loc);
163 Op->Token.Data = Str.data();
164 Op->Token.Length = Str.size();
168 static std::unique_ptr<SystemZOperand>
169 createReg(RegisterKind Kind, unsigned Num, SMLoc StartLoc, SMLoc EndLoc) {
170 auto Op = make_unique<SystemZOperand>(KindReg, StartLoc, EndLoc);
176 static std::unique_ptr<SystemZOperand>
177 createImm(const MCExpr *Expr, SMLoc StartLoc, SMLoc EndLoc) {
178 auto Op = make_unique<SystemZOperand>(KindImm, StartLoc, EndLoc);
183 static std::unique_ptr<SystemZOperand>
184 createMem(MemoryKind MemKind, RegisterKind RegKind, unsigned Base,
185 const MCExpr *Disp, unsigned Index, const MCExpr *LengthImm,
186 unsigned LengthReg, SMLoc StartLoc, SMLoc EndLoc) {
187 auto Op = make_unique<SystemZOperand>(KindMem, StartLoc, EndLoc);
188 Op->Mem.MemKind = MemKind;
189 Op->Mem.RegKind = RegKind;
191 Op->Mem.Index = Index;
193 if (MemKind == BDLMem)
194 Op->Mem.Length.Imm = LengthImm;
195 if (MemKind == BDRMem)
196 Op->Mem.Length.Reg = LengthReg;
200 static std::unique_ptr<SystemZOperand>
201 createImmTLS(const MCExpr *Imm, const MCExpr *Sym,
202 SMLoc StartLoc, SMLoc EndLoc) {
203 auto Op = make_unique<SystemZOperand>(KindImmTLS, StartLoc, EndLoc);
204 Op->ImmTLS.Imm = Imm;
205 Op->ImmTLS.Sym = Sym;
210 bool isToken() const override {
211 return Kind == KindToken;
213 StringRef getToken() const {
214 assert(Kind == KindToken && "Not a token");
215 return StringRef(Token.Data, Token.Length);
218 // Register operands.
219 bool isReg() const override {
220 return Kind == KindReg;
222 bool isReg(RegisterKind RegKind) const {
223 return Kind == KindReg && Reg.Kind == RegKind;
225 unsigned getReg() const override {
226 assert(Kind == KindReg && "Not a register");
230 // Immediate operands.
231 bool isImm() const override {
232 return Kind == KindImm;
234 bool isImm(int64_t MinValue, int64_t MaxValue) const {
235 return Kind == KindImm && inRange(Imm, MinValue, MaxValue);
237 const MCExpr *getImm() const {
238 assert(Kind == KindImm && "Not an immediate");
242 // Immediate operands with optional TLS symbol.
243 bool isImmTLS() const {
244 return Kind == KindImmTLS;
247 const ImmTLSOp getImmTLS() const {
248 assert(Kind == KindImmTLS && "Not a TLS immediate");
253 bool isMem() const override {
254 return Kind == KindMem;
256 bool isMem(MemoryKind MemKind) const {
257 return (Kind == KindMem &&
258 (Mem.MemKind == MemKind ||
259 // A BDMem can be treated as a BDXMem in which the index
260 // register field is 0.
261 (Mem.MemKind == BDMem && MemKind == BDXMem)));
263 bool isMem(MemoryKind MemKind, RegisterKind RegKind) const {
264 return isMem(MemKind) && Mem.RegKind == RegKind;
266 bool isMemDisp12(MemoryKind MemKind, RegisterKind RegKind) const {
267 return isMem(MemKind, RegKind) && inRange(Mem.Disp, 0, 0xfff);
269 bool isMemDisp20(MemoryKind MemKind, RegisterKind RegKind) const {
270 return isMem(MemKind, RegKind) && inRange(Mem.Disp, -524288, 524287);
272 bool isMemDisp12Len4(RegisterKind RegKind) const {
273 return isMemDisp12(BDLMem, RegKind) && inRange(Mem.Length.Imm, 1, 0x10);
275 bool isMemDisp12Len8(RegisterKind RegKind) const {
276 return isMemDisp12(BDLMem, RegKind) && inRange(Mem.Length.Imm, 1, 0x100);
279 const MemOp& getMem() const {
280 assert(Kind == KindMem && "Not a Mem operand");
284 // Override MCParsedAsmOperand.
285 SMLoc getStartLoc() const override { return StartLoc; }
286 SMLoc getEndLoc() const override { return EndLoc; }
287 void print(raw_ostream &OS) const override;
289 /// getLocRange - Get the range between the first and last token of this
291 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
293 // Used by the TableGen code to add particular types of operand
294 // to an instruction.
295 void addRegOperands(MCInst &Inst, unsigned N) const {
296 assert(N == 1 && "Invalid number of operands");
297 Inst.addOperand(MCOperand::createReg(getReg()));
299 void addImmOperands(MCInst &Inst, unsigned N) const {
300 assert(N == 1 && "Invalid number of operands");
301 addExpr(Inst, getImm());
303 void addBDAddrOperands(MCInst &Inst, unsigned N) const {
304 assert(N == 2 && "Invalid number of operands");
305 assert(isMem(BDMem) && "Invalid operand type");
306 Inst.addOperand(MCOperand::createReg(Mem.Base));
307 addExpr(Inst, Mem.Disp);
309 void addBDXAddrOperands(MCInst &Inst, unsigned N) const {
310 assert(N == 3 && "Invalid number of operands");
311 assert(isMem(BDXMem) && "Invalid operand type");
312 Inst.addOperand(MCOperand::createReg(Mem.Base));
313 addExpr(Inst, Mem.Disp);
314 Inst.addOperand(MCOperand::createReg(Mem.Index));
316 void addBDLAddrOperands(MCInst &Inst, unsigned N) const {
317 assert(N == 3 && "Invalid number of operands");
318 assert(isMem(BDLMem) && "Invalid operand type");
319 Inst.addOperand(MCOperand::createReg(Mem.Base));
320 addExpr(Inst, Mem.Disp);
321 addExpr(Inst, Mem.Length.Imm);
323 void addBDRAddrOperands(MCInst &Inst, unsigned N) const {
324 assert(N == 3 && "Invalid number of operands");
325 assert(isMem(BDRMem) && "Invalid operand type");
326 Inst.addOperand(MCOperand::createReg(Mem.Base));
327 addExpr(Inst, Mem.Disp);
328 Inst.addOperand(MCOperand::createReg(Mem.Length.Reg));
330 void addBDVAddrOperands(MCInst &Inst, unsigned N) const {
331 assert(N == 3 && "Invalid number of operands");
332 assert(isMem(BDVMem) && "Invalid operand type");
333 Inst.addOperand(MCOperand::createReg(Mem.Base));
334 addExpr(Inst, Mem.Disp);
335 Inst.addOperand(MCOperand::createReg(Mem.Index));
337 void addImmTLSOperands(MCInst &Inst, unsigned N) const {
338 assert(N == 2 && "Invalid number of operands");
339 assert(Kind == KindImmTLS && "Invalid operand type");
340 addExpr(Inst, ImmTLS.Imm);
342 addExpr(Inst, ImmTLS.Sym);
345 // Used by the TableGen code to check for particular operand types.
346 bool isGR32() const { return isReg(GR32Reg); }
347 bool isGRH32() const { return isReg(GRH32Reg); }
348 bool isGRX32() const { return false; }
349 bool isGR64() const { return isReg(GR64Reg); }
350 bool isGR128() const { return isReg(GR128Reg); }
351 bool isADDR32() const { return isReg(ADDR32Reg); }
352 bool isADDR64() const { return isReg(ADDR64Reg); }
353 bool isADDR128() const { return false; }
354 bool isFP32() const { return isReg(FP32Reg); }
355 bool isFP64() const { return isReg(FP64Reg); }
356 bool isFP128() const { return isReg(FP128Reg); }
357 bool isVR32() const { return isReg(VR32Reg); }
358 bool isVR64() const { return isReg(VR64Reg); }
359 bool isVF128() const { return false; }
360 bool isVR128() const { return isReg(VR128Reg); }
361 bool isAR32() const { return isReg(AR32Reg); }
362 bool isCR64() const { return isReg(CR64Reg); }
363 bool isAnyReg() const { return (isReg() || isImm(0, 15)); }
364 bool isBDAddr32Disp12() const { return isMemDisp12(BDMem, ADDR32Reg); }
365 bool isBDAddr32Disp20() const { return isMemDisp20(BDMem, ADDR32Reg); }
366 bool isBDAddr64Disp12() const { return isMemDisp12(BDMem, ADDR64Reg); }
367 bool isBDAddr64Disp20() const { return isMemDisp20(BDMem, ADDR64Reg); }
368 bool isBDXAddr64Disp12() const { return isMemDisp12(BDXMem, ADDR64Reg); }
369 bool isBDXAddr64Disp20() const { return isMemDisp20(BDXMem, ADDR64Reg); }
370 bool isBDLAddr64Disp12Len4() const { return isMemDisp12Len4(ADDR64Reg); }
371 bool isBDLAddr64Disp12Len8() const { return isMemDisp12Len8(ADDR64Reg); }
372 bool isBDRAddr64Disp12() const { return isMemDisp12(BDRMem, ADDR64Reg); }
373 bool isBDVAddr64Disp12() const { return isMemDisp12(BDVMem, ADDR64Reg); }
374 bool isU1Imm() const { return isImm(0, 1); }
375 bool isU2Imm() const { return isImm(0, 3); }
376 bool isU3Imm() const { return isImm(0, 7); }
377 bool isU4Imm() const { return isImm(0, 15); }
378 bool isU6Imm() const { return isImm(0, 63); }
379 bool isU8Imm() const { return isImm(0, 255); }
380 bool isS8Imm() const { return isImm(-128, 127); }
381 bool isU12Imm() const { return isImm(0, 4095); }
382 bool isU16Imm() const { return isImm(0, 65535); }
383 bool isS16Imm() const { return isImm(-32768, 32767); }
384 bool isU32Imm() const { return isImm(0, (1LL << 32) - 1); }
385 bool isS32Imm() const { return isImm(-(1LL << 31), (1LL << 31) - 1); }
386 bool isU48Imm() const { return isImm(0, (1LL << 48) - 1); }
389 class SystemZAsmParser : public MCTargetAsmParser {
390 #define GET_ASSEMBLER_HEADER
391 #include "SystemZGenAsmMatcher.inc"
405 SMLoc StartLoc, EndLoc;
408 bool parseRegister(Register &Reg);
410 bool parseRegister(Register &Reg, RegisterGroup Group, const unsigned *Regs,
411 bool IsAddress = false);
413 OperandMatchResultTy parseRegister(OperandVector &Operands,
414 RegisterGroup Group, const unsigned *Regs,
417 OperandMatchResultTy parseAnyRegister(OperandVector &Operands);
419 bool parseAddress(bool &HaveReg1, Register &Reg1,
420 bool &HaveReg2, Register &Reg2,
421 const MCExpr *&Disp, const MCExpr *&Length);
422 bool parseAddressRegister(Register &Reg);
424 bool ParseDirectiveInsn(SMLoc L);
426 OperandMatchResultTy parseAddress(OperandVector &Operands,
427 MemoryKind MemKind, const unsigned *Regs,
428 RegisterKind RegKind);
430 OperandMatchResultTy parsePCRel(OperandVector &Operands, int64_t MinVal,
431 int64_t MaxVal, bool AllowTLS);
433 bool parseOperand(OperandVector &Operands, StringRef Mnemonic);
436 SystemZAsmParser(const MCSubtargetInfo &sti, MCAsmParser &parser,
437 const MCInstrInfo &MII,
438 const MCTargetOptions &Options)
439 : MCTargetAsmParser(Options, sti, MII), Parser(parser) {
440 MCAsmParserExtension::Initialize(Parser);
442 // Alias the .word directive to .short.
443 parser.addAliasForDirective(".word", ".short");
445 // Initialize the set of available features.
446 setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
449 // Override MCTargetAsmParser.
450 bool ParseDirective(AsmToken DirectiveID) override;
451 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
452 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
453 SMLoc NameLoc, OperandVector &Operands) override;
454 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
455 OperandVector &Operands, MCStreamer &Out,
457 bool MatchingInlineAsm) override;
459 // Used by the TableGen code to parse particular operand types.
460 OperandMatchResultTy parseGR32(OperandVector &Operands) {
461 return parseRegister(Operands, RegGR, SystemZMC::GR32Regs, GR32Reg);
463 OperandMatchResultTy parseGRH32(OperandVector &Operands) {
464 return parseRegister(Operands, RegGR, SystemZMC::GRH32Regs, GRH32Reg);
466 OperandMatchResultTy parseGRX32(OperandVector &Operands) {
467 llvm_unreachable("GRX32 should only be used for pseudo instructions");
469 OperandMatchResultTy parseGR64(OperandVector &Operands) {
470 return parseRegister(Operands, RegGR, SystemZMC::GR64Regs, GR64Reg);
472 OperandMatchResultTy parseGR128(OperandVector &Operands) {
473 return parseRegister(Operands, RegGR, SystemZMC::GR128Regs, GR128Reg);
475 OperandMatchResultTy parseADDR32(OperandVector &Operands) {
476 return parseRegister(Operands, RegGR, SystemZMC::GR32Regs, ADDR32Reg);
478 OperandMatchResultTy parseADDR64(OperandVector &Operands) {
479 return parseRegister(Operands, RegGR, SystemZMC::GR64Regs, ADDR64Reg);
481 OperandMatchResultTy parseADDR128(OperandVector &Operands) {
482 llvm_unreachable("Shouldn't be used as an operand");
484 OperandMatchResultTy parseFP32(OperandVector &Operands) {
485 return parseRegister(Operands, RegFP, SystemZMC::FP32Regs, FP32Reg);
487 OperandMatchResultTy parseFP64(OperandVector &Operands) {
488 return parseRegister(Operands, RegFP, SystemZMC::FP64Regs, FP64Reg);
490 OperandMatchResultTy parseFP128(OperandVector &Operands) {
491 return parseRegister(Operands, RegFP, SystemZMC::FP128Regs, FP128Reg);
493 OperandMatchResultTy parseVR32(OperandVector &Operands) {
494 return parseRegister(Operands, RegV, SystemZMC::VR32Regs, VR32Reg);
496 OperandMatchResultTy parseVR64(OperandVector &Operands) {
497 return parseRegister(Operands, RegV, SystemZMC::VR64Regs, VR64Reg);
499 OperandMatchResultTy parseVF128(OperandVector &Operands) {
500 llvm_unreachable("Shouldn't be used as an operand");
502 OperandMatchResultTy parseVR128(OperandVector &Operands) {
503 return parseRegister(Operands, RegV, SystemZMC::VR128Regs, VR128Reg);
505 OperandMatchResultTy parseAR32(OperandVector &Operands) {
506 return parseRegister(Operands, RegAR, SystemZMC::AR32Regs, AR32Reg);
508 OperandMatchResultTy parseCR64(OperandVector &Operands) {
509 return parseRegister(Operands, RegCR, SystemZMC::CR64Regs, CR64Reg);
511 OperandMatchResultTy parseAnyReg(OperandVector &Operands) {
512 return parseAnyRegister(Operands);
514 OperandMatchResultTy parseBDAddr32(OperandVector &Operands) {
515 return parseAddress(Operands, BDMem, SystemZMC::GR32Regs, ADDR32Reg);
517 OperandMatchResultTy parseBDAddr64(OperandVector &Operands) {
518 return parseAddress(Operands, BDMem, SystemZMC::GR64Regs, ADDR64Reg);
520 OperandMatchResultTy parseBDXAddr64(OperandVector &Operands) {
521 return parseAddress(Operands, BDXMem, SystemZMC::GR64Regs, ADDR64Reg);
523 OperandMatchResultTy parseBDLAddr64(OperandVector &Operands) {
524 return parseAddress(Operands, BDLMem, SystemZMC::GR64Regs, ADDR64Reg);
526 OperandMatchResultTy parseBDRAddr64(OperandVector &Operands) {
527 return parseAddress(Operands, BDRMem, SystemZMC::GR64Regs, ADDR64Reg);
529 OperandMatchResultTy parseBDVAddr64(OperandVector &Operands) {
530 return parseAddress(Operands, BDVMem, SystemZMC::GR64Regs, ADDR64Reg);
532 OperandMatchResultTy parsePCRel12(OperandVector &Operands) {
533 return parsePCRel(Operands, -(1LL << 12), (1LL << 12) - 1, false);
535 OperandMatchResultTy parsePCRel16(OperandVector &Operands) {
536 return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1, false);
538 OperandMatchResultTy parsePCRel24(OperandVector &Operands) {
539 return parsePCRel(Operands, -(1LL << 24), (1LL << 24) - 1, false);
541 OperandMatchResultTy parsePCRel32(OperandVector &Operands) {
542 return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1, false);
544 OperandMatchResultTy parsePCRelTLS16(OperandVector &Operands) {
545 return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1, true);
547 OperandMatchResultTy parsePCRelTLS32(OperandVector &Operands) {
548 return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1, true);
552 } // end anonymous namespace
554 #define GET_REGISTER_MATCHER
555 #define GET_SUBTARGET_FEATURE_NAME
556 #define GET_MATCHER_IMPLEMENTATION
557 #define GET_MNEMONIC_SPELL_CHECKER
558 #include "SystemZGenAsmMatcher.inc"
560 // Used for the .insn directives; contains information needed to parse the
561 // operands in the directive.
562 struct InsnMatchEntry {
566 MatchClassKind OperandKinds[5];
569 // For equal_range comparison.
571 bool operator() (const InsnMatchEntry &LHS, StringRef RHS) {
572 return LHS.Format < RHS;
574 bool operator() (StringRef LHS, const InsnMatchEntry &RHS) {
575 return LHS < RHS.Format;
577 bool operator() (const InsnMatchEntry &LHS, const InsnMatchEntry &RHS) {
578 return LHS.Format < RHS.Format;
582 // Table initializing information for parsing the .insn directive.
583 static struct InsnMatchEntry InsnMatchTable[] = {
584 /* Format, Opcode, NumOperands, OperandKinds */
585 { "e", SystemZ::InsnE, 1,
587 { "ri", SystemZ::InsnRI, 3,
588 { MCK_U32Imm, MCK_AnyReg, MCK_S16Imm } },
589 { "rie", SystemZ::InsnRIE, 4,
590 { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_PCRel16 } },
591 { "ril", SystemZ::InsnRIL, 3,
592 { MCK_U48Imm, MCK_AnyReg, MCK_PCRel32 } },
593 { "rilu", SystemZ::InsnRILU, 3,
594 { MCK_U48Imm, MCK_AnyReg, MCK_U32Imm } },
595 { "ris", SystemZ::InsnRIS, 5,
596 { MCK_U48Imm, MCK_AnyReg, MCK_S8Imm, MCK_U4Imm, MCK_BDAddr64Disp12 } },
597 { "rr", SystemZ::InsnRR, 3,
598 { MCK_U16Imm, MCK_AnyReg, MCK_AnyReg } },
599 { "rre", SystemZ::InsnRRE, 3,
600 { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg } },
601 { "rrf", SystemZ::InsnRRF, 5,
602 { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm } },
603 { "rrs", SystemZ::InsnRRS, 5,
604 { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm, MCK_BDAddr64Disp12 } },
605 { "rs", SystemZ::InsnRS, 4,
606 { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12 } },
607 { "rse", SystemZ::InsnRSE, 4,
608 { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12 } },
609 { "rsi", SystemZ::InsnRSI, 4,
610 { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_PCRel16 } },
611 { "rsy", SystemZ::InsnRSY, 4,
612 { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp20 } },
613 { "rx", SystemZ::InsnRX, 3,
614 { MCK_U32Imm, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
615 { "rxe", SystemZ::InsnRXE, 3,
616 { MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
617 { "rxf", SystemZ::InsnRXF, 4,
618 { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
619 { "rxy", SystemZ::InsnRXY, 3,
620 { MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp20 } },
621 { "s", SystemZ::InsnS, 2,
622 { MCK_U32Imm, MCK_BDAddr64Disp12 } },
623 { "si", SystemZ::InsnSI, 3,
624 { MCK_U32Imm, MCK_BDAddr64Disp12, MCK_S8Imm } },
625 { "sil", SystemZ::InsnSIL, 3,
626 { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_U16Imm } },
627 { "siy", SystemZ::InsnSIY, 3,
628 { MCK_U48Imm, MCK_BDAddr64Disp20, MCK_U8Imm } },
629 { "ss", SystemZ::InsnSS, 4,
630 { MCK_U48Imm, MCK_BDXAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg } },
631 { "sse", SystemZ::InsnSSE, 3,
632 { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12 } },
633 { "ssf", SystemZ::InsnSSF, 4,
634 { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg } }
637 static void printMCExpr(const MCExpr *E, raw_ostream &OS) {
640 if (auto *CE = dyn_cast<MCConstantExpr>(E))
642 else if (auto *UE = dyn_cast<MCUnaryExpr>(E))
644 else if (auto *BE = dyn_cast<MCBinaryExpr>(E))
646 else if (auto *SRE = dyn_cast<MCSymbolRefExpr>(E))
652 void SystemZOperand::print(raw_ostream &OS) const {
656 OS << "Token:" << getToken();
659 OS << "Reg:" << SystemZInstPrinter::getRegisterName(getReg());
663 printMCExpr(getImm(), OS);
667 printMCExpr(getImmTLS().Imm, OS);
668 if (getImmTLS().Sym) {
670 printMCExpr(getImmTLS().Sym, OS);
674 const MemOp &Op = getMem();
675 OS << "Mem:" << *cast<MCConstantExpr>(Op.Disp);
678 if (Op.MemKind == BDLMem)
679 OS << *cast<MCConstantExpr>(Op.Length.Imm) << ",";
680 else if (Op.MemKind == BDRMem)
681 OS << SystemZInstPrinter::getRegisterName(Op.Length.Reg) << ",";
683 OS << SystemZInstPrinter::getRegisterName(Op.Index) << ",";
684 OS << SystemZInstPrinter::getRegisterName(Op.Base);
694 // Parse one register of the form %<prefix><number>.
695 bool SystemZAsmParser::parseRegister(Register &Reg) {
696 Reg.StartLoc = Parser.getTok().getLoc();
699 if (Parser.getTok().isNot(AsmToken::Percent))
700 return Error(Parser.getTok().getLoc(), "register expected");
703 // Expect a register name.
704 if (Parser.getTok().isNot(AsmToken::Identifier))
705 return Error(Reg.StartLoc, "invalid register");
707 // Check that there's a prefix.
708 StringRef Name = Parser.getTok().getString();
710 return Error(Reg.StartLoc, "invalid register");
711 char Prefix = Name[0];
713 // Treat the rest of the register name as a register number.
714 if (Name.substr(1).getAsInteger(10, Reg.Num))
715 return Error(Reg.StartLoc, "invalid register");
717 // Look for valid combinations of prefix and number.
718 if (Prefix == 'r' && Reg.Num < 16)
720 else if (Prefix == 'f' && Reg.Num < 16)
722 else if (Prefix == 'v' && Reg.Num < 32)
724 else if (Prefix == 'a' && Reg.Num < 16)
726 else if (Prefix == 'c' && Reg.Num < 16)
729 return Error(Reg.StartLoc, "invalid register");
731 Reg.EndLoc = Parser.getTok().getLoc();
736 // Parse a register of group Group. If Regs is nonnull, use it to map
737 // the raw register number to LLVM numbering, with zero entries
738 // indicating an invalid register. IsAddress says whether the
739 // register appears in an address context. Allow FP Group if expecting
740 // RegV Group, since the f-prefix yields the FP group even while used
741 // with vector instructions.
742 bool SystemZAsmParser::parseRegister(Register &Reg, RegisterGroup Group,
743 const unsigned *Regs, bool IsAddress) {
744 if (parseRegister(Reg))
746 if (Reg.Group != Group && !(Reg.Group == RegFP && Group == RegV))
747 return Error(Reg.StartLoc, "invalid operand for instruction");
748 if (Regs && Regs[Reg.Num] == 0)
749 return Error(Reg.StartLoc, "invalid register pair");
750 if (Reg.Num == 0 && IsAddress)
751 return Error(Reg.StartLoc, "%r0 used in an address");
753 Reg.Num = Regs[Reg.Num];
757 // Parse a register and add it to Operands. The other arguments are as above.
759 SystemZAsmParser::parseRegister(OperandVector &Operands, RegisterGroup Group,
760 const unsigned *Regs, RegisterKind Kind) {
761 if (Parser.getTok().isNot(AsmToken::Percent))
762 return MatchOperand_NoMatch;
765 bool IsAddress = (Kind == ADDR32Reg || Kind == ADDR64Reg);
766 if (parseRegister(Reg, Group, Regs, IsAddress))
767 return MatchOperand_ParseFail;
769 Operands.push_back(SystemZOperand::createReg(Kind, Reg.Num,
770 Reg.StartLoc, Reg.EndLoc));
771 return MatchOperand_Success;
774 // Parse any type of register (including integers) and add it to Operands.
776 SystemZAsmParser::parseAnyRegister(OperandVector &Operands) {
777 // Handle integer values.
778 if (Parser.getTok().is(AsmToken::Integer)) {
779 const MCExpr *Register;
780 SMLoc StartLoc = Parser.getTok().getLoc();
781 if (Parser.parseExpression(Register))
782 return MatchOperand_ParseFail;
784 if (auto *CE = dyn_cast<MCConstantExpr>(Register)) {
785 int64_t Value = CE->getValue();
786 if (Value < 0 || Value > 15) {
787 Error(StartLoc, "invalid register");
788 return MatchOperand_ParseFail;
793 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
795 Operands.push_back(SystemZOperand::createImm(Register, StartLoc, EndLoc));
799 if (parseRegister(Reg))
800 return MatchOperand_ParseFail;
802 // Map to the correct register kind.
805 if (Reg.Group == RegGR) {
807 RegNo = SystemZMC::GR64Regs[Reg.Num];
809 else if (Reg.Group == RegFP) {
811 RegNo = SystemZMC::FP64Regs[Reg.Num];
813 else if (Reg.Group == RegV) {
815 RegNo = SystemZMC::VR128Regs[Reg.Num];
817 else if (Reg.Group == RegAR) {
819 RegNo = SystemZMC::AR32Regs[Reg.Num];
821 else if (Reg.Group == RegCR) {
823 RegNo = SystemZMC::CR64Regs[Reg.Num];
826 return MatchOperand_ParseFail;
829 Operands.push_back(SystemZOperand::createReg(Kind, RegNo,
830 Reg.StartLoc, Reg.EndLoc));
832 return MatchOperand_Success;
835 // Parse a memory operand into Reg1, Reg2, Disp, and Length.
836 bool SystemZAsmParser::parseAddress(bool &HaveReg1, Register &Reg1,
837 bool &HaveReg2, Register &Reg2,
839 const MCExpr *&Length) {
840 // Parse the displacement, which must always be present.
841 if (getParser().parseExpression(Disp))
844 // Parse the optional base and index.
848 if (getLexer().is(AsmToken::LParen)) {
851 if (getLexer().is(AsmToken::Percent)) {
852 // Parse the first register.
854 if (parseRegister(Reg1))
858 if (getParser().parseExpression(Length))
862 // Check whether there's a second register.
863 if (getLexer().is(AsmToken::Comma)) {
866 if (parseRegister(Reg2))
870 // Consume the closing bracket.
871 if (getLexer().isNot(AsmToken::RParen))
872 return Error(Parser.getTok().getLoc(), "unexpected token in address");
878 // Verify that Reg is a valid address register (base or index).
880 SystemZAsmParser::parseAddressRegister(Register &Reg) {
881 if (Reg.Group == RegV) {
882 Error(Reg.StartLoc, "invalid use of vector addressing");
884 } else if (Reg.Group != RegGR) {
885 Error(Reg.StartLoc, "invalid address register");
887 } else if (Reg.Num == 0) {
888 Error(Reg.StartLoc, "%r0 used in an address");
894 // Parse a memory operand and add it to Operands. The other arguments
897 SystemZAsmParser::parseAddress(OperandVector &Operands, MemoryKind MemKind,
898 const unsigned *Regs, RegisterKind RegKind) {
899 SMLoc StartLoc = Parser.getTok().getLoc();
900 unsigned Base = 0, Index = 0, LengthReg = 0;
902 bool HaveReg1, HaveReg2;
904 const MCExpr *Length;
905 if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Disp, Length))
906 return MatchOperand_ParseFail;
910 // If we have Reg1, it must be an address register.
912 if (parseAddressRegister(Reg1))
913 return MatchOperand_ParseFail;
914 Base = Regs[Reg1.Num];
916 // There must be no Reg2 or length.
918 Error(StartLoc, "invalid use of length addressing");
919 return MatchOperand_ParseFail;
922 Error(StartLoc, "invalid use of indexed addressing");
923 return MatchOperand_ParseFail;
927 // If we have Reg1, it must be an address register.
929 if (parseAddressRegister(Reg1))
930 return MatchOperand_ParseFail;
931 // If the are two registers, the first one is the index and the
932 // second is the base.
934 Index = Regs[Reg1.Num];
936 Base = Regs[Reg1.Num];
938 // If we have Reg2, it must be an address register.
940 if (parseAddressRegister(Reg2))
941 return MatchOperand_ParseFail;
942 Base = Regs[Reg2.Num];
944 // There must be no length.
946 Error(StartLoc, "invalid use of length addressing");
947 return MatchOperand_ParseFail;
951 // If we have Reg2, it must be an address register.
953 if (parseAddressRegister(Reg2))
954 return MatchOperand_ParseFail;
955 Base = Regs[Reg2.Num];
957 // We cannot support base+index addressing.
958 if (HaveReg1 && HaveReg2) {
959 Error(StartLoc, "invalid use of indexed addressing");
960 return MatchOperand_ParseFail;
962 // We must have a length.
964 Error(StartLoc, "missing length in address");
965 return MatchOperand_ParseFail;
969 // We must have Reg1, and it must be a GPR.
970 if (!HaveReg1 || Reg1.Group != RegGR) {
971 Error(StartLoc, "invalid operand for instruction");
972 return MatchOperand_ParseFail;
974 LengthReg = SystemZMC::GR64Regs[Reg1.Num];
975 // If we have Reg2, it must be an address register.
977 if (parseAddressRegister(Reg2))
978 return MatchOperand_ParseFail;
979 Base = Regs[Reg2.Num];
981 // There must be no length.
983 Error(StartLoc, "invalid use of length addressing");
984 return MatchOperand_ParseFail;
988 // We must have Reg1, and it must be a vector register.
989 if (!HaveReg1 || Reg1.Group != RegV) {
990 Error(StartLoc, "vector index required in address");
991 return MatchOperand_ParseFail;
993 Index = SystemZMC::VR128Regs[Reg1.Num];
994 // If we have Reg2, it must be an address register.
996 if (parseAddressRegister(Reg2))
997 return MatchOperand_ParseFail;
998 Base = Regs[Reg2.Num];
1000 // There must be no length.
1002 Error(StartLoc, "invalid use of length addressing");
1003 return MatchOperand_ParseFail;
1009 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1010 Operands.push_back(SystemZOperand::createMem(MemKind, RegKind, Base, Disp,
1011 Index, Length, LengthReg,
1013 return MatchOperand_Success;
1016 bool SystemZAsmParser::ParseDirective(AsmToken DirectiveID) {
1017 StringRef IDVal = DirectiveID.getIdentifier();
1019 if (IDVal == ".insn")
1020 return ParseDirectiveInsn(DirectiveID.getLoc());
1025 /// ParseDirectiveInsn
1026 /// ::= .insn [ format, encoding, (operands (, operands)*) ]
1027 bool SystemZAsmParser::ParseDirectiveInsn(SMLoc L) {
1028 MCAsmParser &Parser = getParser();
1030 // Expect instruction format as identifier.
1032 SMLoc ErrorLoc = Parser.getTok().getLoc();
1033 if (Parser.parseIdentifier(Format))
1034 return Error(ErrorLoc, "expected instruction format");
1036 SmallVector<std::unique_ptr<MCParsedAsmOperand>, 8> Operands;
1038 // Find entry for this format in InsnMatchTable.
1040 std::equal_range(std::begin(InsnMatchTable), std::end(InsnMatchTable),
1041 Format, CompareInsn());
1043 // If first == second, couldn't find a match in the table.
1044 if (EntryRange.first == EntryRange.second)
1045 return Error(ErrorLoc, "unrecognized format");
1047 struct InsnMatchEntry *Entry = EntryRange.first;
1049 // Format should match from equal_range.
1050 assert(Entry->Format == Format);
1052 // Parse the following operands using the table's information.
1053 for (int i = 0; i < Entry->NumOperands; i++) {
1054 MatchClassKind Kind = Entry->OperandKinds[i];
1056 SMLoc StartLoc = Parser.getTok().getLoc();
1058 // Always expect commas as separators for operands.
1059 if (getLexer().isNot(AsmToken::Comma))
1060 return Error(StartLoc, "unexpected token in directive");
1064 OperandMatchResultTy ResTy;
1065 if (Kind == MCK_AnyReg)
1066 ResTy = parseAnyReg(Operands);
1067 else if (Kind == MCK_BDXAddr64Disp12 || Kind == MCK_BDXAddr64Disp20)
1068 ResTy = parseBDXAddr64(Operands);
1069 else if (Kind == MCK_BDAddr64Disp12 || Kind == MCK_BDAddr64Disp20)
1070 ResTy = parseBDAddr64(Operands);
1071 else if (Kind == MCK_PCRel32)
1072 ResTy = parsePCRel32(Operands);
1073 else if (Kind == MCK_PCRel16)
1074 ResTy = parsePCRel16(Operands);
1076 // Only remaining operand kind is an immediate.
1078 SMLoc StartLoc = Parser.getTok().getLoc();
1080 // Expect immediate expression.
1081 if (Parser.parseExpression(Expr))
1082 return Error(StartLoc, "unexpected token in directive");
1085 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1087 Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
1088 ResTy = MatchOperand_Success;
1091 if (ResTy != MatchOperand_Success)
1095 // Build the instruction with the parsed operands.
1096 MCInst Inst = MCInstBuilder(Entry->Opcode);
1098 for (size_t i = 0; i < Operands.size(); i++) {
1099 MCParsedAsmOperand &Operand = *Operands[i];
1100 MatchClassKind Kind = Entry->OperandKinds[i];
1103 unsigned Res = validateOperandClass(Operand, Kind);
1104 if (Res != Match_Success)
1105 return Error(Operand.getStartLoc(), "unexpected operand type");
1107 // Add operands to instruction.
1108 SystemZOperand &ZOperand = static_cast<SystemZOperand &>(Operand);
1109 if (ZOperand.isReg())
1110 ZOperand.addRegOperands(Inst, 1);
1111 else if (ZOperand.isMem(BDMem))
1112 ZOperand.addBDAddrOperands(Inst, 2);
1113 else if (ZOperand.isMem(BDXMem))
1114 ZOperand.addBDXAddrOperands(Inst, 3);
1115 else if (ZOperand.isImm())
1116 ZOperand.addImmOperands(Inst, 1);
1118 llvm_unreachable("unexpected operand type");
1121 // Emit as a regular instruction.
1122 Parser.getStreamer().EmitInstruction(Inst, getSTI());
1127 bool SystemZAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
1130 if (parseRegister(Reg))
1132 if (Reg.Group == RegGR)
1133 RegNo = SystemZMC::GR64Regs[Reg.Num];
1134 else if (Reg.Group == RegFP)
1135 RegNo = SystemZMC::FP64Regs[Reg.Num];
1136 else if (Reg.Group == RegV)
1137 RegNo = SystemZMC::VR128Regs[Reg.Num];
1138 else if (Reg.Group == RegAR)
1139 RegNo = SystemZMC::AR32Regs[Reg.Num];
1140 else if (Reg.Group == RegCR)
1141 RegNo = SystemZMC::CR64Regs[Reg.Num];
1142 StartLoc = Reg.StartLoc;
1143 EndLoc = Reg.EndLoc;
1147 bool SystemZAsmParser::ParseInstruction(ParseInstructionInfo &Info,
1148 StringRef Name, SMLoc NameLoc,
1149 OperandVector &Operands) {
1150 Operands.push_back(SystemZOperand::createToken(Name, NameLoc));
1152 // Read the remaining operands.
1153 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1154 // Read the first operand.
1155 if (parseOperand(Operands, Name)) {
1159 // Read any subsequent operands.
1160 while (getLexer().is(AsmToken::Comma)) {
1162 if (parseOperand(Operands, Name)) {
1166 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1167 SMLoc Loc = getLexer().getLoc();
1168 return Error(Loc, "unexpected token in argument list");
1172 // Consume the EndOfStatement.
1177 bool SystemZAsmParser::parseOperand(OperandVector &Operands,
1178 StringRef Mnemonic) {
1179 // Check if the current operand has a custom associated parser, if so, try to
1180 // custom parse the operand, or fallback to the general approach. Force all
1181 // features to be available during the operand check, or else we will fail to
1182 // find the custom parser, and then we will later get an InvalidOperand error
1183 // instead of a MissingFeature errror.
1184 uint64_t AvailableFeatures = getAvailableFeatures();
1185 setAvailableFeatures(~(uint64_t)0);
1186 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
1187 setAvailableFeatures(AvailableFeatures);
1188 if (ResTy == MatchOperand_Success)
1191 // If there wasn't a custom match, try the generic matcher below. Otherwise,
1192 // there was a match, but an error occurred, in which case, just return that
1193 // the operand parsing failed.
1194 if (ResTy == MatchOperand_ParseFail)
1197 // Check for a register. All real register operands should have used
1198 // a context-dependent parse routine, which gives the required register
1199 // class. The code is here to mop up other cases, like those where
1200 // the instruction isn't recognized.
1201 if (Parser.getTok().is(AsmToken::Percent)) {
1203 if (parseRegister(Reg))
1205 Operands.push_back(SystemZOperand::createInvalid(Reg.StartLoc, Reg.EndLoc));
1209 // The only other type of operand is an immediate or address. As above,
1210 // real address operands should have used a context-dependent parse routine,
1211 // so we treat any plain expression as an immediate.
1212 SMLoc StartLoc = Parser.getTok().getLoc();
1213 Register Reg1, Reg2;
1214 bool HaveReg1, HaveReg2;
1216 const MCExpr *Length;
1217 if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Expr, Length))
1219 // If the register combination is not valid for any instruction, reject it.
1220 // Otherwise, fall back to reporting an unrecognized instruction.
1221 if (HaveReg1 && Reg1.Group != RegGR && Reg1.Group != RegV
1222 && parseAddressRegister(Reg1))
1224 if (HaveReg2 && parseAddressRegister(Reg2))
1228 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1229 if (HaveReg1 || HaveReg2 || Length)
1230 Operands.push_back(SystemZOperand::createInvalid(StartLoc, EndLoc));
1232 Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
1236 static std::string SystemZMnemonicSpellCheck(StringRef S, uint64_t FBS,
1237 unsigned VariantID = 0);
1239 bool SystemZAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
1240 OperandVector &Operands,
1242 uint64_t &ErrorInfo,
1243 bool MatchingInlineAsm) {
1245 unsigned MatchResult;
1247 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
1249 switch (MatchResult) {
1252 Out.EmitInstruction(Inst, getSTI());
1255 case Match_MissingFeature: {
1256 assert(ErrorInfo && "Unknown missing feature!");
1257 // Special case the error message for the very common case where only
1258 // a single subtarget feature is missing
1259 std::string Msg = "instruction requires:";
1261 for (unsigned I = 0; I < sizeof(ErrorInfo) * 8 - 1; ++I) {
1262 if (ErrorInfo & Mask) {
1264 Msg += getSubtargetFeatureName(ErrorInfo & Mask);
1268 return Error(IDLoc, Msg);
1271 case Match_InvalidOperand: {
1272 SMLoc ErrorLoc = IDLoc;
1273 if (ErrorInfo != ~0ULL) {
1274 if (ErrorInfo >= Operands.size())
1275 return Error(IDLoc, "too few operands for instruction");
1277 ErrorLoc = ((SystemZOperand &)*Operands[ErrorInfo]).getStartLoc();
1278 if (ErrorLoc == SMLoc())
1281 return Error(ErrorLoc, "invalid operand for instruction");
1284 case Match_MnemonicFail: {
1285 uint64_t FBS = ComputeAvailableFeatures(getSTI().getFeatureBits());
1286 std::string Suggestion = SystemZMnemonicSpellCheck(
1287 ((SystemZOperand &)*Operands[0]).getToken(), FBS);
1288 return Error(IDLoc, "invalid instruction" + Suggestion,
1289 ((SystemZOperand &)*Operands[0]).getLocRange());
1293 llvm_unreachable("Unexpected match type");
1296 OperandMatchResultTy
1297 SystemZAsmParser::parsePCRel(OperandVector &Operands, int64_t MinVal,
1298 int64_t MaxVal, bool AllowTLS) {
1299 MCContext &Ctx = getContext();
1300 MCStreamer &Out = getStreamer();
1302 SMLoc StartLoc = Parser.getTok().getLoc();
1303 if (getParser().parseExpression(Expr))
1304 return MatchOperand_NoMatch;
1306 // For consistency with the GNU assembler, treat immediates as offsets
1308 if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
1309 int64_t Value = CE->getValue();
1310 if ((Value & 1) || Value < MinVal || Value > MaxVal) {
1311 Error(StartLoc, "offset out of range");
1312 return MatchOperand_ParseFail;
1314 MCSymbol *Sym = Ctx.createTempSymbol();
1316 const MCExpr *Base = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None,
1318 Expr = Value == 0 ? Base : MCBinaryExpr::createAdd(Base, Expr, Ctx);
1321 // Optionally match :tls_gdcall: or :tls_ldcall: followed by a TLS symbol.
1322 const MCExpr *Sym = nullptr;
1323 if (AllowTLS && getLexer().is(AsmToken::Colon)) {
1326 if (Parser.getTok().isNot(AsmToken::Identifier)) {
1327 Error(Parser.getTok().getLoc(), "unexpected token");
1328 return MatchOperand_ParseFail;
1331 MCSymbolRefExpr::VariantKind Kind = MCSymbolRefExpr::VK_None;
1332 StringRef Name = Parser.getTok().getString();
1333 if (Name == "tls_gdcall")
1334 Kind = MCSymbolRefExpr::VK_TLSGD;
1335 else if (Name == "tls_ldcall")
1336 Kind = MCSymbolRefExpr::VK_TLSLDM;
1338 Error(Parser.getTok().getLoc(), "unknown TLS tag");
1339 return MatchOperand_ParseFail;
1343 if (Parser.getTok().isNot(AsmToken::Colon)) {
1344 Error(Parser.getTok().getLoc(), "unexpected token");
1345 return MatchOperand_ParseFail;
1349 if (Parser.getTok().isNot(AsmToken::Identifier)) {
1350 Error(Parser.getTok().getLoc(), "unexpected token");
1351 return MatchOperand_ParseFail;
1354 StringRef Identifier = Parser.getTok().getString();
1355 Sym = MCSymbolRefExpr::create(Ctx.getOrCreateSymbol(Identifier),
1361 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1364 Operands.push_back(SystemZOperand::createImmTLS(Expr, Sym,
1367 Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
1369 return MatchOperand_Success;
1372 // Force static initialization.
1373 extern "C" void LLVMInitializeSystemZAsmParser() {
1374 RegisterMCAsmParser<SystemZAsmParser> X(getTheSystemZTarget());