1 //===---------------------------------------------------------------------===//
2 // Random notes about and ideas for the SystemZ backend.
3 //===---------------------------------------------------------------------===//
5 The initial backend is deliberately restricted to z10. We should add support
6 for later architectures at some point.
10 If an inline asm ties an i32 "r" result to an i64 input, the input
11 will be treated as an i32, leaving the upper bits uninitialised.
14 define void @f4(i32 *%dst) {
15 %val = call i32 asm "blah $0", "=r,0" (i64 103)
16 store i32 %val, i32 *%dst
20 from CodeGen/SystemZ/asm-09.ll will use LHI rather than LGHI.
21 to load 103. This seems to be a general target-independent problem.
25 The tuning of the choice between LOAD ADDRESS (LA) and addition in
26 SystemZISelDAGToDAG.cpp is suspect. It should be tweaked based on
27 performance measurements.
31 There is no scheduling support.
35 We don't use the BRANCH ON INDEX instructions.
39 We only use MVC, XC and CLC for constant-length block operations.
40 We could extend them to variable-length operations too,
41 using EXECUTE RELATIVE LONG.
43 MVCIN, MVCLE and CLCLE may be worthwhile too.
47 We don't use CUSE or the TRANSLATE family of instructions for string
48 operations. The TRANSLATE ones are probably more difficult to exploit.
52 We don't take full advantage of builtins like fabsl because the calling
53 conventions require f128s to be returned by invisible reference.
57 ADD LOGICAL WITH SIGNED IMMEDIATE could be useful when we need to
58 produce a carry. SUBTRACT LOGICAL IMMEDIATE could be useful when we
59 need to produce a borrow. (Note that there are no memory forms of
60 ADD LOGICAL WITH CARRY and SUBTRACT LOGICAL WITH BORROW, so the high
61 part of 128-bit memory operations would probably need to be done
66 We don't use ICM or STCM.
70 DAGCombiner doesn't yet fold truncations of extended loads. Functions like:
72 unsigned long f (unsigned long x, unsigned short *y)
74 return (x << 32) | *y;
84 but truncating the load would give:
94 define i64 @f1(i64 %a) {
99 ought to be implemented as:
105 but two-address optimizations reverse the order of the AND and force:
112 CodeGen/SystemZ/and-04.ll has several examples of this.
116 Out-of-range displacements are usually handled by loading the full
117 address into a register. In many cases it would be better to create
118 an anchor point instead. E.g. for:
120 define void @f4a(i128 *%aptr, i64 %base) {
121 %addr = add i64 %base, 524288
122 %bptr = inttoptr i64 %addr to i128 *
123 %a = load volatile i128 *%aptr
124 %b = load i128 *%bptr
125 %add = add i128 %a, %b
126 store i128 %add, i128 *%aptr
130 (from CodeGen/SystemZ/int-add-08.ll) we load %base+524288 and %base+524296
131 into separate registers, rather than using %base+524288 as a base for both.
135 Dynamic stack allocations round the size to 8 bytes and then allocate
136 that rounded amount. It would be simpler to subtract the unrounded
137 size from the copy of the stack pointer and then align the result.
138 See CodeGen/SystemZ/alloca-01.ll for an example.
142 If needed, we can support 16-byte atomics using LPQ, STPQ and CSDG.
146 We might want to model all access registers and use them to spill
151 We might want to use the 'overflow' condition of eg. AR to support
152 llvm.sadd.with.overflow.i32 and related instructions - the generated code
153 for signed overflow check is currently quite bad. This would improve
154 the results of using -ftrapv.