1 //===-- SystemZElimCompare.cpp - Eliminate comparison instructions --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 // (1) tries to remove compares if CC already contains the required information
12 // (2) fuses compares and branches into COMPARE AND BRANCH instructions
14 //===----------------------------------------------------------------------===//
17 #include "SystemZInstrInfo.h"
18 #include "SystemZTargetMachine.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/ADT/Statistic.h"
21 #include "llvm/ADT/StringRef.h"
22 #include "llvm/CodeGen/MachineBasicBlock.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineFunctionPass.h"
25 #include "llvm/CodeGen/MachineInstr.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineOperand.h"
28 #include "llvm/MC/MCInstrDesc.h"
29 #include "llvm/Target/TargetRegisterInfo.h"
30 #include "llvm/Target/TargetSubtargetInfo.h"
36 #define DEBUG_TYPE "systemz-elim-compare"
38 STATISTIC(BranchOnCounts, "Number of branch-on-count instructions");
39 STATISTIC(LoadAndTraps, "Number of load-and-trap instructions");
40 STATISTIC(EliminatedComparisons, "Number of eliminated comparisons");
41 STATISTIC(FusedComparisons, "Number of fused compare-and-branch instructions");
45 // Represents the references to a particular register in one or more
48 Reference() = default;
50 Reference &operator|=(const Reference &Other) {
56 explicit operator bool() const { return Def || Use; }
58 // True if the register is defined or used in some form, either directly or
59 // via a sub- or super-register.
64 class SystemZElimCompare : public MachineFunctionPass {
68 SystemZElimCompare(const SystemZTargetMachine &tm)
69 : MachineFunctionPass(ID) {}
71 StringRef getPassName() const override {
72 return "SystemZ Comparison Elimination";
75 bool processBlock(MachineBasicBlock &MBB);
76 bool runOnMachineFunction(MachineFunction &F) override;
78 MachineFunctionProperties getRequiredProperties() const override {
79 return MachineFunctionProperties().set(
80 MachineFunctionProperties::Property::NoVRegs);
84 Reference getRegReferences(MachineInstr &MI, unsigned Reg);
85 bool convertToBRCT(MachineInstr &MI, MachineInstr &Compare,
86 SmallVectorImpl<MachineInstr *> &CCUsers);
87 bool convertToLoadAndTrap(MachineInstr &MI, MachineInstr &Compare,
88 SmallVectorImpl<MachineInstr *> &CCUsers);
89 bool convertToLoadAndTest(MachineInstr &MI);
90 bool adjustCCMasksForInstr(MachineInstr &MI, MachineInstr &Compare,
91 SmallVectorImpl<MachineInstr *> &CCUsers);
92 bool optimizeCompareZero(MachineInstr &Compare,
93 SmallVectorImpl<MachineInstr *> &CCUsers);
94 bool fuseCompareOperations(MachineInstr &Compare,
95 SmallVectorImpl<MachineInstr *> &CCUsers);
97 const SystemZInstrInfo *TII = nullptr;
98 const TargetRegisterInfo *TRI = nullptr;
101 char SystemZElimCompare::ID = 0;
103 } // end anonymous namespace
105 // Return true if CC is live out of MBB.
106 static bool isCCLiveOut(MachineBasicBlock &MBB) {
107 for (auto SI = MBB.succ_begin(), SE = MBB.succ_end(); SI != SE; ++SI)
108 if ((*SI)->isLiveIn(SystemZ::CC))
113 // Return true if any CC result of MI would reflect the value of Reg.
114 static bool resultTests(MachineInstr &MI, unsigned Reg) {
115 if (MI.getNumOperands() > 0 && MI.getOperand(0).isReg() &&
116 MI.getOperand(0).isDef() && MI.getOperand(0).getReg() == Reg)
119 switch (MI.getOpcode()) {
132 if (MI.getOperand(1).getReg() == Reg)
139 // Describe the references to Reg or any of its aliases in MI.
140 Reference SystemZElimCompare::getRegReferences(MachineInstr &MI, unsigned Reg) {
142 for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I) {
143 const MachineOperand &MO = MI.getOperand(I);
145 if (unsigned MOReg = MO.getReg()) {
146 if (TRI->regsOverlap(MOReg, Reg)) {
158 // Return true if this is a load and test which can be optimized the
159 // same way as compare instruction.
160 static bool isLoadAndTestAsCmp(MachineInstr &MI) {
161 // If we during isel used a load-and-test as a compare with 0, the
162 // def operand is dead.
163 return (MI.getOpcode() == SystemZ::LTEBR ||
164 MI.getOpcode() == SystemZ::LTDBR ||
165 MI.getOpcode() == SystemZ::LTXBR) &&
166 MI.getOperand(0).isDead();
169 // Return the source register of Compare, which is the unknown value
171 static unsigned getCompareSourceReg(MachineInstr &Compare) {
173 if (Compare.isCompare())
174 reg = Compare.getOperand(0).getReg();
175 else if (isLoadAndTestAsCmp(Compare))
176 reg = Compare.getOperand(1).getReg();
182 // Compare compares the result of MI against zero. If MI is an addition
183 // of -1 and if CCUsers is a single branch on nonzero, eliminate the addition
184 // and convert the branch to a BRCT(G) or BRCTH. Return true on success.
185 bool SystemZElimCompare::convertToBRCT(
186 MachineInstr &MI, MachineInstr &Compare,
187 SmallVectorImpl<MachineInstr *> &CCUsers) {
188 // Check whether we have an addition of -1.
189 unsigned Opcode = MI.getOpcode();
191 if (Opcode == SystemZ::AHI)
192 BRCT = SystemZ::BRCT;
193 else if (Opcode == SystemZ::AGHI)
194 BRCT = SystemZ::BRCTG;
195 else if (Opcode == SystemZ::AIH)
196 BRCT = SystemZ::BRCTH;
199 if (MI.getOperand(2).getImm() != -1)
202 // Check whether we have a single JLH.
203 if (CCUsers.size() != 1)
205 MachineInstr *Branch = CCUsers[0];
206 if (Branch->getOpcode() != SystemZ::BRC ||
207 Branch->getOperand(0).getImm() != SystemZ::CCMASK_ICMP ||
208 Branch->getOperand(1).getImm() != SystemZ::CCMASK_CMP_NE)
211 // We already know that there are no references to the register between
212 // MI and Compare. Make sure that there are also no references between
213 // Compare and Branch.
214 unsigned SrcReg = getCompareSourceReg(Compare);
215 MachineBasicBlock::iterator MBBI = Compare, MBBE = Branch;
216 for (++MBBI; MBBI != MBBE; ++MBBI)
217 if (getRegReferences(*MBBI, SrcReg))
220 // The transformation is OK. Rebuild Branch as a BRCT(G) or BRCTH.
221 MachineOperand Target(Branch->getOperand(2));
222 while (Branch->getNumOperands())
223 Branch->RemoveOperand(0);
224 Branch->setDesc(TII->get(BRCT));
225 MachineInstrBuilder MIB(*Branch->getParent()->getParent(), Branch);
226 MIB.add(MI.getOperand(0)).add(MI.getOperand(1)).add(Target);
227 // Add a CC def to BRCT(G), since we may have to split them again if the
228 // branch displacement overflows. BRCTH has a 32-bit displacement, so
229 // this is not necessary there.
230 if (BRCT != SystemZ::BRCTH)
231 MIB.addReg(SystemZ::CC, RegState::ImplicitDefine | RegState::Dead);
232 MI.eraseFromParent();
236 // Compare compares the result of MI against zero. If MI is a suitable load
237 // instruction and if CCUsers is a single conditional trap on zero, eliminate
238 // the load and convert the branch to a load-and-trap. Return true on success.
239 bool SystemZElimCompare::convertToLoadAndTrap(
240 MachineInstr &MI, MachineInstr &Compare,
241 SmallVectorImpl<MachineInstr *> &CCUsers) {
242 unsigned LATOpcode = TII->getLoadAndTrap(MI.getOpcode());
246 // Check whether we have a single CondTrap that traps on zero.
247 if (CCUsers.size() != 1)
249 MachineInstr *Branch = CCUsers[0];
250 if (Branch->getOpcode() != SystemZ::CondTrap ||
251 Branch->getOperand(0).getImm() != SystemZ::CCMASK_ICMP ||
252 Branch->getOperand(1).getImm() != SystemZ::CCMASK_CMP_EQ)
255 // We already know that there are no references to the register between
256 // MI and Compare. Make sure that there are also no references between
257 // Compare and Branch.
258 unsigned SrcReg = getCompareSourceReg(Compare);
259 MachineBasicBlock::iterator MBBI = Compare, MBBE = Branch;
260 for (++MBBI; MBBI != MBBE; ++MBBI)
261 if (getRegReferences(*MBBI, SrcReg))
264 // The transformation is OK. Rebuild Branch as a load-and-trap.
265 while (Branch->getNumOperands())
266 Branch->RemoveOperand(0);
267 Branch->setDesc(TII->get(LATOpcode));
268 MachineInstrBuilder(*Branch->getParent()->getParent(), Branch)
269 .add(MI.getOperand(0))
270 .add(MI.getOperand(1))
271 .add(MI.getOperand(2))
272 .add(MI.getOperand(3));
273 MI.eraseFromParent();
277 // If MI is a load instruction, try to convert it into a LOAD AND TEST.
278 // Return true on success.
279 bool SystemZElimCompare::convertToLoadAndTest(MachineInstr &MI) {
280 unsigned Opcode = TII->getLoadAndTest(MI.getOpcode());
284 MI.setDesc(TII->get(Opcode));
285 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
286 .addReg(SystemZ::CC, RegState::ImplicitDefine);
290 // The CC users in CCUsers are testing the result of a comparison of some
291 // value X against zero and we know that any CC value produced by MI
292 // would also reflect the value of X. Try to adjust CCUsers so that
293 // they test the result of MI directly, returning true on success.
294 // Leave everything unchanged on failure.
295 bool SystemZElimCompare::adjustCCMasksForInstr(
296 MachineInstr &MI, MachineInstr &Compare,
297 SmallVectorImpl<MachineInstr *> &CCUsers) {
298 int Opcode = MI.getOpcode();
299 const MCInstrDesc &Desc = TII->get(Opcode);
300 unsigned MIFlags = Desc.TSFlags;
302 // See which compare-style condition codes are available.
303 unsigned ReusableCCMask = SystemZII::getCompareZeroCCMask(MIFlags);
305 // For unsigned comparisons with zero, only equality makes sense.
306 unsigned CompareFlags = Compare.getDesc().TSFlags;
307 if (CompareFlags & SystemZII::IsLogical)
308 ReusableCCMask &= SystemZ::CCMASK_CMP_EQ;
310 if (ReusableCCMask == 0)
313 unsigned CCValues = SystemZII::getCCValues(MIFlags);
314 assert((ReusableCCMask & ~CCValues) == 0 && "Invalid CCValues");
316 // Now check whether these flags are enough for all users.
317 SmallVector<MachineOperand *, 4> AlterMasks;
318 for (unsigned int I = 0, E = CCUsers.size(); I != E; ++I) {
319 MachineInstr *MI = CCUsers[I];
321 // Fail if this isn't a use of CC that we understand.
322 unsigned Flags = MI->getDesc().TSFlags;
324 if (Flags & SystemZII::CCMaskFirst)
326 else if (Flags & SystemZII::CCMaskLast)
327 FirstOpNum = MI->getNumExplicitOperands() - 2;
331 // Check whether the instruction predicate treats all CC values
332 // outside of ReusableCCMask in the same way. In that case it
333 // doesn't matter what those CC values mean.
334 unsigned CCValid = MI->getOperand(FirstOpNum).getImm();
335 unsigned CCMask = MI->getOperand(FirstOpNum + 1).getImm();
336 unsigned OutValid = ~ReusableCCMask & CCValid;
337 unsigned OutMask = ~ReusableCCMask & CCMask;
338 if (OutMask != 0 && OutMask != OutValid)
341 AlterMasks.push_back(&MI->getOperand(FirstOpNum));
342 AlterMasks.push_back(&MI->getOperand(FirstOpNum + 1));
345 // All users are OK. Adjust the masks for MI.
346 for (unsigned I = 0, E = AlterMasks.size(); I != E; I += 2) {
347 AlterMasks[I]->setImm(CCValues);
348 unsigned CCMask = AlterMasks[I + 1]->getImm();
349 if (CCMask & ~ReusableCCMask)
350 AlterMasks[I + 1]->setImm((CCMask & ReusableCCMask) |
351 (CCValues & ~ReusableCCMask));
354 // CC is now live after MI.
355 int CCDef = MI.findRegisterDefOperandIdx(SystemZ::CC, false, true, TRI);
356 assert(CCDef >= 0 && "Couldn't find CC set");
357 MI.getOperand(CCDef).setIsDead(false);
359 // Clear any intervening kills of CC.
360 MachineBasicBlock::iterator MBBI = MI, MBBE = Compare;
361 for (++MBBI; MBBI != MBBE; ++MBBI)
362 MBBI->clearRegisterKills(SystemZ::CC, TRI);
367 // Return true if Compare is a comparison against zero.
368 static bool isCompareZero(MachineInstr &Compare) {
369 switch (Compare.getOpcode()) {
370 case SystemZ::LTEBRCompare:
371 case SystemZ::LTDBRCompare:
372 case SystemZ::LTXBRCompare:
376 if (isLoadAndTestAsCmp(Compare))
378 return Compare.getNumExplicitOperands() == 2 &&
379 Compare.getOperand(1).isImm() && Compare.getOperand(1).getImm() == 0;
383 // Try to optimize cases where comparison instruction Compare is testing
384 // a value against zero. Return true on success and if Compare should be
385 // deleted as dead. CCUsers is the list of instructions that use the CC
386 // value produced by Compare.
387 bool SystemZElimCompare::optimizeCompareZero(
388 MachineInstr &Compare, SmallVectorImpl<MachineInstr *> &CCUsers) {
389 if (!isCompareZero(Compare))
392 // Search back for CC results that are based on the first operand.
393 unsigned SrcReg = getCompareSourceReg(Compare);
394 MachineBasicBlock &MBB = *Compare.getParent();
395 MachineBasicBlock::iterator MBBI = Compare, MBBE = MBB.begin();
398 while (MBBI != MBBE) {
400 MachineInstr &MI = *MBBI;
401 if (resultTests(MI, SrcReg)) {
402 // Try to remove both MI and Compare by converting a branch to BRCT(G).
403 // or a load-and-trap instruction. We don't care in this case whether
404 // CC is modified between MI and Compare.
405 if (!CCRefs.Use && !SrcRefs) {
406 if (convertToBRCT(MI, Compare, CCUsers)) {
410 if (convertToLoadAndTrap(MI, Compare, CCUsers)) {
415 // Try to eliminate Compare by reusing a CC result from MI.
416 if ((!CCRefs && convertToLoadAndTest(MI)) ||
417 (!CCRefs.Def && adjustCCMasksForInstr(MI, Compare, CCUsers))) {
418 EliminatedComparisons += 1;
422 SrcRefs |= getRegReferences(MI, SrcReg);
425 CCRefs |= getRegReferences(MI, SystemZ::CC);
426 if (CCRefs.Use && CCRefs.Def)
432 // Try to fuse comparison instruction Compare into a later branch.
433 // Return true on success and if Compare is therefore redundant.
434 bool SystemZElimCompare::fuseCompareOperations(
435 MachineInstr &Compare, SmallVectorImpl<MachineInstr *> &CCUsers) {
436 // See whether we have a single branch with which to fuse.
437 if (CCUsers.size() != 1)
439 MachineInstr *Branch = CCUsers[0];
440 SystemZII::FusedCompareType Type;
441 switch (Branch->getOpcode()) {
443 Type = SystemZII::CompareAndBranch;
445 case SystemZ::CondReturn:
446 Type = SystemZII::CompareAndReturn;
448 case SystemZ::CallBCR:
449 Type = SystemZII::CompareAndSibcall;
451 case SystemZ::CondTrap:
452 Type = SystemZII::CompareAndTrap;
458 // See whether we have a comparison that can be fused.
459 unsigned FusedOpcode =
460 TII->getFusedCompare(Compare.getOpcode(), Type, &Compare);
464 // Make sure that the operands are available at the branch.
465 // SrcReg2 is the register if the source operand is a register,
466 // 0 if the source operand is immediate, and the base register
467 // if the source operand is memory (index is not supported).
468 unsigned SrcReg = Compare.getOperand(0).getReg();
470 Compare.getOperand(1).isReg() ? Compare.getOperand(1).getReg() : 0;
471 MachineBasicBlock::iterator MBBI = Compare, MBBE = Branch;
472 for (++MBBI; MBBI != MBBE; ++MBBI)
473 if (MBBI->modifiesRegister(SrcReg, TRI) ||
474 (SrcReg2 && MBBI->modifiesRegister(SrcReg2, TRI)))
477 // Read the branch mask, target (if applicable), regmask (if applicable).
478 MachineOperand CCMask(MBBI->getOperand(1));
479 assert((CCMask.getImm() & ~SystemZ::CCMASK_ICMP) == 0 &&
480 "Invalid condition-code mask for integer comparison");
481 // This is only valid for CompareAndBranch.
482 MachineOperand Target(MBBI->getOperand(
483 Type == SystemZII::CompareAndBranch ? 2 : 0));
484 const uint32_t *RegMask;
485 if (Type == SystemZII::CompareAndSibcall)
486 RegMask = MBBI->getOperand(2).getRegMask();
488 // Clear out all current operands.
489 int CCUse = MBBI->findRegisterUseOperandIdx(SystemZ::CC, false, TRI);
490 assert(CCUse >= 0 && "BRC/BCR must use CC");
491 Branch->RemoveOperand(CCUse);
492 // Remove target (branch) or regmask (sibcall).
493 if (Type == SystemZII::CompareAndBranch ||
494 Type == SystemZII::CompareAndSibcall)
495 Branch->RemoveOperand(2);
496 Branch->RemoveOperand(1);
497 Branch->RemoveOperand(0);
499 // Rebuild Branch as a fused compare and branch.
500 // SrcNOps is the number of MI operands of the compare instruction
501 // that we need to copy over.
502 unsigned SrcNOps = 2;
503 if (FusedOpcode == SystemZ::CLT || FusedOpcode == SystemZ::CLGT)
505 Branch->setDesc(TII->get(FusedOpcode));
506 MachineInstrBuilder MIB(*Branch->getParent()->getParent(), Branch);
507 for (unsigned I = 0; I < SrcNOps; I++)
508 MIB.add(Compare.getOperand(I));
511 if (Type == SystemZII::CompareAndBranch) {
512 // Only conditional branches define CC, as they may be converted back
513 // to a non-fused branch because of a long displacement. Conditional
514 // returns don't have that problem.
515 MIB.add(Target).addReg(SystemZ::CC,
516 RegState::ImplicitDefine | RegState::Dead);
519 if (Type == SystemZII::CompareAndSibcall)
520 MIB.addRegMask(RegMask);
522 // Clear any intervening kills of SrcReg and SrcReg2.
524 for (++MBBI; MBBI != MBBE; ++MBBI) {
525 MBBI->clearRegisterKills(SrcReg, TRI);
527 MBBI->clearRegisterKills(SrcReg2, TRI);
529 FusedComparisons += 1;
533 // Process all comparison instructions in MBB. Return true if something
535 bool SystemZElimCompare::processBlock(MachineBasicBlock &MBB) {
536 bool Changed = false;
538 // Walk backwards through the block looking for comparisons, recording
539 // all CC users as we go. The subroutines can delete Compare and
540 // instructions before it.
541 bool CompleteCCUsers = !isCCLiveOut(MBB);
542 SmallVector<MachineInstr *, 4> CCUsers;
543 MachineBasicBlock::iterator MBBI = MBB.end();
544 while (MBBI != MBB.begin()) {
545 MachineInstr &MI = *--MBBI;
546 if (CompleteCCUsers && (MI.isCompare() || isLoadAndTestAsCmp(MI)) &&
547 (optimizeCompareZero(MI, CCUsers) ||
548 fuseCompareOperations(MI, CCUsers))) {
550 MI.eraseFromParent();
556 if (MI.definesRegister(SystemZ::CC)) {
558 CompleteCCUsers = true;
560 if (MI.readsRegister(SystemZ::CC) && CompleteCCUsers)
561 CCUsers.push_back(&MI);
566 bool SystemZElimCompare::runOnMachineFunction(MachineFunction &F) {
567 if (skipFunction(*F.getFunction()))
570 TII = static_cast<const SystemZInstrInfo *>(F.getSubtarget().getInstrInfo());
571 TRI = &TII->getRegisterInfo();
573 bool Changed = false;
575 Changed |= processBlock(MBB);
580 FunctionPass *llvm::createSystemZElimComparePass(SystemZTargetMachine &TM) {
581 return new SystemZElimCompare(TM);