1 //===-- SystemZFrameLowering.cpp - Frame lowering for SystemZ -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "SystemZFrameLowering.h"
11 #include "SystemZCallingConv.h"
12 #include "SystemZInstrBuilder.h"
13 #include "SystemZInstrInfo.h"
14 #include "SystemZMachineFunctionInfo.h"
15 #include "SystemZRegisterInfo.h"
16 #include "SystemZSubtarget.h"
17 #include "llvm/CodeGen/MachineModuleInfo.h"
18 #include "llvm/CodeGen/MachineRegisterInfo.h"
19 #include "llvm/CodeGen/RegisterScavenging.h"
20 #include "llvm/IR/Function.h"
25 // The ABI-defined register save slots, relative to the incoming stack
27 static const TargetFrameLowering::SpillSlot SpillOffsetTable[] = {
28 { SystemZ::R2D, 0x10 },
29 { SystemZ::R3D, 0x18 },
30 { SystemZ::R4D, 0x20 },
31 { SystemZ::R5D, 0x28 },
32 { SystemZ::R6D, 0x30 },
33 { SystemZ::R7D, 0x38 },
34 { SystemZ::R8D, 0x40 },
35 { SystemZ::R9D, 0x48 },
36 { SystemZ::R10D, 0x50 },
37 { SystemZ::R11D, 0x58 },
38 { SystemZ::R12D, 0x60 },
39 { SystemZ::R13D, 0x68 },
40 { SystemZ::R14D, 0x70 },
41 { SystemZ::R15D, 0x78 },
42 { SystemZ::F0D, 0x80 },
43 { SystemZ::F2D, 0x88 },
44 { SystemZ::F4D, 0x90 },
45 { SystemZ::F6D, 0x98 }
47 } // end anonymous namespace
49 SystemZFrameLowering::SystemZFrameLowering()
50 : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 8,
51 -SystemZMC::CallFrameSize, 8,
52 false /* StackRealignable */) {
53 // Create a mapping from register number to save slot offset.
54 RegSpillOffsets.grow(SystemZ::NUM_TARGET_REGS);
55 for (unsigned I = 0, E = array_lengthof(SpillOffsetTable); I != E; ++I)
56 RegSpillOffsets[SpillOffsetTable[I].Reg] = SpillOffsetTable[I].Offset;
59 const TargetFrameLowering::SpillSlot *
60 SystemZFrameLowering::getCalleeSavedSpillSlots(unsigned &NumEntries) const {
61 NumEntries = array_lengthof(SpillOffsetTable);
62 return SpillOffsetTable;
65 void SystemZFrameLowering::determineCalleeSaves(MachineFunction &MF,
67 RegScavenger *RS) const {
68 TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
70 MachineFrameInfo &MFFrame = MF.getFrameInfo();
71 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
72 bool HasFP = hasFP(MF);
73 SystemZMachineFunctionInfo *MFI = MF.getInfo<SystemZMachineFunctionInfo>();
74 bool IsVarArg = MF.getFunction().isVarArg();
76 // va_start stores incoming FPR varargs in the normal way, but delegates
77 // the saving of incoming GPR varargs to spillCalleeSavedRegisters().
78 // Record these pending uses, which typically include the call-saved
79 // argument register R6D.
81 for (unsigned I = MFI->getVarArgsFirstGPR(); I < SystemZ::NumArgGPRs; ++I)
82 SavedRegs.set(SystemZ::ArgGPRs[I]);
84 // If there are any landing pads, entering them will modify r6/r7.
85 if (!MF.getLandingPads().empty()) {
86 SavedRegs.set(SystemZ::R6D);
87 SavedRegs.set(SystemZ::R7D);
90 // If the function requires a frame pointer, record that the hard
91 // frame pointer will be clobbered.
93 SavedRegs.set(SystemZ::R11D);
95 // If the function calls other functions, record that the return
96 // address register will be clobbered.
97 if (MFFrame.hasCalls())
98 SavedRegs.set(SystemZ::R14D);
100 // If we are saving GPRs other than the stack pointer, we might as well
101 // save and restore the stack pointer at the same time, via STMG and LMG.
102 // This allows the deallocation to be done by the LMG, rather than needing
103 // a separate %r15 addition.
104 const MCPhysReg *CSRegs = TRI->getCalleeSavedRegs(&MF);
105 for (unsigned I = 0; CSRegs[I]; ++I) {
106 unsigned Reg = CSRegs[I];
107 if (SystemZ::GR64BitRegClass.contains(Reg) && SavedRegs.test(Reg)) {
108 SavedRegs.set(SystemZ::R15D);
114 // Add GPR64 to the save instruction being built by MIB, which is in basic
115 // block MBB. IsImplicit says whether this is an explicit operand to the
116 // instruction, or an implicit one that comes between the explicit start
117 // and end registers.
118 static void addSavedGPR(MachineBasicBlock &MBB, MachineInstrBuilder &MIB,
119 unsigned GPR64, bool IsImplicit) {
120 const TargetRegisterInfo *RI =
121 MBB.getParent()->getSubtarget().getRegisterInfo();
122 unsigned GPR32 = RI->getSubReg(GPR64, SystemZ::subreg_l32);
123 bool IsLive = MBB.isLiveIn(GPR64) || MBB.isLiveIn(GPR32);
124 if (!IsLive || !IsImplicit) {
125 MIB.addReg(GPR64, getImplRegState(IsImplicit) | getKillRegState(!IsLive));
127 MBB.addLiveIn(GPR64);
131 bool SystemZFrameLowering::
132 spillCalleeSavedRegisters(MachineBasicBlock &MBB,
133 MachineBasicBlock::iterator MBBI,
134 const std::vector<CalleeSavedInfo> &CSI,
135 const TargetRegisterInfo *TRI) const {
139 MachineFunction &MF = *MBB.getParent();
140 const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
141 SystemZMachineFunctionInfo *ZFI = MF.getInfo<SystemZMachineFunctionInfo>();
142 bool IsVarArg = MF.getFunction().isVarArg();
145 // Scan the call-saved GPRs and find the bounds of the register spill area.
147 unsigned HighGPR = SystemZ::R15D;
148 unsigned StartOffset = -1U;
149 for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
150 unsigned Reg = CSI[I].getReg();
151 if (SystemZ::GR64BitRegClass.contains(Reg)) {
152 unsigned Offset = RegSpillOffsets[Reg];
153 assert(Offset && "Unexpected GPR save");
154 if (StartOffset > Offset) {
156 StartOffset = Offset;
161 // Save the range of call-saved registers, for use by the epilogue inserter.
162 ZFI->setLowSavedGPR(LowGPR);
163 ZFI->setHighSavedGPR(HighGPR);
165 // Include the GPR varargs, if any. R6D is call-saved, so would
166 // be included by the loop above, but we also need to handle the
167 // call-clobbered argument registers.
169 unsigned FirstGPR = ZFI->getVarArgsFirstGPR();
170 if (FirstGPR < SystemZ::NumArgGPRs) {
171 unsigned Reg = SystemZ::ArgGPRs[FirstGPR];
172 unsigned Offset = RegSpillOffsets[Reg];
173 if (StartOffset > Offset) {
174 LowGPR = Reg; StartOffset = Offset;
181 assert(LowGPR != HighGPR && "Should be saving %r15 and something else");
183 // Build an STMG instruction.
184 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(SystemZ::STMG));
186 // Add the explicit register operands.
187 addSavedGPR(MBB, MIB, LowGPR, false);
188 addSavedGPR(MBB, MIB, HighGPR, false);
191 MIB.addReg(SystemZ::R15D).addImm(StartOffset);
193 // Make sure all call-saved GPRs are included as operands and are
194 // marked as live on entry.
195 for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
196 unsigned Reg = CSI[I].getReg();
197 if (SystemZ::GR64BitRegClass.contains(Reg))
198 addSavedGPR(MBB, MIB, Reg, true);
201 // ...likewise GPR varargs.
203 for (unsigned I = ZFI->getVarArgsFirstGPR(); I < SystemZ::NumArgGPRs; ++I)
204 addSavedGPR(MBB, MIB, SystemZ::ArgGPRs[I], true);
207 // Save FPRs/VRs in the normal TargetInstrInfo way.
208 for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
209 unsigned Reg = CSI[I].getReg();
210 if (SystemZ::FP64BitRegClass.contains(Reg)) {
212 TII->storeRegToStackSlot(MBB, MBBI, Reg, true, CSI[I].getFrameIdx(),
213 &SystemZ::FP64BitRegClass, TRI);
215 if (SystemZ::VR128BitRegClass.contains(Reg)) {
217 TII->storeRegToStackSlot(MBB, MBBI, Reg, true, CSI[I].getFrameIdx(),
218 &SystemZ::VR128BitRegClass, TRI);
225 bool SystemZFrameLowering::
226 restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
227 MachineBasicBlock::iterator MBBI,
228 std::vector<CalleeSavedInfo> &CSI,
229 const TargetRegisterInfo *TRI) const {
233 MachineFunction &MF = *MBB.getParent();
234 const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
235 SystemZMachineFunctionInfo *ZFI = MF.getInfo<SystemZMachineFunctionInfo>();
236 bool HasFP = hasFP(MF);
237 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
239 // Restore FPRs/VRs in the normal TargetInstrInfo way.
240 for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
241 unsigned Reg = CSI[I].getReg();
242 if (SystemZ::FP64BitRegClass.contains(Reg))
243 TII->loadRegFromStackSlot(MBB, MBBI, Reg, CSI[I].getFrameIdx(),
244 &SystemZ::FP64BitRegClass, TRI);
245 if (SystemZ::VR128BitRegClass.contains(Reg))
246 TII->loadRegFromStackSlot(MBB, MBBI, Reg, CSI[I].getFrameIdx(),
247 &SystemZ::VR128BitRegClass, TRI);
250 // Restore call-saved GPRs (but not call-clobbered varargs, which at
251 // this point might hold return values).
252 unsigned LowGPR = ZFI->getLowSavedGPR();
253 unsigned HighGPR = ZFI->getHighSavedGPR();
254 unsigned StartOffset = RegSpillOffsets[LowGPR];
256 // If we saved any of %r2-%r5 as varargs, we should also be saving
257 // and restoring %r6. If we're saving %r6 or above, we should be
259 assert(LowGPR != HighGPR && "Should be loading %r15 and something else");
261 // Build an LMG instruction.
262 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(SystemZ::LMG));
264 // Add the explicit register operands.
265 MIB.addReg(LowGPR, RegState::Define);
266 MIB.addReg(HighGPR, RegState::Define);
269 MIB.addReg(HasFP ? SystemZ::R11D : SystemZ::R15D);
270 MIB.addImm(StartOffset);
272 // Do a second scan adding regs as being defined by instruction
273 for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
274 unsigned Reg = CSI[I].getReg();
275 if (Reg != LowGPR && Reg != HighGPR &&
276 SystemZ::GR64BitRegClass.contains(Reg))
277 MIB.addReg(Reg, RegState::ImplicitDefine);
284 void SystemZFrameLowering::
285 processFunctionBeforeFrameFinalized(MachineFunction &MF,
286 RegScavenger *RS) const {
287 MachineFrameInfo &MFFrame = MF.getFrameInfo();
288 // Get the size of our stack frame to be allocated ...
289 uint64_t StackSize = (MFFrame.estimateStackSize(MF) +
290 SystemZMC::CallFrameSize);
291 // ... and the maximum offset we may need to reach into the
292 // caller's frame to access the save area or stack arguments.
293 int64_t MaxArgOffset = SystemZMC::CallFrameSize;
294 for (int I = MFFrame.getObjectIndexBegin(); I != 0; ++I)
295 if (MFFrame.getObjectOffset(I) >= 0) {
296 int64_t ArgOffset = SystemZMC::CallFrameSize +
297 MFFrame.getObjectOffset(I) +
298 MFFrame.getObjectSize(I);
299 MaxArgOffset = std::max(MaxArgOffset, ArgOffset);
302 uint64_t MaxReach = StackSize + MaxArgOffset;
303 if (!isUInt<12>(MaxReach)) {
304 // We may need register scavenging slots if some parts of the frame
305 // are outside the reach of an unsigned 12-bit displacement.
306 // Create 2 for the case where both addresses in an MVC are
308 RS->addScavengingFrameIndex(MFFrame.CreateStackObject(8, 8, false));
309 RS->addScavengingFrameIndex(MFFrame.CreateStackObject(8, 8, false));
313 // Emit instructions before MBBI (in MBB) to add NumBytes to Reg.
314 static void emitIncrement(MachineBasicBlock &MBB,
315 MachineBasicBlock::iterator &MBBI,
317 unsigned Reg, int64_t NumBytes,
318 const TargetInstrInfo *TII) {
321 int64_t ThisVal = NumBytes;
322 if (isInt<16>(NumBytes))
323 Opcode = SystemZ::AGHI;
325 Opcode = SystemZ::AGFI;
326 // Make sure we maintain 8-byte stack alignment.
327 int64_t MinVal = -uint64_t(1) << 31;
328 int64_t MaxVal = (int64_t(1) << 31) - 8;
329 if (ThisVal < MinVal)
331 else if (ThisVal > MaxVal)
334 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII->get(Opcode), Reg)
335 .addReg(Reg).addImm(ThisVal);
336 // The CC implicit def is dead.
337 MI->getOperand(3).setIsDead();
342 void SystemZFrameLowering::emitPrologue(MachineFunction &MF,
343 MachineBasicBlock &MBB) const {
344 assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported");
345 MachineFrameInfo &MFFrame = MF.getFrameInfo();
347 static_cast<const SystemZInstrInfo *>(MF.getSubtarget().getInstrInfo());
348 SystemZMachineFunctionInfo *ZFI = MF.getInfo<SystemZMachineFunctionInfo>();
349 MachineBasicBlock::iterator MBBI = MBB.begin();
350 MachineModuleInfo &MMI = MF.getMMI();
351 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
352 const std::vector<CalleeSavedInfo> &CSI = MFFrame.getCalleeSavedInfo();
353 bool HasFP = hasFP(MF);
355 // Debug location must be unknown since the first debug location is used
356 // to determine the end of the prologue.
359 // The current offset of the stack pointer from the CFA.
360 int64_t SPOffsetFromCFA = -SystemZMC::CFAOffsetFromInitialSP;
362 if (ZFI->getLowSavedGPR()) {
363 // Skip over the GPR saves.
364 if (MBBI != MBB.end() && MBBI->getOpcode() == SystemZ::STMG)
367 llvm_unreachable("Couldn't skip over GPR saves");
369 // Add CFI for the GPR saves.
370 for (auto &Save : CSI) {
371 unsigned Reg = Save.getReg();
372 if (SystemZ::GR64BitRegClass.contains(Reg)) {
373 int64_t Offset = SPOffsetFromCFA + RegSpillOffsets[Reg];
374 unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
375 nullptr, MRI->getDwarfRegNum(Reg, true), Offset));
376 BuildMI(MBB, MBBI, DL, ZII->get(TargetOpcode::CFI_INSTRUCTION))
377 .addCFIIndex(CFIIndex);
382 uint64_t StackSize = MFFrame.getStackSize();
383 // We need to allocate the ABI-defined 160-byte base area whenever
384 // we allocate stack space for our own use and whenever we call another
386 if (StackSize || MFFrame.hasVarSizedObjects() || MFFrame.hasCalls()) {
387 StackSize += SystemZMC::CallFrameSize;
388 MFFrame.setStackSize(StackSize);
392 // Determine if we want to store a backchain.
393 bool StoreBackchain = MF.getFunction().hasFnAttribute("backchain");
395 // If we need backchain, save current stack pointer. R1 is free at this
398 BuildMI(MBB, MBBI, DL, ZII->get(SystemZ::LGR))
399 .addReg(SystemZ::R1D, RegState::Define).addReg(SystemZ::R15D);
401 // Allocate StackSize bytes.
402 int64_t Delta = -int64_t(StackSize);
403 emitIncrement(MBB, MBBI, DL, SystemZ::R15D, Delta, ZII);
405 // Add CFI for the allocation.
406 unsigned CFIIndex = MF.addFrameInst(
407 MCCFIInstruction::createDefCfaOffset(nullptr, SPOffsetFromCFA + Delta));
408 BuildMI(MBB, MBBI, DL, ZII->get(TargetOpcode::CFI_INSTRUCTION))
409 .addCFIIndex(CFIIndex);
410 SPOffsetFromCFA += Delta;
413 BuildMI(MBB, MBBI, DL, ZII->get(SystemZ::STG))
414 .addReg(SystemZ::R1D, RegState::Kill).addReg(SystemZ::R15D).addImm(0).addReg(0);
418 // Copy the base of the frame to R11.
419 BuildMI(MBB, MBBI, DL, ZII->get(SystemZ::LGR), SystemZ::R11D)
420 .addReg(SystemZ::R15D);
422 // Add CFI for the new frame location.
423 unsigned HardFP = MRI->getDwarfRegNum(SystemZ::R11D, true);
424 unsigned CFIIndex = MF.addFrameInst(
425 MCCFIInstruction::createDefCfaRegister(nullptr, HardFP));
426 BuildMI(MBB, MBBI, DL, ZII->get(TargetOpcode::CFI_INSTRUCTION))
427 .addCFIIndex(CFIIndex);
429 // Mark the FramePtr as live at the beginning of every block except
430 // the entry block. (We'll have marked R11 as live on entry when
432 for (auto I = std::next(MF.begin()), E = MF.end(); I != E; ++I)
433 I->addLiveIn(SystemZ::R11D);
436 // Skip over the FPR/VR saves.
437 SmallVector<unsigned, 8> CFIIndexes;
438 for (auto &Save : CSI) {
439 unsigned Reg = Save.getReg();
440 if (SystemZ::FP64BitRegClass.contains(Reg)) {
441 if (MBBI != MBB.end() &&
442 (MBBI->getOpcode() == SystemZ::STD ||
443 MBBI->getOpcode() == SystemZ::STDY))
446 llvm_unreachable("Couldn't skip over FPR save");
447 } else if (SystemZ::VR128BitRegClass.contains(Reg)) {
448 if (MBBI != MBB.end() &&
449 MBBI->getOpcode() == SystemZ::VST)
452 llvm_unreachable("Couldn't skip over VR save");
456 // Add CFI for the this save.
457 unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
458 unsigned IgnoredFrameReg;
460 getFrameIndexReference(MF, Save.getFrameIdx(), IgnoredFrameReg);
462 unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
463 nullptr, DwarfReg, SPOffsetFromCFA + Offset));
464 CFIIndexes.push_back(CFIIndex);
466 // Complete the CFI for the FPR/VR saves, modelling them as taking effect
467 // after the last save.
468 for (auto CFIIndex : CFIIndexes) {
469 BuildMI(MBB, MBBI, DL, ZII->get(TargetOpcode::CFI_INSTRUCTION))
470 .addCFIIndex(CFIIndex);
474 void SystemZFrameLowering::emitEpilogue(MachineFunction &MF,
475 MachineBasicBlock &MBB) const {
476 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
478 static_cast<const SystemZInstrInfo *>(MF.getSubtarget().getInstrInfo());
479 SystemZMachineFunctionInfo *ZFI = MF.getInfo<SystemZMachineFunctionInfo>();
480 MachineFrameInfo &MFFrame = MF.getFrameInfo();
482 // Skip the return instruction.
483 assert(MBBI->isReturn() && "Can only insert epilogue into returning blocks");
485 uint64_t StackSize = MFFrame.getStackSize();
486 if (ZFI->getLowSavedGPR()) {
488 unsigned Opcode = MBBI->getOpcode();
489 if (Opcode != SystemZ::LMG)
490 llvm_unreachable("Expected to see callee-save register restore code");
492 unsigned AddrOpNo = 2;
493 DebugLoc DL = MBBI->getDebugLoc();
494 uint64_t Offset = StackSize + MBBI->getOperand(AddrOpNo + 1).getImm();
495 unsigned NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset);
497 // If the offset is too large, use the largest stack-aligned offset
498 // and add the rest to the base register (the stack or frame pointer).
500 uint64_t NumBytes = Offset - 0x7fff8;
501 emitIncrement(MBB, MBBI, DL, MBBI->getOperand(AddrOpNo).getReg(),
504 NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset);
505 assert(NewOpcode && "No restore instruction available");
508 MBBI->setDesc(ZII->get(NewOpcode));
509 MBBI->getOperand(AddrOpNo + 1).ChangeToImmediate(Offset);
510 } else if (StackSize) {
511 DebugLoc DL = MBBI->getDebugLoc();
512 emitIncrement(MBB, MBBI, DL, SystemZ::R15D, StackSize, ZII);
516 bool SystemZFrameLowering::hasFP(const MachineFunction &MF) const {
517 return (MF.getTarget().Options.DisableFramePointerElim(MF) ||
518 MF.getFrameInfo().hasVarSizedObjects() ||
519 MF.getInfo<SystemZMachineFunctionInfo>()->getManipulatesSP());
523 SystemZFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
524 // The ABI requires us to allocate 160 bytes of stack space for the callee,
525 // with any outgoing stack arguments being placed above that. It seems
526 // better to make that area a permanent feature of the frame even if
527 // we're using a frame pointer.
531 MachineBasicBlock::iterator SystemZFrameLowering::
532 eliminateCallFramePseudoInstr(MachineFunction &MF,
533 MachineBasicBlock &MBB,
534 MachineBasicBlock::iterator MI) const {
535 switch (MI->getOpcode()) {
536 case SystemZ::ADJCALLSTACKDOWN:
537 case SystemZ::ADJCALLSTACKUP:
538 assert(hasReservedCallFrame(MF) &&
539 "ADJSTACKDOWN and ADJSTACKUP should be no-ops");
540 return MBB.erase(MI);
544 llvm_unreachable("Unexpected call frame instruction");