1 //===-- SystemZISelDAGToDAG.cpp - A dag to dag inst selector for SystemZ --===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the SystemZ target.
12 //===----------------------------------------------------------------------===//
14 #include "SystemZTargetMachine.h"
15 #include "llvm/Analysis/AliasAnalysis.h"
16 #include "llvm/CodeGen/SelectionDAGISel.h"
17 #include "llvm/Support/Debug.h"
18 #include "llvm/Support/raw_ostream.h"
22 #define DEBUG_TYPE "systemz-isel"
25 // Used to build addressing modes.
26 struct SystemZAddressingMode {
27 // The shape of the address.
32 // base+displacement+index for load and store operands
35 // base+displacement+index for load address operands
38 // base+displacement+index+ADJDYNALLOC
43 // The type of displacement. The enum names here correspond directly
44 // to the definitions in SystemZOperand.td. We could split them into
45 // flags -- single/pair, 128-bit, etc. -- but it hardly seems worth it.
55 // The parts of the address. The address is equivalent to:
57 // Base + Disp + Index + (IncludesDynAlloc ? ADJDYNALLOC : 0)
61 bool IncludesDynAlloc;
63 SystemZAddressingMode(AddrForm form, DispRange dr)
64 : Form(form), DR(dr), Base(), Disp(0), Index(),
65 IncludesDynAlloc(false) {}
67 // True if the address can have an index register.
68 bool hasIndexField() { return Form != FormBD; }
70 // True if the address can (and must) include ADJDYNALLOC.
71 bool isDynAlloc() { return Form == FormBDXDynAlloc; }
74 errs() << "SystemZAddressingMode " << this << '\n';
78 Base.getNode()->dump();
82 if (hasIndexField()) {
85 Index.getNode()->dump();
90 errs() << " Disp " << Disp;
92 errs() << " + ADJDYNALLOC";
97 // Return a mask with Count low bits set.
98 static uint64_t allOnes(unsigned int Count) {
102 return (uint64_t(1) << Count) - 1;
105 // Represents operands 2 to 5 of the ROTATE AND ... SELECTED BITS operation
106 // given by Opcode. The operands are: Input (R2), Start (I3), End (I4) and
107 // Rotate (I5). The combined operand value is effectively:
109 // (or (rotl Input, Rotate), ~Mask)
113 // (and (rotl Input, Rotate), Mask)
115 // otherwise. The output value has BitSize bits, although Input may be
116 // narrower (in which case the upper bits are don't care), or wider (in which
117 // case the result will be truncated as part of the operation).
118 struct RxSBGOperands {
119 RxSBGOperands(unsigned Op, SDValue N)
120 : Opcode(Op), BitSize(N.getValueType().getSizeInBits()),
121 Mask(allOnes(BitSize)), Input(N), Start(64 - BitSize), End(63),
133 class SystemZDAGToDAGISel : public SelectionDAGISel {
134 const SystemZSubtarget *Subtarget;
136 // Used by SystemZOperands.td to create integer constants.
137 inline SDValue getImm(const SDNode *Node, uint64_t Imm) const {
138 return CurDAG->getTargetConstant(Imm, SDLoc(Node), Node->getValueType(0));
141 const SystemZTargetMachine &getTargetMachine() const {
142 return static_cast<const SystemZTargetMachine &>(TM);
145 const SystemZInstrInfo *getInstrInfo() const {
146 return Subtarget->getInstrInfo();
149 // Try to fold more of the base or index of AM into AM, where IsBase
150 // selects between the base and index.
151 bool expandAddress(SystemZAddressingMode &AM, bool IsBase) const;
153 // Try to describe N in AM, returning true on success.
154 bool selectAddress(SDValue N, SystemZAddressingMode &AM) const;
156 // Extract individual target operands from matched address AM.
157 void getAddressOperands(const SystemZAddressingMode &AM, EVT VT,
158 SDValue &Base, SDValue &Disp) const;
159 void getAddressOperands(const SystemZAddressingMode &AM, EVT VT,
160 SDValue &Base, SDValue &Disp, SDValue &Index) const;
162 // Try to match Addr as a FormBD address with displacement type DR.
163 // Return true on success, storing the base and displacement in
164 // Base and Disp respectively.
165 bool selectBDAddr(SystemZAddressingMode::DispRange DR, SDValue Addr,
166 SDValue &Base, SDValue &Disp) const;
168 // Try to match Addr as a FormBDX address with displacement type DR.
169 // Return true on success and if the result had no index. Store the
170 // base and displacement in Base and Disp respectively.
171 bool selectMVIAddr(SystemZAddressingMode::DispRange DR, SDValue Addr,
172 SDValue &Base, SDValue &Disp) const;
174 // Try to match Addr as a FormBDX* address of form Form with
175 // displacement type DR. Return true on success, storing the base,
176 // displacement and index in Base, Disp and Index respectively.
177 bool selectBDXAddr(SystemZAddressingMode::AddrForm Form,
178 SystemZAddressingMode::DispRange DR, SDValue Addr,
179 SDValue &Base, SDValue &Disp, SDValue &Index) const;
181 // PC-relative address matching routines used by SystemZOperands.td.
182 bool selectPCRelAddress(SDValue Addr, SDValue &Target) const {
183 if (SystemZISD::isPCREL(Addr.getOpcode())) {
184 Target = Addr.getOperand(0);
190 // BD matching routines used by SystemZOperands.td.
191 bool selectBDAddr12Only(SDValue Addr, SDValue &Base, SDValue &Disp) const {
192 return selectBDAddr(SystemZAddressingMode::Disp12Only, Addr, Base, Disp);
194 bool selectBDAddr12Pair(SDValue Addr, SDValue &Base, SDValue &Disp) const {
195 return selectBDAddr(SystemZAddressingMode::Disp12Pair, Addr, Base, Disp);
197 bool selectBDAddr20Only(SDValue Addr, SDValue &Base, SDValue &Disp) const {
198 return selectBDAddr(SystemZAddressingMode::Disp20Only, Addr, Base, Disp);
200 bool selectBDAddr20Pair(SDValue Addr, SDValue &Base, SDValue &Disp) const {
201 return selectBDAddr(SystemZAddressingMode::Disp20Pair, Addr, Base, Disp);
204 // MVI matching routines used by SystemZOperands.td.
205 bool selectMVIAddr12Pair(SDValue Addr, SDValue &Base, SDValue &Disp) const {
206 return selectMVIAddr(SystemZAddressingMode::Disp12Pair, Addr, Base, Disp);
208 bool selectMVIAddr20Pair(SDValue Addr, SDValue &Base, SDValue &Disp) const {
209 return selectMVIAddr(SystemZAddressingMode::Disp20Pair, Addr, Base, Disp);
212 // BDX matching routines used by SystemZOperands.td.
213 bool selectBDXAddr12Only(SDValue Addr, SDValue &Base, SDValue &Disp,
214 SDValue &Index) const {
215 return selectBDXAddr(SystemZAddressingMode::FormBDXNormal,
216 SystemZAddressingMode::Disp12Only,
217 Addr, Base, Disp, Index);
219 bool selectBDXAddr12Pair(SDValue Addr, SDValue &Base, SDValue &Disp,
220 SDValue &Index) const {
221 return selectBDXAddr(SystemZAddressingMode::FormBDXNormal,
222 SystemZAddressingMode::Disp12Pair,
223 Addr, Base, Disp, Index);
225 bool selectDynAlloc12Only(SDValue Addr, SDValue &Base, SDValue &Disp,
226 SDValue &Index) const {
227 return selectBDXAddr(SystemZAddressingMode::FormBDXDynAlloc,
228 SystemZAddressingMode::Disp12Only,
229 Addr, Base, Disp, Index);
231 bool selectBDXAddr20Only(SDValue Addr, SDValue &Base, SDValue &Disp,
232 SDValue &Index) const {
233 return selectBDXAddr(SystemZAddressingMode::FormBDXNormal,
234 SystemZAddressingMode::Disp20Only,
235 Addr, Base, Disp, Index);
237 bool selectBDXAddr20Only128(SDValue Addr, SDValue &Base, SDValue &Disp,
238 SDValue &Index) const {
239 return selectBDXAddr(SystemZAddressingMode::FormBDXNormal,
240 SystemZAddressingMode::Disp20Only128,
241 Addr, Base, Disp, Index);
243 bool selectBDXAddr20Pair(SDValue Addr, SDValue &Base, SDValue &Disp,
244 SDValue &Index) const {
245 return selectBDXAddr(SystemZAddressingMode::FormBDXNormal,
246 SystemZAddressingMode::Disp20Pair,
247 Addr, Base, Disp, Index);
249 bool selectLAAddr12Pair(SDValue Addr, SDValue &Base, SDValue &Disp,
250 SDValue &Index) const {
251 return selectBDXAddr(SystemZAddressingMode::FormBDXLA,
252 SystemZAddressingMode::Disp12Pair,
253 Addr, Base, Disp, Index);
255 bool selectLAAddr20Pair(SDValue Addr, SDValue &Base, SDValue &Disp,
256 SDValue &Index) const {
257 return selectBDXAddr(SystemZAddressingMode::FormBDXLA,
258 SystemZAddressingMode::Disp20Pair,
259 Addr, Base, Disp, Index);
262 // Try to match Addr as an address with a base, 12-bit displacement
263 // and index, where the index is element Elem of a vector.
264 // Return true on success, storing the base, displacement and vector
265 // in Base, Disp and Index respectively.
266 bool selectBDVAddr12Only(SDValue Addr, SDValue Elem, SDValue &Base,
267 SDValue &Disp, SDValue &Index) const;
269 // Check whether (or Op (and X InsertMask)) is effectively an insertion
270 // of X into bits InsertMask of some Y != Op. Return true if so and
272 bool detectOrAndInsertion(SDValue &Op, uint64_t InsertMask) const;
274 // Try to update RxSBG so that only the bits of RxSBG.Input in Mask are used.
275 // Return true on success.
276 bool refineRxSBGMask(RxSBGOperands &RxSBG, uint64_t Mask) const;
278 // Try to fold some of RxSBG.Input into other fields of RxSBG.
279 // Return true on success.
280 bool expandRxSBG(RxSBGOperands &RxSBG) const;
282 // Return an undefined value of type VT.
283 SDValue getUNDEF(const SDLoc &DL, EVT VT) const;
285 // Convert N to VT, if it isn't already.
286 SDValue convertTo(const SDLoc &DL, EVT VT, SDValue N) const;
288 // Try to implement AND or shift node N using RISBG with the zero flag set.
289 // Return the selected node on success, otherwise return null.
290 bool tryRISBGZero(SDNode *N);
292 // Try to use RISBG or Opcode to implement OR or XOR node N.
293 // Return the selected node on success, otherwise return null.
294 bool tryRxSBG(SDNode *N, unsigned Opcode);
296 // If Op0 is null, then Node is a constant that can be loaded using:
298 // (Opcode UpperVal LowerVal)
300 // If Op0 is nonnull, then Node can be implemented using:
302 // (Opcode (Opcode Op0 UpperVal) LowerVal)
303 void splitLargeImmediate(unsigned Opcode, SDNode *Node, SDValue Op0,
304 uint64_t UpperVal, uint64_t LowerVal);
306 // Try to use gather instruction Opcode to implement vector insertion N.
307 bool tryGather(SDNode *N, unsigned Opcode);
309 // Try to use scatter instruction Opcode to implement store Store.
310 bool tryScatter(StoreSDNode *Store, unsigned Opcode);
312 // Return true if Load and Store are loads and stores of the same size
313 // and are guaranteed not to overlap. Such operations can be implemented
314 // using block (SS-format) instructions.
316 // Partial overlap would lead to incorrect code, since the block operations
317 // are logically bytewise, even though they have a fast path for the
318 // non-overlapping case. We also need to avoid full overlap (i.e. two
319 // addresses that might be equal at run time) because although that case
320 // would be handled correctly, it might be implemented by millicode.
321 bool canUseBlockOperation(StoreSDNode *Store, LoadSDNode *Load) const;
323 // N is a (store (load Y), X) pattern. Return true if it can use an MVC
325 bool storeLoadCanUseMVC(SDNode *N) const;
327 // N is a (store (op (load A[0]), (load A[1])), X) pattern. Return true
328 // if A[1 - I] == X and if N can use a block operation like NC from A[I]
330 bool storeLoadCanUseBlockBinary(SDNode *N, unsigned I) const;
333 SystemZDAGToDAGISel(SystemZTargetMachine &TM, CodeGenOpt::Level OptLevel)
334 : SelectionDAGISel(TM, OptLevel) {}
336 bool runOnMachineFunction(MachineFunction &MF) override {
337 Subtarget = &MF.getSubtarget<SystemZSubtarget>();
338 return SelectionDAGISel::runOnMachineFunction(MF);
341 // Override MachineFunctionPass.
342 const char *getPassName() const override {
343 return "SystemZ DAG->DAG Pattern Instruction Selection";
346 // Override SelectionDAGISel.
347 void Select(SDNode *Node) override;
348 bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
349 std::vector<SDValue> &OutOps) override;
351 // Include the pieces autogenerated from the target description.
352 #include "SystemZGenDAGISel.inc"
354 } // end anonymous namespace
356 FunctionPass *llvm::createSystemZISelDag(SystemZTargetMachine &TM,
357 CodeGenOpt::Level OptLevel) {
358 return new SystemZDAGToDAGISel(TM, OptLevel);
361 // Return true if Val should be selected as a displacement for an address
362 // with range DR. Here we're interested in the range of both the instruction
363 // described by DR and of any pairing instruction.
364 static bool selectDisp(SystemZAddressingMode::DispRange DR, int64_t Val) {
366 case SystemZAddressingMode::Disp12Only:
367 return isUInt<12>(Val);
369 case SystemZAddressingMode::Disp12Pair:
370 case SystemZAddressingMode::Disp20Only:
371 case SystemZAddressingMode::Disp20Pair:
372 return isInt<20>(Val);
374 case SystemZAddressingMode::Disp20Only128:
375 return isInt<20>(Val) && isInt<20>(Val + 8);
377 llvm_unreachable("Unhandled displacement range");
380 // Change the base or index in AM to Value, where IsBase selects
381 // between the base and index.
382 static void changeComponent(SystemZAddressingMode &AM, bool IsBase,
390 // The base or index of AM is equivalent to Value + ADJDYNALLOC,
391 // where IsBase selects between the base and index. Try to fold the
392 // ADJDYNALLOC into AM.
393 static bool expandAdjDynAlloc(SystemZAddressingMode &AM, bool IsBase,
395 if (AM.isDynAlloc() && !AM.IncludesDynAlloc) {
396 changeComponent(AM, IsBase, Value);
397 AM.IncludesDynAlloc = true;
403 // The base of AM is equivalent to Base + Index. Try to use Index as
404 // the index register.
405 static bool expandIndex(SystemZAddressingMode &AM, SDValue Base,
407 if (AM.hasIndexField() && !AM.Index.getNode()) {
415 // The base or index of AM is equivalent to Op0 + Op1, where IsBase selects
416 // between the base and index. Try to fold Op1 into AM's displacement.
417 static bool expandDisp(SystemZAddressingMode &AM, bool IsBase,
418 SDValue Op0, uint64_t Op1) {
419 // First try adjusting the displacement.
420 int64_t TestDisp = AM.Disp + Op1;
421 if (selectDisp(AM.DR, TestDisp)) {
422 changeComponent(AM, IsBase, Op0);
427 // We could consider forcing the displacement into a register and
428 // using it as an index, but it would need to be carefully tuned.
432 bool SystemZDAGToDAGISel::expandAddress(SystemZAddressingMode &AM,
434 SDValue N = IsBase ? AM.Base : AM.Index;
435 unsigned Opcode = N.getOpcode();
436 if (Opcode == ISD::TRUNCATE) {
438 Opcode = N.getOpcode();
440 if (Opcode == ISD::ADD || CurDAG->isBaseWithConstantOffset(N)) {
441 SDValue Op0 = N.getOperand(0);
442 SDValue Op1 = N.getOperand(1);
444 unsigned Op0Code = Op0->getOpcode();
445 unsigned Op1Code = Op1->getOpcode();
447 if (Op0Code == SystemZISD::ADJDYNALLOC)
448 return expandAdjDynAlloc(AM, IsBase, Op1);
449 if (Op1Code == SystemZISD::ADJDYNALLOC)
450 return expandAdjDynAlloc(AM, IsBase, Op0);
452 if (Op0Code == ISD::Constant)
453 return expandDisp(AM, IsBase, Op1,
454 cast<ConstantSDNode>(Op0)->getSExtValue());
455 if (Op1Code == ISD::Constant)
456 return expandDisp(AM, IsBase, Op0,
457 cast<ConstantSDNode>(Op1)->getSExtValue());
459 if (IsBase && expandIndex(AM, Op0, Op1))
462 if (Opcode == SystemZISD::PCREL_OFFSET) {
463 SDValue Full = N.getOperand(0);
464 SDValue Base = N.getOperand(1);
465 SDValue Anchor = Base.getOperand(0);
466 uint64_t Offset = (cast<GlobalAddressSDNode>(Full)->getOffset() -
467 cast<GlobalAddressSDNode>(Anchor)->getOffset());
468 return expandDisp(AM, IsBase, Base, Offset);
473 // Return true if an instruction with displacement range DR should be
474 // used for displacement value Val. selectDisp(DR, Val) must already hold.
475 static bool isValidDisp(SystemZAddressingMode::DispRange DR, int64_t Val) {
476 assert(selectDisp(DR, Val) && "Invalid displacement");
478 case SystemZAddressingMode::Disp12Only:
479 case SystemZAddressingMode::Disp20Only:
480 case SystemZAddressingMode::Disp20Only128:
483 case SystemZAddressingMode::Disp12Pair:
484 // Use the other instruction if the displacement is too large.
485 return isUInt<12>(Val);
487 case SystemZAddressingMode::Disp20Pair:
488 // Use the other instruction if the displacement is small enough.
489 return !isUInt<12>(Val);
491 llvm_unreachable("Unhandled displacement range");
494 // Return true if Base + Disp + Index should be performed by LA(Y).
495 static bool shouldUseLA(SDNode *Base, int64_t Disp, SDNode *Index) {
496 // Don't use LA(Y) for constants.
500 // Always use LA(Y) for frame addresses, since we know that the destination
501 // register is almost always (perhaps always) going to be different from
502 // the frame register.
503 if (Base->getOpcode() == ISD::FrameIndex)
507 // Always use LA(Y) if there is a base, displacement and index.
511 // Always use LA if the displacement is small enough. It should always
512 // be no worse than AGHI (and better if it avoids a move).
513 if (isUInt<12>(Disp))
516 // For similar reasons, always use LAY if the constant is too big for AGHI.
517 // LAY should be no worse than AGFI.
518 if (!isInt<16>(Disp))
521 // Don't use LA for plain registers.
525 // Don't use LA for plain addition if the index operand is only used
526 // once. It should be a natural two-operand addition in that case.
527 if (Index->hasOneUse())
530 // Prefer addition if the second operation is sign-extended, in the
531 // hope of using AGF.
532 unsigned IndexOpcode = Index->getOpcode();
533 if (IndexOpcode == ISD::SIGN_EXTEND ||
534 IndexOpcode == ISD::SIGN_EXTEND_INREG)
538 // Don't use LA for two-operand addition if either operand is only
539 // used once. The addition instructions are better in that case.
540 if (Base->hasOneUse())
546 // Return true if Addr is suitable for AM, updating AM if so.
547 bool SystemZDAGToDAGISel::selectAddress(SDValue Addr,
548 SystemZAddressingMode &AM) const {
549 // Start out assuming that the address will need to be loaded separately,
550 // then try to extend it as much as we can.
553 // First try treating the address as a constant.
554 if (Addr.getOpcode() == ISD::Constant &&
555 expandDisp(AM, true, SDValue(),
556 cast<ConstantSDNode>(Addr)->getSExtValue()))
558 // Also see if it's a bare ADJDYNALLOC.
559 else if (Addr.getOpcode() == SystemZISD::ADJDYNALLOC &&
560 expandAdjDynAlloc(AM, true, SDValue()))
563 // Otherwise try expanding each component.
564 while (expandAddress(AM, true) ||
565 (AM.Index.getNode() && expandAddress(AM, false)))
568 // Reject cases where it isn't profitable to use LA(Y).
569 if (AM.Form == SystemZAddressingMode::FormBDXLA &&
570 !shouldUseLA(AM.Base.getNode(), AM.Disp, AM.Index.getNode()))
573 // Reject cases where the other instruction in a pair should be used.
574 if (!isValidDisp(AM.DR, AM.Disp))
577 // Make sure that ADJDYNALLOC is included where necessary.
578 if (AM.isDynAlloc() && !AM.IncludesDynAlloc)
585 // Insert a node into the DAG at least before Pos. This will reposition
586 // the node as needed, and will assign it a node ID that is <= Pos's ID.
587 // Note that this does *not* preserve the uniqueness of node IDs!
588 // The selection DAG must no longer depend on their uniqueness when this
590 static void insertDAGNode(SelectionDAG *DAG, SDNode *Pos, SDValue N) {
591 if (N.getNode()->getNodeId() == -1 ||
592 N.getNode()->getNodeId() > Pos->getNodeId()) {
593 DAG->RepositionNode(Pos->getIterator(), N.getNode());
594 N.getNode()->setNodeId(Pos->getNodeId());
598 void SystemZDAGToDAGISel::getAddressOperands(const SystemZAddressingMode &AM,
599 EVT VT, SDValue &Base,
600 SDValue &Disp) const {
603 // Register 0 means "no base". This is mostly useful for shifts.
604 Base = CurDAG->getRegister(0, VT);
605 else if (Base.getOpcode() == ISD::FrameIndex) {
606 // Lower a FrameIndex to a TargetFrameIndex.
607 int64_t FrameIndex = cast<FrameIndexSDNode>(Base)->getIndex();
608 Base = CurDAG->getTargetFrameIndex(FrameIndex, VT);
609 } else if (Base.getValueType() != VT) {
610 // Truncate values from i64 to i32, for shifts.
611 assert(VT == MVT::i32 && Base.getValueType() == MVT::i64 &&
612 "Unexpected truncation");
614 SDValue Trunc = CurDAG->getNode(ISD::TRUNCATE, DL, VT, Base);
615 insertDAGNode(CurDAG, Base.getNode(), Trunc);
619 // Lower the displacement to a TargetConstant.
620 Disp = CurDAG->getTargetConstant(AM.Disp, SDLoc(Base), VT);
623 void SystemZDAGToDAGISel::getAddressOperands(const SystemZAddressingMode &AM,
624 EVT VT, SDValue &Base,
626 SDValue &Index) const {
627 getAddressOperands(AM, VT, Base, Disp);
630 if (!Index.getNode())
631 // Register 0 means "no index".
632 Index = CurDAG->getRegister(0, VT);
635 bool SystemZDAGToDAGISel::selectBDAddr(SystemZAddressingMode::DispRange DR,
636 SDValue Addr, SDValue &Base,
637 SDValue &Disp) const {
638 SystemZAddressingMode AM(SystemZAddressingMode::FormBD, DR);
639 if (!selectAddress(Addr, AM))
642 getAddressOperands(AM, Addr.getValueType(), Base, Disp);
646 bool SystemZDAGToDAGISel::selectMVIAddr(SystemZAddressingMode::DispRange DR,
647 SDValue Addr, SDValue &Base,
648 SDValue &Disp) const {
649 SystemZAddressingMode AM(SystemZAddressingMode::FormBDXNormal, DR);
650 if (!selectAddress(Addr, AM) || AM.Index.getNode())
653 getAddressOperands(AM, Addr.getValueType(), Base, Disp);
657 bool SystemZDAGToDAGISel::selectBDXAddr(SystemZAddressingMode::AddrForm Form,
658 SystemZAddressingMode::DispRange DR,
659 SDValue Addr, SDValue &Base,
660 SDValue &Disp, SDValue &Index) const {
661 SystemZAddressingMode AM(Form, DR);
662 if (!selectAddress(Addr, AM))
665 getAddressOperands(AM, Addr.getValueType(), Base, Disp, Index);
669 bool SystemZDAGToDAGISel::selectBDVAddr12Only(SDValue Addr, SDValue Elem,
672 SDValue &Index) const {
674 if (selectBDXAddr12Only(Addr, Regs[0], Disp, Regs[1]) &&
675 Regs[0].getNode() && Regs[1].getNode()) {
676 for (unsigned int I = 0; I < 2; ++I) {
679 // We can't tell here whether the index vector has the right type
680 // for the access; the caller needs to do that instead.
681 if (Index.getOpcode() == ISD::ZERO_EXTEND)
682 Index = Index.getOperand(0);
683 if (Index.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
684 Index.getOperand(1) == Elem) {
685 Index = Index.getOperand(0);
693 bool SystemZDAGToDAGISel::detectOrAndInsertion(SDValue &Op,
694 uint64_t InsertMask) const {
695 // We're only interested in cases where the insertion is into some operand
696 // of Op, rather than into Op itself. The only useful case is an AND.
697 if (Op.getOpcode() != ISD::AND)
700 // We need a constant mask.
701 auto *MaskNode = dyn_cast<ConstantSDNode>(Op.getOperand(1).getNode());
705 // It's not an insertion of Op.getOperand(0) if the two masks overlap.
706 uint64_t AndMask = MaskNode->getZExtValue();
707 if (InsertMask & AndMask)
710 // It's only an insertion if all bits are covered or are known to be zero.
711 // The inner check covers all cases but is more expensive.
712 uint64_t Used = allOnes(Op.getValueType().getSizeInBits());
713 if (Used != (AndMask | InsertMask)) {
714 APInt KnownZero, KnownOne;
715 CurDAG->computeKnownBits(Op.getOperand(0), KnownZero, KnownOne);
716 if (Used != (AndMask | InsertMask | KnownZero.getZExtValue()))
720 Op = Op.getOperand(0);
724 bool SystemZDAGToDAGISel::refineRxSBGMask(RxSBGOperands &RxSBG,
725 uint64_t Mask) const {
726 const SystemZInstrInfo *TII = getInstrInfo();
727 if (RxSBG.Rotate != 0)
728 Mask = (Mask << RxSBG.Rotate) | (Mask >> (64 - RxSBG.Rotate));
730 if (TII->isRxSBGMask(Mask, RxSBG.BitSize, RxSBG.Start, RxSBG.End)) {
737 // Return true if any bits of (RxSBG.Input & Mask) are significant.
738 static bool maskMatters(RxSBGOperands &RxSBG, uint64_t Mask) {
739 // Rotate the mask in the same way as RxSBG.Input is rotated.
740 if (RxSBG.Rotate != 0)
741 Mask = ((Mask << RxSBG.Rotate) | (Mask >> (64 - RxSBG.Rotate)));
742 return (Mask & RxSBG.Mask) != 0;
745 bool SystemZDAGToDAGISel::expandRxSBG(RxSBGOperands &RxSBG) const {
746 SDValue N = RxSBG.Input;
747 unsigned Opcode = N.getOpcode();
749 case ISD::TRUNCATE: {
750 if (RxSBG.Opcode == SystemZ::RNSBG)
752 uint64_t BitSize = N.getValueType().getSizeInBits();
753 uint64_t Mask = allOnes(BitSize);
754 if (!refineRxSBGMask(RxSBG, Mask))
756 RxSBG.Input = N.getOperand(0);
760 if (RxSBG.Opcode == SystemZ::RNSBG)
763 auto *MaskNode = dyn_cast<ConstantSDNode>(N.getOperand(1).getNode());
767 SDValue Input = N.getOperand(0);
768 uint64_t Mask = MaskNode->getZExtValue();
769 if (!refineRxSBGMask(RxSBG, Mask)) {
770 // If some bits of Input are already known zeros, those bits will have
771 // been removed from the mask. See if adding them back in makes the
773 APInt KnownZero, KnownOne;
774 CurDAG->computeKnownBits(Input, KnownZero, KnownOne);
775 Mask |= KnownZero.getZExtValue();
776 if (!refineRxSBGMask(RxSBG, Mask))
784 if (RxSBG.Opcode != SystemZ::RNSBG)
787 auto *MaskNode = dyn_cast<ConstantSDNode>(N.getOperand(1).getNode());
791 SDValue Input = N.getOperand(0);
792 uint64_t Mask = ~MaskNode->getZExtValue();
793 if (!refineRxSBGMask(RxSBG, Mask)) {
794 // If some bits of Input are already known ones, those bits will have
795 // been removed from the mask. See if adding them back in makes the
797 APInt KnownZero, KnownOne;
798 CurDAG->computeKnownBits(Input, KnownZero, KnownOne);
799 Mask &= ~KnownOne.getZExtValue();
800 if (!refineRxSBGMask(RxSBG, Mask))
808 // Any 64-bit rotate left can be merged into the RxSBG.
809 if (RxSBG.BitSize != 64 || N.getValueType() != MVT::i64)
811 auto *CountNode = dyn_cast<ConstantSDNode>(N.getOperand(1).getNode());
815 RxSBG.Rotate = (RxSBG.Rotate + CountNode->getZExtValue()) & 63;
816 RxSBG.Input = N.getOperand(0);
820 case ISD::ANY_EXTEND:
821 // Bits above the extended operand are don't-care.
822 RxSBG.Input = N.getOperand(0);
825 case ISD::ZERO_EXTEND:
826 if (RxSBG.Opcode != SystemZ::RNSBG) {
827 // Restrict the mask to the extended operand.
828 unsigned InnerBitSize = N.getOperand(0).getValueType().getSizeInBits();
829 if (!refineRxSBGMask(RxSBG, allOnes(InnerBitSize)))
832 RxSBG.Input = N.getOperand(0);
837 case ISD::SIGN_EXTEND: {
838 // Check that the extension bits are don't-care (i.e. are masked out
839 // by the final mask).
840 unsigned InnerBitSize = N.getOperand(0).getValueType().getSizeInBits();
841 if (maskMatters(RxSBG, allOnes(RxSBG.BitSize) - allOnes(InnerBitSize)))
844 RxSBG.Input = N.getOperand(0);
849 auto *CountNode = dyn_cast<ConstantSDNode>(N.getOperand(1).getNode());
853 uint64_t Count = CountNode->getZExtValue();
854 unsigned BitSize = N.getValueType().getSizeInBits();
855 if (Count < 1 || Count >= BitSize)
858 if (RxSBG.Opcode == SystemZ::RNSBG) {
859 // Treat (shl X, count) as (rotl X, size-count) as long as the bottom
860 // count bits from RxSBG.Input are ignored.
861 if (maskMatters(RxSBG, allOnes(Count)))
864 // Treat (shl X, count) as (and (rotl X, count), ~0<<count).
865 if (!refineRxSBGMask(RxSBG, allOnes(BitSize - Count) << Count))
869 RxSBG.Rotate = (RxSBG.Rotate + Count) & 63;
870 RxSBG.Input = N.getOperand(0);
876 auto *CountNode = dyn_cast<ConstantSDNode>(N.getOperand(1).getNode());
880 uint64_t Count = CountNode->getZExtValue();
881 unsigned BitSize = N.getValueType().getSizeInBits();
882 if (Count < 1 || Count >= BitSize)
885 if (RxSBG.Opcode == SystemZ::RNSBG || Opcode == ISD::SRA) {
886 // Treat (srl|sra X, count) as (rotl X, size-count) as long as the top
887 // count bits from RxSBG.Input are ignored.
888 if (maskMatters(RxSBG, allOnes(Count) << (BitSize - Count)))
891 // Treat (srl X, count), mask) as (and (rotl X, size-count), ~0>>count),
892 // which is similar to SLL above.
893 if (!refineRxSBGMask(RxSBG, allOnes(BitSize - Count)))
897 RxSBG.Rotate = (RxSBG.Rotate - Count) & 63;
898 RxSBG.Input = N.getOperand(0);
906 SDValue SystemZDAGToDAGISel::getUNDEF(const SDLoc &DL, EVT VT) const {
907 SDNode *N = CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, VT);
908 return SDValue(N, 0);
911 SDValue SystemZDAGToDAGISel::convertTo(const SDLoc &DL, EVT VT,
913 if (N.getValueType() == MVT::i32 && VT == MVT::i64)
914 return CurDAG->getTargetInsertSubreg(SystemZ::subreg_l32,
915 DL, VT, getUNDEF(DL, MVT::i64), N);
916 if (N.getValueType() == MVT::i64 && VT == MVT::i32)
917 return CurDAG->getTargetExtractSubreg(SystemZ::subreg_l32, DL, VT, N);
918 assert(N.getValueType() == VT && "Unexpected value types");
922 bool SystemZDAGToDAGISel::tryRISBGZero(SDNode *N) {
924 EVT VT = N->getValueType(0);
925 if (!VT.isInteger() || VT.getSizeInBits() > 64)
927 RxSBGOperands RISBG(SystemZ::RISBG, SDValue(N, 0));
929 while (expandRxSBG(RISBG))
930 // The widening or narrowing is expected to be free.
931 // Counting widening or narrowing as a saved operation will result in
932 // preferring an R*SBG over a simple shift/logical instruction.
933 if (RISBG.Input.getOpcode() != ISD::ANY_EXTEND &&
934 RISBG.Input.getOpcode() != ISD::TRUNCATE)
939 // Prefer to use normal shift instructions over RISBG, since they can handle
940 // all cases and are sometimes shorter.
941 if (N->getOpcode() != ISD::AND)
944 // Prefer register extensions like LLC over RISBG. Also prefer to start
945 // out with normal ANDs if one instruction would be enough. We can convert
946 // these ANDs into an RISBG later if a three-address instruction is useful.
947 if (VT == MVT::i32 ||
948 RISBG.Mask == 0xff ||
949 RISBG.Mask == 0xffff ||
950 SystemZ::isImmLF(~RISBG.Mask) ||
951 SystemZ::isImmHF(~RISBG.Mask)) {
952 // Force the new mask into the DAG, since it may include known-one bits.
953 auto *MaskN = cast<ConstantSDNode>(N->getOperand(1).getNode());
954 if (MaskN->getZExtValue() != RISBG.Mask) {
955 SDValue NewMask = CurDAG->getConstant(RISBG.Mask, DL, VT);
956 N = CurDAG->UpdateNodeOperands(N, N->getOperand(0), NewMask);
964 // If the RISBG operands require no rotation and just masks the bottom
965 // 8/16 bits, attempt to convert this to a LLC zero extension.
966 if (RISBG.Rotate == 0 && (RISBG.Mask == 0xff || RISBG.Mask == 0xffff)) {
967 unsigned OpCode = (RISBG.Mask == 0xff ? SystemZ::LLGCR : SystemZ::LLGHR);
968 if (VT == MVT::i32) {
969 if (Subtarget->hasHighWord())
970 OpCode = (RISBG.Mask == 0xff ? SystemZ::LLCRMux : SystemZ::LLHRMux);
972 OpCode = (RISBG.Mask == 0xff ? SystemZ::LLCR : SystemZ::LLHR);
975 SDValue In = convertTo(DL, VT, RISBG.Input);
976 SDValue New = convertTo(
977 DL, VT, SDValue(CurDAG->getMachineNode(OpCode, DL, VT, In), 0));
978 ReplaceUses(N, New.getNode());
979 CurDAG->RemoveDeadNode(N);
983 unsigned Opcode = SystemZ::RISBG;
984 // Prefer RISBGN if available, since it does not clobber CC.
985 if (Subtarget->hasMiscellaneousExtensions())
986 Opcode = SystemZ::RISBGN;
987 EVT OpcodeVT = MVT::i64;
988 if (VT == MVT::i32 && Subtarget->hasHighWord()) {
989 Opcode = SystemZ::RISBMux;
995 getUNDEF(DL, OpcodeVT),
996 convertTo(DL, OpcodeVT, RISBG.Input),
997 CurDAG->getTargetConstant(RISBG.Start, DL, MVT::i32),
998 CurDAG->getTargetConstant(RISBG.End | 128, DL, MVT::i32),
999 CurDAG->getTargetConstant(RISBG.Rotate, DL, MVT::i32)
1001 SDValue New = convertTo(
1002 DL, VT, SDValue(CurDAG->getMachineNode(Opcode, DL, OpcodeVT, Ops), 0));
1003 ReplaceUses(N, New.getNode());
1004 CurDAG->RemoveDeadNode(N);
1008 bool SystemZDAGToDAGISel::tryRxSBG(SDNode *N, unsigned Opcode) {
1010 EVT VT = N->getValueType(0);
1011 if (!VT.isInteger() || VT.getSizeInBits() > 64)
1013 // Try treating each operand of N as the second operand of the RxSBG
1014 // and see which goes deepest.
1015 RxSBGOperands RxSBG[] = {
1016 RxSBGOperands(Opcode, N->getOperand(0)),
1017 RxSBGOperands(Opcode, N->getOperand(1))
1019 unsigned Count[] = { 0, 0 };
1020 for (unsigned I = 0; I < 2; ++I)
1021 while (expandRxSBG(RxSBG[I]))
1022 // The widening or narrowing is expected to be free.
1023 // Counting widening or narrowing as a saved operation will result in
1024 // preferring an R*SBG over a simple shift/logical instruction.
1025 if (RxSBG[I].Input.getOpcode() != ISD::ANY_EXTEND &&
1026 RxSBG[I].Input.getOpcode() != ISD::TRUNCATE)
1029 // Do nothing if neither operand is suitable.
1030 if (Count[0] == 0 && Count[1] == 0)
1033 // Pick the deepest second operand.
1034 unsigned I = Count[0] > Count[1] ? 0 : 1;
1035 SDValue Op0 = N->getOperand(I ^ 1);
1037 // Prefer IC for character insertions from memory.
1038 if (Opcode == SystemZ::ROSBG && (RxSBG[I].Mask & 0xff) == 0)
1039 if (auto *Load = dyn_cast<LoadSDNode>(Op0.getNode()))
1040 if (Load->getMemoryVT() == MVT::i8)
1043 // See whether we can avoid an AND in the first operand by converting
1045 if (Opcode == SystemZ::ROSBG && detectOrAndInsertion(Op0, RxSBG[I].Mask)) {
1046 Opcode = SystemZ::RISBG;
1047 // Prefer RISBGN if available, since it does not clobber CC.
1048 if (Subtarget->hasMiscellaneousExtensions())
1049 Opcode = SystemZ::RISBGN;
1053 convertTo(DL, MVT::i64, Op0),
1054 convertTo(DL, MVT::i64, RxSBG[I].Input),
1055 CurDAG->getTargetConstant(RxSBG[I].Start, DL, MVT::i32),
1056 CurDAG->getTargetConstant(RxSBG[I].End, DL, MVT::i32),
1057 CurDAG->getTargetConstant(RxSBG[I].Rotate, DL, MVT::i32)
1059 SDValue New = convertTo(
1060 DL, VT, SDValue(CurDAG->getMachineNode(Opcode, DL, MVT::i64, Ops), 0));
1061 ReplaceNode(N, New.getNode());
1065 void SystemZDAGToDAGISel::splitLargeImmediate(unsigned Opcode, SDNode *Node,
1066 SDValue Op0, uint64_t UpperVal,
1067 uint64_t LowerVal) {
1068 EVT VT = Node->getValueType(0);
1070 SDValue Upper = CurDAG->getConstant(UpperVal, DL, VT);
1072 Upper = CurDAG->getNode(Opcode, DL, VT, Op0, Upper);
1075 // When we haven't passed in Op0, Upper will be a constant. In order to
1076 // prevent folding back to the large immediate in `Or = getNode(...)` we run
1077 // SelectCode first and end up with an opaque machine node. This means that
1078 // we need to use a handle to keep track of Upper in case it gets CSE'd by
1081 // Note that in the case where Op0 is passed in we could just call
1082 // SelectCode(Upper) later, along with the SelectCode(Or), and avoid needing
1083 // the handle at all, but it's fine to do it here.
1085 // TODO: This is a pretty hacky way to do this. Can we do something that
1086 // doesn't require a two paragraph explanation?
1087 HandleSDNode Handle(Upper);
1088 SelectCode(Upper.getNode());
1089 Upper = Handle.getValue();
1092 SDValue Lower = CurDAG->getConstant(LowerVal, DL, VT);
1093 SDValue Or = CurDAG->getNode(Opcode, DL, VT, Upper, Lower);
1095 ReplaceUses(Node, Or.getNode());
1096 CurDAG->RemoveDeadNode(Node);
1098 SelectCode(Or.getNode());
1101 bool SystemZDAGToDAGISel::tryGather(SDNode *N, unsigned Opcode) {
1102 SDValue ElemV = N->getOperand(2);
1103 auto *ElemN = dyn_cast<ConstantSDNode>(ElemV);
1107 unsigned Elem = ElemN->getZExtValue();
1108 EVT VT = N->getValueType(0);
1109 if (Elem >= VT.getVectorNumElements())
1112 auto *Load = dyn_cast<LoadSDNode>(N->getOperand(1));
1113 if (!Load || !Load->hasOneUse())
1115 if (Load->getMemoryVT().getSizeInBits() !=
1116 Load->getValueType(0).getSizeInBits())
1119 SDValue Base, Disp, Index;
1120 if (!selectBDVAddr12Only(Load->getBasePtr(), ElemV, Base, Disp, Index) ||
1121 Index.getValueType() != VT.changeVectorElementTypeToInteger())
1126 N->getOperand(0), Base, Disp, Index,
1127 CurDAG->getTargetConstant(Elem, DL, MVT::i32), Load->getChain()
1129 SDNode *Res = CurDAG->getMachineNode(Opcode, DL, VT, MVT::Other, Ops);
1130 ReplaceUses(SDValue(Load, 1), SDValue(Res, 1));
1131 ReplaceNode(N, Res);
1135 bool SystemZDAGToDAGISel::tryScatter(StoreSDNode *Store, unsigned Opcode) {
1136 SDValue Value = Store->getValue();
1137 if (Value.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
1139 if (Store->getMemoryVT().getSizeInBits() !=
1140 Value.getValueType().getSizeInBits())
1143 SDValue ElemV = Value.getOperand(1);
1144 auto *ElemN = dyn_cast<ConstantSDNode>(ElemV);
1148 SDValue Vec = Value.getOperand(0);
1149 EVT VT = Vec.getValueType();
1150 unsigned Elem = ElemN->getZExtValue();
1151 if (Elem >= VT.getVectorNumElements())
1154 SDValue Base, Disp, Index;
1155 if (!selectBDVAddr12Only(Store->getBasePtr(), ElemV, Base, Disp, Index) ||
1156 Index.getValueType() != VT.changeVectorElementTypeToInteger())
1161 Vec, Base, Disp, Index, CurDAG->getTargetConstant(Elem, DL, MVT::i32),
1164 ReplaceNode(Store, CurDAG->getMachineNode(Opcode, DL, MVT::Other, Ops));
1168 bool SystemZDAGToDAGISel::canUseBlockOperation(StoreSDNode *Store,
1169 LoadSDNode *Load) const {
1170 // Check that the two memory operands have the same size.
1171 if (Load->getMemoryVT() != Store->getMemoryVT())
1174 // Volatility stops an access from being decomposed.
1175 if (Load->isVolatile() || Store->isVolatile())
1178 // There's no chance of overlap if the load is invariant.
1179 if (Load->isInvariant())
1182 // Otherwise we need to check whether there's an alias.
1183 const Value *V1 = Load->getMemOperand()->getValue();
1184 const Value *V2 = Store->getMemOperand()->getValue();
1189 uint64_t Size = Load->getMemoryVT().getStoreSize();
1190 int64_t End1 = Load->getSrcValueOffset() + Size;
1191 int64_t End2 = Store->getSrcValueOffset() + Size;
1192 if (V1 == V2 && End1 == End2)
1195 return !AA->alias(MemoryLocation(V1, End1, Load->getAAInfo()),
1196 MemoryLocation(V2, End2, Store->getAAInfo()));
1199 bool SystemZDAGToDAGISel::storeLoadCanUseMVC(SDNode *N) const {
1200 auto *Store = cast<StoreSDNode>(N);
1201 auto *Load = cast<LoadSDNode>(Store->getValue());
1203 // Prefer not to use MVC if either address can use ... RELATIVE LONG
1205 uint64_t Size = Load->getMemoryVT().getStoreSize();
1206 if (Size > 1 && Size <= 8) {
1207 // Prefer LHRL, LRL and LGRL.
1208 if (SystemZISD::isPCREL(Load->getBasePtr().getOpcode()))
1210 // Prefer STHRL, STRL and STGRL.
1211 if (SystemZISD::isPCREL(Store->getBasePtr().getOpcode()))
1215 return canUseBlockOperation(Store, Load);
1218 bool SystemZDAGToDAGISel::storeLoadCanUseBlockBinary(SDNode *N,
1220 auto *StoreA = cast<StoreSDNode>(N);
1221 auto *LoadA = cast<LoadSDNode>(StoreA->getValue().getOperand(1 - I));
1222 auto *LoadB = cast<LoadSDNode>(StoreA->getValue().getOperand(I));
1223 return !LoadA->isVolatile() && canUseBlockOperation(StoreA, LoadB);
1226 void SystemZDAGToDAGISel::Select(SDNode *Node) {
1227 // Dump information about the Node being selected
1228 DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n");
1230 // If we have a custom node, we already have selected!
1231 if (Node->isMachineOpcode()) {
1232 DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");
1233 Node->setNodeId(-1);
1237 unsigned Opcode = Node->getOpcode();
1240 if (Node->getOperand(1).getOpcode() != ISD::Constant)
1241 if (tryRxSBG(Node, SystemZ::ROSBG))
1246 if (Node->getOperand(1).getOpcode() != ISD::Constant)
1247 if (tryRxSBG(Node, SystemZ::RXSBG))
1251 // If this is a 64-bit operation in which both 32-bit halves are nonzero,
1252 // split the operation into two.
1253 if (Node->getValueType(0) == MVT::i64)
1254 if (auto *Op1 = dyn_cast<ConstantSDNode>(Node->getOperand(1))) {
1255 uint64_t Val = Op1->getZExtValue();
1256 if (!SystemZ::isImmLF(Val) && !SystemZ::isImmHF(Val)) {
1257 splitLargeImmediate(Opcode, Node, Node->getOperand(0),
1258 Val - uint32_t(Val), uint32_t(Val));
1265 if (Node->getOperand(1).getOpcode() != ISD::Constant)
1266 if (tryRxSBG(Node, SystemZ::RNSBG))
1272 case ISD::ZERO_EXTEND:
1273 if (tryRISBGZero(Node))
1278 // If this is a 64-bit constant that is out of the range of LLILF,
1279 // LLIHF and LGFI, split it into two 32-bit pieces.
1280 if (Node->getValueType(0) == MVT::i64) {
1281 uint64_t Val = cast<ConstantSDNode>(Node)->getZExtValue();
1282 if (!SystemZ::isImmLF(Val) && !SystemZ::isImmHF(Val) && !isInt<32>(Val)) {
1283 splitLargeImmediate(ISD::OR, Node, SDValue(), Val - uint32_t(Val),
1290 case SystemZISD::SELECT_CCMASK: {
1291 SDValue Op0 = Node->getOperand(0);
1292 SDValue Op1 = Node->getOperand(1);
1293 // Prefer to put any load first, so that it can be matched as a
1294 // conditional load.
1295 if (Op1.getOpcode() == ISD::LOAD && Op0.getOpcode() != ISD::LOAD) {
1296 SDValue CCValid = Node->getOperand(2);
1297 SDValue CCMask = Node->getOperand(3);
1298 uint64_t ConstCCValid =
1299 cast<ConstantSDNode>(CCValid.getNode())->getZExtValue();
1300 uint64_t ConstCCMask =
1301 cast<ConstantSDNode>(CCMask.getNode())->getZExtValue();
1302 // Invert the condition.
1303 CCMask = CurDAG->getConstant(ConstCCValid ^ ConstCCMask, SDLoc(Node),
1304 CCMask.getValueType());
1305 SDValue Op4 = Node->getOperand(4);
1306 Node = CurDAG->UpdateNodeOperands(Node, Op1, Op0, CCValid, CCMask, Op4);
1311 case ISD::INSERT_VECTOR_ELT: {
1312 EVT VT = Node->getValueType(0);
1313 unsigned ElemBitSize = VT.getVectorElementType().getSizeInBits();
1314 if (ElemBitSize == 32) {
1315 if (tryGather(Node, SystemZ::VGEF))
1317 } else if (ElemBitSize == 64) {
1318 if (tryGather(Node, SystemZ::VGEG))
1325 auto *Store = cast<StoreSDNode>(Node);
1326 unsigned ElemBitSize = Store->getValue().getValueType().getSizeInBits();
1327 if (ElemBitSize == 32) {
1328 if (tryScatter(Store, SystemZ::VSCEF))
1330 } else if (ElemBitSize == 64) {
1331 if (tryScatter(Store, SystemZ::VSCEG))
1341 bool SystemZDAGToDAGISel::
1342 SelectInlineAsmMemoryOperand(const SDValue &Op,
1343 unsigned ConstraintID,
1344 std::vector<SDValue> &OutOps) {
1345 SystemZAddressingMode::AddrForm Form;
1346 SystemZAddressingMode::DispRange DispRange;
1347 SDValue Base, Disp, Index;
1349 switch(ConstraintID) {
1351 llvm_unreachable("Unexpected asm memory constraint");
1352 case InlineAsm::Constraint_i:
1353 case InlineAsm::Constraint_Q:
1354 // Accept an address with a short displacement, but no index.
1355 Form = SystemZAddressingMode::FormBD;
1356 DispRange = SystemZAddressingMode::Disp12Only;
1358 case InlineAsm::Constraint_R:
1359 // Accept an address with a short displacement and an index.
1360 Form = SystemZAddressingMode::FormBDXNormal;
1361 DispRange = SystemZAddressingMode::Disp12Only;
1363 case InlineAsm::Constraint_S:
1364 // Accept an address with a long displacement, but no index.
1365 Form = SystemZAddressingMode::FormBD;
1366 DispRange = SystemZAddressingMode::Disp20Only;
1368 case InlineAsm::Constraint_T:
1369 case InlineAsm::Constraint_m:
1370 // Accept an address with a long displacement and an index.
1371 // m works the same as T, as this is the most general case.
1372 Form = SystemZAddressingMode::FormBDXNormal;
1373 DispRange = SystemZAddressingMode::Disp20Only;
1377 if (selectBDXAddr(Form, DispRange, Op, Base, Disp, Index)) {
1378 OutOps.push_back(Base);
1379 OutOps.push_back(Disp);
1380 OutOps.push_back(Index);