1 //===-- SystemZISelLowering.cpp - SystemZ DAG lowering implementation -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SystemZTargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "SystemZISelLowering.h"
15 #include "SystemZCallingConv.h"
16 #include "SystemZConstantPoolValue.h"
17 #include "SystemZMachineFunctionInfo.h"
18 #include "SystemZTargetMachine.h"
19 #include "llvm/CodeGen/CallingConvLower.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
23 #include "llvm/Support/CommandLine.h"
24 #include "llvm/IR/Intrinsics.h"
29 #define DEBUG_TYPE "systemz-lower"
32 // Represents a sequence for extracting a 0/1 value from an IPM result:
33 // (((X ^ XORValue) + AddValue) >> Bit)
34 struct IPMConversion {
35 IPMConversion(unsigned xorValue, int64_t addValue, unsigned bit)
36 : XORValue(xorValue), AddValue(addValue), Bit(bit) {}
43 // Represents information about a comparison.
45 Comparison(SDValue Op0In, SDValue Op1In)
46 : Op0(Op0In), Op1(Op1In), Opcode(0), ICmpType(0), CCValid(0), CCMask(0) {}
48 // The operands to the comparison.
51 // The opcode that should be used to compare Op0 and Op1.
54 // A SystemZICMP value. Only used for integer comparisons.
57 // The mask of CC values that Opcode can produce.
60 // The mask of CC values for which the original condition is true.
63 } // end anonymous namespace
65 // Classify VT as either 32 or 64 bit.
66 static bool is32Bit(EVT VT) {
67 switch (VT.getSimpleVT().SimpleTy) {
73 llvm_unreachable("Unsupported type");
77 // Return a version of MachineOperand that can be safely used before the
79 static MachineOperand earlyUseOperand(MachineOperand Op) {
85 SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &TM,
86 const SystemZSubtarget &STI)
87 : TargetLowering(TM), Subtarget(STI) {
88 MVT PtrVT = MVT::getIntegerVT(8 * TM.getPointerSize());
90 // Set up the register classes.
91 if (Subtarget.hasHighWord())
92 addRegisterClass(MVT::i32, &SystemZ::GRX32BitRegClass);
94 addRegisterClass(MVT::i32, &SystemZ::GR32BitRegClass);
95 addRegisterClass(MVT::i64, &SystemZ::GR64BitRegClass);
96 if (Subtarget.hasVector()) {
97 addRegisterClass(MVT::f32, &SystemZ::VR32BitRegClass);
98 addRegisterClass(MVT::f64, &SystemZ::VR64BitRegClass);
100 addRegisterClass(MVT::f32, &SystemZ::FP32BitRegClass);
101 addRegisterClass(MVT::f64, &SystemZ::FP64BitRegClass);
103 addRegisterClass(MVT::f128, &SystemZ::FP128BitRegClass);
105 if (Subtarget.hasVector()) {
106 addRegisterClass(MVT::v16i8, &SystemZ::VR128BitRegClass);
107 addRegisterClass(MVT::v8i16, &SystemZ::VR128BitRegClass);
108 addRegisterClass(MVT::v4i32, &SystemZ::VR128BitRegClass);
109 addRegisterClass(MVT::v2i64, &SystemZ::VR128BitRegClass);
110 addRegisterClass(MVT::v4f32, &SystemZ::VR128BitRegClass);
111 addRegisterClass(MVT::v2f64, &SystemZ::VR128BitRegClass);
114 // Compute derived properties from the register classes
115 computeRegisterProperties(Subtarget.getRegisterInfo());
117 // Set up special registers.
118 setStackPointerRegisterToSaveRestore(SystemZ::R15D);
120 // TODO: It may be better to default to latency-oriented scheduling, however
121 // LLVM's current latency-oriented scheduler can't handle physreg definitions
122 // such as SystemZ has with CC, so set this to the register-pressure
123 // scheduler, because it can.
124 setSchedulingPreference(Sched::RegPressure);
126 setBooleanContents(ZeroOrOneBooleanContent);
127 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
129 // Instructions are strings of 2-byte aligned 2-byte values.
130 setMinFunctionAlignment(2);
132 // Handle operations that are handled in a similar way for all types.
133 for (unsigned I = MVT::FIRST_INTEGER_VALUETYPE;
134 I <= MVT::LAST_FP_VALUETYPE;
136 MVT VT = MVT::SimpleValueType(I);
137 if (isTypeLegal(VT)) {
138 // Lower SET_CC into an IPM-based sequence.
139 setOperationAction(ISD::SETCC, VT, Custom);
141 // Expand SELECT(C, A, B) into SELECT_CC(X, 0, A, B, NE).
142 setOperationAction(ISD::SELECT, VT, Expand);
144 // Lower SELECT_CC and BR_CC into separate comparisons and branches.
145 setOperationAction(ISD::SELECT_CC, VT, Custom);
146 setOperationAction(ISD::BR_CC, VT, Custom);
150 // Expand jump table branches as address arithmetic followed by an
152 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
154 // Expand BRCOND into a BR_CC (see above).
155 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
157 // Handle integer types.
158 for (unsigned I = MVT::FIRST_INTEGER_VALUETYPE;
159 I <= MVT::LAST_INTEGER_VALUETYPE;
161 MVT VT = MVT::SimpleValueType(I);
162 if (isTypeLegal(VT)) {
163 // Expand individual DIV and REMs into DIVREMs.
164 setOperationAction(ISD::SDIV, VT, Expand);
165 setOperationAction(ISD::UDIV, VT, Expand);
166 setOperationAction(ISD::SREM, VT, Expand);
167 setOperationAction(ISD::UREM, VT, Expand);
168 setOperationAction(ISD::SDIVREM, VT, Custom);
169 setOperationAction(ISD::UDIVREM, VT, Custom);
171 // Lower ATOMIC_LOAD and ATOMIC_STORE into normal volatile loads and
172 // stores, putting a serialization instruction after the stores.
173 setOperationAction(ISD::ATOMIC_LOAD, VT, Custom);
174 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
176 // Lower ATOMIC_LOAD_SUB into ATOMIC_LOAD_ADD if LAA and LAAG are
177 // available, or if the operand is constant.
178 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
180 // Use POPCNT on z196 and above.
181 if (Subtarget.hasPopulationCount())
182 setOperationAction(ISD::CTPOP, VT, Custom);
184 setOperationAction(ISD::CTPOP, VT, Expand);
186 // No special instructions for these.
187 setOperationAction(ISD::CTTZ, VT, Expand);
188 setOperationAction(ISD::ROTR, VT, Expand);
190 // Use *MUL_LOHI where possible instead of MULH*.
191 setOperationAction(ISD::MULHS, VT, Expand);
192 setOperationAction(ISD::MULHU, VT, Expand);
193 setOperationAction(ISD::SMUL_LOHI, VT, Custom);
194 setOperationAction(ISD::UMUL_LOHI, VT, Custom);
196 // Only z196 and above have native support for conversions to unsigned.
197 if (!Subtarget.hasFPExtension())
198 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
202 // Type legalization will convert 8- and 16-bit atomic operations into
203 // forms that operate on i32s (but still keeping the original memory VT).
204 // Lower them into full i32 operations.
205 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Custom);
206 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Custom);
207 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom);
208 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Custom);
209 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Custom);
210 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Custom);
211 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Custom);
212 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Custom);
213 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Custom);
214 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Custom);
215 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Custom);
216 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
218 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
220 // Traps are legal, as we will convert them to "j .+2".
221 setOperationAction(ISD::TRAP, MVT::Other, Legal);
223 // z10 has instructions for signed but not unsigned FP conversion.
224 // Handle unsigned 32-bit types as signed 64-bit types.
225 if (!Subtarget.hasFPExtension()) {
226 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Promote);
227 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
230 // We have native support for a 64-bit CTLZ, via FLOGR.
231 setOperationAction(ISD::CTLZ, MVT::i32, Promote);
232 setOperationAction(ISD::CTLZ, MVT::i64, Legal);
234 // Give LowerOperation the chance to replace 64-bit ORs with subregs.
235 setOperationAction(ISD::OR, MVT::i64, Custom);
237 // FIXME: Can we support these natively?
238 setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand);
239 setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand);
240 setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand);
242 // We have native instructions for i8, i16 and i32 extensions, but not i1.
243 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
244 for (MVT VT : MVT::integer_valuetypes()) {
245 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
246 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
247 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
250 // Handle the various types of symbolic address.
251 setOperationAction(ISD::ConstantPool, PtrVT, Custom);
252 setOperationAction(ISD::GlobalAddress, PtrVT, Custom);
253 setOperationAction(ISD::GlobalTLSAddress, PtrVT, Custom);
254 setOperationAction(ISD::BlockAddress, PtrVT, Custom);
255 setOperationAction(ISD::JumpTable, PtrVT, Custom);
257 // We need to handle dynamic allocations specially because of the
258 // 160-byte area at the bottom of the stack.
259 setOperationAction(ISD::DYNAMIC_STACKALLOC, PtrVT, Custom);
260 setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, PtrVT, Custom);
262 // Use custom expanders so that we can force the function to use
264 setOperationAction(ISD::STACKSAVE, MVT::Other, Custom);
265 setOperationAction(ISD::STACKRESTORE, MVT::Other, Custom);
267 // Handle prefetches with PFD or PFDRL.
268 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
270 for (MVT VT : MVT::vector_valuetypes()) {
271 // Assume by default that all vector operations need to be expanded.
272 for (unsigned Opcode = 0; Opcode < ISD::BUILTIN_OP_END; ++Opcode)
273 if (getOperationAction(Opcode, VT) == Legal)
274 setOperationAction(Opcode, VT, Expand);
276 // Likewise all truncating stores and extending loads.
277 for (MVT InnerVT : MVT::vector_valuetypes()) {
278 setTruncStoreAction(VT, InnerVT, Expand);
279 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
280 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
281 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
284 if (isTypeLegal(VT)) {
285 // These operations are legal for anything that can be stored in a
286 // vector register, even if there is no native support for the format
287 // as such. In particular, we can do these for v4f32 even though there
288 // are no specific instructions for that format.
289 setOperationAction(ISD::LOAD, VT, Legal);
290 setOperationAction(ISD::STORE, VT, Legal);
291 setOperationAction(ISD::VSELECT, VT, Legal);
292 setOperationAction(ISD::BITCAST, VT, Legal);
293 setOperationAction(ISD::UNDEF, VT, Legal);
295 // Likewise, except that we need to replace the nodes with something
297 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
298 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
302 // Handle integer vector types.
303 for (MVT VT : MVT::integer_vector_valuetypes()) {
304 if (isTypeLegal(VT)) {
305 // These operations have direct equivalents.
306 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Legal);
307 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Legal);
308 setOperationAction(ISD::ADD, VT, Legal);
309 setOperationAction(ISD::SUB, VT, Legal);
310 if (VT != MVT::v2i64)
311 setOperationAction(ISD::MUL, VT, Legal);
312 setOperationAction(ISD::AND, VT, Legal);
313 setOperationAction(ISD::OR, VT, Legal);
314 setOperationAction(ISD::XOR, VT, Legal);
315 setOperationAction(ISD::CTPOP, VT, Custom);
316 setOperationAction(ISD::CTTZ, VT, Legal);
317 setOperationAction(ISD::CTLZ, VT, Legal);
319 // Convert a GPR scalar to a vector by inserting it into element 0.
320 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
322 // Use a series of unpacks for extensions.
323 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Custom);
324 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Custom);
326 // Detect shifts by a scalar amount and convert them into
328 setOperationAction(ISD::SHL, VT, Custom);
329 setOperationAction(ISD::SRA, VT, Custom);
330 setOperationAction(ISD::SRL, VT, Custom);
332 // At present ROTL isn't matched by DAGCombiner. ROTR should be
333 // converted into ROTL.
334 setOperationAction(ISD::ROTL, VT, Expand);
335 setOperationAction(ISD::ROTR, VT, Expand);
337 // Map SETCCs onto one of VCE, VCH or VCHL, swapping the operands
338 // and inverting the result as necessary.
339 setOperationAction(ISD::SETCC, VT, Custom);
343 if (Subtarget.hasVector()) {
344 // There should be no need to check for float types other than v2f64
345 // since <2 x f32> isn't a legal type.
346 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
347 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
348 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
349 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
352 // Handle floating-point types.
353 for (unsigned I = MVT::FIRST_FP_VALUETYPE;
354 I <= MVT::LAST_FP_VALUETYPE;
356 MVT VT = MVT::SimpleValueType(I);
357 if (isTypeLegal(VT)) {
358 // We can use FI for FRINT.
359 setOperationAction(ISD::FRINT, VT, Legal);
361 // We can use the extended form of FI for other rounding operations.
362 if (Subtarget.hasFPExtension()) {
363 setOperationAction(ISD::FNEARBYINT, VT, Legal);
364 setOperationAction(ISD::FFLOOR, VT, Legal);
365 setOperationAction(ISD::FCEIL, VT, Legal);
366 setOperationAction(ISD::FTRUNC, VT, Legal);
367 setOperationAction(ISD::FROUND, VT, Legal);
370 // No special instructions for these.
371 setOperationAction(ISD::FSIN, VT, Expand);
372 setOperationAction(ISD::FCOS, VT, Expand);
373 setOperationAction(ISD::FSINCOS, VT, Expand);
374 setOperationAction(ISD::FREM, VT, Expand);
375 setOperationAction(ISD::FPOW, VT, Expand);
379 // Handle floating-point vector types.
380 if (Subtarget.hasVector()) {
381 // Scalar-to-vector conversion is just a subreg.
382 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal);
383 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
385 // Some insertions and extractions can be done directly but others
386 // need to go via integers.
387 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
388 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
389 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
390 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
392 // These operations have direct equivalents.
393 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
394 setOperationAction(ISD::FNEG, MVT::v2f64, Legal);
395 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
396 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
397 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
398 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
399 setOperationAction(ISD::FABS, MVT::v2f64, Legal);
400 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
401 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
402 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
403 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
404 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
405 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
406 setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
409 // We have fused multiply-addition for f32 and f64 but not f128.
410 setOperationAction(ISD::FMA, MVT::f32, Legal);
411 setOperationAction(ISD::FMA, MVT::f64, Legal);
412 setOperationAction(ISD::FMA, MVT::f128, Expand);
414 // Needed so that we don't try to implement f128 constant loads using
415 // a load-and-extend of a f80 constant (in cases where the constant
416 // would fit in an f80).
417 for (MVT VT : MVT::fp_valuetypes())
418 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f80, Expand);
420 // Floating-point truncation and stores need to be done separately.
421 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
422 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
423 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
425 // We have 64-bit FPR<->GPR moves, but need special handling for
427 if (!Subtarget.hasVector()) {
428 setOperationAction(ISD::BITCAST, MVT::i32, Custom);
429 setOperationAction(ISD::BITCAST, MVT::f32, Custom);
432 // VASTART and VACOPY need to deal with the SystemZ-specific varargs
433 // structure, but VAEND is a no-op.
434 setOperationAction(ISD::VASTART, MVT::Other, Custom);
435 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
436 setOperationAction(ISD::VAEND, MVT::Other, Expand);
438 // Codes for which we want to perform some z-specific combinations.
439 setTargetDAGCombine(ISD::SIGN_EXTEND);
440 setTargetDAGCombine(ISD::STORE);
441 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
442 setTargetDAGCombine(ISD::FP_ROUND);
443 setTargetDAGCombine(ISD::BSWAP);
444 setTargetDAGCombine(ISD::SHL);
445 setTargetDAGCombine(ISD::SRA);
446 setTargetDAGCombine(ISD::SRL);
447 setTargetDAGCombine(ISD::ROTL);
449 // Handle intrinsics.
450 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
451 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
453 // We want to use MVC in preference to even a single load/store pair.
454 MaxStoresPerMemcpy = 0;
455 MaxStoresPerMemcpyOptSize = 0;
457 // The main memset sequence is a byte store followed by an MVC.
458 // Two STC or MV..I stores win over that, but the kind of fused stores
459 // generated by target-independent code don't when the byte value is
460 // variable. E.g. "STC <reg>;MHI <reg>,257;STH <reg>" is not better
461 // than "STC;MVC". Handle the choice in target-specific code instead.
462 MaxStoresPerMemset = 0;
463 MaxStoresPerMemsetOptSize = 0;
466 EVT SystemZTargetLowering::getSetCCResultType(const DataLayout &DL,
467 LLVMContext &, EVT VT) const {
470 return VT.changeVectorElementTypeToInteger();
473 bool SystemZTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
474 VT = VT.getScalarType();
479 switch (VT.getSimpleVT().SimpleTy) {
492 bool SystemZTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
493 // We can load zero using LZ?R and negative zero using LZ?R;LC?BR.
494 return Imm.isZero() || Imm.isNegZero();
497 bool SystemZTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
498 // We can use CGFI or CLGFI.
499 return isInt<32>(Imm) || isUInt<32>(Imm);
502 bool SystemZTargetLowering::isLegalAddImmediate(int64_t Imm) const {
503 // We can use ALGFI or SLGFI.
504 return isUInt<32>(Imm) || isUInt<32>(-Imm);
507 bool SystemZTargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
511 // Unaligned accesses should never be slower than the expanded version.
512 // We check specifically for aligned accesses in the few cases where
513 // they are required.
519 bool SystemZTargetLowering::isLegalAddressingMode(const DataLayout &DL,
520 const AddrMode &AM, Type *Ty,
522 // Punt on globals for now, although they can be used in limited
523 // RELATIVE LONG cases.
527 // Require a 20-bit signed offset.
528 if (!isInt<20>(AM.BaseOffs))
531 // Indexing is OK but no scale factor can be applied.
532 return AM.Scale == 0 || AM.Scale == 1;
535 bool SystemZTargetLowering::isFoldableMemAccessOffset(Instruction *I,
536 int64_t Offset) const {
537 // This only applies to z13.
538 if (!Subtarget.hasVector())
541 // * Use LDE instead of LE/LEY to avoid partial register
542 // dependencies (LDE only supports small offsets).
543 // * Utilize the vector registers to hold floating point
544 // values (vector load / store instructions only support small
547 assert (isa<LoadInst>(I) || isa<StoreInst>(I));
548 Type *MemAccessTy = (isa<LoadInst>(I) ? I->getType() :
549 I->getOperand(0)->getType());
550 if (!isUInt<12>(Offset) &&
551 (MemAccessTy->isFloatingPointTy() || MemAccessTy->isVectorTy()))
557 bool SystemZTargetLowering::isTruncateFree(Type *FromType, Type *ToType) const {
558 if (!FromType->isIntegerTy() || !ToType->isIntegerTy())
560 unsigned FromBits = FromType->getPrimitiveSizeInBits();
561 unsigned ToBits = ToType->getPrimitiveSizeInBits();
562 return FromBits > ToBits;
565 bool SystemZTargetLowering::isTruncateFree(EVT FromVT, EVT ToVT) const {
566 if (!FromVT.isInteger() || !ToVT.isInteger())
568 unsigned FromBits = FromVT.getSizeInBits();
569 unsigned ToBits = ToVT.getSizeInBits();
570 return FromBits > ToBits;
573 //===----------------------------------------------------------------------===//
574 // Inline asm support
575 //===----------------------------------------------------------------------===//
577 TargetLowering::ConstraintType
578 SystemZTargetLowering::getConstraintType(StringRef Constraint) const {
579 if (Constraint.size() == 1) {
580 switch (Constraint[0]) {
581 case 'a': // Address register
582 case 'd': // Data register (equivalent to 'r')
583 case 'f': // Floating-point register
584 case 'h': // High-part register
585 case 'r': // General-purpose register
586 return C_RegisterClass;
588 case 'Q': // Memory with base and unsigned 12-bit displacement
589 case 'R': // Likewise, plus an index
590 case 'S': // Memory with base and signed 20-bit displacement
591 case 'T': // Likewise, plus an index
592 case 'm': // Equivalent to 'T'.
595 case 'I': // Unsigned 8-bit constant
596 case 'J': // Unsigned 12-bit constant
597 case 'K': // Signed 16-bit constant
598 case 'L': // Signed 20-bit displacement (on all targets we support)
599 case 'M': // 0x7fffffff
606 return TargetLowering::getConstraintType(Constraint);
609 TargetLowering::ConstraintWeight SystemZTargetLowering::
610 getSingleConstraintMatchWeight(AsmOperandInfo &info,
611 const char *constraint) const {
612 ConstraintWeight weight = CW_Invalid;
613 Value *CallOperandVal = info.CallOperandVal;
614 // If we don't have a value, we can't do a match,
615 // but allow it at the lowest weight.
618 Type *type = CallOperandVal->getType();
619 // Look at the constraint type.
620 switch (*constraint) {
622 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
625 case 'a': // Address register
626 case 'd': // Data register (equivalent to 'r')
627 case 'h': // High-part register
628 case 'r': // General-purpose register
629 if (CallOperandVal->getType()->isIntegerTy())
630 weight = CW_Register;
633 case 'f': // Floating-point register
634 if (type->isFloatingPointTy())
635 weight = CW_Register;
638 case 'I': // Unsigned 8-bit constant
639 if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
640 if (isUInt<8>(C->getZExtValue()))
641 weight = CW_Constant;
644 case 'J': // Unsigned 12-bit constant
645 if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
646 if (isUInt<12>(C->getZExtValue()))
647 weight = CW_Constant;
650 case 'K': // Signed 16-bit constant
651 if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
652 if (isInt<16>(C->getSExtValue()))
653 weight = CW_Constant;
656 case 'L': // Signed 20-bit displacement (on all targets we support)
657 if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
658 if (isInt<20>(C->getSExtValue()))
659 weight = CW_Constant;
662 case 'M': // 0x7fffffff
663 if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
664 if (C->getZExtValue() == 0x7fffffff)
665 weight = CW_Constant;
671 // Parse a "{tNNN}" register constraint for which the register type "t"
672 // has already been verified. MC is the class associated with "t" and
673 // Map maps 0-based register numbers to LLVM register numbers.
674 static std::pair<unsigned, const TargetRegisterClass *>
675 parseRegisterNumber(StringRef Constraint, const TargetRegisterClass *RC,
676 const unsigned *Map) {
677 assert(*(Constraint.end()-1) == '}' && "Missing '}'");
678 if (isdigit(Constraint[2])) {
681 Constraint.slice(2, Constraint.size() - 1).getAsInteger(10, Index);
682 if (!Failed && Index < 16 && Map[Index])
683 return std::make_pair(Map[Index], RC);
685 return std::make_pair(0U, nullptr);
688 std::pair<unsigned, const TargetRegisterClass *>
689 SystemZTargetLowering::getRegForInlineAsmConstraint(
690 const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
691 if (Constraint.size() == 1) {
692 // GCC Constraint Letters
693 switch (Constraint[0]) {
695 case 'd': // Data register (equivalent to 'r')
696 case 'r': // General-purpose register
698 return std::make_pair(0U, &SystemZ::GR64BitRegClass);
699 else if (VT == MVT::i128)
700 return std::make_pair(0U, &SystemZ::GR128BitRegClass);
701 return std::make_pair(0U, &SystemZ::GR32BitRegClass);
703 case 'a': // Address register
705 return std::make_pair(0U, &SystemZ::ADDR64BitRegClass);
706 else if (VT == MVT::i128)
707 return std::make_pair(0U, &SystemZ::ADDR128BitRegClass);
708 return std::make_pair(0U, &SystemZ::ADDR32BitRegClass);
710 case 'h': // High-part register (an LLVM extension)
711 return std::make_pair(0U, &SystemZ::GRH32BitRegClass);
713 case 'f': // Floating-point register
715 return std::make_pair(0U, &SystemZ::FP64BitRegClass);
716 else if (VT == MVT::f128)
717 return std::make_pair(0U, &SystemZ::FP128BitRegClass);
718 return std::make_pair(0U, &SystemZ::FP32BitRegClass);
721 if (Constraint.size() > 0 && Constraint[0] == '{') {
722 // We need to override the default register parsing for GPRs and FPRs
723 // because the interpretation depends on VT. The internal names of
724 // the registers are also different from the external names
725 // (F0D and F0S instead of F0, etc.).
726 if (Constraint[1] == 'r') {
728 return parseRegisterNumber(Constraint, &SystemZ::GR32BitRegClass,
729 SystemZMC::GR32Regs);
731 return parseRegisterNumber(Constraint, &SystemZ::GR128BitRegClass,
732 SystemZMC::GR128Regs);
733 return parseRegisterNumber(Constraint, &SystemZ::GR64BitRegClass,
734 SystemZMC::GR64Regs);
736 if (Constraint[1] == 'f') {
738 return parseRegisterNumber(Constraint, &SystemZ::FP32BitRegClass,
739 SystemZMC::FP32Regs);
741 return parseRegisterNumber(Constraint, &SystemZ::FP128BitRegClass,
742 SystemZMC::FP128Regs);
743 return parseRegisterNumber(Constraint, &SystemZ::FP64BitRegClass,
744 SystemZMC::FP64Regs);
747 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
750 void SystemZTargetLowering::
751 LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
752 std::vector<SDValue> &Ops,
753 SelectionDAG &DAG) const {
754 // Only support length 1 constraints for now.
755 if (Constraint.length() == 1) {
756 switch (Constraint[0]) {
757 case 'I': // Unsigned 8-bit constant
758 if (auto *C = dyn_cast<ConstantSDNode>(Op))
759 if (isUInt<8>(C->getZExtValue()))
760 Ops.push_back(DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
764 case 'J': // Unsigned 12-bit constant
765 if (auto *C = dyn_cast<ConstantSDNode>(Op))
766 if (isUInt<12>(C->getZExtValue()))
767 Ops.push_back(DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
771 case 'K': // Signed 16-bit constant
772 if (auto *C = dyn_cast<ConstantSDNode>(Op))
773 if (isInt<16>(C->getSExtValue()))
774 Ops.push_back(DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
778 case 'L': // Signed 20-bit displacement (on all targets we support)
779 if (auto *C = dyn_cast<ConstantSDNode>(Op))
780 if (isInt<20>(C->getSExtValue()))
781 Ops.push_back(DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
785 case 'M': // 0x7fffffff
786 if (auto *C = dyn_cast<ConstantSDNode>(Op))
787 if (C->getZExtValue() == 0x7fffffff)
788 Ops.push_back(DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
793 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
796 //===----------------------------------------------------------------------===//
797 // Calling conventions
798 //===----------------------------------------------------------------------===//
800 #include "SystemZGenCallingConv.inc"
802 bool SystemZTargetLowering::allowTruncateForTailCall(Type *FromType,
803 Type *ToType) const {
804 return isTruncateFree(FromType, ToType);
807 bool SystemZTargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
808 return CI->isTailCall();
811 // We do not yet support 128-bit single-element vector types. If the user
812 // attempts to use such types as function argument or return type, prefer
813 // to error out instead of emitting code violating the ABI.
814 static void VerifyVectorType(MVT VT, EVT ArgVT) {
815 if (ArgVT.isVector() && !VT.isVector())
816 report_fatal_error("Unsupported vector argument or return type");
819 static void VerifyVectorTypes(const SmallVectorImpl<ISD::InputArg> &Ins) {
820 for (unsigned i = 0; i < Ins.size(); ++i)
821 VerifyVectorType(Ins[i].VT, Ins[i].ArgVT);
824 static void VerifyVectorTypes(const SmallVectorImpl<ISD::OutputArg> &Outs) {
825 for (unsigned i = 0; i < Outs.size(); ++i)
826 VerifyVectorType(Outs[i].VT, Outs[i].ArgVT);
829 // Value is a value that has been passed to us in the location described by VA
830 // (and so has type VA.getLocVT()). Convert Value to VA.getValVT(), chaining
831 // any loads onto Chain.
832 static SDValue convertLocVTToValVT(SelectionDAG &DAG, const SDLoc &DL,
833 CCValAssign &VA, SDValue Chain,
835 // If the argument has been promoted from a smaller type, insert an
836 // assertion to capture this.
837 if (VA.getLocInfo() == CCValAssign::SExt)
838 Value = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Value,
839 DAG.getValueType(VA.getValVT()));
840 else if (VA.getLocInfo() == CCValAssign::ZExt)
841 Value = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Value,
842 DAG.getValueType(VA.getValVT()));
845 Value = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Value);
846 else if (VA.getLocInfo() == CCValAssign::BCvt) {
847 // If this is a short vector argument loaded from the stack,
848 // extend from i64 to full vector size and then bitcast.
849 assert(VA.getLocVT() == MVT::i64);
850 assert(VA.getValVT().isVector());
851 Value = DAG.getBuildVector(MVT::v2i64, DL, {Value, DAG.getUNDEF(MVT::i64)});
852 Value = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Value);
854 assert(VA.getLocInfo() == CCValAssign::Full && "Unsupported getLocInfo");
858 // Value is a value of type VA.getValVT() that we need to copy into
859 // the location described by VA. Return a copy of Value converted to
860 // VA.getValVT(). The caller is responsible for handling indirect values.
861 static SDValue convertValVTToLocVT(SelectionDAG &DAG, const SDLoc &DL,
862 CCValAssign &VA, SDValue Value) {
863 switch (VA.getLocInfo()) {
864 case CCValAssign::SExt:
865 return DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Value);
866 case CCValAssign::ZExt:
867 return DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Value);
868 case CCValAssign::AExt:
869 return DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Value);
870 case CCValAssign::BCvt:
871 // If this is a short vector argument to be stored to the stack,
872 // bitcast to v2i64 and then extract first element.
873 assert(VA.getLocVT() == MVT::i64);
874 assert(VA.getValVT().isVector());
875 Value = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Value);
876 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VA.getLocVT(), Value,
877 DAG.getConstant(0, DL, MVT::i32));
878 case CCValAssign::Full:
881 llvm_unreachable("Unhandled getLocInfo()");
885 SDValue SystemZTargetLowering::LowerFormalArguments(
886 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
887 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
888 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
889 MachineFunction &MF = DAG.getMachineFunction();
890 MachineFrameInfo &MFI = MF.getFrameInfo();
891 MachineRegisterInfo &MRI = MF.getRegInfo();
892 SystemZMachineFunctionInfo *FuncInfo =
893 MF.getInfo<SystemZMachineFunctionInfo>();
895 static_cast<const SystemZFrameLowering *>(Subtarget.getFrameLowering());
896 EVT PtrVT = getPointerTy(DAG.getDataLayout());
898 // Detect unsupported vector argument types.
899 if (Subtarget.hasVector())
900 VerifyVectorTypes(Ins);
902 // Assign locations to all of the incoming arguments.
903 SmallVector<CCValAssign, 16> ArgLocs;
904 SystemZCCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
905 CCInfo.AnalyzeFormalArguments(Ins, CC_SystemZ);
907 unsigned NumFixedGPRs = 0;
908 unsigned NumFixedFPRs = 0;
909 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
911 CCValAssign &VA = ArgLocs[I];
912 EVT LocVT = VA.getLocVT();
914 // Arguments passed in registers
915 const TargetRegisterClass *RC;
916 switch (LocVT.getSimpleVT().SimpleTy) {
918 // Integers smaller than i64 should be promoted to i64.
919 llvm_unreachable("Unexpected argument type");
922 RC = &SystemZ::GR32BitRegClass;
926 RC = &SystemZ::GR64BitRegClass;
930 RC = &SystemZ::FP32BitRegClass;
934 RC = &SystemZ::FP64BitRegClass;
942 RC = &SystemZ::VR128BitRegClass;
946 unsigned VReg = MRI.createVirtualRegister(RC);
947 MRI.addLiveIn(VA.getLocReg(), VReg);
948 ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, LocVT);
950 assert(VA.isMemLoc() && "Argument not register or memory");
952 // Create the frame index object for this incoming parameter.
953 int FI = MFI.CreateFixedObject(LocVT.getSizeInBits() / 8,
954 VA.getLocMemOffset(), true);
956 // Create the SelectionDAG nodes corresponding to a load
957 // from this parameter. Unpromoted ints and floats are
958 // passed as right-justified 8-byte values.
959 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
960 if (VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::f32)
961 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN,
962 DAG.getIntPtrConstant(4, DL));
963 ArgValue = DAG.getLoad(LocVT, DL, Chain, FIN,
964 MachinePointerInfo::getFixedStack(MF, FI));
967 // Convert the value of the argument register into the value that's
969 if (VA.getLocInfo() == CCValAssign::Indirect) {
970 InVals.push_back(DAG.getLoad(VA.getValVT(), DL, Chain, ArgValue,
971 MachinePointerInfo()));
972 // If the original argument was split (e.g. i128), we need
973 // to load all parts of it here (using the same address).
974 unsigned ArgIndex = Ins[I].OrigArgIndex;
975 assert (Ins[I].PartOffset == 0);
976 while (I + 1 != E && Ins[I + 1].OrigArgIndex == ArgIndex) {
977 CCValAssign &PartVA = ArgLocs[I + 1];
978 unsigned PartOffset = Ins[I + 1].PartOffset;
979 SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, ArgValue,
980 DAG.getIntPtrConstant(PartOffset, DL));
981 InVals.push_back(DAG.getLoad(PartVA.getValVT(), DL, Chain, Address,
982 MachinePointerInfo()));
986 InVals.push_back(convertLocVTToValVT(DAG, DL, VA, Chain, ArgValue));
990 // Save the number of non-varargs registers for later use by va_start, etc.
991 FuncInfo->setVarArgsFirstGPR(NumFixedGPRs);
992 FuncInfo->setVarArgsFirstFPR(NumFixedFPRs);
994 // Likewise the address (in the form of a frame index) of where the
995 // first stack vararg would be. The 1-byte size here is arbitrary.
996 int64_t StackSize = CCInfo.getNextStackOffset();
997 FuncInfo->setVarArgsFrameIndex(MFI.CreateFixedObject(1, StackSize, true));
999 // ...and a similar frame index for the caller-allocated save area
1000 // that will be used to store the incoming registers.
1001 int64_t RegSaveOffset = TFL->getOffsetOfLocalArea();
1002 unsigned RegSaveIndex = MFI.CreateFixedObject(1, RegSaveOffset, true);
1003 FuncInfo->setRegSaveFrameIndex(RegSaveIndex);
1005 // Store the FPR varargs in the reserved frame slots. (We store the
1006 // GPRs as part of the prologue.)
1007 if (NumFixedFPRs < SystemZ::NumArgFPRs) {
1008 SDValue MemOps[SystemZ::NumArgFPRs];
1009 for (unsigned I = NumFixedFPRs; I < SystemZ::NumArgFPRs; ++I) {
1010 unsigned Offset = TFL->getRegSpillOffset(SystemZ::ArgFPRs[I]);
1011 int FI = MFI.CreateFixedObject(8, RegSaveOffset + Offset, true);
1012 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
1013 unsigned VReg = MF.addLiveIn(SystemZ::ArgFPRs[I],
1014 &SystemZ::FP64BitRegClass);
1015 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f64);
1016 MemOps[I] = DAG.getStore(ArgValue.getValue(1), DL, ArgValue, FIN,
1017 MachinePointerInfo::getFixedStack(MF, FI));
1019 // Join the stores, which are independent of one another.
1020 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
1021 makeArrayRef(&MemOps[NumFixedFPRs],
1022 SystemZ::NumArgFPRs-NumFixedFPRs));
1029 static bool canUseSiblingCall(const CCState &ArgCCInfo,
1030 SmallVectorImpl<CCValAssign> &ArgLocs,
1031 SmallVectorImpl<ISD::OutputArg> &Outs) {
1032 // Punt if there are any indirect or stack arguments, or if the call
1033 // needs the callee-saved argument register R6, or if the call uses
1034 // the callee-saved register arguments SwiftSelf and SwiftError.
1035 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
1036 CCValAssign &VA = ArgLocs[I];
1037 if (VA.getLocInfo() == CCValAssign::Indirect)
1041 unsigned Reg = VA.getLocReg();
1042 if (Reg == SystemZ::R6H || Reg == SystemZ::R6L || Reg == SystemZ::R6D)
1044 if (Outs[I].Flags.isSwiftSelf() || Outs[I].Flags.isSwiftError())
1051 SystemZTargetLowering::LowerCall(CallLoweringInfo &CLI,
1052 SmallVectorImpl<SDValue> &InVals) const {
1053 SelectionDAG &DAG = CLI.DAG;
1055 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
1056 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
1057 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
1058 SDValue Chain = CLI.Chain;
1059 SDValue Callee = CLI.Callee;
1060 bool &IsTailCall = CLI.IsTailCall;
1061 CallingConv::ID CallConv = CLI.CallConv;
1062 bool IsVarArg = CLI.IsVarArg;
1063 MachineFunction &MF = DAG.getMachineFunction();
1064 EVT PtrVT = getPointerTy(MF.getDataLayout());
1066 // Detect unsupported vector argument and return types.
1067 if (Subtarget.hasVector()) {
1068 VerifyVectorTypes(Outs);
1069 VerifyVectorTypes(Ins);
1072 // Analyze the operands of the call, assigning locations to each operand.
1073 SmallVector<CCValAssign, 16> ArgLocs;
1074 SystemZCCState ArgCCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
1075 ArgCCInfo.AnalyzeCallOperands(Outs, CC_SystemZ);
1077 // We don't support GuaranteedTailCallOpt, only automatically-detected
1079 if (IsTailCall && !canUseSiblingCall(ArgCCInfo, ArgLocs, Outs))
1082 // Get a count of how many bytes are to be pushed on the stack.
1083 unsigned NumBytes = ArgCCInfo.getNextStackOffset();
1085 // Mark the start of the call.
1087 Chain = DAG.getCALLSEQ_START(Chain,
1088 DAG.getConstant(NumBytes, DL, PtrVT, true),
1091 // Copy argument values to their designated locations.
1092 SmallVector<std::pair<unsigned, SDValue>, 9> RegsToPass;
1093 SmallVector<SDValue, 8> MemOpChains;
1095 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
1096 CCValAssign &VA = ArgLocs[I];
1097 SDValue ArgValue = OutVals[I];
1099 if (VA.getLocInfo() == CCValAssign::Indirect) {
1100 // Store the argument in a stack slot and pass its address.
1101 SDValue SpillSlot = DAG.CreateStackTemporary(Outs[I].ArgVT);
1102 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
1103 MemOpChains.push_back(
1104 DAG.getStore(Chain, DL, ArgValue, SpillSlot,
1105 MachinePointerInfo::getFixedStack(MF, FI)));
1106 // If the original argument was split (e.g. i128), we need
1107 // to store all parts of it here (and pass just one address).
1108 unsigned ArgIndex = Outs[I].OrigArgIndex;
1109 assert (Outs[I].PartOffset == 0);
1110 while (I + 1 != E && Outs[I + 1].OrigArgIndex == ArgIndex) {
1111 SDValue PartValue = OutVals[I + 1];
1112 unsigned PartOffset = Outs[I + 1].PartOffset;
1113 SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, SpillSlot,
1114 DAG.getIntPtrConstant(PartOffset, DL));
1115 MemOpChains.push_back(
1116 DAG.getStore(Chain, DL, PartValue, Address,
1117 MachinePointerInfo::getFixedStack(MF, FI)));
1120 ArgValue = SpillSlot;
1122 ArgValue = convertValVTToLocVT(DAG, DL, VA, ArgValue);
1125 // Queue up the argument copies and emit them at the end.
1126 RegsToPass.push_back(std::make_pair(VA.getLocReg(), ArgValue));
1128 assert(VA.isMemLoc() && "Argument not register or memory");
1130 // Work out the address of the stack slot. Unpromoted ints and
1131 // floats are passed as right-justified 8-byte values.
1132 if (!StackPtr.getNode())
1133 StackPtr = DAG.getCopyFromReg(Chain, DL, SystemZ::R15D, PtrVT);
1134 unsigned Offset = SystemZMC::CallFrameSize + VA.getLocMemOffset();
1135 if (VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::f32)
1137 SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr,
1138 DAG.getIntPtrConstant(Offset, DL));
1141 MemOpChains.push_back(
1142 DAG.getStore(Chain, DL, ArgValue, Address, MachinePointerInfo()));
1146 // Join the stores, which are independent of one another.
1147 if (!MemOpChains.empty())
1148 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
1150 // Accept direct calls by converting symbolic call addresses to the
1151 // associated Target* opcodes. Force %r1 to be used for indirect
1154 if (auto *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1155 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, PtrVT);
1156 Callee = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Callee);
1157 } else if (auto *E = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1158 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), PtrVT);
1159 Callee = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Callee);
1160 } else if (IsTailCall) {
1161 Chain = DAG.getCopyToReg(Chain, DL, SystemZ::R1D, Callee, Glue);
1162 Glue = Chain.getValue(1);
1163 Callee = DAG.getRegister(SystemZ::R1D, Callee.getValueType());
1166 // Build a sequence of copy-to-reg nodes, chained and glued together.
1167 for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I) {
1168 Chain = DAG.getCopyToReg(Chain, DL, RegsToPass[I].first,
1169 RegsToPass[I].second, Glue);
1170 Glue = Chain.getValue(1);
1173 // The first call operand is the chain and the second is the target address.
1174 SmallVector<SDValue, 8> Ops;
1175 Ops.push_back(Chain);
1176 Ops.push_back(Callee);
1178 // Add argument registers to the end of the list so that they are
1179 // known live into the call.
1180 for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I)
1181 Ops.push_back(DAG.getRegister(RegsToPass[I].first,
1182 RegsToPass[I].second.getValueType()));
1184 // Add a register mask operand representing the call-preserved registers.
1185 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
1186 const uint32_t *Mask = TRI->getCallPreservedMask(MF, CallConv);
1187 assert(Mask && "Missing call preserved mask for calling convention");
1188 Ops.push_back(DAG.getRegisterMask(Mask));
1190 // Glue the call to the argument copies, if any.
1192 Ops.push_back(Glue);
1195 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1197 return DAG.getNode(SystemZISD::SIBCALL, DL, NodeTys, Ops);
1198 Chain = DAG.getNode(SystemZISD::CALL, DL, NodeTys, Ops);
1199 Glue = Chain.getValue(1);
1201 // Mark the end of the call, which is glued to the call itself.
1202 Chain = DAG.getCALLSEQ_END(Chain,
1203 DAG.getConstant(NumBytes, DL, PtrVT, true),
1204 DAG.getConstant(0, DL, PtrVT, true),
1206 Glue = Chain.getValue(1);
1208 // Assign locations to each value returned by this call.
1209 SmallVector<CCValAssign, 16> RetLocs;
1210 CCState RetCCInfo(CallConv, IsVarArg, MF, RetLocs, *DAG.getContext());
1211 RetCCInfo.AnalyzeCallResult(Ins, RetCC_SystemZ);
1213 // Copy all of the result registers out of their specified physreg.
1214 for (unsigned I = 0, E = RetLocs.size(); I != E; ++I) {
1215 CCValAssign &VA = RetLocs[I];
1217 // Copy the value out, gluing the copy to the end of the call sequence.
1218 SDValue RetValue = DAG.getCopyFromReg(Chain, DL, VA.getLocReg(),
1219 VA.getLocVT(), Glue);
1220 Chain = RetValue.getValue(1);
1221 Glue = RetValue.getValue(2);
1223 // Convert the value of the return register into the value that's
1225 InVals.push_back(convertLocVTToValVT(DAG, DL, VA, Chain, RetValue));
1231 bool SystemZTargetLowering::
1232 CanLowerReturn(CallingConv::ID CallConv,
1233 MachineFunction &MF, bool isVarArg,
1234 const SmallVectorImpl<ISD::OutputArg> &Outs,
1235 LLVMContext &Context) const {
1236 // Detect unsupported vector return types.
1237 if (Subtarget.hasVector())
1238 VerifyVectorTypes(Outs);
1240 // Special case that we cannot easily detect in RetCC_SystemZ since
1241 // i128 is not a legal type.
1242 for (auto &Out : Outs)
1243 if (Out.ArgVT == MVT::i128)
1246 SmallVector<CCValAssign, 16> RetLocs;
1247 CCState RetCCInfo(CallConv, isVarArg, MF, RetLocs, Context);
1248 return RetCCInfo.CheckReturn(Outs, RetCC_SystemZ);
1252 SystemZTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
1254 const SmallVectorImpl<ISD::OutputArg> &Outs,
1255 const SmallVectorImpl<SDValue> &OutVals,
1256 const SDLoc &DL, SelectionDAG &DAG) const {
1257 MachineFunction &MF = DAG.getMachineFunction();
1259 // Detect unsupported vector return types.
1260 if (Subtarget.hasVector())
1261 VerifyVectorTypes(Outs);
1263 // Assign locations to each returned value.
1264 SmallVector<CCValAssign, 16> RetLocs;
1265 CCState RetCCInfo(CallConv, IsVarArg, MF, RetLocs, *DAG.getContext());
1266 RetCCInfo.AnalyzeReturn(Outs, RetCC_SystemZ);
1268 // Quick exit for void returns
1269 if (RetLocs.empty())
1270 return DAG.getNode(SystemZISD::RET_FLAG, DL, MVT::Other, Chain);
1272 // Copy the result values into the output registers.
1274 SmallVector<SDValue, 4> RetOps;
1275 RetOps.push_back(Chain);
1276 for (unsigned I = 0, E = RetLocs.size(); I != E; ++I) {
1277 CCValAssign &VA = RetLocs[I];
1278 SDValue RetValue = OutVals[I];
1280 // Make the return register live on exit.
1281 assert(VA.isRegLoc() && "Can only return in registers!");
1283 // Promote the value as required.
1284 RetValue = convertValVTToLocVT(DAG, DL, VA, RetValue);
1286 // Chain and glue the copies together.
1287 unsigned Reg = VA.getLocReg();
1288 Chain = DAG.getCopyToReg(Chain, DL, Reg, RetValue, Glue);
1289 Glue = Chain.getValue(1);
1290 RetOps.push_back(DAG.getRegister(Reg, VA.getLocVT()));
1293 // Update chain and glue.
1296 RetOps.push_back(Glue);
1298 return DAG.getNode(SystemZISD::RET_FLAG, DL, MVT::Other, RetOps);
1301 SDValue SystemZTargetLowering::prepareVolatileOrAtomicLoad(
1302 SDValue Chain, const SDLoc &DL, SelectionDAG &DAG) const {
1303 return DAG.getNode(SystemZISD::SERIALIZE, DL, MVT::Other, Chain);
1306 // Return true if Op is an intrinsic node with chain that returns the CC value
1307 // as its only (other) argument. Provide the associated SystemZISD opcode and
1308 // the mask of valid CC values if so.
1309 static bool isIntrinsicWithCCAndChain(SDValue Op, unsigned &Opcode,
1310 unsigned &CCValid) {
1311 unsigned Id = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
1313 case Intrinsic::s390_tbegin:
1314 Opcode = SystemZISD::TBEGIN;
1315 CCValid = SystemZ::CCMASK_TBEGIN;
1318 case Intrinsic::s390_tbegin_nofloat:
1319 Opcode = SystemZISD::TBEGIN_NOFLOAT;
1320 CCValid = SystemZ::CCMASK_TBEGIN;
1323 case Intrinsic::s390_tend:
1324 Opcode = SystemZISD::TEND;
1325 CCValid = SystemZ::CCMASK_TEND;
1333 // Return true if Op is an intrinsic node without chain that returns the
1334 // CC value as its final argument. Provide the associated SystemZISD
1335 // opcode and the mask of valid CC values if so.
1336 static bool isIntrinsicWithCC(SDValue Op, unsigned &Opcode, unsigned &CCValid) {
1337 unsigned Id = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1339 case Intrinsic::s390_vpkshs:
1340 case Intrinsic::s390_vpksfs:
1341 case Intrinsic::s390_vpksgs:
1342 Opcode = SystemZISD::PACKS_CC;
1343 CCValid = SystemZ::CCMASK_VCMP;
1346 case Intrinsic::s390_vpklshs:
1347 case Intrinsic::s390_vpklsfs:
1348 case Intrinsic::s390_vpklsgs:
1349 Opcode = SystemZISD::PACKLS_CC;
1350 CCValid = SystemZ::CCMASK_VCMP;
1353 case Intrinsic::s390_vceqbs:
1354 case Intrinsic::s390_vceqhs:
1355 case Intrinsic::s390_vceqfs:
1356 case Intrinsic::s390_vceqgs:
1357 Opcode = SystemZISD::VICMPES;
1358 CCValid = SystemZ::CCMASK_VCMP;
1361 case Intrinsic::s390_vchbs:
1362 case Intrinsic::s390_vchhs:
1363 case Intrinsic::s390_vchfs:
1364 case Intrinsic::s390_vchgs:
1365 Opcode = SystemZISD::VICMPHS;
1366 CCValid = SystemZ::CCMASK_VCMP;
1369 case Intrinsic::s390_vchlbs:
1370 case Intrinsic::s390_vchlhs:
1371 case Intrinsic::s390_vchlfs:
1372 case Intrinsic::s390_vchlgs:
1373 Opcode = SystemZISD::VICMPHLS;
1374 CCValid = SystemZ::CCMASK_VCMP;
1377 case Intrinsic::s390_vtm:
1378 Opcode = SystemZISD::VTM;
1379 CCValid = SystemZ::CCMASK_VCMP;
1382 case Intrinsic::s390_vfaebs:
1383 case Intrinsic::s390_vfaehs:
1384 case Intrinsic::s390_vfaefs:
1385 Opcode = SystemZISD::VFAE_CC;
1386 CCValid = SystemZ::CCMASK_ANY;
1389 case Intrinsic::s390_vfaezbs:
1390 case Intrinsic::s390_vfaezhs:
1391 case Intrinsic::s390_vfaezfs:
1392 Opcode = SystemZISD::VFAEZ_CC;
1393 CCValid = SystemZ::CCMASK_ANY;
1396 case Intrinsic::s390_vfeebs:
1397 case Intrinsic::s390_vfeehs:
1398 case Intrinsic::s390_vfeefs:
1399 Opcode = SystemZISD::VFEE_CC;
1400 CCValid = SystemZ::CCMASK_ANY;
1403 case Intrinsic::s390_vfeezbs:
1404 case Intrinsic::s390_vfeezhs:
1405 case Intrinsic::s390_vfeezfs:
1406 Opcode = SystemZISD::VFEEZ_CC;
1407 CCValid = SystemZ::CCMASK_ANY;
1410 case Intrinsic::s390_vfenebs:
1411 case Intrinsic::s390_vfenehs:
1412 case Intrinsic::s390_vfenefs:
1413 Opcode = SystemZISD::VFENE_CC;
1414 CCValid = SystemZ::CCMASK_ANY;
1417 case Intrinsic::s390_vfenezbs:
1418 case Intrinsic::s390_vfenezhs:
1419 case Intrinsic::s390_vfenezfs:
1420 Opcode = SystemZISD::VFENEZ_CC;
1421 CCValid = SystemZ::CCMASK_ANY;
1424 case Intrinsic::s390_vistrbs:
1425 case Intrinsic::s390_vistrhs:
1426 case Intrinsic::s390_vistrfs:
1427 Opcode = SystemZISD::VISTR_CC;
1428 CCValid = SystemZ::CCMASK_0 | SystemZ::CCMASK_3;
1431 case Intrinsic::s390_vstrcbs:
1432 case Intrinsic::s390_vstrchs:
1433 case Intrinsic::s390_vstrcfs:
1434 Opcode = SystemZISD::VSTRC_CC;
1435 CCValid = SystemZ::CCMASK_ANY;
1438 case Intrinsic::s390_vstrczbs:
1439 case Intrinsic::s390_vstrczhs:
1440 case Intrinsic::s390_vstrczfs:
1441 Opcode = SystemZISD::VSTRCZ_CC;
1442 CCValid = SystemZ::CCMASK_ANY;
1445 case Intrinsic::s390_vfcedbs:
1446 Opcode = SystemZISD::VFCMPES;
1447 CCValid = SystemZ::CCMASK_VCMP;
1450 case Intrinsic::s390_vfchdbs:
1451 Opcode = SystemZISD::VFCMPHS;
1452 CCValid = SystemZ::CCMASK_VCMP;
1455 case Intrinsic::s390_vfchedbs:
1456 Opcode = SystemZISD::VFCMPHES;
1457 CCValid = SystemZ::CCMASK_VCMP;
1460 case Intrinsic::s390_vftcidb:
1461 Opcode = SystemZISD::VFTCI;
1462 CCValid = SystemZ::CCMASK_VCMP;
1465 case Intrinsic::s390_tdc:
1466 Opcode = SystemZISD::TDC;
1467 CCValid = SystemZ::CCMASK_TDC;
1475 // Emit an intrinsic with chain with a glued value instead of its CC result.
1476 static SDValue emitIntrinsicWithChainAndGlue(SelectionDAG &DAG, SDValue Op,
1478 // Copy all operands except the intrinsic ID.
1479 unsigned NumOps = Op.getNumOperands();
1480 SmallVector<SDValue, 6> Ops;
1481 Ops.reserve(NumOps - 1);
1482 Ops.push_back(Op.getOperand(0));
1483 for (unsigned I = 2; I < NumOps; ++I)
1484 Ops.push_back(Op.getOperand(I));
1486 assert(Op->getNumValues() == 2 && "Expected only CC result and chain");
1487 SDVTList RawVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1488 SDValue Intr = DAG.getNode(Opcode, SDLoc(Op), RawVTs, Ops);
1489 SDValue OldChain = SDValue(Op.getNode(), 1);
1490 SDValue NewChain = SDValue(Intr.getNode(), 0);
1491 DAG.ReplaceAllUsesOfValueWith(OldChain, NewChain);
1495 // Emit an intrinsic with a glued value instead of its CC result.
1496 static SDValue emitIntrinsicWithGlue(SelectionDAG &DAG, SDValue Op,
1498 // Copy all operands except the intrinsic ID.
1499 unsigned NumOps = Op.getNumOperands();
1500 SmallVector<SDValue, 6> Ops;
1501 Ops.reserve(NumOps - 1);
1502 for (unsigned I = 1; I < NumOps; ++I)
1503 Ops.push_back(Op.getOperand(I));
1505 if (Op->getNumValues() == 1)
1506 return DAG.getNode(Opcode, SDLoc(Op), MVT::Glue, Ops);
1507 assert(Op->getNumValues() == 2 && "Expected exactly one non-CC result");
1508 SDVTList RawVTs = DAG.getVTList(Op->getValueType(0), MVT::Glue);
1509 return DAG.getNode(Opcode, SDLoc(Op), RawVTs, Ops);
1512 // CC is a comparison that will be implemented using an integer or
1513 // floating-point comparison. Return the condition code mask for
1514 // a branch on true. In the integer case, CCMASK_CMP_UO is set for
1515 // unsigned comparisons and clear for signed ones. In the floating-point
1516 // case, CCMASK_CMP_UO has its normal mask meaning (unordered).
1517 static unsigned CCMaskForCondCode(ISD::CondCode CC) {
1519 case ISD::SET##X: return SystemZ::CCMASK_CMP_##X; \
1520 case ISD::SETO##X: return SystemZ::CCMASK_CMP_##X; \
1521 case ISD::SETU##X: return SystemZ::CCMASK_CMP_UO | SystemZ::CCMASK_CMP_##X
1525 llvm_unreachable("Invalid integer condition!");
1534 case ISD::SETO: return SystemZ::CCMASK_CMP_O;
1535 case ISD::SETUO: return SystemZ::CCMASK_CMP_UO;
1540 // Return a sequence for getting a 1 from an IPM result when CC has a
1541 // value in CCMask and a 0 when CC has a value in CCValid & ~CCMask.
1542 // The handling of CC values outside CCValid doesn't matter.
1543 static IPMConversion getIPMConversion(unsigned CCValid, unsigned CCMask) {
1544 // Deal with cases where the result can be taken directly from a bit
1545 // of the IPM result.
1546 if (CCMask == (CCValid & (SystemZ::CCMASK_1 | SystemZ::CCMASK_3)))
1547 return IPMConversion(0, 0, SystemZ::IPM_CC);
1548 if (CCMask == (CCValid & (SystemZ::CCMASK_2 | SystemZ::CCMASK_3)))
1549 return IPMConversion(0, 0, SystemZ::IPM_CC + 1);
1551 // Deal with cases where we can add a value to force the sign bit
1552 // to contain the right value. Putting the bit in 31 means we can
1553 // use SRL rather than RISBG(L), and also makes it easier to get a
1554 // 0/-1 value, so it has priority over the other tests below.
1556 // These sequences rely on the fact that the upper two bits of the
1557 // IPM result are zero.
1558 uint64_t TopBit = uint64_t(1) << 31;
1559 if (CCMask == (CCValid & SystemZ::CCMASK_0))
1560 return IPMConversion(0, -(1 << SystemZ::IPM_CC), 31);
1561 if (CCMask == (CCValid & (SystemZ::CCMASK_0 | SystemZ::CCMASK_1)))
1562 return IPMConversion(0, -(2 << SystemZ::IPM_CC), 31);
1563 if (CCMask == (CCValid & (SystemZ::CCMASK_0
1565 | SystemZ::CCMASK_2)))
1566 return IPMConversion(0, -(3 << SystemZ::IPM_CC), 31);
1567 if (CCMask == (CCValid & SystemZ::CCMASK_3))
1568 return IPMConversion(0, TopBit - (3 << SystemZ::IPM_CC), 31);
1569 if (CCMask == (CCValid & (SystemZ::CCMASK_1
1571 | SystemZ::CCMASK_3)))
1572 return IPMConversion(0, TopBit - (1 << SystemZ::IPM_CC), 31);
1574 // Next try inverting the value and testing a bit. 0/1 could be
1575 // handled this way too, but we dealt with that case above.
1576 if (CCMask == (CCValid & (SystemZ::CCMASK_0 | SystemZ::CCMASK_2)))
1577 return IPMConversion(-1, 0, SystemZ::IPM_CC);
1579 // Handle cases where adding a value forces a non-sign bit to contain
1581 if (CCMask == (CCValid & (SystemZ::CCMASK_1 | SystemZ::CCMASK_2)))
1582 return IPMConversion(0, 1 << SystemZ::IPM_CC, SystemZ::IPM_CC + 1);
1583 if (CCMask == (CCValid & (SystemZ::CCMASK_0 | SystemZ::CCMASK_3)))
1584 return IPMConversion(0, -(1 << SystemZ::IPM_CC), SystemZ::IPM_CC + 1);
1586 // The remaining cases are 1, 2, 0/1/3 and 0/2/3. All these are
1587 // can be done by inverting the low CC bit and applying one of the
1588 // sign-based extractions above.
1589 if (CCMask == (CCValid & SystemZ::CCMASK_1))
1590 return IPMConversion(1 << SystemZ::IPM_CC, -(1 << SystemZ::IPM_CC), 31);
1591 if (CCMask == (CCValid & SystemZ::CCMASK_2))
1592 return IPMConversion(1 << SystemZ::IPM_CC,
1593 TopBit - (3 << SystemZ::IPM_CC), 31);
1594 if (CCMask == (CCValid & (SystemZ::CCMASK_0
1596 | SystemZ::CCMASK_3)))
1597 return IPMConversion(1 << SystemZ::IPM_CC, -(3 << SystemZ::IPM_CC), 31);
1598 if (CCMask == (CCValid & (SystemZ::CCMASK_0
1600 | SystemZ::CCMASK_3)))
1601 return IPMConversion(1 << SystemZ::IPM_CC,
1602 TopBit - (1 << SystemZ::IPM_CC), 31);
1604 llvm_unreachable("Unexpected CC combination");
1607 // If C can be converted to a comparison against zero, adjust the operands
1609 static void adjustZeroCmp(SelectionDAG &DAG, const SDLoc &DL, Comparison &C) {
1610 if (C.ICmpType == SystemZICMP::UnsignedOnly)
1613 auto *ConstOp1 = dyn_cast<ConstantSDNode>(C.Op1.getNode());
1617 int64_t Value = ConstOp1->getSExtValue();
1618 if ((Value == -1 && C.CCMask == SystemZ::CCMASK_CMP_GT) ||
1619 (Value == -1 && C.CCMask == SystemZ::CCMASK_CMP_LE) ||
1620 (Value == 1 && C.CCMask == SystemZ::CCMASK_CMP_LT) ||
1621 (Value == 1 && C.CCMask == SystemZ::CCMASK_CMP_GE)) {
1622 C.CCMask ^= SystemZ::CCMASK_CMP_EQ;
1623 C.Op1 = DAG.getConstant(0, DL, C.Op1.getValueType());
1627 // If a comparison described by C is suitable for CLI(Y), CHHSI or CLHHSI,
1628 // adjust the operands as necessary.
1629 static void adjustSubwordCmp(SelectionDAG &DAG, const SDLoc &DL,
1631 // For us to make any changes, it must a comparison between a single-use
1632 // load and a constant.
1633 if (!C.Op0.hasOneUse() ||
1634 C.Op0.getOpcode() != ISD::LOAD ||
1635 C.Op1.getOpcode() != ISD::Constant)
1638 // We must have an 8- or 16-bit load.
1639 auto *Load = cast<LoadSDNode>(C.Op0);
1640 unsigned NumBits = Load->getMemoryVT().getStoreSizeInBits();
1641 if (NumBits != 8 && NumBits != 16)
1644 // The load must be an extending one and the constant must be within the
1645 // range of the unextended value.
1646 auto *ConstOp1 = cast<ConstantSDNode>(C.Op1);
1647 uint64_t Value = ConstOp1->getZExtValue();
1648 uint64_t Mask = (1 << NumBits) - 1;
1649 if (Load->getExtensionType() == ISD::SEXTLOAD) {
1650 // Make sure that ConstOp1 is in range of C.Op0.
1651 int64_t SignedValue = ConstOp1->getSExtValue();
1652 if (uint64_t(SignedValue) + (uint64_t(1) << (NumBits - 1)) > Mask)
1654 if (C.ICmpType != SystemZICMP::SignedOnly) {
1655 // Unsigned comparison between two sign-extended values is equivalent
1656 // to unsigned comparison between two zero-extended values.
1658 } else if (NumBits == 8) {
1659 // Try to treat the comparison as unsigned, so that we can use CLI.
1660 // Adjust CCMask and Value as necessary.
1661 if (Value == 0 && C.CCMask == SystemZ::CCMASK_CMP_LT)
1662 // Test whether the high bit of the byte is set.
1663 Value = 127, C.CCMask = SystemZ::CCMASK_CMP_GT;
1664 else if (Value == 0 && C.CCMask == SystemZ::CCMASK_CMP_GE)
1665 // Test whether the high bit of the byte is clear.
1666 Value = 128, C.CCMask = SystemZ::CCMASK_CMP_LT;
1668 // No instruction exists for this combination.
1670 C.ICmpType = SystemZICMP::UnsignedOnly;
1672 } else if (Load->getExtensionType() == ISD::ZEXTLOAD) {
1675 // If the constant is in range, we can use any comparison.
1676 C.ICmpType = SystemZICMP::Any;
1680 // Make sure that the first operand is an i32 of the right extension type.
1681 ISD::LoadExtType ExtType = (C.ICmpType == SystemZICMP::SignedOnly ?
1684 if (C.Op0.getValueType() != MVT::i32 ||
1685 Load->getExtensionType() != ExtType)
1686 C.Op0 = DAG.getExtLoad(ExtType, SDLoc(Load), MVT::i32, Load->getChain(),
1687 Load->getBasePtr(), Load->getPointerInfo(),
1688 Load->getMemoryVT(), Load->getAlignment(),
1689 Load->getMemOperand()->getFlags());
1691 // Make sure that the second operand is an i32 with the right value.
1692 if (C.Op1.getValueType() != MVT::i32 ||
1693 Value != ConstOp1->getZExtValue())
1694 C.Op1 = DAG.getConstant(Value, DL, MVT::i32);
1697 // Return true if Op is either an unextended load, or a load suitable
1698 // for integer register-memory comparisons of type ICmpType.
1699 static bool isNaturalMemoryOperand(SDValue Op, unsigned ICmpType) {
1700 auto *Load = dyn_cast<LoadSDNode>(Op.getNode());
1702 // There are no instructions to compare a register with a memory byte.
1703 if (Load->getMemoryVT() == MVT::i8)
1705 // Otherwise decide on extension type.
1706 switch (Load->getExtensionType()) {
1707 case ISD::NON_EXTLOAD:
1710 return ICmpType != SystemZICMP::UnsignedOnly;
1712 return ICmpType != SystemZICMP::SignedOnly;
1720 // Return true if it is better to swap the operands of C.
1721 static bool shouldSwapCmpOperands(const Comparison &C) {
1722 // Leave f128 comparisons alone, since they have no memory forms.
1723 if (C.Op0.getValueType() == MVT::f128)
1726 // Always keep a floating-point constant second, since comparisons with
1727 // zero can use LOAD TEST and comparisons with other constants make a
1728 // natural memory operand.
1729 if (isa<ConstantFPSDNode>(C.Op1))
1732 // Never swap comparisons with zero since there are many ways to optimize
1734 auto *ConstOp1 = dyn_cast<ConstantSDNode>(C.Op1);
1735 if (ConstOp1 && ConstOp1->getZExtValue() == 0)
1738 // Also keep natural memory operands second if the loaded value is
1739 // only used here. Several comparisons have memory forms.
1740 if (isNaturalMemoryOperand(C.Op1, C.ICmpType) && C.Op1.hasOneUse())
1743 // Look for cases where Cmp0 is a single-use load and Cmp1 isn't.
1744 // In that case we generally prefer the memory to be second.
1745 if (isNaturalMemoryOperand(C.Op0, C.ICmpType) && C.Op0.hasOneUse()) {
1746 // The only exceptions are when the second operand is a constant and
1747 // we can use things like CHHSI.
1750 // The unsigned memory-immediate instructions can handle 16-bit
1751 // unsigned integers.
1752 if (C.ICmpType != SystemZICMP::SignedOnly &&
1753 isUInt<16>(ConstOp1->getZExtValue()))
1755 // The signed memory-immediate instructions can handle 16-bit
1757 if (C.ICmpType != SystemZICMP::UnsignedOnly &&
1758 isInt<16>(ConstOp1->getSExtValue()))
1763 // Try to promote the use of CGFR and CLGFR.
1764 unsigned Opcode0 = C.Op0.getOpcode();
1765 if (C.ICmpType != SystemZICMP::UnsignedOnly && Opcode0 == ISD::SIGN_EXTEND)
1767 if (C.ICmpType != SystemZICMP::SignedOnly && Opcode0 == ISD::ZERO_EXTEND)
1769 if (C.ICmpType != SystemZICMP::SignedOnly &&
1770 Opcode0 == ISD::AND &&
1771 C.Op0.getOperand(1).getOpcode() == ISD::Constant &&
1772 cast<ConstantSDNode>(C.Op0.getOperand(1))->getZExtValue() == 0xffffffff)
1778 // Return a version of comparison CC mask CCMask in which the LT and GT
1779 // actions are swapped.
1780 static unsigned reverseCCMask(unsigned CCMask) {
1781 return ((CCMask & SystemZ::CCMASK_CMP_EQ) |
1782 (CCMask & SystemZ::CCMASK_CMP_GT ? SystemZ::CCMASK_CMP_LT : 0) |
1783 (CCMask & SystemZ::CCMASK_CMP_LT ? SystemZ::CCMASK_CMP_GT : 0) |
1784 (CCMask & SystemZ::CCMASK_CMP_UO));
1787 // Check whether C tests for equality between X and Y and whether X - Y
1788 // or Y - X is also computed. In that case it's better to compare the
1789 // result of the subtraction against zero.
1790 static void adjustForSubtraction(SelectionDAG &DAG, const SDLoc &DL,
1792 if (C.CCMask == SystemZ::CCMASK_CMP_EQ ||
1793 C.CCMask == SystemZ::CCMASK_CMP_NE) {
1794 for (auto I = C.Op0->use_begin(), E = C.Op0->use_end(); I != E; ++I) {
1796 if (N->getOpcode() == ISD::SUB &&
1797 ((N->getOperand(0) == C.Op0 && N->getOperand(1) == C.Op1) ||
1798 (N->getOperand(0) == C.Op1 && N->getOperand(1) == C.Op0))) {
1799 C.Op0 = SDValue(N, 0);
1800 C.Op1 = DAG.getConstant(0, DL, N->getValueType(0));
1807 // Check whether C compares a floating-point value with zero and if that
1808 // floating-point value is also negated. In this case we can use the
1809 // negation to set CC, so avoiding separate LOAD AND TEST and
1810 // LOAD (NEGATIVE/COMPLEMENT) instructions.
1811 static void adjustForFNeg(Comparison &C) {
1812 auto *C1 = dyn_cast<ConstantFPSDNode>(C.Op1);
1813 if (C1 && C1->isZero()) {
1814 for (auto I = C.Op0->use_begin(), E = C.Op0->use_end(); I != E; ++I) {
1816 if (N->getOpcode() == ISD::FNEG) {
1817 C.Op0 = SDValue(N, 0);
1818 C.CCMask = reverseCCMask(C.CCMask);
1825 // Check whether C compares (shl X, 32) with 0 and whether X is
1826 // also sign-extended. In that case it is better to test the result
1827 // of the sign extension using LTGFR.
1829 // This case is important because InstCombine transforms a comparison
1830 // with (sext (trunc X)) into a comparison with (shl X, 32).
1831 static void adjustForLTGFR(Comparison &C) {
1832 // Check for a comparison between (shl X, 32) and 0.
1833 if (C.Op0.getOpcode() == ISD::SHL &&
1834 C.Op0.getValueType() == MVT::i64 &&
1835 C.Op1.getOpcode() == ISD::Constant &&
1836 cast<ConstantSDNode>(C.Op1)->getZExtValue() == 0) {
1837 auto *C1 = dyn_cast<ConstantSDNode>(C.Op0.getOperand(1));
1838 if (C1 && C1->getZExtValue() == 32) {
1839 SDValue ShlOp0 = C.Op0.getOperand(0);
1840 // See whether X has any SIGN_EXTEND_INREG uses.
1841 for (auto I = ShlOp0->use_begin(), E = ShlOp0->use_end(); I != E; ++I) {
1843 if (N->getOpcode() == ISD::SIGN_EXTEND_INREG &&
1844 cast<VTSDNode>(N->getOperand(1))->getVT() == MVT::i32) {
1845 C.Op0 = SDValue(N, 0);
1853 // If C compares the truncation of an extending load, try to compare
1854 // the untruncated value instead. This exposes more opportunities to
1856 static void adjustICmpTruncate(SelectionDAG &DAG, const SDLoc &DL,
1858 if (C.Op0.getOpcode() == ISD::TRUNCATE &&
1859 C.Op0.getOperand(0).getOpcode() == ISD::LOAD &&
1860 C.Op1.getOpcode() == ISD::Constant &&
1861 cast<ConstantSDNode>(C.Op1)->getZExtValue() == 0) {
1862 auto *L = cast<LoadSDNode>(C.Op0.getOperand(0));
1863 if (L->getMemoryVT().getStoreSizeInBits() <= C.Op0.getValueSizeInBits()) {
1864 unsigned Type = L->getExtensionType();
1865 if ((Type == ISD::ZEXTLOAD && C.ICmpType != SystemZICMP::SignedOnly) ||
1866 (Type == ISD::SEXTLOAD && C.ICmpType != SystemZICMP::UnsignedOnly)) {
1867 C.Op0 = C.Op0.getOperand(0);
1868 C.Op1 = DAG.getConstant(0, DL, C.Op0.getValueType());
1874 // Return true if shift operation N has an in-range constant shift value.
1875 // Store it in ShiftVal if so.
1876 static bool isSimpleShift(SDValue N, unsigned &ShiftVal) {
1877 auto *Shift = dyn_cast<ConstantSDNode>(N.getOperand(1));
1881 uint64_t Amount = Shift->getZExtValue();
1882 if (Amount >= N.getValueSizeInBits())
1889 // Check whether an AND with Mask is suitable for a TEST UNDER MASK
1890 // instruction and whether the CC value is descriptive enough to handle
1891 // a comparison of type Opcode between the AND result and CmpVal.
1892 // CCMask says which comparison result is being tested and BitSize is
1893 // the number of bits in the operands. If TEST UNDER MASK can be used,
1894 // return the corresponding CC mask, otherwise return 0.
1895 static unsigned getTestUnderMaskCond(unsigned BitSize, unsigned CCMask,
1896 uint64_t Mask, uint64_t CmpVal,
1897 unsigned ICmpType) {
1898 assert(Mask != 0 && "ANDs with zero should have been removed by now");
1900 // Check whether the mask is suitable for TMHH, TMHL, TMLH or TMLL.
1901 if (!SystemZ::isImmLL(Mask) && !SystemZ::isImmLH(Mask) &&
1902 !SystemZ::isImmHL(Mask) && !SystemZ::isImmHH(Mask))
1905 // Work out the masks for the lowest and highest bits.
1906 unsigned HighShift = 63 - countLeadingZeros(Mask);
1907 uint64_t High = uint64_t(1) << HighShift;
1908 uint64_t Low = uint64_t(1) << countTrailingZeros(Mask);
1910 // Signed ordered comparisons are effectively unsigned if the sign
1912 bool EffectivelyUnsigned = (ICmpType != SystemZICMP::SignedOnly);
1914 // Check for equality comparisons with 0, or the equivalent.
1916 if (CCMask == SystemZ::CCMASK_CMP_EQ)
1917 return SystemZ::CCMASK_TM_ALL_0;
1918 if (CCMask == SystemZ::CCMASK_CMP_NE)
1919 return SystemZ::CCMASK_TM_SOME_1;
1921 if (EffectivelyUnsigned && CmpVal > 0 && CmpVal <= Low) {
1922 if (CCMask == SystemZ::CCMASK_CMP_LT)
1923 return SystemZ::CCMASK_TM_ALL_0;
1924 if (CCMask == SystemZ::CCMASK_CMP_GE)
1925 return SystemZ::CCMASK_TM_SOME_1;
1927 if (EffectivelyUnsigned && CmpVal < Low) {
1928 if (CCMask == SystemZ::CCMASK_CMP_LE)
1929 return SystemZ::CCMASK_TM_ALL_0;
1930 if (CCMask == SystemZ::CCMASK_CMP_GT)
1931 return SystemZ::CCMASK_TM_SOME_1;
1934 // Check for equality comparisons with the mask, or the equivalent.
1935 if (CmpVal == Mask) {
1936 if (CCMask == SystemZ::CCMASK_CMP_EQ)
1937 return SystemZ::CCMASK_TM_ALL_1;
1938 if (CCMask == SystemZ::CCMASK_CMP_NE)
1939 return SystemZ::CCMASK_TM_SOME_0;
1941 if (EffectivelyUnsigned && CmpVal >= Mask - Low && CmpVal < Mask) {
1942 if (CCMask == SystemZ::CCMASK_CMP_GT)
1943 return SystemZ::CCMASK_TM_ALL_1;
1944 if (CCMask == SystemZ::CCMASK_CMP_LE)
1945 return SystemZ::CCMASK_TM_SOME_0;
1947 if (EffectivelyUnsigned && CmpVal > Mask - Low && CmpVal <= Mask) {
1948 if (CCMask == SystemZ::CCMASK_CMP_GE)
1949 return SystemZ::CCMASK_TM_ALL_1;
1950 if (CCMask == SystemZ::CCMASK_CMP_LT)
1951 return SystemZ::CCMASK_TM_SOME_0;
1954 // Check for ordered comparisons with the top bit.
1955 if (EffectivelyUnsigned && CmpVal >= Mask - High && CmpVal < High) {
1956 if (CCMask == SystemZ::CCMASK_CMP_LE)
1957 return SystemZ::CCMASK_TM_MSB_0;
1958 if (CCMask == SystemZ::CCMASK_CMP_GT)
1959 return SystemZ::CCMASK_TM_MSB_1;
1961 if (EffectivelyUnsigned && CmpVal > Mask - High && CmpVal <= High) {
1962 if (CCMask == SystemZ::CCMASK_CMP_LT)
1963 return SystemZ::CCMASK_TM_MSB_0;
1964 if (CCMask == SystemZ::CCMASK_CMP_GE)
1965 return SystemZ::CCMASK_TM_MSB_1;
1968 // If there are just two bits, we can do equality checks for Low and High
1970 if (Mask == Low + High) {
1971 if (CCMask == SystemZ::CCMASK_CMP_EQ && CmpVal == Low)
1972 return SystemZ::CCMASK_TM_MIXED_MSB_0;
1973 if (CCMask == SystemZ::CCMASK_CMP_NE && CmpVal == Low)
1974 return SystemZ::CCMASK_TM_MIXED_MSB_0 ^ SystemZ::CCMASK_ANY;
1975 if (CCMask == SystemZ::CCMASK_CMP_EQ && CmpVal == High)
1976 return SystemZ::CCMASK_TM_MIXED_MSB_1;
1977 if (CCMask == SystemZ::CCMASK_CMP_NE && CmpVal == High)
1978 return SystemZ::CCMASK_TM_MIXED_MSB_1 ^ SystemZ::CCMASK_ANY;
1981 // Looks like we've exhausted our options.
1985 // See whether C can be implemented as a TEST UNDER MASK instruction.
1986 // Update the arguments with the TM version if so.
1987 static void adjustForTestUnderMask(SelectionDAG &DAG, const SDLoc &DL,
1989 // Check that we have a comparison with a constant.
1990 auto *ConstOp1 = dyn_cast<ConstantSDNode>(C.Op1);
1993 uint64_t CmpVal = ConstOp1->getZExtValue();
1995 // Check whether the nonconstant input is an AND with a constant mask.
1998 ConstantSDNode *Mask = nullptr;
1999 if (C.Op0.getOpcode() == ISD::AND) {
2000 NewC.Op0 = C.Op0.getOperand(0);
2001 NewC.Op1 = C.Op0.getOperand(1);
2002 Mask = dyn_cast<ConstantSDNode>(NewC.Op1);
2005 MaskVal = Mask->getZExtValue();
2007 // There is no instruction to compare with a 64-bit immediate
2008 // so use TMHH instead if possible. We need an unsigned ordered
2009 // comparison with an i64 immediate.
2010 if (NewC.Op0.getValueType() != MVT::i64 ||
2011 NewC.CCMask == SystemZ::CCMASK_CMP_EQ ||
2012 NewC.CCMask == SystemZ::CCMASK_CMP_NE ||
2013 NewC.ICmpType == SystemZICMP::SignedOnly)
2015 // Convert LE and GT comparisons into LT and GE.
2016 if (NewC.CCMask == SystemZ::CCMASK_CMP_LE ||
2017 NewC.CCMask == SystemZ::CCMASK_CMP_GT) {
2018 if (CmpVal == uint64_t(-1))
2021 NewC.CCMask ^= SystemZ::CCMASK_CMP_EQ;
2023 // If the low N bits of Op1 are zero than the low N bits of Op0 can
2024 // be masked off without changing the result.
2025 MaskVal = -(CmpVal & -CmpVal);
2026 NewC.ICmpType = SystemZICMP::UnsignedOnly;
2031 // Check whether the combination of mask, comparison value and comparison
2032 // type are suitable.
2033 unsigned BitSize = NewC.Op0.getValueSizeInBits();
2034 unsigned NewCCMask, ShiftVal;
2035 if (NewC.ICmpType != SystemZICMP::SignedOnly &&
2036 NewC.Op0.getOpcode() == ISD::SHL &&
2037 isSimpleShift(NewC.Op0, ShiftVal) &&
2038 (NewCCMask = getTestUnderMaskCond(BitSize, NewC.CCMask,
2039 MaskVal >> ShiftVal,
2041 SystemZICMP::Any))) {
2042 NewC.Op0 = NewC.Op0.getOperand(0);
2043 MaskVal >>= ShiftVal;
2044 } else if (NewC.ICmpType != SystemZICMP::SignedOnly &&
2045 NewC.Op0.getOpcode() == ISD::SRL &&
2046 isSimpleShift(NewC.Op0, ShiftVal) &&
2047 (NewCCMask = getTestUnderMaskCond(BitSize, NewC.CCMask,
2048 MaskVal << ShiftVal,
2050 SystemZICMP::UnsignedOnly))) {
2051 NewC.Op0 = NewC.Op0.getOperand(0);
2052 MaskVal <<= ShiftVal;
2054 NewCCMask = getTestUnderMaskCond(BitSize, NewC.CCMask, MaskVal, CmpVal,
2060 // Go ahead and make the change.
2061 C.Opcode = SystemZISD::TM;
2063 if (Mask && Mask->getZExtValue() == MaskVal)
2064 C.Op1 = SDValue(Mask, 0);
2066 C.Op1 = DAG.getConstant(MaskVal, DL, C.Op0.getValueType());
2067 C.CCValid = SystemZ::CCMASK_TM;
2068 C.CCMask = NewCCMask;
2071 // Return a Comparison that tests the condition-code result of intrinsic
2072 // node Call against constant integer CC using comparison code Cond.
2073 // Opcode is the opcode of the SystemZISD operation for the intrinsic
2074 // and CCValid is the set of possible condition-code results.
2075 static Comparison getIntrinsicCmp(SelectionDAG &DAG, unsigned Opcode,
2076 SDValue Call, unsigned CCValid, uint64_t CC,
2077 ISD::CondCode Cond) {
2078 Comparison C(Call, SDValue());
2080 C.CCValid = CCValid;
2081 if (Cond == ISD::SETEQ)
2082 // bit 3 for CC==0, bit 0 for CC==3, always false for CC>3.
2083 C.CCMask = CC < 4 ? 1 << (3 - CC) : 0;
2084 else if (Cond == ISD::SETNE)
2085 // ...and the inverse of that.
2086 C.CCMask = CC < 4 ? ~(1 << (3 - CC)) : -1;
2087 else if (Cond == ISD::SETLT || Cond == ISD::SETULT)
2088 // bits above bit 3 for CC==0 (always false), bits above bit 0 for CC==3,
2089 // always true for CC>3.
2090 C.CCMask = CC < 4 ? ~0U << (4 - CC) : -1;
2091 else if (Cond == ISD::SETGE || Cond == ISD::SETUGE)
2092 // ...and the inverse of that.
2093 C.CCMask = CC < 4 ? ~(~0U << (4 - CC)) : 0;
2094 else if (Cond == ISD::SETLE || Cond == ISD::SETULE)
2095 // bit 3 and above for CC==0, bit 0 and above for CC==3 (always true),
2096 // always true for CC>3.
2097 C.CCMask = CC < 4 ? ~0U << (3 - CC) : -1;
2098 else if (Cond == ISD::SETGT || Cond == ISD::SETUGT)
2099 // ...and the inverse of that.
2100 C.CCMask = CC < 4 ? ~(~0U << (3 - CC)) : 0;
2102 llvm_unreachable("Unexpected integer comparison type");
2103 C.CCMask &= CCValid;
2107 // Decide how to implement a comparison of type Cond between CmpOp0 with CmpOp1.
2108 static Comparison getCmp(SelectionDAG &DAG, SDValue CmpOp0, SDValue CmpOp1,
2109 ISD::CondCode Cond, const SDLoc &DL) {
2110 if (CmpOp1.getOpcode() == ISD::Constant) {
2111 uint64_t Constant = cast<ConstantSDNode>(CmpOp1)->getZExtValue();
2112 unsigned Opcode, CCValid;
2113 if (CmpOp0.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
2114 CmpOp0.getResNo() == 0 && CmpOp0->hasNUsesOfValue(1, 0) &&
2115 isIntrinsicWithCCAndChain(CmpOp0, Opcode, CCValid))
2116 return getIntrinsicCmp(DAG, Opcode, CmpOp0, CCValid, Constant, Cond);
2117 if (CmpOp0.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
2118 CmpOp0.getResNo() == CmpOp0->getNumValues() - 1 &&
2119 isIntrinsicWithCC(CmpOp0, Opcode, CCValid))
2120 return getIntrinsicCmp(DAG, Opcode, CmpOp0, CCValid, Constant, Cond);
2122 Comparison C(CmpOp0, CmpOp1);
2123 C.CCMask = CCMaskForCondCode(Cond);
2124 if (C.Op0.getValueType().isFloatingPoint()) {
2125 C.CCValid = SystemZ::CCMASK_FCMP;
2126 C.Opcode = SystemZISD::FCMP;
2129 C.CCValid = SystemZ::CCMASK_ICMP;
2130 C.Opcode = SystemZISD::ICMP;
2131 // Choose the type of comparison. Equality and inequality tests can
2132 // use either signed or unsigned comparisons. The choice also doesn't
2133 // matter if both sign bits are known to be clear. In those cases we
2134 // want to give the main isel code the freedom to choose whichever
2136 if (C.CCMask == SystemZ::CCMASK_CMP_EQ ||
2137 C.CCMask == SystemZ::CCMASK_CMP_NE ||
2138 (DAG.SignBitIsZero(C.Op0) && DAG.SignBitIsZero(C.Op1)))
2139 C.ICmpType = SystemZICMP::Any;
2140 else if (C.CCMask & SystemZ::CCMASK_CMP_UO)
2141 C.ICmpType = SystemZICMP::UnsignedOnly;
2143 C.ICmpType = SystemZICMP::SignedOnly;
2144 C.CCMask &= ~SystemZ::CCMASK_CMP_UO;
2145 adjustZeroCmp(DAG, DL, C);
2146 adjustSubwordCmp(DAG, DL, C);
2147 adjustForSubtraction(DAG, DL, C);
2149 adjustICmpTruncate(DAG, DL, C);
2152 if (shouldSwapCmpOperands(C)) {
2153 std::swap(C.Op0, C.Op1);
2154 C.CCMask = reverseCCMask(C.CCMask);
2157 adjustForTestUnderMask(DAG, DL, C);
2161 // Emit the comparison instruction described by C.
2162 static SDValue emitCmp(SelectionDAG &DAG, const SDLoc &DL, Comparison &C) {
2163 if (!C.Op1.getNode()) {
2165 switch (C.Op0.getOpcode()) {
2166 case ISD::INTRINSIC_W_CHAIN:
2167 Op = emitIntrinsicWithChainAndGlue(DAG, C.Op0, C.Opcode);
2169 case ISD::INTRINSIC_WO_CHAIN:
2170 Op = emitIntrinsicWithGlue(DAG, C.Op0, C.Opcode);
2173 llvm_unreachable("Invalid comparison operands");
2175 return SDValue(Op.getNode(), Op->getNumValues() - 1);
2177 if (C.Opcode == SystemZISD::ICMP)
2178 return DAG.getNode(SystemZISD::ICMP, DL, MVT::Glue, C.Op0, C.Op1,
2179 DAG.getConstant(C.ICmpType, DL, MVT::i32));
2180 if (C.Opcode == SystemZISD::TM) {
2181 bool RegisterOnly = (bool(C.CCMask & SystemZ::CCMASK_TM_MIXED_MSB_0) !=
2182 bool(C.CCMask & SystemZ::CCMASK_TM_MIXED_MSB_1));
2183 return DAG.getNode(SystemZISD::TM, DL, MVT::Glue, C.Op0, C.Op1,
2184 DAG.getConstant(RegisterOnly, DL, MVT::i32));
2186 return DAG.getNode(C.Opcode, DL, MVT::Glue, C.Op0, C.Op1);
2189 // Implement a 32-bit *MUL_LOHI operation by extending both operands to
2190 // 64 bits. Extend is the extension type to use. Store the high part
2191 // in Hi and the low part in Lo.
2192 static void lowerMUL_LOHI32(SelectionDAG &DAG, const SDLoc &DL, unsigned Extend,
2193 SDValue Op0, SDValue Op1, SDValue &Hi,
2195 Op0 = DAG.getNode(Extend, DL, MVT::i64, Op0);
2196 Op1 = DAG.getNode(Extend, DL, MVT::i64, Op1);
2197 SDValue Mul = DAG.getNode(ISD::MUL, DL, MVT::i64, Op0, Op1);
2198 Hi = DAG.getNode(ISD::SRL, DL, MVT::i64, Mul,
2199 DAG.getConstant(32, DL, MVT::i64));
2200 Hi = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Hi);
2201 Lo = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mul);
2204 // Lower a binary operation that produces two VT results, one in each
2205 // half of a GR128 pair. Op0 and Op1 are the VT operands to the operation,
2206 // Extend extends Op0 to a GR128, and Opcode performs the GR128 operation
2207 // on the extended Op0 and (unextended) Op1. Store the even register result
2208 // in Even and the odd register result in Odd.
2209 static void lowerGR128Binary(SelectionDAG &DAG, const SDLoc &DL, EVT VT,
2210 unsigned Extend, unsigned Opcode, SDValue Op0,
2211 SDValue Op1, SDValue &Even, SDValue &Odd) {
2212 SDNode *In128 = DAG.getMachineNode(Extend, DL, MVT::Untyped, Op0);
2213 SDValue Result = DAG.getNode(Opcode, DL, MVT::Untyped,
2214 SDValue(In128, 0), Op1);
2215 bool Is32Bit = is32Bit(VT);
2216 Even = DAG.getTargetExtractSubreg(SystemZ::even128(Is32Bit), DL, VT, Result);
2217 Odd = DAG.getTargetExtractSubreg(SystemZ::odd128(Is32Bit), DL, VT, Result);
2220 // Return an i32 value that is 1 if the CC value produced by Glue is
2221 // in the mask CCMask and 0 otherwise. CC is known to have a value
2222 // in CCValid, so other values can be ignored.
2223 static SDValue emitSETCC(SelectionDAG &DAG, const SDLoc &DL, SDValue Glue,
2224 unsigned CCValid, unsigned CCMask) {
2225 IPMConversion Conversion = getIPMConversion(CCValid, CCMask);
2226 SDValue Result = DAG.getNode(SystemZISD::IPM, DL, MVT::i32, Glue);
2228 if (Conversion.XORValue)
2229 Result = DAG.getNode(ISD::XOR, DL, MVT::i32, Result,
2230 DAG.getConstant(Conversion.XORValue, DL, MVT::i32));
2232 if (Conversion.AddValue)
2233 Result = DAG.getNode(ISD::ADD, DL, MVT::i32, Result,
2234 DAG.getConstant(Conversion.AddValue, DL, MVT::i32));
2236 // The SHR/AND sequence should get optimized to an RISBG.
2237 Result = DAG.getNode(ISD::SRL, DL, MVT::i32, Result,
2238 DAG.getConstant(Conversion.Bit, DL, MVT::i32));
2239 if (Conversion.Bit != 31)
2240 Result = DAG.getNode(ISD::AND, DL, MVT::i32, Result,
2241 DAG.getConstant(1, DL, MVT::i32));
2245 // Return the SystemISD vector comparison operation for CC, or 0 if it cannot
2246 // be done directly. IsFP is true if CC is for a floating-point rather than
2247 // integer comparison.
2248 static unsigned getVectorComparison(ISD::CondCode CC, bool IsFP) {
2252 return IsFP ? SystemZISD::VFCMPE : SystemZISD::VICMPE;
2256 return IsFP ? SystemZISD::VFCMPHE : static_cast<SystemZISD::NodeType>(0);
2260 return IsFP ? SystemZISD::VFCMPH : SystemZISD::VICMPH;
2263 return IsFP ? static_cast<SystemZISD::NodeType>(0) : SystemZISD::VICMPHL;
2270 // Return the SystemZISD vector comparison operation for CC or its inverse,
2271 // or 0 if neither can be done directly. Indicate in Invert whether the
2272 // result is for the inverse of CC. IsFP is true if CC is for a
2273 // floating-point rather than integer comparison.
2274 static unsigned getVectorComparisonOrInvert(ISD::CondCode CC, bool IsFP,
2276 if (unsigned Opcode = getVectorComparison(CC, IsFP)) {
2281 CC = ISD::getSetCCInverse(CC, !IsFP);
2282 if (unsigned Opcode = getVectorComparison(CC, IsFP)) {
2290 // Return a v2f64 that contains the extended form of elements Start and Start+1
2291 // of v4f32 value Op.
2292 static SDValue expandV4F32ToV2F64(SelectionDAG &DAG, int Start, const SDLoc &DL,
2294 int Mask[] = { Start, -1, Start + 1, -1 };
2295 Op = DAG.getVectorShuffle(MVT::v4f32, DL, Op, DAG.getUNDEF(MVT::v4f32), Mask);
2296 return DAG.getNode(SystemZISD::VEXTEND, DL, MVT::v2f64, Op);
2299 // Build a comparison of vectors CmpOp0 and CmpOp1 using opcode Opcode,
2300 // producing a result of type VT.
2301 static SDValue getVectorCmp(SelectionDAG &DAG, unsigned Opcode, const SDLoc &DL,
2302 EVT VT, SDValue CmpOp0, SDValue CmpOp1) {
2303 // There is no hardware support for v4f32, so extend the vector into
2304 // two v2f64s and compare those.
2305 if (CmpOp0.getValueType() == MVT::v4f32) {
2306 SDValue H0 = expandV4F32ToV2F64(DAG, 0, DL, CmpOp0);
2307 SDValue L0 = expandV4F32ToV2F64(DAG, 2, DL, CmpOp0);
2308 SDValue H1 = expandV4F32ToV2F64(DAG, 0, DL, CmpOp1);
2309 SDValue L1 = expandV4F32ToV2F64(DAG, 2, DL, CmpOp1);
2310 SDValue HRes = DAG.getNode(Opcode, DL, MVT::v2i64, H0, H1);
2311 SDValue LRes = DAG.getNode(Opcode, DL, MVT::v2i64, L0, L1);
2312 return DAG.getNode(SystemZISD::PACK, DL, VT, HRes, LRes);
2314 return DAG.getNode(Opcode, DL, VT, CmpOp0, CmpOp1);
2317 // Lower a vector comparison of type CC between CmpOp0 and CmpOp1, producing
2318 // an integer mask of type VT.
2319 static SDValue lowerVectorSETCC(SelectionDAG &DAG, const SDLoc &DL, EVT VT,
2320 ISD::CondCode CC, SDValue CmpOp0,
2322 bool IsFP = CmpOp0.getValueType().isFloatingPoint();
2323 bool Invert = false;
2326 // Handle tests for order using (or (ogt y x) (oge x y)).
2330 assert(IsFP && "Unexpected integer comparison");
2331 SDValue LT = getVectorCmp(DAG, SystemZISD::VFCMPH, DL, VT, CmpOp1, CmpOp0);
2332 SDValue GE = getVectorCmp(DAG, SystemZISD::VFCMPHE, DL, VT, CmpOp0, CmpOp1);
2333 Cmp = DAG.getNode(ISD::OR, DL, VT, LT, GE);
2337 // Handle <> tests using (or (ogt y x) (ogt x y)).
2341 assert(IsFP && "Unexpected integer comparison");
2342 SDValue LT = getVectorCmp(DAG, SystemZISD::VFCMPH, DL, VT, CmpOp1, CmpOp0);
2343 SDValue GT = getVectorCmp(DAG, SystemZISD::VFCMPH, DL, VT, CmpOp0, CmpOp1);
2344 Cmp = DAG.getNode(ISD::OR, DL, VT, LT, GT);
2348 // Otherwise a single comparison is enough. It doesn't really
2349 // matter whether we try the inversion or the swap first, since
2350 // there are no cases where both work.
2352 if (unsigned Opcode = getVectorComparisonOrInvert(CC, IsFP, Invert))
2353 Cmp = getVectorCmp(DAG, Opcode, DL, VT, CmpOp0, CmpOp1);
2355 CC = ISD::getSetCCSwappedOperands(CC);
2356 if (unsigned Opcode = getVectorComparisonOrInvert(CC, IsFP, Invert))
2357 Cmp = getVectorCmp(DAG, Opcode, DL, VT, CmpOp1, CmpOp0);
2359 llvm_unreachable("Unhandled comparison");
2364 SDValue Mask = DAG.getNode(SystemZISD::BYTE_MASK, DL, MVT::v16i8,
2365 DAG.getConstant(65535, DL, MVT::i32));
2366 Mask = DAG.getNode(ISD::BITCAST, DL, VT, Mask);
2367 Cmp = DAG.getNode(ISD::XOR, DL, VT, Cmp, Mask);
2372 SDValue SystemZTargetLowering::lowerSETCC(SDValue Op,
2373 SelectionDAG &DAG) const {
2374 SDValue CmpOp0 = Op.getOperand(0);
2375 SDValue CmpOp1 = Op.getOperand(1);
2376 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
2378 EVT VT = Op.getValueType();
2380 return lowerVectorSETCC(DAG, DL, VT, CC, CmpOp0, CmpOp1);
2382 Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC, DL));
2383 SDValue Glue = emitCmp(DAG, DL, C);
2384 return emitSETCC(DAG, DL, Glue, C.CCValid, C.CCMask);
2387 SDValue SystemZTargetLowering::lowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
2388 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2389 SDValue CmpOp0 = Op.getOperand(2);
2390 SDValue CmpOp1 = Op.getOperand(3);
2391 SDValue Dest = Op.getOperand(4);
2394 Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC, DL));
2395 SDValue Glue = emitCmp(DAG, DL, C);
2396 return DAG.getNode(SystemZISD::BR_CCMASK, DL, Op.getValueType(),
2397 Op.getOperand(0), DAG.getConstant(C.CCValid, DL, MVT::i32),
2398 DAG.getConstant(C.CCMask, DL, MVT::i32), Dest, Glue);
2401 // Return true if Pos is CmpOp and Neg is the negative of CmpOp,
2402 // allowing Pos and Neg to be wider than CmpOp.
2403 static bool isAbsolute(SDValue CmpOp, SDValue Pos, SDValue Neg) {
2404 return (Neg.getOpcode() == ISD::SUB &&
2405 Neg.getOperand(0).getOpcode() == ISD::Constant &&
2406 cast<ConstantSDNode>(Neg.getOperand(0))->getZExtValue() == 0 &&
2407 Neg.getOperand(1) == Pos &&
2409 (Pos.getOpcode() == ISD::SIGN_EXTEND &&
2410 Pos.getOperand(0) == CmpOp)));
2413 // Return the absolute or negative absolute of Op; IsNegative decides which.
2414 static SDValue getAbsolute(SelectionDAG &DAG, const SDLoc &DL, SDValue Op,
2416 Op = DAG.getNode(SystemZISD::IABS, DL, Op.getValueType(), Op);
2418 Op = DAG.getNode(ISD::SUB, DL, Op.getValueType(),
2419 DAG.getConstant(0, DL, Op.getValueType()), Op);
2423 SDValue SystemZTargetLowering::lowerSELECT_CC(SDValue Op,
2424 SelectionDAG &DAG) const {
2425 SDValue CmpOp0 = Op.getOperand(0);
2426 SDValue CmpOp1 = Op.getOperand(1);
2427 SDValue TrueOp = Op.getOperand(2);
2428 SDValue FalseOp = Op.getOperand(3);
2429 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2432 Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC, DL));
2434 // Check for absolute and negative-absolute selections, including those
2435 // where the comparison value is sign-extended (for LPGFR and LNGFR).
2436 // This check supplements the one in DAGCombiner.
2437 if (C.Opcode == SystemZISD::ICMP &&
2438 C.CCMask != SystemZ::CCMASK_CMP_EQ &&
2439 C.CCMask != SystemZ::CCMASK_CMP_NE &&
2440 C.Op1.getOpcode() == ISD::Constant &&
2441 cast<ConstantSDNode>(C.Op1)->getZExtValue() == 0) {
2442 if (isAbsolute(C.Op0, TrueOp, FalseOp))
2443 return getAbsolute(DAG, DL, TrueOp, C.CCMask & SystemZ::CCMASK_CMP_LT);
2444 if (isAbsolute(C.Op0, FalseOp, TrueOp))
2445 return getAbsolute(DAG, DL, FalseOp, C.CCMask & SystemZ::CCMASK_CMP_GT);
2448 SDValue Glue = emitCmp(DAG, DL, C);
2450 // Special case for handling -1/0 results. The shifts we use here
2451 // should get optimized with the IPM conversion sequence.
2452 auto *TrueC = dyn_cast<ConstantSDNode>(TrueOp);
2453 auto *FalseC = dyn_cast<ConstantSDNode>(FalseOp);
2454 if (TrueC && FalseC) {
2455 int64_t TrueVal = TrueC->getSExtValue();
2456 int64_t FalseVal = FalseC->getSExtValue();
2457 if ((TrueVal == -1 && FalseVal == 0) || (TrueVal == 0 && FalseVal == -1)) {
2458 // Invert the condition if we want -1 on false.
2460 C.CCMask ^= C.CCValid;
2461 SDValue Result = emitSETCC(DAG, DL, Glue, C.CCValid, C.CCMask);
2462 EVT VT = Op.getValueType();
2463 // Extend the result to VT. Upper bits are ignored.
2465 Result = DAG.getNode(ISD::ANY_EXTEND, DL, VT, Result);
2466 // Sign-extend from the low bit.
2467 SDValue ShAmt = DAG.getConstant(VT.getSizeInBits() - 1, DL, MVT::i32);
2468 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, Result, ShAmt);
2469 return DAG.getNode(ISD::SRA, DL, VT, Shl, ShAmt);
2473 SDValue Ops[] = {TrueOp, FalseOp, DAG.getConstant(C.CCValid, DL, MVT::i32),
2474 DAG.getConstant(C.CCMask, DL, MVT::i32), Glue};
2476 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
2477 return DAG.getNode(SystemZISD::SELECT_CCMASK, DL, VTs, Ops);
2480 SDValue SystemZTargetLowering::lowerGlobalAddress(GlobalAddressSDNode *Node,
2481 SelectionDAG &DAG) const {
2483 const GlobalValue *GV = Node->getGlobal();
2484 int64_t Offset = Node->getOffset();
2485 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2486 CodeModel::Model CM = DAG.getTarget().getCodeModel();
2489 if (Subtarget.isPC32DBLSymbol(GV, CM)) {
2490 // Assign anchors at 1<<12 byte boundaries.
2491 uint64_t Anchor = Offset & ~uint64_t(0xfff);
2492 Result = DAG.getTargetGlobalAddress(GV, DL, PtrVT, Anchor);
2493 Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
2495 // The offset can be folded into the address if it is aligned to a halfword.
2497 if (Offset != 0 && (Offset & 1) == 0) {
2498 SDValue Full = DAG.getTargetGlobalAddress(GV, DL, PtrVT, Anchor + Offset);
2499 Result = DAG.getNode(SystemZISD::PCREL_OFFSET, DL, PtrVT, Full, Result);
2503 Result = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, SystemZII::MO_GOT);
2504 Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
2505 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
2506 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
2509 // If there was a non-zero offset that we didn't fold, create an explicit
2512 Result = DAG.getNode(ISD::ADD, DL, PtrVT, Result,
2513 DAG.getConstant(Offset, DL, PtrVT));
2518 SDValue SystemZTargetLowering::lowerTLSGetOffset(GlobalAddressSDNode *Node,
2521 SDValue GOTOffset) const {
2523 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2524 SDValue Chain = DAG.getEntryNode();
2527 // __tls_get_offset takes the GOT offset in %r2 and the GOT in %r12.
2528 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
2529 Chain = DAG.getCopyToReg(Chain, DL, SystemZ::R12D, GOT, Glue);
2530 Glue = Chain.getValue(1);
2531 Chain = DAG.getCopyToReg(Chain, DL, SystemZ::R2D, GOTOffset, Glue);
2532 Glue = Chain.getValue(1);
2534 // The first call operand is the chain and the second is the TLS symbol.
2535 SmallVector<SDValue, 8> Ops;
2536 Ops.push_back(Chain);
2537 Ops.push_back(DAG.getTargetGlobalAddress(Node->getGlobal(), DL,
2538 Node->getValueType(0),
2541 // Add argument registers to the end of the list so that they are
2542 // known live into the call.
2543 Ops.push_back(DAG.getRegister(SystemZ::R2D, PtrVT));
2544 Ops.push_back(DAG.getRegister(SystemZ::R12D, PtrVT));
2546 // Add a register mask operand representing the call-preserved registers.
2547 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
2548 const uint32_t *Mask =
2549 TRI->getCallPreservedMask(DAG.getMachineFunction(), CallingConv::C);
2550 assert(Mask && "Missing call preserved mask for calling convention");
2551 Ops.push_back(DAG.getRegisterMask(Mask));
2553 // Glue the call to the argument copies.
2554 Ops.push_back(Glue);
2557 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2558 Chain = DAG.getNode(Opcode, DL, NodeTys, Ops);
2559 Glue = Chain.getValue(1);
2561 // Copy the return value from %r2.
2562 return DAG.getCopyFromReg(Chain, DL, SystemZ::R2D, PtrVT, Glue);
2565 SDValue SystemZTargetLowering::lowerThreadPointer(const SDLoc &DL,
2566 SelectionDAG &DAG) const {
2567 SDValue Chain = DAG.getEntryNode();
2568 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2570 // The high part of the thread pointer is in access register 0.
2571 SDValue TPHi = DAG.getCopyFromReg(Chain, DL, SystemZ::A0, MVT::i32);
2572 TPHi = DAG.getNode(ISD::ANY_EXTEND, DL, PtrVT, TPHi);
2574 // The low part of the thread pointer is in access register 1.
2575 SDValue TPLo = DAG.getCopyFromReg(Chain, DL, SystemZ::A1, MVT::i32);
2576 TPLo = DAG.getNode(ISD::ZERO_EXTEND, DL, PtrVT, TPLo);
2578 // Merge them into a single 64-bit address.
2579 SDValue TPHiShifted = DAG.getNode(ISD::SHL, DL, PtrVT, TPHi,
2580 DAG.getConstant(32, DL, PtrVT));
2581 return DAG.getNode(ISD::OR, DL, PtrVT, TPHiShifted, TPLo);
2584 SDValue SystemZTargetLowering::lowerGlobalTLSAddress(GlobalAddressSDNode *Node,
2585 SelectionDAG &DAG) const {
2586 if (DAG.getTarget().Options.EmulatedTLS)
2587 return LowerToTLSEmulatedModel(Node, DAG);
2589 const GlobalValue *GV = Node->getGlobal();
2590 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2591 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
2593 SDValue TP = lowerThreadPointer(DL, DAG);
2595 // Get the offset of GA from the thread pointer, based on the TLS model.
2598 case TLSModel::GeneralDynamic: {
2599 // Load the GOT offset of the tls_index (module ID / per-symbol offset).
2600 SystemZConstantPoolValue *CPV =
2601 SystemZConstantPoolValue::Create(GV, SystemZCP::TLSGD);
2603 Offset = DAG.getConstantPool(CPV, PtrVT, 8);
2604 Offset = DAG.getLoad(
2605 PtrVT, DL, DAG.getEntryNode(), Offset,
2606 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2608 // Call __tls_get_offset to retrieve the offset.
2609 Offset = lowerTLSGetOffset(Node, DAG, SystemZISD::TLS_GDCALL, Offset);
2613 case TLSModel::LocalDynamic: {
2614 // Load the GOT offset of the module ID.
2615 SystemZConstantPoolValue *CPV =
2616 SystemZConstantPoolValue::Create(GV, SystemZCP::TLSLDM);
2618 Offset = DAG.getConstantPool(CPV, PtrVT, 8);
2619 Offset = DAG.getLoad(
2620 PtrVT, DL, DAG.getEntryNode(), Offset,
2621 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2623 // Call __tls_get_offset to retrieve the module base offset.
2624 Offset = lowerTLSGetOffset(Node, DAG, SystemZISD::TLS_LDCALL, Offset);
2626 // Note: The SystemZLDCleanupPass will remove redundant computations
2627 // of the module base offset. Count total number of local-dynamic
2628 // accesses to trigger execution of that pass.
2629 SystemZMachineFunctionInfo* MFI =
2630 DAG.getMachineFunction().getInfo<SystemZMachineFunctionInfo>();
2631 MFI->incNumLocalDynamicTLSAccesses();
2633 // Add the per-symbol offset.
2634 CPV = SystemZConstantPoolValue::Create(GV, SystemZCP::DTPOFF);
2636 SDValue DTPOffset = DAG.getConstantPool(CPV, PtrVT, 8);
2637 DTPOffset = DAG.getLoad(
2638 PtrVT, DL, DAG.getEntryNode(), DTPOffset,
2639 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2641 Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Offset, DTPOffset);
2645 case TLSModel::InitialExec: {
2646 // Load the offset from the GOT.
2647 Offset = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2648 SystemZII::MO_INDNTPOFF);
2649 Offset = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Offset);
2651 DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Offset,
2652 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
2656 case TLSModel::LocalExec: {
2657 // Force the offset into the constant pool and load it from there.
2658 SystemZConstantPoolValue *CPV =
2659 SystemZConstantPoolValue::Create(GV, SystemZCP::NTPOFF);
2661 Offset = DAG.getConstantPool(CPV, PtrVT, 8);
2662 Offset = DAG.getLoad(
2663 PtrVT, DL, DAG.getEntryNode(), Offset,
2664 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2669 // Add the base and offset together.
2670 return DAG.getNode(ISD::ADD, DL, PtrVT, TP, Offset);
2673 SDValue SystemZTargetLowering::lowerBlockAddress(BlockAddressSDNode *Node,
2674 SelectionDAG &DAG) const {
2676 const BlockAddress *BA = Node->getBlockAddress();
2677 int64_t Offset = Node->getOffset();
2678 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2680 SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT, Offset);
2681 Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
2685 SDValue SystemZTargetLowering::lowerJumpTable(JumpTableSDNode *JT,
2686 SelectionDAG &DAG) const {
2688 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2689 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
2691 // Use LARL to load the address of the table.
2692 return DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
2695 SDValue SystemZTargetLowering::lowerConstantPool(ConstantPoolSDNode *CP,
2696 SelectionDAG &DAG) const {
2698 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2701 if (CP->isMachineConstantPoolEntry())
2702 Result = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
2703 CP->getAlignment());
2705 Result = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
2706 CP->getAlignment(), CP->getOffset());
2708 // Use LARL to load the address of the constant pool entry.
2709 return DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
2712 SDValue SystemZTargetLowering::lowerFRAMEADDR(SDValue Op,
2713 SelectionDAG &DAG) const {
2714 MachineFunction &MF = DAG.getMachineFunction();
2715 MachineFrameInfo &MFI = MF.getFrameInfo();
2716 MFI.setFrameAddressIsTaken(true);
2719 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2720 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2722 // If the back chain frame index has not been allocated yet, do so.
2723 SystemZMachineFunctionInfo *FI = MF.getInfo<SystemZMachineFunctionInfo>();
2724 int BackChainIdx = FI->getFramePointerSaveIndex();
2725 if (!BackChainIdx) {
2726 // By definition, the frame address is the address of the back chain.
2727 BackChainIdx = MFI.CreateFixedObject(8, -SystemZMC::CallFrameSize, false);
2728 FI->setFramePointerSaveIndex(BackChainIdx);
2730 SDValue BackChain = DAG.getFrameIndex(BackChainIdx, PtrVT);
2732 // FIXME The frontend should detect this case.
2734 report_fatal_error("Unsupported stack frame traversal count");
2740 SDValue SystemZTargetLowering::lowerRETURNADDR(SDValue Op,
2741 SelectionDAG &DAG) const {
2742 MachineFunction &MF = DAG.getMachineFunction();
2743 MachineFrameInfo &MFI = MF.getFrameInfo();
2744 MFI.setReturnAddressIsTaken(true);
2746 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
2750 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2751 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2753 // FIXME The frontend should detect this case.
2755 report_fatal_error("Unsupported stack frame traversal count");
2758 // Return R14D, which has the return address. Mark it an implicit live-in.
2759 unsigned LinkReg = MF.addLiveIn(SystemZ::R14D, &SystemZ::GR64BitRegClass);
2760 return DAG.getCopyFromReg(DAG.getEntryNode(), DL, LinkReg, PtrVT);
2763 SDValue SystemZTargetLowering::lowerBITCAST(SDValue Op,
2764 SelectionDAG &DAG) const {
2766 SDValue In = Op.getOperand(0);
2767 EVT InVT = In.getValueType();
2768 EVT ResVT = Op.getValueType();
2770 // Convert loads directly. This is normally done by DAGCombiner,
2771 // but we need this case for bitcasts that are created during lowering
2772 // and which are then lowered themselves.
2773 if (auto *LoadN = dyn_cast<LoadSDNode>(In))
2774 return DAG.getLoad(ResVT, DL, LoadN->getChain(), LoadN->getBasePtr(),
2775 LoadN->getMemOperand());
2777 if (InVT == MVT::i32 && ResVT == MVT::f32) {
2779 if (Subtarget.hasHighWord()) {
2780 SDNode *U64 = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL,
2782 In64 = DAG.getTargetInsertSubreg(SystemZ::subreg_h32, DL,
2783 MVT::i64, SDValue(U64, 0), In);
2785 In64 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, In);
2786 In64 = DAG.getNode(ISD::SHL, DL, MVT::i64, In64,
2787 DAG.getConstant(32, DL, MVT::i64));
2789 SDValue Out64 = DAG.getNode(ISD::BITCAST, DL, MVT::f64, In64);
2790 return DAG.getTargetExtractSubreg(SystemZ::subreg_r32,
2791 DL, MVT::f32, Out64);
2793 if (InVT == MVT::f32 && ResVT == MVT::i32) {
2794 SDNode *U64 = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, MVT::f64);
2795 SDValue In64 = DAG.getTargetInsertSubreg(SystemZ::subreg_r32, DL,
2796 MVT::f64, SDValue(U64, 0), In);
2797 SDValue Out64 = DAG.getNode(ISD::BITCAST, DL, MVT::i64, In64);
2798 if (Subtarget.hasHighWord())
2799 return DAG.getTargetExtractSubreg(SystemZ::subreg_h32, DL,
2801 SDValue Shift = DAG.getNode(ISD::SRL, DL, MVT::i64, Out64,
2802 DAG.getConstant(32, DL, MVT::i64));
2803 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Shift);
2805 llvm_unreachable("Unexpected bitcast combination");
2808 SDValue SystemZTargetLowering::lowerVASTART(SDValue Op,
2809 SelectionDAG &DAG) const {
2810 MachineFunction &MF = DAG.getMachineFunction();
2811 SystemZMachineFunctionInfo *FuncInfo =
2812 MF.getInfo<SystemZMachineFunctionInfo>();
2813 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2815 SDValue Chain = Op.getOperand(0);
2816 SDValue Addr = Op.getOperand(1);
2817 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2820 // The initial values of each field.
2821 const unsigned NumFields = 4;
2822 SDValue Fields[NumFields] = {
2823 DAG.getConstant(FuncInfo->getVarArgsFirstGPR(), DL, PtrVT),
2824 DAG.getConstant(FuncInfo->getVarArgsFirstFPR(), DL, PtrVT),
2825 DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT),
2826 DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), PtrVT)
2829 // Store each field into its respective slot.
2830 SDValue MemOps[NumFields];
2831 unsigned Offset = 0;
2832 for (unsigned I = 0; I < NumFields; ++I) {
2833 SDValue FieldAddr = Addr;
2835 FieldAddr = DAG.getNode(ISD::ADD, DL, PtrVT, FieldAddr,
2836 DAG.getIntPtrConstant(Offset, DL));
2837 MemOps[I] = DAG.getStore(Chain, DL, Fields[I], FieldAddr,
2838 MachinePointerInfo(SV, Offset));
2841 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
2844 SDValue SystemZTargetLowering::lowerVACOPY(SDValue Op,
2845 SelectionDAG &DAG) const {
2846 SDValue Chain = Op.getOperand(0);
2847 SDValue DstPtr = Op.getOperand(1);
2848 SDValue SrcPtr = Op.getOperand(2);
2849 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
2850 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
2853 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr, DAG.getIntPtrConstant(32, DL),
2854 /*Align*/8, /*isVolatile*/false, /*AlwaysInline*/false,
2855 /*isTailCall*/false,
2856 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
2859 SDValue SystemZTargetLowering::
2860 lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const {
2861 const TargetFrameLowering *TFI = Subtarget.getFrameLowering();
2862 MachineFunction &MF = DAG.getMachineFunction();
2863 bool RealignOpt = !MF.getFunction()-> hasFnAttribute("no-realign-stack");
2864 bool StoreBackchain = MF.getFunction()->hasFnAttribute("backchain");
2866 SDValue Chain = Op.getOperand(0);
2867 SDValue Size = Op.getOperand(1);
2868 SDValue Align = Op.getOperand(2);
2871 // If user has set the no alignment function attribute, ignore
2872 // alloca alignments.
2873 uint64_t AlignVal = (RealignOpt ?
2874 dyn_cast<ConstantSDNode>(Align)->getZExtValue() : 0);
2876 uint64_t StackAlign = TFI->getStackAlignment();
2877 uint64_t RequiredAlign = std::max(AlignVal, StackAlign);
2878 uint64_t ExtraAlignSpace = RequiredAlign - StackAlign;
2880 unsigned SPReg = getStackPointerRegisterToSaveRestore();
2881 SDValue NeededSpace = Size;
2883 // Get a reference to the stack pointer.
2884 SDValue OldSP = DAG.getCopyFromReg(Chain, DL, SPReg, MVT::i64);
2886 // If we need a backchain, save it now.
2889 Backchain = DAG.getLoad(MVT::i64, DL, Chain, OldSP, MachinePointerInfo());
2891 // Add extra space for alignment if needed.
2892 if (ExtraAlignSpace)
2893 NeededSpace = DAG.getNode(ISD::ADD, DL, MVT::i64, NeededSpace,
2894 DAG.getConstant(ExtraAlignSpace, DL, MVT::i64));
2896 // Get the new stack pointer value.
2897 SDValue NewSP = DAG.getNode(ISD::SUB, DL, MVT::i64, OldSP, NeededSpace);
2899 // Copy the new stack pointer back.
2900 Chain = DAG.getCopyToReg(Chain, DL, SPReg, NewSP);
2902 // The allocated data lives above the 160 bytes allocated for the standard
2903 // frame, plus any outgoing stack arguments. We don't know how much that
2904 // amounts to yet, so emit a special ADJDYNALLOC placeholder.
2905 SDValue ArgAdjust = DAG.getNode(SystemZISD::ADJDYNALLOC, DL, MVT::i64);
2906 SDValue Result = DAG.getNode(ISD::ADD, DL, MVT::i64, NewSP, ArgAdjust);
2908 // Dynamically realign if needed.
2909 if (RequiredAlign > StackAlign) {
2911 DAG.getNode(ISD::ADD, DL, MVT::i64, Result,
2912 DAG.getConstant(ExtraAlignSpace, DL, MVT::i64));
2914 DAG.getNode(ISD::AND, DL, MVT::i64, Result,
2915 DAG.getConstant(~(RequiredAlign - 1), DL, MVT::i64));
2919 Chain = DAG.getStore(Chain, DL, Backchain, NewSP, MachinePointerInfo());
2921 SDValue Ops[2] = { Result, Chain };
2922 return DAG.getMergeValues(Ops, DL);
2925 SDValue SystemZTargetLowering::lowerGET_DYNAMIC_AREA_OFFSET(
2926 SDValue Op, SelectionDAG &DAG) const {
2929 return DAG.getNode(SystemZISD::ADJDYNALLOC, DL, MVT::i64);
2932 SDValue SystemZTargetLowering::lowerSMUL_LOHI(SDValue Op,
2933 SelectionDAG &DAG) const {
2934 EVT VT = Op.getValueType();
2938 // Just do a normal 64-bit multiplication and extract the results.
2939 // We define this so that it can be used for constant division.
2940 lowerMUL_LOHI32(DAG, DL, ISD::SIGN_EXTEND, Op.getOperand(0),
2941 Op.getOperand(1), Ops[1], Ops[0]);
2943 // Do a full 128-bit multiplication based on UMUL_LOHI64:
2945 // (ll * rl) + ((lh * rl) << 64) + ((ll * rh) << 64)
2947 // but using the fact that the upper halves are either all zeros
2950 // (ll * rl) - ((lh & rl) << 64) - ((ll & rh) << 64)
2952 // and grouping the right terms together since they are quicker than the
2955 // (ll * rl) - (((lh & rl) + (ll & rh)) << 64)
2956 SDValue C63 = DAG.getConstant(63, DL, MVT::i64);
2957 SDValue LL = Op.getOperand(0);
2958 SDValue RL = Op.getOperand(1);
2959 SDValue LH = DAG.getNode(ISD::SRA, DL, VT, LL, C63);
2960 SDValue RH = DAG.getNode(ISD::SRA, DL, VT, RL, C63);
2961 // UMUL_LOHI64 returns the low result in the odd register and the high
2962 // result in the even register. SMUL_LOHI is defined to return the
2963 // low half first, so the results are in reverse order.
2964 lowerGR128Binary(DAG, DL, VT, SystemZ::AEXT128_64, SystemZISD::UMUL_LOHI64,
2965 LL, RL, Ops[1], Ops[0]);
2966 SDValue NegLLTimesRH = DAG.getNode(ISD::AND, DL, VT, LL, RH);
2967 SDValue NegLHTimesRL = DAG.getNode(ISD::AND, DL, VT, LH, RL);
2968 SDValue NegSum = DAG.getNode(ISD::ADD, DL, VT, NegLLTimesRH, NegLHTimesRL);
2969 Ops[1] = DAG.getNode(ISD::SUB, DL, VT, Ops[1], NegSum);
2971 return DAG.getMergeValues(Ops, DL);
2974 SDValue SystemZTargetLowering::lowerUMUL_LOHI(SDValue Op,
2975 SelectionDAG &DAG) const {
2976 EVT VT = Op.getValueType();
2980 // Just do a normal 64-bit multiplication and extract the results.
2981 // We define this so that it can be used for constant division.
2982 lowerMUL_LOHI32(DAG, DL, ISD::ZERO_EXTEND, Op.getOperand(0),
2983 Op.getOperand(1), Ops[1], Ops[0]);
2985 // UMUL_LOHI64 returns the low result in the odd register and the high
2986 // result in the even register. UMUL_LOHI is defined to return the
2987 // low half first, so the results are in reverse order.
2988 lowerGR128Binary(DAG, DL, VT, SystemZ::AEXT128_64, SystemZISD::UMUL_LOHI64,
2989 Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
2990 return DAG.getMergeValues(Ops, DL);
2993 SDValue SystemZTargetLowering::lowerSDIVREM(SDValue Op,
2994 SelectionDAG &DAG) const {
2995 SDValue Op0 = Op.getOperand(0);
2996 SDValue Op1 = Op.getOperand(1);
2997 EVT VT = Op.getValueType();
3001 // We use DSGF for 32-bit division.
3003 Op0 = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i64, Op0);
3004 Opcode = SystemZISD::SDIVREM32;
3005 } else if (DAG.ComputeNumSignBits(Op1) > 32) {
3006 Op1 = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Op1);
3007 Opcode = SystemZISD::SDIVREM32;
3009 Opcode = SystemZISD::SDIVREM64;
3011 // DSG(F) takes a 64-bit dividend, so the even register in the GR128
3012 // input is "don't care". The instruction returns the remainder in
3013 // the even register and the quotient in the odd register.
3015 lowerGR128Binary(DAG, DL, VT, SystemZ::AEXT128_64, Opcode,
3016 Op0, Op1, Ops[1], Ops[0]);
3017 return DAG.getMergeValues(Ops, DL);
3020 SDValue SystemZTargetLowering::lowerUDIVREM(SDValue Op,
3021 SelectionDAG &DAG) const {
3022 EVT VT = Op.getValueType();
3025 // DL(G) uses a double-width dividend, so we need to clear the even
3026 // register in the GR128 input. The instruction returns the remainder
3027 // in the even register and the quotient in the odd register.
3030 lowerGR128Binary(DAG, DL, VT, SystemZ::ZEXT128_32, SystemZISD::UDIVREM32,
3031 Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
3033 lowerGR128Binary(DAG, DL, VT, SystemZ::ZEXT128_64, SystemZISD::UDIVREM64,
3034 Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
3035 return DAG.getMergeValues(Ops, DL);
3038 SDValue SystemZTargetLowering::lowerOR(SDValue Op, SelectionDAG &DAG) const {
3039 assert(Op.getValueType() == MVT::i64 && "Should be 64-bit operation");
3041 // Get the known-zero masks for each operand.
3042 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1) };
3043 APInt KnownZero[2], KnownOne[2];
3044 DAG.computeKnownBits(Ops[0], KnownZero[0], KnownOne[0]);
3045 DAG.computeKnownBits(Ops[1], KnownZero[1], KnownOne[1]);
3047 // See if the upper 32 bits of one operand and the lower 32 bits of the
3048 // other are known zero. They are the low and high operands respectively.
3049 uint64_t Masks[] = { KnownZero[0].getZExtValue(),
3050 KnownZero[1].getZExtValue() };
3052 if ((Masks[0] >> 32) == 0xffffffff && uint32_t(Masks[1]) == 0xffffffff)
3054 else if ((Masks[1] >> 32) == 0xffffffff && uint32_t(Masks[0]) == 0xffffffff)
3059 SDValue LowOp = Ops[Low];
3060 SDValue HighOp = Ops[High];
3062 // If the high part is a constant, we're better off using IILH.
3063 if (HighOp.getOpcode() == ISD::Constant)
3066 // If the low part is a constant that is outside the range of LHI,
3067 // then we're better off using IILF.
3068 if (LowOp.getOpcode() == ISD::Constant) {
3069 int64_t Value = int32_t(cast<ConstantSDNode>(LowOp)->getZExtValue());
3070 if (!isInt<16>(Value))
3074 // Check whether the high part is an AND that doesn't change the
3075 // high 32 bits and just masks out low bits. We can skip it if so.
3076 if (HighOp.getOpcode() == ISD::AND &&
3077 HighOp.getOperand(1).getOpcode() == ISD::Constant) {
3078 SDValue HighOp0 = HighOp.getOperand(0);
3079 uint64_t Mask = cast<ConstantSDNode>(HighOp.getOperand(1))->getZExtValue();
3080 if (DAG.MaskedValueIsZero(HighOp0, APInt(64, ~(Mask | 0xffffffff))))
3084 // Take advantage of the fact that all GR32 operations only change the
3085 // low 32 bits by truncating Low to an i32 and inserting it directly
3086 // using a subreg. The interesting cases are those where the truncation
3089 SDValue Low32 = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, LowOp);
3090 return DAG.getTargetInsertSubreg(SystemZ::subreg_l32, DL,
3091 MVT::i64, HighOp, Low32);
3094 SDValue SystemZTargetLowering::lowerCTPOP(SDValue Op,
3095 SelectionDAG &DAG) const {
3096 EVT VT = Op.getValueType();
3098 Op = Op.getOperand(0);
3100 // Handle vector types via VPOPCT.
3101 if (VT.isVector()) {
3102 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Op);
3103 Op = DAG.getNode(SystemZISD::POPCNT, DL, MVT::v16i8, Op);
3104 switch (VT.getScalarSizeInBits()) {
3108 Op = DAG.getNode(ISD::BITCAST, DL, VT, Op);
3109 SDValue Shift = DAG.getConstant(8, DL, MVT::i32);
3110 SDValue Tmp = DAG.getNode(SystemZISD::VSHL_BY_SCALAR, DL, VT, Op, Shift);
3111 Op = DAG.getNode(ISD::ADD, DL, VT, Op, Tmp);
3112 Op = DAG.getNode(SystemZISD::VSRL_BY_SCALAR, DL, VT, Op, Shift);
3116 SDValue Tmp = DAG.getNode(SystemZISD::BYTE_MASK, DL, MVT::v16i8,
3117 DAG.getConstant(0, DL, MVT::i32));
3118 Op = DAG.getNode(SystemZISD::VSUM, DL, VT, Op, Tmp);
3122 SDValue Tmp = DAG.getNode(SystemZISD::BYTE_MASK, DL, MVT::v16i8,
3123 DAG.getConstant(0, DL, MVT::i32));
3124 Op = DAG.getNode(SystemZISD::VSUM, DL, MVT::v4i32, Op, Tmp);
3125 Op = DAG.getNode(SystemZISD::VSUM, DL, VT, Op, Tmp);
3129 llvm_unreachable("Unexpected type");
3134 // Get the known-zero mask for the operand.
3135 APInt KnownZero, KnownOne;
3136 DAG.computeKnownBits(Op, KnownZero, KnownOne);
3137 unsigned NumSignificantBits = (~KnownZero).getActiveBits();
3138 if (NumSignificantBits == 0)
3139 return DAG.getConstant(0, DL, VT);
3141 // Skip known-zero high parts of the operand.
3142 int64_t OrigBitSize = VT.getSizeInBits();
3143 int64_t BitSize = (int64_t)1 << Log2_32_Ceil(NumSignificantBits);
3144 BitSize = std::min(BitSize, OrigBitSize);
3146 // The POPCNT instruction counts the number of bits in each byte.
3147 Op = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op);
3148 Op = DAG.getNode(SystemZISD::POPCNT, DL, MVT::i64, Op);
3149 Op = DAG.getNode(ISD::TRUNCATE, DL, VT, Op);
3151 // Add up per-byte counts in a binary tree. All bits of Op at
3152 // position larger than BitSize remain zero throughout.
3153 for (int64_t I = BitSize / 2; I >= 8; I = I / 2) {
3154 SDValue Tmp = DAG.getNode(ISD::SHL, DL, VT, Op, DAG.getConstant(I, DL, VT));
3155 if (BitSize != OrigBitSize)
3156 Tmp = DAG.getNode(ISD::AND, DL, VT, Tmp,
3157 DAG.getConstant(((uint64_t)1 << BitSize) - 1, DL, VT));
3158 Op = DAG.getNode(ISD::ADD, DL, VT, Op, Tmp);
3161 // Extract overall result from high byte.
3163 Op = DAG.getNode(ISD::SRL, DL, VT, Op,
3164 DAG.getConstant(BitSize - 8, DL, VT));
3169 SDValue SystemZTargetLowering::lowerATOMIC_FENCE(SDValue Op,
3170 SelectionDAG &DAG) const {
3172 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
3173 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
3174 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
3175 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
3177 // The only fence that needs an instruction is a sequentially-consistent
3178 // cross-thread fence.
3179 if (FenceOrdering == AtomicOrdering::SequentiallyConsistent &&
3180 FenceScope == CrossThread) {
3181 return SDValue(DAG.getMachineNode(SystemZ::Serialize, DL, MVT::Other,
3186 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
3187 return DAG.getNode(SystemZISD::MEMBARRIER, DL, MVT::Other, Op.getOperand(0));
3190 // Op is an atomic load. Lower it into a normal volatile load.
3191 SDValue SystemZTargetLowering::lowerATOMIC_LOAD(SDValue Op,
3192 SelectionDAG &DAG) const {
3193 auto *Node = cast<AtomicSDNode>(Op.getNode());
3194 return DAG.getExtLoad(ISD::EXTLOAD, SDLoc(Op), Op.getValueType(),
3195 Node->getChain(), Node->getBasePtr(),
3196 Node->getMemoryVT(), Node->getMemOperand());
3199 // Op is an atomic store. Lower it into a normal volatile store followed
3200 // by a serialization.
3201 SDValue SystemZTargetLowering::lowerATOMIC_STORE(SDValue Op,
3202 SelectionDAG &DAG) const {
3203 auto *Node = cast<AtomicSDNode>(Op.getNode());
3204 SDValue Chain = DAG.getTruncStore(Node->getChain(), SDLoc(Op), Node->getVal(),
3205 Node->getBasePtr(), Node->getMemoryVT(),
3206 Node->getMemOperand());
3207 return SDValue(DAG.getMachineNode(SystemZ::Serialize, SDLoc(Op), MVT::Other,
3211 // Op is an 8-, 16-bit or 32-bit ATOMIC_LOAD_* operation. Lower the first
3212 // two into the fullword ATOMIC_LOADW_* operation given by Opcode.
3213 SDValue SystemZTargetLowering::lowerATOMIC_LOAD_OP(SDValue Op,
3215 unsigned Opcode) const {
3216 auto *Node = cast<AtomicSDNode>(Op.getNode());
3218 // 32-bit operations need no code outside the main loop.
3219 EVT NarrowVT = Node->getMemoryVT();
3220 EVT WideVT = MVT::i32;
3221 if (NarrowVT == WideVT)
3224 int64_t BitSize = NarrowVT.getSizeInBits();
3225 SDValue ChainIn = Node->getChain();
3226 SDValue Addr = Node->getBasePtr();
3227 SDValue Src2 = Node->getVal();
3228 MachineMemOperand *MMO = Node->getMemOperand();
3230 EVT PtrVT = Addr.getValueType();
3232 // Convert atomic subtracts of constants into additions.
3233 if (Opcode == SystemZISD::ATOMIC_LOADW_SUB)
3234 if (auto *Const = dyn_cast<ConstantSDNode>(Src2)) {
3235 Opcode = SystemZISD::ATOMIC_LOADW_ADD;
3236 Src2 = DAG.getConstant(-Const->getSExtValue(), DL, Src2.getValueType());
3239 // Get the address of the containing word.
3240 SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr,
3241 DAG.getConstant(-4, DL, PtrVT));
3243 // Get the number of bits that the word must be rotated left in order
3244 // to bring the field to the top bits of a GR32.
3245 SDValue BitShift = DAG.getNode(ISD::SHL, DL, PtrVT, Addr,
3246 DAG.getConstant(3, DL, PtrVT));
3247 BitShift = DAG.getNode(ISD::TRUNCATE, DL, WideVT, BitShift);
3249 // Get the complementing shift amount, for rotating a field in the top
3250 // bits back to its proper position.
3251 SDValue NegBitShift = DAG.getNode(ISD::SUB, DL, WideVT,
3252 DAG.getConstant(0, DL, WideVT), BitShift);
3254 // Extend the source operand to 32 bits and prepare it for the inner loop.
3255 // ATOMIC_SWAPW uses RISBG to rotate the field left, but all other
3256 // operations require the source to be shifted in advance. (This shift
3257 // can be folded if the source is constant.) For AND and NAND, the lower
3258 // bits must be set, while for other opcodes they should be left clear.
3259 if (Opcode != SystemZISD::ATOMIC_SWAPW)
3260 Src2 = DAG.getNode(ISD::SHL, DL, WideVT, Src2,
3261 DAG.getConstant(32 - BitSize, DL, WideVT));
3262 if (Opcode == SystemZISD::ATOMIC_LOADW_AND ||
3263 Opcode == SystemZISD::ATOMIC_LOADW_NAND)
3264 Src2 = DAG.getNode(ISD::OR, DL, WideVT, Src2,
3265 DAG.getConstant(uint32_t(-1) >> BitSize, DL, WideVT));
3267 // Construct the ATOMIC_LOADW_* node.
3268 SDVTList VTList = DAG.getVTList(WideVT, MVT::Other);
3269 SDValue Ops[] = { ChainIn, AlignedAddr, Src2, BitShift, NegBitShift,
3270 DAG.getConstant(BitSize, DL, WideVT) };
3271 SDValue AtomicOp = DAG.getMemIntrinsicNode(Opcode, DL, VTList, Ops,
3274 // Rotate the result of the final CS so that the field is in the lower
3275 // bits of a GR32, then truncate it.
3276 SDValue ResultShift = DAG.getNode(ISD::ADD, DL, WideVT, BitShift,
3277 DAG.getConstant(BitSize, DL, WideVT));
3278 SDValue Result = DAG.getNode(ISD::ROTL, DL, WideVT, AtomicOp, ResultShift);
3280 SDValue RetOps[2] = { Result, AtomicOp.getValue(1) };
3281 return DAG.getMergeValues(RetOps, DL);
3284 // Op is an ATOMIC_LOAD_SUB operation. Lower 8- and 16-bit operations
3285 // into ATOMIC_LOADW_SUBs and decide whether to convert 32- and 64-bit
3286 // operations into additions.
3287 SDValue SystemZTargetLowering::lowerATOMIC_LOAD_SUB(SDValue Op,
3288 SelectionDAG &DAG) const {
3289 auto *Node = cast<AtomicSDNode>(Op.getNode());
3290 EVT MemVT = Node->getMemoryVT();
3291 if (MemVT == MVT::i32 || MemVT == MVT::i64) {
3292 // A full-width operation.
3293 assert(Op.getValueType() == MemVT && "Mismatched VTs");
3294 SDValue Src2 = Node->getVal();
3298 if (auto *Op2 = dyn_cast<ConstantSDNode>(Src2)) {
3299 // Use an addition if the operand is constant and either LAA(G) is
3300 // available or the negative value is in the range of A(G)FHI.
3301 int64_t Value = (-Op2->getAPIntValue()).getSExtValue();
3302 if (isInt<32>(Value) || Subtarget.hasInterlockedAccess1())
3303 NegSrc2 = DAG.getConstant(Value, DL, MemVT);
3304 } else if (Subtarget.hasInterlockedAccess1())
3305 // Use LAA(G) if available.
3306 NegSrc2 = DAG.getNode(ISD::SUB, DL, MemVT, DAG.getConstant(0, DL, MemVT),
3309 if (NegSrc2.getNode())
3310 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, DL, MemVT,
3311 Node->getChain(), Node->getBasePtr(), NegSrc2,
3312 Node->getMemOperand());
3314 // Use the node as-is.
3318 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_SUB);
3321 // Node is an 8- or 16-bit ATOMIC_CMP_SWAP operation. Lower the first two
3322 // into a fullword ATOMIC_CMP_SWAPW operation.
3323 SDValue SystemZTargetLowering::lowerATOMIC_CMP_SWAP(SDValue Op,
3324 SelectionDAG &DAG) const {
3325 auto *Node = cast<AtomicSDNode>(Op.getNode());
3327 // We have native support for 32-bit compare and swap.
3328 EVT NarrowVT = Node->getMemoryVT();
3329 EVT WideVT = MVT::i32;
3330 if (NarrowVT == WideVT)
3333 int64_t BitSize = NarrowVT.getSizeInBits();
3334 SDValue ChainIn = Node->getOperand(0);
3335 SDValue Addr = Node->getOperand(1);
3336 SDValue CmpVal = Node->getOperand(2);
3337 SDValue SwapVal = Node->getOperand(3);
3338 MachineMemOperand *MMO = Node->getMemOperand();
3340 EVT PtrVT = Addr.getValueType();
3342 // Get the address of the containing word.
3343 SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr,
3344 DAG.getConstant(-4, DL, PtrVT));
3346 // Get the number of bits that the word must be rotated left in order
3347 // to bring the field to the top bits of a GR32.
3348 SDValue BitShift = DAG.getNode(ISD::SHL, DL, PtrVT, Addr,
3349 DAG.getConstant(3, DL, PtrVT));
3350 BitShift = DAG.getNode(ISD::TRUNCATE, DL, WideVT, BitShift);
3352 // Get the complementing shift amount, for rotating a field in the top
3353 // bits back to its proper position.
3354 SDValue NegBitShift = DAG.getNode(ISD::SUB, DL, WideVT,
3355 DAG.getConstant(0, DL, WideVT), BitShift);
3357 // Construct the ATOMIC_CMP_SWAPW node.
3358 SDVTList VTList = DAG.getVTList(WideVT, MVT::Other);
3359 SDValue Ops[] = { ChainIn, AlignedAddr, CmpVal, SwapVal, BitShift,
3360 NegBitShift, DAG.getConstant(BitSize, DL, WideVT) };
3361 SDValue AtomicOp = DAG.getMemIntrinsicNode(SystemZISD::ATOMIC_CMP_SWAPW, DL,
3362 VTList, Ops, NarrowVT, MMO);
3366 SDValue SystemZTargetLowering::lowerSTACKSAVE(SDValue Op,
3367 SelectionDAG &DAG) const {
3368 MachineFunction &MF = DAG.getMachineFunction();
3369 MF.getInfo<SystemZMachineFunctionInfo>()->setManipulatesSP(true);
3370 return DAG.getCopyFromReg(Op.getOperand(0), SDLoc(Op),
3371 SystemZ::R15D, Op.getValueType());
3374 SDValue SystemZTargetLowering::lowerSTACKRESTORE(SDValue Op,
3375 SelectionDAG &DAG) const {
3376 MachineFunction &MF = DAG.getMachineFunction();
3377 MF.getInfo<SystemZMachineFunctionInfo>()->setManipulatesSP(true);
3378 bool StoreBackchain = MF.getFunction()->hasFnAttribute("backchain");
3380 SDValue Chain = Op.getOperand(0);
3381 SDValue NewSP = Op.getOperand(1);
3385 if (StoreBackchain) {
3386 SDValue OldSP = DAG.getCopyFromReg(Chain, DL, SystemZ::R15D, MVT::i64);
3387 Backchain = DAG.getLoad(MVT::i64, DL, Chain, OldSP, MachinePointerInfo());
3390 Chain = DAG.getCopyToReg(Chain, DL, SystemZ::R15D, NewSP);
3393 Chain = DAG.getStore(Chain, DL, Backchain, NewSP, MachinePointerInfo());
3398 SDValue SystemZTargetLowering::lowerPREFETCH(SDValue Op,
3399 SelectionDAG &DAG) const {
3400 bool IsData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
3402 // Just preserve the chain.
3403 return Op.getOperand(0);
3406 bool IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
3407 unsigned Code = IsWrite ? SystemZ::PFD_WRITE : SystemZ::PFD_READ;
3408 auto *Node = cast<MemIntrinsicSDNode>(Op.getNode());
3411 DAG.getConstant(Code, DL, MVT::i32),
3414 return DAG.getMemIntrinsicNode(SystemZISD::PREFETCH, DL,
3415 Node->getVTList(), Ops,
3416 Node->getMemoryVT(), Node->getMemOperand());
3419 // Return an i32 that contains the value of CC immediately after After,
3420 // whose final operand must be MVT::Glue.
3421 static SDValue getCCResult(SelectionDAG &DAG, SDNode *After) {
3423 SDValue Glue = SDValue(After, After->getNumValues() - 1);
3424 SDValue IPM = DAG.getNode(SystemZISD::IPM, DL, MVT::i32, Glue);
3425 return DAG.getNode(ISD::SRL, DL, MVT::i32, IPM,
3426 DAG.getConstant(SystemZ::IPM_CC, DL, MVT::i32));
3430 SystemZTargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op,
3431 SelectionDAG &DAG) const {
3432 unsigned Opcode, CCValid;
3433 if (isIntrinsicWithCCAndChain(Op, Opcode, CCValid)) {
3434 assert(Op->getNumValues() == 2 && "Expected only CC result and chain");
3435 SDValue Glued = emitIntrinsicWithChainAndGlue(DAG, Op, Opcode);
3436 SDValue CC = getCCResult(DAG, Glued.getNode());
3437 DAG.ReplaceAllUsesOfValueWith(SDValue(Op.getNode(), 0), CC);
3445 SystemZTargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
3446 SelectionDAG &DAG) const {
3447 unsigned Opcode, CCValid;
3448 if (isIntrinsicWithCC(Op, Opcode, CCValid)) {
3449 SDValue Glued = emitIntrinsicWithGlue(DAG, Op, Opcode);
3450 SDValue CC = getCCResult(DAG, Glued.getNode());
3451 if (Op->getNumValues() == 1)
3453 assert(Op->getNumValues() == 2 && "Expected a CC and non-CC result");
3454 return DAG.getNode(ISD::MERGE_VALUES, SDLoc(Op), Op->getVTList(), Glued,
3458 unsigned Id = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3460 case Intrinsic::thread_pointer:
3461 return lowerThreadPointer(SDLoc(Op), DAG);
3463 case Intrinsic::s390_vpdi:
3464 return DAG.getNode(SystemZISD::PERMUTE_DWORDS, SDLoc(Op), Op.getValueType(),
3465 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
3467 case Intrinsic::s390_vperm:
3468 return DAG.getNode(SystemZISD::PERMUTE, SDLoc(Op), Op.getValueType(),
3469 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
3471 case Intrinsic::s390_vuphb:
3472 case Intrinsic::s390_vuphh:
3473 case Intrinsic::s390_vuphf:
3474 return DAG.getNode(SystemZISD::UNPACK_HIGH, SDLoc(Op), Op.getValueType(),
3477 case Intrinsic::s390_vuplhb:
3478 case Intrinsic::s390_vuplhh:
3479 case Intrinsic::s390_vuplhf:
3480 return DAG.getNode(SystemZISD::UNPACKL_HIGH, SDLoc(Op), Op.getValueType(),
3483 case Intrinsic::s390_vuplb:
3484 case Intrinsic::s390_vuplhw:
3485 case Intrinsic::s390_vuplf:
3486 return DAG.getNode(SystemZISD::UNPACK_LOW, SDLoc(Op), Op.getValueType(),
3489 case Intrinsic::s390_vupllb:
3490 case Intrinsic::s390_vupllh:
3491 case Intrinsic::s390_vupllf:
3492 return DAG.getNode(SystemZISD::UNPACKL_LOW, SDLoc(Op), Op.getValueType(),
3495 case Intrinsic::s390_vsumb:
3496 case Intrinsic::s390_vsumh:
3497 case Intrinsic::s390_vsumgh:
3498 case Intrinsic::s390_vsumgf:
3499 case Intrinsic::s390_vsumqf:
3500 case Intrinsic::s390_vsumqg:
3501 return DAG.getNode(SystemZISD::VSUM, SDLoc(Op), Op.getValueType(),
3502 Op.getOperand(1), Op.getOperand(2));
3509 // Says that SystemZISD operation Opcode can be used to perform the equivalent
3510 // of a VPERM with permute vector Bytes. If Opcode takes three operands,
3511 // Operand is the constant third operand, otherwise it is the number of
3512 // bytes in each element of the result.
3516 unsigned char Bytes[SystemZ::VectorBytes];
3520 static const Permute PermuteForms[] = {
3522 { SystemZISD::MERGE_HIGH, 8,
3523 { 0, 1, 2, 3, 4, 5, 6, 7, 16, 17, 18, 19, 20, 21, 22, 23 } },
3525 { SystemZISD::MERGE_HIGH, 4,
3526 { 0, 1, 2, 3, 16, 17, 18, 19, 4, 5, 6, 7, 20, 21, 22, 23 } },
3528 { SystemZISD::MERGE_HIGH, 2,
3529 { 0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23 } },
3531 { SystemZISD::MERGE_HIGH, 1,
3532 { 0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23 } },
3534 { SystemZISD::MERGE_LOW, 8,
3535 { 8, 9, 10, 11, 12, 13, 14, 15, 24, 25, 26, 27, 28, 29, 30, 31 } },
3537 { SystemZISD::MERGE_LOW, 4,
3538 { 8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31 } },
3540 { SystemZISD::MERGE_LOW, 2,
3541 { 8, 9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, 30, 31 } },
3543 { SystemZISD::MERGE_LOW, 1,
3544 { 8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31 } },
3546 { SystemZISD::PACK, 4,
3547 { 4, 5, 6, 7, 12, 13, 14, 15, 20, 21, 22, 23, 28, 29, 30, 31 } },
3549 { SystemZISD::PACK, 2,
3550 { 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31 } },
3552 { SystemZISD::PACK, 1,
3553 { 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 } },
3554 // VPDI V1, V2, 4 (low half of V1, high half of V2)
3555 { SystemZISD::PERMUTE_DWORDS, 4,
3556 { 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 } },
3557 // VPDI V1, V2, 1 (high half of V1, low half of V2)
3558 { SystemZISD::PERMUTE_DWORDS, 1,
3559 { 0, 1, 2, 3, 4, 5, 6, 7, 24, 25, 26, 27, 28, 29, 30, 31 } }
3562 // Called after matching a vector shuffle against a particular pattern.
3563 // Both the original shuffle and the pattern have two vector operands.
3564 // OpNos[0] is the operand of the original shuffle that should be used for
3565 // operand 0 of the pattern, or -1 if operand 0 of the pattern can be anything.
3566 // OpNos[1] is the same for operand 1 of the pattern. Resolve these -1s and
3567 // set OpNo0 and OpNo1 to the shuffle operands that should actually be used
3568 // for operands 0 and 1 of the pattern.
3569 static bool chooseShuffleOpNos(int *OpNos, unsigned &OpNo0, unsigned &OpNo1) {
3573 OpNo0 = OpNo1 = OpNos[1];
3574 } else if (OpNos[1] < 0) {
3575 OpNo0 = OpNo1 = OpNos[0];
3583 // Bytes is a VPERM-like permute vector, except that -1 is used for
3584 // undefined bytes. Return true if the VPERM can be implemented using P.
3585 // When returning true set OpNo0 to the VPERM operand that should be
3586 // used for operand 0 of P and likewise OpNo1 for operand 1 of P.
3588 // For example, if swapping the VPERM operands allows P to match, OpNo0
3589 // will be 1 and OpNo1 will be 0. If instead Bytes only refers to one
3590 // operand, but rewriting it to use two duplicated operands allows it to
3591 // match P, then OpNo0 and OpNo1 will be the same.
3592 static bool matchPermute(const SmallVectorImpl<int> &Bytes, const Permute &P,
3593 unsigned &OpNo0, unsigned &OpNo1) {
3594 int OpNos[] = { -1, -1 };
3595 for (unsigned I = 0; I < SystemZ::VectorBytes; ++I) {
3598 // Make sure that the two permute vectors use the same suboperand
3599 // byte number. Only the operand numbers (the high bits) are
3600 // allowed to differ.
3601 if ((Elt ^ P.Bytes[I]) & (SystemZ::VectorBytes - 1))
3603 int ModelOpNo = P.Bytes[I] / SystemZ::VectorBytes;
3604 int RealOpNo = unsigned(Elt) / SystemZ::VectorBytes;
3605 // Make sure that the operand mappings are consistent with previous
3607 if (OpNos[ModelOpNo] == 1 - RealOpNo)
3609 OpNos[ModelOpNo] = RealOpNo;
3612 return chooseShuffleOpNos(OpNos, OpNo0, OpNo1);
3615 // As above, but search for a matching permute.
3616 static const Permute *matchPermute(const SmallVectorImpl<int> &Bytes,
3617 unsigned &OpNo0, unsigned &OpNo1) {
3618 for (auto &P : PermuteForms)
3619 if (matchPermute(Bytes, P, OpNo0, OpNo1))
3624 // Bytes is a VPERM-like permute vector, except that -1 is used for
3625 // undefined bytes. This permute is an operand of an outer permute.
3626 // See whether redistributing the -1 bytes gives a shuffle that can be
3627 // implemented using P. If so, set Transform to a VPERM-like permute vector
3628 // that, when applied to the result of P, gives the original permute in Bytes.
3629 static bool matchDoublePermute(const SmallVectorImpl<int> &Bytes,
3631 SmallVectorImpl<int> &Transform) {
3633 for (unsigned From = 0; From < SystemZ::VectorBytes; ++From) {
3634 int Elt = Bytes[From];
3636 // Byte number From of the result is undefined.
3637 Transform[From] = -1;
3639 while (P.Bytes[To] != Elt) {
3641 if (To == SystemZ::VectorBytes)
3644 Transform[From] = To;
3650 // As above, but search for a matching permute.
3651 static const Permute *matchDoublePermute(const SmallVectorImpl<int> &Bytes,
3652 SmallVectorImpl<int> &Transform) {
3653 for (auto &P : PermuteForms)
3654 if (matchDoublePermute(Bytes, P, Transform))
3659 // Convert the mask of the given VECTOR_SHUFFLE into a byte-level mask,
3660 // as if it had type vNi8.
3661 static void getVPermMask(ShuffleVectorSDNode *VSN,
3662 SmallVectorImpl<int> &Bytes) {
3663 EVT VT = VSN->getValueType(0);
3664 unsigned NumElements = VT.getVectorNumElements();
3665 unsigned BytesPerElement = VT.getVectorElementType().getStoreSize();
3666 Bytes.resize(NumElements * BytesPerElement, -1);
3667 for (unsigned I = 0; I < NumElements; ++I) {
3668 int Index = VSN->getMaskElt(I);
3670 for (unsigned J = 0; J < BytesPerElement; ++J)
3671 Bytes[I * BytesPerElement + J] = Index * BytesPerElement + J;
3675 // Bytes is a VPERM-like permute vector, except that -1 is used for
3676 // undefined bytes. See whether bytes [Start, Start + BytesPerElement) of
3677 // the result come from a contiguous sequence of bytes from one input.
3678 // Set Base to the selector for the first byte if so.
3679 static bool getShuffleInput(const SmallVectorImpl<int> &Bytes, unsigned Start,
3680 unsigned BytesPerElement, int &Base) {
3682 for (unsigned I = 0; I < BytesPerElement; ++I) {
3683 if (Bytes[Start + I] >= 0) {
3684 unsigned Elem = Bytes[Start + I];
3687 // Make sure the bytes would come from one input operand.
3688 if (unsigned(Base) % Bytes.size() + BytesPerElement > Bytes.size())
3690 } else if (unsigned(Base) != Elem - I)
3697 // Bytes is a VPERM-like permute vector, except that -1 is used for
3698 // undefined bytes. Return true if it can be performed using VSLDI.
3699 // When returning true, set StartIndex to the shift amount and OpNo0
3700 // and OpNo1 to the VPERM operands that should be used as the first
3701 // and second shift operand respectively.
3702 static bool isShlDoublePermute(const SmallVectorImpl<int> &Bytes,
3703 unsigned &StartIndex, unsigned &OpNo0,
3705 int OpNos[] = { -1, -1 };
3707 for (unsigned I = 0; I < 16; ++I) {
3708 int Index = Bytes[I];
3710 int ExpectedShift = (Index - I) % SystemZ::VectorBytes;
3711 int ModelOpNo = unsigned(ExpectedShift + I) / SystemZ::VectorBytes;
3712 int RealOpNo = unsigned(Index) / SystemZ::VectorBytes;
3714 Shift = ExpectedShift;
3715 else if (Shift != ExpectedShift)
3717 // Make sure that the operand mappings are consistent with previous
3719 if (OpNos[ModelOpNo] == 1 - RealOpNo)
3721 OpNos[ModelOpNo] = RealOpNo;
3725 return chooseShuffleOpNos(OpNos, OpNo0, OpNo1);
3728 // Create a node that performs P on operands Op0 and Op1, casting the
3729 // operands to the appropriate type. The type of the result is determined by P.
3730 static SDValue getPermuteNode(SelectionDAG &DAG, const SDLoc &DL,
3731 const Permute &P, SDValue Op0, SDValue Op1) {
3732 // VPDI (PERMUTE_DWORDS) always operates on v2i64s. The input
3733 // elements of a PACK are twice as wide as the outputs.
3734 unsigned InBytes = (P.Opcode == SystemZISD::PERMUTE_DWORDS ? 8 :
3735 P.Opcode == SystemZISD::PACK ? P.Operand * 2 :
3737 // Cast both operands to the appropriate type.
3738 MVT InVT = MVT::getVectorVT(MVT::getIntegerVT(InBytes * 8),
3739 SystemZ::VectorBytes / InBytes);
3740 Op0 = DAG.getNode(ISD::BITCAST, DL, InVT, Op0);
3741 Op1 = DAG.getNode(ISD::BITCAST, DL, InVT, Op1);
3743 if (P.Opcode == SystemZISD::PERMUTE_DWORDS) {
3744 SDValue Op2 = DAG.getConstant(P.Operand, DL, MVT::i32);
3745 Op = DAG.getNode(SystemZISD::PERMUTE_DWORDS, DL, InVT, Op0, Op1, Op2);
3746 } else if (P.Opcode == SystemZISD::PACK) {
3747 MVT OutVT = MVT::getVectorVT(MVT::getIntegerVT(P.Operand * 8),
3748 SystemZ::VectorBytes / P.Operand);
3749 Op = DAG.getNode(SystemZISD::PACK, DL, OutVT, Op0, Op1);
3751 Op = DAG.getNode(P.Opcode, DL, InVT, Op0, Op1);
3756 // Bytes is a VPERM-like permute vector, except that -1 is used for
3757 // undefined bytes. Implement it on operands Ops[0] and Ops[1] using
3759 static SDValue getGeneralPermuteNode(SelectionDAG &DAG, const SDLoc &DL,
3761 const SmallVectorImpl<int> &Bytes) {
3762 for (unsigned I = 0; I < 2; ++I)
3763 Ops[I] = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Ops[I]);
3765 // First see whether VSLDI can be used.
3766 unsigned StartIndex, OpNo0, OpNo1;
3767 if (isShlDoublePermute(Bytes, StartIndex, OpNo0, OpNo1))
3768 return DAG.getNode(SystemZISD::SHL_DOUBLE, DL, MVT::v16i8, Ops[OpNo0],
3769 Ops[OpNo1], DAG.getConstant(StartIndex, DL, MVT::i32));
3771 // Fall back on VPERM. Construct an SDNode for the permute vector.
3772 SDValue IndexNodes[SystemZ::VectorBytes];
3773 for (unsigned I = 0; I < SystemZ::VectorBytes; ++I)
3775 IndexNodes[I] = DAG.getConstant(Bytes[I], DL, MVT::i32);
3777 IndexNodes[I] = DAG.getUNDEF(MVT::i32);
3778 SDValue Op2 = DAG.getBuildVector(MVT::v16i8, DL, IndexNodes);
3779 return DAG.getNode(SystemZISD::PERMUTE, DL, MVT::v16i8, Ops[0], Ops[1], Op2);
3783 // Describes a general N-operand vector shuffle.
3784 struct GeneralShuffle {
3785 GeneralShuffle(EVT vt) : VT(vt) {}
3787 void add(SDValue, unsigned);
3788 SDValue getNode(SelectionDAG &, const SDLoc &);
3790 // The operands of the shuffle.
3791 SmallVector<SDValue, SystemZ::VectorBytes> Ops;
3793 // Index I is -1 if byte I of the result is undefined. Otherwise the
3794 // result comes from byte Bytes[I] % SystemZ::VectorBytes of operand
3795 // Bytes[I] / SystemZ::VectorBytes.
3796 SmallVector<int, SystemZ::VectorBytes> Bytes;
3798 // The type of the shuffle result.
3803 // Add an extra undefined element to the shuffle.
3804 void GeneralShuffle::addUndef() {
3805 unsigned BytesPerElement = VT.getVectorElementType().getStoreSize();
3806 for (unsigned I = 0; I < BytesPerElement; ++I)
3807 Bytes.push_back(-1);
3810 // Add an extra element to the shuffle, taking it from element Elem of Op.
3811 // A null Op indicates a vector input whose value will be calculated later;
3812 // there is at most one such input per shuffle and it always has the same
3813 // type as the result.
3814 void GeneralShuffle::add(SDValue Op, unsigned Elem) {
3815 unsigned BytesPerElement = VT.getVectorElementType().getStoreSize();
3817 // The source vector can have wider elements than the result,
3818 // either through an explicit TRUNCATE or because of type legalization.
3819 // We want the least significant part.
3820 EVT FromVT = Op.getNode() ? Op.getValueType() : VT;
3821 unsigned FromBytesPerElement = FromVT.getVectorElementType().getStoreSize();
3822 assert(FromBytesPerElement >= BytesPerElement &&
3823 "Invalid EXTRACT_VECTOR_ELT");
3824 unsigned Byte = ((Elem * FromBytesPerElement) % SystemZ::VectorBytes +
3825 (FromBytesPerElement - BytesPerElement));
3827 // Look through things like shuffles and bitcasts.
3828 while (Op.getNode()) {
3829 if (Op.getOpcode() == ISD::BITCAST)
3830 Op = Op.getOperand(0);
3831 else if (Op.getOpcode() == ISD::VECTOR_SHUFFLE && Op.hasOneUse()) {
3832 // See whether the bytes we need come from a contiguous part of one
3834 SmallVector<int, SystemZ::VectorBytes> OpBytes;
3835 getVPermMask(cast<ShuffleVectorSDNode>(Op), OpBytes);
3837 if (!getShuffleInput(OpBytes, Byte, BytesPerElement, NewByte))
3843 Op = Op.getOperand(unsigned(NewByte) / SystemZ::VectorBytes);
3844 Byte = unsigned(NewByte) % SystemZ::VectorBytes;
3845 } else if (Op.isUndef()) {
3852 // Make sure that the source of the extraction is in Ops.
3854 for (; OpNo < Ops.size(); ++OpNo)
3855 if (Ops[OpNo] == Op)
3857 if (OpNo == Ops.size())
3860 // Add the element to Bytes.
3861 unsigned Base = OpNo * SystemZ::VectorBytes + Byte;
3862 for (unsigned I = 0; I < BytesPerElement; ++I)
3863 Bytes.push_back(Base + I);
3866 // Return SDNodes for the completed shuffle.
3867 SDValue GeneralShuffle::getNode(SelectionDAG &DAG, const SDLoc &DL) {
3868 assert(Bytes.size() == SystemZ::VectorBytes && "Incomplete vector");
3870 if (Ops.size() == 0)
3871 return DAG.getUNDEF(VT);
3873 // Make sure that there are at least two shuffle operands.
3874 if (Ops.size() == 1)
3875 Ops.push_back(DAG.getUNDEF(MVT::v16i8));
3877 // Create a tree of shuffles, deferring root node until after the loop.
3878 // Try to redistribute the undefined elements of non-root nodes so that
3879 // the non-root shuffles match something like a pack or merge, then adjust
3880 // the parent node's permute vector to compensate for the new order.
3881 // Among other things, this copes with vectors like <2 x i16> that were
3882 // padded with undefined elements during type legalization.
3884 // In the best case this redistribution will lead to the whole tree
3885 // using packs and merges. It should rarely be a loss in other cases.
3886 unsigned Stride = 1;
3887 for (; Stride * 2 < Ops.size(); Stride *= 2) {
3888 for (unsigned I = 0; I < Ops.size() - Stride; I += Stride * 2) {
3889 SDValue SubOps[] = { Ops[I], Ops[I + Stride] };
3891 // Create a mask for just these two operands.
3892 SmallVector<int, SystemZ::VectorBytes> NewBytes(SystemZ::VectorBytes);
3893 for (unsigned J = 0; J < SystemZ::VectorBytes; ++J) {
3894 unsigned OpNo = unsigned(Bytes[J]) / SystemZ::VectorBytes;
3895 unsigned Byte = unsigned(Bytes[J]) % SystemZ::VectorBytes;
3898 else if (OpNo == I + Stride)
3899 NewBytes[J] = SystemZ::VectorBytes + Byte;
3903 // See if it would be better to reorganize NewMask to avoid using VPERM.
3904 SmallVector<int, SystemZ::VectorBytes> NewBytesMap(SystemZ::VectorBytes);
3905 if (const Permute *P = matchDoublePermute(NewBytes, NewBytesMap)) {
3906 Ops[I] = getPermuteNode(DAG, DL, *P, SubOps[0], SubOps[1]);
3907 // Applying NewBytesMap to Ops[I] gets back to NewBytes.
3908 for (unsigned J = 0; J < SystemZ::VectorBytes; ++J) {
3909 if (NewBytes[J] >= 0) {
3910 assert(unsigned(NewBytesMap[J]) < SystemZ::VectorBytes &&
3911 "Invalid double permute");
3912 Bytes[J] = I * SystemZ::VectorBytes + NewBytesMap[J];
3914 assert(NewBytesMap[J] < 0 && "Invalid double permute");
3917 // Just use NewBytes on the operands.
3918 Ops[I] = getGeneralPermuteNode(DAG, DL, SubOps, NewBytes);
3919 for (unsigned J = 0; J < SystemZ::VectorBytes; ++J)
3920 if (NewBytes[J] >= 0)
3921 Bytes[J] = I * SystemZ::VectorBytes + J;
3926 // Now we just have 2 inputs. Put the second operand in Ops[1].
3928 Ops[1] = Ops[Stride];
3929 for (unsigned I = 0; I < SystemZ::VectorBytes; ++I)
3930 if (Bytes[I] >= int(SystemZ::VectorBytes))
3931 Bytes[I] -= (Stride - 1) * SystemZ::VectorBytes;
3934 // Look for an instruction that can do the permute without resorting
3936 unsigned OpNo0, OpNo1;
3938 if (const Permute *P = matchPermute(Bytes, OpNo0, OpNo1))
3939 Op = getPermuteNode(DAG, DL, *P, Ops[OpNo0], Ops[OpNo1]);
3941 Op = getGeneralPermuteNode(DAG, DL, &Ops[0], Bytes);
3942 return DAG.getNode(ISD::BITCAST, DL, VT, Op);
3945 // Return true if the given BUILD_VECTOR is a scalar-to-vector conversion.
3946 static bool isScalarToVector(SDValue Op) {
3947 for (unsigned I = 1, E = Op.getNumOperands(); I != E; ++I)
3948 if (!Op.getOperand(I).isUndef())
3953 // Return a vector of type VT that contains Value in the first element.
3954 // The other elements don't matter.
3955 static SDValue buildScalarToVector(SelectionDAG &DAG, const SDLoc &DL, EVT VT,
3957 // If we have a constant, replicate it to all elements and let the
3958 // BUILD_VECTOR lowering take care of it.
3959 if (Value.getOpcode() == ISD::Constant ||
3960 Value.getOpcode() == ISD::ConstantFP) {
3961 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Value);
3962 return DAG.getBuildVector(VT, DL, Ops);
3964 if (Value.isUndef())
3965 return DAG.getUNDEF(VT);
3966 return DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VT, Value);
3969 // Return a vector of type VT in which Op0 is in element 0 and Op1 is in
3970 // element 1. Used for cases in which replication is cheap.
3971 static SDValue buildMergeScalars(SelectionDAG &DAG, const SDLoc &DL, EVT VT,
3972 SDValue Op0, SDValue Op1) {
3973 if (Op0.isUndef()) {
3975 return DAG.getUNDEF(VT);
3976 return DAG.getNode(SystemZISD::REPLICATE, DL, VT, Op1);
3979 return DAG.getNode(SystemZISD::REPLICATE, DL, VT, Op0);
3980 return DAG.getNode(SystemZISD::MERGE_HIGH, DL, VT,
3981 buildScalarToVector(DAG, DL, VT, Op0),
3982 buildScalarToVector(DAG, DL, VT, Op1));
3985 // Extend GPR scalars Op0 and Op1 to doublewords and return a v2i64
3987 static SDValue joinDwords(SelectionDAG &DAG, const SDLoc &DL, SDValue Op0,
3989 if (Op0.isUndef() && Op1.isUndef())
3990 return DAG.getUNDEF(MVT::v2i64);
3991 // If one of the two inputs is undefined then replicate the other one,
3992 // in order to avoid using another register unnecessarily.
3994 Op0 = Op1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op1);
3995 else if (Op1.isUndef())
3996 Op0 = Op1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op0);
3998 Op0 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op0);
3999 Op1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op1);
4001 return DAG.getNode(SystemZISD::JOIN_DWORDS, DL, MVT::v2i64, Op0, Op1);
4004 // Try to represent constant BUILD_VECTOR node BVN using a
4005 // SystemZISD::BYTE_MASK-style mask. Store the mask value in Mask
4007 static bool tryBuildVectorByteMask(BuildVectorSDNode *BVN, uint64_t &Mask) {
4008 EVT ElemVT = BVN->getValueType(0).getVectorElementType();
4009 unsigned BytesPerElement = ElemVT.getStoreSize();
4010 for (unsigned I = 0, E = BVN->getNumOperands(); I != E; ++I) {
4011 SDValue Op = BVN->getOperand(I);
4012 if (!Op.isUndef()) {
4014 if (Op.getOpcode() == ISD::Constant)
4015 Value = dyn_cast<ConstantSDNode>(Op)->getZExtValue();
4016 else if (Op.getOpcode() == ISD::ConstantFP)
4017 Value = (dyn_cast<ConstantFPSDNode>(Op)->getValueAPF().bitcastToAPInt()
4021 for (unsigned J = 0; J < BytesPerElement; ++J) {
4022 uint64_t Byte = (Value >> (J * 8)) & 0xff;
4024 Mask |= 1ULL << ((E - I - 1) * BytesPerElement + J);
4033 // Try to load a vector constant in which BitsPerElement-bit value Value
4034 // is replicated to fill the vector. VT is the type of the resulting
4035 // constant, which may have elements of a different size from BitsPerElement.
4036 // Return the SDValue of the constant on success, otherwise return
4038 static SDValue tryBuildVectorReplicate(SelectionDAG &DAG,
4039 const SystemZInstrInfo *TII,
4040 const SDLoc &DL, EVT VT, uint64_t Value,
4041 unsigned BitsPerElement) {
4042 // Signed 16-bit values can be replicated using VREPI.
4043 int64_t SignedValue = SignExtend64(Value, BitsPerElement);
4044 if (isInt<16>(SignedValue)) {
4045 MVT VecVT = MVT::getVectorVT(MVT::getIntegerVT(BitsPerElement),
4046 SystemZ::VectorBits / BitsPerElement);
4047 SDValue Op = DAG.getNode(SystemZISD::REPLICATE, DL, VecVT,
4048 DAG.getConstant(SignedValue, DL, MVT::i32));
4049 return DAG.getNode(ISD::BITCAST, DL, VT, Op);
4051 // See whether rotating the constant left some N places gives a value that
4052 // is one less than a power of 2 (i.e. all zeros followed by all ones).
4053 // If so we can use VGM.
4054 unsigned Start, End;
4055 if (TII->isRxSBGMask(Value, BitsPerElement, Start, End)) {
4056 // isRxSBGMask returns the bit numbers for a full 64-bit value,
4057 // with 0 denoting 1 << 63 and 63 denoting 1. Convert them to
4058 // bit numbers for an BitsPerElement value, so that 0 denotes
4059 // 1 << (BitsPerElement-1).
4060 Start -= 64 - BitsPerElement;
4061 End -= 64 - BitsPerElement;
4062 MVT VecVT = MVT::getVectorVT(MVT::getIntegerVT(BitsPerElement),
4063 SystemZ::VectorBits / BitsPerElement);
4064 SDValue Op = DAG.getNode(SystemZISD::ROTATE_MASK, DL, VecVT,
4065 DAG.getConstant(Start, DL, MVT::i32),
4066 DAG.getConstant(End, DL, MVT::i32));
4067 return DAG.getNode(ISD::BITCAST, DL, VT, Op);
4072 // If a BUILD_VECTOR contains some EXTRACT_VECTOR_ELTs, it's usually
4073 // better to use VECTOR_SHUFFLEs on them, only using BUILD_VECTOR for
4074 // the non-EXTRACT_VECTOR_ELT elements. See if the given BUILD_VECTOR
4075 // would benefit from this representation and return it if so.
4076 static SDValue tryBuildVectorShuffle(SelectionDAG &DAG,
4077 BuildVectorSDNode *BVN) {
4078 EVT VT = BVN->getValueType(0);
4079 unsigned NumElements = VT.getVectorNumElements();
4081 // Represent the BUILD_VECTOR as an N-operand VECTOR_SHUFFLE-like operation
4082 // on byte vectors. If there are non-EXTRACT_VECTOR_ELT elements that still
4083 // need a BUILD_VECTOR, add an additional placeholder operand for that
4084 // BUILD_VECTOR and store its operands in ResidueOps.
4085 GeneralShuffle GS(VT);
4086 SmallVector<SDValue, SystemZ::VectorBytes> ResidueOps;
4087 bool FoundOne = false;
4088 for (unsigned I = 0; I < NumElements; ++I) {
4089 SDValue Op = BVN->getOperand(I);
4090 if (Op.getOpcode() == ISD::TRUNCATE)
4091 Op = Op.getOperand(0);
4092 if (Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
4093 Op.getOperand(1).getOpcode() == ISD::Constant) {
4094 unsigned Elem = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4095 GS.add(Op.getOperand(0), Elem);
4097 } else if (Op.isUndef()) {
4100 GS.add(SDValue(), ResidueOps.size());
4101 ResidueOps.push_back(BVN->getOperand(I));
4105 // Nothing to do if there are no EXTRACT_VECTOR_ELTs.
4109 // Create the BUILD_VECTOR for the remaining elements, if any.
4110 if (!ResidueOps.empty()) {
4111 while (ResidueOps.size() < NumElements)
4112 ResidueOps.push_back(DAG.getUNDEF(ResidueOps[0].getValueType()));
4113 for (auto &Op : GS.Ops) {
4114 if (!Op.getNode()) {
4115 Op = DAG.getBuildVector(VT, SDLoc(BVN), ResidueOps);
4120 return GS.getNode(DAG, SDLoc(BVN));
4123 // Combine GPR scalar values Elems into a vector of type VT.
4124 static SDValue buildVector(SelectionDAG &DAG, const SDLoc &DL, EVT VT,
4125 SmallVectorImpl<SDValue> &Elems) {
4126 // See whether there is a single replicated value.
4128 unsigned int NumElements = Elems.size();
4129 unsigned int Count = 0;
4130 for (auto Elem : Elems) {
4131 if (!Elem.isUndef()) {
4132 if (!Single.getNode())
4134 else if (Elem != Single) {
4141 // There are three cases here:
4143 // - if the only defined element is a loaded one, the best sequence
4144 // is a replicating load.
4146 // - otherwise, if the only defined element is an i64 value, we will
4147 // end up with the same VLVGP sequence regardless of whether we short-cut
4148 // for replication or fall through to the later code.
4150 // - otherwise, if the only defined element is an i32 or smaller value,
4151 // we would need 2 instructions to replicate it: VLVGP followed by VREPx.
4152 // This is only a win if the single defined element is used more than once.
4153 // In other cases we're better off using a single VLVGx.
4154 if (Single.getNode() && (Count > 1 || Single.getOpcode() == ISD::LOAD))
4155 return DAG.getNode(SystemZISD::REPLICATE, DL, VT, Single);
4157 // The best way of building a v2i64 from two i64s is to use VLVGP.
4158 if (VT == MVT::v2i64)
4159 return joinDwords(DAG, DL, Elems[0], Elems[1]);
4161 // Use a 64-bit merge high to combine two doubles.
4162 if (VT == MVT::v2f64)
4163 return buildMergeScalars(DAG, DL, VT, Elems[0], Elems[1]);
4165 // Build v4f32 values directly from the FPRs:
4167 // <Axxx> <Bxxx> <Cxxxx> <Dxxx>
4172 if (VT == MVT::v4f32) {
4173 SDValue Op01 = buildMergeScalars(DAG, DL, VT, Elems[0], Elems[1]);
4174 SDValue Op23 = buildMergeScalars(DAG, DL, VT, Elems[2], Elems[3]);
4175 // Avoid unnecessary undefs by reusing the other operand.
4178 else if (Op23.isUndef())
4180 // Merging identical replications is a no-op.
4181 if (Op01.getOpcode() == SystemZISD::REPLICATE && Op01 == Op23)
4183 Op01 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Op01);
4184 Op23 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Op23);
4185 SDValue Op = DAG.getNode(SystemZISD::MERGE_HIGH,
4186 DL, MVT::v2i64, Op01, Op23);
4187 return DAG.getNode(ISD::BITCAST, DL, VT, Op);
4190 // Collect the constant terms.
4191 SmallVector<SDValue, SystemZ::VectorBytes> Constants(NumElements, SDValue());
4192 SmallVector<bool, SystemZ::VectorBytes> Done(NumElements, false);
4194 unsigned NumConstants = 0;
4195 for (unsigned I = 0; I < NumElements; ++I) {
4196 SDValue Elem = Elems[I];
4197 if (Elem.getOpcode() == ISD::Constant ||
4198 Elem.getOpcode() == ISD::ConstantFP) {
4200 Constants[I] = Elem;
4204 // If there was at least one constant, fill in the other elements of
4205 // Constants with undefs to get a full vector constant and use that
4206 // as the starting point.
4208 if (NumConstants > 0) {
4209 for (unsigned I = 0; I < NumElements; ++I)
4210 if (!Constants[I].getNode())
4211 Constants[I] = DAG.getUNDEF(Elems[I].getValueType());
4212 Result = DAG.getBuildVector(VT, DL, Constants);
4214 // Otherwise try to use VLVGP to start the sequence in order to
4215 // avoid a false dependency on any previous contents of the vector
4216 // register. This only makes sense if one of the associated elements
4218 unsigned I1 = NumElements / 2 - 1;
4219 unsigned I2 = NumElements - 1;
4220 bool Def1 = !Elems[I1].isUndef();
4221 bool Def2 = !Elems[I2].isUndef();
4223 SDValue Elem1 = Elems[Def1 ? I1 : I2];
4224 SDValue Elem2 = Elems[Def2 ? I2 : I1];
4225 Result = DAG.getNode(ISD::BITCAST, DL, VT,
4226 joinDwords(DAG, DL, Elem1, Elem2));
4230 Result = DAG.getUNDEF(VT);
4233 // Use VLVGx to insert the other elements.
4234 for (unsigned I = 0; I < NumElements; ++I)
4235 if (!Done[I] && !Elems[I].isUndef())
4236 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, Result, Elems[I],
4237 DAG.getConstant(I, DL, MVT::i32));
4241 SDValue SystemZTargetLowering::lowerBUILD_VECTOR(SDValue Op,
4242 SelectionDAG &DAG) const {
4243 const SystemZInstrInfo *TII =
4244 static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
4245 auto *BVN = cast<BuildVectorSDNode>(Op.getNode());
4247 EVT VT = Op.getValueType();
4249 if (BVN->isConstant()) {
4250 // Try using VECTOR GENERATE BYTE MASK. This is the architecturally-
4251 // preferred way of creating all-zero and all-one vectors so give it
4252 // priority over other methods below.
4254 if (tryBuildVectorByteMask(BVN, Mask)) {
4255 SDValue Op = DAG.getNode(SystemZISD::BYTE_MASK, DL, MVT::v16i8,
4256 DAG.getConstant(Mask, DL, MVT::i32));
4257 return DAG.getNode(ISD::BITCAST, DL, VT, Op);
4260 // Try using some form of replication.
4261 APInt SplatBits, SplatUndef;
4262 unsigned SplatBitSize;
4264 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs,
4266 SplatBitSize <= 64) {
4267 // First try assuming that any undefined bits above the highest set bit
4268 // and below the lowest set bit are 1s. This increases the likelihood of
4269 // being able to use a sign-extended element value in VECTOR REPLICATE
4270 // IMMEDIATE or a wraparound mask in VECTOR GENERATE MASK.
4271 uint64_t SplatBitsZ = SplatBits.getZExtValue();
4272 uint64_t SplatUndefZ = SplatUndef.getZExtValue();
4273 uint64_t Lower = (SplatUndefZ
4274 & ((uint64_t(1) << findFirstSet(SplatBitsZ)) - 1));
4275 uint64_t Upper = (SplatUndefZ
4276 & ~((uint64_t(1) << findLastSet(SplatBitsZ)) - 1));
4277 uint64_t Value = SplatBitsZ | Upper | Lower;
4278 SDValue Op = tryBuildVectorReplicate(DAG, TII, DL, VT, Value,
4283 // Now try assuming that any undefined bits between the first and
4284 // last defined set bits are set. This increases the chances of
4285 // using a non-wraparound mask.
4286 uint64_t Middle = SplatUndefZ & ~Upper & ~Lower;
4287 Value = SplatBitsZ | Middle;
4288 Op = tryBuildVectorReplicate(DAG, TII, DL, VT, Value, SplatBitSize);
4293 // Fall back to loading it from memory.
4297 // See if we should use shuffles to construct the vector from other vectors.
4298 if (SDValue Res = tryBuildVectorShuffle(DAG, BVN))
4301 // Detect SCALAR_TO_VECTOR conversions.
4302 if (isOperationLegal(ISD::SCALAR_TO_VECTOR, VT) && isScalarToVector(Op))
4303 return buildScalarToVector(DAG, DL, VT, Op.getOperand(0));
4305 // Otherwise use buildVector to build the vector up from GPRs.
4306 unsigned NumElements = Op.getNumOperands();
4307 SmallVector<SDValue, SystemZ::VectorBytes> Ops(NumElements);
4308 for (unsigned I = 0; I < NumElements; ++I)
4309 Ops[I] = Op.getOperand(I);
4310 return buildVector(DAG, DL, VT, Ops);
4313 SDValue SystemZTargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,
4314 SelectionDAG &DAG) const {
4315 auto *VSN = cast<ShuffleVectorSDNode>(Op.getNode());
4317 EVT VT = Op.getValueType();
4318 unsigned NumElements = VT.getVectorNumElements();
4320 if (VSN->isSplat()) {
4321 SDValue Op0 = Op.getOperand(0);
4322 unsigned Index = VSN->getSplatIndex();
4323 assert(Index < VT.getVectorNumElements() &&
4324 "Splat index should be defined and in first operand");
4325 // See whether the value we're splatting is directly available as a scalar.
4326 if ((Index == 0 && Op0.getOpcode() == ISD::SCALAR_TO_VECTOR) ||
4327 Op0.getOpcode() == ISD::BUILD_VECTOR)
4328 return DAG.getNode(SystemZISD::REPLICATE, DL, VT, Op0.getOperand(Index));
4329 // Otherwise keep it as a vector-to-vector operation.
4330 return DAG.getNode(SystemZISD::SPLAT, DL, VT, Op.getOperand(0),
4331 DAG.getConstant(Index, DL, MVT::i32));
4334 GeneralShuffle GS(VT);
4335 for (unsigned I = 0; I < NumElements; ++I) {
4336 int Elt = VSN->getMaskElt(I);
4340 GS.add(Op.getOperand(unsigned(Elt) / NumElements),
4341 unsigned(Elt) % NumElements);
4343 return GS.getNode(DAG, SDLoc(VSN));
4346 SDValue SystemZTargetLowering::lowerSCALAR_TO_VECTOR(SDValue Op,
4347 SelectionDAG &DAG) const {
4349 // Just insert the scalar into element 0 of an undefined vector.
4350 return DAG.getNode(ISD::INSERT_VECTOR_ELT, DL,
4351 Op.getValueType(), DAG.getUNDEF(Op.getValueType()),
4352 Op.getOperand(0), DAG.getConstant(0, DL, MVT::i32));
4355 SDValue SystemZTargetLowering::lowerINSERT_VECTOR_ELT(SDValue Op,
4356 SelectionDAG &DAG) const {
4357 // Handle insertions of floating-point values.
4359 SDValue Op0 = Op.getOperand(0);
4360 SDValue Op1 = Op.getOperand(1);
4361 SDValue Op2 = Op.getOperand(2);
4362 EVT VT = Op.getValueType();
4364 // Insertions into constant indices of a v2f64 can be done using VPDI.
4365 // However, if the inserted value is a bitcast or a constant then it's
4366 // better to use GPRs, as below.
4367 if (VT == MVT::v2f64 &&
4368 Op1.getOpcode() != ISD::BITCAST &&
4369 Op1.getOpcode() != ISD::ConstantFP &&
4370 Op2.getOpcode() == ISD::Constant) {
4371 uint64_t Index = dyn_cast<ConstantSDNode>(Op2)->getZExtValue();
4372 unsigned Mask = VT.getVectorNumElements() - 1;
4377 // Otherwise bitcast to the equivalent integer form and insert via a GPR.
4378 MVT IntVT = MVT::getIntegerVT(VT.getScalarSizeInBits());
4379 MVT IntVecVT = MVT::getVectorVT(IntVT, VT.getVectorNumElements());
4380 SDValue Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, IntVecVT,
4381 DAG.getNode(ISD::BITCAST, DL, IntVecVT, Op0),
4382 DAG.getNode(ISD::BITCAST, DL, IntVT, Op1), Op2);
4383 return DAG.getNode(ISD::BITCAST, DL, VT, Res);
4387 SystemZTargetLowering::lowerEXTRACT_VECTOR_ELT(SDValue Op,
4388 SelectionDAG &DAG) const {
4389 // Handle extractions of floating-point values.
4391 SDValue Op0 = Op.getOperand(0);
4392 SDValue Op1 = Op.getOperand(1);
4393 EVT VT = Op.getValueType();
4394 EVT VecVT = Op0.getValueType();
4396 // Extractions of constant indices can be done directly.
4397 if (auto *CIndexN = dyn_cast<ConstantSDNode>(Op1)) {
4398 uint64_t Index = CIndexN->getZExtValue();
4399 unsigned Mask = VecVT.getVectorNumElements() - 1;
4404 // Otherwise bitcast to the equivalent integer form and extract via a GPR.
4405 MVT IntVT = MVT::getIntegerVT(VT.getSizeInBits());
4406 MVT IntVecVT = MVT::getVectorVT(IntVT, VecVT.getVectorNumElements());
4407 SDValue Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, IntVT,
4408 DAG.getNode(ISD::BITCAST, DL, IntVecVT, Op0), Op1);
4409 return DAG.getNode(ISD::BITCAST, DL, VT, Res);
4413 SystemZTargetLowering::lowerExtendVectorInreg(SDValue Op, SelectionDAG &DAG,
4414 unsigned UnpackHigh) const {
4415 SDValue PackedOp = Op.getOperand(0);
4416 EVT OutVT = Op.getValueType();
4417 EVT InVT = PackedOp.getValueType();
4418 unsigned ToBits = OutVT.getScalarSizeInBits();
4419 unsigned FromBits = InVT.getScalarSizeInBits();
4422 EVT OutVT = MVT::getVectorVT(MVT::getIntegerVT(FromBits),
4423 SystemZ::VectorBits / FromBits);
4424 PackedOp = DAG.getNode(UnpackHigh, SDLoc(PackedOp), OutVT, PackedOp);
4425 } while (FromBits != ToBits);
4429 SDValue SystemZTargetLowering::lowerShift(SDValue Op, SelectionDAG &DAG,
4430 unsigned ByScalar) const {
4431 // Look for cases where a vector shift can use the *_BY_SCALAR form.
4432 SDValue Op0 = Op.getOperand(0);
4433 SDValue Op1 = Op.getOperand(1);
4435 EVT VT = Op.getValueType();
4436 unsigned ElemBitSize = VT.getScalarSizeInBits();
4438 // See whether the shift vector is a splat represented as BUILD_VECTOR.
4439 if (auto *BVN = dyn_cast<BuildVectorSDNode>(Op1)) {
4440 APInt SplatBits, SplatUndef;
4441 unsigned SplatBitSize;
4443 // Check for constant splats. Use ElemBitSize as the minimum element
4444 // width and reject splats that need wider elements.
4445 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs,
4446 ElemBitSize, true) &&
4447 SplatBitSize == ElemBitSize) {
4448 SDValue Shift = DAG.getConstant(SplatBits.getZExtValue() & 0xfff,
4450 return DAG.getNode(ByScalar, DL, VT, Op0, Shift);
4452 // Check for variable splats.
4453 BitVector UndefElements;
4454 SDValue Splat = BVN->getSplatValue(&UndefElements);
4456 // Since i32 is the smallest legal type, we either need a no-op
4458 SDValue Shift = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Splat);
4459 return DAG.getNode(ByScalar, DL, VT, Op0, Shift);
4463 // See whether the shift vector is a splat represented as SHUFFLE_VECTOR,
4464 // and the shift amount is directly available in a GPR.
4465 if (auto *VSN = dyn_cast<ShuffleVectorSDNode>(Op1)) {
4466 if (VSN->isSplat()) {
4467 SDValue VSNOp0 = VSN->getOperand(0);
4468 unsigned Index = VSN->getSplatIndex();
4469 assert(Index < VT.getVectorNumElements() &&
4470 "Splat index should be defined and in first operand");
4471 if ((Index == 0 && VSNOp0.getOpcode() == ISD::SCALAR_TO_VECTOR) ||
4472 VSNOp0.getOpcode() == ISD::BUILD_VECTOR) {
4473 // Since i32 is the smallest legal type, we either need a no-op
4475 SDValue Shift = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32,
4476 VSNOp0.getOperand(Index));
4477 return DAG.getNode(ByScalar, DL, VT, Op0, Shift);
4482 // Otherwise just treat the current form as legal.
4486 SDValue SystemZTargetLowering::LowerOperation(SDValue Op,
4487 SelectionDAG &DAG) const {
4488 switch (Op.getOpcode()) {
4489 case ISD::FRAMEADDR:
4490 return lowerFRAMEADDR(Op, DAG);
4491 case ISD::RETURNADDR:
4492 return lowerRETURNADDR(Op, DAG);
4494 return lowerBR_CC(Op, DAG);
4495 case ISD::SELECT_CC:
4496 return lowerSELECT_CC(Op, DAG);
4498 return lowerSETCC(Op, DAG);
4499 case ISD::GlobalAddress:
4500 return lowerGlobalAddress(cast<GlobalAddressSDNode>(Op), DAG);
4501 case ISD::GlobalTLSAddress:
4502 return lowerGlobalTLSAddress(cast<GlobalAddressSDNode>(Op), DAG);
4503 case ISD::BlockAddress:
4504 return lowerBlockAddress(cast<BlockAddressSDNode>(Op), DAG);
4505 case ISD::JumpTable:
4506 return lowerJumpTable(cast<JumpTableSDNode>(Op), DAG);
4507 case ISD::ConstantPool:
4508 return lowerConstantPool(cast<ConstantPoolSDNode>(Op), DAG);
4510 return lowerBITCAST(Op, DAG);
4512 return lowerVASTART(Op, DAG);
4514 return lowerVACOPY(Op, DAG);
4515 case ISD::DYNAMIC_STACKALLOC:
4516 return lowerDYNAMIC_STACKALLOC(Op, DAG);
4517 case ISD::GET_DYNAMIC_AREA_OFFSET:
4518 return lowerGET_DYNAMIC_AREA_OFFSET(Op, DAG);
4519 case ISD::SMUL_LOHI:
4520 return lowerSMUL_LOHI(Op, DAG);
4521 case ISD::UMUL_LOHI:
4522 return lowerUMUL_LOHI(Op, DAG);
4524 return lowerSDIVREM(Op, DAG);
4526 return lowerUDIVREM(Op, DAG);
4528 return lowerOR(Op, DAG);
4530 return lowerCTPOP(Op, DAG);
4531 case ISD::ATOMIC_FENCE:
4532 return lowerATOMIC_FENCE(Op, DAG);
4533 case ISD::ATOMIC_SWAP:
4534 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_SWAPW);
4535 case ISD::ATOMIC_STORE:
4536 return lowerATOMIC_STORE(Op, DAG);
4537 case ISD::ATOMIC_LOAD:
4538 return lowerATOMIC_LOAD(Op, DAG);
4539 case ISD::ATOMIC_LOAD_ADD:
4540 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_ADD);
4541 case ISD::ATOMIC_LOAD_SUB:
4542 return lowerATOMIC_LOAD_SUB(Op, DAG);
4543 case ISD::ATOMIC_LOAD_AND:
4544 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_AND);
4545 case ISD::ATOMIC_LOAD_OR:
4546 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_OR);
4547 case ISD::ATOMIC_LOAD_XOR:
4548 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_XOR);
4549 case ISD::ATOMIC_LOAD_NAND:
4550 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_NAND);
4551 case ISD::ATOMIC_LOAD_MIN:
4552 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_MIN);
4553 case ISD::ATOMIC_LOAD_MAX:
4554 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_MAX);
4555 case ISD::ATOMIC_LOAD_UMIN:
4556 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_UMIN);
4557 case ISD::ATOMIC_LOAD_UMAX:
4558 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_UMAX);
4559 case ISD::ATOMIC_CMP_SWAP:
4560 return lowerATOMIC_CMP_SWAP(Op, DAG);
4561 case ISD::STACKSAVE:
4562 return lowerSTACKSAVE(Op, DAG);
4563 case ISD::STACKRESTORE:
4564 return lowerSTACKRESTORE(Op, DAG);
4566 return lowerPREFETCH(Op, DAG);
4567 case ISD::INTRINSIC_W_CHAIN:
4568 return lowerINTRINSIC_W_CHAIN(Op, DAG);
4569 case ISD::INTRINSIC_WO_CHAIN:
4570 return lowerINTRINSIC_WO_CHAIN(Op, DAG);
4571 case ISD::BUILD_VECTOR:
4572 return lowerBUILD_VECTOR(Op, DAG);
4573 case ISD::VECTOR_SHUFFLE:
4574 return lowerVECTOR_SHUFFLE(Op, DAG);
4575 case ISD::SCALAR_TO_VECTOR:
4576 return lowerSCALAR_TO_VECTOR(Op, DAG);
4577 case ISD::INSERT_VECTOR_ELT:
4578 return lowerINSERT_VECTOR_ELT(Op, DAG);
4579 case ISD::EXTRACT_VECTOR_ELT:
4580 return lowerEXTRACT_VECTOR_ELT(Op, DAG);
4581 case ISD::SIGN_EXTEND_VECTOR_INREG:
4582 return lowerExtendVectorInreg(Op, DAG, SystemZISD::UNPACK_HIGH);
4583 case ISD::ZERO_EXTEND_VECTOR_INREG:
4584 return lowerExtendVectorInreg(Op, DAG, SystemZISD::UNPACKL_HIGH);
4586 return lowerShift(Op, DAG, SystemZISD::VSHL_BY_SCALAR);
4588 return lowerShift(Op, DAG, SystemZISD::VSRL_BY_SCALAR);
4590 return lowerShift(Op, DAG, SystemZISD::VSRA_BY_SCALAR);
4592 llvm_unreachable("Unexpected node to lower");
4596 const char *SystemZTargetLowering::getTargetNodeName(unsigned Opcode) const {
4597 #define OPCODE(NAME) case SystemZISD::NAME: return "SystemZISD::" #NAME
4598 switch ((SystemZISD::NodeType)Opcode) {
4599 case SystemZISD::FIRST_NUMBER: break;
4605 OPCODE(PCREL_WRAPPER);
4606 OPCODE(PCREL_OFFSET);
4612 OPCODE(SELECT_CCMASK);
4613 OPCODE(ADJDYNALLOC);
4615 OPCODE(UMUL_LOHI64);
4632 OPCODE(SEARCH_STRING);
4637 OPCODE(TBEGIN_NOFLOAT);
4640 OPCODE(ROTATE_MASK);
4642 OPCODE(JOIN_DWORDS);
4647 OPCODE(PERMUTE_DWORDS);
4652 OPCODE(UNPACK_HIGH);
4653 OPCODE(UNPACKL_HIGH);
4655 OPCODE(UNPACKL_LOW);
4656 OPCODE(VSHL_BY_SCALAR);
4657 OPCODE(VSRL_BY_SCALAR);
4658 OPCODE(VSRA_BY_SCALAR);
4686 OPCODE(ATOMIC_SWAPW);
4687 OPCODE(ATOMIC_LOADW_ADD);
4688 OPCODE(ATOMIC_LOADW_SUB);
4689 OPCODE(ATOMIC_LOADW_AND);
4690 OPCODE(ATOMIC_LOADW_OR);
4691 OPCODE(ATOMIC_LOADW_XOR);
4692 OPCODE(ATOMIC_LOADW_NAND);
4693 OPCODE(ATOMIC_LOADW_MIN);
4694 OPCODE(ATOMIC_LOADW_MAX);
4695 OPCODE(ATOMIC_LOADW_UMIN);
4696 OPCODE(ATOMIC_LOADW_UMAX);
4697 OPCODE(ATOMIC_CMP_SWAPW);
4706 // Return true if VT is a vector whose elements are a whole number of bytes
4708 static bool canTreatAsByteVector(EVT VT) {
4709 return VT.isVector() && VT.getScalarSizeInBits() % 8 == 0;
4712 // Try to simplify an EXTRACT_VECTOR_ELT from a vector of type VecVT
4713 // producing a result of type ResVT. Op is a possibly bitcast version
4714 // of the input vector and Index is the index (based on type VecVT) that
4715 // should be extracted. Return the new extraction if a simplification
4716 // was possible or if Force is true.
4717 SDValue SystemZTargetLowering::combineExtract(const SDLoc &DL, EVT ResVT,
4718 EVT VecVT, SDValue Op,
4720 DAGCombinerInfo &DCI,
4722 SelectionDAG &DAG = DCI.DAG;
4724 // The number of bytes being extracted.
4725 unsigned BytesPerElement = VecVT.getVectorElementType().getStoreSize();
4728 unsigned Opcode = Op.getOpcode();
4729 if (Opcode == ISD::BITCAST)
4730 // Look through bitcasts.
4731 Op = Op.getOperand(0);
4732 else if (Opcode == ISD::VECTOR_SHUFFLE &&
4733 canTreatAsByteVector(Op.getValueType())) {
4734 // Get a VPERM-like permute mask and see whether the bytes covered
4735 // by the extracted element are a contiguous sequence from one
4737 SmallVector<int, SystemZ::VectorBytes> Bytes;
4738 getVPermMask(cast<ShuffleVectorSDNode>(Op), Bytes);
4740 if (!getShuffleInput(Bytes, Index * BytesPerElement,
4741 BytesPerElement, First))
4744 return DAG.getUNDEF(ResVT);
4745 // Make sure the contiguous sequence starts at a multiple of the
4746 // original element size.
4747 unsigned Byte = unsigned(First) % Bytes.size();
4748 if (Byte % BytesPerElement != 0)
4750 // We can get the extracted value directly from an input.
4751 Index = Byte / BytesPerElement;
4752 Op = Op.getOperand(unsigned(First) / Bytes.size());
4754 } else if (Opcode == ISD::BUILD_VECTOR &&
4755 canTreatAsByteVector(Op.getValueType())) {
4756 // We can only optimize this case if the BUILD_VECTOR elements are
4757 // at least as wide as the extracted value.
4758 EVT OpVT = Op.getValueType();
4759 unsigned OpBytesPerElement = OpVT.getVectorElementType().getStoreSize();
4760 if (OpBytesPerElement < BytesPerElement)
4762 // Make sure that the least-significant bit of the extracted value
4763 // is the least significant bit of an input.
4764 unsigned End = (Index + 1) * BytesPerElement;
4765 if (End % OpBytesPerElement != 0)
4767 // We're extracting the low part of one operand of the BUILD_VECTOR.
4768 Op = Op.getOperand(End / OpBytesPerElement - 1);
4769 if (!Op.getValueType().isInteger()) {
4770 EVT VT = MVT::getIntegerVT(Op.getValueSizeInBits());
4771 Op = DAG.getNode(ISD::BITCAST, DL, VT, Op);
4772 DCI.AddToWorklist(Op.getNode());
4774 EVT VT = MVT::getIntegerVT(ResVT.getSizeInBits());
4775 Op = DAG.getNode(ISD::TRUNCATE, DL, VT, Op);
4777 DCI.AddToWorklist(Op.getNode());
4778 Op = DAG.getNode(ISD::BITCAST, DL, ResVT, Op);
4781 } else if ((Opcode == ISD::SIGN_EXTEND_VECTOR_INREG ||
4782 Opcode == ISD::ZERO_EXTEND_VECTOR_INREG ||
4783 Opcode == ISD::ANY_EXTEND_VECTOR_INREG) &&
4784 canTreatAsByteVector(Op.getValueType()) &&
4785 canTreatAsByteVector(Op.getOperand(0).getValueType())) {
4786 // Make sure that only the unextended bits are significant.
4787 EVT ExtVT = Op.getValueType();
4788 EVT OpVT = Op.getOperand(0).getValueType();
4789 unsigned ExtBytesPerElement = ExtVT.getVectorElementType().getStoreSize();
4790 unsigned OpBytesPerElement = OpVT.getVectorElementType().getStoreSize();
4791 unsigned Byte = Index * BytesPerElement;
4792 unsigned SubByte = Byte % ExtBytesPerElement;
4793 unsigned MinSubByte = ExtBytesPerElement - OpBytesPerElement;
4794 if (SubByte < MinSubByte ||
4795 SubByte + BytesPerElement > ExtBytesPerElement)
4797 // Get the byte offset of the unextended element
4798 Byte = Byte / ExtBytesPerElement * OpBytesPerElement;
4799 // ...then add the byte offset relative to that element.
4800 Byte += SubByte - MinSubByte;
4801 if (Byte % BytesPerElement != 0)
4803 Op = Op.getOperand(0);
4804 Index = Byte / BytesPerElement;
4810 if (Op.getValueType() != VecVT) {
4811 Op = DAG.getNode(ISD::BITCAST, DL, VecVT, Op);
4812 DCI.AddToWorklist(Op.getNode());
4814 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ResVT, Op,
4815 DAG.getConstant(Index, DL, MVT::i32));
4820 // Optimize vector operations in scalar value Op on the basis that Op
4821 // is truncated to TruncVT.
4822 SDValue SystemZTargetLowering::combineTruncateExtract(
4823 const SDLoc &DL, EVT TruncVT, SDValue Op, DAGCombinerInfo &DCI) const {
4824 // If we have (trunc (extract_vector_elt X, Y)), try to turn it into
4825 // (extract_vector_elt (bitcast X), Y'), where (bitcast X) has elements
4827 if (Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
4828 TruncVT.getSizeInBits() % 8 == 0) {
4829 SDValue Vec = Op.getOperand(0);
4830 EVT VecVT = Vec.getValueType();
4831 if (canTreatAsByteVector(VecVT)) {
4832 if (auto *IndexN = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
4833 unsigned BytesPerElement = VecVT.getVectorElementType().getStoreSize();
4834 unsigned TruncBytes = TruncVT.getStoreSize();
4835 if (BytesPerElement % TruncBytes == 0) {
4836 // Calculate the value of Y' in the above description. We are
4837 // splitting the original elements into Scale equal-sized pieces
4838 // and for truncation purposes want the last (least-significant)
4839 // of these pieces for IndexN. This is easiest to do by calculating
4840 // the start index of the following element and then subtracting 1.
4841 unsigned Scale = BytesPerElement / TruncBytes;
4842 unsigned NewIndex = (IndexN->getZExtValue() + 1) * Scale - 1;
4844 // Defer the creation of the bitcast from X to combineExtract,
4845 // which might be able to optimize the extraction.
4846 VecVT = MVT::getVectorVT(MVT::getIntegerVT(TruncBytes * 8),
4847 VecVT.getStoreSize() / TruncBytes);
4848 EVT ResVT = (TruncBytes < 4 ? MVT::i32 : TruncVT);
4849 return combineExtract(DL, ResVT, VecVT, Vec, NewIndex, DCI, true);
4857 SDValue SystemZTargetLowering::combineSIGN_EXTEND(
4858 SDNode *N, DAGCombinerInfo &DCI) const {
4859 // Convert (sext (ashr (shl X, C1), C2)) to
4860 // (ashr (shl (anyext X), C1'), C2')), since wider shifts are as
4861 // cheap as narrower ones.
4862 SelectionDAG &DAG = DCI.DAG;
4863 SDValue N0 = N->getOperand(0);
4864 EVT VT = N->getValueType(0);
4865 if (N0.hasOneUse() && N0.getOpcode() == ISD::SRA) {
4866 auto *SraAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1));
4867 SDValue Inner = N0.getOperand(0);
4868 if (SraAmt && Inner.hasOneUse() && Inner.getOpcode() == ISD::SHL) {
4869 if (auto *ShlAmt = dyn_cast<ConstantSDNode>(Inner.getOperand(1))) {
4870 unsigned Extra = (VT.getSizeInBits() - N0.getValueSizeInBits());
4871 unsigned NewShlAmt = ShlAmt->getZExtValue() + Extra;
4872 unsigned NewSraAmt = SraAmt->getZExtValue() + Extra;
4873 EVT ShiftVT = N0.getOperand(1).getValueType();
4874 SDValue Ext = DAG.getNode(ISD::ANY_EXTEND, SDLoc(Inner), VT,
4875 Inner.getOperand(0));
4876 SDValue Shl = DAG.getNode(ISD::SHL, SDLoc(Inner), VT, Ext,
4877 DAG.getConstant(NewShlAmt, SDLoc(Inner),
4879 return DAG.getNode(ISD::SRA, SDLoc(N0), VT, Shl,
4880 DAG.getConstant(NewSraAmt, SDLoc(N0), ShiftVT));
4887 SDValue SystemZTargetLowering::combineMERGE(
4888 SDNode *N, DAGCombinerInfo &DCI) const {
4889 SelectionDAG &DAG = DCI.DAG;
4890 unsigned Opcode = N->getOpcode();
4891 SDValue Op0 = N->getOperand(0);
4892 SDValue Op1 = N->getOperand(1);
4893 if (Op0.getOpcode() == ISD::BITCAST)
4894 Op0 = Op0.getOperand(0);
4895 if (Op0.getOpcode() == SystemZISD::BYTE_MASK &&
4896 cast<ConstantSDNode>(Op0.getOperand(0))->getZExtValue() == 0) {
4897 // (z_merge_* 0, 0) -> 0. This is mostly useful for using VLLEZF
4899 if (Op1 == N->getOperand(0))
4901 // (z_merge_? 0, X) -> (z_unpackl_? 0, X).
4902 EVT VT = Op1.getValueType();
4903 unsigned ElemBytes = VT.getVectorElementType().getStoreSize();
4904 if (ElemBytes <= 4) {
4905 Opcode = (Opcode == SystemZISD::MERGE_HIGH ?
4906 SystemZISD::UNPACKL_HIGH : SystemZISD::UNPACKL_LOW);
4907 EVT InVT = VT.changeVectorElementTypeToInteger();
4908 EVT OutVT = MVT::getVectorVT(MVT::getIntegerVT(ElemBytes * 16),
4909 SystemZ::VectorBytes / ElemBytes / 2);
4911 Op1 = DAG.getNode(ISD::BITCAST, SDLoc(N), InVT, Op1);
4912 DCI.AddToWorklist(Op1.getNode());
4914 SDValue Op = DAG.getNode(Opcode, SDLoc(N), OutVT, Op1);
4915 DCI.AddToWorklist(Op.getNode());
4916 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
4922 SDValue SystemZTargetLowering::combineSTORE(
4923 SDNode *N, DAGCombinerInfo &DCI) const {
4924 SelectionDAG &DAG = DCI.DAG;
4925 auto *SN = cast<StoreSDNode>(N);
4926 auto &Op1 = N->getOperand(1);
4927 EVT MemVT = SN->getMemoryVT();
4928 // If we have (truncstoreiN (extract_vector_elt X, Y), Z) then it is better
4929 // for the extraction to be done on a vMiN value, so that we can use VSTE.
4930 // If X has wider elements then convert it to:
4931 // (truncstoreiN (extract_vector_elt (bitcast X), Y2), Z).
4932 if (MemVT.isInteger()) {
4934 combineTruncateExtract(SDLoc(N), MemVT, SN->getValue(), DCI)) {
4935 DCI.AddToWorklist(Value.getNode());
4937 // Rewrite the store with the new form of stored value.
4938 return DAG.getTruncStore(SN->getChain(), SDLoc(SN), Value,
4939 SN->getBasePtr(), SN->getMemoryVT(),
4940 SN->getMemOperand());
4943 // Combine STORE (BSWAP) into STRVH/STRV/STRVG
4944 // See comment in combineBSWAP about volatile accesses.
4945 if (!SN->isVolatile() &&
4946 Op1.getOpcode() == ISD::BSWAP &&
4947 Op1.getNode()->hasOneUse() &&
4948 (Op1.getValueType() == MVT::i16 ||
4949 Op1.getValueType() == MVT::i32 ||
4950 Op1.getValueType() == MVT::i64)) {
4952 SDValue BSwapOp = Op1.getOperand(0);
4954 if (BSwapOp.getValueType() == MVT::i16)
4955 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), MVT::i32, BSwapOp);
4958 N->getOperand(0), BSwapOp, N->getOperand(2),
4959 DAG.getValueType(Op1.getValueType())
4963 DAG.getMemIntrinsicNode(SystemZISD::STRV, SDLoc(N), DAG.getVTList(MVT::Other),
4964 Ops, MemVT, SN->getMemOperand());
4969 SDValue SystemZTargetLowering::combineEXTRACT_VECTOR_ELT(
4970 SDNode *N, DAGCombinerInfo &DCI) const {
4971 // Try to simplify a vector extraction.
4972 if (auto *IndexN = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
4973 SDValue Op0 = N->getOperand(0);
4974 EVT VecVT = Op0.getValueType();
4975 return combineExtract(SDLoc(N), N->getValueType(0), VecVT, Op0,
4976 IndexN->getZExtValue(), DCI, false);
4981 SDValue SystemZTargetLowering::combineJOIN_DWORDS(
4982 SDNode *N, DAGCombinerInfo &DCI) const {
4983 SelectionDAG &DAG = DCI.DAG;
4984 // (join_dwords X, X) == (replicate X)
4985 if (N->getOperand(0) == N->getOperand(1))
4986 return DAG.getNode(SystemZISD::REPLICATE, SDLoc(N), N->getValueType(0),
4991 SDValue SystemZTargetLowering::combineFP_ROUND(
4992 SDNode *N, DAGCombinerInfo &DCI) const {
4993 // (fpround (extract_vector_elt X 0))
4994 // (fpround (extract_vector_elt X 1)) ->
4995 // (extract_vector_elt (VROUND X) 0)
4996 // (extract_vector_elt (VROUND X) 1)
4998 // This is a special case since the target doesn't really support v2f32s.
4999 SelectionDAG &DAG = DCI.DAG;
5000 SDValue Op0 = N->getOperand(0);
5001 if (N->getValueType(0) == MVT::f32 &&
5003 Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5004 Op0.getOperand(0).getValueType() == MVT::v2f64 &&
5005 Op0.getOperand(1).getOpcode() == ISD::Constant &&
5006 cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue() == 0) {
5007 SDValue Vec = Op0.getOperand(0);
5008 for (auto *U : Vec->uses()) {
5009 if (U != Op0.getNode() &&
5011 U->getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5012 U->getOperand(0) == Vec &&
5013 U->getOperand(1).getOpcode() == ISD::Constant &&
5014 cast<ConstantSDNode>(U->getOperand(1))->getZExtValue() == 1) {
5015 SDValue OtherRound = SDValue(*U->use_begin(), 0);
5016 if (OtherRound.getOpcode() == ISD::FP_ROUND &&
5017 OtherRound.getOperand(0) == SDValue(U, 0) &&
5018 OtherRound.getValueType() == MVT::f32) {
5019 SDValue VRound = DAG.getNode(SystemZISD::VROUND, SDLoc(N),
5021 DCI.AddToWorklist(VRound.getNode());
5023 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(U), MVT::f32,
5024 VRound, DAG.getConstant(2, SDLoc(U), MVT::i32));
5025 DCI.AddToWorklist(Extract1.getNode());
5026 DAG.ReplaceAllUsesOfValueWith(OtherRound, Extract1);
5028 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op0), MVT::f32,
5029 VRound, DAG.getConstant(0, SDLoc(Op0), MVT::i32));
5038 SDValue SystemZTargetLowering::combineBSWAP(
5039 SDNode *N, DAGCombinerInfo &DCI) const {
5040 SelectionDAG &DAG = DCI.DAG;
5041 // Combine BSWAP (LOAD) into LRVH/LRV/LRVG
5042 // These loads are allowed to access memory multiple times, and so we must check
5043 // that the loads are not volatile before performing the combine.
5044 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
5045 N->getOperand(0).hasOneUse() &&
5046 (N->getValueType(0) == MVT::i16 || N->getValueType(0) == MVT::i32 ||
5047 N->getValueType(0) == MVT::i64) &&
5048 !cast<LoadSDNode>(N->getOperand(0))->isVolatile()) {
5049 SDValue Load = N->getOperand(0);
5050 LoadSDNode *LD = cast<LoadSDNode>(Load);
5052 // Create the byte-swapping load.
5054 LD->getChain(), // Chain
5055 LD->getBasePtr(), // Ptr
5056 DAG.getValueType(N->getValueType(0)) // VT
5059 DAG.getMemIntrinsicNode(SystemZISD::LRV, SDLoc(N),
5060 DAG.getVTList(N->getValueType(0) == MVT::i64 ?
5061 MVT::i64 : MVT::i32, MVT::Other),
5062 Ops, LD->getMemoryVT(), LD->getMemOperand());
5064 // If this is an i16 load, insert the truncate.
5065 SDValue ResVal = BSLoad;
5066 if (N->getValueType(0) == MVT::i16)
5067 ResVal = DAG.getNode(ISD::TRUNCATE, SDLoc(N), MVT::i16, BSLoad);
5069 // First, combine the bswap away. This makes the value produced by the
5071 DCI.CombineTo(N, ResVal);
5073 // Next, combine the load away, we give it a bogus result value but a real
5074 // chain result. The result value is dead because the bswap is dead.
5075 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
5077 // Return N so it doesn't get rechecked!
5078 return SDValue(N, 0);
5083 SDValue SystemZTargetLowering::combineSHIFTROT(
5084 SDNode *N, DAGCombinerInfo &DCI) const {
5086 SelectionDAG &DAG = DCI.DAG;
5088 // Shift/rotate instructions only use the last 6 bits of the second operand
5089 // register. If the second operand is the result of an AND with an immediate
5090 // value that has its last 6 bits set, we can safely remove the AND operation.
5092 // If the AND operation doesn't have the last 6 bits set, we can't remove it
5093 // entirely, but we can still truncate it to a 16-bit value. This prevents
5094 // us from ending up with a NILL with a signed operand, which will cause the
5095 // instruction printer to abort.
5096 SDValue N1 = N->getOperand(1);
5097 if (N1.getOpcode() == ISD::AND) {
5098 SDValue AndMaskOp = N1->getOperand(1);
5099 auto *AndMask = dyn_cast<ConstantSDNode>(AndMaskOp);
5101 // The AND mask is constant
5103 auto AmtVal = AndMask->getZExtValue();
5105 // Bottom 6 bits are set
5106 if ((AmtVal & 0x3f) == 0x3f) {
5107 SDValue AndOp = N1->getOperand(0);
5109 // This is the only use, so remove the node
5110 if (N1.hasOneUse()) {
5111 // Combine the AND away
5112 DCI.CombineTo(N1.getNode(), AndOp);
5114 // Return N so it isn't rechecked
5115 return SDValue(N, 0);
5117 // The node will be reused, so create a new node for this one use
5119 SDValue Replace = DAG.getNode(N->getOpcode(), SDLoc(N),
5120 N->getValueType(0), N->getOperand(0),
5122 DCI.AddToWorklist(Replace.getNode());
5127 // We can't remove the AND, but we can use NILL here (normally we would
5128 // use NILF). Only keep the last 16 bits of the mask. The actual
5129 // transformation will be handled by .td definitions.
5130 } else if (AmtVal >> 16 != 0) {
5131 SDValue AndOp = N1->getOperand(0);
5133 auto NewMask = DAG.getConstant(AndMask->getZExtValue() & 0x0000ffff,
5135 AndMaskOp.getValueType());
5137 auto NewAnd = DAG.getNode(N1.getOpcode(), SDLoc(N1), N1.getValueType(),
5140 SDValue Replace = DAG.getNode(N->getOpcode(), SDLoc(N),
5141 N->getValueType(0), N->getOperand(0),
5143 DCI.AddToWorklist(Replace.getNode());
5153 SDValue SystemZTargetLowering::PerformDAGCombine(SDNode *N,
5154 DAGCombinerInfo &DCI) const {
5155 switch(N->getOpcode()) {
5157 case ISD::SIGN_EXTEND: return combineSIGN_EXTEND(N, DCI);
5158 case SystemZISD::MERGE_HIGH:
5159 case SystemZISD::MERGE_LOW: return combineMERGE(N, DCI);
5160 case ISD::STORE: return combineSTORE(N, DCI);
5161 case ISD::EXTRACT_VECTOR_ELT: return combineEXTRACT_VECTOR_ELT(N, DCI);
5162 case SystemZISD::JOIN_DWORDS: return combineJOIN_DWORDS(N, DCI);
5163 case ISD::FP_ROUND: return combineFP_ROUND(N, DCI);
5164 case ISD::BSWAP: return combineBSWAP(N, DCI);
5168 case ISD::ROTL: return combineSHIFTROT(N, DCI);
5174 //===----------------------------------------------------------------------===//
5176 //===----------------------------------------------------------------------===//
5178 // Create a new basic block after MBB.
5179 static MachineBasicBlock *emitBlockAfter(MachineBasicBlock *MBB) {
5180 MachineFunction &MF = *MBB->getParent();
5181 MachineBasicBlock *NewMBB = MF.CreateMachineBasicBlock(MBB->getBasicBlock());
5182 MF.insert(std::next(MachineFunction::iterator(MBB)), NewMBB);
5186 // Split MBB after MI and return the new block (the one that contains
5187 // instructions after MI).
5188 static MachineBasicBlock *splitBlockAfter(MachineBasicBlock::iterator MI,
5189 MachineBasicBlock *MBB) {
5190 MachineBasicBlock *NewMBB = emitBlockAfter(MBB);
5191 NewMBB->splice(NewMBB->begin(), MBB,
5192 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
5193 NewMBB->transferSuccessorsAndUpdatePHIs(MBB);
5197 // Split MBB before MI and return the new block (the one that contains MI).
5198 static MachineBasicBlock *splitBlockBefore(MachineBasicBlock::iterator MI,
5199 MachineBasicBlock *MBB) {
5200 MachineBasicBlock *NewMBB = emitBlockAfter(MBB);
5201 NewMBB->splice(NewMBB->begin(), MBB, MI, MBB->end());
5202 NewMBB->transferSuccessorsAndUpdatePHIs(MBB);
5206 // Force base value Base into a register before MI. Return the register.
5207 static unsigned forceReg(MachineInstr &MI, MachineOperand &Base,
5208 const SystemZInstrInfo *TII) {
5210 return Base.getReg();
5212 MachineBasicBlock *MBB = MI.getParent();
5213 MachineFunction &MF = *MBB->getParent();
5214 MachineRegisterInfo &MRI = MF.getRegInfo();
5216 unsigned Reg = MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass);
5217 BuildMI(*MBB, MI, MI.getDebugLoc(), TII->get(SystemZ::LA), Reg)
5224 // Implement EmitInstrWithCustomInserter for pseudo Select* instruction MI.
5226 SystemZTargetLowering::emitSelect(MachineInstr &MI,
5227 MachineBasicBlock *MBB,
5228 unsigned LOCROpcode) const {
5229 const SystemZInstrInfo *TII =
5230 static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
5232 unsigned DestReg = MI.getOperand(0).getReg();
5233 unsigned TrueReg = MI.getOperand(1).getReg();
5234 unsigned FalseReg = MI.getOperand(2).getReg();
5235 unsigned CCValid = MI.getOperand(3).getImm();
5236 unsigned CCMask = MI.getOperand(4).getImm();
5237 DebugLoc DL = MI.getDebugLoc();
5239 // Use LOCROpcode if possible.
5240 if (LOCROpcode && Subtarget.hasLoadStoreOnCond()) {
5241 BuildMI(*MBB, MI, DL, TII->get(LOCROpcode), DestReg)
5242 .addReg(FalseReg).addReg(TrueReg)
5243 .addImm(CCValid).addImm(CCMask);
5244 MI.eraseFromParent();
5248 MachineBasicBlock *StartMBB = MBB;
5249 MachineBasicBlock *JoinMBB = splitBlockBefore(MI, MBB);
5250 MachineBasicBlock *FalseMBB = emitBlockAfter(StartMBB);
5253 // BRC CCMask, JoinMBB
5254 // # fallthrough to FalseMBB
5256 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
5257 .addImm(CCValid).addImm(CCMask).addMBB(JoinMBB);
5258 MBB->addSuccessor(JoinMBB);
5259 MBB->addSuccessor(FalseMBB);
5262 // # fallthrough to JoinMBB
5264 MBB->addSuccessor(JoinMBB);
5267 // %Result = phi [ %FalseReg, FalseMBB ], [ %TrueReg, StartMBB ]
5270 BuildMI(*MBB, MI, DL, TII->get(SystemZ::PHI), DestReg)
5271 .addReg(TrueReg).addMBB(StartMBB)
5272 .addReg(FalseReg).addMBB(FalseMBB);
5274 MI.eraseFromParent();
5278 // Implement EmitInstrWithCustomInserter for pseudo CondStore* instruction MI.
5279 // StoreOpcode is the store to use and Invert says whether the store should
5280 // happen when the condition is false rather than true. If a STORE ON
5281 // CONDITION is available, STOCOpcode is its opcode, otherwise it is 0.
5282 MachineBasicBlock *SystemZTargetLowering::emitCondStore(MachineInstr &MI,
5283 MachineBasicBlock *MBB,
5284 unsigned StoreOpcode,
5285 unsigned STOCOpcode,
5286 bool Invert) const {
5287 const SystemZInstrInfo *TII =
5288 static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
5290 unsigned SrcReg = MI.getOperand(0).getReg();
5291 MachineOperand Base = MI.getOperand(1);
5292 int64_t Disp = MI.getOperand(2).getImm();
5293 unsigned IndexReg = MI.getOperand(3).getReg();
5294 unsigned CCValid = MI.getOperand(4).getImm();
5295 unsigned CCMask = MI.getOperand(5).getImm();
5296 DebugLoc DL = MI.getDebugLoc();
5298 StoreOpcode = TII->getOpcodeForOffset(StoreOpcode, Disp);
5300 // Use STOCOpcode if possible. We could use different store patterns in
5301 // order to avoid matching the index register, but the performance trade-offs
5302 // might be more complicated in that case.
5303 if (STOCOpcode && !IndexReg && Subtarget.hasLoadStoreOnCond()) {
5306 BuildMI(*MBB, MI, DL, TII->get(STOCOpcode))
5307 .addReg(SrcReg).addOperand(Base).addImm(Disp)
5308 .addImm(CCValid).addImm(CCMask);
5309 MI.eraseFromParent();
5313 // Get the condition needed to branch around the store.
5317 MachineBasicBlock *StartMBB = MBB;
5318 MachineBasicBlock *JoinMBB = splitBlockBefore(MI, MBB);
5319 MachineBasicBlock *FalseMBB = emitBlockAfter(StartMBB);
5322 // BRC CCMask, JoinMBB
5323 // # fallthrough to FalseMBB
5325 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
5326 .addImm(CCValid).addImm(CCMask).addMBB(JoinMBB);
5327 MBB->addSuccessor(JoinMBB);
5328 MBB->addSuccessor(FalseMBB);
5331 // store %SrcReg, %Disp(%Index,%Base)
5332 // # fallthrough to JoinMBB
5334 BuildMI(MBB, DL, TII->get(StoreOpcode))
5335 .addReg(SrcReg).addOperand(Base).addImm(Disp).addReg(IndexReg);
5336 MBB->addSuccessor(JoinMBB);
5338 MI.eraseFromParent();
5342 // Implement EmitInstrWithCustomInserter for pseudo ATOMIC_LOAD{,W}_*
5343 // or ATOMIC_SWAP{,W} instruction MI. BinOpcode is the instruction that
5344 // performs the binary operation elided by "*", or 0 for ATOMIC_SWAP{,W}.
5345 // BitSize is the width of the field in bits, or 0 if this is a partword
5346 // ATOMIC_LOADW_* or ATOMIC_SWAPW instruction, in which case the bitsize
5347 // is one of the operands. Invert says whether the field should be
5348 // inverted after performing BinOpcode (e.g. for NAND).
5349 MachineBasicBlock *SystemZTargetLowering::emitAtomicLoadBinary(
5350 MachineInstr &MI, MachineBasicBlock *MBB, unsigned BinOpcode,
5351 unsigned BitSize, bool Invert) const {
5352 MachineFunction &MF = *MBB->getParent();
5353 const SystemZInstrInfo *TII =
5354 static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
5355 MachineRegisterInfo &MRI = MF.getRegInfo();
5356 bool IsSubWord = (BitSize < 32);
5358 // Extract the operands. Base can be a register or a frame index.
5359 // Src2 can be a register or immediate.
5360 unsigned Dest = MI.getOperand(0).getReg();
5361 MachineOperand Base = earlyUseOperand(MI.getOperand(1));
5362 int64_t Disp = MI.getOperand(2).getImm();
5363 MachineOperand Src2 = earlyUseOperand(MI.getOperand(3));
5364 unsigned BitShift = (IsSubWord ? MI.getOperand(4).getReg() : 0);
5365 unsigned NegBitShift = (IsSubWord ? MI.getOperand(5).getReg() : 0);
5366 DebugLoc DL = MI.getDebugLoc();
5368 BitSize = MI.getOperand(6).getImm();
5370 // Subword operations use 32-bit registers.
5371 const TargetRegisterClass *RC = (BitSize <= 32 ?
5372 &SystemZ::GR32BitRegClass :
5373 &SystemZ::GR64BitRegClass);
5374 unsigned LOpcode = BitSize <= 32 ? SystemZ::L : SystemZ::LG;
5375 unsigned CSOpcode = BitSize <= 32 ? SystemZ::CS : SystemZ::CSG;
5377 // Get the right opcodes for the displacement.
5378 LOpcode = TII->getOpcodeForOffset(LOpcode, Disp);
5379 CSOpcode = TII->getOpcodeForOffset(CSOpcode, Disp);
5380 assert(LOpcode && CSOpcode && "Displacement out of range");
5382 // Create virtual registers for temporary results.
5383 unsigned OrigVal = MRI.createVirtualRegister(RC);
5384 unsigned OldVal = MRI.createVirtualRegister(RC);
5385 unsigned NewVal = (BinOpcode || IsSubWord ?
5386 MRI.createVirtualRegister(RC) : Src2.getReg());
5387 unsigned RotatedOldVal = (IsSubWord ? MRI.createVirtualRegister(RC) : OldVal);
5388 unsigned RotatedNewVal = (IsSubWord ? MRI.createVirtualRegister(RC) : NewVal);
5390 // Insert a basic block for the main loop.
5391 MachineBasicBlock *StartMBB = MBB;
5392 MachineBasicBlock *DoneMBB = splitBlockBefore(MI, MBB);
5393 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
5397 // %OrigVal = L Disp(%Base)
5398 // # fall through to LoopMMB
5400 BuildMI(MBB, DL, TII->get(LOpcode), OrigVal)
5401 .addOperand(Base).addImm(Disp).addReg(0);
5402 MBB->addSuccessor(LoopMBB);
5405 // %OldVal = phi [ %OrigVal, StartMBB ], [ %Dest, LoopMBB ]
5406 // %RotatedOldVal = RLL %OldVal, 0(%BitShift)
5407 // %RotatedNewVal = OP %RotatedOldVal, %Src2
5408 // %NewVal = RLL %RotatedNewVal, 0(%NegBitShift)
5409 // %Dest = CS %OldVal, %NewVal, Disp(%Base)
5411 // # fall through to DoneMMB
5413 BuildMI(MBB, DL, TII->get(SystemZ::PHI), OldVal)
5414 .addReg(OrigVal).addMBB(StartMBB)
5415 .addReg(Dest).addMBB(LoopMBB);
5417 BuildMI(MBB, DL, TII->get(SystemZ::RLL), RotatedOldVal)
5418 .addReg(OldVal).addReg(BitShift).addImm(0);
5420 // Perform the operation normally and then invert every bit of the field.
5421 unsigned Tmp = MRI.createVirtualRegister(RC);
5422 BuildMI(MBB, DL, TII->get(BinOpcode), Tmp)
5423 .addReg(RotatedOldVal).addOperand(Src2);
5425 // XILF with the upper BitSize bits set.
5426 BuildMI(MBB, DL, TII->get(SystemZ::XILF), RotatedNewVal)
5427 .addReg(Tmp).addImm(-1U << (32 - BitSize));
5429 // Use LCGR and add -1 to the result, which is more compact than
5430 // an XILF, XILH pair.
5431 unsigned Tmp2 = MRI.createVirtualRegister(RC);
5432 BuildMI(MBB, DL, TII->get(SystemZ::LCGR), Tmp2).addReg(Tmp);
5433 BuildMI(MBB, DL, TII->get(SystemZ::AGHI), RotatedNewVal)
5434 .addReg(Tmp2).addImm(-1);
5436 } else if (BinOpcode)
5437 // A simply binary operation.
5438 BuildMI(MBB, DL, TII->get(BinOpcode), RotatedNewVal)
5439 .addReg(RotatedOldVal).addOperand(Src2);
5441 // Use RISBG to rotate Src2 into position and use it to replace the
5442 // field in RotatedOldVal.
5443 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RotatedNewVal)
5444 .addReg(RotatedOldVal).addReg(Src2.getReg())
5445 .addImm(32).addImm(31 + BitSize).addImm(32 - BitSize);
5447 BuildMI(MBB, DL, TII->get(SystemZ::RLL), NewVal)
5448 .addReg(RotatedNewVal).addReg(NegBitShift).addImm(0);
5449 BuildMI(MBB, DL, TII->get(CSOpcode), Dest)
5450 .addReg(OldVal).addReg(NewVal).addOperand(Base).addImm(Disp);
5451 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
5452 .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
5453 MBB->addSuccessor(LoopMBB);
5454 MBB->addSuccessor(DoneMBB);
5456 MI.eraseFromParent();
5460 // Implement EmitInstrWithCustomInserter for pseudo
5461 // ATOMIC_LOAD{,W}_{,U}{MIN,MAX} instruction MI. CompareOpcode is the
5462 // instruction that should be used to compare the current field with the
5463 // minimum or maximum value. KeepOldMask is the BRC condition-code mask
5464 // for when the current field should be kept. BitSize is the width of
5465 // the field in bits, or 0 if this is a partword ATOMIC_LOADW_* instruction.
5466 MachineBasicBlock *SystemZTargetLowering::emitAtomicLoadMinMax(
5467 MachineInstr &MI, MachineBasicBlock *MBB, unsigned CompareOpcode,
5468 unsigned KeepOldMask, unsigned BitSize) const {
5469 MachineFunction &MF = *MBB->getParent();
5470 const SystemZInstrInfo *TII =
5471 static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
5472 MachineRegisterInfo &MRI = MF.getRegInfo();
5473 bool IsSubWord = (BitSize < 32);
5475 // Extract the operands. Base can be a register or a frame index.
5476 unsigned Dest = MI.getOperand(0).getReg();
5477 MachineOperand Base = earlyUseOperand(MI.getOperand(1));
5478 int64_t Disp = MI.getOperand(2).getImm();
5479 unsigned Src2 = MI.getOperand(3).getReg();
5480 unsigned BitShift = (IsSubWord ? MI.getOperand(4).getReg() : 0);
5481 unsigned NegBitShift = (IsSubWord ? MI.getOperand(5).getReg() : 0);
5482 DebugLoc DL = MI.getDebugLoc();
5484 BitSize = MI.getOperand(6).getImm();
5486 // Subword operations use 32-bit registers.
5487 const TargetRegisterClass *RC = (BitSize <= 32 ?
5488 &SystemZ::GR32BitRegClass :
5489 &SystemZ::GR64BitRegClass);
5490 unsigned LOpcode = BitSize <= 32 ? SystemZ::L : SystemZ::LG;
5491 unsigned CSOpcode = BitSize <= 32 ? SystemZ::CS : SystemZ::CSG;
5493 // Get the right opcodes for the displacement.
5494 LOpcode = TII->getOpcodeForOffset(LOpcode, Disp);
5495 CSOpcode = TII->getOpcodeForOffset(CSOpcode, Disp);
5496 assert(LOpcode && CSOpcode && "Displacement out of range");
5498 // Create virtual registers for temporary results.
5499 unsigned OrigVal = MRI.createVirtualRegister(RC);
5500 unsigned OldVal = MRI.createVirtualRegister(RC);
5501 unsigned NewVal = MRI.createVirtualRegister(RC);
5502 unsigned RotatedOldVal = (IsSubWord ? MRI.createVirtualRegister(RC) : OldVal);
5503 unsigned RotatedAltVal = (IsSubWord ? MRI.createVirtualRegister(RC) : Src2);
5504 unsigned RotatedNewVal = (IsSubWord ? MRI.createVirtualRegister(RC) : NewVal);
5506 // Insert 3 basic blocks for the loop.
5507 MachineBasicBlock *StartMBB = MBB;
5508 MachineBasicBlock *DoneMBB = splitBlockBefore(MI, MBB);
5509 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
5510 MachineBasicBlock *UseAltMBB = emitBlockAfter(LoopMBB);
5511 MachineBasicBlock *UpdateMBB = emitBlockAfter(UseAltMBB);
5515 // %OrigVal = L Disp(%Base)
5516 // # fall through to LoopMMB
5518 BuildMI(MBB, DL, TII->get(LOpcode), OrigVal)
5519 .addOperand(Base).addImm(Disp).addReg(0);
5520 MBB->addSuccessor(LoopMBB);
5523 // %OldVal = phi [ %OrigVal, StartMBB ], [ %Dest, UpdateMBB ]
5524 // %RotatedOldVal = RLL %OldVal, 0(%BitShift)
5525 // CompareOpcode %RotatedOldVal, %Src2
5526 // BRC KeepOldMask, UpdateMBB
5528 BuildMI(MBB, DL, TII->get(SystemZ::PHI), OldVal)
5529 .addReg(OrigVal).addMBB(StartMBB)
5530 .addReg(Dest).addMBB(UpdateMBB);
5532 BuildMI(MBB, DL, TII->get(SystemZ::RLL), RotatedOldVal)
5533 .addReg(OldVal).addReg(BitShift).addImm(0);
5534 BuildMI(MBB, DL, TII->get(CompareOpcode))
5535 .addReg(RotatedOldVal).addReg(Src2);
5536 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
5537 .addImm(SystemZ::CCMASK_ICMP).addImm(KeepOldMask).addMBB(UpdateMBB);
5538 MBB->addSuccessor(UpdateMBB);
5539 MBB->addSuccessor(UseAltMBB);
5542 // %RotatedAltVal = RISBG %RotatedOldVal, %Src2, 32, 31 + BitSize, 0
5543 // # fall through to UpdateMMB
5546 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RotatedAltVal)
5547 .addReg(RotatedOldVal).addReg(Src2)
5548 .addImm(32).addImm(31 + BitSize).addImm(0);
5549 MBB->addSuccessor(UpdateMBB);
5552 // %RotatedNewVal = PHI [ %RotatedOldVal, LoopMBB ],
5553 // [ %RotatedAltVal, UseAltMBB ]
5554 // %NewVal = RLL %RotatedNewVal, 0(%NegBitShift)
5555 // %Dest = CS %OldVal, %NewVal, Disp(%Base)
5557 // # fall through to DoneMMB
5559 BuildMI(MBB, DL, TII->get(SystemZ::PHI), RotatedNewVal)
5560 .addReg(RotatedOldVal).addMBB(LoopMBB)
5561 .addReg(RotatedAltVal).addMBB(UseAltMBB);
5563 BuildMI(MBB, DL, TII->get(SystemZ::RLL), NewVal)
5564 .addReg(RotatedNewVal).addReg(NegBitShift).addImm(0);
5565 BuildMI(MBB, DL, TII->get(CSOpcode), Dest)
5566 .addReg(OldVal).addReg(NewVal).addOperand(Base).addImm(Disp);
5567 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
5568 .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
5569 MBB->addSuccessor(LoopMBB);
5570 MBB->addSuccessor(DoneMBB);
5572 MI.eraseFromParent();
5576 // Implement EmitInstrWithCustomInserter for pseudo ATOMIC_CMP_SWAPW
5579 SystemZTargetLowering::emitAtomicCmpSwapW(MachineInstr &MI,
5580 MachineBasicBlock *MBB) const {
5582 MachineFunction &MF = *MBB->getParent();
5583 const SystemZInstrInfo *TII =
5584 static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
5585 MachineRegisterInfo &MRI = MF.getRegInfo();
5587 // Extract the operands. Base can be a register or a frame index.
5588 unsigned Dest = MI.getOperand(0).getReg();
5589 MachineOperand Base = earlyUseOperand(MI.getOperand(1));
5590 int64_t Disp = MI.getOperand(2).getImm();
5591 unsigned OrigCmpVal = MI.getOperand(3).getReg();
5592 unsigned OrigSwapVal = MI.getOperand(4).getReg();
5593 unsigned BitShift = MI.getOperand(5).getReg();
5594 unsigned NegBitShift = MI.getOperand(6).getReg();
5595 int64_t BitSize = MI.getOperand(7).getImm();
5596 DebugLoc DL = MI.getDebugLoc();
5598 const TargetRegisterClass *RC = &SystemZ::GR32BitRegClass;
5600 // Get the right opcodes for the displacement.
5601 unsigned LOpcode = TII->getOpcodeForOffset(SystemZ::L, Disp);
5602 unsigned CSOpcode = TII->getOpcodeForOffset(SystemZ::CS, Disp);
5603 assert(LOpcode && CSOpcode && "Displacement out of range");
5605 // Create virtual registers for temporary results.
5606 unsigned OrigOldVal = MRI.createVirtualRegister(RC);
5607 unsigned OldVal = MRI.createVirtualRegister(RC);
5608 unsigned CmpVal = MRI.createVirtualRegister(RC);
5609 unsigned SwapVal = MRI.createVirtualRegister(RC);
5610 unsigned StoreVal = MRI.createVirtualRegister(RC);
5611 unsigned RetryOldVal = MRI.createVirtualRegister(RC);
5612 unsigned RetryCmpVal = MRI.createVirtualRegister(RC);
5613 unsigned RetrySwapVal = MRI.createVirtualRegister(RC);
5615 // Insert 2 basic blocks for the loop.
5616 MachineBasicBlock *StartMBB = MBB;
5617 MachineBasicBlock *DoneMBB = splitBlockBefore(MI, MBB);
5618 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
5619 MachineBasicBlock *SetMBB = emitBlockAfter(LoopMBB);
5623 // %OrigOldVal = L Disp(%Base)
5624 // # fall through to LoopMMB
5626 BuildMI(MBB, DL, TII->get(LOpcode), OrigOldVal)
5627 .addOperand(Base).addImm(Disp).addReg(0);
5628 MBB->addSuccessor(LoopMBB);
5631 // %OldVal = phi [ %OrigOldVal, EntryBB ], [ %RetryOldVal, SetMBB ]
5632 // %CmpVal = phi [ %OrigCmpVal, EntryBB ], [ %RetryCmpVal, SetMBB ]
5633 // %SwapVal = phi [ %OrigSwapVal, EntryBB ], [ %RetrySwapVal, SetMBB ]
5634 // %Dest = RLL %OldVal, BitSize(%BitShift)
5635 // ^^ The low BitSize bits contain the field
5637 // %RetryCmpVal = RISBG32 %CmpVal, %Dest, 32, 63-BitSize, 0
5638 // ^^ Replace the upper 32-BitSize bits of the
5639 // comparison value with those that we loaded,
5640 // so that we can use a full word comparison.
5641 // CR %Dest, %RetryCmpVal
5643 // # Fall through to SetMBB
5645 BuildMI(MBB, DL, TII->get(SystemZ::PHI), OldVal)
5646 .addReg(OrigOldVal).addMBB(StartMBB)
5647 .addReg(RetryOldVal).addMBB(SetMBB);
5648 BuildMI(MBB, DL, TII->get(SystemZ::PHI), CmpVal)
5649 .addReg(OrigCmpVal).addMBB(StartMBB)
5650 .addReg(RetryCmpVal).addMBB(SetMBB);
5651 BuildMI(MBB, DL, TII->get(SystemZ::PHI), SwapVal)
5652 .addReg(OrigSwapVal).addMBB(StartMBB)
5653 .addReg(RetrySwapVal).addMBB(SetMBB);
5654 BuildMI(MBB, DL, TII->get(SystemZ::RLL), Dest)
5655 .addReg(OldVal).addReg(BitShift).addImm(BitSize);
5656 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RetryCmpVal)
5657 .addReg(CmpVal).addReg(Dest).addImm(32).addImm(63 - BitSize).addImm(0);
5658 BuildMI(MBB, DL, TII->get(SystemZ::CR))
5659 .addReg(Dest).addReg(RetryCmpVal);
5660 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
5661 .addImm(SystemZ::CCMASK_ICMP)
5662 .addImm(SystemZ::CCMASK_CMP_NE).addMBB(DoneMBB);
5663 MBB->addSuccessor(DoneMBB);
5664 MBB->addSuccessor(SetMBB);
5667 // %RetrySwapVal = RISBG32 %SwapVal, %Dest, 32, 63-BitSize, 0
5668 // ^^ Replace the upper 32-BitSize bits of the new
5669 // value with those that we loaded.
5670 // %StoreVal = RLL %RetrySwapVal, -BitSize(%NegBitShift)
5671 // ^^ Rotate the new field to its proper position.
5672 // %RetryOldVal = CS %Dest, %StoreVal, Disp(%Base)
5674 // # fall through to ExitMMB
5676 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RetrySwapVal)
5677 .addReg(SwapVal).addReg(Dest).addImm(32).addImm(63 - BitSize).addImm(0);
5678 BuildMI(MBB, DL, TII->get(SystemZ::RLL), StoreVal)
5679 .addReg(RetrySwapVal).addReg(NegBitShift).addImm(-BitSize);
5680 BuildMI(MBB, DL, TII->get(CSOpcode), RetryOldVal)
5681 .addReg(OldVal).addReg(StoreVal).addOperand(Base).addImm(Disp);
5682 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
5683 .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
5684 MBB->addSuccessor(LoopMBB);
5685 MBB->addSuccessor(DoneMBB);
5687 MI.eraseFromParent();
5691 // Emit an extension from a GR32 or GR64 to a GR128. ClearEven is true
5692 // if the high register of the GR128 value must be cleared or false if
5693 // it's "don't care". SubReg is subreg_l32 when extending a GR32
5694 // and subreg_l64 when extending a GR64.
5695 MachineBasicBlock *SystemZTargetLowering::emitExt128(MachineInstr &MI,
5696 MachineBasicBlock *MBB,
5698 unsigned SubReg) const {
5699 MachineFunction &MF = *MBB->getParent();
5700 const SystemZInstrInfo *TII =
5701 static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
5702 MachineRegisterInfo &MRI = MF.getRegInfo();
5703 DebugLoc DL = MI.getDebugLoc();
5705 unsigned Dest = MI.getOperand(0).getReg();
5706 unsigned Src = MI.getOperand(1).getReg();
5707 unsigned In128 = MRI.createVirtualRegister(&SystemZ::GR128BitRegClass);
5709 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::IMPLICIT_DEF), In128);
5711 unsigned NewIn128 = MRI.createVirtualRegister(&SystemZ::GR128BitRegClass);
5712 unsigned Zero64 = MRI.createVirtualRegister(&SystemZ::GR64BitRegClass);
5714 BuildMI(*MBB, MI, DL, TII->get(SystemZ::LLILL), Zero64)
5716 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::INSERT_SUBREG), NewIn128)
5717 .addReg(In128).addReg(Zero64).addImm(SystemZ::subreg_h64);
5720 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::INSERT_SUBREG), Dest)
5721 .addReg(In128).addReg(Src).addImm(SubReg);
5723 MI.eraseFromParent();
5727 MachineBasicBlock *SystemZTargetLowering::emitMemMemWrapper(
5728 MachineInstr &MI, MachineBasicBlock *MBB, unsigned Opcode) const {
5729 MachineFunction &MF = *MBB->getParent();
5730 const SystemZInstrInfo *TII =
5731 static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
5732 MachineRegisterInfo &MRI = MF.getRegInfo();
5733 DebugLoc DL = MI.getDebugLoc();
5735 MachineOperand DestBase = earlyUseOperand(MI.getOperand(0));
5736 uint64_t DestDisp = MI.getOperand(1).getImm();
5737 MachineOperand SrcBase = earlyUseOperand(MI.getOperand(2));
5738 uint64_t SrcDisp = MI.getOperand(3).getImm();
5739 uint64_t Length = MI.getOperand(4).getImm();
5741 // When generating more than one CLC, all but the last will need to
5742 // branch to the end when a difference is found.
5743 MachineBasicBlock *EndMBB = (Length > 256 && Opcode == SystemZ::CLC ?
5744 splitBlockAfter(MI, MBB) : nullptr);
5746 // Check for the loop form, in which operand 5 is the trip count.
5747 if (MI.getNumExplicitOperands() > 5) {
5748 bool HaveSingleBase = DestBase.isIdenticalTo(SrcBase);
5750 uint64_t StartCountReg = MI.getOperand(5).getReg();
5751 uint64_t StartSrcReg = forceReg(MI, SrcBase, TII);
5752 uint64_t StartDestReg = (HaveSingleBase ? StartSrcReg :
5753 forceReg(MI, DestBase, TII));
5755 const TargetRegisterClass *RC = &SystemZ::ADDR64BitRegClass;
5756 uint64_t ThisSrcReg = MRI.createVirtualRegister(RC);
5757 uint64_t ThisDestReg = (HaveSingleBase ? ThisSrcReg :
5758 MRI.createVirtualRegister(RC));
5759 uint64_t NextSrcReg = MRI.createVirtualRegister(RC);
5760 uint64_t NextDestReg = (HaveSingleBase ? NextSrcReg :
5761 MRI.createVirtualRegister(RC));
5763 RC = &SystemZ::GR64BitRegClass;
5764 uint64_t ThisCountReg = MRI.createVirtualRegister(RC);
5765 uint64_t NextCountReg = MRI.createVirtualRegister(RC);
5767 MachineBasicBlock *StartMBB = MBB;
5768 MachineBasicBlock *DoneMBB = splitBlockBefore(MI, MBB);
5769 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
5770 MachineBasicBlock *NextMBB = (EndMBB ? emitBlockAfter(LoopMBB) : LoopMBB);
5773 // # fall through to LoopMMB
5774 MBB->addSuccessor(LoopMBB);
5777 // %ThisDestReg = phi [ %StartDestReg, StartMBB ],
5778 // [ %NextDestReg, NextMBB ]
5779 // %ThisSrcReg = phi [ %StartSrcReg, StartMBB ],
5780 // [ %NextSrcReg, NextMBB ]
5781 // %ThisCountReg = phi [ %StartCountReg, StartMBB ],
5782 // [ %NextCountReg, NextMBB ]
5783 // ( PFD 2, 768+DestDisp(%ThisDestReg) )
5784 // Opcode DestDisp(256,%ThisDestReg), SrcDisp(%ThisSrcReg)
5787 // The prefetch is used only for MVC. The JLH is used only for CLC.
5790 BuildMI(MBB, DL, TII->get(SystemZ::PHI), ThisDestReg)
5791 .addReg(StartDestReg).addMBB(StartMBB)
5792 .addReg(NextDestReg).addMBB(NextMBB);
5793 if (!HaveSingleBase)
5794 BuildMI(MBB, DL, TII->get(SystemZ::PHI), ThisSrcReg)
5795 .addReg(StartSrcReg).addMBB(StartMBB)
5796 .addReg(NextSrcReg).addMBB(NextMBB);
5797 BuildMI(MBB, DL, TII->get(SystemZ::PHI), ThisCountReg)
5798 .addReg(StartCountReg).addMBB(StartMBB)
5799 .addReg(NextCountReg).addMBB(NextMBB);
5800 if (Opcode == SystemZ::MVC)
5801 BuildMI(MBB, DL, TII->get(SystemZ::PFD))
5802 .addImm(SystemZ::PFD_WRITE)
5803 .addReg(ThisDestReg).addImm(DestDisp + 768).addReg(0);
5804 BuildMI(MBB, DL, TII->get(Opcode))
5805 .addReg(ThisDestReg).addImm(DestDisp).addImm(256)
5806 .addReg(ThisSrcReg).addImm(SrcDisp);
5808 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
5809 .addImm(SystemZ::CCMASK_ICMP).addImm(SystemZ::CCMASK_CMP_NE)
5811 MBB->addSuccessor(EndMBB);
5812 MBB->addSuccessor(NextMBB);
5816 // %NextDestReg = LA 256(%ThisDestReg)
5817 // %NextSrcReg = LA 256(%ThisSrcReg)
5818 // %NextCountReg = AGHI %ThisCountReg, -1
5819 // CGHI %NextCountReg, 0
5821 // # fall through to DoneMMB
5823 // The AGHI, CGHI and JLH should be converted to BRCTG by later passes.
5826 BuildMI(MBB, DL, TII->get(SystemZ::LA), NextDestReg)
5827 .addReg(ThisDestReg).addImm(256).addReg(0);
5828 if (!HaveSingleBase)
5829 BuildMI(MBB, DL, TII->get(SystemZ::LA), NextSrcReg)
5830 .addReg(ThisSrcReg).addImm(256).addReg(0);
5831 BuildMI(MBB, DL, TII->get(SystemZ::AGHI), NextCountReg)
5832 .addReg(ThisCountReg).addImm(-1);
5833 BuildMI(MBB, DL, TII->get(SystemZ::CGHI))
5834 .addReg(NextCountReg).addImm(0);
5835 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
5836 .addImm(SystemZ::CCMASK_ICMP).addImm(SystemZ::CCMASK_CMP_NE)
5838 MBB->addSuccessor(LoopMBB);
5839 MBB->addSuccessor(DoneMBB);
5841 DestBase = MachineOperand::CreateReg(NextDestReg, false);
5842 SrcBase = MachineOperand::CreateReg(NextSrcReg, false);
5846 // Handle any remaining bytes with straight-line code.
5847 while (Length > 0) {
5848 uint64_t ThisLength = std::min(Length, uint64_t(256));
5849 // The previous iteration might have created out-of-range displacements.
5850 // Apply them using LAY if so.
5851 if (!isUInt<12>(DestDisp)) {
5852 unsigned Reg = MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass);
5853 BuildMI(*MBB, MI, MI.getDebugLoc(), TII->get(SystemZ::LAY), Reg)
5854 .addOperand(DestBase)
5857 DestBase = MachineOperand::CreateReg(Reg, false);
5860 if (!isUInt<12>(SrcDisp)) {
5861 unsigned Reg = MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass);
5862 BuildMI(*MBB, MI, MI.getDebugLoc(), TII->get(SystemZ::LAY), Reg)
5863 .addOperand(SrcBase)
5866 SrcBase = MachineOperand::CreateReg(Reg, false);
5869 BuildMI(*MBB, MI, DL, TII->get(Opcode))
5870 .addOperand(DestBase).addImm(DestDisp).addImm(ThisLength)
5871 .addOperand(SrcBase).addImm(SrcDisp);
5872 DestDisp += ThisLength;
5873 SrcDisp += ThisLength;
5874 Length -= ThisLength;
5875 // If there's another CLC to go, branch to the end if a difference
5877 if (EndMBB && Length > 0) {
5878 MachineBasicBlock *NextMBB = splitBlockBefore(MI, MBB);
5879 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
5880 .addImm(SystemZ::CCMASK_ICMP).addImm(SystemZ::CCMASK_CMP_NE)
5882 MBB->addSuccessor(EndMBB);
5883 MBB->addSuccessor(NextMBB);
5888 MBB->addSuccessor(EndMBB);
5890 MBB->addLiveIn(SystemZ::CC);
5893 MI.eraseFromParent();
5897 // Decompose string pseudo-instruction MI into a loop that continually performs
5898 // Opcode until CC != 3.
5899 MachineBasicBlock *SystemZTargetLowering::emitStringWrapper(
5900 MachineInstr &MI, MachineBasicBlock *MBB, unsigned Opcode) const {
5901 MachineFunction &MF = *MBB->getParent();
5902 const SystemZInstrInfo *TII =
5903 static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
5904 MachineRegisterInfo &MRI = MF.getRegInfo();
5905 DebugLoc DL = MI.getDebugLoc();
5907 uint64_t End1Reg = MI.getOperand(0).getReg();
5908 uint64_t Start1Reg = MI.getOperand(1).getReg();
5909 uint64_t Start2Reg = MI.getOperand(2).getReg();
5910 uint64_t CharReg = MI.getOperand(3).getReg();
5912 const TargetRegisterClass *RC = &SystemZ::GR64BitRegClass;
5913 uint64_t This1Reg = MRI.createVirtualRegister(RC);
5914 uint64_t This2Reg = MRI.createVirtualRegister(RC);
5915 uint64_t End2Reg = MRI.createVirtualRegister(RC);
5917 MachineBasicBlock *StartMBB = MBB;
5918 MachineBasicBlock *DoneMBB = splitBlockBefore(MI, MBB);
5919 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
5922 // # fall through to LoopMMB
5923 MBB->addSuccessor(LoopMBB);
5926 // %This1Reg = phi [ %Start1Reg, StartMBB ], [ %End1Reg, LoopMBB ]
5927 // %This2Reg = phi [ %Start2Reg, StartMBB ], [ %End2Reg, LoopMBB ]
5929 // %End1Reg, %End2Reg = CLST %This1Reg, %This2Reg -- uses R0L
5931 // # fall through to DoneMMB
5933 // The load of R0L can be hoisted by post-RA LICM.
5936 BuildMI(MBB, DL, TII->get(SystemZ::PHI), This1Reg)
5937 .addReg(Start1Reg).addMBB(StartMBB)
5938 .addReg(End1Reg).addMBB(LoopMBB);
5939 BuildMI(MBB, DL, TII->get(SystemZ::PHI), This2Reg)
5940 .addReg(Start2Reg).addMBB(StartMBB)
5941 .addReg(End2Reg).addMBB(LoopMBB);
5942 BuildMI(MBB, DL, TII->get(TargetOpcode::COPY), SystemZ::R0L).addReg(CharReg);
5943 BuildMI(MBB, DL, TII->get(Opcode))
5944 .addReg(End1Reg, RegState::Define).addReg(End2Reg, RegState::Define)
5945 .addReg(This1Reg).addReg(This2Reg);
5946 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
5947 .addImm(SystemZ::CCMASK_ANY).addImm(SystemZ::CCMASK_3).addMBB(LoopMBB);
5948 MBB->addSuccessor(LoopMBB);
5949 MBB->addSuccessor(DoneMBB);
5951 DoneMBB->addLiveIn(SystemZ::CC);
5953 MI.eraseFromParent();
5957 // Update TBEGIN instruction with final opcode and register clobbers.
5958 MachineBasicBlock *SystemZTargetLowering::emitTransactionBegin(
5959 MachineInstr &MI, MachineBasicBlock *MBB, unsigned Opcode,
5960 bool NoFloat) const {
5961 MachineFunction &MF = *MBB->getParent();
5962 const TargetFrameLowering *TFI = Subtarget.getFrameLowering();
5963 const SystemZInstrInfo *TII = Subtarget.getInstrInfo();
5966 MI.setDesc(TII->get(Opcode));
5968 // We cannot handle a TBEGIN that clobbers the stack or frame pointer.
5969 // Make sure to add the corresponding GRSM bits if they are missing.
5970 uint64_t Control = MI.getOperand(2).getImm();
5971 static const unsigned GPRControlBit[16] = {
5972 0x8000, 0x8000, 0x4000, 0x4000, 0x2000, 0x2000, 0x1000, 0x1000,
5973 0x0800, 0x0800, 0x0400, 0x0400, 0x0200, 0x0200, 0x0100, 0x0100
5975 Control |= GPRControlBit[15];
5977 Control |= GPRControlBit[11];
5978 MI.getOperand(2).setImm(Control);
5980 // Add GPR clobbers.
5981 for (int I = 0; I < 16; I++) {
5982 if ((Control & GPRControlBit[I]) == 0) {
5983 unsigned Reg = SystemZMC::GR64Regs[I];
5984 MI.addOperand(MachineOperand::CreateReg(Reg, true, true));
5988 // Add FPR/VR clobbers.
5989 if (!NoFloat && (Control & 4) != 0) {
5990 if (Subtarget.hasVector()) {
5991 for (int I = 0; I < 32; I++) {
5992 unsigned Reg = SystemZMC::VR128Regs[I];
5993 MI.addOperand(MachineOperand::CreateReg(Reg, true, true));
5996 for (int I = 0; I < 16; I++) {
5997 unsigned Reg = SystemZMC::FP64Regs[I];
5998 MI.addOperand(MachineOperand::CreateReg(Reg, true, true));
6006 MachineBasicBlock *SystemZTargetLowering::emitLoadAndTestCmp0(
6007 MachineInstr &MI, MachineBasicBlock *MBB, unsigned Opcode) const {
6008 MachineFunction &MF = *MBB->getParent();
6009 MachineRegisterInfo *MRI = &MF.getRegInfo();
6010 const SystemZInstrInfo *TII =
6011 static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
6012 DebugLoc DL = MI.getDebugLoc();
6014 unsigned SrcReg = MI.getOperand(0).getReg();
6016 // Create new virtual register of the same class as source.
6017 const TargetRegisterClass *RC = MRI->getRegClass(SrcReg);
6018 unsigned DstReg = MRI->createVirtualRegister(RC);
6020 // Replace pseudo with a normal load-and-test that models the def as
6022 BuildMI(*MBB, MI, DL, TII->get(Opcode), DstReg)
6024 MI.eraseFromParent();
6029 MachineBasicBlock *SystemZTargetLowering::EmitInstrWithCustomInserter(
6030 MachineInstr &MI, MachineBasicBlock *MBB) const {
6031 switch (MI.getOpcode()) {
6032 case SystemZ::Select32Mux:
6033 return emitSelect(MI, MBB,
6034 Subtarget.hasLoadStoreOnCond2()? SystemZ::LOCRMux : 0);
6035 case SystemZ::Select32:
6036 return emitSelect(MI, MBB, SystemZ::LOCR);
6037 case SystemZ::Select64:
6038 return emitSelect(MI, MBB, SystemZ::LOCGR);
6039 case SystemZ::SelectF32:
6040 case SystemZ::SelectF64:
6041 case SystemZ::SelectF128:
6042 return emitSelect(MI, MBB, 0);
6044 case SystemZ::CondStore8Mux:
6045 return emitCondStore(MI, MBB, SystemZ::STCMux, 0, false);
6046 case SystemZ::CondStore8MuxInv:
6047 return emitCondStore(MI, MBB, SystemZ::STCMux, 0, true);
6048 case SystemZ::CondStore16Mux:
6049 return emitCondStore(MI, MBB, SystemZ::STHMux, 0, false);
6050 case SystemZ::CondStore16MuxInv:
6051 return emitCondStore(MI, MBB, SystemZ::STHMux, 0, true);
6052 case SystemZ::CondStore32Mux:
6053 return emitCondStore(MI, MBB, SystemZ::STMux, SystemZ::STOCMux, false);
6054 case SystemZ::CondStore32MuxInv:
6055 return emitCondStore(MI, MBB, SystemZ::STMux, SystemZ::STOCMux, true);
6056 case SystemZ::CondStore8:
6057 return emitCondStore(MI, MBB, SystemZ::STC, 0, false);
6058 case SystemZ::CondStore8Inv:
6059 return emitCondStore(MI, MBB, SystemZ::STC, 0, true);
6060 case SystemZ::CondStore16:
6061 return emitCondStore(MI, MBB, SystemZ::STH, 0, false);
6062 case SystemZ::CondStore16Inv:
6063 return emitCondStore(MI, MBB, SystemZ::STH, 0, true);
6064 case SystemZ::CondStore32:
6065 return emitCondStore(MI, MBB, SystemZ::ST, SystemZ::STOC, false);
6066 case SystemZ::CondStore32Inv:
6067 return emitCondStore(MI, MBB, SystemZ::ST, SystemZ::STOC, true);
6068 case SystemZ::CondStore64:
6069 return emitCondStore(MI, MBB, SystemZ::STG, SystemZ::STOCG, false);
6070 case SystemZ::CondStore64Inv:
6071 return emitCondStore(MI, MBB, SystemZ::STG, SystemZ::STOCG, true);
6072 case SystemZ::CondStoreF32:
6073 return emitCondStore(MI, MBB, SystemZ::STE, 0, false);
6074 case SystemZ::CondStoreF32Inv:
6075 return emitCondStore(MI, MBB, SystemZ::STE, 0, true);
6076 case SystemZ::CondStoreF64:
6077 return emitCondStore(MI, MBB, SystemZ::STD, 0, false);
6078 case SystemZ::CondStoreF64Inv:
6079 return emitCondStore(MI, MBB, SystemZ::STD, 0, true);
6081 case SystemZ::AEXT128_64:
6082 return emitExt128(MI, MBB, false, SystemZ::subreg_l64);
6083 case SystemZ::ZEXT128_32:
6084 return emitExt128(MI, MBB, true, SystemZ::subreg_l32);
6085 case SystemZ::ZEXT128_64:
6086 return emitExt128(MI, MBB, true, SystemZ::subreg_l64);
6088 case SystemZ::ATOMIC_SWAPW:
6089 return emitAtomicLoadBinary(MI, MBB, 0, 0);
6090 case SystemZ::ATOMIC_SWAP_32:
6091 return emitAtomicLoadBinary(MI, MBB, 0, 32);
6092 case SystemZ::ATOMIC_SWAP_64:
6093 return emitAtomicLoadBinary(MI, MBB, 0, 64);
6095 case SystemZ::ATOMIC_LOADW_AR:
6096 return emitAtomicLoadBinary(MI, MBB, SystemZ::AR, 0);
6097 case SystemZ::ATOMIC_LOADW_AFI:
6098 return emitAtomicLoadBinary(MI, MBB, SystemZ::AFI, 0);
6099 case SystemZ::ATOMIC_LOAD_AR:
6100 return emitAtomicLoadBinary(MI, MBB, SystemZ::AR, 32);
6101 case SystemZ::ATOMIC_LOAD_AHI:
6102 return emitAtomicLoadBinary(MI, MBB, SystemZ::AHI, 32);
6103 case SystemZ::ATOMIC_LOAD_AFI:
6104 return emitAtomicLoadBinary(MI, MBB, SystemZ::AFI, 32);
6105 case SystemZ::ATOMIC_LOAD_AGR:
6106 return emitAtomicLoadBinary(MI, MBB, SystemZ::AGR, 64);
6107 case SystemZ::ATOMIC_LOAD_AGHI:
6108 return emitAtomicLoadBinary(MI, MBB, SystemZ::AGHI, 64);
6109 case SystemZ::ATOMIC_LOAD_AGFI:
6110 return emitAtomicLoadBinary(MI, MBB, SystemZ::AGFI, 64);
6112 case SystemZ::ATOMIC_LOADW_SR:
6113 return emitAtomicLoadBinary(MI, MBB, SystemZ::SR, 0);
6114 case SystemZ::ATOMIC_LOAD_SR:
6115 return emitAtomicLoadBinary(MI, MBB, SystemZ::SR, 32);
6116 case SystemZ::ATOMIC_LOAD_SGR:
6117 return emitAtomicLoadBinary(MI, MBB, SystemZ::SGR, 64);
6119 case SystemZ::ATOMIC_LOADW_NR:
6120 return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 0);
6121 case SystemZ::ATOMIC_LOADW_NILH:
6122 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 0);
6123 case SystemZ::ATOMIC_LOAD_NR:
6124 return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 32);
6125 case SystemZ::ATOMIC_LOAD_NILL:
6126 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL, 32);
6127 case SystemZ::ATOMIC_LOAD_NILH:
6128 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 32);
6129 case SystemZ::ATOMIC_LOAD_NILF:
6130 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF, 32);
6131 case SystemZ::ATOMIC_LOAD_NGR:
6132 return emitAtomicLoadBinary(MI, MBB, SystemZ::NGR, 64);
6133 case SystemZ::ATOMIC_LOAD_NILL64:
6134 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL64, 64);
6135 case SystemZ::ATOMIC_LOAD_NILH64:
6136 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH64, 64);
6137 case SystemZ::ATOMIC_LOAD_NIHL64:
6138 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHL64, 64);
6139 case SystemZ::ATOMIC_LOAD_NIHH64:
6140 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHH64, 64);
6141 case SystemZ::ATOMIC_LOAD_NILF64:
6142 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF64, 64);
6143 case SystemZ::ATOMIC_LOAD_NIHF64:
6144 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHF64, 64);
6146 case SystemZ::ATOMIC_LOADW_OR:
6147 return emitAtomicLoadBinary(MI, MBB, SystemZ::OR, 0);
6148 case SystemZ::ATOMIC_LOADW_OILH:
6149 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILH, 0);
6150 case SystemZ::ATOMIC_LOAD_OR:
6151 return emitAtomicLoadBinary(MI, MBB, SystemZ::OR, 32);
6152 case SystemZ::ATOMIC_LOAD_OILL:
6153 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILL, 32);
6154 case SystemZ::ATOMIC_LOAD_OILH:
6155 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILH, 32);
6156 case SystemZ::ATOMIC_LOAD_OILF:
6157 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILF, 32);
6158 case SystemZ::ATOMIC_LOAD_OGR:
6159 return emitAtomicLoadBinary(MI, MBB, SystemZ::OGR, 64);
6160 case SystemZ::ATOMIC_LOAD_OILL64:
6161 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILL64, 64);
6162 case SystemZ::ATOMIC_LOAD_OILH64:
6163 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILH64, 64);
6164 case SystemZ::ATOMIC_LOAD_OIHL64:
6165 return emitAtomicLoadBinary(MI, MBB, SystemZ::OIHL64, 64);
6166 case SystemZ::ATOMIC_LOAD_OIHH64:
6167 return emitAtomicLoadBinary(MI, MBB, SystemZ::OIHH64, 64);
6168 case SystemZ::ATOMIC_LOAD_OILF64:
6169 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILF64, 64);
6170 case SystemZ::ATOMIC_LOAD_OIHF64:
6171 return emitAtomicLoadBinary(MI, MBB, SystemZ::OIHF64, 64);
6173 case SystemZ::ATOMIC_LOADW_XR:
6174 return emitAtomicLoadBinary(MI, MBB, SystemZ::XR, 0);
6175 case SystemZ::ATOMIC_LOADW_XILF:
6176 return emitAtomicLoadBinary(MI, MBB, SystemZ::XILF, 0);
6177 case SystemZ::ATOMIC_LOAD_XR:
6178 return emitAtomicLoadBinary(MI, MBB, SystemZ::XR, 32);
6179 case SystemZ::ATOMIC_LOAD_XILF:
6180 return emitAtomicLoadBinary(MI, MBB, SystemZ::XILF, 32);
6181 case SystemZ::ATOMIC_LOAD_XGR:
6182 return emitAtomicLoadBinary(MI, MBB, SystemZ::XGR, 64);
6183 case SystemZ::ATOMIC_LOAD_XILF64:
6184 return emitAtomicLoadBinary(MI, MBB, SystemZ::XILF64, 64);
6185 case SystemZ::ATOMIC_LOAD_XIHF64:
6186 return emitAtomicLoadBinary(MI, MBB, SystemZ::XIHF64, 64);
6188 case SystemZ::ATOMIC_LOADW_NRi:
6189 return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 0, true);
6190 case SystemZ::ATOMIC_LOADW_NILHi:
6191 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 0, true);
6192 case SystemZ::ATOMIC_LOAD_NRi:
6193 return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 32, true);
6194 case SystemZ::ATOMIC_LOAD_NILLi:
6195 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL, 32, true);
6196 case SystemZ::ATOMIC_LOAD_NILHi:
6197 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 32, true);
6198 case SystemZ::ATOMIC_LOAD_NILFi:
6199 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF, 32, true);
6200 case SystemZ::ATOMIC_LOAD_NGRi:
6201 return emitAtomicLoadBinary(MI, MBB, SystemZ::NGR, 64, true);
6202 case SystemZ::ATOMIC_LOAD_NILL64i:
6203 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL64, 64, true);
6204 case SystemZ::ATOMIC_LOAD_NILH64i:
6205 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH64, 64, true);
6206 case SystemZ::ATOMIC_LOAD_NIHL64i:
6207 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHL64, 64, true);
6208 case SystemZ::ATOMIC_LOAD_NIHH64i:
6209 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHH64, 64, true);
6210 case SystemZ::ATOMIC_LOAD_NILF64i:
6211 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF64, 64, true);
6212 case SystemZ::ATOMIC_LOAD_NIHF64i:
6213 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHF64, 64, true);
6215 case SystemZ::ATOMIC_LOADW_MIN:
6216 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
6217 SystemZ::CCMASK_CMP_LE, 0);
6218 case SystemZ::ATOMIC_LOAD_MIN_32:
6219 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
6220 SystemZ::CCMASK_CMP_LE, 32);
6221 case SystemZ::ATOMIC_LOAD_MIN_64:
6222 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CGR,
6223 SystemZ::CCMASK_CMP_LE, 64);
6225 case SystemZ::ATOMIC_LOADW_MAX:
6226 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
6227 SystemZ::CCMASK_CMP_GE, 0);
6228 case SystemZ::ATOMIC_LOAD_MAX_32:
6229 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
6230 SystemZ::CCMASK_CMP_GE, 32);
6231 case SystemZ::ATOMIC_LOAD_MAX_64:
6232 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CGR,
6233 SystemZ::CCMASK_CMP_GE, 64);
6235 case SystemZ::ATOMIC_LOADW_UMIN:
6236 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
6237 SystemZ::CCMASK_CMP_LE, 0);
6238 case SystemZ::ATOMIC_LOAD_UMIN_32:
6239 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
6240 SystemZ::CCMASK_CMP_LE, 32);
6241 case SystemZ::ATOMIC_LOAD_UMIN_64:
6242 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLGR,
6243 SystemZ::CCMASK_CMP_LE, 64);
6245 case SystemZ::ATOMIC_LOADW_UMAX:
6246 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
6247 SystemZ::CCMASK_CMP_GE, 0);
6248 case SystemZ::ATOMIC_LOAD_UMAX_32:
6249 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
6250 SystemZ::CCMASK_CMP_GE, 32);
6251 case SystemZ::ATOMIC_LOAD_UMAX_64:
6252 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLGR,
6253 SystemZ::CCMASK_CMP_GE, 64);
6255 case SystemZ::ATOMIC_CMP_SWAPW:
6256 return emitAtomicCmpSwapW(MI, MBB);
6257 case SystemZ::MVCSequence:
6258 case SystemZ::MVCLoop:
6259 return emitMemMemWrapper(MI, MBB, SystemZ::MVC);
6260 case SystemZ::NCSequence:
6261 case SystemZ::NCLoop:
6262 return emitMemMemWrapper(MI, MBB, SystemZ::NC);
6263 case SystemZ::OCSequence:
6264 case SystemZ::OCLoop:
6265 return emitMemMemWrapper(MI, MBB, SystemZ::OC);
6266 case SystemZ::XCSequence:
6267 case SystemZ::XCLoop:
6268 return emitMemMemWrapper(MI, MBB, SystemZ::XC);
6269 case SystemZ::CLCSequence:
6270 case SystemZ::CLCLoop:
6271 return emitMemMemWrapper(MI, MBB, SystemZ::CLC);
6272 case SystemZ::CLSTLoop:
6273 return emitStringWrapper(MI, MBB, SystemZ::CLST);
6274 case SystemZ::MVSTLoop:
6275 return emitStringWrapper(MI, MBB, SystemZ::MVST);
6276 case SystemZ::SRSTLoop:
6277 return emitStringWrapper(MI, MBB, SystemZ::SRST);
6278 case SystemZ::TBEGIN:
6279 return emitTransactionBegin(MI, MBB, SystemZ::TBEGIN, false);
6280 case SystemZ::TBEGIN_nofloat:
6281 return emitTransactionBegin(MI, MBB, SystemZ::TBEGIN, true);
6282 case SystemZ::TBEGINC:
6283 return emitTransactionBegin(MI, MBB, SystemZ::TBEGINC, true);
6284 case SystemZ::LTEBRCompare_VecPseudo:
6285 return emitLoadAndTestCmp0(MI, MBB, SystemZ::LTEBR);
6286 case SystemZ::LTDBRCompare_VecPseudo:
6287 return emitLoadAndTestCmp0(MI, MBB, SystemZ::LTDBR);
6288 case SystemZ::LTXBRCompare_VecPseudo:
6289 return emitLoadAndTestCmp0(MI, MBB, SystemZ::LTXBR);
6292 llvm_unreachable("Unexpected instr type to insert");