1 //===-- SystemZISelLowering.cpp - SystemZ DAG lowering implementation -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SystemZTargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "SystemZISelLowering.h"
15 #include "SystemZCallingConv.h"
16 #include "SystemZConstantPoolValue.h"
17 #include "SystemZMachineFunctionInfo.h"
18 #include "SystemZTargetMachine.h"
19 #include "llvm/CodeGen/CallingConvLower.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
23 #include "llvm/Support/CommandLine.h"
24 #include "llvm/IR/Intrinsics.h"
29 #define DEBUG_TYPE "systemz-lower"
32 // Represents a sequence for extracting a 0/1 value from an IPM result:
33 // (((X ^ XORValue) + AddValue) >> Bit)
34 struct IPMConversion {
35 IPMConversion(unsigned xorValue, int64_t addValue, unsigned bit)
36 : XORValue(xorValue), AddValue(addValue), Bit(bit) {}
43 // Represents information about a comparison.
45 Comparison(SDValue Op0In, SDValue Op1In)
46 : Op0(Op0In), Op1(Op1In), Opcode(0), ICmpType(0), CCValid(0), CCMask(0) {}
48 // The operands to the comparison.
51 // The opcode that should be used to compare Op0 and Op1.
54 // A SystemZICMP value. Only used for integer comparisons.
57 // The mask of CC values that Opcode can produce.
60 // The mask of CC values for which the original condition is true.
63 } // end anonymous namespace
65 // Classify VT as either 32 or 64 bit.
66 static bool is32Bit(EVT VT) {
67 switch (VT.getSimpleVT().SimpleTy) {
73 llvm_unreachable("Unsupported type");
77 // Return a version of MachineOperand that can be safely used before the
79 static MachineOperand earlyUseOperand(MachineOperand Op) {
85 SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &TM,
86 const SystemZSubtarget &STI)
87 : TargetLowering(TM), Subtarget(STI) {
88 MVT PtrVT = MVT::getIntegerVT(8 * TM.getPointerSize());
90 // Set up the register classes.
91 if (Subtarget.hasHighWord())
92 addRegisterClass(MVT::i32, &SystemZ::GRX32BitRegClass);
94 addRegisterClass(MVT::i32, &SystemZ::GR32BitRegClass);
95 addRegisterClass(MVT::i64, &SystemZ::GR64BitRegClass);
96 if (Subtarget.hasVector()) {
97 addRegisterClass(MVT::f32, &SystemZ::VR32BitRegClass);
98 addRegisterClass(MVT::f64, &SystemZ::VR64BitRegClass);
100 addRegisterClass(MVT::f32, &SystemZ::FP32BitRegClass);
101 addRegisterClass(MVT::f64, &SystemZ::FP64BitRegClass);
103 addRegisterClass(MVT::f128, &SystemZ::FP128BitRegClass);
105 if (Subtarget.hasVector()) {
106 addRegisterClass(MVT::v16i8, &SystemZ::VR128BitRegClass);
107 addRegisterClass(MVT::v8i16, &SystemZ::VR128BitRegClass);
108 addRegisterClass(MVT::v4i32, &SystemZ::VR128BitRegClass);
109 addRegisterClass(MVT::v2i64, &SystemZ::VR128BitRegClass);
110 addRegisterClass(MVT::v4f32, &SystemZ::VR128BitRegClass);
111 addRegisterClass(MVT::v2f64, &SystemZ::VR128BitRegClass);
114 // Compute derived properties from the register classes
115 computeRegisterProperties(Subtarget.getRegisterInfo());
117 // Set up special registers.
118 setStackPointerRegisterToSaveRestore(SystemZ::R15D);
120 // TODO: It may be better to default to latency-oriented scheduling, however
121 // LLVM's current latency-oriented scheduler can't handle physreg definitions
122 // such as SystemZ has with CC, so set this to the register-pressure
123 // scheduler, because it can.
124 setSchedulingPreference(Sched::RegPressure);
126 setBooleanContents(ZeroOrOneBooleanContent);
127 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
129 // Instructions are strings of 2-byte aligned 2-byte values.
130 setMinFunctionAlignment(2);
132 // Handle operations that are handled in a similar way for all types.
133 for (unsigned I = MVT::FIRST_INTEGER_VALUETYPE;
134 I <= MVT::LAST_FP_VALUETYPE;
136 MVT VT = MVT::SimpleValueType(I);
137 if (isTypeLegal(VT)) {
138 // Lower SET_CC into an IPM-based sequence.
139 setOperationAction(ISD::SETCC, VT, Custom);
141 // Expand SELECT(C, A, B) into SELECT_CC(X, 0, A, B, NE).
142 setOperationAction(ISD::SELECT, VT, Expand);
144 // Lower SELECT_CC and BR_CC into separate comparisons and branches.
145 setOperationAction(ISD::SELECT_CC, VT, Custom);
146 setOperationAction(ISD::BR_CC, VT, Custom);
150 // Expand jump table branches as address arithmetic followed by an
152 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
154 // Expand BRCOND into a BR_CC (see above).
155 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
157 // Handle integer types.
158 for (unsigned I = MVT::FIRST_INTEGER_VALUETYPE;
159 I <= MVT::LAST_INTEGER_VALUETYPE;
161 MVT VT = MVT::SimpleValueType(I);
162 if (isTypeLegal(VT)) {
163 // Expand individual DIV and REMs into DIVREMs.
164 setOperationAction(ISD::SDIV, VT, Expand);
165 setOperationAction(ISD::UDIV, VT, Expand);
166 setOperationAction(ISD::SREM, VT, Expand);
167 setOperationAction(ISD::UREM, VT, Expand);
168 setOperationAction(ISD::SDIVREM, VT, Custom);
169 setOperationAction(ISD::UDIVREM, VT, Custom);
171 // Lower ATOMIC_LOAD and ATOMIC_STORE into normal volatile loads and
172 // stores, putting a serialization instruction after the stores.
173 setOperationAction(ISD::ATOMIC_LOAD, VT, Custom);
174 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
176 // Lower ATOMIC_LOAD_SUB into ATOMIC_LOAD_ADD if LAA and LAAG are
177 // available, or if the operand is constant.
178 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
180 // Use POPCNT on z196 and above.
181 if (Subtarget.hasPopulationCount())
182 setOperationAction(ISD::CTPOP, VT, Custom);
184 setOperationAction(ISD::CTPOP, VT, Expand);
186 // No special instructions for these.
187 setOperationAction(ISD::CTTZ, VT, Expand);
188 setOperationAction(ISD::ROTR, VT, Expand);
190 // Use *MUL_LOHI where possible instead of MULH*.
191 setOperationAction(ISD::MULHS, VT, Expand);
192 setOperationAction(ISD::MULHU, VT, Expand);
193 setOperationAction(ISD::SMUL_LOHI, VT, Custom);
194 setOperationAction(ISD::UMUL_LOHI, VT, Custom);
196 // Only z196 and above have native support for conversions to unsigned.
197 // On z10, promoting to i64 doesn't generate an inexact condition for
198 // values that are outside the i32 range but in the i64 range, so use
199 // the default expansion.
200 if (!Subtarget.hasFPExtension())
201 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
205 // Type legalization will convert 8- and 16-bit atomic operations into
206 // forms that operate on i32s (but still keeping the original memory VT).
207 // Lower them into full i32 operations.
208 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Custom);
209 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Custom);
210 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom);
211 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Custom);
212 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Custom);
213 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Custom);
214 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Custom);
215 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Custom);
216 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Custom);
217 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Custom);
218 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Custom);
219 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
221 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
223 // Traps are legal, as we will convert them to "j .+2".
224 setOperationAction(ISD::TRAP, MVT::Other, Legal);
226 // z10 has instructions for signed but not unsigned FP conversion.
227 // Handle unsigned 32-bit types as signed 64-bit types.
228 if (!Subtarget.hasFPExtension()) {
229 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Promote);
230 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
233 // We have native support for a 64-bit CTLZ, via FLOGR.
234 setOperationAction(ISD::CTLZ, MVT::i32, Promote);
235 setOperationAction(ISD::CTLZ, MVT::i64, Legal);
237 // Give LowerOperation the chance to replace 64-bit ORs with subregs.
238 setOperationAction(ISD::OR, MVT::i64, Custom);
240 // FIXME: Can we support these natively?
241 setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand);
242 setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand);
243 setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand);
245 // We have native instructions for i8, i16 and i32 extensions, but not i1.
246 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
247 for (MVT VT : MVT::integer_valuetypes()) {
248 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
249 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
250 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
253 // Handle the various types of symbolic address.
254 setOperationAction(ISD::ConstantPool, PtrVT, Custom);
255 setOperationAction(ISD::GlobalAddress, PtrVT, Custom);
256 setOperationAction(ISD::GlobalTLSAddress, PtrVT, Custom);
257 setOperationAction(ISD::BlockAddress, PtrVT, Custom);
258 setOperationAction(ISD::JumpTable, PtrVT, Custom);
260 // We need to handle dynamic allocations specially because of the
261 // 160-byte area at the bottom of the stack.
262 setOperationAction(ISD::DYNAMIC_STACKALLOC, PtrVT, Custom);
263 setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, PtrVT, Custom);
265 // Use custom expanders so that we can force the function to use
267 setOperationAction(ISD::STACKSAVE, MVT::Other, Custom);
268 setOperationAction(ISD::STACKRESTORE, MVT::Other, Custom);
270 // Handle prefetches with PFD or PFDRL.
271 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
273 for (MVT VT : MVT::vector_valuetypes()) {
274 // Assume by default that all vector operations need to be expanded.
275 for (unsigned Opcode = 0; Opcode < ISD::BUILTIN_OP_END; ++Opcode)
276 if (getOperationAction(Opcode, VT) == Legal)
277 setOperationAction(Opcode, VT, Expand);
279 // Likewise all truncating stores and extending loads.
280 for (MVT InnerVT : MVT::vector_valuetypes()) {
281 setTruncStoreAction(VT, InnerVT, Expand);
282 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
283 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
284 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
287 if (isTypeLegal(VT)) {
288 // These operations are legal for anything that can be stored in a
289 // vector register, even if there is no native support for the format
290 // as such. In particular, we can do these for v4f32 even though there
291 // are no specific instructions for that format.
292 setOperationAction(ISD::LOAD, VT, Legal);
293 setOperationAction(ISD::STORE, VT, Legal);
294 setOperationAction(ISD::VSELECT, VT, Legal);
295 setOperationAction(ISD::BITCAST, VT, Legal);
296 setOperationAction(ISD::UNDEF, VT, Legal);
298 // Likewise, except that we need to replace the nodes with something
300 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
301 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
305 // Handle integer vector types.
306 for (MVT VT : MVT::integer_vector_valuetypes()) {
307 if (isTypeLegal(VT)) {
308 // These operations have direct equivalents.
309 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Legal);
310 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Legal);
311 setOperationAction(ISD::ADD, VT, Legal);
312 setOperationAction(ISD::SUB, VT, Legal);
313 if (VT != MVT::v2i64)
314 setOperationAction(ISD::MUL, VT, Legal);
315 setOperationAction(ISD::AND, VT, Legal);
316 setOperationAction(ISD::OR, VT, Legal);
317 setOperationAction(ISD::XOR, VT, Legal);
318 setOperationAction(ISD::CTPOP, VT, Custom);
319 setOperationAction(ISD::CTTZ, VT, Legal);
320 setOperationAction(ISD::CTLZ, VT, Legal);
322 // Convert a GPR scalar to a vector by inserting it into element 0.
323 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
325 // Use a series of unpacks for extensions.
326 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Custom);
327 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Custom);
329 // Detect shifts by a scalar amount and convert them into
331 setOperationAction(ISD::SHL, VT, Custom);
332 setOperationAction(ISD::SRA, VT, Custom);
333 setOperationAction(ISD::SRL, VT, Custom);
335 // At present ROTL isn't matched by DAGCombiner. ROTR should be
336 // converted into ROTL.
337 setOperationAction(ISD::ROTL, VT, Expand);
338 setOperationAction(ISD::ROTR, VT, Expand);
340 // Map SETCCs onto one of VCE, VCH or VCHL, swapping the operands
341 // and inverting the result as necessary.
342 setOperationAction(ISD::SETCC, VT, Custom);
346 if (Subtarget.hasVector()) {
347 // There should be no need to check for float types other than v2f64
348 // since <2 x f32> isn't a legal type.
349 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
350 setOperationAction(ISD::FP_TO_SINT, MVT::v2f64, Legal);
351 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
352 setOperationAction(ISD::FP_TO_UINT, MVT::v2f64, Legal);
353 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
354 setOperationAction(ISD::SINT_TO_FP, MVT::v2f64, Legal);
355 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
356 setOperationAction(ISD::UINT_TO_FP, MVT::v2f64, Legal);
359 // Handle floating-point types.
360 for (unsigned I = MVT::FIRST_FP_VALUETYPE;
361 I <= MVT::LAST_FP_VALUETYPE;
363 MVT VT = MVT::SimpleValueType(I);
364 if (isTypeLegal(VT)) {
365 // We can use FI for FRINT.
366 setOperationAction(ISD::FRINT, VT, Legal);
368 // We can use the extended form of FI for other rounding operations.
369 if (Subtarget.hasFPExtension()) {
370 setOperationAction(ISD::FNEARBYINT, VT, Legal);
371 setOperationAction(ISD::FFLOOR, VT, Legal);
372 setOperationAction(ISD::FCEIL, VT, Legal);
373 setOperationAction(ISD::FTRUNC, VT, Legal);
374 setOperationAction(ISD::FROUND, VT, Legal);
377 // No special instructions for these.
378 setOperationAction(ISD::FSIN, VT, Expand);
379 setOperationAction(ISD::FCOS, VT, Expand);
380 setOperationAction(ISD::FSINCOS, VT, Expand);
381 setOperationAction(ISD::FREM, VT, Expand);
382 setOperationAction(ISD::FPOW, VT, Expand);
386 // Handle floating-point vector types.
387 if (Subtarget.hasVector()) {
388 // Scalar-to-vector conversion is just a subreg.
389 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal);
390 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
392 // Some insertions and extractions can be done directly but others
393 // need to go via integers.
394 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
395 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
396 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
397 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
399 // These operations have direct equivalents.
400 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
401 setOperationAction(ISD::FNEG, MVT::v2f64, Legal);
402 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
403 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
404 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
405 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
406 setOperationAction(ISD::FABS, MVT::v2f64, Legal);
407 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
408 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
409 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
410 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
411 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
412 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
413 setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
416 // We have fused multiply-addition for f32 and f64 but not f128.
417 setOperationAction(ISD::FMA, MVT::f32, Legal);
418 setOperationAction(ISD::FMA, MVT::f64, Legal);
419 setOperationAction(ISD::FMA, MVT::f128, Expand);
421 // Needed so that we don't try to implement f128 constant loads using
422 // a load-and-extend of a f80 constant (in cases where the constant
423 // would fit in an f80).
424 for (MVT VT : MVT::fp_valuetypes())
425 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f80, Expand);
427 // Floating-point truncation and stores need to be done separately.
428 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
429 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
430 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
432 // We have 64-bit FPR<->GPR moves, but need special handling for
434 if (!Subtarget.hasVector()) {
435 setOperationAction(ISD::BITCAST, MVT::i32, Custom);
436 setOperationAction(ISD::BITCAST, MVT::f32, Custom);
439 // VASTART and VACOPY need to deal with the SystemZ-specific varargs
440 // structure, but VAEND is a no-op.
441 setOperationAction(ISD::VASTART, MVT::Other, Custom);
442 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
443 setOperationAction(ISD::VAEND, MVT::Other, Expand);
445 // Codes for which we want to perform some z-specific combinations.
446 setTargetDAGCombine(ISD::SIGN_EXTEND);
447 setTargetDAGCombine(ISD::STORE);
448 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
449 setTargetDAGCombine(ISD::FP_ROUND);
450 setTargetDAGCombine(ISD::BSWAP);
451 setTargetDAGCombine(ISD::SHL);
452 setTargetDAGCombine(ISD::SRA);
453 setTargetDAGCombine(ISD::SRL);
454 setTargetDAGCombine(ISD::ROTL);
456 // Handle intrinsics.
457 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
458 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
460 // We want to use MVC in preference to even a single load/store pair.
461 MaxStoresPerMemcpy = 0;
462 MaxStoresPerMemcpyOptSize = 0;
464 // The main memset sequence is a byte store followed by an MVC.
465 // Two STC or MV..I stores win over that, but the kind of fused stores
466 // generated by target-independent code don't when the byte value is
467 // variable. E.g. "STC <reg>;MHI <reg>,257;STH <reg>" is not better
468 // than "STC;MVC". Handle the choice in target-specific code instead.
469 MaxStoresPerMemset = 0;
470 MaxStoresPerMemsetOptSize = 0;
473 EVT SystemZTargetLowering::getSetCCResultType(const DataLayout &DL,
474 LLVMContext &, EVT VT) const {
477 return VT.changeVectorElementTypeToInteger();
480 bool SystemZTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
481 VT = VT.getScalarType();
486 switch (VT.getSimpleVT().SimpleTy) {
499 bool SystemZTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
500 // We can load zero using LZ?R and negative zero using LZ?R;LC?BR.
501 return Imm.isZero() || Imm.isNegZero();
504 bool SystemZTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
505 // We can use CGFI or CLGFI.
506 return isInt<32>(Imm) || isUInt<32>(Imm);
509 bool SystemZTargetLowering::isLegalAddImmediate(int64_t Imm) const {
510 // We can use ALGFI or SLGFI.
511 return isUInt<32>(Imm) || isUInt<32>(-Imm);
514 bool SystemZTargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
518 // Unaligned accesses should never be slower than the expanded version.
519 // We check specifically for aligned accesses in the few cases where
520 // they are required.
526 bool SystemZTargetLowering::isLegalAddressingMode(const DataLayout &DL,
527 const AddrMode &AM, Type *Ty,
529 // Punt on globals for now, although they can be used in limited
530 // RELATIVE LONG cases.
534 // Require a 20-bit signed offset.
535 if (!isInt<20>(AM.BaseOffs))
538 // Indexing is OK but no scale factor can be applied.
539 return AM.Scale == 0 || AM.Scale == 1;
542 bool SystemZTargetLowering::isFoldableMemAccessOffset(Instruction *I,
543 int64_t Offset) const {
544 // This only applies to z13.
545 if (!Subtarget.hasVector())
548 // * Use LDE instead of LE/LEY to avoid partial register
549 // dependencies (LDE only supports small offsets).
550 // * Utilize the vector registers to hold floating point
551 // values (vector load / store instructions only support small
554 assert (isa<LoadInst>(I) || isa<StoreInst>(I));
555 Type *MemAccessTy = (isa<LoadInst>(I) ? I->getType() :
556 I->getOperand(0)->getType());
557 bool IsFPAccess = MemAccessTy->isFloatingPointTy();
558 bool IsVectorAccess = MemAccessTy->isVectorTy();
560 // A store of an extracted vector element will be combined into a VSTE type
562 if (!IsVectorAccess && isa<StoreInst>(I)) {
563 Value *DataOp = I->getOperand(0);
564 if (isa<ExtractElementInst>(DataOp))
565 IsVectorAccess = true;
568 // A load which gets inserted into a vector element will be combined into a
569 // VLE type instruction.
570 if (!IsVectorAccess && isa<LoadInst>(I) && I->hasOneUse()) {
571 User *LoadUser = *I->user_begin();
572 if (isa<InsertElementInst>(LoadUser))
573 IsVectorAccess = true;
576 if (!isUInt<12>(Offset) && (IsFPAccess || IsVectorAccess))
582 bool SystemZTargetLowering::isTruncateFree(Type *FromType, Type *ToType) const {
583 if (!FromType->isIntegerTy() || !ToType->isIntegerTy())
585 unsigned FromBits = FromType->getPrimitiveSizeInBits();
586 unsigned ToBits = ToType->getPrimitiveSizeInBits();
587 return FromBits > ToBits;
590 bool SystemZTargetLowering::isTruncateFree(EVT FromVT, EVT ToVT) const {
591 if (!FromVT.isInteger() || !ToVT.isInteger())
593 unsigned FromBits = FromVT.getSizeInBits();
594 unsigned ToBits = ToVT.getSizeInBits();
595 return FromBits > ToBits;
598 //===----------------------------------------------------------------------===//
599 // Inline asm support
600 //===----------------------------------------------------------------------===//
602 TargetLowering::ConstraintType
603 SystemZTargetLowering::getConstraintType(StringRef Constraint) const {
604 if (Constraint.size() == 1) {
605 switch (Constraint[0]) {
606 case 'a': // Address register
607 case 'd': // Data register (equivalent to 'r')
608 case 'f': // Floating-point register
609 case 'h': // High-part register
610 case 'r': // General-purpose register
611 return C_RegisterClass;
613 case 'Q': // Memory with base and unsigned 12-bit displacement
614 case 'R': // Likewise, plus an index
615 case 'S': // Memory with base and signed 20-bit displacement
616 case 'T': // Likewise, plus an index
617 case 'm': // Equivalent to 'T'.
620 case 'I': // Unsigned 8-bit constant
621 case 'J': // Unsigned 12-bit constant
622 case 'K': // Signed 16-bit constant
623 case 'L': // Signed 20-bit displacement (on all targets we support)
624 case 'M': // 0x7fffffff
631 return TargetLowering::getConstraintType(Constraint);
634 TargetLowering::ConstraintWeight SystemZTargetLowering::
635 getSingleConstraintMatchWeight(AsmOperandInfo &info,
636 const char *constraint) const {
637 ConstraintWeight weight = CW_Invalid;
638 Value *CallOperandVal = info.CallOperandVal;
639 // If we don't have a value, we can't do a match,
640 // but allow it at the lowest weight.
643 Type *type = CallOperandVal->getType();
644 // Look at the constraint type.
645 switch (*constraint) {
647 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
650 case 'a': // Address register
651 case 'd': // Data register (equivalent to 'r')
652 case 'h': // High-part register
653 case 'r': // General-purpose register
654 if (CallOperandVal->getType()->isIntegerTy())
655 weight = CW_Register;
658 case 'f': // Floating-point register
659 if (type->isFloatingPointTy())
660 weight = CW_Register;
663 case 'I': // Unsigned 8-bit constant
664 if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
665 if (isUInt<8>(C->getZExtValue()))
666 weight = CW_Constant;
669 case 'J': // Unsigned 12-bit constant
670 if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
671 if (isUInt<12>(C->getZExtValue()))
672 weight = CW_Constant;
675 case 'K': // Signed 16-bit constant
676 if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
677 if (isInt<16>(C->getSExtValue()))
678 weight = CW_Constant;
681 case 'L': // Signed 20-bit displacement (on all targets we support)
682 if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
683 if (isInt<20>(C->getSExtValue()))
684 weight = CW_Constant;
687 case 'M': // 0x7fffffff
688 if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
689 if (C->getZExtValue() == 0x7fffffff)
690 weight = CW_Constant;
696 // Parse a "{tNNN}" register constraint for which the register type "t"
697 // has already been verified. MC is the class associated with "t" and
698 // Map maps 0-based register numbers to LLVM register numbers.
699 static std::pair<unsigned, const TargetRegisterClass *>
700 parseRegisterNumber(StringRef Constraint, const TargetRegisterClass *RC,
701 const unsigned *Map) {
702 assert(*(Constraint.end()-1) == '}' && "Missing '}'");
703 if (isdigit(Constraint[2])) {
706 Constraint.slice(2, Constraint.size() - 1).getAsInteger(10, Index);
707 if (!Failed && Index < 16 && Map[Index])
708 return std::make_pair(Map[Index], RC);
710 return std::make_pair(0U, nullptr);
713 std::pair<unsigned, const TargetRegisterClass *>
714 SystemZTargetLowering::getRegForInlineAsmConstraint(
715 const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
716 if (Constraint.size() == 1) {
717 // GCC Constraint Letters
718 switch (Constraint[0]) {
720 case 'd': // Data register (equivalent to 'r')
721 case 'r': // General-purpose register
723 return std::make_pair(0U, &SystemZ::GR64BitRegClass);
724 else if (VT == MVT::i128)
725 return std::make_pair(0U, &SystemZ::GR128BitRegClass);
726 return std::make_pair(0U, &SystemZ::GR32BitRegClass);
728 case 'a': // Address register
730 return std::make_pair(0U, &SystemZ::ADDR64BitRegClass);
731 else if (VT == MVT::i128)
732 return std::make_pair(0U, &SystemZ::ADDR128BitRegClass);
733 return std::make_pair(0U, &SystemZ::ADDR32BitRegClass);
735 case 'h': // High-part register (an LLVM extension)
736 return std::make_pair(0U, &SystemZ::GRH32BitRegClass);
738 case 'f': // Floating-point register
740 return std::make_pair(0U, &SystemZ::FP64BitRegClass);
741 else if (VT == MVT::f128)
742 return std::make_pair(0U, &SystemZ::FP128BitRegClass);
743 return std::make_pair(0U, &SystemZ::FP32BitRegClass);
746 if (Constraint.size() > 0 && Constraint[0] == '{') {
747 // We need to override the default register parsing for GPRs and FPRs
748 // because the interpretation depends on VT. The internal names of
749 // the registers are also different from the external names
750 // (F0D and F0S instead of F0, etc.).
751 if (Constraint[1] == 'r') {
753 return parseRegisterNumber(Constraint, &SystemZ::GR32BitRegClass,
754 SystemZMC::GR32Regs);
756 return parseRegisterNumber(Constraint, &SystemZ::GR128BitRegClass,
757 SystemZMC::GR128Regs);
758 return parseRegisterNumber(Constraint, &SystemZ::GR64BitRegClass,
759 SystemZMC::GR64Regs);
761 if (Constraint[1] == 'f') {
763 return parseRegisterNumber(Constraint, &SystemZ::FP32BitRegClass,
764 SystemZMC::FP32Regs);
766 return parseRegisterNumber(Constraint, &SystemZ::FP128BitRegClass,
767 SystemZMC::FP128Regs);
768 return parseRegisterNumber(Constraint, &SystemZ::FP64BitRegClass,
769 SystemZMC::FP64Regs);
772 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
775 void SystemZTargetLowering::
776 LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
777 std::vector<SDValue> &Ops,
778 SelectionDAG &DAG) const {
779 // Only support length 1 constraints for now.
780 if (Constraint.length() == 1) {
781 switch (Constraint[0]) {
782 case 'I': // Unsigned 8-bit constant
783 if (auto *C = dyn_cast<ConstantSDNode>(Op))
784 if (isUInt<8>(C->getZExtValue()))
785 Ops.push_back(DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
789 case 'J': // Unsigned 12-bit constant
790 if (auto *C = dyn_cast<ConstantSDNode>(Op))
791 if (isUInt<12>(C->getZExtValue()))
792 Ops.push_back(DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
796 case 'K': // Signed 16-bit constant
797 if (auto *C = dyn_cast<ConstantSDNode>(Op))
798 if (isInt<16>(C->getSExtValue()))
799 Ops.push_back(DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
803 case 'L': // Signed 20-bit displacement (on all targets we support)
804 if (auto *C = dyn_cast<ConstantSDNode>(Op))
805 if (isInt<20>(C->getSExtValue()))
806 Ops.push_back(DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
810 case 'M': // 0x7fffffff
811 if (auto *C = dyn_cast<ConstantSDNode>(Op))
812 if (C->getZExtValue() == 0x7fffffff)
813 Ops.push_back(DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
818 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
821 //===----------------------------------------------------------------------===//
822 // Calling conventions
823 //===----------------------------------------------------------------------===//
825 #include "SystemZGenCallingConv.inc"
827 bool SystemZTargetLowering::allowTruncateForTailCall(Type *FromType,
828 Type *ToType) const {
829 return isTruncateFree(FromType, ToType);
832 bool SystemZTargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {
833 return CI->isTailCall();
836 // We do not yet support 128-bit single-element vector types. If the user
837 // attempts to use such types as function argument or return type, prefer
838 // to error out instead of emitting code violating the ABI.
839 static void VerifyVectorType(MVT VT, EVT ArgVT) {
840 if (ArgVT.isVector() && !VT.isVector())
841 report_fatal_error("Unsupported vector argument or return type");
844 static void VerifyVectorTypes(const SmallVectorImpl<ISD::InputArg> &Ins) {
845 for (unsigned i = 0; i < Ins.size(); ++i)
846 VerifyVectorType(Ins[i].VT, Ins[i].ArgVT);
849 static void VerifyVectorTypes(const SmallVectorImpl<ISD::OutputArg> &Outs) {
850 for (unsigned i = 0; i < Outs.size(); ++i)
851 VerifyVectorType(Outs[i].VT, Outs[i].ArgVT);
854 // Value is a value that has been passed to us in the location described by VA
855 // (and so has type VA.getLocVT()). Convert Value to VA.getValVT(), chaining
856 // any loads onto Chain.
857 static SDValue convertLocVTToValVT(SelectionDAG &DAG, const SDLoc &DL,
858 CCValAssign &VA, SDValue Chain,
860 // If the argument has been promoted from a smaller type, insert an
861 // assertion to capture this.
862 if (VA.getLocInfo() == CCValAssign::SExt)
863 Value = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Value,
864 DAG.getValueType(VA.getValVT()));
865 else if (VA.getLocInfo() == CCValAssign::ZExt)
866 Value = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Value,
867 DAG.getValueType(VA.getValVT()));
870 Value = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Value);
871 else if (VA.getLocInfo() == CCValAssign::BCvt) {
872 // If this is a short vector argument loaded from the stack,
873 // extend from i64 to full vector size and then bitcast.
874 assert(VA.getLocVT() == MVT::i64);
875 assert(VA.getValVT().isVector());
876 Value = DAG.getBuildVector(MVT::v2i64, DL, {Value, DAG.getUNDEF(MVT::i64)});
877 Value = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Value);
879 assert(VA.getLocInfo() == CCValAssign::Full && "Unsupported getLocInfo");
883 // Value is a value of type VA.getValVT() that we need to copy into
884 // the location described by VA. Return a copy of Value converted to
885 // VA.getValVT(). The caller is responsible for handling indirect values.
886 static SDValue convertValVTToLocVT(SelectionDAG &DAG, const SDLoc &DL,
887 CCValAssign &VA, SDValue Value) {
888 switch (VA.getLocInfo()) {
889 case CCValAssign::SExt:
890 return DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Value);
891 case CCValAssign::ZExt:
892 return DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Value);
893 case CCValAssign::AExt:
894 return DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Value);
895 case CCValAssign::BCvt:
896 // If this is a short vector argument to be stored to the stack,
897 // bitcast to v2i64 and then extract first element.
898 assert(VA.getLocVT() == MVT::i64);
899 assert(VA.getValVT().isVector());
900 Value = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Value);
901 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VA.getLocVT(), Value,
902 DAG.getConstant(0, DL, MVT::i32));
903 case CCValAssign::Full:
906 llvm_unreachable("Unhandled getLocInfo()");
910 SDValue SystemZTargetLowering::LowerFormalArguments(
911 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
912 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
913 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
914 MachineFunction &MF = DAG.getMachineFunction();
915 MachineFrameInfo &MFI = MF.getFrameInfo();
916 MachineRegisterInfo &MRI = MF.getRegInfo();
917 SystemZMachineFunctionInfo *FuncInfo =
918 MF.getInfo<SystemZMachineFunctionInfo>();
920 static_cast<const SystemZFrameLowering *>(Subtarget.getFrameLowering());
921 EVT PtrVT = getPointerTy(DAG.getDataLayout());
923 // Detect unsupported vector argument types.
924 if (Subtarget.hasVector())
925 VerifyVectorTypes(Ins);
927 // Assign locations to all of the incoming arguments.
928 SmallVector<CCValAssign, 16> ArgLocs;
929 SystemZCCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
930 CCInfo.AnalyzeFormalArguments(Ins, CC_SystemZ);
932 unsigned NumFixedGPRs = 0;
933 unsigned NumFixedFPRs = 0;
934 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
936 CCValAssign &VA = ArgLocs[I];
937 EVT LocVT = VA.getLocVT();
939 // Arguments passed in registers
940 const TargetRegisterClass *RC;
941 switch (LocVT.getSimpleVT().SimpleTy) {
943 // Integers smaller than i64 should be promoted to i64.
944 llvm_unreachable("Unexpected argument type");
947 RC = &SystemZ::GR32BitRegClass;
951 RC = &SystemZ::GR64BitRegClass;
955 RC = &SystemZ::FP32BitRegClass;
959 RC = &SystemZ::FP64BitRegClass;
967 RC = &SystemZ::VR128BitRegClass;
971 unsigned VReg = MRI.createVirtualRegister(RC);
972 MRI.addLiveIn(VA.getLocReg(), VReg);
973 ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, LocVT);
975 assert(VA.isMemLoc() && "Argument not register or memory");
977 // Create the frame index object for this incoming parameter.
978 int FI = MFI.CreateFixedObject(LocVT.getSizeInBits() / 8,
979 VA.getLocMemOffset(), true);
981 // Create the SelectionDAG nodes corresponding to a load
982 // from this parameter. Unpromoted ints and floats are
983 // passed as right-justified 8-byte values.
984 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
985 if (VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::f32)
986 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN,
987 DAG.getIntPtrConstant(4, DL));
988 ArgValue = DAG.getLoad(LocVT, DL, Chain, FIN,
989 MachinePointerInfo::getFixedStack(MF, FI));
992 // Convert the value of the argument register into the value that's
994 if (VA.getLocInfo() == CCValAssign::Indirect) {
995 InVals.push_back(DAG.getLoad(VA.getValVT(), DL, Chain, ArgValue,
996 MachinePointerInfo()));
997 // If the original argument was split (e.g. i128), we need
998 // to load all parts of it here (using the same address).
999 unsigned ArgIndex = Ins[I].OrigArgIndex;
1000 assert (Ins[I].PartOffset == 0);
1001 while (I + 1 != E && Ins[I + 1].OrigArgIndex == ArgIndex) {
1002 CCValAssign &PartVA = ArgLocs[I + 1];
1003 unsigned PartOffset = Ins[I + 1].PartOffset;
1004 SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, ArgValue,
1005 DAG.getIntPtrConstant(PartOffset, DL));
1006 InVals.push_back(DAG.getLoad(PartVA.getValVT(), DL, Chain, Address,
1007 MachinePointerInfo()));
1011 InVals.push_back(convertLocVTToValVT(DAG, DL, VA, Chain, ArgValue));
1015 // Save the number of non-varargs registers for later use by va_start, etc.
1016 FuncInfo->setVarArgsFirstGPR(NumFixedGPRs);
1017 FuncInfo->setVarArgsFirstFPR(NumFixedFPRs);
1019 // Likewise the address (in the form of a frame index) of where the
1020 // first stack vararg would be. The 1-byte size here is arbitrary.
1021 int64_t StackSize = CCInfo.getNextStackOffset();
1022 FuncInfo->setVarArgsFrameIndex(MFI.CreateFixedObject(1, StackSize, true));
1024 // ...and a similar frame index for the caller-allocated save area
1025 // that will be used to store the incoming registers.
1026 int64_t RegSaveOffset = TFL->getOffsetOfLocalArea();
1027 unsigned RegSaveIndex = MFI.CreateFixedObject(1, RegSaveOffset, true);
1028 FuncInfo->setRegSaveFrameIndex(RegSaveIndex);
1030 // Store the FPR varargs in the reserved frame slots. (We store the
1031 // GPRs as part of the prologue.)
1032 if (NumFixedFPRs < SystemZ::NumArgFPRs) {
1033 SDValue MemOps[SystemZ::NumArgFPRs];
1034 for (unsigned I = NumFixedFPRs; I < SystemZ::NumArgFPRs; ++I) {
1035 unsigned Offset = TFL->getRegSpillOffset(SystemZ::ArgFPRs[I]);
1036 int FI = MFI.CreateFixedObject(8, RegSaveOffset + Offset, true);
1037 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
1038 unsigned VReg = MF.addLiveIn(SystemZ::ArgFPRs[I],
1039 &SystemZ::FP64BitRegClass);
1040 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f64);
1041 MemOps[I] = DAG.getStore(ArgValue.getValue(1), DL, ArgValue, FIN,
1042 MachinePointerInfo::getFixedStack(MF, FI));
1044 // Join the stores, which are independent of one another.
1045 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
1046 makeArrayRef(&MemOps[NumFixedFPRs],
1047 SystemZ::NumArgFPRs-NumFixedFPRs));
1054 static bool canUseSiblingCall(const CCState &ArgCCInfo,
1055 SmallVectorImpl<CCValAssign> &ArgLocs,
1056 SmallVectorImpl<ISD::OutputArg> &Outs) {
1057 // Punt if there are any indirect or stack arguments, or if the call
1058 // needs the callee-saved argument register R6, or if the call uses
1059 // the callee-saved register arguments SwiftSelf and SwiftError.
1060 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
1061 CCValAssign &VA = ArgLocs[I];
1062 if (VA.getLocInfo() == CCValAssign::Indirect)
1066 unsigned Reg = VA.getLocReg();
1067 if (Reg == SystemZ::R6H || Reg == SystemZ::R6L || Reg == SystemZ::R6D)
1069 if (Outs[I].Flags.isSwiftSelf() || Outs[I].Flags.isSwiftError())
1076 SystemZTargetLowering::LowerCall(CallLoweringInfo &CLI,
1077 SmallVectorImpl<SDValue> &InVals) const {
1078 SelectionDAG &DAG = CLI.DAG;
1080 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
1081 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
1082 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
1083 SDValue Chain = CLI.Chain;
1084 SDValue Callee = CLI.Callee;
1085 bool &IsTailCall = CLI.IsTailCall;
1086 CallingConv::ID CallConv = CLI.CallConv;
1087 bool IsVarArg = CLI.IsVarArg;
1088 MachineFunction &MF = DAG.getMachineFunction();
1089 EVT PtrVT = getPointerTy(MF.getDataLayout());
1091 // Detect unsupported vector argument and return types.
1092 if (Subtarget.hasVector()) {
1093 VerifyVectorTypes(Outs);
1094 VerifyVectorTypes(Ins);
1097 // Analyze the operands of the call, assigning locations to each operand.
1098 SmallVector<CCValAssign, 16> ArgLocs;
1099 SystemZCCState ArgCCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
1100 ArgCCInfo.AnalyzeCallOperands(Outs, CC_SystemZ);
1102 // We don't support GuaranteedTailCallOpt, only automatically-detected
1104 if (IsTailCall && !canUseSiblingCall(ArgCCInfo, ArgLocs, Outs))
1107 // Get a count of how many bytes are to be pushed on the stack.
1108 unsigned NumBytes = ArgCCInfo.getNextStackOffset();
1110 // Mark the start of the call.
1112 Chain = DAG.getCALLSEQ_START(Chain,
1113 DAG.getConstant(NumBytes, DL, PtrVT, true),
1116 // Copy argument values to their designated locations.
1117 SmallVector<std::pair<unsigned, SDValue>, 9> RegsToPass;
1118 SmallVector<SDValue, 8> MemOpChains;
1120 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
1121 CCValAssign &VA = ArgLocs[I];
1122 SDValue ArgValue = OutVals[I];
1124 if (VA.getLocInfo() == CCValAssign::Indirect) {
1125 // Store the argument in a stack slot and pass its address.
1126 SDValue SpillSlot = DAG.CreateStackTemporary(Outs[I].ArgVT);
1127 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
1128 MemOpChains.push_back(
1129 DAG.getStore(Chain, DL, ArgValue, SpillSlot,
1130 MachinePointerInfo::getFixedStack(MF, FI)));
1131 // If the original argument was split (e.g. i128), we need
1132 // to store all parts of it here (and pass just one address).
1133 unsigned ArgIndex = Outs[I].OrigArgIndex;
1134 assert (Outs[I].PartOffset == 0);
1135 while (I + 1 != E && Outs[I + 1].OrigArgIndex == ArgIndex) {
1136 SDValue PartValue = OutVals[I + 1];
1137 unsigned PartOffset = Outs[I + 1].PartOffset;
1138 SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, SpillSlot,
1139 DAG.getIntPtrConstant(PartOffset, DL));
1140 MemOpChains.push_back(
1141 DAG.getStore(Chain, DL, PartValue, Address,
1142 MachinePointerInfo::getFixedStack(MF, FI)));
1145 ArgValue = SpillSlot;
1147 ArgValue = convertValVTToLocVT(DAG, DL, VA, ArgValue);
1150 // Queue up the argument copies and emit them at the end.
1151 RegsToPass.push_back(std::make_pair(VA.getLocReg(), ArgValue));
1153 assert(VA.isMemLoc() && "Argument not register or memory");
1155 // Work out the address of the stack slot. Unpromoted ints and
1156 // floats are passed as right-justified 8-byte values.
1157 if (!StackPtr.getNode())
1158 StackPtr = DAG.getCopyFromReg(Chain, DL, SystemZ::R15D, PtrVT);
1159 unsigned Offset = SystemZMC::CallFrameSize + VA.getLocMemOffset();
1160 if (VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::f32)
1162 SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr,
1163 DAG.getIntPtrConstant(Offset, DL));
1166 MemOpChains.push_back(
1167 DAG.getStore(Chain, DL, ArgValue, Address, MachinePointerInfo()));
1171 // Join the stores, which are independent of one another.
1172 if (!MemOpChains.empty())
1173 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
1175 // Accept direct calls by converting symbolic call addresses to the
1176 // associated Target* opcodes. Force %r1 to be used for indirect
1179 if (auto *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1180 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, PtrVT);
1181 Callee = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Callee);
1182 } else if (auto *E = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1183 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), PtrVT);
1184 Callee = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Callee);
1185 } else if (IsTailCall) {
1186 Chain = DAG.getCopyToReg(Chain, DL, SystemZ::R1D, Callee, Glue);
1187 Glue = Chain.getValue(1);
1188 Callee = DAG.getRegister(SystemZ::R1D, Callee.getValueType());
1191 // Build a sequence of copy-to-reg nodes, chained and glued together.
1192 for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I) {
1193 Chain = DAG.getCopyToReg(Chain, DL, RegsToPass[I].first,
1194 RegsToPass[I].second, Glue);
1195 Glue = Chain.getValue(1);
1198 // The first call operand is the chain and the second is the target address.
1199 SmallVector<SDValue, 8> Ops;
1200 Ops.push_back(Chain);
1201 Ops.push_back(Callee);
1203 // Add argument registers to the end of the list so that they are
1204 // known live into the call.
1205 for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I)
1206 Ops.push_back(DAG.getRegister(RegsToPass[I].first,
1207 RegsToPass[I].second.getValueType()));
1209 // Add a register mask operand representing the call-preserved registers.
1210 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
1211 const uint32_t *Mask = TRI->getCallPreservedMask(MF, CallConv);
1212 assert(Mask && "Missing call preserved mask for calling convention");
1213 Ops.push_back(DAG.getRegisterMask(Mask));
1215 // Glue the call to the argument copies, if any.
1217 Ops.push_back(Glue);
1220 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1222 return DAG.getNode(SystemZISD::SIBCALL, DL, NodeTys, Ops);
1223 Chain = DAG.getNode(SystemZISD::CALL, DL, NodeTys, Ops);
1224 Glue = Chain.getValue(1);
1226 // Mark the end of the call, which is glued to the call itself.
1227 Chain = DAG.getCALLSEQ_END(Chain,
1228 DAG.getConstant(NumBytes, DL, PtrVT, true),
1229 DAG.getConstant(0, DL, PtrVT, true),
1231 Glue = Chain.getValue(1);
1233 // Assign locations to each value returned by this call.
1234 SmallVector<CCValAssign, 16> RetLocs;
1235 CCState RetCCInfo(CallConv, IsVarArg, MF, RetLocs, *DAG.getContext());
1236 RetCCInfo.AnalyzeCallResult(Ins, RetCC_SystemZ);
1238 // Copy all of the result registers out of their specified physreg.
1239 for (unsigned I = 0, E = RetLocs.size(); I != E; ++I) {
1240 CCValAssign &VA = RetLocs[I];
1242 // Copy the value out, gluing the copy to the end of the call sequence.
1243 SDValue RetValue = DAG.getCopyFromReg(Chain, DL, VA.getLocReg(),
1244 VA.getLocVT(), Glue);
1245 Chain = RetValue.getValue(1);
1246 Glue = RetValue.getValue(2);
1248 // Convert the value of the return register into the value that's
1250 InVals.push_back(convertLocVTToValVT(DAG, DL, VA, Chain, RetValue));
1256 bool SystemZTargetLowering::
1257 CanLowerReturn(CallingConv::ID CallConv,
1258 MachineFunction &MF, bool isVarArg,
1259 const SmallVectorImpl<ISD::OutputArg> &Outs,
1260 LLVMContext &Context) const {
1261 // Detect unsupported vector return types.
1262 if (Subtarget.hasVector())
1263 VerifyVectorTypes(Outs);
1265 // Special case that we cannot easily detect in RetCC_SystemZ since
1266 // i128 is not a legal type.
1267 for (auto &Out : Outs)
1268 if (Out.ArgVT == MVT::i128)
1271 SmallVector<CCValAssign, 16> RetLocs;
1272 CCState RetCCInfo(CallConv, isVarArg, MF, RetLocs, Context);
1273 return RetCCInfo.CheckReturn(Outs, RetCC_SystemZ);
1277 SystemZTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
1279 const SmallVectorImpl<ISD::OutputArg> &Outs,
1280 const SmallVectorImpl<SDValue> &OutVals,
1281 const SDLoc &DL, SelectionDAG &DAG) const {
1282 MachineFunction &MF = DAG.getMachineFunction();
1284 // Detect unsupported vector return types.
1285 if (Subtarget.hasVector())
1286 VerifyVectorTypes(Outs);
1288 // Assign locations to each returned value.
1289 SmallVector<CCValAssign, 16> RetLocs;
1290 CCState RetCCInfo(CallConv, IsVarArg, MF, RetLocs, *DAG.getContext());
1291 RetCCInfo.AnalyzeReturn(Outs, RetCC_SystemZ);
1293 // Quick exit for void returns
1294 if (RetLocs.empty())
1295 return DAG.getNode(SystemZISD::RET_FLAG, DL, MVT::Other, Chain);
1297 // Copy the result values into the output registers.
1299 SmallVector<SDValue, 4> RetOps;
1300 RetOps.push_back(Chain);
1301 for (unsigned I = 0, E = RetLocs.size(); I != E; ++I) {
1302 CCValAssign &VA = RetLocs[I];
1303 SDValue RetValue = OutVals[I];
1305 // Make the return register live on exit.
1306 assert(VA.isRegLoc() && "Can only return in registers!");
1308 // Promote the value as required.
1309 RetValue = convertValVTToLocVT(DAG, DL, VA, RetValue);
1311 // Chain and glue the copies together.
1312 unsigned Reg = VA.getLocReg();
1313 Chain = DAG.getCopyToReg(Chain, DL, Reg, RetValue, Glue);
1314 Glue = Chain.getValue(1);
1315 RetOps.push_back(DAG.getRegister(Reg, VA.getLocVT()));
1318 // Update chain and glue.
1321 RetOps.push_back(Glue);
1323 return DAG.getNode(SystemZISD::RET_FLAG, DL, MVT::Other, RetOps);
1326 SDValue SystemZTargetLowering::prepareVolatileOrAtomicLoad(
1327 SDValue Chain, const SDLoc &DL, SelectionDAG &DAG) const {
1328 return DAG.getNode(SystemZISD::SERIALIZE, DL, MVT::Other, Chain);
1331 // Return true if Op is an intrinsic node with chain that returns the CC value
1332 // as its only (other) argument. Provide the associated SystemZISD opcode and
1333 // the mask of valid CC values if so.
1334 static bool isIntrinsicWithCCAndChain(SDValue Op, unsigned &Opcode,
1335 unsigned &CCValid) {
1336 unsigned Id = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
1338 case Intrinsic::s390_tbegin:
1339 Opcode = SystemZISD::TBEGIN;
1340 CCValid = SystemZ::CCMASK_TBEGIN;
1343 case Intrinsic::s390_tbegin_nofloat:
1344 Opcode = SystemZISD::TBEGIN_NOFLOAT;
1345 CCValid = SystemZ::CCMASK_TBEGIN;
1348 case Intrinsic::s390_tend:
1349 Opcode = SystemZISD::TEND;
1350 CCValid = SystemZ::CCMASK_TEND;
1358 // Return true if Op is an intrinsic node without chain that returns the
1359 // CC value as its final argument. Provide the associated SystemZISD
1360 // opcode and the mask of valid CC values if so.
1361 static bool isIntrinsicWithCC(SDValue Op, unsigned &Opcode, unsigned &CCValid) {
1362 unsigned Id = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1364 case Intrinsic::s390_vpkshs:
1365 case Intrinsic::s390_vpksfs:
1366 case Intrinsic::s390_vpksgs:
1367 Opcode = SystemZISD::PACKS_CC;
1368 CCValid = SystemZ::CCMASK_VCMP;
1371 case Intrinsic::s390_vpklshs:
1372 case Intrinsic::s390_vpklsfs:
1373 case Intrinsic::s390_vpklsgs:
1374 Opcode = SystemZISD::PACKLS_CC;
1375 CCValid = SystemZ::CCMASK_VCMP;
1378 case Intrinsic::s390_vceqbs:
1379 case Intrinsic::s390_vceqhs:
1380 case Intrinsic::s390_vceqfs:
1381 case Intrinsic::s390_vceqgs:
1382 Opcode = SystemZISD::VICMPES;
1383 CCValid = SystemZ::CCMASK_VCMP;
1386 case Intrinsic::s390_vchbs:
1387 case Intrinsic::s390_vchhs:
1388 case Intrinsic::s390_vchfs:
1389 case Intrinsic::s390_vchgs:
1390 Opcode = SystemZISD::VICMPHS;
1391 CCValid = SystemZ::CCMASK_VCMP;
1394 case Intrinsic::s390_vchlbs:
1395 case Intrinsic::s390_vchlhs:
1396 case Intrinsic::s390_vchlfs:
1397 case Intrinsic::s390_vchlgs:
1398 Opcode = SystemZISD::VICMPHLS;
1399 CCValid = SystemZ::CCMASK_VCMP;
1402 case Intrinsic::s390_vtm:
1403 Opcode = SystemZISD::VTM;
1404 CCValid = SystemZ::CCMASK_VCMP;
1407 case Intrinsic::s390_vfaebs:
1408 case Intrinsic::s390_vfaehs:
1409 case Intrinsic::s390_vfaefs:
1410 Opcode = SystemZISD::VFAE_CC;
1411 CCValid = SystemZ::CCMASK_ANY;
1414 case Intrinsic::s390_vfaezbs:
1415 case Intrinsic::s390_vfaezhs:
1416 case Intrinsic::s390_vfaezfs:
1417 Opcode = SystemZISD::VFAEZ_CC;
1418 CCValid = SystemZ::CCMASK_ANY;
1421 case Intrinsic::s390_vfeebs:
1422 case Intrinsic::s390_vfeehs:
1423 case Intrinsic::s390_vfeefs:
1424 Opcode = SystemZISD::VFEE_CC;
1425 CCValid = SystemZ::CCMASK_ANY;
1428 case Intrinsic::s390_vfeezbs:
1429 case Intrinsic::s390_vfeezhs:
1430 case Intrinsic::s390_vfeezfs:
1431 Opcode = SystemZISD::VFEEZ_CC;
1432 CCValid = SystemZ::CCMASK_ANY;
1435 case Intrinsic::s390_vfenebs:
1436 case Intrinsic::s390_vfenehs:
1437 case Intrinsic::s390_vfenefs:
1438 Opcode = SystemZISD::VFENE_CC;
1439 CCValid = SystemZ::CCMASK_ANY;
1442 case Intrinsic::s390_vfenezbs:
1443 case Intrinsic::s390_vfenezhs:
1444 case Intrinsic::s390_vfenezfs:
1445 Opcode = SystemZISD::VFENEZ_CC;
1446 CCValid = SystemZ::CCMASK_ANY;
1449 case Intrinsic::s390_vistrbs:
1450 case Intrinsic::s390_vistrhs:
1451 case Intrinsic::s390_vistrfs:
1452 Opcode = SystemZISD::VISTR_CC;
1453 CCValid = SystemZ::CCMASK_0 | SystemZ::CCMASK_3;
1456 case Intrinsic::s390_vstrcbs:
1457 case Intrinsic::s390_vstrchs:
1458 case Intrinsic::s390_vstrcfs:
1459 Opcode = SystemZISD::VSTRC_CC;
1460 CCValid = SystemZ::CCMASK_ANY;
1463 case Intrinsic::s390_vstrczbs:
1464 case Intrinsic::s390_vstrczhs:
1465 case Intrinsic::s390_vstrczfs:
1466 Opcode = SystemZISD::VSTRCZ_CC;
1467 CCValid = SystemZ::CCMASK_ANY;
1470 case Intrinsic::s390_vfcedbs:
1471 Opcode = SystemZISD::VFCMPES;
1472 CCValid = SystemZ::CCMASK_VCMP;
1475 case Intrinsic::s390_vfchdbs:
1476 Opcode = SystemZISD::VFCMPHS;
1477 CCValid = SystemZ::CCMASK_VCMP;
1480 case Intrinsic::s390_vfchedbs:
1481 Opcode = SystemZISD::VFCMPHES;
1482 CCValid = SystemZ::CCMASK_VCMP;
1485 case Intrinsic::s390_vftcidb:
1486 Opcode = SystemZISD::VFTCI;
1487 CCValid = SystemZ::CCMASK_VCMP;
1490 case Intrinsic::s390_tdc:
1491 Opcode = SystemZISD::TDC;
1492 CCValid = SystemZ::CCMASK_TDC;
1500 // Emit an intrinsic with chain with a glued value instead of its CC result.
1501 static SDValue emitIntrinsicWithChainAndGlue(SelectionDAG &DAG, SDValue Op,
1503 // Copy all operands except the intrinsic ID.
1504 unsigned NumOps = Op.getNumOperands();
1505 SmallVector<SDValue, 6> Ops;
1506 Ops.reserve(NumOps - 1);
1507 Ops.push_back(Op.getOperand(0));
1508 for (unsigned I = 2; I < NumOps; ++I)
1509 Ops.push_back(Op.getOperand(I));
1511 assert(Op->getNumValues() == 2 && "Expected only CC result and chain");
1512 SDVTList RawVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1513 SDValue Intr = DAG.getNode(Opcode, SDLoc(Op), RawVTs, Ops);
1514 SDValue OldChain = SDValue(Op.getNode(), 1);
1515 SDValue NewChain = SDValue(Intr.getNode(), 0);
1516 DAG.ReplaceAllUsesOfValueWith(OldChain, NewChain);
1520 // Emit an intrinsic with a glued value instead of its CC result.
1521 static SDValue emitIntrinsicWithGlue(SelectionDAG &DAG, SDValue Op,
1523 // Copy all operands except the intrinsic ID.
1524 unsigned NumOps = Op.getNumOperands();
1525 SmallVector<SDValue, 6> Ops;
1526 Ops.reserve(NumOps - 1);
1527 for (unsigned I = 1; I < NumOps; ++I)
1528 Ops.push_back(Op.getOperand(I));
1530 if (Op->getNumValues() == 1)
1531 return DAG.getNode(Opcode, SDLoc(Op), MVT::Glue, Ops);
1532 assert(Op->getNumValues() == 2 && "Expected exactly one non-CC result");
1533 SDVTList RawVTs = DAG.getVTList(Op->getValueType(0), MVT::Glue);
1534 return DAG.getNode(Opcode, SDLoc(Op), RawVTs, Ops);
1537 // CC is a comparison that will be implemented using an integer or
1538 // floating-point comparison. Return the condition code mask for
1539 // a branch on true. In the integer case, CCMASK_CMP_UO is set for
1540 // unsigned comparisons and clear for signed ones. In the floating-point
1541 // case, CCMASK_CMP_UO has its normal mask meaning (unordered).
1542 static unsigned CCMaskForCondCode(ISD::CondCode CC) {
1544 case ISD::SET##X: return SystemZ::CCMASK_CMP_##X; \
1545 case ISD::SETO##X: return SystemZ::CCMASK_CMP_##X; \
1546 case ISD::SETU##X: return SystemZ::CCMASK_CMP_UO | SystemZ::CCMASK_CMP_##X
1550 llvm_unreachable("Invalid integer condition!");
1559 case ISD::SETO: return SystemZ::CCMASK_CMP_O;
1560 case ISD::SETUO: return SystemZ::CCMASK_CMP_UO;
1565 // Return a sequence for getting a 1 from an IPM result when CC has a
1566 // value in CCMask and a 0 when CC has a value in CCValid & ~CCMask.
1567 // The handling of CC values outside CCValid doesn't matter.
1568 static IPMConversion getIPMConversion(unsigned CCValid, unsigned CCMask) {
1569 // Deal with cases where the result can be taken directly from a bit
1570 // of the IPM result.
1571 if (CCMask == (CCValid & (SystemZ::CCMASK_1 | SystemZ::CCMASK_3)))
1572 return IPMConversion(0, 0, SystemZ::IPM_CC);
1573 if (CCMask == (CCValid & (SystemZ::CCMASK_2 | SystemZ::CCMASK_3)))
1574 return IPMConversion(0, 0, SystemZ::IPM_CC + 1);
1576 // Deal with cases where we can add a value to force the sign bit
1577 // to contain the right value. Putting the bit in 31 means we can
1578 // use SRL rather than RISBG(L), and also makes it easier to get a
1579 // 0/-1 value, so it has priority over the other tests below.
1581 // These sequences rely on the fact that the upper two bits of the
1582 // IPM result are zero.
1583 uint64_t TopBit = uint64_t(1) << 31;
1584 if (CCMask == (CCValid & SystemZ::CCMASK_0))
1585 return IPMConversion(0, -(1 << SystemZ::IPM_CC), 31);
1586 if (CCMask == (CCValid & (SystemZ::CCMASK_0 | SystemZ::CCMASK_1)))
1587 return IPMConversion(0, -(2 << SystemZ::IPM_CC), 31);
1588 if (CCMask == (CCValid & (SystemZ::CCMASK_0
1590 | SystemZ::CCMASK_2)))
1591 return IPMConversion(0, -(3 << SystemZ::IPM_CC), 31);
1592 if (CCMask == (CCValid & SystemZ::CCMASK_3))
1593 return IPMConversion(0, TopBit - (3 << SystemZ::IPM_CC), 31);
1594 if (CCMask == (CCValid & (SystemZ::CCMASK_1
1596 | SystemZ::CCMASK_3)))
1597 return IPMConversion(0, TopBit - (1 << SystemZ::IPM_CC), 31);
1599 // Next try inverting the value and testing a bit. 0/1 could be
1600 // handled this way too, but we dealt with that case above.
1601 if (CCMask == (CCValid & (SystemZ::CCMASK_0 | SystemZ::CCMASK_2)))
1602 return IPMConversion(-1, 0, SystemZ::IPM_CC);
1604 // Handle cases where adding a value forces a non-sign bit to contain
1606 if (CCMask == (CCValid & (SystemZ::CCMASK_1 | SystemZ::CCMASK_2)))
1607 return IPMConversion(0, 1 << SystemZ::IPM_CC, SystemZ::IPM_CC + 1);
1608 if (CCMask == (CCValid & (SystemZ::CCMASK_0 | SystemZ::CCMASK_3)))
1609 return IPMConversion(0, -(1 << SystemZ::IPM_CC), SystemZ::IPM_CC + 1);
1611 // The remaining cases are 1, 2, 0/1/3 and 0/2/3. All these are
1612 // can be done by inverting the low CC bit and applying one of the
1613 // sign-based extractions above.
1614 if (CCMask == (CCValid & SystemZ::CCMASK_1))
1615 return IPMConversion(1 << SystemZ::IPM_CC, -(1 << SystemZ::IPM_CC), 31);
1616 if (CCMask == (CCValid & SystemZ::CCMASK_2))
1617 return IPMConversion(1 << SystemZ::IPM_CC,
1618 TopBit - (3 << SystemZ::IPM_CC), 31);
1619 if (CCMask == (CCValid & (SystemZ::CCMASK_0
1621 | SystemZ::CCMASK_3)))
1622 return IPMConversion(1 << SystemZ::IPM_CC, -(3 << SystemZ::IPM_CC), 31);
1623 if (CCMask == (CCValid & (SystemZ::CCMASK_0
1625 | SystemZ::CCMASK_3)))
1626 return IPMConversion(1 << SystemZ::IPM_CC,
1627 TopBit - (1 << SystemZ::IPM_CC), 31);
1629 llvm_unreachable("Unexpected CC combination");
1632 // If C can be converted to a comparison against zero, adjust the operands
1634 static void adjustZeroCmp(SelectionDAG &DAG, const SDLoc &DL, Comparison &C) {
1635 if (C.ICmpType == SystemZICMP::UnsignedOnly)
1638 auto *ConstOp1 = dyn_cast<ConstantSDNode>(C.Op1.getNode());
1642 int64_t Value = ConstOp1->getSExtValue();
1643 if ((Value == -1 && C.CCMask == SystemZ::CCMASK_CMP_GT) ||
1644 (Value == -1 && C.CCMask == SystemZ::CCMASK_CMP_LE) ||
1645 (Value == 1 && C.CCMask == SystemZ::CCMASK_CMP_LT) ||
1646 (Value == 1 && C.CCMask == SystemZ::CCMASK_CMP_GE)) {
1647 C.CCMask ^= SystemZ::CCMASK_CMP_EQ;
1648 C.Op1 = DAG.getConstant(0, DL, C.Op1.getValueType());
1652 // If a comparison described by C is suitable for CLI(Y), CHHSI or CLHHSI,
1653 // adjust the operands as necessary.
1654 static void adjustSubwordCmp(SelectionDAG &DAG, const SDLoc &DL,
1656 // For us to make any changes, it must a comparison between a single-use
1657 // load and a constant.
1658 if (!C.Op0.hasOneUse() ||
1659 C.Op0.getOpcode() != ISD::LOAD ||
1660 C.Op1.getOpcode() != ISD::Constant)
1663 // We must have an 8- or 16-bit load.
1664 auto *Load = cast<LoadSDNode>(C.Op0);
1665 unsigned NumBits = Load->getMemoryVT().getStoreSizeInBits();
1666 if (NumBits != 8 && NumBits != 16)
1669 // The load must be an extending one and the constant must be within the
1670 // range of the unextended value.
1671 auto *ConstOp1 = cast<ConstantSDNode>(C.Op1);
1672 uint64_t Value = ConstOp1->getZExtValue();
1673 uint64_t Mask = (1 << NumBits) - 1;
1674 if (Load->getExtensionType() == ISD::SEXTLOAD) {
1675 // Make sure that ConstOp1 is in range of C.Op0.
1676 int64_t SignedValue = ConstOp1->getSExtValue();
1677 if (uint64_t(SignedValue) + (uint64_t(1) << (NumBits - 1)) > Mask)
1679 if (C.ICmpType != SystemZICMP::SignedOnly) {
1680 // Unsigned comparison between two sign-extended values is equivalent
1681 // to unsigned comparison between two zero-extended values.
1683 } else if (NumBits == 8) {
1684 // Try to treat the comparison as unsigned, so that we can use CLI.
1685 // Adjust CCMask and Value as necessary.
1686 if (Value == 0 && C.CCMask == SystemZ::CCMASK_CMP_LT)
1687 // Test whether the high bit of the byte is set.
1688 Value = 127, C.CCMask = SystemZ::CCMASK_CMP_GT;
1689 else if (Value == 0 && C.CCMask == SystemZ::CCMASK_CMP_GE)
1690 // Test whether the high bit of the byte is clear.
1691 Value = 128, C.CCMask = SystemZ::CCMASK_CMP_LT;
1693 // No instruction exists for this combination.
1695 C.ICmpType = SystemZICMP::UnsignedOnly;
1697 } else if (Load->getExtensionType() == ISD::ZEXTLOAD) {
1700 // If the constant is in range, we can use any comparison.
1701 C.ICmpType = SystemZICMP::Any;
1705 // Make sure that the first operand is an i32 of the right extension type.
1706 ISD::LoadExtType ExtType = (C.ICmpType == SystemZICMP::SignedOnly ?
1709 if (C.Op0.getValueType() != MVT::i32 ||
1710 Load->getExtensionType() != ExtType)
1711 C.Op0 = DAG.getExtLoad(ExtType, SDLoc(Load), MVT::i32, Load->getChain(),
1712 Load->getBasePtr(), Load->getPointerInfo(),
1713 Load->getMemoryVT(), Load->getAlignment(),
1714 Load->getMemOperand()->getFlags());
1716 // Make sure that the second operand is an i32 with the right value.
1717 if (C.Op1.getValueType() != MVT::i32 ||
1718 Value != ConstOp1->getZExtValue())
1719 C.Op1 = DAG.getConstant(Value, DL, MVT::i32);
1722 // Return true if Op is either an unextended load, or a load suitable
1723 // for integer register-memory comparisons of type ICmpType.
1724 static bool isNaturalMemoryOperand(SDValue Op, unsigned ICmpType) {
1725 auto *Load = dyn_cast<LoadSDNode>(Op.getNode());
1727 // There are no instructions to compare a register with a memory byte.
1728 if (Load->getMemoryVT() == MVT::i8)
1730 // Otherwise decide on extension type.
1731 switch (Load->getExtensionType()) {
1732 case ISD::NON_EXTLOAD:
1735 return ICmpType != SystemZICMP::UnsignedOnly;
1737 return ICmpType != SystemZICMP::SignedOnly;
1745 // Return true if it is better to swap the operands of C.
1746 static bool shouldSwapCmpOperands(const Comparison &C) {
1747 // Leave f128 comparisons alone, since they have no memory forms.
1748 if (C.Op0.getValueType() == MVT::f128)
1751 // Always keep a floating-point constant second, since comparisons with
1752 // zero can use LOAD TEST and comparisons with other constants make a
1753 // natural memory operand.
1754 if (isa<ConstantFPSDNode>(C.Op1))
1757 // Never swap comparisons with zero since there are many ways to optimize
1759 auto *ConstOp1 = dyn_cast<ConstantSDNode>(C.Op1);
1760 if (ConstOp1 && ConstOp1->getZExtValue() == 0)
1763 // Also keep natural memory operands second if the loaded value is
1764 // only used here. Several comparisons have memory forms.
1765 if (isNaturalMemoryOperand(C.Op1, C.ICmpType) && C.Op1.hasOneUse())
1768 // Look for cases where Cmp0 is a single-use load and Cmp1 isn't.
1769 // In that case we generally prefer the memory to be second.
1770 if (isNaturalMemoryOperand(C.Op0, C.ICmpType) && C.Op0.hasOneUse()) {
1771 // The only exceptions are when the second operand is a constant and
1772 // we can use things like CHHSI.
1775 // The unsigned memory-immediate instructions can handle 16-bit
1776 // unsigned integers.
1777 if (C.ICmpType != SystemZICMP::SignedOnly &&
1778 isUInt<16>(ConstOp1->getZExtValue()))
1780 // The signed memory-immediate instructions can handle 16-bit
1782 if (C.ICmpType != SystemZICMP::UnsignedOnly &&
1783 isInt<16>(ConstOp1->getSExtValue()))
1788 // Try to promote the use of CGFR and CLGFR.
1789 unsigned Opcode0 = C.Op0.getOpcode();
1790 if (C.ICmpType != SystemZICMP::UnsignedOnly && Opcode0 == ISD::SIGN_EXTEND)
1792 if (C.ICmpType != SystemZICMP::SignedOnly && Opcode0 == ISD::ZERO_EXTEND)
1794 if (C.ICmpType != SystemZICMP::SignedOnly &&
1795 Opcode0 == ISD::AND &&
1796 C.Op0.getOperand(1).getOpcode() == ISD::Constant &&
1797 cast<ConstantSDNode>(C.Op0.getOperand(1))->getZExtValue() == 0xffffffff)
1803 // Return a version of comparison CC mask CCMask in which the LT and GT
1804 // actions are swapped.
1805 static unsigned reverseCCMask(unsigned CCMask) {
1806 return ((CCMask & SystemZ::CCMASK_CMP_EQ) |
1807 (CCMask & SystemZ::CCMASK_CMP_GT ? SystemZ::CCMASK_CMP_LT : 0) |
1808 (CCMask & SystemZ::CCMASK_CMP_LT ? SystemZ::CCMASK_CMP_GT : 0) |
1809 (CCMask & SystemZ::CCMASK_CMP_UO));
1812 // Check whether C tests for equality between X and Y and whether X - Y
1813 // or Y - X is also computed. In that case it's better to compare the
1814 // result of the subtraction against zero.
1815 static void adjustForSubtraction(SelectionDAG &DAG, const SDLoc &DL,
1817 if (C.CCMask == SystemZ::CCMASK_CMP_EQ ||
1818 C.CCMask == SystemZ::CCMASK_CMP_NE) {
1819 for (auto I = C.Op0->use_begin(), E = C.Op0->use_end(); I != E; ++I) {
1821 if (N->getOpcode() == ISD::SUB &&
1822 ((N->getOperand(0) == C.Op0 && N->getOperand(1) == C.Op1) ||
1823 (N->getOperand(0) == C.Op1 && N->getOperand(1) == C.Op0))) {
1824 C.Op0 = SDValue(N, 0);
1825 C.Op1 = DAG.getConstant(0, DL, N->getValueType(0));
1832 // Check whether C compares a floating-point value with zero and if that
1833 // floating-point value is also negated. In this case we can use the
1834 // negation to set CC, so avoiding separate LOAD AND TEST and
1835 // LOAD (NEGATIVE/COMPLEMENT) instructions.
1836 static void adjustForFNeg(Comparison &C) {
1837 auto *C1 = dyn_cast<ConstantFPSDNode>(C.Op1);
1838 if (C1 && C1->isZero()) {
1839 for (auto I = C.Op0->use_begin(), E = C.Op0->use_end(); I != E; ++I) {
1841 if (N->getOpcode() == ISD::FNEG) {
1842 C.Op0 = SDValue(N, 0);
1843 C.CCMask = reverseCCMask(C.CCMask);
1850 // Check whether C compares (shl X, 32) with 0 and whether X is
1851 // also sign-extended. In that case it is better to test the result
1852 // of the sign extension using LTGFR.
1854 // This case is important because InstCombine transforms a comparison
1855 // with (sext (trunc X)) into a comparison with (shl X, 32).
1856 static void adjustForLTGFR(Comparison &C) {
1857 // Check for a comparison between (shl X, 32) and 0.
1858 if (C.Op0.getOpcode() == ISD::SHL &&
1859 C.Op0.getValueType() == MVT::i64 &&
1860 C.Op1.getOpcode() == ISD::Constant &&
1861 cast<ConstantSDNode>(C.Op1)->getZExtValue() == 0) {
1862 auto *C1 = dyn_cast<ConstantSDNode>(C.Op0.getOperand(1));
1863 if (C1 && C1->getZExtValue() == 32) {
1864 SDValue ShlOp0 = C.Op0.getOperand(0);
1865 // See whether X has any SIGN_EXTEND_INREG uses.
1866 for (auto I = ShlOp0->use_begin(), E = ShlOp0->use_end(); I != E; ++I) {
1868 if (N->getOpcode() == ISD::SIGN_EXTEND_INREG &&
1869 cast<VTSDNode>(N->getOperand(1))->getVT() == MVT::i32) {
1870 C.Op0 = SDValue(N, 0);
1878 // If C compares the truncation of an extending load, try to compare
1879 // the untruncated value instead. This exposes more opportunities to
1881 static void adjustICmpTruncate(SelectionDAG &DAG, const SDLoc &DL,
1883 if (C.Op0.getOpcode() == ISD::TRUNCATE &&
1884 C.Op0.getOperand(0).getOpcode() == ISD::LOAD &&
1885 C.Op1.getOpcode() == ISD::Constant &&
1886 cast<ConstantSDNode>(C.Op1)->getZExtValue() == 0) {
1887 auto *L = cast<LoadSDNode>(C.Op0.getOperand(0));
1888 if (L->getMemoryVT().getStoreSizeInBits() <= C.Op0.getValueSizeInBits()) {
1889 unsigned Type = L->getExtensionType();
1890 if ((Type == ISD::ZEXTLOAD && C.ICmpType != SystemZICMP::SignedOnly) ||
1891 (Type == ISD::SEXTLOAD && C.ICmpType != SystemZICMP::UnsignedOnly)) {
1892 C.Op0 = C.Op0.getOperand(0);
1893 C.Op1 = DAG.getConstant(0, DL, C.Op0.getValueType());
1899 // Return true if shift operation N has an in-range constant shift value.
1900 // Store it in ShiftVal if so.
1901 static bool isSimpleShift(SDValue N, unsigned &ShiftVal) {
1902 auto *Shift = dyn_cast<ConstantSDNode>(N.getOperand(1));
1906 uint64_t Amount = Shift->getZExtValue();
1907 if (Amount >= N.getValueSizeInBits())
1914 // Check whether an AND with Mask is suitable for a TEST UNDER MASK
1915 // instruction and whether the CC value is descriptive enough to handle
1916 // a comparison of type Opcode between the AND result and CmpVal.
1917 // CCMask says which comparison result is being tested and BitSize is
1918 // the number of bits in the operands. If TEST UNDER MASK can be used,
1919 // return the corresponding CC mask, otherwise return 0.
1920 static unsigned getTestUnderMaskCond(unsigned BitSize, unsigned CCMask,
1921 uint64_t Mask, uint64_t CmpVal,
1922 unsigned ICmpType) {
1923 assert(Mask != 0 && "ANDs with zero should have been removed by now");
1925 // Check whether the mask is suitable for TMHH, TMHL, TMLH or TMLL.
1926 if (!SystemZ::isImmLL(Mask) && !SystemZ::isImmLH(Mask) &&
1927 !SystemZ::isImmHL(Mask) && !SystemZ::isImmHH(Mask))
1930 // Work out the masks for the lowest and highest bits.
1931 unsigned HighShift = 63 - countLeadingZeros(Mask);
1932 uint64_t High = uint64_t(1) << HighShift;
1933 uint64_t Low = uint64_t(1) << countTrailingZeros(Mask);
1935 // Signed ordered comparisons are effectively unsigned if the sign
1937 bool EffectivelyUnsigned = (ICmpType != SystemZICMP::SignedOnly);
1939 // Check for equality comparisons with 0, or the equivalent.
1941 if (CCMask == SystemZ::CCMASK_CMP_EQ)
1942 return SystemZ::CCMASK_TM_ALL_0;
1943 if (CCMask == SystemZ::CCMASK_CMP_NE)
1944 return SystemZ::CCMASK_TM_SOME_1;
1946 if (EffectivelyUnsigned && CmpVal > 0 && CmpVal <= Low) {
1947 if (CCMask == SystemZ::CCMASK_CMP_LT)
1948 return SystemZ::CCMASK_TM_ALL_0;
1949 if (CCMask == SystemZ::CCMASK_CMP_GE)
1950 return SystemZ::CCMASK_TM_SOME_1;
1952 if (EffectivelyUnsigned && CmpVal < Low) {
1953 if (CCMask == SystemZ::CCMASK_CMP_LE)
1954 return SystemZ::CCMASK_TM_ALL_0;
1955 if (CCMask == SystemZ::CCMASK_CMP_GT)
1956 return SystemZ::CCMASK_TM_SOME_1;
1959 // Check for equality comparisons with the mask, or the equivalent.
1960 if (CmpVal == Mask) {
1961 if (CCMask == SystemZ::CCMASK_CMP_EQ)
1962 return SystemZ::CCMASK_TM_ALL_1;
1963 if (CCMask == SystemZ::CCMASK_CMP_NE)
1964 return SystemZ::CCMASK_TM_SOME_0;
1966 if (EffectivelyUnsigned && CmpVal >= Mask - Low && CmpVal < Mask) {
1967 if (CCMask == SystemZ::CCMASK_CMP_GT)
1968 return SystemZ::CCMASK_TM_ALL_1;
1969 if (CCMask == SystemZ::CCMASK_CMP_LE)
1970 return SystemZ::CCMASK_TM_SOME_0;
1972 if (EffectivelyUnsigned && CmpVal > Mask - Low && CmpVal <= Mask) {
1973 if (CCMask == SystemZ::CCMASK_CMP_GE)
1974 return SystemZ::CCMASK_TM_ALL_1;
1975 if (CCMask == SystemZ::CCMASK_CMP_LT)
1976 return SystemZ::CCMASK_TM_SOME_0;
1979 // Check for ordered comparisons with the top bit.
1980 if (EffectivelyUnsigned && CmpVal >= Mask - High && CmpVal < High) {
1981 if (CCMask == SystemZ::CCMASK_CMP_LE)
1982 return SystemZ::CCMASK_TM_MSB_0;
1983 if (CCMask == SystemZ::CCMASK_CMP_GT)
1984 return SystemZ::CCMASK_TM_MSB_1;
1986 if (EffectivelyUnsigned && CmpVal > Mask - High && CmpVal <= High) {
1987 if (CCMask == SystemZ::CCMASK_CMP_LT)
1988 return SystemZ::CCMASK_TM_MSB_0;
1989 if (CCMask == SystemZ::CCMASK_CMP_GE)
1990 return SystemZ::CCMASK_TM_MSB_1;
1993 // If there are just two bits, we can do equality checks for Low and High
1995 if (Mask == Low + High) {
1996 if (CCMask == SystemZ::CCMASK_CMP_EQ && CmpVal == Low)
1997 return SystemZ::CCMASK_TM_MIXED_MSB_0;
1998 if (CCMask == SystemZ::CCMASK_CMP_NE && CmpVal == Low)
1999 return SystemZ::CCMASK_TM_MIXED_MSB_0 ^ SystemZ::CCMASK_ANY;
2000 if (CCMask == SystemZ::CCMASK_CMP_EQ && CmpVal == High)
2001 return SystemZ::CCMASK_TM_MIXED_MSB_1;
2002 if (CCMask == SystemZ::CCMASK_CMP_NE && CmpVal == High)
2003 return SystemZ::CCMASK_TM_MIXED_MSB_1 ^ SystemZ::CCMASK_ANY;
2006 // Looks like we've exhausted our options.
2010 // See whether C can be implemented as a TEST UNDER MASK instruction.
2011 // Update the arguments with the TM version if so.
2012 static void adjustForTestUnderMask(SelectionDAG &DAG, const SDLoc &DL,
2014 // Check that we have a comparison with a constant.
2015 auto *ConstOp1 = dyn_cast<ConstantSDNode>(C.Op1);
2018 uint64_t CmpVal = ConstOp1->getZExtValue();
2020 // Check whether the nonconstant input is an AND with a constant mask.
2023 ConstantSDNode *Mask = nullptr;
2024 if (C.Op0.getOpcode() == ISD::AND) {
2025 NewC.Op0 = C.Op0.getOperand(0);
2026 NewC.Op1 = C.Op0.getOperand(1);
2027 Mask = dyn_cast<ConstantSDNode>(NewC.Op1);
2030 MaskVal = Mask->getZExtValue();
2032 // There is no instruction to compare with a 64-bit immediate
2033 // so use TMHH instead if possible. We need an unsigned ordered
2034 // comparison with an i64 immediate.
2035 if (NewC.Op0.getValueType() != MVT::i64 ||
2036 NewC.CCMask == SystemZ::CCMASK_CMP_EQ ||
2037 NewC.CCMask == SystemZ::CCMASK_CMP_NE ||
2038 NewC.ICmpType == SystemZICMP::SignedOnly)
2040 // Convert LE and GT comparisons into LT and GE.
2041 if (NewC.CCMask == SystemZ::CCMASK_CMP_LE ||
2042 NewC.CCMask == SystemZ::CCMASK_CMP_GT) {
2043 if (CmpVal == uint64_t(-1))
2046 NewC.CCMask ^= SystemZ::CCMASK_CMP_EQ;
2048 // If the low N bits of Op1 are zero than the low N bits of Op0 can
2049 // be masked off without changing the result.
2050 MaskVal = -(CmpVal & -CmpVal);
2051 NewC.ICmpType = SystemZICMP::UnsignedOnly;
2056 // Check whether the combination of mask, comparison value and comparison
2057 // type are suitable.
2058 unsigned BitSize = NewC.Op0.getValueSizeInBits();
2059 unsigned NewCCMask, ShiftVal;
2060 if (NewC.ICmpType != SystemZICMP::SignedOnly &&
2061 NewC.Op0.getOpcode() == ISD::SHL &&
2062 isSimpleShift(NewC.Op0, ShiftVal) &&
2063 (NewCCMask = getTestUnderMaskCond(BitSize, NewC.CCMask,
2064 MaskVal >> ShiftVal,
2066 SystemZICMP::Any))) {
2067 NewC.Op0 = NewC.Op0.getOperand(0);
2068 MaskVal >>= ShiftVal;
2069 } else if (NewC.ICmpType != SystemZICMP::SignedOnly &&
2070 NewC.Op0.getOpcode() == ISD::SRL &&
2071 isSimpleShift(NewC.Op0, ShiftVal) &&
2072 (NewCCMask = getTestUnderMaskCond(BitSize, NewC.CCMask,
2073 MaskVal << ShiftVal,
2075 SystemZICMP::UnsignedOnly))) {
2076 NewC.Op0 = NewC.Op0.getOperand(0);
2077 MaskVal <<= ShiftVal;
2079 NewCCMask = getTestUnderMaskCond(BitSize, NewC.CCMask, MaskVal, CmpVal,
2085 // Go ahead and make the change.
2086 C.Opcode = SystemZISD::TM;
2088 if (Mask && Mask->getZExtValue() == MaskVal)
2089 C.Op1 = SDValue(Mask, 0);
2091 C.Op1 = DAG.getConstant(MaskVal, DL, C.Op0.getValueType());
2092 C.CCValid = SystemZ::CCMASK_TM;
2093 C.CCMask = NewCCMask;
2096 // Return a Comparison that tests the condition-code result of intrinsic
2097 // node Call against constant integer CC using comparison code Cond.
2098 // Opcode is the opcode of the SystemZISD operation for the intrinsic
2099 // and CCValid is the set of possible condition-code results.
2100 static Comparison getIntrinsicCmp(SelectionDAG &DAG, unsigned Opcode,
2101 SDValue Call, unsigned CCValid, uint64_t CC,
2102 ISD::CondCode Cond) {
2103 Comparison C(Call, SDValue());
2105 C.CCValid = CCValid;
2106 if (Cond == ISD::SETEQ)
2107 // bit 3 for CC==0, bit 0 for CC==3, always false for CC>3.
2108 C.CCMask = CC < 4 ? 1 << (3 - CC) : 0;
2109 else if (Cond == ISD::SETNE)
2110 // ...and the inverse of that.
2111 C.CCMask = CC < 4 ? ~(1 << (3 - CC)) : -1;
2112 else if (Cond == ISD::SETLT || Cond == ISD::SETULT)
2113 // bits above bit 3 for CC==0 (always false), bits above bit 0 for CC==3,
2114 // always true for CC>3.
2115 C.CCMask = CC < 4 ? ~0U << (4 - CC) : -1;
2116 else if (Cond == ISD::SETGE || Cond == ISD::SETUGE)
2117 // ...and the inverse of that.
2118 C.CCMask = CC < 4 ? ~(~0U << (4 - CC)) : 0;
2119 else if (Cond == ISD::SETLE || Cond == ISD::SETULE)
2120 // bit 3 and above for CC==0, bit 0 and above for CC==3 (always true),
2121 // always true for CC>3.
2122 C.CCMask = CC < 4 ? ~0U << (3 - CC) : -1;
2123 else if (Cond == ISD::SETGT || Cond == ISD::SETUGT)
2124 // ...and the inverse of that.
2125 C.CCMask = CC < 4 ? ~(~0U << (3 - CC)) : 0;
2127 llvm_unreachable("Unexpected integer comparison type");
2128 C.CCMask &= CCValid;
2132 // Decide how to implement a comparison of type Cond between CmpOp0 with CmpOp1.
2133 static Comparison getCmp(SelectionDAG &DAG, SDValue CmpOp0, SDValue CmpOp1,
2134 ISD::CondCode Cond, const SDLoc &DL) {
2135 if (CmpOp1.getOpcode() == ISD::Constant) {
2136 uint64_t Constant = cast<ConstantSDNode>(CmpOp1)->getZExtValue();
2137 unsigned Opcode, CCValid;
2138 if (CmpOp0.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
2139 CmpOp0.getResNo() == 0 && CmpOp0->hasNUsesOfValue(1, 0) &&
2140 isIntrinsicWithCCAndChain(CmpOp0, Opcode, CCValid))
2141 return getIntrinsicCmp(DAG, Opcode, CmpOp0, CCValid, Constant, Cond);
2142 if (CmpOp0.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
2143 CmpOp0.getResNo() == CmpOp0->getNumValues() - 1 &&
2144 isIntrinsicWithCC(CmpOp0, Opcode, CCValid))
2145 return getIntrinsicCmp(DAG, Opcode, CmpOp0, CCValid, Constant, Cond);
2147 Comparison C(CmpOp0, CmpOp1);
2148 C.CCMask = CCMaskForCondCode(Cond);
2149 if (C.Op0.getValueType().isFloatingPoint()) {
2150 C.CCValid = SystemZ::CCMASK_FCMP;
2151 C.Opcode = SystemZISD::FCMP;
2154 C.CCValid = SystemZ::CCMASK_ICMP;
2155 C.Opcode = SystemZISD::ICMP;
2156 // Choose the type of comparison. Equality and inequality tests can
2157 // use either signed or unsigned comparisons. The choice also doesn't
2158 // matter if both sign bits are known to be clear. In those cases we
2159 // want to give the main isel code the freedom to choose whichever
2161 if (C.CCMask == SystemZ::CCMASK_CMP_EQ ||
2162 C.CCMask == SystemZ::CCMASK_CMP_NE ||
2163 (DAG.SignBitIsZero(C.Op0) && DAG.SignBitIsZero(C.Op1)))
2164 C.ICmpType = SystemZICMP::Any;
2165 else if (C.CCMask & SystemZ::CCMASK_CMP_UO)
2166 C.ICmpType = SystemZICMP::UnsignedOnly;
2168 C.ICmpType = SystemZICMP::SignedOnly;
2169 C.CCMask &= ~SystemZ::CCMASK_CMP_UO;
2170 adjustZeroCmp(DAG, DL, C);
2171 adjustSubwordCmp(DAG, DL, C);
2172 adjustForSubtraction(DAG, DL, C);
2174 adjustICmpTruncate(DAG, DL, C);
2177 if (shouldSwapCmpOperands(C)) {
2178 std::swap(C.Op0, C.Op1);
2179 C.CCMask = reverseCCMask(C.CCMask);
2182 adjustForTestUnderMask(DAG, DL, C);
2186 // Emit the comparison instruction described by C.
2187 static SDValue emitCmp(SelectionDAG &DAG, const SDLoc &DL, Comparison &C) {
2188 if (!C.Op1.getNode()) {
2190 switch (C.Op0.getOpcode()) {
2191 case ISD::INTRINSIC_W_CHAIN:
2192 Op = emitIntrinsicWithChainAndGlue(DAG, C.Op0, C.Opcode);
2194 case ISD::INTRINSIC_WO_CHAIN:
2195 Op = emitIntrinsicWithGlue(DAG, C.Op0, C.Opcode);
2198 llvm_unreachable("Invalid comparison operands");
2200 return SDValue(Op.getNode(), Op->getNumValues() - 1);
2202 if (C.Opcode == SystemZISD::ICMP)
2203 return DAG.getNode(SystemZISD::ICMP, DL, MVT::Glue, C.Op0, C.Op1,
2204 DAG.getConstant(C.ICmpType, DL, MVT::i32));
2205 if (C.Opcode == SystemZISD::TM) {
2206 bool RegisterOnly = (bool(C.CCMask & SystemZ::CCMASK_TM_MIXED_MSB_0) !=
2207 bool(C.CCMask & SystemZ::CCMASK_TM_MIXED_MSB_1));
2208 return DAG.getNode(SystemZISD::TM, DL, MVT::Glue, C.Op0, C.Op1,
2209 DAG.getConstant(RegisterOnly, DL, MVT::i32));
2211 return DAG.getNode(C.Opcode, DL, MVT::Glue, C.Op0, C.Op1);
2214 // Implement a 32-bit *MUL_LOHI operation by extending both operands to
2215 // 64 bits. Extend is the extension type to use. Store the high part
2216 // in Hi and the low part in Lo.
2217 static void lowerMUL_LOHI32(SelectionDAG &DAG, const SDLoc &DL, unsigned Extend,
2218 SDValue Op0, SDValue Op1, SDValue &Hi,
2220 Op0 = DAG.getNode(Extend, DL, MVT::i64, Op0);
2221 Op1 = DAG.getNode(Extend, DL, MVT::i64, Op1);
2222 SDValue Mul = DAG.getNode(ISD::MUL, DL, MVT::i64, Op0, Op1);
2223 Hi = DAG.getNode(ISD::SRL, DL, MVT::i64, Mul,
2224 DAG.getConstant(32, DL, MVT::i64));
2225 Hi = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Hi);
2226 Lo = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mul);
2229 // Lower a binary operation that produces two VT results, one in each
2230 // half of a GR128 pair. Op0 and Op1 are the VT operands to the operation,
2231 // Extend extends Op0 to a GR128, and Opcode performs the GR128 operation
2232 // on the extended Op0 and (unextended) Op1. Store the even register result
2233 // in Even and the odd register result in Odd.
2234 static void lowerGR128Binary(SelectionDAG &DAG, const SDLoc &DL, EVT VT,
2235 unsigned Extend, unsigned Opcode, SDValue Op0,
2236 SDValue Op1, SDValue &Even, SDValue &Odd) {
2237 SDNode *In128 = DAG.getMachineNode(Extend, DL, MVT::Untyped, Op0);
2238 SDValue Result = DAG.getNode(Opcode, DL, MVT::Untyped,
2239 SDValue(In128, 0), Op1);
2240 bool Is32Bit = is32Bit(VT);
2241 Even = DAG.getTargetExtractSubreg(SystemZ::even128(Is32Bit), DL, VT, Result);
2242 Odd = DAG.getTargetExtractSubreg(SystemZ::odd128(Is32Bit), DL, VT, Result);
2245 // Return an i32 value that is 1 if the CC value produced by Glue is
2246 // in the mask CCMask and 0 otherwise. CC is known to have a value
2247 // in CCValid, so other values can be ignored.
2248 static SDValue emitSETCC(SelectionDAG &DAG, const SDLoc &DL, SDValue Glue,
2249 unsigned CCValid, unsigned CCMask) {
2250 IPMConversion Conversion = getIPMConversion(CCValid, CCMask);
2251 SDValue Result = DAG.getNode(SystemZISD::IPM, DL, MVT::i32, Glue);
2253 if (Conversion.XORValue)
2254 Result = DAG.getNode(ISD::XOR, DL, MVT::i32, Result,
2255 DAG.getConstant(Conversion.XORValue, DL, MVT::i32));
2257 if (Conversion.AddValue)
2258 Result = DAG.getNode(ISD::ADD, DL, MVT::i32, Result,
2259 DAG.getConstant(Conversion.AddValue, DL, MVT::i32));
2261 // The SHR/AND sequence should get optimized to an RISBG.
2262 Result = DAG.getNode(ISD::SRL, DL, MVT::i32, Result,
2263 DAG.getConstant(Conversion.Bit, DL, MVT::i32));
2264 if (Conversion.Bit != 31)
2265 Result = DAG.getNode(ISD::AND, DL, MVT::i32, Result,
2266 DAG.getConstant(1, DL, MVT::i32));
2270 // Return the SystemISD vector comparison operation for CC, or 0 if it cannot
2271 // be done directly. IsFP is true if CC is for a floating-point rather than
2272 // integer comparison.
2273 static unsigned getVectorComparison(ISD::CondCode CC, bool IsFP) {
2277 return IsFP ? SystemZISD::VFCMPE : SystemZISD::VICMPE;
2281 return IsFP ? SystemZISD::VFCMPHE : static_cast<SystemZISD::NodeType>(0);
2285 return IsFP ? SystemZISD::VFCMPH : SystemZISD::VICMPH;
2288 return IsFP ? static_cast<SystemZISD::NodeType>(0) : SystemZISD::VICMPHL;
2295 // Return the SystemZISD vector comparison operation for CC or its inverse,
2296 // or 0 if neither can be done directly. Indicate in Invert whether the
2297 // result is for the inverse of CC. IsFP is true if CC is for a
2298 // floating-point rather than integer comparison.
2299 static unsigned getVectorComparisonOrInvert(ISD::CondCode CC, bool IsFP,
2301 if (unsigned Opcode = getVectorComparison(CC, IsFP)) {
2306 CC = ISD::getSetCCInverse(CC, !IsFP);
2307 if (unsigned Opcode = getVectorComparison(CC, IsFP)) {
2315 // Return a v2f64 that contains the extended form of elements Start and Start+1
2316 // of v4f32 value Op.
2317 static SDValue expandV4F32ToV2F64(SelectionDAG &DAG, int Start, const SDLoc &DL,
2319 int Mask[] = { Start, -1, Start + 1, -1 };
2320 Op = DAG.getVectorShuffle(MVT::v4f32, DL, Op, DAG.getUNDEF(MVT::v4f32), Mask);
2321 return DAG.getNode(SystemZISD::VEXTEND, DL, MVT::v2f64, Op);
2324 // Build a comparison of vectors CmpOp0 and CmpOp1 using opcode Opcode,
2325 // producing a result of type VT.
2326 static SDValue getVectorCmp(SelectionDAG &DAG, unsigned Opcode, const SDLoc &DL,
2327 EVT VT, SDValue CmpOp0, SDValue CmpOp1) {
2328 // There is no hardware support for v4f32, so extend the vector into
2329 // two v2f64s and compare those.
2330 if (CmpOp0.getValueType() == MVT::v4f32) {
2331 SDValue H0 = expandV4F32ToV2F64(DAG, 0, DL, CmpOp0);
2332 SDValue L0 = expandV4F32ToV2F64(DAG, 2, DL, CmpOp0);
2333 SDValue H1 = expandV4F32ToV2F64(DAG, 0, DL, CmpOp1);
2334 SDValue L1 = expandV4F32ToV2F64(DAG, 2, DL, CmpOp1);
2335 SDValue HRes = DAG.getNode(Opcode, DL, MVT::v2i64, H0, H1);
2336 SDValue LRes = DAG.getNode(Opcode, DL, MVT::v2i64, L0, L1);
2337 return DAG.getNode(SystemZISD::PACK, DL, VT, HRes, LRes);
2339 return DAG.getNode(Opcode, DL, VT, CmpOp0, CmpOp1);
2342 // Lower a vector comparison of type CC between CmpOp0 and CmpOp1, producing
2343 // an integer mask of type VT.
2344 static SDValue lowerVectorSETCC(SelectionDAG &DAG, const SDLoc &DL, EVT VT,
2345 ISD::CondCode CC, SDValue CmpOp0,
2347 bool IsFP = CmpOp0.getValueType().isFloatingPoint();
2348 bool Invert = false;
2351 // Handle tests for order using (or (ogt y x) (oge x y)).
2355 assert(IsFP && "Unexpected integer comparison");
2356 SDValue LT = getVectorCmp(DAG, SystemZISD::VFCMPH, DL, VT, CmpOp1, CmpOp0);
2357 SDValue GE = getVectorCmp(DAG, SystemZISD::VFCMPHE, DL, VT, CmpOp0, CmpOp1);
2358 Cmp = DAG.getNode(ISD::OR, DL, VT, LT, GE);
2362 // Handle <> tests using (or (ogt y x) (ogt x y)).
2366 assert(IsFP && "Unexpected integer comparison");
2367 SDValue LT = getVectorCmp(DAG, SystemZISD::VFCMPH, DL, VT, CmpOp1, CmpOp0);
2368 SDValue GT = getVectorCmp(DAG, SystemZISD::VFCMPH, DL, VT, CmpOp0, CmpOp1);
2369 Cmp = DAG.getNode(ISD::OR, DL, VT, LT, GT);
2373 // Otherwise a single comparison is enough. It doesn't really
2374 // matter whether we try the inversion or the swap first, since
2375 // there are no cases where both work.
2377 if (unsigned Opcode = getVectorComparisonOrInvert(CC, IsFP, Invert))
2378 Cmp = getVectorCmp(DAG, Opcode, DL, VT, CmpOp0, CmpOp1);
2380 CC = ISD::getSetCCSwappedOperands(CC);
2381 if (unsigned Opcode = getVectorComparisonOrInvert(CC, IsFP, Invert))
2382 Cmp = getVectorCmp(DAG, Opcode, DL, VT, CmpOp1, CmpOp0);
2384 llvm_unreachable("Unhandled comparison");
2389 SDValue Mask = DAG.getNode(SystemZISD::BYTE_MASK, DL, MVT::v16i8,
2390 DAG.getConstant(65535, DL, MVT::i32));
2391 Mask = DAG.getNode(ISD::BITCAST, DL, VT, Mask);
2392 Cmp = DAG.getNode(ISD::XOR, DL, VT, Cmp, Mask);
2397 SDValue SystemZTargetLowering::lowerSETCC(SDValue Op,
2398 SelectionDAG &DAG) const {
2399 SDValue CmpOp0 = Op.getOperand(0);
2400 SDValue CmpOp1 = Op.getOperand(1);
2401 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
2403 EVT VT = Op.getValueType();
2405 return lowerVectorSETCC(DAG, DL, VT, CC, CmpOp0, CmpOp1);
2407 Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC, DL));
2408 SDValue Glue = emitCmp(DAG, DL, C);
2409 return emitSETCC(DAG, DL, Glue, C.CCValid, C.CCMask);
2412 SDValue SystemZTargetLowering::lowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
2413 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2414 SDValue CmpOp0 = Op.getOperand(2);
2415 SDValue CmpOp1 = Op.getOperand(3);
2416 SDValue Dest = Op.getOperand(4);
2419 Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC, DL));
2420 SDValue Glue = emitCmp(DAG, DL, C);
2421 return DAG.getNode(SystemZISD::BR_CCMASK, DL, Op.getValueType(),
2422 Op.getOperand(0), DAG.getConstant(C.CCValid, DL, MVT::i32),
2423 DAG.getConstant(C.CCMask, DL, MVT::i32), Dest, Glue);
2426 // Return true if Pos is CmpOp and Neg is the negative of CmpOp,
2427 // allowing Pos and Neg to be wider than CmpOp.
2428 static bool isAbsolute(SDValue CmpOp, SDValue Pos, SDValue Neg) {
2429 return (Neg.getOpcode() == ISD::SUB &&
2430 Neg.getOperand(0).getOpcode() == ISD::Constant &&
2431 cast<ConstantSDNode>(Neg.getOperand(0))->getZExtValue() == 0 &&
2432 Neg.getOperand(1) == Pos &&
2434 (Pos.getOpcode() == ISD::SIGN_EXTEND &&
2435 Pos.getOperand(0) == CmpOp)));
2438 // Return the absolute or negative absolute of Op; IsNegative decides which.
2439 static SDValue getAbsolute(SelectionDAG &DAG, const SDLoc &DL, SDValue Op,
2441 Op = DAG.getNode(SystemZISD::IABS, DL, Op.getValueType(), Op);
2443 Op = DAG.getNode(ISD::SUB, DL, Op.getValueType(),
2444 DAG.getConstant(0, DL, Op.getValueType()), Op);
2448 SDValue SystemZTargetLowering::lowerSELECT_CC(SDValue Op,
2449 SelectionDAG &DAG) const {
2450 SDValue CmpOp0 = Op.getOperand(0);
2451 SDValue CmpOp1 = Op.getOperand(1);
2452 SDValue TrueOp = Op.getOperand(2);
2453 SDValue FalseOp = Op.getOperand(3);
2454 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2457 Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC, DL));
2459 // Check for absolute and negative-absolute selections, including those
2460 // where the comparison value is sign-extended (for LPGFR and LNGFR).
2461 // This check supplements the one in DAGCombiner.
2462 if (C.Opcode == SystemZISD::ICMP &&
2463 C.CCMask != SystemZ::CCMASK_CMP_EQ &&
2464 C.CCMask != SystemZ::CCMASK_CMP_NE &&
2465 C.Op1.getOpcode() == ISD::Constant &&
2466 cast<ConstantSDNode>(C.Op1)->getZExtValue() == 0) {
2467 if (isAbsolute(C.Op0, TrueOp, FalseOp))
2468 return getAbsolute(DAG, DL, TrueOp, C.CCMask & SystemZ::CCMASK_CMP_LT);
2469 if (isAbsolute(C.Op0, FalseOp, TrueOp))
2470 return getAbsolute(DAG, DL, FalseOp, C.CCMask & SystemZ::CCMASK_CMP_GT);
2473 SDValue Glue = emitCmp(DAG, DL, C);
2475 // Special case for handling -1/0 results. The shifts we use here
2476 // should get optimized with the IPM conversion sequence.
2477 auto *TrueC = dyn_cast<ConstantSDNode>(TrueOp);
2478 auto *FalseC = dyn_cast<ConstantSDNode>(FalseOp);
2479 if (TrueC && FalseC) {
2480 int64_t TrueVal = TrueC->getSExtValue();
2481 int64_t FalseVal = FalseC->getSExtValue();
2482 if ((TrueVal == -1 && FalseVal == 0) || (TrueVal == 0 && FalseVal == -1)) {
2483 // Invert the condition if we want -1 on false.
2485 C.CCMask ^= C.CCValid;
2486 SDValue Result = emitSETCC(DAG, DL, Glue, C.CCValid, C.CCMask);
2487 EVT VT = Op.getValueType();
2488 // Extend the result to VT. Upper bits are ignored.
2490 Result = DAG.getNode(ISD::ANY_EXTEND, DL, VT, Result);
2491 // Sign-extend from the low bit.
2492 SDValue ShAmt = DAG.getConstant(VT.getSizeInBits() - 1, DL, MVT::i32);
2493 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, Result, ShAmt);
2494 return DAG.getNode(ISD::SRA, DL, VT, Shl, ShAmt);
2498 SDValue Ops[] = {TrueOp, FalseOp, DAG.getConstant(C.CCValid, DL, MVT::i32),
2499 DAG.getConstant(C.CCMask, DL, MVT::i32), Glue};
2501 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
2502 return DAG.getNode(SystemZISD::SELECT_CCMASK, DL, VTs, Ops);
2505 SDValue SystemZTargetLowering::lowerGlobalAddress(GlobalAddressSDNode *Node,
2506 SelectionDAG &DAG) const {
2508 const GlobalValue *GV = Node->getGlobal();
2509 int64_t Offset = Node->getOffset();
2510 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2511 CodeModel::Model CM = DAG.getTarget().getCodeModel();
2514 if (Subtarget.isPC32DBLSymbol(GV, CM)) {
2515 // Assign anchors at 1<<12 byte boundaries.
2516 uint64_t Anchor = Offset & ~uint64_t(0xfff);
2517 Result = DAG.getTargetGlobalAddress(GV, DL, PtrVT, Anchor);
2518 Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
2520 // The offset can be folded into the address if it is aligned to a halfword.
2522 if (Offset != 0 && (Offset & 1) == 0) {
2523 SDValue Full = DAG.getTargetGlobalAddress(GV, DL, PtrVT, Anchor + Offset);
2524 Result = DAG.getNode(SystemZISD::PCREL_OFFSET, DL, PtrVT, Full, Result);
2528 Result = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, SystemZII::MO_GOT);
2529 Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
2530 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
2531 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
2534 // If there was a non-zero offset that we didn't fold, create an explicit
2537 Result = DAG.getNode(ISD::ADD, DL, PtrVT, Result,
2538 DAG.getConstant(Offset, DL, PtrVT));
2543 SDValue SystemZTargetLowering::lowerTLSGetOffset(GlobalAddressSDNode *Node,
2546 SDValue GOTOffset) const {
2548 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2549 SDValue Chain = DAG.getEntryNode();
2552 // __tls_get_offset takes the GOT offset in %r2 and the GOT in %r12.
2553 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
2554 Chain = DAG.getCopyToReg(Chain, DL, SystemZ::R12D, GOT, Glue);
2555 Glue = Chain.getValue(1);
2556 Chain = DAG.getCopyToReg(Chain, DL, SystemZ::R2D, GOTOffset, Glue);
2557 Glue = Chain.getValue(1);
2559 // The first call operand is the chain and the second is the TLS symbol.
2560 SmallVector<SDValue, 8> Ops;
2561 Ops.push_back(Chain);
2562 Ops.push_back(DAG.getTargetGlobalAddress(Node->getGlobal(), DL,
2563 Node->getValueType(0),
2566 // Add argument registers to the end of the list so that they are
2567 // known live into the call.
2568 Ops.push_back(DAG.getRegister(SystemZ::R2D, PtrVT));
2569 Ops.push_back(DAG.getRegister(SystemZ::R12D, PtrVT));
2571 // Add a register mask operand representing the call-preserved registers.
2572 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
2573 const uint32_t *Mask =
2574 TRI->getCallPreservedMask(DAG.getMachineFunction(), CallingConv::C);
2575 assert(Mask && "Missing call preserved mask for calling convention");
2576 Ops.push_back(DAG.getRegisterMask(Mask));
2578 // Glue the call to the argument copies.
2579 Ops.push_back(Glue);
2582 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2583 Chain = DAG.getNode(Opcode, DL, NodeTys, Ops);
2584 Glue = Chain.getValue(1);
2586 // Copy the return value from %r2.
2587 return DAG.getCopyFromReg(Chain, DL, SystemZ::R2D, PtrVT, Glue);
2590 SDValue SystemZTargetLowering::lowerThreadPointer(const SDLoc &DL,
2591 SelectionDAG &DAG) const {
2592 SDValue Chain = DAG.getEntryNode();
2593 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2595 // The high part of the thread pointer is in access register 0.
2596 SDValue TPHi = DAG.getCopyFromReg(Chain, DL, SystemZ::A0, MVT::i32);
2597 TPHi = DAG.getNode(ISD::ANY_EXTEND, DL, PtrVT, TPHi);
2599 // The low part of the thread pointer is in access register 1.
2600 SDValue TPLo = DAG.getCopyFromReg(Chain, DL, SystemZ::A1, MVT::i32);
2601 TPLo = DAG.getNode(ISD::ZERO_EXTEND, DL, PtrVT, TPLo);
2603 // Merge them into a single 64-bit address.
2604 SDValue TPHiShifted = DAG.getNode(ISD::SHL, DL, PtrVT, TPHi,
2605 DAG.getConstant(32, DL, PtrVT));
2606 return DAG.getNode(ISD::OR, DL, PtrVT, TPHiShifted, TPLo);
2609 SDValue SystemZTargetLowering::lowerGlobalTLSAddress(GlobalAddressSDNode *Node,
2610 SelectionDAG &DAG) const {
2611 if (DAG.getTarget().Options.EmulatedTLS)
2612 return LowerToTLSEmulatedModel(Node, DAG);
2614 const GlobalValue *GV = Node->getGlobal();
2615 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2616 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
2618 SDValue TP = lowerThreadPointer(DL, DAG);
2620 // Get the offset of GA from the thread pointer, based on the TLS model.
2623 case TLSModel::GeneralDynamic: {
2624 // Load the GOT offset of the tls_index (module ID / per-symbol offset).
2625 SystemZConstantPoolValue *CPV =
2626 SystemZConstantPoolValue::Create(GV, SystemZCP::TLSGD);
2628 Offset = DAG.getConstantPool(CPV, PtrVT, 8);
2629 Offset = DAG.getLoad(
2630 PtrVT, DL, DAG.getEntryNode(), Offset,
2631 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2633 // Call __tls_get_offset to retrieve the offset.
2634 Offset = lowerTLSGetOffset(Node, DAG, SystemZISD::TLS_GDCALL, Offset);
2638 case TLSModel::LocalDynamic: {
2639 // Load the GOT offset of the module ID.
2640 SystemZConstantPoolValue *CPV =
2641 SystemZConstantPoolValue::Create(GV, SystemZCP::TLSLDM);
2643 Offset = DAG.getConstantPool(CPV, PtrVT, 8);
2644 Offset = DAG.getLoad(
2645 PtrVT, DL, DAG.getEntryNode(), Offset,
2646 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2648 // Call __tls_get_offset to retrieve the module base offset.
2649 Offset = lowerTLSGetOffset(Node, DAG, SystemZISD::TLS_LDCALL, Offset);
2651 // Note: The SystemZLDCleanupPass will remove redundant computations
2652 // of the module base offset. Count total number of local-dynamic
2653 // accesses to trigger execution of that pass.
2654 SystemZMachineFunctionInfo* MFI =
2655 DAG.getMachineFunction().getInfo<SystemZMachineFunctionInfo>();
2656 MFI->incNumLocalDynamicTLSAccesses();
2658 // Add the per-symbol offset.
2659 CPV = SystemZConstantPoolValue::Create(GV, SystemZCP::DTPOFF);
2661 SDValue DTPOffset = DAG.getConstantPool(CPV, PtrVT, 8);
2662 DTPOffset = DAG.getLoad(
2663 PtrVT, DL, DAG.getEntryNode(), DTPOffset,
2664 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2666 Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Offset, DTPOffset);
2670 case TLSModel::InitialExec: {
2671 // Load the offset from the GOT.
2672 Offset = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2673 SystemZII::MO_INDNTPOFF);
2674 Offset = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Offset);
2676 DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Offset,
2677 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
2681 case TLSModel::LocalExec: {
2682 // Force the offset into the constant pool and load it from there.
2683 SystemZConstantPoolValue *CPV =
2684 SystemZConstantPoolValue::Create(GV, SystemZCP::NTPOFF);
2686 Offset = DAG.getConstantPool(CPV, PtrVT, 8);
2687 Offset = DAG.getLoad(
2688 PtrVT, DL, DAG.getEntryNode(), Offset,
2689 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2694 // Add the base and offset together.
2695 return DAG.getNode(ISD::ADD, DL, PtrVT, TP, Offset);
2698 SDValue SystemZTargetLowering::lowerBlockAddress(BlockAddressSDNode *Node,
2699 SelectionDAG &DAG) const {
2701 const BlockAddress *BA = Node->getBlockAddress();
2702 int64_t Offset = Node->getOffset();
2703 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2705 SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT, Offset);
2706 Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
2710 SDValue SystemZTargetLowering::lowerJumpTable(JumpTableSDNode *JT,
2711 SelectionDAG &DAG) const {
2713 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2714 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
2716 // Use LARL to load the address of the table.
2717 return DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
2720 SDValue SystemZTargetLowering::lowerConstantPool(ConstantPoolSDNode *CP,
2721 SelectionDAG &DAG) const {
2723 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2726 if (CP->isMachineConstantPoolEntry())
2727 Result = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
2728 CP->getAlignment());
2730 Result = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
2731 CP->getAlignment(), CP->getOffset());
2733 // Use LARL to load the address of the constant pool entry.
2734 return DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
2737 SDValue SystemZTargetLowering::lowerFRAMEADDR(SDValue Op,
2738 SelectionDAG &DAG) const {
2739 MachineFunction &MF = DAG.getMachineFunction();
2740 MachineFrameInfo &MFI = MF.getFrameInfo();
2741 MFI.setFrameAddressIsTaken(true);
2744 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2745 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2747 // If the back chain frame index has not been allocated yet, do so.
2748 SystemZMachineFunctionInfo *FI = MF.getInfo<SystemZMachineFunctionInfo>();
2749 int BackChainIdx = FI->getFramePointerSaveIndex();
2750 if (!BackChainIdx) {
2751 // By definition, the frame address is the address of the back chain.
2752 BackChainIdx = MFI.CreateFixedObject(8, -SystemZMC::CallFrameSize, false);
2753 FI->setFramePointerSaveIndex(BackChainIdx);
2755 SDValue BackChain = DAG.getFrameIndex(BackChainIdx, PtrVT);
2757 // FIXME The frontend should detect this case.
2759 report_fatal_error("Unsupported stack frame traversal count");
2765 SDValue SystemZTargetLowering::lowerRETURNADDR(SDValue Op,
2766 SelectionDAG &DAG) const {
2767 MachineFunction &MF = DAG.getMachineFunction();
2768 MachineFrameInfo &MFI = MF.getFrameInfo();
2769 MFI.setReturnAddressIsTaken(true);
2771 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
2775 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2776 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2778 // FIXME The frontend should detect this case.
2780 report_fatal_error("Unsupported stack frame traversal count");
2783 // Return R14D, which has the return address. Mark it an implicit live-in.
2784 unsigned LinkReg = MF.addLiveIn(SystemZ::R14D, &SystemZ::GR64BitRegClass);
2785 return DAG.getCopyFromReg(DAG.getEntryNode(), DL, LinkReg, PtrVT);
2788 SDValue SystemZTargetLowering::lowerBITCAST(SDValue Op,
2789 SelectionDAG &DAG) const {
2791 SDValue In = Op.getOperand(0);
2792 EVT InVT = In.getValueType();
2793 EVT ResVT = Op.getValueType();
2795 // Convert loads directly. This is normally done by DAGCombiner,
2796 // but we need this case for bitcasts that are created during lowering
2797 // and which are then lowered themselves.
2798 if (auto *LoadN = dyn_cast<LoadSDNode>(In))
2799 if (ISD::isNormalLoad(LoadN))
2800 return DAG.getLoad(ResVT, DL, LoadN->getChain(), LoadN->getBasePtr(),
2801 LoadN->getMemOperand());
2803 if (InVT == MVT::i32 && ResVT == MVT::f32) {
2805 if (Subtarget.hasHighWord()) {
2806 SDNode *U64 = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL,
2808 In64 = DAG.getTargetInsertSubreg(SystemZ::subreg_h32, DL,
2809 MVT::i64, SDValue(U64, 0), In);
2811 In64 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, In);
2812 In64 = DAG.getNode(ISD::SHL, DL, MVT::i64, In64,
2813 DAG.getConstant(32, DL, MVT::i64));
2815 SDValue Out64 = DAG.getNode(ISD::BITCAST, DL, MVT::f64, In64);
2816 return DAG.getTargetExtractSubreg(SystemZ::subreg_r32,
2817 DL, MVT::f32, Out64);
2819 if (InVT == MVT::f32 && ResVT == MVT::i32) {
2820 SDNode *U64 = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, MVT::f64);
2821 SDValue In64 = DAG.getTargetInsertSubreg(SystemZ::subreg_r32, DL,
2822 MVT::f64, SDValue(U64, 0), In);
2823 SDValue Out64 = DAG.getNode(ISD::BITCAST, DL, MVT::i64, In64);
2824 if (Subtarget.hasHighWord())
2825 return DAG.getTargetExtractSubreg(SystemZ::subreg_h32, DL,
2827 SDValue Shift = DAG.getNode(ISD::SRL, DL, MVT::i64, Out64,
2828 DAG.getConstant(32, DL, MVT::i64));
2829 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Shift);
2831 llvm_unreachable("Unexpected bitcast combination");
2834 SDValue SystemZTargetLowering::lowerVASTART(SDValue Op,
2835 SelectionDAG &DAG) const {
2836 MachineFunction &MF = DAG.getMachineFunction();
2837 SystemZMachineFunctionInfo *FuncInfo =
2838 MF.getInfo<SystemZMachineFunctionInfo>();
2839 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2841 SDValue Chain = Op.getOperand(0);
2842 SDValue Addr = Op.getOperand(1);
2843 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2846 // The initial values of each field.
2847 const unsigned NumFields = 4;
2848 SDValue Fields[NumFields] = {
2849 DAG.getConstant(FuncInfo->getVarArgsFirstGPR(), DL, PtrVT),
2850 DAG.getConstant(FuncInfo->getVarArgsFirstFPR(), DL, PtrVT),
2851 DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT),
2852 DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), PtrVT)
2855 // Store each field into its respective slot.
2856 SDValue MemOps[NumFields];
2857 unsigned Offset = 0;
2858 for (unsigned I = 0; I < NumFields; ++I) {
2859 SDValue FieldAddr = Addr;
2861 FieldAddr = DAG.getNode(ISD::ADD, DL, PtrVT, FieldAddr,
2862 DAG.getIntPtrConstant(Offset, DL));
2863 MemOps[I] = DAG.getStore(Chain, DL, Fields[I], FieldAddr,
2864 MachinePointerInfo(SV, Offset));
2867 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
2870 SDValue SystemZTargetLowering::lowerVACOPY(SDValue Op,
2871 SelectionDAG &DAG) const {
2872 SDValue Chain = Op.getOperand(0);
2873 SDValue DstPtr = Op.getOperand(1);
2874 SDValue SrcPtr = Op.getOperand(2);
2875 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
2876 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
2879 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr, DAG.getIntPtrConstant(32, DL),
2880 /*Align*/8, /*isVolatile*/false, /*AlwaysInline*/false,
2881 /*isTailCall*/false,
2882 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
2885 SDValue SystemZTargetLowering::
2886 lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const {
2887 const TargetFrameLowering *TFI = Subtarget.getFrameLowering();
2888 MachineFunction &MF = DAG.getMachineFunction();
2889 bool RealignOpt = !MF.getFunction()-> hasFnAttribute("no-realign-stack");
2890 bool StoreBackchain = MF.getFunction()->hasFnAttribute("backchain");
2892 SDValue Chain = Op.getOperand(0);
2893 SDValue Size = Op.getOperand(1);
2894 SDValue Align = Op.getOperand(2);
2897 // If user has set the no alignment function attribute, ignore
2898 // alloca alignments.
2899 uint64_t AlignVal = (RealignOpt ?
2900 dyn_cast<ConstantSDNode>(Align)->getZExtValue() : 0);
2902 uint64_t StackAlign = TFI->getStackAlignment();
2903 uint64_t RequiredAlign = std::max(AlignVal, StackAlign);
2904 uint64_t ExtraAlignSpace = RequiredAlign - StackAlign;
2906 unsigned SPReg = getStackPointerRegisterToSaveRestore();
2907 SDValue NeededSpace = Size;
2909 // Get a reference to the stack pointer.
2910 SDValue OldSP = DAG.getCopyFromReg(Chain, DL, SPReg, MVT::i64);
2912 // If we need a backchain, save it now.
2915 Backchain = DAG.getLoad(MVT::i64, DL, Chain, OldSP, MachinePointerInfo());
2917 // Add extra space for alignment if needed.
2918 if (ExtraAlignSpace)
2919 NeededSpace = DAG.getNode(ISD::ADD, DL, MVT::i64, NeededSpace,
2920 DAG.getConstant(ExtraAlignSpace, DL, MVT::i64));
2922 // Get the new stack pointer value.
2923 SDValue NewSP = DAG.getNode(ISD::SUB, DL, MVT::i64, OldSP, NeededSpace);
2925 // Copy the new stack pointer back.
2926 Chain = DAG.getCopyToReg(Chain, DL, SPReg, NewSP);
2928 // The allocated data lives above the 160 bytes allocated for the standard
2929 // frame, plus any outgoing stack arguments. We don't know how much that
2930 // amounts to yet, so emit a special ADJDYNALLOC placeholder.
2931 SDValue ArgAdjust = DAG.getNode(SystemZISD::ADJDYNALLOC, DL, MVT::i64);
2932 SDValue Result = DAG.getNode(ISD::ADD, DL, MVT::i64, NewSP, ArgAdjust);
2934 // Dynamically realign if needed.
2935 if (RequiredAlign > StackAlign) {
2937 DAG.getNode(ISD::ADD, DL, MVT::i64, Result,
2938 DAG.getConstant(ExtraAlignSpace, DL, MVT::i64));
2940 DAG.getNode(ISD::AND, DL, MVT::i64, Result,
2941 DAG.getConstant(~(RequiredAlign - 1), DL, MVT::i64));
2945 Chain = DAG.getStore(Chain, DL, Backchain, NewSP, MachinePointerInfo());
2947 SDValue Ops[2] = { Result, Chain };
2948 return DAG.getMergeValues(Ops, DL);
2951 SDValue SystemZTargetLowering::lowerGET_DYNAMIC_AREA_OFFSET(
2952 SDValue Op, SelectionDAG &DAG) const {
2955 return DAG.getNode(SystemZISD::ADJDYNALLOC, DL, MVT::i64);
2958 SDValue SystemZTargetLowering::lowerSMUL_LOHI(SDValue Op,
2959 SelectionDAG &DAG) const {
2960 EVT VT = Op.getValueType();
2964 // Just do a normal 64-bit multiplication and extract the results.
2965 // We define this so that it can be used for constant division.
2966 lowerMUL_LOHI32(DAG, DL, ISD::SIGN_EXTEND, Op.getOperand(0),
2967 Op.getOperand(1), Ops[1], Ops[0]);
2969 // Do a full 128-bit multiplication based on UMUL_LOHI64:
2971 // (ll * rl) + ((lh * rl) << 64) + ((ll * rh) << 64)
2973 // but using the fact that the upper halves are either all zeros
2976 // (ll * rl) - ((lh & rl) << 64) - ((ll & rh) << 64)
2978 // and grouping the right terms together since they are quicker than the
2981 // (ll * rl) - (((lh & rl) + (ll & rh)) << 64)
2982 SDValue C63 = DAG.getConstant(63, DL, MVT::i64);
2983 SDValue LL = Op.getOperand(0);
2984 SDValue RL = Op.getOperand(1);
2985 SDValue LH = DAG.getNode(ISD::SRA, DL, VT, LL, C63);
2986 SDValue RH = DAG.getNode(ISD::SRA, DL, VT, RL, C63);
2987 // UMUL_LOHI64 returns the low result in the odd register and the high
2988 // result in the even register. SMUL_LOHI is defined to return the
2989 // low half first, so the results are in reverse order.
2990 lowerGR128Binary(DAG, DL, VT, SystemZ::AEXT128_64, SystemZISD::UMUL_LOHI64,
2991 LL, RL, Ops[1], Ops[0]);
2992 SDValue NegLLTimesRH = DAG.getNode(ISD::AND, DL, VT, LL, RH);
2993 SDValue NegLHTimesRL = DAG.getNode(ISD::AND, DL, VT, LH, RL);
2994 SDValue NegSum = DAG.getNode(ISD::ADD, DL, VT, NegLLTimesRH, NegLHTimesRL);
2995 Ops[1] = DAG.getNode(ISD::SUB, DL, VT, Ops[1], NegSum);
2997 return DAG.getMergeValues(Ops, DL);
3000 SDValue SystemZTargetLowering::lowerUMUL_LOHI(SDValue Op,
3001 SelectionDAG &DAG) const {
3002 EVT VT = Op.getValueType();
3006 // Just do a normal 64-bit multiplication and extract the results.
3007 // We define this so that it can be used for constant division.
3008 lowerMUL_LOHI32(DAG, DL, ISD::ZERO_EXTEND, Op.getOperand(0),
3009 Op.getOperand(1), Ops[1], Ops[0]);
3011 // UMUL_LOHI64 returns the low result in the odd register and the high
3012 // result in the even register. UMUL_LOHI is defined to return the
3013 // low half first, so the results are in reverse order.
3014 lowerGR128Binary(DAG, DL, VT, SystemZ::AEXT128_64, SystemZISD::UMUL_LOHI64,
3015 Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
3016 return DAG.getMergeValues(Ops, DL);
3019 SDValue SystemZTargetLowering::lowerSDIVREM(SDValue Op,
3020 SelectionDAG &DAG) const {
3021 SDValue Op0 = Op.getOperand(0);
3022 SDValue Op1 = Op.getOperand(1);
3023 EVT VT = Op.getValueType();
3027 // We use DSGF for 32-bit division.
3029 Op0 = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i64, Op0);
3030 Opcode = SystemZISD::SDIVREM32;
3031 } else if (DAG.ComputeNumSignBits(Op1) > 32) {
3032 Op1 = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Op1);
3033 Opcode = SystemZISD::SDIVREM32;
3035 Opcode = SystemZISD::SDIVREM64;
3037 // DSG(F) takes a 64-bit dividend, so the even register in the GR128
3038 // input is "don't care". The instruction returns the remainder in
3039 // the even register and the quotient in the odd register.
3041 lowerGR128Binary(DAG, DL, VT, SystemZ::AEXT128_64, Opcode,
3042 Op0, Op1, Ops[1], Ops[0]);
3043 return DAG.getMergeValues(Ops, DL);
3046 SDValue SystemZTargetLowering::lowerUDIVREM(SDValue Op,
3047 SelectionDAG &DAG) const {
3048 EVT VT = Op.getValueType();
3051 // DL(G) uses a double-width dividend, so we need to clear the even
3052 // register in the GR128 input. The instruction returns the remainder
3053 // in the even register and the quotient in the odd register.
3056 lowerGR128Binary(DAG, DL, VT, SystemZ::ZEXT128_32, SystemZISD::UDIVREM32,
3057 Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
3059 lowerGR128Binary(DAG, DL, VT, SystemZ::ZEXT128_64, SystemZISD::UDIVREM64,
3060 Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
3061 return DAG.getMergeValues(Ops, DL);
3064 SDValue SystemZTargetLowering::lowerOR(SDValue Op, SelectionDAG &DAG) const {
3065 assert(Op.getValueType() == MVT::i64 && "Should be 64-bit operation");
3067 // Get the known-zero masks for each operand.
3068 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1) };
3069 APInt KnownZero[2], KnownOne[2];
3070 DAG.computeKnownBits(Ops[0], KnownZero[0], KnownOne[0]);
3071 DAG.computeKnownBits(Ops[1], KnownZero[1], KnownOne[1]);
3073 // See if the upper 32 bits of one operand and the lower 32 bits of the
3074 // other are known zero. They are the low and high operands respectively.
3075 uint64_t Masks[] = { KnownZero[0].getZExtValue(),
3076 KnownZero[1].getZExtValue() };
3078 if ((Masks[0] >> 32) == 0xffffffff && uint32_t(Masks[1]) == 0xffffffff)
3080 else if ((Masks[1] >> 32) == 0xffffffff && uint32_t(Masks[0]) == 0xffffffff)
3085 SDValue LowOp = Ops[Low];
3086 SDValue HighOp = Ops[High];
3088 // If the high part is a constant, we're better off using IILH.
3089 if (HighOp.getOpcode() == ISD::Constant)
3092 // If the low part is a constant that is outside the range of LHI,
3093 // then we're better off using IILF.
3094 if (LowOp.getOpcode() == ISD::Constant) {
3095 int64_t Value = int32_t(cast<ConstantSDNode>(LowOp)->getZExtValue());
3096 if (!isInt<16>(Value))
3100 // Check whether the high part is an AND that doesn't change the
3101 // high 32 bits and just masks out low bits. We can skip it if so.
3102 if (HighOp.getOpcode() == ISD::AND &&
3103 HighOp.getOperand(1).getOpcode() == ISD::Constant) {
3104 SDValue HighOp0 = HighOp.getOperand(0);
3105 uint64_t Mask = cast<ConstantSDNode>(HighOp.getOperand(1))->getZExtValue();
3106 if (DAG.MaskedValueIsZero(HighOp0, APInt(64, ~(Mask | 0xffffffff))))
3110 // Take advantage of the fact that all GR32 operations only change the
3111 // low 32 bits by truncating Low to an i32 and inserting it directly
3112 // using a subreg. The interesting cases are those where the truncation
3115 SDValue Low32 = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, LowOp);
3116 return DAG.getTargetInsertSubreg(SystemZ::subreg_l32, DL,
3117 MVT::i64, HighOp, Low32);
3120 SDValue SystemZTargetLowering::lowerCTPOP(SDValue Op,
3121 SelectionDAG &DAG) const {
3122 EVT VT = Op.getValueType();
3124 Op = Op.getOperand(0);
3126 // Handle vector types via VPOPCT.
3127 if (VT.isVector()) {
3128 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Op);
3129 Op = DAG.getNode(SystemZISD::POPCNT, DL, MVT::v16i8, Op);
3130 switch (VT.getScalarSizeInBits()) {
3134 Op = DAG.getNode(ISD::BITCAST, DL, VT, Op);
3135 SDValue Shift = DAG.getConstant(8, DL, MVT::i32);
3136 SDValue Tmp = DAG.getNode(SystemZISD::VSHL_BY_SCALAR, DL, VT, Op, Shift);
3137 Op = DAG.getNode(ISD::ADD, DL, VT, Op, Tmp);
3138 Op = DAG.getNode(SystemZISD::VSRL_BY_SCALAR, DL, VT, Op, Shift);
3142 SDValue Tmp = DAG.getNode(SystemZISD::BYTE_MASK, DL, MVT::v16i8,
3143 DAG.getConstant(0, DL, MVT::i32));
3144 Op = DAG.getNode(SystemZISD::VSUM, DL, VT, Op, Tmp);
3148 SDValue Tmp = DAG.getNode(SystemZISD::BYTE_MASK, DL, MVT::v16i8,
3149 DAG.getConstant(0, DL, MVT::i32));
3150 Op = DAG.getNode(SystemZISD::VSUM, DL, MVT::v4i32, Op, Tmp);
3151 Op = DAG.getNode(SystemZISD::VSUM, DL, VT, Op, Tmp);
3155 llvm_unreachable("Unexpected type");
3160 // Get the known-zero mask for the operand.
3161 APInt KnownZero, KnownOne;
3162 DAG.computeKnownBits(Op, KnownZero, KnownOne);
3163 unsigned NumSignificantBits = (~KnownZero).getActiveBits();
3164 if (NumSignificantBits == 0)
3165 return DAG.getConstant(0, DL, VT);
3167 // Skip known-zero high parts of the operand.
3168 int64_t OrigBitSize = VT.getSizeInBits();
3169 int64_t BitSize = (int64_t)1 << Log2_32_Ceil(NumSignificantBits);
3170 BitSize = std::min(BitSize, OrigBitSize);
3172 // The POPCNT instruction counts the number of bits in each byte.
3173 Op = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op);
3174 Op = DAG.getNode(SystemZISD::POPCNT, DL, MVT::i64, Op);
3175 Op = DAG.getNode(ISD::TRUNCATE, DL, VT, Op);
3177 // Add up per-byte counts in a binary tree. All bits of Op at
3178 // position larger than BitSize remain zero throughout.
3179 for (int64_t I = BitSize / 2; I >= 8; I = I / 2) {
3180 SDValue Tmp = DAG.getNode(ISD::SHL, DL, VT, Op, DAG.getConstant(I, DL, VT));
3181 if (BitSize != OrigBitSize)
3182 Tmp = DAG.getNode(ISD::AND, DL, VT, Tmp,
3183 DAG.getConstant(((uint64_t)1 << BitSize) - 1, DL, VT));
3184 Op = DAG.getNode(ISD::ADD, DL, VT, Op, Tmp);
3187 // Extract overall result from high byte.
3189 Op = DAG.getNode(ISD::SRL, DL, VT, Op,
3190 DAG.getConstant(BitSize - 8, DL, VT));
3195 SDValue SystemZTargetLowering::lowerATOMIC_FENCE(SDValue Op,
3196 SelectionDAG &DAG) const {
3198 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
3199 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
3200 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
3201 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
3203 // The only fence that needs an instruction is a sequentially-consistent
3204 // cross-thread fence.
3205 if (FenceOrdering == AtomicOrdering::SequentiallyConsistent &&
3206 FenceScope == CrossThread) {
3207 return SDValue(DAG.getMachineNode(SystemZ::Serialize, DL, MVT::Other,
3212 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
3213 return DAG.getNode(SystemZISD::MEMBARRIER, DL, MVT::Other, Op.getOperand(0));
3216 // Op is an atomic load. Lower it into a normal volatile load.
3217 SDValue SystemZTargetLowering::lowerATOMIC_LOAD(SDValue Op,
3218 SelectionDAG &DAG) const {
3219 auto *Node = cast<AtomicSDNode>(Op.getNode());
3220 return DAG.getExtLoad(ISD::EXTLOAD, SDLoc(Op), Op.getValueType(),
3221 Node->getChain(), Node->getBasePtr(),
3222 Node->getMemoryVT(), Node->getMemOperand());
3225 // Op is an atomic store. Lower it into a normal volatile store followed
3226 // by a serialization.
3227 SDValue SystemZTargetLowering::lowerATOMIC_STORE(SDValue Op,
3228 SelectionDAG &DAG) const {
3229 auto *Node = cast<AtomicSDNode>(Op.getNode());
3230 SDValue Chain = DAG.getTruncStore(Node->getChain(), SDLoc(Op), Node->getVal(),
3231 Node->getBasePtr(), Node->getMemoryVT(),
3232 Node->getMemOperand());
3233 return SDValue(DAG.getMachineNode(SystemZ::Serialize, SDLoc(Op), MVT::Other,
3237 // Op is an 8-, 16-bit or 32-bit ATOMIC_LOAD_* operation. Lower the first
3238 // two into the fullword ATOMIC_LOADW_* operation given by Opcode.
3239 SDValue SystemZTargetLowering::lowerATOMIC_LOAD_OP(SDValue Op,
3241 unsigned Opcode) const {
3242 auto *Node = cast<AtomicSDNode>(Op.getNode());
3244 // 32-bit operations need no code outside the main loop.
3245 EVT NarrowVT = Node->getMemoryVT();
3246 EVT WideVT = MVT::i32;
3247 if (NarrowVT == WideVT)
3250 int64_t BitSize = NarrowVT.getSizeInBits();
3251 SDValue ChainIn = Node->getChain();
3252 SDValue Addr = Node->getBasePtr();
3253 SDValue Src2 = Node->getVal();
3254 MachineMemOperand *MMO = Node->getMemOperand();
3256 EVT PtrVT = Addr.getValueType();
3258 // Convert atomic subtracts of constants into additions.
3259 if (Opcode == SystemZISD::ATOMIC_LOADW_SUB)
3260 if (auto *Const = dyn_cast<ConstantSDNode>(Src2)) {
3261 Opcode = SystemZISD::ATOMIC_LOADW_ADD;
3262 Src2 = DAG.getConstant(-Const->getSExtValue(), DL, Src2.getValueType());
3265 // Get the address of the containing word.
3266 SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr,
3267 DAG.getConstant(-4, DL, PtrVT));
3269 // Get the number of bits that the word must be rotated left in order
3270 // to bring the field to the top bits of a GR32.
3271 SDValue BitShift = DAG.getNode(ISD::SHL, DL, PtrVT, Addr,
3272 DAG.getConstant(3, DL, PtrVT));
3273 BitShift = DAG.getNode(ISD::TRUNCATE, DL, WideVT, BitShift);
3275 // Get the complementing shift amount, for rotating a field in the top
3276 // bits back to its proper position.
3277 SDValue NegBitShift = DAG.getNode(ISD::SUB, DL, WideVT,
3278 DAG.getConstant(0, DL, WideVT), BitShift);
3280 // Extend the source operand to 32 bits and prepare it for the inner loop.
3281 // ATOMIC_SWAPW uses RISBG to rotate the field left, but all other
3282 // operations require the source to be shifted in advance. (This shift
3283 // can be folded if the source is constant.) For AND and NAND, the lower
3284 // bits must be set, while for other opcodes they should be left clear.
3285 if (Opcode != SystemZISD::ATOMIC_SWAPW)
3286 Src2 = DAG.getNode(ISD::SHL, DL, WideVT, Src2,
3287 DAG.getConstant(32 - BitSize, DL, WideVT));
3288 if (Opcode == SystemZISD::ATOMIC_LOADW_AND ||
3289 Opcode == SystemZISD::ATOMIC_LOADW_NAND)
3290 Src2 = DAG.getNode(ISD::OR, DL, WideVT, Src2,
3291 DAG.getConstant(uint32_t(-1) >> BitSize, DL, WideVT));
3293 // Construct the ATOMIC_LOADW_* node.
3294 SDVTList VTList = DAG.getVTList(WideVT, MVT::Other);
3295 SDValue Ops[] = { ChainIn, AlignedAddr, Src2, BitShift, NegBitShift,
3296 DAG.getConstant(BitSize, DL, WideVT) };
3297 SDValue AtomicOp = DAG.getMemIntrinsicNode(Opcode, DL, VTList, Ops,
3300 // Rotate the result of the final CS so that the field is in the lower
3301 // bits of a GR32, then truncate it.
3302 SDValue ResultShift = DAG.getNode(ISD::ADD, DL, WideVT, BitShift,
3303 DAG.getConstant(BitSize, DL, WideVT));
3304 SDValue Result = DAG.getNode(ISD::ROTL, DL, WideVT, AtomicOp, ResultShift);
3306 SDValue RetOps[2] = { Result, AtomicOp.getValue(1) };
3307 return DAG.getMergeValues(RetOps, DL);
3310 // Op is an ATOMIC_LOAD_SUB operation. Lower 8- and 16-bit operations
3311 // into ATOMIC_LOADW_SUBs and decide whether to convert 32- and 64-bit
3312 // operations into additions.
3313 SDValue SystemZTargetLowering::lowerATOMIC_LOAD_SUB(SDValue Op,
3314 SelectionDAG &DAG) const {
3315 auto *Node = cast<AtomicSDNode>(Op.getNode());
3316 EVT MemVT = Node->getMemoryVT();
3317 if (MemVT == MVT::i32 || MemVT == MVT::i64) {
3318 // A full-width operation.
3319 assert(Op.getValueType() == MemVT && "Mismatched VTs");
3320 SDValue Src2 = Node->getVal();
3324 if (auto *Op2 = dyn_cast<ConstantSDNode>(Src2)) {
3325 // Use an addition if the operand is constant and either LAA(G) is
3326 // available or the negative value is in the range of A(G)FHI.
3327 int64_t Value = (-Op2->getAPIntValue()).getSExtValue();
3328 if (isInt<32>(Value) || Subtarget.hasInterlockedAccess1())
3329 NegSrc2 = DAG.getConstant(Value, DL, MemVT);
3330 } else if (Subtarget.hasInterlockedAccess1())
3331 // Use LAA(G) if available.
3332 NegSrc2 = DAG.getNode(ISD::SUB, DL, MemVT, DAG.getConstant(0, DL, MemVT),
3335 if (NegSrc2.getNode())
3336 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, DL, MemVT,
3337 Node->getChain(), Node->getBasePtr(), NegSrc2,
3338 Node->getMemOperand());
3340 // Use the node as-is.
3344 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_SUB);
3347 // Node is an 8- or 16-bit ATOMIC_CMP_SWAP operation. Lower the first two
3348 // into a fullword ATOMIC_CMP_SWAPW operation.
3349 SDValue SystemZTargetLowering::lowerATOMIC_CMP_SWAP(SDValue Op,
3350 SelectionDAG &DAG) const {
3351 auto *Node = cast<AtomicSDNode>(Op.getNode());
3353 // We have native support for 32-bit compare and swap.
3354 EVT NarrowVT = Node->getMemoryVT();
3355 EVT WideVT = MVT::i32;
3356 if (NarrowVT == WideVT)
3359 int64_t BitSize = NarrowVT.getSizeInBits();
3360 SDValue ChainIn = Node->getOperand(0);
3361 SDValue Addr = Node->getOperand(1);
3362 SDValue CmpVal = Node->getOperand(2);
3363 SDValue SwapVal = Node->getOperand(3);
3364 MachineMemOperand *MMO = Node->getMemOperand();
3366 EVT PtrVT = Addr.getValueType();
3368 // Get the address of the containing word.
3369 SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr,
3370 DAG.getConstant(-4, DL, PtrVT));
3372 // Get the number of bits that the word must be rotated left in order
3373 // to bring the field to the top bits of a GR32.
3374 SDValue BitShift = DAG.getNode(ISD::SHL, DL, PtrVT, Addr,
3375 DAG.getConstant(3, DL, PtrVT));
3376 BitShift = DAG.getNode(ISD::TRUNCATE, DL, WideVT, BitShift);
3378 // Get the complementing shift amount, for rotating a field in the top
3379 // bits back to its proper position.
3380 SDValue NegBitShift = DAG.getNode(ISD::SUB, DL, WideVT,
3381 DAG.getConstant(0, DL, WideVT), BitShift);
3383 // Construct the ATOMIC_CMP_SWAPW node.
3384 SDVTList VTList = DAG.getVTList(WideVT, MVT::Other);
3385 SDValue Ops[] = { ChainIn, AlignedAddr, CmpVal, SwapVal, BitShift,
3386 NegBitShift, DAG.getConstant(BitSize, DL, WideVT) };
3387 SDValue AtomicOp = DAG.getMemIntrinsicNode(SystemZISD::ATOMIC_CMP_SWAPW, DL,
3388 VTList, Ops, NarrowVT, MMO);
3392 SDValue SystemZTargetLowering::lowerSTACKSAVE(SDValue Op,
3393 SelectionDAG &DAG) const {
3394 MachineFunction &MF = DAG.getMachineFunction();
3395 MF.getInfo<SystemZMachineFunctionInfo>()->setManipulatesSP(true);
3396 return DAG.getCopyFromReg(Op.getOperand(0), SDLoc(Op),
3397 SystemZ::R15D, Op.getValueType());
3400 SDValue SystemZTargetLowering::lowerSTACKRESTORE(SDValue Op,
3401 SelectionDAG &DAG) const {
3402 MachineFunction &MF = DAG.getMachineFunction();
3403 MF.getInfo<SystemZMachineFunctionInfo>()->setManipulatesSP(true);
3404 bool StoreBackchain = MF.getFunction()->hasFnAttribute("backchain");
3406 SDValue Chain = Op.getOperand(0);
3407 SDValue NewSP = Op.getOperand(1);
3411 if (StoreBackchain) {
3412 SDValue OldSP = DAG.getCopyFromReg(Chain, DL, SystemZ::R15D, MVT::i64);
3413 Backchain = DAG.getLoad(MVT::i64, DL, Chain, OldSP, MachinePointerInfo());
3416 Chain = DAG.getCopyToReg(Chain, DL, SystemZ::R15D, NewSP);
3419 Chain = DAG.getStore(Chain, DL, Backchain, NewSP, MachinePointerInfo());
3424 SDValue SystemZTargetLowering::lowerPREFETCH(SDValue Op,
3425 SelectionDAG &DAG) const {
3426 bool IsData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
3428 // Just preserve the chain.
3429 return Op.getOperand(0);
3432 bool IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
3433 unsigned Code = IsWrite ? SystemZ::PFD_WRITE : SystemZ::PFD_READ;
3434 auto *Node = cast<MemIntrinsicSDNode>(Op.getNode());
3437 DAG.getConstant(Code, DL, MVT::i32),
3440 return DAG.getMemIntrinsicNode(SystemZISD::PREFETCH, DL,
3441 Node->getVTList(), Ops,
3442 Node->getMemoryVT(), Node->getMemOperand());
3445 // Return an i32 that contains the value of CC immediately after After,
3446 // whose final operand must be MVT::Glue.
3447 static SDValue getCCResult(SelectionDAG &DAG, SDNode *After) {
3449 SDValue Glue = SDValue(After, After->getNumValues() - 1);
3450 SDValue IPM = DAG.getNode(SystemZISD::IPM, DL, MVT::i32, Glue);
3451 return DAG.getNode(ISD::SRL, DL, MVT::i32, IPM,
3452 DAG.getConstant(SystemZ::IPM_CC, DL, MVT::i32));
3456 SystemZTargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op,
3457 SelectionDAG &DAG) const {
3458 unsigned Opcode, CCValid;
3459 if (isIntrinsicWithCCAndChain(Op, Opcode, CCValid)) {
3460 assert(Op->getNumValues() == 2 && "Expected only CC result and chain");
3461 SDValue Glued = emitIntrinsicWithChainAndGlue(DAG, Op, Opcode);
3462 SDValue CC = getCCResult(DAG, Glued.getNode());
3463 DAG.ReplaceAllUsesOfValueWith(SDValue(Op.getNode(), 0), CC);
3471 SystemZTargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
3472 SelectionDAG &DAG) const {
3473 unsigned Opcode, CCValid;
3474 if (isIntrinsicWithCC(Op, Opcode, CCValid)) {
3475 SDValue Glued = emitIntrinsicWithGlue(DAG, Op, Opcode);
3476 SDValue CC = getCCResult(DAG, Glued.getNode());
3477 if (Op->getNumValues() == 1)
3479 assert(Op->getNumValues() == 2 && "Expected a CC and non-CC result");
3480 return DAG.getNode(ISD::MERGE_VALUES, SDLoc(Op), Op->getVTList(), Glued,
3484 unsigned Id = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3486 case Intrinsic::thread_pointer:
3487 return lowerThreadPointer(SDLoc(Op), DAG);
3489 case Intrinsic::s390_vpdi:
3490 return DAG.getNode(SystemZISD::PERMUTE_DWORDS, SDLoc(Op), Op.getValueType(),
3491 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
3493 case Intrinsic::s390_vperm:
3494 return DAG.getNode(SystemZISD::PERMUTE, SDLoc(Op), Op.getValueType(),
3495 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
3497 case Intrinsic::s390_vuphb:
3498 case Intrinsic::s390_vuphh:
3499 case Intrinsic::s390_vuphf:
3500 return DAG.getNode(SystemZISD::UNPACK_HIGH, SDLoc(Op), Op.getValueType(),
3503 case Intrinsic::s390_vuplhb:
3504 case Intrinsic::s390_vuplhh:
3505 case Intrinsic::s390_vuplhf:
3506 return DAG.getNode(SystemZISD::UNPACKL_HIGH, SDLoc(Op), Op.getValueType(),
3509 case Intrinsic::s390_vuplb:
3510 case Intrinsic::s390_vuplhw:
3511 case Intrinsic::s390_vuplf:
3512 return DAG.getNode(SystemZISD::UNPACK_LOW, SDLoc(Op), Op.getValueType(),
3515 case Intrinsic::s390_vupllb:
3516 case Intrinsic::s390_vupllh:
3517 case Intrinsic::s390_vupllf:
3518 return DAG.getNode(SystemZISD::UNPACKL_LOW, SDLoc(Op), Op.getValueType(),
3521 case Intrinsic::s390_vsumb:
3522 case Intrinsic::s390_vsumh:
3523 case Intrinsic::s390_vsumgh:
3524 case Intrinsic::s390_vsumgf:
3525 case Intrinsic::s390_vsumqf:
3526 case Intrinsic::s390_vsumqg:
3527 return DAG.getNode(SystemZISD::VSUM, SDLoc(Op), Op.getValueType(),
3528 Op.getOperand(1), Op.getOperand(2));
3535 // Says that SystemZISD operation Opcode can be used to perform the equivalent
3536 // of a VPERM with permute vector Bytes. If Opcode takes three operands,
3537 // Operand is the constant third operand, otherwise it is the number of
3538 // bytes in each element of the result.
3542 unsigned char Bytes[SystemZ::VectorBytes];
3546 static const Permute PermuteForms[] = {
3548 { SystemZISD::MERGE_HIGH, 8,
3549 { 0, 1, 2, 3, 4, 5, 6, 7, 16, 17, 18, 19, 20, 21, 22, 23 } },
3551 { SystemZISD::MERGE_HIGH, 4,
3552 { 0, 1, 2, 3, 16, 17, 18, 19, 4, 5, 6, 7, 20, 21, 22, 23 } },
3554 { SystemZISD::MERGE_HIGH, 2,
3555 { 0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23 } },
3557 { SystemZISD::MERGE_HIGH, 1,
3558 { 0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23 } },
3560 { SystemZISD::MERGE_LOW, 8,
3561 { 8, 9, 10, 11, 12, 13, 14, 15, 24, 25, 26, 27, 28, 29, 30, 31 } },
3563 { SystemZISD::MERGE_LOW, 4,
3564 { 8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31 } },
3566 { SystemZISD::MERGE_LOW, 2,
3567 { 8, 9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, 30, 31 } },
3569 { SystemZISD::MERGE_LOW, 1,
3570 { 8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31 } },
3572 { SystemZISD::PACK, 4,
3573 { 4, 5, 6, 7, 12, 13, 14, 15, 20, 21, 22, 23, 28, 29, 30, 31 } },
3575 { SystemZISD::PACK, 2,
3576 { 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31 } },
3578 { SystemZISD::PACK, 1,
3579 { 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 } },
3580 // VPDI V1, V2, 4 (low half of V1, high half of V2)
3581 { SystemZISD::PERMUTE_DWORDS, 4,
3582 { 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 } },
3583 // VPDI V1, V2, 1 (high half of V1, low half of V2)
3584 { SystemZISD::PERMUTE_DWORDS, 1,
3585 { 0, 1, 2, 3, 4, 5, 6, 7, 24, 25, 26, 27, 28, 29, 30, 31 } }
3588 // Called after matching a vector shuffle against a particular pattern.
3589 // Both the original shuffle and the pattern have two vector operands.
3590 // OpNos[0] is the operand of the original shuffle that should be used for
3591 // operand 0 of the pattern, or -1 if operand 0 of the pattern can be anything.
3592 // OpNos[1] is the same for operand 1 of the pattern. Resolve these -1s and
3593 // set OpNo0 and OpNo1 to the shuffle operands that should actually be used
3594 // for operands 0 and 1 of the pattern.
3595 static bool chooseShuffleOpNos(int *OpNos, unsigned &OpNo0, unsigned &OpNo1) {
3599 OpNo0 = OpNo1 = OpNos[1];
3600 } else if (OpNos[1] < 0) {
3601 OpNo0 = OpNo1 = OpNos[0];
3609 // Bytes is a VPERM-like permute vector, except that -1 is used for
3610 // undefined bytes. Return true if the VPERM can be implemented using P.
3611 // When returning true set OpNo0 to the VPERM operand that should be
3612 // used for operand 0 of P and likewise OpNo1 for operand 1 of P.
3614 // For example, if swapping the VPERM operands allows P to match, OpNo0
3615 // will be 1 and OpNo1 will be 0. If instead Bytes only refers to one
3616 // operand, but rewriting it to use two duplicated operands allows it to
3617 // match P, then OpNo0 and OpNo1 will be the same.
3618 static bool matchPermute(const SmallVectorImpl<int> &Bytes, const Permute &P,
3619 unsigned &OpNo0, unsigned &OpNo1) {
3620 int OpNos[] = { -1, -1 };
3621 for (unsigned I = 0; I < SystemZ::VectorBytes; ++I) {
3624 // Make sure that the two permute vectors use the same suboperand
3625 // byte number. Only the operand numbers (the high bits) are
3626 // allowed to differ.
3627 if ((Elt ^ P.Bytes[I]) & (SystemZ::VectorBytes - 1))
3629 int ModelOpNo = P.Bytes[I] / SystemZ::VectorBytes;
3630 int RealOpNo = unsigned(Elt) / SystemZ::VectorBytes;
3631 // Make sure that the operand mappings are consistent with previous
3633 if (OpNos[ModelOpNo] == 1 - RealOpNo)
3635 OpNos[ModelOpNo] = RealOpNo;
3638 return chooseShuffleOpNos(OpNos, OpNo0, OpNo1);
3641 // As above, but search for a matching permute.
3642 static const Permute *matchPermute(const SmallVectorImpl<int> &Bytes,
3643 unsigned &OpNo0, unsigned &OpNo1) {
3644 for (auto &P : PermuteForms)
3645 if (matchPermute(Bytes, P, OpNo0, OpNo1))
3650 // Bytes is a VPERM-like permute vector, except that -1 is used for
3651 // undefined bytes. This permute is an operand of an outer permute.
3652 // See whether redistributing the -1 bytes gives a shuffle that can be
3653 // implemented using P. If so, set Transform to a VPERM-like permute vector
3654 // that, when applied to the result of P, gives the original permute in Bytes.
3655 static bool matchDoublePermute(const SmallVectorImpl<int> &Bytes,
3657 SmallVectorImpl<int> &Transform) {
3659 for (unsigned From = 0; From < SystemZ::VectorBytes; ++From) {
3660 int Elt = Bytes[From];
3662 // Byte number From of the result is undefined.
3663 Transform[From] = -1;
3665 while (P.Bytes[To] != Elt) {
3667 if (To == SystemZ::VectorBytes)
3670 Transform[From] = To;
3676 // As above, but search for a matching permute.
3677 static const Permute *matchDoublePermute(const SmallVectorImpl<int> &Bytes,
3678 SmallVectorImpl<int> &Transform) {
3679 for (auto &P : PermuteForms)
3680 if (matchDoublePermute(Bytes, P, Transform))
3685 // Convert the mask of the given VECTOR_SHUFFLE into a byte-level mask,
3686 // as if it had type vNi8.
3687 static void getVPermMask(ShuffleVectorSDNode *VSN,
3688 SmallVectorImpl<int> &Bytes) {
3689 EVT VT = VSN->getValueType(0);
3690 unsigned NumElements = VT.getVectorNumElements();
3691 unsigned BytesPerElement = VT.getVectorElementType().getStoreSize();
3692 Bytes.resize(NumElements * BytesPerElement, -1);
3693 for (unsigned I = 0; I < NumElements; ++I) {
3694 int Index = VSN->getMaskElt(I);
3696 for (unsigned J = 0; J < BytesPerElement; ++J)
3697 Bytes[I * BytesPerElement + J] = Index * BytesPerElement + J;
3701 // Bytes is a VPERM-like permute vector, except that -1 is used for
3702 // undefined bytes. See whether bytes [Start, Start + BytesPerElement) of
3703 // the result come from a contiguous sequence of bytes from one input.
3704 // Set Base to the selector for the first byte if so.
3705 static bool getShuffleInput(const SmallVectorImpl<int> &Bytes, unsigned Start,
3706 unsigned BytesPerElement, int &Base) {
3708 for (unsigned I = 0; I < BytesPerElement; ++I) {
3709 if (Bytes[Start + I] >= 0) {
3710 unsigned Elem = Bytes[Start + I];
3713 // Make sure the bytes would come from one input operand.
3714 if (unsigned(Base) % Bytes.size() + BytesPerElement > Bytes.size())
3716 } else if (unsigned(Base) != Elem - I)
3723 // Bytes is a VPERM-like permute vector, except that -1 is used for
3724 // undefined bytes. Return true if it can be performed using VSLDI.
3725 // When returning true, set StartIndex to the shift amount and OpNo0
3726 // and OpNo1 to the VPERM operands that should be used as the first
3727 // and second shift operand respectively.
3728 static bool isShlDoublePermute(const SmallVectorImpl<int> &Bytes,
3729 unsigned &StartIndex, unsigned &OpNo0,
3731 int OpNos[] = { -1, -1 };
3733 for (unsigned I = 0; I < 16; ++I) {
3734 int Index = Bytes[I];
3736 int ExpectedShift = (Index - I) % SystemZ::VectorBytes;
3737 int ModelOpNo = unsigned(ExpectedShift + I) / SystemZ::VectorBytes;
3738 int RealOpNo = unsigned(Index) / SystemZ::VectorBytes;
3740 Shift = ExpectedShift;
3741 else if (Shift != ExpectedShift)
3743 // Make sure that the operand mappings are consistent with previous
3745 if (OpNos[ModelOpNo] == 1 - RealOpNo)
3747 OpNos[ModelOpNo] = RealOpNo;
3751 return chooseShuffleOpNos(OpNos, OpNo0, OpNo1);
3754 // Create a node that performs P on operands Op0 and Op1, casting the
3755 // operands to the appropriate type. The type of the result is determined by P.
3756 static SDValue getPermuteNode(SelectionDAG &DAG, const SDLoc &DL,
3757 const Permute &P, SDValue Op0, SDValue Op1) {
3758 // VPDI (PERMUTE_DWORDS) always operates on v2i64s. The input
3759 // elements of a PACK are twice as wide as the outputs.
3760 unsigned InBytes = (P.Opcode == SystemZISD::PERMUTE_DWORDS ? 8 :
3761 P.Opcode == SystemZISD::PACK ? P.Operand * 2 :
3763 // Cast both operands to the appropriate type.
3764 MVT InVT = MVT::getVectorVT(MVT::getIntegerVT(InBytes * 8),
3765 SystemZ::VectorBytes / InBytes);
3766 Op0 = DAG.getNode(ISD::BITCAST, DL, InVT, Op0);
3767 Op1 = DAG.getNode(ISD::BITCAST, DL, InVT, Op1);
3769 if (P.Opcode == SystemZISD::PERMUTE_DWORDS) {
3770 SDValue Op2 = DAG.getConstant(P.Operand, DL, MVT::i32);
3771 Op = DAG.getNode(SystemZISD::PERMUTE_DWORDS, DL, InVT, Op0, Op1, Op2);
3772 } else if (P.Opcode == SystemZISD::PACK) {
3773 MVT OutVT = MVT::getVectorVT(MVT::getIntegerVT(P.Operand * 8),
3774 SystemZ::VectorBytes / P.Operand);
3775 Op = DAG.getNode(SystemZISD::PACK, DL, OutVT, Op0, Op1);
3777 Op = DAG.getNode(P.Opcode, DL, InVT, Op0, Op1);
3782 // Bytes is a VPERM-like permute vector, except that -1 is used for
3783 // undefined bytes. Implement it on operands Ops[0] and Ops[1] using
3785 static SDValue getGeneralPermuteNode(SelectionDAG &DAG, const SDLoc &DL,
3787 const SmallVectorImpl<int> &Bytes) {
3788 for (unsigned I = 0; I < 2; ++I)
3789 Ops[I] = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Ops[I]);
3791 // First see whether VSLDI can be used.
3792 unsigned StartIndex, OpNo0, OpNo1;
3793 if (isShlDoublePermute(Bytes, StartIndex, OpNo0, OpNo1))
3794 return DAG.getNode(SystemZISD::SHL_DOUBLE, DL, MVT::v16i8, Ops[OpNo0],
3795 Ops[OpNo1], DAG.getConstant(StartIndex, DL, MVT::i32));
3797 // Fall back on VPERM. Construct an SDNode for the permute vector.
3798 SDValue IndexNodes[SystemZ::VectorBytes];
3799 for (unsigned I = 0; I < SystemZ::VectorBytes; ++I)
3801 IndexNodes[I] = DAG.getConstant(Bytes[I], DL, MVT::i32);
3803 IndexNodes[I] = DAG.getUNDEF(MVT::i32);
3804 SDValue Op2 = DAG.getBuildVector(MVT::v16i8, DL, IndexNodes);
3805 return DAG.getNode(SystemZISD::PERMUTE, DL, MVT::v16i8, Ops[0], Ops[1], Op2);
3809 // Describes a general N-operand vector shuffle.
3810 struct GeneralShuffle {
3811 GeneralShuffle(EVT vt) : VT(vt) {}
3813 bool add(SDValue, unsigned);
3814 SDValue getNode(SelectionDAG &, const SDLoc &);
3816 // The operands of the shuffle.
3817 SmallVector<SDValue, SystemZ::VectorBytes> Ops;
3819 // Index I is -1 if byte I of the result is undefined. Otherwise the
3820 // result comes from byte Bytes[I] % SystemZ::VectorBytes of operand
3821 // Bytes[I] / SystemZ::VectorBytes.
3822 SmallVector<int, SystemZ::VectorBytes> Bytes;
3824 // The type of the shuffle result.
3829 // Add an extra undefined element to the shuffle.
3830 void GeneralShuffle::addUndef() {
3831 unsigned BytesPerElement = VT.getVectorElementType().getStoreSize();
3832 for (unsigned I = 0; I < BytesPerElement; ++I)
3833 Bytes.push_back(-1);
3836 // Add an extra element to the shuffle, taking it from element Elem of Op.
3837 // A null Op indicates a vector input whose value will be calculated later;
3838 // there is at most one such input per shuffle and it always has the same
3839 // type as the result. Aborts and returns false if the source vector elements
3840 // of an EXTRACT_VECTOR_ELT are smaller than the destination elements. Per
3841 // LLVM they become implicitly extended, but this is rare and not optimized.
3842 bool GeneralShuffle::add(SDValue Op, unsigned Elem) {
3843 unsigned BytesPerElement = VT.getVectorElementType().getStoreSize();
3845 // The source vector can have wider elements than the result,
3846 // either through an explicit TRUNCATE or because of type legalization.
3847 // We want the least significant part.
3848 EVT FromVT = Op.getNode() ? Op.getValueType() : VT;
3849 unsigned FromBytesPerElement = FromVT.getVectorElementType().getStoreSize();
3851 // Return false if the source elements are smaller than their destination
3853 if (FromBytesPerElement < BytesPerElement)
3856 unsigned Byte = ((Elem * FromBytesPerElement) % SystemZ::VectorBytes +
3857 (FromBytesPerElement - BytesPerElement));
3859 // Look through things like shuffles and bitcasts.
3860 while (Op.getNode()) {
3861 if (Op.getOpcode() == ISD::BITCAST)
3862 Op = Op.getOperand(0);
3863 else if (Op.getOpcode() == ISD::VECTOR_SHUFFLE && Op.hasOneUse()) {
3864 // See whether the bytes we need come from a contiguous part of one
3866 SmallVector<int, SystemZ::VectorBytes> OpBytes;
3867 getVPermMask(cast<ShuffleVectorSDNode>(Op), OpBytes);
3869 if (!getShuffleInput(OpBytes, Byte, BytesPerElement, NewByte))
3875 Op = Op.getOperand(unsigned(NewByte) / SystemZ::VectorBytes);
3876 Byte = unsigned(NewByte) % SystemZ::VectorBytes;
3877 } else if (Op.isUndef()) {
3884 // Make sure that the source of the extraction is in Ops.
3886 for (; OpNo < Ops.size(); ++OpNo)
3887 if (Ops[OpNo] == Op)
3889 if (OpNo == Ops.size())
3892 // Add the element to Bytes.
3893 unsigned Base = OpNo * SystemZ::VectorBytes + Byte;
3894 for (unsigned I = 0; I < BytesPerElement; ++I)
3895 Bytes.push_back(Base + I);
3900 // Return SDNodes for the completed shuffle.
3901 SDValue GeneralShuffle::getNode(SelectionDAG &DAG, const SDLoc &DL) {
3902 assert(Bytes.size() == SystemZ::VectorBytes && "Incomplete vector");
3904 if (Ops.size() == 0)
3905 return DAG.getUNDEF(VT);
3907 // Make sure that there are at least two shuffle operands.
3908 if (Ops.size() == 1)
3909 Ops.push_back(DAG.getUNDEF(MVT::v16i8));
3911 // Create a tree of shuffles, deferring root node until after the loop.
3912 // Try to redistribute the undefined elements of non-root nodes so that
3913 // the non-root shuffles match something like a pack or merge, then adjust
3914 // the parent node's permute vector to compensate for the new order.
3915 // Among other things, this copes with vectors like <2 x i16> that were
3916 // padded with undefined elements during type legalization.
3918 // In the best case this redistribution will lead to the whole tree
3919 // using packs and merges. It should rarely be a loss in other cases.
3920 unsigned Stride = 1;
3921 for (; Stride * 2 < Ops.size(); Stride *= 2) {
3922 for (unsigned I = 0; I < Ops.size() - Stride; I += Stride * 2) {
3923 SDValue SubOps[] = { Ops[I], Ops[I + Stride] };
3925 // Create a mask for just these two operands.
3926 SmallVector<int, SystemZ::VectorBytes> NewBytes(SystemZ::VectorBytes);
3927 for (unsigned J = 0; J < SystemZ::VectorBytes; ++J) {
3928 unsigned OpNo = unsigned(Bytes[J]) / SystemZ::VectorBytes;
3929 unsigned Byte = unsigned(Bytes[J]) % SystemZ::VectorBytes;
3932 else if (OpNo == I + Stride)
3933 NewBytes[J] = SystemZ::VectorBytes + Byte;
3937 // See if it would be better to reorganize NewMask to avoid using VPERM.
3938 SmallVector<int, SystemZ::VectorBytes> NewBytesMap(SystemZ::VectorBytes);
3939 if (const Permute *P = matchDoublePermute(NewBytes, NewBytesMap)) {
3940 Ops[I] = getPermuteNode(DAG, DL, *P, SubOps[0], SubOps[1]);
3941 // Applying NewBytesMap to Ops[I] gets back to NewBytes.
3942 for (unsigned J = 0; J < SystemZ::VectorBytes; ++J) {
3943 if (NewBytes[J] >= 0) {
3944 assert(unsigned(NewBytesMap[J]) < SystemZ::VectorBytes &&
3945 "Invalid double permute");
3946 Bytes[J] = I * SystemZ::VectorBytes + NewBytesMap[J];
3948 assert(NewBytesMap[J] < 0 && "Invalid double permute");
3951 // Just use NewBytes on the operands.
3952 Ops[I] = getGeneralPermuteNode(DAG, DL, SubOps, NewBytes);
3953 for (unsigned J = 0; J < SystemZ::VectorBytes; ++J)
3954 if (NewBytes[J] >= 0)
3955 Bytes[J] = I * SystemZ::VectorBytes + J;
3960 // Now we just have 2 inputs. Put the second operand in Ops[1].
3962 Ops[1] = Ops[Stride];
3963 for (unsigned I = 0; I < SystemZ::VectorBytes; ++I)
3964 if (Bytes[I] >= int(SystemZ::VectorBytes))
3965 Bytes[I] -= (Stride - 1) * SystemZ::VectorBytes;
3968 // Look for an instruction that can do the permute without resorting
3970 unsigned OpNo0, OpNo1;
3972 if (const Permute *P = matchPermute(Bytes, OpNo0, OpNo1))
3973 Op = getPermuteNode(DAG, DL, *P, Ops[OpNo0], Ops[OpNo1]);
3975 Op = getGeneralPermuteNode(DAG, DL, &Ops[0], Bytes);
3976 return DAG.getNode(ISD::BITCAST, DL, VT, Op);
3979 // Return true if the given BUILD_VECTOR is a scalar-to-vector conversion.
3980 static bool isScalarToVector(SDValue Op) {
3981 for (unsigned I = 1, E = Op.getNumOperands(); I != E; ++I)
3982 if (!Op.getOperand(I).isUndef())
3987 // Return a vector of type VT that contains Value in the first element.
3988 // The other elements don't matter.
3989 static SDValue buildScalarToVector(SelectionDAG &DAG, const SDLoc &DL, EVT VT,
3991 // If we have a constant, replicate it to all elements and let the
3992 // BUILD_VECTOR lowering take care of it.
3993 if (Value.getOpcode() == ISD::Constant ||
3994 Value.getOpcode() == ISD::ConstantFP) {
3995 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Value);
3996 return DAG.getBuildVector(VT, DL, Ops);
3998 if (Value.isUndef())
3999 return DAG.getUNDEF(VT);
4000 return DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VT, Value);
4003 // Return a vector of type VT in which Op0 is in element 0 and Op1 is in
4004 // element 1. Used for cases in which replication is cheap.
4005 static SDValue buildMergeScalars(SelectionDAG &DAG, const SDLoc &DL, EVT VT,
4006 SDValue Op0, SDValue Op1) {
4007 if (Op0.isUndef()) {
4009 return DAG.getUNDEF(VT);
4010 return DAG.getNode(SystemZISD::REPLICATE, DL, VT, Op1);
4013 return DAG.getNode(SystemZISD::REPLICATE, DL, VT, Op0);
4014 return DAG.getNode(SystemZISD::MERGE_HIGH, DL, VT,
4015 buildScalarToVector(DAG, DL, VT, Op0),
4016 buildScalarToVector(DAG, DL, VT, Op1));
4019 // Extend GPR scalars Op0 and Op1 to doublewords and return a v2i64
4021 static SDValue joinDwords(SelectionDAG &DAG, const SDLoc &DL, SDValue Op0,
4023 if (Op0.isUndef() && Op1.isUndef())
4024 return DAG.getUNDEF(MVT::v2i64);
4025 // If one of the two inputs is undefined then replicate the other one,
4026 // in order to avoid using another register unnecessarily.
4028 Op0 = Op1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op1);
4029 else if (Op1.isUndef())
4030 Op0 = Op1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op0);
4032 Op0 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op0);
4033 Op1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op1);
4035 return DAG.getNode(SystemZISD::JOIN_DWORDS, DL, MVT::v2i64, Op0, Op1);
4038 // Try to represent constant BUILD_VECTOR node BVN using a
4039 // SystemZISD::BYTE_MASK-style mask. Store the mask value in Mask
4041 static bool tryBuildVectorByteMask(BuildVectorSDNode *BVN, uint64_t &Mask) {
4042 EVT ElemVT = BVN->getValueType(0).getVectorElementType();
4043 unsigned BytesPerElement = ElemVT.getStoreSize();
4044 for (unsigned I = 0, E = BVN->getNumOperands(); I != E; ++I) {
4045 SDValue Op = BVN->getOperand(I);
4046 if (!Op.isUndef()) {
4048 if (Op.getOpcode() == ISD::Constant)
4049 Value = dyn_cast<ConstantSDNode>(Op)->getZExtValue();
4050 else if (Op.getOpcode() == ISD::ConstantFP)
4051 Value = (dyn_cast<ConstantFPSDNode>(Op)->getValueAPF().bitcastToAPInt()
4055 for (unsigned J = 0; J < BytesPerElement; ++J) {
4056 uint64_t Byte = (Value >> (J * 8)) & 0xff;
4058 Mask |= 1ULL << ((E - I - 1) * BytesPerElement + J);
4067 // Try to load a vector constant in which BitsPerElement-bit value Value
4068 // is replicated to fill the vector. VT is the type of the resulting
4069 // constant, which may have elements of a different size from BitsPerElement.
4070 // Return the SDValue of the constant on success, otherwise return
4072 static SDValue tryBuildVectorReplicate(SelectionDAG &DAG,
4073 const SystemZInstrInfo *TII,
4074 const SDLoc &DL, EVT VT, uint64_t Value,
4075 unsigned BitsPerElement) {
4076 // Signed 16-bit values can be replicated using VREPI.
4077 int64_t SignedValue = SignExtend64(Value, BitsPerElement);
4078 if (isInt<16>(SignedValue)) {
4079 MVT VecVT = MVT::getVectorVT(MVT::getIntegerVT(BitsPerElement),
4080 SystemZ::VectorBits / BitsPerElement);
4081 SDValue Op = DAG.getNode(SystemZISD::REPLICATE, DL, VecVT,
4082 DAG.getConstant(SignedValue, DL, MVT::i32));
4083 return DAG.getNode(ISD::BITCAST, DL, VT, Op);
4085 // See whether rotating the constant left some N places gives a value that
4086 // is one less than a power of 2 (i.e. all zeros followed by all ones).
4087 // If so we can use VGM.
4088 unsigned Start, End;
4089 if (TII->isRxSBGMask(Value, BitsPerElement, Start, End)) {
4090 // isRxSBGMask returns the bit numbers for a full 64-bit value,
4091 // with 0 denoting 1 << 63 and 63 denoting 1. Convert them to
4092 // bit numbers for an BitsPerElement value, so that 0 denotes
4093 // 1 << (BitsPerElement-1).
4094 Start -= 64 - BitsPerElement;
4095 End -= 64 - BitsPerElement;
4096 MVT VecVT = MVT::getVectorVT(MVT::getIntegerVT(BitsPerElement),
4097 SystemZ::VectorBits / BitsPerElement);
4098 SDValue Op = DAG.getNode(SystemZISD::ROTATE_MASK, DL, VecVT,
4099 DAG.getConstant(Start, DL, MVT::i32),
4100 DAG.getConstant(End, DL, MVT::i32));
4101 return DAG.getNode(ISD::BITCAST, DL, VT, Op);
4106 // If a BUILD_VECTOR contains some EXTRACT_VECTOR_ELTs, it's usually
4107 // better to use VECTOR_SHUFFLEs on them, only using BUILD_VECTOR for
4108 // the non-EXTRACT_VECTOR_ELT elements. See if the given BUILD_VECTOR
4109 // would benefit from this representation and return it if so.
4110 static SDValue tryBuildVectorShuffle(SelectionDAG &DAG,
4111 BuildVectorSDNode *BVN) {
4112 EVT VT = BVN->getValueType(0);
4113 unsigned NumElements = VT.getVectorNumElements();
4115 // Represent the BUILD_VECTOR as an N-operand VECTOR_SHUFFLE-like operation
4116 // on byte vectors. If there are non-EXTRACT_VECTOR_ELT elements that still
4117 // need a BUILD_VECTOR, add an additional placeholder operand for that
4118 // BUILD_VECTOR and store its operands in ResidueOps.
4119 GeneralShuffle GS(VT);
4120 SmallVector<SDValue, SystemZ::VectorBytes> ResidueOps;
4121 bool FoundOne = false;
4122 for (unsigned I = 0; I < NumElements; ++I) {
4123 SDValue Op = BVN->getOperand(I);
4124 if (Op.getOpcode() == ISD::TRUNCATE)
4125 Op = Op.getOperand(0);
4126 if (Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
4127 Op.getOperand(1).getOpcode() == ISD::Constant) {
4128 unsigned Elem = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4129 if (!GS.add(Op.getOperand(0), Elem))
4132 } else if (Op.isUndef()) {
4135 if (!GS.add(SDValue(), ResidueOps.size()))
4137 ResidueOps.push_back(BVN->getOperand(I));
4141 // Nothing to do if there are no EXTRACT_VECTOR_ELTs.
4145 // Create the BUILD_VECTOR for the remaining elements, if any.
4146 if (!ResidueOps.empty()) {
4147 while (ResidueOps.size() < NumElements)
4148 ResidueOps.push_back(DAG.getUNDEF(ResidueOps[0].getValueType()));
4149 for (auto &Op : GS.Ops) {
4150 if (!Op.getNode()) {
4151 Op = DAG.getBuildVector(VT, SDLoc(BVN), ResidueOps);
4156 return GS.getNode(DAG, SDLoc(BVN));
4159 // Combine GPR scalar values Elems into a vector of type VT.
4160 static SDValue buildVector(SelectionDAG &DAG, const SDLoc &DL, EVT VT,
4161 SmallVectorImpl<SDValue> &Elems) {
4162 // See whether there is a single replicated value.
4164 unsigned int NumElements = Elems.size();
4165 unsigned int Count = 0;
4166 for (auto Elem : Elems) {
4167 if (!Elem.isUndef()) {
4168 if (!Single.getNode())
4170 else if (Elem != Single) {
4177 // There are three cases here:
4179 // - if the only defined element is a loaded one, the best sequence
4180 // is a replicating load.
4182 // - otherwise, if the only defined element is an i64 value, we will
4183 // end up with the same VLVGP sequence regardless of whether we short-cut
4184 // for replication or fall through to the later code.
4186 // - otherwise, if the only defined element is an i32 or smaller value,
4187 // we would need 2 instructions to replicate it: VLVGP followed by VREPx.
4188 // This is only a win if the single defined element is used more than once.
4189 // In other cases we're better off using a single VLVGx.
4190 if (Single.getNode() && (Count > 1 || Single.getOpcode() == ISD::LOAD))
4191 return DAG.getNode(SystemZISD::REPLICATE, DL, VT, Single);
4193 // The best way of building a v2i64 from two i64s is to use VLVGP.
4194 if (VT == MVT::v2i64)
4195 return joinDwords(DAG, DL, Elems[0], Elems[1]);
4197 // Use a 64-bit merge high to combine two doubles.
4198 if (VT == MVT::v2f64)
4199 return buildMergeScalars(DAG, DL, VT, Elems[0], Elems[1]);
4201 // Build v4f32 values directly from the FPRs:
4203 // <Axxx> <Bxxx> <Cxxxx> <Dxxx>
4208 if (VT == MVT::v4f32) {
4209 SDValue Op01 = buildMergeScalars(DAG, DL, VT, Elems[0], Elems[1]);
4210 SDValue Op23 = buildMergeScalars(DAG, DL, VT, Elems[2], Elems[3]);
4211 // Avoid unnecessary undefs by reusing the other operand.
4214 else if (Op23.isUndef())
4216 // Merging identical replications is a no-op.
4217 if (Op01.getOpcode() == SystemZISD::REPLICATE && Op01 == Op23)
4219 Op01 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Op01);
4220 Op23 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Op23);
4221 SDValue Op = DAG.getNode(SystemZISD::MERGE_HIGH,
4222 DL, MVT::v2i64, Op01, Op23);
4223 return DAG.getNode(ISD::BITCAST, DL, VT, Op);
4226 // Collect the constant terms.
4227 SmallVector<SDValue, SystemZ::VectorBytes> Constants(NumElements, SDValue());
4228 SmallVector<bool, SystemZ::VectorBytes> Done(NumElements, false);
4230 unsigned NumConstants = 0;
4231 for (unsigned I = 0; I < NumElements; ++I) {
4232 SDValue Elem = Elems[I];
4233 if (Elem.getOpcode() == ISD::Constant ||
4234 Elem.getOpcode() == ISD::ConstantFP) {
4236 Constants[I] = Elem;
4240 // If there was at least one constant, fill in the other elements of
4241 // Constants with undefs to get a full vector constant and use that
4242 // as the starting point.
4244 if (NumConstants > 0) {
4245 for (unsigned I = 0; I < NumElements; ++I)
4246 if (!Constants[I].getNode())
4247 Constants[I] = DAG.getUNDEF(Elems[I].getValueType());
4248 Result = DAG.getBuildVector(VT, DL, Constants);
4250 // Otherwise try to use VLVGP to start the sequence in order to
4251 // avoid a false dependency on any previous contents of the vector
4252 // register. This only makes sense if one of the associated elements
4254 unsigned I1 = NumElements / 2 - 1;
4255 unsigned I2 = NumElements - 1;
4256 bool Def1 = !Elems[I1].isUndef();
4257 bool Def2 = !Elems[I2].isUndef();
4259 SDValue Elem1 = Elems[Def1 ? I1 : I2];
4260 SDValue Elem2 = Elems[Def2 ? I2 : I1];
4261 Result = DAG.getNode(ISD::BITCAST, DL, VT,
4262 joinDwords(DAG, DL, Elem1, Elem2));
4266 Result = DAG.getUNDEF(VT);
4269 // Use VLVGx to insert the other elements.
4270 for (unsigned I = 0; I < NumElements; ++I)
4271 if (!Done[I] && !Elems[I].isUndef())
4272 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, Result, Elems[I],
4273 DAG.getConstant(I, DL, MVT::i32));
4277 SDValue SystemZTargetLowering::lowerBUILD_VECTOR(SDValue Op,
4278 SelectionDAG &DAG) const {
4279 const SystemZInstrInfo *TII =
4280 static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
4281 auto *BVN = cast<BuildVectorSDNode>(Op.getNode());
4283 EVT VT = Op.getValueType();
4285 if (BVN->isConstant()) {
4286 // Try using VECTOR GENERATE BYTE MASK. This is the architecturally-
4287 // preferred way of creating all-zero and all-one vectors so give it
4288 // priority over other methods below.
4290 if (tryBuildVectorByteMask(BVN, Mask)) {
4291 SDValue Op = DAG.getNode(SystemZISD::BYTE_MASK, DL, MVT::v16i8,
4292 DAG.getConstant(Mask, DL, MVT::i32));
4293 return DAG.getNode(ISD::BITCAST, DL, VT, Op);
4296 // Try using some form of replication.
4297 APInt SplatBits, SplatUndef;
4298 unsigned SplatBitSize;
4300 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs,
4302 SplatBitSize <= 64) {
4303 // First try assuming that any undefined bits above the highest set bit
4304 // and below the lowest set bit are 1s. This increases the likelihood of
4305 // being able to use a sign-extended element value in VECTOR REPLICATE
4306 // IMMEDIATE or a wraparound mask in VECTOR GENERATE MASK.
4307 uint64_t SplatBitsZ = SplatBits.getZExtValue();
4308 uint64_t SplatUndefZ = SplatUndef.getZExtValue();
4309 uint64_t Lower = (SplatUndefZ
4310 & ((uint64_t(1) << findFirstSet(SplatBitsZ)) - 1));
4311 uint64_t Upper = (SplatUndefZ
4312 & ~((uint64_t(1) << findLastSet(SplatBitsZ)) - 1));
4313 uint64_t Value = SplatBitsZ | Upper | Lower;
4314 SDValue Op = tryBuildVectorReplicate(DAG, TII, DL, VT, Value,
4319 // Now try assuming that any undefined bits between the first and
4320 // last defined set bits are set. This increases the chances of
4321 // using a non-wraparound mask.
4322 uint64_t Middle = SplatUndefZ & ~Upper & ~Lower;
4323 Value = SplatBitsZ | Middle;
4324 Op = tryBuildVectorReplicate(DAG, TII, DL, VT, Value, SplatBitSize);
4329 // Fall back to loading it from memory.
4333 // See if we should use shuffles to construct the vector from other vectors.
4334 if (SDValue Res = tryBuildVectorShuffle(DAG, BVN))
4337 // Detect SCALAR_TO_VECTOR conversions.
4338 if (isOperationLegal(ISD::SCALAR_TO_VECTOR, VT) && isScalarToVector(Op))
4339 return buildScalarToVector(DAG, DL, VT, Op.getOperand(0));
4341 // Otherwise use buildVector to build the vector up from GPRs.
4342 unsigned NumElements = Op.getNumOperands();
4343 SmallVector<SDValue, SystemZ::VectorBytes> Ops(NumElements);
4344 for (unsigned I = 0; I < NumElements; ++I)
4345 Ops[I] = Op.getOperand(I);
4346 return buildVector(DAG, DL, VT, Ops);
4349 SDValue SystemZTargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,
4350 SelectionDAG &DAG) const {
4351 auto *VSN = cast<ShuffleVectorSDNode>(Op.getNode());
4353 EVT VT = Op.getValueType();
4354 unsigned NumElements = VT.getVectorNumElements();
4356 if (VSN->isSplat()) {
4357 SDValue Op0 = Op.getOperand(0);
4358 unsigned Index = VSN->getSplatIndex();
4359 assert(Index < VT.getVectorNumElements() &&
4360 "Splat index should be defined and in first operand");
4361 // See whether the value we're splatting is directly available as a scalar.
4362 if ((Index == 0 && Op0.getOpcode() == ISD::SCALAR_TO_VECTOR) ||
4363 Op0.getOpcode() == ISD::BUILD_VECTOR)
4364 return DAG.getNode(SystemZISD::REPLICATE, DL, VT, Op0.getOperand(Index));
4365 // Otherwise keep it as a vector-to-vector operation.
4366 return DAG.getNode(SystemZISD::SPLAT, DL, VT, Op.getOperand(0),
4367 DAG.getConstant(Index, DL, MVT::i32));
4370 GeneralShuffle GS(VT);
4371 for (unsigned I = 0; I < NumElements; ++I) {
4372 int Elt = VSN->getMaskElt(I);
4375 else if (!GS.add(Op.getOperand(unsigned(Elt) / NumElements),
4376 unsigned(Elt) % NumElements))
4379 return GS.getNode(DAG, SDLoc(VSN));
4382 SDValue SystemZTargetLowering::lowerSCALAR_TO_VECTOR(SDValue Op,
4383 SelectionDAG &DAG) const {
4385 // Just insert the scalar into element 0 of an undefined vector.
4386 return DAG.getNode(ISD::INSERT_VECTOR_ELT, DL,
4387 Op.getValueType(), DAG.getUNDEF(Op.getValueType()),
4388 Op.getOperand(0), DAG.getConstant(0, DL, MVT::i32));
4391 SDValue SystemZTargetLowering::lowerINSERT_VECTOR_ELT(SDValue Op,
4392 SelectionDAG &DAG) const {
4393 // Handle insertions of floating-point values.
4395 SDValue Op0 = Op.getOperand(0);
4396 SDValue Op1 = Op.getOperand(1);
4397 SDValue Op2 = Op.getOperand(2);
4398 EVT VT = Op.getValueType();
4400 // Insertions into constant indices of a v2f64 can be done using VPDI.
4401 // However, if the inserted value is a bitcast or a constant then it's
4402 // better to use GPRs, as below.
4403 if (VT == MVT::v2f64 &&
4404 Op1.getOpcode() != ISD::BITCAST &&
4405 Op1.getOpcode() != ISD::ConstantFP &&
4406 Op2.getOpcode() == ISD::Constant) {
4407 uint64_t Index = dyn_cast<ConstantSDNode>(Op2)->getZExtValue();
4408 unsigned Mask = VT.getVectorNumElements() - 1;
4413 // Otherwise bitcast to the equivalent integer form and insert via a GPR.
4414 MVT IntVT = MVT::getIntegerVT(VT.getScalarSizeInBits());
4415 MVT IntVecVT = MVT::getVectorVT(IntVT, VT.getVectorNumElements());
4416 SDValue Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, IntVecVT,
4417 DAG.getNode(ISD::BITCAST, DL, IntVecVT, Op0),
4418 DAG.getNode(ISD::BITCAST, DL, IntVT, Op1), Op2);
4419 return DAG.getNode(ISD::BITCAST, DL, VT, Res);
4423 SystemZTargetLowering::lowerEXTRACT_VECTOR_ELT(SDValue Op,
4424 SelectionDAG &DAG) const {
4425 // Handle extractions of floating-point values.
4427 SDValue Op0 = Op.getOperand(0);
4428 SDValue Op1 = Op.getOperand(1);
4429 EVT VT = Op.getValueType();
4430 EVT VecVT = Op0.getValueType();
4432 // Extractions of constant indices can be done directly.
4433 if (auto *CIndexN = dyn_cast<ConstantSDNode>(Op1)) {
4434 uint64_t Index = CIndexN->getZExtValue();
4435 unsigned Mask = VecVT.getVectorNumElements() - 1;
4440 // Otherwise bitcast to the equivalent integer form and extract via a GPR.
4441 MVT IntVT = MVT::getIntegerVT(VT.getSizeInBits());
4442 MVT IntVecVT = MVT::getVectorVT(IntVT, VecVT.getVectorNumElements());
4443 SDValue Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, IntVT,
4444 DAG.getNode(ISD::BITCAST, DL, IntVecVT, Op0), Op1);
4445 return DAG.getNode(ISD::BITCAST, DL, VT, Res);
4449 SystemZTargetLowering::lowerExtendVectorInreg(SDValue Op, SelectionDAG &DAG,
4450 unsigned UnpackHigh) const {
4451 SDValue PackedOp = Op.getOperand(0);
4452 EVT OutVT = Op.getValueType();
4453 EVT InVT = PackedOp.getValueType();
4454 unsigned ToBits = OutVT.getScalarSizeInBits();
4455 unsigned FromBits = InVT.getScalarSizeInBits();
4458 EVT OutVT = MVT::getVectorVT(MVT::getIntegerVT(FromBits),
4459 SystemZ::VectorBits / FromBits);
4460 PackedOp = DAG.getNode(UnpackHigh, SDLoc(PackedOp), OutVT, PackedOp);
4461 } while (FromBits != ToBits);
4465 SDValue SystemZTargetLowering::lowerShift(SDValue Op, SelectionDAG &DAG,
4466 unsigned ByScalar) const {
4467 // Look for cases where a vector shift can use the *_BY_SCALAR form.
4468 SDValue Op0 = Op.getOperand(0);
4469 SDValue Op1 = Op.getOperand(1);
4471 EVT VT = Op.getValueType();
4472 unsigned ElemBitSize = VT.getScalarSizeInBits();
4474 // See whether the shift vector is a splat represented as BUILD_VECTOR.
4475 if (auto *BVN = dyn_cast<BuildVectorSDNode>(Op1)) {
4476 APInt SplatBits, SplatUndef;
4477 unsigned SplatBitSize;
4479 // Check for constant splats. Use ElemBitSize as the minimum element
4480 // width and reject splats that need wider elements.
4481 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs,
4482 ElemBitSize, true) &&
4483 SplatBitSize == ElemBitSize) {
4484 SDValue Shift = DAG.getConstant(SplatBits.getZExtValue() & 0xfff,
4486 return DAG.getNode(ByScalar, DL, VT, Op0, Shift);
4488 // Check for variable splats.
4489 BitVector UndefElements;
4490 SDValue Splat = BVN->getSplatValue(&UndefElements);
4492 // Since i32 is the smallest legal type, we either need a no-op
4494 SDValue Shift = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Splat);
4495 return DAG.getNode(ByScalar, DL, VT, Op0, Shift);
4499 // See whether the shift vector is a splat represented as SHUFFLE_VECTOR,
4500 // and the shift amount is directly available in a GPR.
4501 if (auto *VSN = dyn_cast<ShuffleVectorSDNode>(Op1)) {
4502 if (VSN->isSplat()) {
4503 SDValue VSNOp0 = VSN->getOperand(0);
4504 unsigned Index = VSN->getSplatIndex();
4505 assert(Index < VT.getVectorNumElements() &&
4506 "Splat index should be defined and in first operand");
4507 if ((Index == 0 && VSNOp0.getOpcode() == ISD::SCALAR_TO_VECTOR) ||
4508 VSNOp0.getOpcode() == ISD::BUILD_VECTOR) {
4509 // Since i32 is the smallest legal type, we either need a no-op
4511 SDValue Shift = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32,
4512 VSNOp0.getOperand(Index));
4513 return DAG.getNode(ByScalar, DL, VT, Op0, Shift);
4518 // Otherwise just treat the current form as legal.
4522 SDValue SystemZTargetLowering::LowerOperation(SDValue Op,
4523 SelectionDAG &DAG) const {
4524 switch (Op.getOpcode()) {
4525 case ISD::FRAMEADDR:
4526 return lowerFRAMEADDR(Op, DAG);
4527 case ISD::RETURNADDR:
4528 return lowerRETURNADDR(Op, DAG);
4530 return lowerBR_CC(Op, DAG);
4531 case ISD::SELECT_CC:
4532 return lowerSELECT_CC(Op, DAG);
4534 return lowerSETCC(Op, DAG);
4535 case ISD::GlobalAddress:
4536 return lowerGlobalAddress(cast<GlobalAddressSDNode>(Op), DAG);
4537 case ISD::GlobalTLSAddress:
4538 return lowerGlobalTLSAddress(cast<GlobalAddressSDNode>(Op), DAG);
4539 case ISD::BlockAddress:
4540 return lowerBlockAddress(cast<BlockAddressSDNode>(Op), DAG);
4541 case ISD::JumpTable:
4542 return lowerJumpTable(cast<JumpTableSDNode>(Op), DAG);
4543 case ISD::ConstantPool:
4544 return lowerConstantPool(cast<ConstantPoolSDNode>(Op), DAG);
4546 return lowerBITCAST(Op, DAG);
4548 return lowerVASTART(Op, DAG);
4550 return lowerVACOPY(Op, DAG);
4551 case ISD::DYNAMIC_STACKALLOC:
4552 return lowerDYNAMIC_STACKALLOC(Op, DAG);
4553 case ISD::GET_DYNAMIC_AREA_OFFSET:
4554 return lowerGET_DYNAMIC_AREA_OFFSET(Op, DAG);
4555 case ISD::SMUL_LOHI:
4556 return lowerSMUL_LOHI(Op, DAG);
4557 case ISD::UMUL_LOHI:
4558 return lowerUMUL_LOHI(Op, DAG);
4560 return lowerSDIVREM(Op, DAG);
4562 return lowerUDIVREM(Op, DAG);
4564 return lowerOR(Op, DAG);
4566 return lowerCTPOP(Op, DAG);
4567 case ISD::ATOMIC_FENCE:
4568 return lowerATOMIC_FENCE(Op, DAG);
4569 case ISD::ATOMIC_SWAP:
4570 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_SWAPW);
4571 case ISD::ATOMIC_STORE:
4572 return lowerATOMIC_STORE(Op, DAG);
4573 case ISD::ATOMIC_LOAD:
4574 return lowerATOMIC_LOAD(Op, DAG);
4575 case ISD::ATOMIC_LOAD_ADD:
4576 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_ADD);
4577 case ISD::ATOMIC_LOAD_SUB:
4578 return lowerATOMIC_LOAD_SUB(Op, DAG);
4579 case ISD::ATOMIC_LOAD_AND:
4580 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_AND);
4581 case ISD::ATOMIC_LOAD_OR:
4582 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_OR);
4583 case ISD::ATOMIC_LOAD_XOR:
4584 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_XOR);
4585 case ISD::ATOMIC_LOAD_NAND:
4586 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_NAND);
4587 case ISD::ATOMIC_LOAD_MIN:
4588 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_MIN);
4589 case ISD::ATOMIC_LOAD_MAX:
4590 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_MAX);
4591 case ISD::ATOMIC_LOAD_UMIN:
4592 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_UMIN);
4593 case ISD::ATOMIC_LOAD_UMAX:
4594 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_UMAX);
4595 case ISD::ATOMIC_CMP_SWAP:
4596 return lowerATOMIC_CMP_SWAP(Op, DAG);
4597 case ISD::STACKSAVE:
4598 return lowerSTACKSAVE(Op, DAG);
4599 case ISD::STACKRESTORE:
4600 return lowerSTACKRESTORE(Op, DAG);
4602 return lowerPREFETCH(Op, DAG);
4603 case ISD::INTRINSIC_W_CHAIN:
4604 return lowerINTRINSIC_W_CHAIN(Op, DAG);
4605 case ISD::INTRINSIC_WO_CHAIN:
4606 return lowerINTRINSIC_WO_CHAIN(Op, DAG);
4607 case ISD::BUILD_VECTOR:
4608 return lowerBUILD_VECTOR(Op, DAG);
4609 case ISD::VECTOR_SHUFFLE:
4610 return lowerVECTOR_SHUFFLE(Op, DAG);
4611 case ISD::SCALAR_TO_VECTOR:
4612 return lowerSCALAR_TO_VECTOR(Op, DAG);
4613 case ISD::INSERT_VECTOR_ELT:
4614 return lowerINSERT_VECTOR_ELT(Op, DAG);
4615 case ISD::EXTRACT_VECTOR_ELT:
4616 return lowerEXTRACT_VECTOR_ELT(Op, DAG);
4617 case ISD::SIGN_EXTEND_VECTOR_INREG:
4618 return lowerExtendVectorInreg(Op, DAG, SystemZISD::UNPACK_HIGH);
4619 case ISD::ZERO_EXTEND_VECTOR_INREG:
4620 return lowerExtendVectorInreg(Op, DAG, SystemZISD::UNPACKL_HIGH);
4622 return lowerShift(Op, DAG, SystemZISD::VSHL_BY_SCALAR);
4624 return lowerShift(Op, DAG, SystemZISD::VSRL_BY_SCALAR);
4626 return lowerShift(Op, DAG, SystemZISD::VSRA_BY_SCALAR);
4628 llvm_unreachable("Unexpected node to lower");
4632 const char *SystemZTargetLowering::getTargetNodeName(unsigned Opcode) const {
4633 #define OPCODE(NAME) case SystemZISD::NAME: return "SystemZISD::" #NAME
4634 switch ((SystemZISD::NodeType)Opcode) {
4635 case SystemZISD::FIRST_NUMBER: break;
4641 OPCODE(PCREL_WRAPPER);
4642 OPCODE(PCREL_OFFSET);
4648 OPCODE(SELECT_CCMASK);
4649 OPCODE(ADJDYNALLOC);
4651 OPCODE(UMUL_LOHI64);
4668 OPCODE(SEARCH_STRING);
4673 OPCODE(TBEGIN_NOFLOAT);
4676 OPCODE(ROTATE_MASK);
4678 OPCODE(JOIN_DWORDS);
4683 OPCODE(PERMUTE_DWORDS);
4688 OPCODE(UNPACK_HIGH);
4689 OPCODE(UNPACKL_HIGH);
4691 OPCODE(UNPACKL_LOW);
4692 OPCODE(VSHL_BY_SCALAR);
4693 OPCODE(VSRL_BY_SCALAR);
4694 OPCODE(VSRA_BY_SCALAR);
4722 OPCODE(ATOMIC_SWAPW);
4723 OPCODE(ATOMIC_LOADW_ADD);
4724 OPCODE(ATOMIC_LOADW_SUB);
4725 OPCODE(ATOMIC_LOADW_AND);
4726 OPCODE(ATOMIC_LOADW_OR);
4727 OPCODE(ATOMIC_LOADW_XOR);
4728 OPCODE(ATOMIC_LOADW_NAND);
4729 OPCODE(ATOMIC_LOADW_MIN);
4730 OPCODE(ATOMIC_LOADW_MAX);
4731 OPCODE(ATOMIC_LOADW_UMIN);
4732 OPCODE(ATOMIC_LOADW_UMAX);
4733 OPCODE(ATOMIC_CMP_SWAPW);
4742 // Return true if VT is a vector whose elements are a whole number of bytes
4743 // in width. Also check for presence of vector support.
4744 bool SystemZTargetLowering::canTreatAsByteVector(EVT VT) const {
4745 if (!Subtarget.hasVector())
4748 return VT.isVector() && VT.getScalarSizeInBits() % 8 == 0 && VT.isSimple();
4751 // Try to simplify an EXTRACT_VECTOR_ELT from a vector of type VecVT
4752 // producing a result of type ResVT. Op is a possibly bitcast version
4753 // of the input vector and Index is the index (based on type VecVT) that
4754 // should be extracted. Return the new extraction if a simplification
4755 // was possible or if Force is true.
4756 SDValue SystemZTargetLowering::combineExtract(const SDLoc &DL, EVT ResVT,
4757 EVT VecVT, SDValue Op,
4759 DAGCombinerInfo &DCI,
4761 SelectionDAG &DAG = DCI.DAG;
4763 // The number of bytes being extracted.
4764 unsigned BytesPerElement = VecVT.getVectorElementType().getStoreSize();
4767 unsigned Opcode = Op.getOpcode();
4768 if (Opcode == ISD::BITCAST)
4769 // Look through bitcasts.
4770 Op = Op.getOperand(0);
4771 else if (Opcode == ISD::VECTOR_SHUFFLE &&
4772 canTreatAsByteVector(Op.getValueType())) {
4773 // Get a VPERM-like permute mask and see whether the bytes covered
4774 // by the extracted element are a contiguous sequence from one
4776 SmallVector<int, SystemZ::VectorBytes> Bytes;
4777 getVPermMask(cast<ShuffleVectorSDNode>(Op), Bytes);
4779 if (!getShuffleInput(Bytes, Index * BytesPerElement,
4780 BytesPerElement, First))
4783 return DAG.getUNDEF(ResVT);
4784 // Make sure the contiguous sequence starts at a multiple of the
4785 // original element size.
4786 unsigned Byte = unsigned(First) % Bytes.size();
4787 if (Byte % BytesPerElement != 0)
4789 // We can get the extracted value directly from an input.
4790 Index = Byte / BytesPerElement;
4791 Op = Op.getOperand(unsigned(First) / Bytes.size());
4793 } else if (Opcode == ISD::BUILD_VECTOR &&
4794 canTreatAsByteVector(Op.getValueType())) {
4795 // We can only optimize this case if the BUILD_VECTOR elements are
4796 // at least as wide as the extracted value.
4797 EVT OpVT = Op.getValueType();
4798 unsigned OpBytesPerElement = OpVT.getVectorElementType().getStoreSize();
4799 if (OpBytesPerElement < BytesPerElement)
4801 // Make sure that the least-significant bit of the extracted value
4802 // is the least significant bit of an input.
4803 unsigned End = (Index + 1) * BytesPerElement;
4804 if (End % OpBytesPerElement != 0)
4806 // We're extracting the low part of one operand of the BUILD_VECTOR.
4807 Op = Op.getOperand(End / OpBytesPerElement - 1);
4808 if (!Op.getValueType().isInteger()) {
4809 EVT VT = MVT::getIntegerVT(Op.getValueSizeInBits());
4810 Op = DAG.getNode(ISD::BITCAST, DL, VT, Op);
4811 DCI.AddToWorklist(Op.getNode());
4813 EVT VT = MVT::getIntegerVT(ResVT.getSizeInBits());
4814 Op = DAG.getNode(ISD::TRUNCATE, DL, VT, Op);
4816 DCI.AddToWorklist(Op.getNode());
4817 Op = DAG.getNode(ISD::BITCAST, DL, ResVT, Op);
4820 } else if ((Opcode == ISD::SIGN_EXTEND_VECTOR_INREG ||
4821 Opcode == ISD::ZERO_EXTEND_VECTOR_INREG ||
4822 Opcode == ISD::ANY_EXTEND_VECTOR_INREG) &&
4823 canTreatAsByteVector(Op.getValueType()) &&
4824 canTreatAsByteVector(Op.getOperand(0).getValueType())) {
4825 // Make sure that only the unextended bits are significant.
4826 EVT ExtVT = Op.getValueType();
4827 EVT OpVT = Op.getOperand(0).getValueType();
4828 unsigned ExtBytesPerElement = ExtVT.getVectorElementType().getStoreSize();
4829 unsigned OpBytesPerElement = OpVT.getVectorElementType().getStoreSize();
4830 unsigned Byte = Index * BytesPerElement;
4831 unsigned SubByte = Byte % ExtBytesPerElement;
4832 unsigned MinSubByte = ExtBytesPerElement - OpBytesPerElement;
4833 if (SubByte < MinSubByte ||
4834 SubByte + BytesPerElement > ExtBytesPerElement)
4836 // Get the byte offset of the unextended element
4837 Byte = Byte / ExtBytesPerElement * OpBytesPerElement;
4838 // ...then add the byte offset relative to that element.
4839 Byte += SubByte - MinSubByte;
4840 if (Byte % BytesPerElement != 0)
4842 Op = Op.getOperand(0);
4843 Index = Byte / BytesPerElement;
4849 if (Op.getValueType() != VecVT) {
4850 Op = DAG.getNode(ISD::BITCAST, DL, VecVT, Op);
4851 DCI.AddToWorklist(Op.getNode());
4853 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ResVT, Op,
4854 DAG.getConstant(Index, DL, MVT::i32));
4859 // Optimize vector operations in scalar value Op on the basis that Op
4860 // is truncated to TruncVT.
4861 SDValue SystemZTargetLowering::combineTruncateExtract(
4862 const SDLoc &DL, EVT TruncVT, SDValue Op, DAGCombinerInfo &DCI) const {
4863 // If we have (trunc (extract_vector_elt X, Y)), try to turn it into
4864 // (extract_vector_elt (bitcast X), Y'), where (bitcast X) has elements
4866 if (Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
4867 TruncVT.getSizeInBits() % 8 == 0) {
4868 SDValue Vec = Op.getOperand(0);
4869 EVT VecVT = Vec.getValueType();
4870 if (canTreatAsByteVector(VecVT)) {
4871 if (auto *IndexN = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
4872 unsigned BytesPerElement = VecVT.getVectorElementType().getStoreSize();
4873 unsigned TruncBytes = TruncVT.getStoreSize();
4874 if (BytesPerElement % TruncBytes == 0) {
4875 // Calculate the value of Y' in the above description. We are
4876 // splitting the original elements into Scale equal-sized pieces
4877 // and for truncation purposes want the last (least-significant)
4878 // of these pieces for IndexN. This is easiest to do by calculating
4879 // the start index of the following element and then subtracting 1.
4880 unsigned Scale = BytesPerElement / TruncBytes;
4881 unsigned NewIndex = (IndexN->getZExtValue() + 1) * Scale - 1;
4883 // Defer the creation of the bitcast from X to combineExtract,
4884 // which might be able to optimize the extraction.
4885 VecVT = MVT::getVectorVT(MVT::getIntegerVT(TruncBytes * 8),
4886 VecVT.getStoreSize() / TruncBytes);
4887 EVT ResVT = (TruncBytes < 4 ? MVT::i32 : TruncVT);
4888 return combineExtract(DL, ResVT, VecVT, Vec, NewIndex, DCI, true);
4896 SDValue SystemZTargetLowering::combineSIGN_EXTEND(
4897 SDNode *N, DAGCombinerInfo &DCI) const {
4898 // Convert (sext (ashr (shl X, C1), C2)) to
4899 // (ashr (shl (anyext X), C1'), C2')), since wider shifts are as
4900 // cheap as narrower ones.
4901 SelectionDAG &DAG = DCI.DAG;
4902 SDValue N0 = N->getOperand(0);
4903 EVT VT = N->getValueType(0);
4904 if (N0.hasOneUse() && N0.getOpcode() == ISD::SRA) {
4905 auto *SraAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1));
4906 SDValue Inner = N0.getOperand(0);
4907 if (SraAmt && Inner.hasOneUse() && Inner.getOpcode() == ISD::SHL) {
4908 if (auto *ShlAmt = dyn_cast<ConstantSDNode>(Inner.getOperand(1))) {
4909 unsigned Extra = (VT.getSizeInBits() - N0.getValueSizeInBits());
4910 unsigned NewShlAmt = ShlAmt->getZExtValue() + Extra;
4911 unsigned NewSraAmt = SraAmt->getZExtValue() + Extra;
4912 EVT ShiftVT = N0.getOperand(1).getValueType();
4913 SDValue Ext = DAG.getNode(ISD::ANY_EXTEND, SDLoc(Inner), VT,
4914 Inner.getOperand(0));
4915 SDValue Shl = DAG.getNode(ISD::SHL, SDLoc(Inner), VT, Ext,
4916 DAG.getConstant(NewShlAmt, SDLoc(Inner),
4918 return DAG.getNode(ISD::SRA, SDLoc(N0), VT, Shl,
4919 DAG.getConstant(NewSraAmt, SDLoc(N0), ShiftVT));
4926 SDValue SystemZTargetLowering::combineMERGE(
4927 SDNode *N, DAGCombinerInfo &DCI) const {
4928 SelectionDAG &DAG = DCI.DAG;
4929 unsigned Opcode = N->getOpcode();
4930 SDValue Op0 = N->getOperand(0);
4931 SDValue Op1 = N->getOperand(1);
4932 if (Op0.getOpcode() == ISD::BITCAST)
4933 Op0 = Op0.getOperand(0);
4934 if (Op0.getOpcode() == SystemZISD::BYTE_MASK &&
4935 cast<ConstantSDNode>(Op0.getOperand(0))->getZExtValue() == 0) {
4936 // (z_merge_* 0, 0) -> 0. This is mostly useful for using VLLEZF
4938 if (Op1 == N->getOperand(0))
4940 // (z_merge_? 0, X) -> (z_unpackl_? 0, X).
4941 EVT VT = Op1.getValueType();
4942 unsigned ElemBytes = VT.getVectorElementType().getStoreSize();
4943 if (ElemBytes <= 4) {
4944 Opcode = (Opcode == SystemZISD::MERGE_HIGH ?
4945 SystemZISD::UNPACKL_HIGH : SystemZISD::UNPACKL_LOW);
4946 EVT InVT = VT.changeVectorElementTypeToInteger();
4947 EVT OutVT = MVT::getVectorVT(MVT::getIntegerVT(ElemBytes * 16),
4948 SystemZ::VectorBytes / ElemBytes / 2);
4950 Op1 = DAG.getNode(ISD::BITCAST, SDLoc(N), InVT, Op1);
4951 DCI.AddToWorklist(Op1.getNode());
4953 SDValue Op = DAG.getNode(Opcode, SDLoc(N), OutVT, Op1);
4954 DCI.AddToWorklist(Op.getNode());
4955 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
4961 SDValue SystemZTargetLowering::combineSTORE(
4962 SDNode *N, DAGCombinerInfo &DCI) const {
4963 SelectionDAG &DAG = DCI.DAG;
4964 auto *SN = cast<StoreSDNode>(N);
4965 auto &Op1 = N->getOperand(1);
4966 EVT MemVT = SN->getMemoryVT();
4967 // If we have (truncstoreiN (extract_vector_elt X, Y), Z) then it is better
4968 // for the extraction to be done on a vMiN value, so that we can use VSTE.
4969 // If X has wider elements then convert it to:
4970 // (truncstoreiN (extract_vector_elt (bitcast X), Y2), Z).
4971 if (MemVT.isInteger()) {
4973 combineTruncateExtract(SDLoc(N), MemVT, SN->getValue(), DCI)) {
4974 DCI.AddToWorklist(Value.getNode());
4976 // Rewrite the store with the new form of stored value.
4977 return DAG.getTruncStore(SN->getChain(), SDLoc(SN), Value,
4978 SN->getBasePtr(), SN->getMemoryVT(),
4979 SN->getMemOperand());
4982 // Combine STORE (BSWAP) into STRVH/STRV/STRVG
4983 // See comment in combineBSWAP about volatile accesses.
4984 if (!SN->isVolatile() &&
4985 Op1.getOpcode() == ISD::BSWAP &&
4986 Op1.getNode()->hasOneUse() &&
4987 (Op1.getValueType() == MVT::i16 ||
4988 Op1.getValueType() == MVT::i32 ||
4989 Op1.getValueType() == MVT::i64)) {
4991 SDValue BSwapOp = Op1.getOperand(0);
4993 if (BSwapOp.getValueType() == MVT::i16)
4994 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), MVT::i32, BSwapOp);
4997 N->getOperand(0), BSwapOp, N->getOperand(2),
4998 DAG.getValueType(Op1.getValueType())
5002 DAG.getMemIntrinsicNode(SystemZISD::STRV, SDLoc(N), DAG.getVTList(MVT::Other),
5003 Ops, MemVT, SN->getMemOperand());
5008 SDValue SystemZTargetLowering::combineEXTRACT_VECTOR_ELT(
5009 SDNode *N, DAGCombinerInfo &DCI) const {
5011 if (!Subtarget.hasVector())
5014 // Try to simplify a vector extraction.
5015 if (auto *IndexN = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
5016 SDValue Op0 = N->getOperand(0);
5017 EVT VecVT = Op0.getValueType();
5018 return combineExtract(SDLoc(N), N->getValueType(0), VecVT, Op0,
5019 IndexN->getZExtValue(), DCI, false);
5024 SDValue SystemZTargetLowering::combineJOIN_DWORDS(
5025 SDNode *N, DAGCombinerInfo &DCI) const {
5026 SelectionDAG &DAG = DCI.DAG;
5027 // (join_dwords X, X) == (replicate X)
5028 if (N->getOperand(0) == N->getOperand(1))
5029 return DAG.getNode(SystemZISD::REPLICATE, SDLoc(N), N->getValueType(0),
5034 SDValue SystemZTargetLowering::combineFP_ROUND(
5035 SDNode *N, DAGCombinerInfo &DCI) const {
5036 // (fpround (extract_vector_elt X 0))
5037 // (fpround (extract_vector_elt X 1)) ->
5038 // (extract_vector_elt (VROUND X) 0)
5039 // (extract_vector_elt (VROUND X) 1)
5041 // This is a special case since the target doesn't really support v2f32s.
5042 SelectionDAG &DAG = DCI.DAG;
5043 SDValue Op0 = N->getOperand(0);
5044 if (N->getValueType(0) == MVT::f32 &&
5046 Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5047 Op0.getOperand(0).getValueType() == MVT::v2f64 &&
5048 Op0.getOperand(1).getOpcode() == ISD::Constant &&
5049 cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue() == 0) {
5050 SDValue Vec = Op0.getOperand(0);
5051 for (auto *U : Vec->uses()) {
5052 if (U != Op0.getNode() &&
5054 U->getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5055 U->getOperand(0) == Vec &&
5056 U->getOperand(1).getOpcode() == ISD::Constant &&
5057 cast<ConstantSDNode>(U->getOperand(1))->getZExtValue() == 1) {
5058 SDValue OtherRound = SDValue(*U->use_begin(), 0);
5059 if (OtherRound.getOpcode() == ISD::FP_ROUND &&
5060 OtherRound.getOperand(0) == SDValue(U, 0) &&
5061 OtherRound.getValueType() == MVT::f32) {
5062 SDValue VRound = DAG.getNode(SystemZISD::VROUND, SDLoc(N),
5064 DCI.AddToWorklist(VRound.getNode());
5066 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(U), MVT::f32,
5067 VRound, DAG.getConstant(2, SDLoc(U), MVT::i32));
5068 DCI.AddToWorklist(Extract1.getNode());
5069 DAG.ReplaceAllUsesOfValueWith(OtherRound, Extract1);
5071 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op0), MVT::f32,
5072 VRound, DAG.getConstant(0, SDLoc(Op0), MVT::i32));
5081 SDValue SystemZTargetLowering::combineBSWAP(
5082 SDNode *N, DAGCombinerInfo &DCI) const {
5083 SelectionDAG &DAG = DCI.DAG;
5084 // Combine BSWAP (LOAD) into LRVH/LRV/LRVG
5085 // These loads are allowed to access memory multiple times, and so we must check
5086 // that the loads are not volatile before performing the combine.
5087 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
5088 N->getOperand(0).hasOneUse() &&
5089 (N->getValueType(0) == MVT::i16 || N->getValueType(0) == MVT::i32 ||
5090 N->getValueType(0) == MVT::i64) &&
5091 !cast<LoadSDNode>(N->getOperand(0))->isVolatile()) {
5092 SDValue Load = N->getOperand(0);
5093 LoadSDNode *LD = cast<LoadSDNode>(Load);
5095 // Create the byte-swapping load.
5097 LD->getChain(), // Chain
5098 LD->getBasePtr(), // Ptr
5099 DAG.getValueType(N->getValueType(0)) // VT
5102 DAG.getMemIntrinsicNode(SystemZISD::LRV, SDLoc(N),
5103 DAG.getVTList(N->getValueType(0) == MVT::i64 ?
5104 MVT::i64 : MVT::i32, MVT::Other),
5105 Ops, LD->getMemoryVT(), LD->getMemOperand());
5107 // If this is an i16 load, insert the truncate.
5108 SDValue ResVal = BSLoad;
5109 if (N->getValueType(0) == MVT::i16)
5110 ResVal = DAG.getNode(ISD::TRUNCATE, SDLoc(N), MVT::i16, BSLoad);
5112 // First, combine the bswap away. This makes the value produced by the
5114 DCI.CombineTo(N, ResVal);
5116 // Next, combine the load away, we give it a bogus result value but a real
5117 // chain result. The result value is dead because the bswap is dead.
5118 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
5120 // Return N so it doesn't get rechecked!
5121 return SDValue(N, 0);
5126 SDValue SystemZTargetLowering::combineSHIFTROT(
5127 SDNode *N, DAGCombinerInfo &DCI) const {
5129 SelectionDAG &DAG = DCI.DAG;
5131 // Shift/rotate instructions only use the last 6 bits of the second operand
5132 // register. If the second operand is the result of an AND with an immediate
5133 // value that has its last 6 bits set, we can safely remove the AND operation.
5135 // If the AND operation doesn't have the last 6 bits set, we can't remove it
5136 // entirely, but we can still truncate it to a 16-bit value. This prevents
5137 // us from ending up with a NILL with a signed operand, which will cause the
5138 // instruction printer to abort.
5139 SDValue N1 = N->getOperand(1);
5140 if (N1.getOpcode() == ISD::AND) {
5141 SDValue AndMaskOp = N1->getOperand(1);
5142 auto *AndMask = dyn_cast<ConstantSDNode>(AndMaskOp);
5144 // The AND mask is constant
5146 auto AmtVal = AndMask->getZExtValue();
5148 // Bottom 6 bits are set
5149 if ((AmtVal & 0x3f) == 0x3f) {
5150 SDValue AndOp = N1->getOperand(0);
5152 // This is the only use, so remove the node
5153 if (N1.hasOneUse()) {
5154 // Combine the AND away
5155 DCI.CombineTo(N1.getNode(), AndOp);
5157 // Return N so it isn't rechecked
5158 return SDValue(N, 0);
5160 // The node will be reused, so create a new node for this one use
5162 SDValue Replace = DAG.getNode(N->getOpcode(), SDLoc(N),
5163 N->getValueType(0), N->getOperand(0),
5165 DCI.AddToWorklist(Replace.getNode());
5170 // We can't remove the AND, but we can use NILL here (normally we would
5171 // use NILF). Only keep the last 16 bits of the mask. The actual
5172 // transformation will be handled by .td definitions.
5173 } else if (AmtVal >> 16 != 0) {
5174 SDValue AndOp = N1->getOperand(0);
5176 auto NewMask = DAG.getConstant(AndMask->getZExtValue() & 0x0000ffff,
5178 AndMaskOp.getValueType());
5180 auto NewAnd = DAG.getNode(N1.getOpcode(), SDLoc(N1), N1.getValueType(),
5183 SDValue Replace = DAG.getNode(N->getOpcode(), SDLoc(N),
5184 N->getValueType(0), N->getOperand(0),
5186 DCI.AddToWorklist(Replace.getNode());
5196 SDValue SystemZTargetLowering::PerformDAGCombine(SDNode *N,
5197 DAGCombinerInfo &DCI) const {
5198 switch(N->getOpcode()) {
5200 case ISD::SIGN_EXTEND: return combineSIGN_EXTEND(N, DCI);
5201 case SystemZISD::MERGE_HIGH:
5202 case SystemZISD::MERGE_LOW: return combineMERGE(N, DCI);
5203 case ISD::STORE: return combineSTORE(N, DCI);
5204 case ISD::EXTRACT_VECTOR_ELT: return combineEXTRACT_VECTOR_ELT(N, DCI);
5205 case SystemZISD::JOIN_DWORDS: return combineJOIN_DWORDS(N, DCI);
5206 case ISD::FP_ROUND: return combineFP_ROUND(N, DCI);
5207 case ISD::BSWAP: return combineBSWAP(N, DCI);
5211 case ISD::ROTL: return combineSHIFTROT(N, DCI);
5217 //===----------------------------------------------------------------------===//
5219 //===----------------------------------------------------------------------===//
5221 // Create a new basic block after MBB.
5222 static MachineBasicBlock *emitBlockAfter(MachineBasicBlock *MBB) {
5223 MachineFunction &MF = *MBB->getParent();
5224 MachineBasicBlock *NewMBB = MF.CreateMachineBasicBlock(MBB->getBasicBlock());
5225 MF.insert(std::next(MachineFunction::iterator(MBB)), NewMBB);
5229 // Split MBB after MI and return the new block (the one that contains
5230 // instructions after MI).
5231 static MachineBasicBlock *splitBlockAfter(MachineBasicBlock::iterator MI,
5232 MachineBasicBlock *MBB) {
5233 MachineBasicBlock *NewMBB = emitBlockAfter(MBB);
5234 NewMBB->splice(NewMBB->begin(), MBB,
5235 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
5236 NewMBB->transferSuccessorsAndUpdatePHIs(MBB);
5240 // Split MBB before MI and return the new block (the one that contains MI).
5241 static MachineBasicBlock *splitBlockBefore(MachineBasicBlock::iterator MI,
5242 MachineBasicBlock *MBB) {
5243 MachineBasicBlock *NewMBB = emitBlockAfter(MBB);
5244 NewMBB->splice(NewMBB->begin(), MBB, MI, MBB->end());
5245 NewMBB->transferSuccessorsAndUpdatePHIs(MBB);
5249 // Force base value Base into a register before MI. Return the register.
5250 static unsigned forceReg(MachineInstr &MI, MachineOperand &Base,
5251 const SystemZInstrInfo *TII) {
5253 return Base.getReg();
5255 MachineBasicBlock *MBB = MI.getParent();
5256 MachineFunction &MF = *MBB->getParent();
5257 MachineRegisterInfo &MRI = MF.getRegInfo();
5259 unsigned Reg = MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass);
5260 BuildMI(*MBB, MI, MI.getDebugLoc(), TII->get(SystemZ::LA), Reg)
5267 // Implement EmitInstrWithCustomInserter for pseudo Select* instruction MI.
5269 SystemZTargetLowering::emitSelect(MachineInstr &MI,
5270 MachineBasicBlock *MBB,
5271 unsigned LOCROpcode) const {
5272 const SystemZInstrInfo *TII =
5273 static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
5275 unsigned DestReg = MI.getOperand(0).getReg();
5276 unsigned TrueReg = MI.getOperand(1).getReg();
5277 unsigned FalseReg = MI.getOperand(2).getReg();
5278 unsigned CCValid = MI.getOperand(3).getImm();
5279 unsigned CCMask = MI.getOperand(4).getImm();
5280 DebugLoc DL = MI.getDebugLoc();
5282 // Use LOCROpcode if possible.
5283 if (LOCROpcode && Subtarget.hasLoadStoreOnCond()) {
5284 BuildMI(*MBB, MI, DL, TII->get(LOCROpcode), DestReg)
5285 .addReg(FalseReg).addReg(TrueReg)
5286 .addImm(CCValid).addImm(CCMask);
5287 MI.eraseFromParent();
5291 MachineBasicBlock *StartMBB = MBB;
5292 MachineBasicBlock *JoinMBB = splitBlockBefore(MI, MBB);
5293 MachineBasicBlock *FalseMBB = emitBlockAfter(StartMBB);
5296 // BRC CCMask, JoinMBB
5297 // # fallthrough to FalseMBB
5299 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
5300 .addImm(CCValid).addImm(CCMask).addMBB(JoinMBB);
5301 MBB->addSuccessor(JoinMBB);
5302 MBB->addSuccessor(FalseMBB);
5305 // # fallthrough to JoinMBB
5307 MBB->addSuccessor(JoinMBB);
5310 // %Result = phi [ %FalseReg, FalseMBB ], [ %TrueReg, StartMBB ]
5313 BuildMI(*MBB, MI, DL, TII->get(SystemZ::PHI), DestReg)
5314 .addReg(TrueReg).addMBB(StartMBB)
5315 .addReg(FalseReg).addMBB(FalseMBB);
5317 MI.eraseFromParent();
5321 // Implement EmitInstrWithCustomInserter for pseudo CondStore* instruction MI.
5322 // StoreOpcode is the store to use and Invert says whether the store should
5323 // happen when the condition is false rather than true. If a STORE ON
5324 // CONDITION is available, STOCOpcode is its opcode, otherwise it is 0.
5325 MachineBasicBlock *SystemZTargetLowering::emitCondStore(MachineInstr &MI,
5326 MachineBasicBlock *MBB,
5327 unsigned StoreOpcode,
5328 unsigned STOCOpcode,
5329 bool Invert) const {
5330 const SystemZInstrInfo *TII =
5331 static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
5333 unsigned SrcReg = MI.getOperand(0).getReg();
5334 MachineOperand Base = MI.getOperand(1);
5335 int64_t Disp = MI.getOperand(2).getImm();
5336 unsigned IndexReg = MI.getOperand(3).getReg();
5337 unsigned CCValid = MI.getOperand(4).getImm();
5338 unsigned CCMask = MI.getOperand(5).getImm();
5339 DebugLoc DL = MI.getDebugLoc();
5341 StoreOpcode = TII->getOpcodeForOffset(StoreOpcode, Disp);
5343 // Use STOCOpcode if possible. We could use different store patterns in
5344 // order to avoid matching the index register, but the performance trade-offs
5345 // might be more complicated in that case.
5346 if (STOCOpcode && !IndexReg && Subtarget.hasLoadStoreOnCond()) {
5349 BuildMI(*MBB, MI, DL, TII->get(STOCOpcode))
5355 MI.eraseFromParent();
5359 // Get the condition needed to branch around the store.
5363 MachineBasicBlock *StartMBB = MBB;
5364 MachineBasicBlock *JoinMBB = splitBlockBefore(MI, MBB);
5365 MachineBasicBlock *FalseMBB = emitBlockAfter(StartMBB);
5368 // BRC CCMask, JoinMBB
5369 // # fallthrough to FalseMBB
5371 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
5372 .addImm(CCValid).addImm(CCMask).addMBB(JoinMBB);
5373 MBB->addSuccessor(JoinMBB);
5374 MBB->addSuccessor(FalseMBB);
5377 // store %SrcReg, %Disp(%Index,%Base)
5378 // # fallthrough to JoinMBB
5380 BuildMI(MBB, DL, TII->get(StoreOpcode))
5385 MBB->addSuccessor(JoinMBB);
5387 MI.eraseFromParent();
5391 // Implement EmitInstrWithCustomInserter for pseudo ATOMIC_LOAD{,W}_*
5392 // or ATOMIC_SWAP{,W} instruction MI. BinOpcode is the instruction that
5393 // performs the binary operation elided by "*", or 0 for ATOMIC_SWAP{,W}.
5394 // BitSize is the width of the field in bits, or 0 if this is a partword
5395 // ATOMIC_LOADW_* or ATOMIC_SWAPW instruction, in which case the bitsize
5396 // is one of the operands. Invert says whether the field should be
5397 // inverted after performing BinOpcode (e.g. for NAND).
5398 MachineBasicBlock *SystemZTargetLowering::emitAtomicLoadBinary(
5399 MachineInstr &MI, MachineBasicBlock *MBB, unsigned BinOpcode,
5400 unsigned BitSize, bool Invert) const {
5401 MachineFunction &MF = *MBB->getParent();
5402 const SystemZInstrInfo *TII =
5403 static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
5404 MachineRegisterInfo &MRI = MF.getRegInfo();
5405 bool IsSubWord = (BitSize < 32);
5407 // Extract the operands. Base can be a register or a frame index.
5408 // Src2 can be a register or immediate.
5409 unsigned Dest = MI.getOperand(0).getReg();
5410 MachineOperand Base = earlyUseOperand(MI.getOperand(1));
5411 int64_t Disp = MI.getOperand(2).getImm();
5412 MachineOperand Src2 = earlyUseOperand(MI.getOperand(3));
5413 unsigned BitShift = (IsSubWord ? MI.getOperand(4).getReg() : 0);
5414 unsigned NegBitShift = (IsSubWord ? MI.getOperand(5).getReg() : 0);
5415 DebugLoc DL = MI.getDebugLoc();
5417 BitSize = MI.getOperand(6).getImm();
5419 // Subword operations use 32-bit registers.
5420 const TargetRegisterClass *RC = (BitSize <= 32 ?
5421 &SystemZ::GR32BitRegClass :
5422 &SystemZ::GR64BitRegClass);
5423 unsigned LOpcode = BitSize <= 32 ? SystemZ::L : SystemZ::LG;
5424 unsigned CSOpcode = BitSize <= 32 ? SystemZ::CS : SystemZ::CSG;
5426 // Get the right opcodes for the displacement.
5427 LOpcode = TII->getOpcodeForOffset(LOpcode, Disp);
5428 CSOpcode = TII->getOpcodeForOffset(CSOpcode, Disp);
5429 assert(LOpcode && CSOpcode && "Displacement out of range");
5431 // Create virtual registers for temporary results.
5432 unsigned OrigVal = MRI.createVirtualRegister(RC);
5433 unsigned OldVal = MRI.createVirtualRegister(RC);
5434 unsigned NewVal = (BinOpcode || IsSubWord ?
5435 MRI.createVirtualRegister(RC) : Src2.getReg());
5436 unsigned RotatedOldVal = (IsSubWord ? MRI.createVirtualRegister(RC) : OldVal);
5437 unsigned RotatedNewVal = (IsSubWord ? MRI.createVirtualRegister(RC) : NewVal);
5439 // Insert a basic block for the main loop.
5440 MachineBasicBlock *StartMBB = MBB;
5441 MachineBasicBlock *DoneMBB = splitBlockBefore(MI, MBB);
5442 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
5446 // %OrigVal = L Disp(%Base)
5447 // # fall through to LoopMMB
5449 BuildMI(MBB, DL, TII->get(LOpcode), OrigVal).add(Base).addImm(Disp).addReg(0);
5450 MBB->addSuccessor(LoopMBB);
5453 // %OldVal = phi [ %OrigVal, StartMBB ], [ %Dest, LoopMBB ]
5454 // %RotatedOldVal = RLL %OldVal, 0(%BitShift)
5455 // %RotatedNewVal = OP %RotatedOldVal, %Src2
5456 // %NewVal = RLL %RotatedNewVal, 0(%NegBitShift)
5457 // %Dest = CS %OldVal, %NewVal, Disp(%Base)
5459 // # fall through to DoneMMB
5461 BuildMI(MBB, DL, TII->get(SystemZ::PHI), OldVal)
5462 .addReg(OrigVal).addMBB(StartMBB)
5463 .addReg(Dest).addMBB(LoopMBB);
5465 BuildMI(MBB, DL, TII->get(SystemZ::RLL), RotatedOldVal)
5466 .addReg(OldVal).addReg(BitShift).addImm(0);
5468 // Perform the operation normally and then invert every bit of the field.
5469 unsigned Tmp = MRI.createVirtualRegister(RC);
5470 BuildMI(MBB, DL, TII->get(BinOpcode), Tmp).addReg(RotatedOldVal).add(Src2);
5472 // XILF with the upper BitSize bits set.
5473 BuildMI(MBB, DL, TII->get(SystemZ::XILF), RotatedNewVal)
5474 .addReg(Tmp).addImm(-1U << (32 - BitSize));
5476 // Use LCGR and add -1 to the result, which is more compact than
5477 // an XILF, XILH pair.
5478 unsigned Tmp2 = MRI.createVirtualRegister(RC);
5479 BuildMI(MBB, DL, TII->get(SystemZ::LCGR), Tmp2).addReg(Tmp);
5480 BuildMI(MBB, DL, TII->get(SystemZ::AGHI), RotatedNewVal)
5481 .addReg(Tmp2).addImm(-1);
5483 } else if (BinOpcode)
5484 // A simply binary operation.
5485 BuildMI(MBB, DL, TII->get(BinOpcode), RotatedNewVal)
5486 .addReg(RotatedOldVal)
5489 // Use RISBG to rotate Src2 into position and use it to replace the
5490 // field in RotatedOldVal.
5491 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RotatedNewVal)
5492 .addReg(RotatedOldVal).addReg(Src2.getReg())
5493 .addImm(32).addImm(31 + BitSize).addImm(32 - BitSize);
5495 BuildMI(MBB, DL, TII->get(SystemZ::RLL), NewVal)
5496 .addReg(RotatedNewVal).addReg(NegBitShift).addImm(0);
5497 BuildMI(MBB, DL, TII->get(CSOpcode), Dest)
5502 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
5503 .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
5504 MBB->addSuccessor(LoopMBB);
5505 MBB->addSuccessor(DoneMBB);
5507 MI.eraseFromParent();
5511 // Implement EmitInstrWithCustomInserter for pseudo
5512 // ATOMIC_LOAD{,W}_{,U}{MIN,MAX} instruction MI. CompareOpcode is the
5513 // instruction that should be used to compare the current field with the
5514 // minimum or maximum value. KeepOldMask is the BRC condition-code mask
5515 // for when the current field should be kept. BitSize is the width of
5516 // the field in bits, or 0 if this is a partword ATOMIC_LOADW_* instruction.
5517 MachineBasicBlock *SystemZTargetLowering::emitAtomicLoadMinMax(
5518 MachineInstr &MI, MachineBasicBlock *MBB, unsigned CompareOpcode,
5519 unsigned KeepOldMask, unsigned BitSize) const {
5520 MachineFunction &MF = *MBB->getParent();
5521 const SystemZInstrInfo *TII =
5522 static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
5523 MachineRegisterInfo &MRI = MF.getRegInfo();
5524 bool IsSubWord = (BitSize < 32);
5526 // Extract the operands. Base can be a register or a frame index.
5527 unsigned Dest = MI.getOperand(0).getReg();
5528 MachineOperand Base = earlyUseOperand(MI.getOperand(1));
5529 int64_t Disp = MI.getOperand(2).getImm();
5530 unsigned Src2 = MI.getOperand(3).getReg();
5531 unsigned BitShift = (IsSubWord ? MI.getOperand(4).getReg() : 0);
5532 unsigned NegBitShift = (IsSubWord ? MI.getOperand(5).getReg() : 0);
5533 DebugLoc DL = MI.getDebugLoc();
5535 BitSize = MI.getOperand(6).getImm();
5537 // Subword operations use 32-bit registers.
5538 const TargetRegisterClass *RC = (BitSize <= 32 ?
5539 &SystemZ::GR32BitRegClass :
5540 &SystemZ::GR64BitRegClass);
5541 unsigned LOpcode = BitSize <= 32 ? SystemZ::L : SystemZ::LG;
5542 unsigned CSOpcode = BitSize <= 32 ? SystemZ::CS : SystemZ::CSG;
5544 // Get the right opcodes for the displacement.
5545 LOpcode = TII->getOpcodeForOffset(LOpcode, Disp);
5546 CSOpcode = TII->getOpcodeForOffset(CSOpcode, Disp);
5547 assert(LOpcode && CSOpcode && "Displacement out of range");
5549 // Create virtual registers for temporary results.
5550 unsigned OrigVal = MRI.createVirtualRegister(RC);
5551 unsigned OldVal = MRI.createVirtualRegister(RC);
5552 unsigned NewVal = MRI.createVirtualRegister(RC);
5553 unsigned RotatedOldVal = (IsSubWord ? MRI.createVirtualRegister(RC) : OldVal);
5554 unsigned RotatedAltVal = (IsSubWord ? MRI.createVirtualRegister(RC) : Src2);
5555 unsigned RotatedNewVal = (IsSubWord ? MRI.createVirtualRegister(RC) : NewVal);
5557 // Insert 3 basic blocks for the loop.
5558 MachineBasicBlock *StartMBB = MBB;
5559 MachineBasicBlock *DoneMBB = splitBlockBefore(MI, MBB);
5560 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
5561 MachineBasicBlock *UseAltMBB = emitBlockAfter(LoopMBB);
5562 MachineBasicBlock *UpdateMBB = emitBlockAfter(UseAltMBB);
5566 // %OrigVal = L Disp(%Base)
5567 // # fall through to LoopMMB
5569 BuildMI(MBB, DL, TII->get(LOpcode), OrigVal).add(Base).addImm(Disp).addReg(0);
5570 MBB->addSuccessor(LoopMBB);
5573 // %OldVal = phi [ %OrigVal, StartMBB ], [ %Dest, UpdateMBB ]
5574 // %RotatedOldVal = RLL %OldVal, 0(%BitShift)
5575 // CompareOpcode %RotatedOldVal, %Src2
5576 // BRC KeepOldMask, UpdateMBB
5578 BuildMI(MBB, DL, TII->get(SystemZ::PHI), OldVal)
5579 .addReg(OrigVal).addMBB(StartMBB)
5580 .addReg(Dest).addMBB(UpdateMBB);
5582 BuildMI(MBB, DL, TII->get(SystemZ::RLL), RotatedOldVal)
5583 .addReg(OldVal).addReg(BitShift).addImm(0);
5584 BuildMI(MBB, DL, TII->get(CompareOpcode))
5585 .addReg(RotatedOldVal).addReg(Src2);
5586 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
5587 .addImm(SystemZ::CCMASK_ICMP).addImm(KeepOldMask).addMBB(UpdateMBB);
5588 MBB->addSuccessor(UpdateMBB);
5589 MBB->addSuccessor(UseAltMBB);
5592 // %RotatedAltVal = RISBG %RotatedOldVal, %Src2, 32, 31 + BitSize, 0
5593 // # fall through to UpdateMMB
5596 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RotatedAltVal)
5597 .addReg(RotatedOldVal).addReg(Src2)
5598 .addImm(32).addImm(31 + BitSize).addImm(0);
5599 MBB->addSuccessor(UpdateMBB);
5602 // %RotatedNewVal = PHI [ %RotatedOldVal, LoopMBB ],
5603 // [ %RotatedAltVal, UseAltMBB ]
5604 // %NewVal = RLL %RotatedNewVal, 0(%NegBitShift)
5605 // %Dest = CS %OldVal, %NewVal, Disp(%Base)
5607 // # fall through to DoneMMB
5609 BuildMI(MBB, DL, TII->get(SystemZ::PHI), RotatedNewVal)
5610 .addReg(RotatedOldVal).addMBB(LoopMBB)
5611 .addReg(RotatedAltVal).addMBB(UseAltMBB);
5613 BuildMI(MBB, DL, TII->get(SystemZ::RLL), NewVal)
5614 .addReg(RotatedNewVal).addReg(NegBitShift).addImm(0);
5615 BuildMI(MBB, DL, TII->get(CSOpcode), Dest)
5620 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
5621 .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
5622 MBB->addSuccessor(LoopMBB);
5623 MBB->addSuccessor(DoneMBB);
5625 MI.eraseFromParent();
5629 // Implement EmitInstrWithCustomInserter for pseudo ATOMIC_CMP_SWAPW
5632 SystemZTargetLowering::emitAtomicCmpSwapW(MachineInstr &MI,
5633 MachineBasicBlock *MBB) const {
5635 MachineFunction &MF = *MBB->getParent();
5636 const SystemZInstrInfo *TII =
5637 static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
5638 MachineRegisterInfo &MRI = MF.getRegInfo();
5640 // Extract the operands. Base can be a register or a frame index.
5641 unsigned Dest = MI.getOperand(0).getReg();
5642 MachineOperand Base = earlyUseOperand(MI.getOperand(1));
5643 int64_t Disp = MI.getOperand(2).getImm();
5644 unsigned OrigCmpVal = MI.getOperand(3).getReg();
5645 unsigned OrigSwapVal = MI.getOperand(4).getReg();
5646 unsigned BitShift = MI.getOperand(5).getReg();
5647 unsigned NegBitShift = MI.getOperand(6).getReg();
5648 int64_t BitSize = MI.getOperand(7).getImm();
5649 DebugLoc DL = MI.getDebugLoc();
5651 const TargetRegisterClass *RC = &SystemZ::GR32BitRegClass;
5653 // Get the right opcodes for the displacement.
5654 unsigned LOpcode = TII->getOpcodeForOffset(SystemZ::L, Disp);
5655 unsigned CSOpcode = TII->getOpcodeForOffset(SystemZ::CS, Disp);
5656 assert(LOpcode && CSOpcode && "Displacement out of range");
5658 // Create virtual registers for temporary results.
5659 unsigned OrigOldVal = MRI.createVirtualRegister(RC);
5660 unsigned OldVal = MRI.createVirtualRegister(RC);
5661 unsigned CmpVal = MRI.createVirtualRegister(RC);
5662 unsigned SwapVal = MRI.createVirtualRegister(RC);
5663 unsigned StoreVal = MRI.createVirtualRegister(RC);
5664 unsigned RetryOldVal = MRI.createVirtualRegister(RC);
5665 unsigned RetryCmpVal = MRI.createVirtualRegister(RC);
5666 unsigned RetrySwapVal = MRI.createVirtualRegister(RC);
5668 // Insert 2 basic blocks for the loop.
5669 MachineBasicBlock *StartMBB = MBB;
5670 MachineBasicBlock *DoneMBB = splitBlockBefore(MI, MBB);
5671 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
5672 MachineBasicBlock *SetMBB = emitBlockAfter(LoopMBB);
5676 // %OrigOldVal = L Disp(%Base)
5677 // # fall through to LoopMMB
5679 BuildMI(MBB, DL, TII->get(LOpcode), OrigOldVal)
5683 MBB->addSuccessor(LoopMBB);
5686 // %OldVal = phi [ %OrigOldVal, EntryBB ], [ %RetryOldVal, SetMBB ]
5687 // %CmpVal = phi [ %OrigCmpVal, EntryBB ], [ %RetryCmpVal, SetMBB ]
5688 // %SwapVal = phi [ %OrigSwapVal, EntryBB ], [ %RetrySwapVal, SetMBB ]
5689 // %Dest = RLL %OldVal, BitSize(%BitShift)
5690 // ^^ The low BitSize bits contain the field
5692 // %RetryCmpVal = RISBG32 %CmpVal, %Dest, 32, 63-BitSize, 0
5693 // ^^ Replace the upper 32-BitSize bits of the
5694 // comparison value with those that we loaded,
5695 // so that we can use a full word comparison.
5696 // CR %Dest, %RetryCmpVal
5698 // # Fall through to SetMBB
5700 BuildMI(MBB, DL, TII->get(SystemZ::PHI), OldVal)
5701 .addReg(OrigOldVal).addMBB(StartMBB)
5702 .addReg(RetryOldVal).addMBB(SetMBB);
5703 BuildMI(MBB, DL, TII->get(SystemZ::PHI), CmpVal)
5704 .addReg(OrigCmpVal).addMBB(StartMBB)
5705 .addReg(RetryCmpVal).addMBB(SetMBB);
5706 BuildMI(MBB, DL, TII->get(SystemZ::PHI), SwapVal)
5707 .addReg(OrigSwapVal).addMBB(StartMBB)
5708 .addReg(RetrySwapVal).addMBB(SetMBB);
5709 BuildMI(MBB, DL, TII->get(SystemZ::RLL), Dest)
5710 .addReg(OldVal).addReg(BitShift).addImm(BitSize);
5711 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RetryCmpVal)
5712 .addReg(CmpVal).addReg(Dest).addImm(32).addImm(63 - BitSize).addImm(0);
5713 BuildMI(MBB, DL, TII->get(SystemZ::CR))
5714 .addReg(Dest).addReg(RetryCmpVal);
5715 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
5716 .addImm(SystemZ::CCMASK_ICMP)
5717 .addImm(SystemZ::CCMASK_CMP_NE).addMBB(DoneMBB);
5718 MBB->addSuccessor(DoneMBB);
5719 MBB->addSuccessor(SetMBB);
5722 // %RetrySwapVal = RISBG32 %SwapVal, %Dest, 32, 63-BitSize, 0
5723 // ^^ Replace the upper 32-BitSize bits of the new
5724 // value with those that we loaded.
5725 // %StoreVal = RLL %RetrySwapVal, -BitSize(%NegBitShift)
5726 // ^^ Rotate the new field to its proper position.
5727 // %RetryOldVal = CS %Dest, %StoreVal, Disp(%Base)
5729 // # fall through to ExitMMB
5731 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RetrySwapVal)
5732 .addReg(SwapVal).addReg(Dest).addImm(32).addImm(63 - BitSize).addImm(0);
5733 BuildMI(MBB, DL, TII->get(SystemZ::RLL), StoreVal)
5734 .addReg(RetrySwapVal).addReg(NegBitShift).addImm(-BitSize);
5735 BuildMI(MBB, DL, TII->get(CSOpcode), RetryOldVal)
5740 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
5741 .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
5742 MBB->addSuccessor(LoopMBB);
5743 MBB->addSuccessor(DoneMBB);
5745 MI.eraseFromParent();
5749 // Emit an extension from a GR32 or GR64 to a GR128. ClearEven is true
5750 // if the high register of the GR128 value must be cleared or false if
5751 // it's "don't care". SubReg is subreg_l32 when extending a GR32
5752 // and subreg_l64 when extending a GR64.
5753 MachineBasicBlock *SystemZTargetLowering::emitExt128(MachineInstr &MI,
5754 MachineBasicBlock *MBB,
5756 unsigned SubReg) const {
5757 MachineFunction &MF = *MBB->getParent();
5758 const SystemZInstrInfo *TII =
5759 static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
5760 MachineRegisterInfo &MRI = MF.getRegInfo();
5761 DebugLoc DL = MI.getDebugLoc();
5763 unsigned Dest = MI.getOperand(0).getReg();
5764 unsigned Src = MI.getOperand(1).getReg();
5765 unsigned In128 = MRI.createVirtualRegister(&SystemZ::GR128BitRegClass);
5767 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::IMPLICIT_DEF), In128);
5769 unsigned NewIn128 = MRI.createVirtualRegister(&SystemZ::GR128BitRegClass);
5770 unsigned Zero64 = MRI.createVirtualRegister(&SystemZ::GR64BitRegClass);
5772 BuildMI(*MBB, MI, DL, TII->get(SystemZ::LLILL), Zero64)
5774 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::INSERT_SUBREG), NewIn128)
5775 .addReg(In128).addReg(Zero64).addImm(SystemZ::subreg_h64);
5778 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::INSERT_SUBREG), Dest)
5779 .addReg(In128).addReg(Src).addImm(SubReg);
5781 MI.eraseFromParent();
5785 MachineBasicBlock *SystemZTargetLowering::emitMemMemWrapper(
5786 MachineInstr &MI, MachineBasicBlock *MBB, unsigned Opcode) const {
5787 MachineFunction &MF = *MBB->getParent();
5788 const SystemZInstrInfo *TII =
5789 static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
5790 MachineRegisterInfo &MRI = MF.getRegInfo();
5791 DebugLoc DL = MI.getDebugLoc();
5793 MachineOperand DestBase = earlyUseOperand(MI.getOperand(0));
5794 uint64_t DestDisp = MI.getOperand(1).getImm();
5795 MachineOperand SrcBase = earlyUseOperand(MI.getOperand(2));
5796 uint64_t SrcDisp = MI.getOperand(3).getImm();
5797 uint64_t Length = MI.getOperand(4).getImm();
5799 // When generating more than one CLC, all but the last will need to
5800 // branch to the end when a difference is found.
5801 MachineBasicBlock *EndMBB = (Length > 256 && Opcode == SystemZ::CLC ?
5802 splitBlockAfter(MI, MBB) : nullptr);
5804 // Check for the loop form, in which operand 5 is the trip count.
5805 if (MI.getNumExplicitOperands() > 5) {
5806 bool HaveSingleBase = DestBase.isIdenticalTo(SrcBase);
5808 uint64_t StartCountReg = MI.getOperand(5).getReg();
5809 uint64_t StartSrcReg = forceReg(MI, SrcBase, TII);
5810 uint64_t StartDestReg = (HaveSingleBase ? StartSrcReg :
5811 forceReg(MI, DestBase, TII));
5813 const TargetRegisterClass *RC = &SystemZ::ADDR64BitRegClass;
5814 uint64_t ThisSrcReg = MRI.createVirtualRegister(RC);
5815 uint64_t ThisDestReg = (HaveSingleBase ? ThisSrcReg :
5816 MRI.createVirtualRegister(RC));
5817 uint64_t NextSrcReg = MRI.createVirtualRegister(RC);
5818 uint64_t NextDestReg = (HaveSingleBase ? NextSrcReg :
5819 MRI.createVirtualRegister(RC));
5821 RC = &SystemZ::GR64BitRegClass;
5822 uint64_t ThisCountReg = MRI.createVirtualRegister(RC);
5823 uint64_t NextCountReg = MRI.createVirtualRegister(RC);
5825 MachineBasicBlock *StartMBB = MBB;
5826 MachineBasicBlock *DoneMBB = splitBlockBefore(MI, MBB);
5827 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
5828 MachineBasicBlock *NextMBB = (EndMBB ? emitBlockAfter(LoopMBB) : LoopMBB);
5831 // # fall through to LoopMMB
5832 MBB->addSuccessor(LoopMBB);
5835 // %ThisDestReg = phi [ %StartDestReg, StartMBB ],
5836 // [ %NextDestReg, NextMBB ]
5837 // %ThisSrcReg = phi [ %StartSrcReg, StartMBB ],
5838 // [ %NextSrcReg, NextMBB ]
5839 // %ThisCountReg = phi [ %StartCountReg, StartMBB ],
5840 // [ %NextCountReg, NextMBB ]
5841 // ( PFD 2, 768+DestDisp(%ThisDestReg) )
5842 // Opcode DestDisp(256,%ThisDestReg), SrcDisp(%ThisSrcReg)
5845 // The prefetch is used only for MVC. The JLH is used only for CLC.
5848 BuildMI(MBB, DL, TII->get(SystemZ::PHI), ThisDestReg)
5849 .addReg(StartDestReg).addMBB(StartMBB)
5850 .addReg(NextDestReg).addMBB(NextMBB);
5851 if (!HaveSingleBase)
5852 BuildMI(MBB, DL, TII->get(SystemZ::PHI), ThisSrcReg)
5853 .addReg(StartSrcReg).addMBB(StartMBB)
5854 .addReg(NextSrcReg).addMBB(NextMBB);
5855 BuildMI(MBB, DL, TII->get(SystemZ::PHI), ThisCountReg)
5856 .addReg(StartCountReg).addMBB(StartMBB)
5857 .addReg(NextCountReg).addMBB(NextMBB);
5858 if (Opcode == SystemZ::MVC)
5859 BuildMI(MBB, DL, TII->get(SystemZ::PFD))
5860 .addImm(SystemZ::PFD_WRITE)
5861 .addReg(ThisDestReg).addImm(DestDisp + 768).addReg(0);
5862 BuildMI(MBB, DL, TII->get(Opcode))
5863 .addReg(ThisDestReg).addImm(DestDisp).addImm(256)
5864 .addReg(ThisSrcReg).addImm(SrcDisp);
5866 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
5867 .addImm(SystemZ::CCMASK_ICMP).addImm(SystemZ::CCMASK_CMP_NE)
5869 MBB->addSuccessor(EndMBB);
5870 MBB->addSuccessor(NextMBB);
5874 // %NextDestReg = LA 256(%ThisDestReg)
5875 // %NextSrcReg = LA 256(%ThisSrcReg)
5876 // %NextCountReg = AGHI %ThisCountReg, -1
5877 // CGHI %NextCountReg, 0
5879 // # fall through to DoneMMB
5881 // The AGHI, CGHI and JLH should be converted to BRCTG by later passes.
5884 BuildMI(MBB, DL, TII->get(SystemZ::LA), NextDestReg)
5885 .addReg(ThisDestReg).addImm(256).addReg(0);
5886 if (!HaveSingleBase)
5887 BuildMI(MBB, DL, TII->get(SystemZ::LA), NextSrcReg)
5888 .addReg(ThisSrcReg).addImm(256).addReg(0);
5889 BuildMI(MBB, DL, TII->get(SystemZ::AGHI), NextCountReg)
5890 .addReg(ThisCountReg).addImm(-1);
5891 BuildMI(MBB, DL, TII->get(SystemZ::CGHI))
5892 .addReg(NextCountReg).addImm(0);
5893 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
5894 .addImm(SystemZ::CCMASK_ICMP).addImm(SystemZ::CCMASK_CMP_NE)
5896 MBB->addSuccessor(LoopMBB);
5897 MBB->addSuccessor(DoneMBB);
5899 DestBase = MachineOperand::CreateReg(NextDestReg, false);
5900 SrcBase = MachineOperand::CreateReg(NextSrcReg, false);
5904 // Handle any remaining bytes with straight-line code.
5905 while (Length > 0) {
5906 uint64_t ThisLength = std::min(Length, uint64_t(256));
5907 // The previous iteration might have created out-of-range displacements.
5908 // Apply them using LAY if so.
5909 if (!isUInt<12>(DestDisp)) {
5910 unsigned Reg = MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass);
5911 BuildMI(*MBB, MI, MI.getDebugLoc(), TII->get(SystemZ::LAY), Reg)
5915 DestBase = MachineOperand::CreateReg(Reg, false);
5918 if (!isUInt<12>(SrcDisp)) {
5919 unsigned Reg = MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass);
5920 BuildMI(*MBB, MI, MI.getDebugLoc(), TII->get(SystemZ::LAY), Reg)
5924 SrcBase = MachineOperand::CreateReg(Reg, false);
5927 BuildMI(*MBB, MI, DL, TII->get(Opcode))
5933 DestDisp += ThisLength;
5934 SrcDisp += ThisLength;
5935 Length -= ThisLength;
5936 // If there's another CLC to go, branch to the end if a difference
5938 if (EndMBB && Length > 0) {
5939 MachineBasicBlock *NextMBB = splitBlockBefore(MI, MBB);
5940 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
5941 .addImm(SystemZ::CCMASK_ICMP).addImm(SystemZ::CCMASK_CMP_NE)
5943 MBB->addSuccessor(EndMBB);
5944 MBB->addSuccessor(NextMBB);
5949 MBB->addSuccessor(EndMBB);
5951 MBB->addLiveIn(SystemZ::CC);
5954 MI.eraseFromParent();
5958 // Decompose string pseudo-instruction MI into a loop that continually performs
5959 // Opcode until CC != 3.
5960 MachineBasicBlock *SystemZTargetLowering::emitStringWrapper(
5961 MachineInstr &MI, MachineBasicBlock *MBB, unsigned Opcode) const {
5962 MachineFunction &MF = *MBB->getParent();
5963 const SystemZInstrInfo *TII =
5964 static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
5965 MachineRegisterInfo &MRI = MF.getRegInfo();
5966 DebugLoc DL = MI.getDebugLoc();
5968 uint64_t End1Reg = MI.getOperand(0).getReg();
5969 uint64_t Start1Reg = MI.getOperand(1).getReg();
5970 uint64_t Start2Reg = MI.getOperand(2).getReg();
5971 uint64_t CharReg = MI.getOperand(3).getReg();
5973 const TargetRegisterClass *RC = &SystemZ::GR64BitRegClass;
5974 uint64_t This1Reg = MRI.createVirtualRegister(RC);
5975 uint64_t This2Reg = MRI.createVirtualRegister(RC);
5976 uint64_t End2Reg = MRI.createVirtualRegister(RC);
5978 MachineBasicBlock *StartMBB = MBB;
5979 MachineBasicBlock *DoneMBB = splitBlockBefore(MI, MBB);
5980 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
5983 // # fall through to LoopMMB
5984 MBB->addSuccessor(LoopMBB);
5987 // %This1Reg = phi [ %Start1Reg, StartMBB ], [ %End1Reg, LoopMBB ]
5988 // %This2Reg = phi [ %Start2Reg, StartMBB ], [ %End2Reg, LoopMBB ]
5990 // %End1Reg, %End2Reg = CLST %This1Reg, %This2Reg -- uses R0L
5992 // # fall through to DoneMMB
5994 // The load of R0L can be hoisted by post-RA LICM.
5997 BuildMI(MBB, DL, TII->get(SystemZ::PHI), This1Reg)
5998 .addReg(Start1Reg).addMBB(StartMBB)
5999 .addReg(End1Reg).addMBB(LoopMBB);
6000 BuildMI(MBB, DL, TII->get(SystemZ::PHI), This2Reg)
6001 .addReg(Start2Reg).addMBB(StartMBB)
6002 .addReg(End2Reg).addMBB(LoopMBB);
6003 BuildMI(MBB, DL, TII->get(TargetOpcode::COPY), SystemZ::R0L).addReg(CharReg);
6004 BuildMI(MBB, DL, TII->get(Opcode))
6005 .addReg(End1Reg, RegState::Define).addReg(End2Reg, RegState::Define)
6006 .addReg(This1Reg).addReg(This2Reg);
6007 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
6008 .addImm(SystemZ::CCMASK_ANY).addImm(SystemZ::CCMASK_3).addMBB(LoopMBB);
6009 MBB->addSuccessor(LoopMBB);
6010 MBB->addSuccessor(DoneMBB);
6012 DoneMBB->addLiveIn(SystemZ::CC);
6014 MI.eraseFromParent();
6018 // Update TBEGIN instruction with final opcode and register clobbers.
6019 MachineBasicBlock *SystemZTargetLowering::emitTransactionBegin(
6020 MachineInstr &MI, MachineBasicBlock *MBB, unsigned Opcode,
6021 bool NoFloat) const {
6022 MachineFunction &MF = *MBB->getParent();
6023 const TargetFrameLowering *TFI = Subtarget.getFrameLowering();
6024 const SystemZInstrInfo *TII = Subtarget.getInstrInfo();
6027 MI.setDesc(TII->get(Opcode));
6029 // We cannot handle a TBEGIN that clobbers the stack or frame pointer.
6030 // Make sure to add the corresponding GRSM bits if they are missing.
6031 uint64_t Control = MI.getOperand(2).getImm();
6032 static const unsigned GPRControlBit[16] = {
6033 0x8000, 0x8000, 0x4000, 0x4000, 0x2000, 0x2000, 0x1000, 0x1000,
6034 0x0800, 0x0800, 0x0400, 0x0400, 0x0200, 0x0200, 0x0100, 0x0100
6036 Control |= GPRControlBit[15];
6038 Control |= GPRControlBit[11];
6039 MI.getOperand(2).setImm(Control);
6041 // Add GPR clobbers.
6042 for (int I = 0; I < 16; I++) {
6043 if ((Control & GPRControlBit[I]) == 0) {
6044 unsigned Reg = SystemZMC::GR64Regs[I];
6045 MI.addOperand(MachineOperand::CreateReg(Reg, true, true));
6049 // Add FPR/VR clobbers.
6050 if (!NoFloat && (Control & 4) != 0) {
6051 if (Subtarget.hasVector()) {
6052 for (int I = 0; I < 32; I++) {
6053 unsigned Reg = SystemZMC::VR128Regs[I];
6054 MI.addOperand(MachineOperand::CreateReg(Reg, true, true));
6057 for (int I = 0; I < 16; I++) {
6058 unsigned Reg = SystemZMC::FP64Regs[I];
6059 MI.addOperand(MachineOperand::CreateReg(Reg, true, true));
6067 MachineBasicBlock *SystemZTargetLowering::emitLoadAndTestCmp0(
6068 MachineInstr &MI, MachineBasicBlock *MBB, unsigned Opcode) const {
6069 MachineFunction &MF = *MBB->getParent();
6070 MachineRegisterInfo *MRI = &MF.getRegInfo();
6071 const SystemZInstrInfo *TII =
6072 static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
6073 DebugLoc DL = MI.getDebugLoc();
6075 unsigned SrcReg = MI.getOperand(0).getReg();
6077 // Create new virtual register of the same class as source.
6078 const TargetRegisterClass *RC = MRI->getRegClass(SrcReg);
6079 unsigned DstReg = MRI->createVirtualRegister(RC);
6081 // Replace pseudo with a normal load-and-test that models the def as
6083 BuildMI(*MBB, MI, DL, TII->get(Opcode), DstReg)
6085 MI.eraseFromParent();
6090 MachineBasicBlock *SystemZTargetLowering::EmitInstrWithCustomInserter(
6091 MachineInstr &MI, MachineBasicBlock *MBB) const {
6092 switch (MI.getOpcode()) {
6093 case SystemZ::Select32Mux:
6094 return emitSelect(MI, MBB,
6095 Subtarget.hasLoadStoreOnCond2()? SystemZ::LOCRMux : 0);
6096 case SystemZ::Select32:
6097 return emitSelect(MI, MBB, SystemZ::LOCR);
6098 case SystemZ::Select64:
6099 return emitSelect(MI, MBB, SystemZ::LOCGR);
6100 case SystemZ::SelectF32:
6101 case SystemZ::SelectF64:
6102 case SystemZ::SelectF128:
6103 return emitSelect(MI, MBB, 0);
6105 case SystemZ::CondStore8Mux:
6106 return emitCondStore(MI, MBB, SystemZ::STCMux, 0, false);
6107 case SystemZ::CondStore8MuxInv:
6108 return emitCondStore(MI, MBB, SystemZ::STCMux, 0, true);
6109 case SystemZ::CondStore16Mux:
6110 return emitCondStore(MI, MBB, SystemZ::STHMux, 0, false);
6111 case SystemZ::CondStore16MuxInv:
6112 return emitCondStore(MI, MBB, SystemZ::STHMux, 0, true);
6113 case SystemZ::CondStore32Mux:
6114 return emitCondStore(MI, MBB, SystemZ::STMux, SystemZ::STOCMux, false);
6115 case SystemZ::CondStore32MuxInv:
6116 return emitCondStore(MI, MBB, SystemZ::STMux, SystemZ::STOCMux, true);
6117 case SystemZ::CondStore8:
6118 return emitCondStore(MI, MBB, SystemZ::STC, 0, false);
6119 case SystemZ::CondStore8Inv:
6120 return emitCondStore(MI, MBB, SystemZ::STC, 0, true);
6121 case SystemZ::CondStore16:
6122 return emitCondStore(MI, MBB, SystemZ::STH, 0, false);
6123 case SystemZ::CondStore16Inv:
6124 return emitCondStore(MI, MBB, SystemZ::STH, 0, true);
6125 case SystemZ::CondStore32:
6126 return emitCondStore(MI, MBB, SystemZ::ST, SystemZ::STOC, false);
6127 case SystemZ::CondStore32Inv:
6128 return emitCondStore(MI, MBB, SystemZ::ST, SystemZ::STOC, true);
6129 case SystemZ::CondStore64:
6130 return emitCondStore(MI, MBB, SystemZ::STG, SystemZ::STOCG, false);
6131 case SystemZ::CondStore64Inv:
6132 return emitCondStore(MI, MBB, SystemZ::STG, SystemZ::STOCG, true);
6133 case SystemZ::CondStoreF32:
6134 return emitCondStore(MI, MBB, SystemZ::STE, 0, false);
6135 case SystemZ::CondStoreF32Inv:
6136 return emitCondStore(MI, MBB, SystemZ::STE, 0, true);
6137 case SystemZ::CondStoreF64:
6138 return emitCondStore(MI, MBB, SystemZ::STD, 0, false);
6139 case SystemZ::CondStoreF64Inv:
6140 return emitCondStore(MI, MBB, SystemZ::STD, 0, true);
6142 case SystemZ::AEXT128_64:
6143 return emitExt128(MI, MBB, false, SystemZ::subreg_l64);
6144 case SystemZ::ZEXT128_32:
6145 return emitExt128(MI, MBB, true, SystemZ::subreg_l32);
6146 case SystemZ::ZEXT128_64:
6147 return emitExt128(MI, MBB, true, SystemZ::subreg_l64);
6149 case SystemZ::ATOMIC_SWAPW:
6150 return emitAtomicLoadBinary(MI, MBB, 0, 0);
6151 case SystemZ::ATOMIC_SWAP_32:
6152 return emitAtomicLoadBinary(MI, MBB, 0, 32);
6153 case SystemZ::ATOMIC_SWAP_64:
6154 return emitAtomicLoadBinary(MI, MBB, 0, 64);
6156 case SystemZ::ATOMIC_LOADW_AR:
6157 return emitAtomicLoadBinary(MI, MBB, SystemZ::AR, 0);
6158 case SystemZ::ATOMIC_LOADW_AFI:
6159 return emitAtomicLoadBinary(MI, MBB, SystemZ::AFI, 0);
6160 case SystemZ::ATOMIC_LOAD_AR:
6161 return emitAtomicLoadBinary(MI, MBB, SystemZ::AR, 32);
6162 case SystemZ::ATOMIC_LOAD_AHI:
6163 return emitAtomicLoadBinary(MI, MBB, SystemZ::AHI, 32);
6164 case SystemZ::ATOMIC_LOAD_AFI:
6165 return emitAtomicLoadBinary(MI, MBB, SystemZ::AFI, 32);
6166 case SystemZ::ATOMIC_LOAD_AGR:
6167 return emitAtomicLoadBinary(MI, MBB, SystemZ::AGR, 64);
6168 case SystemZ::ATOMIC_LOAD_AGHI:
6169 return emitAtomicLoadBinary(MI, MBB, SystemZ::AGHI, 64);
6170 case SystemZ::ATOMIC_LOAD_AGFI:
6171 return emitAtomicLoadBinary(MI, MBB, SystemZ::AGFI, 64);
6173 case SystemZ::ATOMIC_LOADW_SR:
6174 return emitAtomicLoadBinary(MI, MBB, SystemZ::SR, 0);
6175 case SystemZ::ATOMIC_LOAD_SR:
6176 return emitAtomicLoadBinary(MI, MBB, SystemZ::SR, 32);
6177 case SystemZ::ATOMIC_LOAD_SGR:
6178 return emitAtomicLoadBinary(MI, MBB, SystemZ::SGR, 64);
6180 case SystemZ::ATOMIC_LOADW_NR:
6181 return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 0);
6182 case SystemZ::ATOMIC_LOADW_NILH:
6183 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 0);
6184 case SystemZ::ATOMIC_LOAD_NR:
6185 return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 32);
6186 case SystemZ::ATOMIC_LOAD_NILL:
6187 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL, 32);
6188 case SystemZ::ATOMIC_LOAD_NILH:
6189 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 32);
6190 case SystemZ::ATOMIC_LOAD_NILF:
6191 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF, 32);
6192 case SystemZ::ATOMIC_LOAD_NGR:
6193 return emitAtomicLoadBinary(MI, MBB, SystemZ::NGR, 64);
6194 case SystemZ::ATOMIC_LOAD_NILL64:
6195 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL64, 64);
6196 case SystemZ::ATOMIC_LOAD_NILH64:
6197 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH64, 64);
6198 case SystemZ::ATOMIC_LOAD_NIHL64:
6199 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHL64, 64);
6200 case SystemZ::ATOMIC_LOAD_NIHH64:
6201 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHH64, 64);
6202 case SystemZ::ATOMIC_LOAD_NILF64:
6203 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF64, 64);
6204 case SystemZ::ATOMIC_LOAD_NIHF64:
6205 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHF64, 64);
6207 case SystemZ::ATOMIC_LOADW_OR:
6208 return emitAtomicLoadBinary(MI, MBB, SystemZ::OR, 0);
6209 case SystemZ::ATOMIC_LOADW_OILH:
6210 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILH, 0);
6211 case SystemZ::ATOMIC_LOAD_OR:
6212 return emitAtomicLoadBinary(MI, MBB, SystemZ::OR, 32);
6213 case SystemZ::ATOMIC_LOAD_OILL:
6214 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILL, 32);
6215 case SystemZ::ATOMIC_LOAD_OILH:
6216 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILH, 32);
6217 case SystemZ::ATOMIC_LOAD_OILF:
6218 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILF, 32);
6219 case SystemZ::ATOMIC_LOAD_OGR:
6220 return emitAtomicLoadBinary(MI, MBB, SystemZ::OGR, 64);
6221 case SystemZ::ATOMIC_LOAD_OILL64:
6222 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILL64, 64);
6223 case SystemZ::ATOMIC_LOAD_OILH64:
6224 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILH64, 64);
6225 case SystemZ::ATOMIC_LOAD_OIHL64:
6226 return emitAtomicLoadBinary(MI, MBB, SystemZ::OIHL64, 64);
6227 case SystemZ::ATOMIC_LOAD_OIHH64:
6228 return emitAtomicLoadBinary(MI, MBB, SystemZ::OIHH64, 64);
6229 case SystemZ::ATOMIC_LOAD_OILF64:
6230 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILF64, 64);
6231 case SystemZ::ATOMIC_LOAD_OIHF64:
6232 return emitAtomicLoadBinary(MI, MBB, SystemZ::OIHF64, 64);
6234 case SystemZ::ATOMIC_LOADW_XR:
6235 return emitAtomicLoadBinary(MI, MBB, SystemZ::XR, 0);
6236 case SystemZ::ATOMIC_LOADW_XILF:
6237 return emitAtomicLoadBinary(MI, MBB, SystemZ::XILF, 0);
6238 case SystemZ::ATOMIC_LOAD_XR:
6239 return emitAtomicLoadBinary(MI, MBB, SystemZ::XR, 32);
6240 case SystemZ::ATOMIC_LOAD_XILF:
6241 return emitAtomicLoadBinary(MI, MBB, SystemZ::XILF, 32);
6242 case SystemZ::ATOMIC_LOAD_XGR:
6243 return emitAtomicLoadBinary(MI, MBB, SystemZ::XGR, 64);
6244 case SystemZ::ATOMIC_LOAD_XILF64:
6245 return emitAtomicLoadBinary(MI, MBB, SystemZ::XILF64, 64);
6246 case SystemZ::ATOMIC_LOAD_XIHF64:
6247 return emitAtomicLoadBinary(MI, MBB, SystemZ::XIHF64, 64);
6249 case SystemZ::ATOMIC_LOADW_NRi:
6250 return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 0, true);
6251 case SystemZ::ATOMIC_LOADW_NILHi:
6252 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 0, true);
6253 case SystemZ::ATOMIC_LOAD_NRi:
6254 return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 32, true);
6255 case SystemZ::ATOMIC_LOAD_NILLi:
6256 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL, 32, true);
6257 case SystemZ::ATOMIC_LOAD_NILHi:
6258 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 32, true);
6259 case SystemZ::ATOMIC_LOAD_NILFi:
6260 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF, 32, true);
6261 case SystemZ::ATOMIC_LOAD_NGRi:
6262 return emitAtomicLoadBinary(MI, MBB, SystemZ::NGR, 64, true);
6263 case SystemZ::ATOMIC_LOAD_NILL64i:
6264 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL64, 64, true);
6265 case SystemZ::ATOMIC_LOAD_NILH64i:
6266 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH64, 64, true);
6267 case SystemZ::ATOMIC_LOAD_NIHL64i:
6268 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHL64, 64, true);
6269 case SystemZ::ATOMIC_LOAD_NIHH64i:
6270 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHH64, 64, true);
6271 case SystemZ::ATOMIC_LOAD_NILF64i:
6272 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF64, 64, true);
6273 case SystemZ::ATOMIC_LOAD_NIHF64i:
6274 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHF64, 64, true);
6276 case SystemZ::ATOMIC_LOADW_MIN:
6277 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
6278 SystemZ::CCMASK_CMP_LE, 0);
6279 case SystemZ::ATOMIC_LOAD_MIN_32:
6280 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
6281 SystemZ::CCMASK_CMP_LE, 32);
6282 case SystemZ::ATOMIC_LOAD_MIN_64:
6283 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CGR,
6284 SystemZ::CCMASK_CMP_LE, 64);
6286 case SystemZ::ATOMIC_LOADW_MAX:
6287 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
6288 SystemZ::CCMASK_CMP_GE, 0);
6289 case SystemZ::ATOMIC_LOAD_MAX_32:
6290 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
6291 SystemZ::CCMASK_CMP_GE, 32);
6292 case SystemZ::ATOMIC_LOAD_MAX_64:
6293 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CGR,
6294 SystemZ::CCMASK_CMP_GE, 64);
6296 case SystemZ::ATOMIC_LOADW_UMIN:
6297 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
6298 SystemZ::CCMASK_CMP_LE, 0);
6299 case SystemZ::ATOMIC_LOAD_UMIN_32:
6300 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
6301 SystemZ::CCMASK_CMP_LE, 32);
6302 case SystemZ::ATOMIC_LOAD_UMIN_64:
6303 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLGR,
6304 SystemZ::CCMASK_CMP_LE, 64);
6306 case SystemZ::ATOMIC_LOADW_UMAX:
6307 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
6308 SystemZ::CCMASK_CMP_GE, 0);
6309 case SystemZ::ATOMIC_LOAD_UMAX_32:
6310 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
6311 SystemZ::CCMASK_CMP_GE, 32);
6312 case SystemZ::ATOMIC_LOAD_UMAX_64:
6313 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLGR,
6314 SystemZ::CCMASK_CMP_GE, 64);
6316 case SystemZ::ATOMIC_CMP_SWAPW:
6317 return emitAtomicCmpSwapW(MI, MBB);
6318 case SystemZ::MVCSequence:
6319 case SystemZ::MVCLoop:
6320 return emitMemMemWrapper(MI, MBB, SystemZ::MVC);
6321 case SystemZ::NCSequence:
6322 case SystemZ::NCLoop:
6323 return emitMemMemWrapper(MI, MBB, SystemZ::NC);
6324 case SystemZ::OCSequence:
6325 case SystemZ::OCLoop:
6326 return emitMemMemWrapper(MI, MBB, SystemZ::OC);
6327 case SystemZ::XCSequence:
6328 case SystemZ::XCLoop:
6329 return emitMemMemWrapper(MI, MBB, SystemZ::XC);
6330 case SystemZ::CLCSequence:
6331 case SystemZ::CLCLoop:
6332 return emitMemMemWrapper(MI, MBB, SystemZ::CLC);
6333 case SystemZ::CLSTLoop:
6334 return emitStringWrapper(MI, MBB, SystemZ::CLST);
6335 case SystemZ::MVSTLoop:
6336 return emitStringWrapper(MI, MBB, SystemZ::MVST);
6337 case SystemZ::SRSTLoop:
6338 return emitStringWrapper(MI, MBB, SystemZ::SRST);
6339 case SystemZ::TBEGIN:
6340 return emitTransactionBegin(MI, MBB, SystemZ::TBEGIN, false);
6341 case SystemZ::TBEGIN_nofloat:
6342 return emitTransactionBegin(MI, MBB, SystemZ::TBEGIN, true);
6343 case SystemZ::TBEGINC:
6344 return emitTransactionBegin(MI, MBB, SystemZ::TBEGINC, true);
6345 case SystemZ::LTEBRCompare_VecPseudo:
6346 return emitLoadAndTestCmp0(MI, MBB, SystemZ::LTEBR);
6347 case SystemZ::LTDBRCompare_VecPseudo:
6348 return emitLoadAndTestCmp0(MI, MBB, SystemZ::LTDBR);
6349 case SystemZ::LTXBRCompare_VecPseudo:
6350 return emitLoadAndTestCmp0(MI, MBB, SystemZ::LTXBR);
6353 llvm_unreachable("Unexpected instr type to insert");