1 //===-- SystemZISelLowering.h - SystemZ DAG lowering interface --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that SystemZ uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZISELLOWERING_H
16 #define LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZISELLOWERING_H
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/CodeGen/TargetLowering.h"
24 namespace SystemZISD {
25 enum NodeType : unsigned {
26 FIRST_NUMBER = ISD::BUILTIN_OP_END,
28 // Return with a flag operand. Operand 0 is the chain operand.
31 // Calls a function. Operand 0 is the chain operand and operand 1
32 // is the target address. The arguments start at operand 2.
33 // There is an optional glue operand at the end.
37 // TLS calls. Like regular calls, except operand 1 is the TLS symbol.
38 // (The call target is implicitly __tls_get_offset.)
42 // Wraps a TargetGlobalAddress that should be loaded using PC-relative
43 // accesses (LARL). Operand 0 is the address.
46 // Used in cases where an offset is applied to a TargetGlobalAddress.
47 // Operand 0 is the full TargetGlobalAddress and operand 1 is a
48 // PCREL_WRAPPER for an anchor point. This is used so that we can
49 // cheaply refer to either the full address or the anchor point
50 // as a register base.
56 // Integer comparisons. There are three operands: the two values
57 // to compare, and an integer of type SystemZICMP.
60 // Floating-point comparisons. The two operands are the values to compare.
63 // Test under mask. The first operand is ANDed with the second operand
64 // and the condition codes are set on the result. The third operand is
65 // a boolean that is true if the condition codes need to distinguish
66 // between CCMASK_TM_MIXED_MSB_0 and CCMASK_TM_MIXED_MSB_1 (which the
67 // register forms do but the memory forms don't).
70 // Branches if a condition is true. Operand 0 is the chain operand;
71 // operand 1 is the 4-bit condition-code mask, with bit N in
72 // big-endian order meaning "branch if CC=N"; operand 2 is the
73 // target block and operand 3 is the flag operand.
76 // Selects between operand 0 and operand 1. Operand 2 is the
77 // mask of condition-code values for which operand 0 should be
78 // chosen over operand 1; it has the same form as BR_CCMASK.
79 // Operand 3 is the flag operand.
82 // Evaluates to the gap between the stack pointer and the
83 // base of the dynamically-allocatable area.
86 // Count number of bits set in operand 0 per byte.
89 // Wrappers around the ISD opcodes of the same name. The output is GR128.
90 // Input operands may be GR64 or GR32, depending on the instruction.
96 // Use a series of MVCs to copy bytes from one memory location to another.
98 // - the target address
99 // - the source address
100 // - the constant length
102 // This isn't a memory opcode because we'd need to attach two
103 // MachineMemOperands rather than one.
106 // Like MVC, but implemented as a loop that handles X*256 bytes
107 // followed by straight-line code to handle the rest (if any).
108 // The value of X is passed as an additional operand.
111 // Similar to MVC and MVC_LOOP, but for logic operations (AND, OR, XOR).
119 // Use CLC to compare two blocks of memory, with the same comments
120 // as for MVC and MVC_LOOP.
124 // Use an MVST-based sequence to implement stpcpy().
127 // Use a CLST-based sequence to implement strcmp(). The two input operands
128 // are the addresses of the strings to compare.
131 // Use an SRST-based sequence to search a block of memory. The first
132 // operand is the end address, the second is the start, and the third
133 // is the character to search for. CC is set to 1 on success and 2
137 // Store the CC value in bits 29 and 28 of an integer.
140 // Compiler barrier only; generate a no-op.
143 // Transaction begin. The first operand is the chain, the second
144 // the TDB pointer, and the third the immediate control field.
145 // Returns chain and glue.
149 // Transaction end. Just the chain operand. Returns chain and glue.
152 // Create a vector constant by filling byte N of the result with bit
153 // 15-N of the single operand.
156 // Create a vector constant by replicating an element-sized RISBG-style mask.
157 // The first operand specifies the starting set bit and the second operand
158 // specifies the ending set bit. Both operands count from the MSB of the
162 // Replicate a GPR scalar value into all elements of a vector.
165 // Create a vector from two i64 GPRs.
168 // Replicate one element of a vector into all elements. The first operand
169 // is the vector and the second is the index of the element to replicate.
172 // Interleave elements from the high half of operand 0 and the high half
176 // Likewise for the low halves.
179 // Concatenate the vectors in the first two operands, shift them left
180 // by the third operand, and take the first half of the result.
183 // Take one element of the first v2i64 operand and the one element of
184 // the second v2i64 operand and concatenate them to form a v2i64 result.
185 // The third operand is a 4-bit value of the form 0A0B, where A and B
186 // are the element selectors for the first operand and second operands
190 // Perform a general vector permute on vector operands 0 and 1.
191 // Each byte of operand 2 controls the corresponding byte of the result,
192 // in the same way as a byte-level VECTOR_SHUFFLE mask.
195 // Pack vector operands 0 and 1 into a single vector with half-sized elements.
198 // Likewise, but saturate the result and set CC. PACKS_CC does signed
199 // saturation and PACKLS_CC does unsigned saturation.
203 // Unpack the first half of vector operand 0 into double-sized elements.
204 // UNPACK_HIGH sign-extends and UNPACKL_HIGH zero-extends.
208 // Likewise for the second half.
212 // Shift each element of vector operand 0 by the number of bits specified
213 // by scalar operand 1.
218 // For each element of the output type, sum across all sub-elements of
219 // operand 0 belonging to the corresponding element, and add in the
220 // rightmost sub-element of the corresponding element of operand 1.
223 // Compare integer vector operands 0 and 1 to produce the usual 0/-1
224 // vector result. VICMPE is for equality, VICMPH for "signed greater than"
225 // and VICMPHL for "unsigned greater than".
230 // Likewise, but also set the condition codes on the result.
235 // Compare floating-point vector operands 0 and 1 to preoduce the usual 0/-1
236 // vector result. VFCMPE is for "ordered and equal", VFCMPH for "ordered and
237 // greater than" and VFCMPHE for "ordered and greater than or equal to".
242 // Likewise, but also set the condition codes on the result.
247 // Test floating-point data class for vectors.
250 // Extend the even f32 elements of vector operand 0 to produce a vector
254 // Round the f64 elements of vector operand 0 to f32s and store them in the
255 // even elements of the result.
258 // AND the two vector operands together and set CC based on the result.
261 // String operations that set CC as a side-effect.
274 // Operand 0: the value to test
275 // Operand 1: the bit mask
278 // Wrappers around the inner loop of an 8- or 16-bit ATOMIC_SWAP or
281 // Operand 0: the address of the containing 32-bit-aligned field
282 // Operand 1: the second operand of <op>, in the high bits of an i32
283 // for everything except ATOMIC_SWAPW
284 // Operand 2: how many bits to rotate the i32 left to bring the first
285 // operand into the high bits
286 // Operand 3: the negative of operand 2, for rotating the other way
287 // Operand 4: the width of the field in bits (8 or 16)
288 ATOMIC_SWAPW = ISD::FIRST_TARGET_MEMORY_OPCODE,
300 // A wrapper around the inner loop of an ATOMIC_CMP_SWAP.
302 // Operand 0: the address of the containing 32-bit-aligned field
303 // Operand 1: the compare value, in the low bits of an i32
304 // Operand 2: the swap value, in the low bits of an i32
305 // Operand 3: how many bits to rotate the i32 left to bring the first
306 // operand into the high bits
307 // Operand 4: the negative of operand 2, for rotating the other way
308 // Operand 5: the width of the field in bits (8 or 16)
311 // Atomic compare-and-swap returning glue (condition code).
312 // Val, OUTCHAIN, glue = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap)
315 // 128-bit atomic load.
316 // Val, OUTCHAIN = ATOMIC_LOAD_128(INCHAIN, ptr)
319 // 128-bit atomic store.
320 // OUTCHAIN = ATOMIC_STORE_128(INCHAIN, val, ptr)
323 // 128-bit atomic compare-and-swap.
324 // Val, OUTCHAIN, glue = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap)
327 // Byte swapping load.
329 // Operand 0: the address to load from
330 // Operand 1: the type of load (i16, i32, i64)
333 // Byte swapping store.
335 // Operand 0: the value to store
336 // Operand 1: the address to store to
337 // Operand 2: the type of store (i16, i32, i64)
340 // Prefetch from the second operand using the 4-bit control code in
341 // the first operand. The code is 1 for a load prefetch and 2 for
346 // Return true if OPCODE is some kind of PC-relative address.
347 inline bool isPCREL(unsigned Opcode) {
348 return Opcode == PCREL_WRAPPER || Opcode == PCREL_OFFSET;
350 } // end namespace SystemZISD
352 namespace SystemZICMP {
353 // Describes whether an integer comparison needs to be signed or unsigned,
354 // or whether either type is OK.
360 } // end namespace SystemZICMP
362 class SystemZSubtarget;
363 class SystemZTargetMachine;
365 class SystemZTargetLowering : public TargetLowering {
367 explicit SystemZTargetLowering(const TargetMachine &TM,
368 const SystemZSubtarget &STI);
370 // Override TargetLowering.
371 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
374 MVT getVectorIdxTy(const DataLayout &DL) const override {
375 // Only the lower 12 bits of an element index are used, so we don't
376 // want to clobber the upper 32 bits of a GPR unnecessarily.
379 TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(EVT VT)
381 // Widen subvectors to the full width rather than promoting integer
382 // elements. This is better because:
384 // (a) it means that we can handle the ABI for passing and returning
385 // sub-128 vectors without having to handle them as legal types.
387 // (b) we don't have instructions to extend on load and truncate on store,
388 // so promoting the integers is less efficient.
390 // (c) there are no multiplication instructions for the widest integer
392 if (VT.getScalarSizeInBits() % 8 == 0)
393 return TypeWidenVector;
394 return TargetLoweringBase::getPreferredVectorAction(VT);
396 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &,
398 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
399 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
400 bool isLegalICmpImmediate(int64_t Imm) const override;
401 bool isLegalAddImmediate(int64_t Imm) const override;
402 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
404 Instruction *I = nullptr) const override;
405 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS,
407 bool *Fast) const override;
408 bool isTruncateFree(Type *, Type *) const override;
409 bool isTruncateFree(EVT, EVT) const override;
410 const char *getTargetNodeName(unsigned Opcode) const override;
411 std::pair<unsigned, const TargetRegisterClass *>
412 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
413 StringRef Constraint, MVT VT) const override;
414 TargetLowering::ConstraintType
415 getConstraintType(StringRef Constraint) const override;
416 TargetLowering::ConstraintWeight
417 getSingleConstraintMatchWeight(AsmOperandInfo &info,
418 const char *constraint) const override;
419 void LowerAsmOperandForConstraint(SDValue Op,
420 std::string &Constraint,
421 std::vector<SDValue> &Ops,
422 SelectionDAG &DAG) const override;
424 unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
425 if (ConstraintCode.size() == 1) {
426 switch(ConstraintCode[0]) {
430 return InlineAsm::Constraint_o;
432 return InlineAsm::Constraint_Q;
434 return InlineAsm::Constraint_R;
436 return InlineAsm::Constraint_S;
438 return InlineAsm::Constraint_T;
441 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
444 /// If a physical register, this returns the register that receives the
445 /// exception address on entry to an EH pad.
447 getExceptionPointerRegister(const Constant *PersonalityFn) const override {
451 /// If a physical register, this returns the register that receives the
452 /// exception typeid on entry to a landing pad.
454 getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
458 /// Override to support customized stack guard loading.
459 bool useLoadStackGuardNode() const override {
462 void insertSSPDeclarations(Module &M) const override {
466 EmitInstrWithCustomInserter(MachineInstr &MI,
467 MachineBasicBlock *BB) const override;
468 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
469 void LowerOperationWrapper(SDNode *N, SmallVectorImpl<SDValue> &Results,
470 SelectionDAG &DAG) const override;
471 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
472 SelectionDAG &DAG) const override;
473 bool allowTruncateForTailCall(Type *, Type *) const override;
474 bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
475 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
477 const SmallVectorImpl<ISD::InputArg> &Ins,
478 const SDLoc &DL, SelectionDAG &DAG,
479 SmallVectorImpl<SDValue> &InVals) const override;
480 SDValue LowerCall(CallLoweringInfo &CLI,
481 SmallVectorImpl<SDValue> &InVals) const override;
483 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
485 const SmallVectorImpl<ISD::OutputArg> &Outs,
486 LLVMContext &Context) const override;
487 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
488 const SmallVectorImpl<ISD::OutputArg> &Outs,
489 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
490 SelectionDAG &DAG) const override;
491 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
493 ISD::NodeType getExtendForAtomicOps() const override {
494 return ISD::ANY_EXTEND;
497 bool supportSwiftError() const override {
502 const SystemZSubtarget &Subtarget;
504 // Implement LowerOperation for individual opcodes.
505 SDValue getVectorCmp(SelectionDAG &DAG, unsigned Opcode,
506 const SDLoc &DL, EVT VT,
507 SDValue CmpOp0, SDValue CmpOp1) const;
508 SDValue lowerVectorSETCC(SelectionDAG &DAG, const SDLoc &DL,
509 EVT VT, ISD::CondCode CC,
510 SDValue CmpOp0, SDValue CmpOp1) const;
511 SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
512 SDValue lowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
513 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
514 SDValue lowerGlobalAddress(GlobalAddressSDNode *Node,
515 SelectionDAG &DAG) const;
516 SDValue lowerTLSGetOffset(GlobalAddressSDNode *Node,
517 SelectionDAG &DAG, unsigned Opcode,
518 SDValue GOTOffset) const;
519 SDValue lowerThreadPointer(const SDLoc &DL, SelectionDAG &DAG) const;
520 SDValue lowerGlobalTLSAddress(GlobalAddressSDNode *Node,
521 SelectionDAG &DAG) const;
522 SDValue lowerBlockAddress(BlockAddressSDNode *Node,
523 SelectionDAG &DAG) const;
524 SDValue lowerJumpTable(JumpTableSDNode *JT, SelectionDAG &DAG) const;
525 SDValue lowerConstantPool(ConstantPoolSDNode *CP, SelectionDAG &DAG) const;
526 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
527 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
528 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
529 SDValue lowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
530 SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
531 SDValue lowerGET_DYNAMIC_AREA_OFFSET(SDValue Op, SelectionDAG &DAG) const;
532 SDValue lowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
533 SDValue lowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
534 SDValue lowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
535 SDValue lowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
536 SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
537 SDValue lowerOR(SDValue Op, SelectionDAG &DAG) const;
538 SDValue lowerCTPOP(SDValue Op, SelectionDAG &DAG) const;
539 SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const;
540 SDValue lowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG) const;
541 SDValue lowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const;
542 SDValue lowerATOMIC_LOAD_OP(SDValue Op, SelectionDAG &DAG,
543 unsigned Opcode) const;
544 SDValue lowerATOMIC_LOAD_SUB(SDValue Op, SelectionDAG &DAG) const;
545 SDValue lowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
546 SDValue lowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const;
547 SDValue lowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const;
548 SDValue lowerPREFETCH(SDValue Op, SelectionDAG &DAG) const;
549 SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
550 SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
551 SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
552 SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
553 SDValue lowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
554 SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
555 SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
556 SDValue lowerExtendVectorInreg(SDValue Op, SelectionDAG &DAG,
557 unsigned UnpackHigh) const;
558 SDValue lowerShift(SDValue Op, SelectionDAG &DAG, unsigned ByScalar) const;
560 bool canTreatAsByteVector(EVT VT) const;
561 SDValue combineExtract(const SDLoc &DL, EVT ElemVT, EVT VecVT, SDValue OrigOp,
562 unsigned Index, DAGCombinerInfo &DCI,
564 SDValue combineTruncateExtract(const SDLoc &DL, EVT TruncVT, SDValue Op,
565 DAGCombinerInfo &DCI) const;
566 SDValue combineSIGN_EXTEND(SDNode *N, DAGCombinerInfo &DCI) const;
567 SDValue combineMERGE(SDNode *N, DAGCombinerInfo &DCI) const;
568 SDValue combineSTORE(SDNode *N, DAGCombinerInfo &DCI) const;
569 SDValue combineEXTRACT_VECTOR_ELT(SDNode *N, DAGCombinerInfo &DCI) const;
570 SDValue combineJOIN_DWORDS(SDNode *N, DAGCombinerInfo &DCI) const;
571 SDValue combineFP_ROUND(SDNode *N, DAGCombinerInfo &DCI) const;
572 SDValue combineBSWAP(SDNode *N, DAGCombinerInfo &DCI) const;
573 SDValue combineSHIFTROT(SDNode *N, DAGCombinerInfo &DCI) const;
575 // If the last instruction before MBBI in MBB was some form of COMPARE,
576 // try to replace it with a COMPARE AND BRANCH just before MBBI.
577 // CCMask and Target are the BRC-like operands for the branch.
578 // Return true if the change was made.
579 bool convertPrevCompareToBranch(MachineBasicBlock *MBB,
580 MachineBasicBlock::iterator MBBI,
582 MachineBasicBlock *Target) const;
584 // Implement EmitInstrWithCustomInserter for individual operation types.
585 MachineBasicBlock *emitSelect(MachineInstr &MI, MachineBasicBlock *BB,
586 unsigned LOCROpcode) const;
587 MachineBasicBlock *emitCondStore(MachineInstr &MI, MachineBasicBlock *BB,
588 unsigned StoreOpcode, unsigned STOCOpcode,
590 MachineBasicBlock *emitPair128(MachineInstr &MI,
591 MachineBasicBlock *MBB) const;
592 MachineBasicBlock *emitExt128(MachineInstr &MI, MachineBasicBlock *MBB,
593 bool ClearEven) const;
594 MachineBasicBlock *emitAtomicLoadBinary(MachineInstr &MI,
595 MachineBasicBlock *BB,
596 unsigned BinOpcode, unsigned BitSize,
597 bool Invert = false) const;
598 MachineBasicBlock *emitAtomicLoadMinMax(MachineInstr &MI,
599 MachineBasicBlock *MBB,
600 unsigned CompareOpcode,
601 unsigned KeepOldMask,
602 unsigned BitSize) const;
603 MachineBasicBlock *emitAtomicCmpSwapW(MachineInstr &MI,
604 MachineBasicBlock *BB) const;
605 MachineBasicBlock *emitMemMemWrapper(MachineInstr &MI, MachineBasicBlock *BB,
606 unsigned Opcode) const;
607 MachineBasicBlock *emitStringWrapper(MachineInstr &MI, MachineBasicBlock *BB,
608 unsigned Opcode) const;
609 MachineBasicBlock *emitTransactionBegin(MachineInstr &MI,
610 MachineBasicBlock *MBB,
611 unsigned Opcode, bool NoFloat) const;
612 MachineBasicBlock *emitLoadAndTestCmp0(MachineInstr &MI,
613 MachineBasicBlock *MBB,
614 unsigned Opcode) const;
616 const TargetRegisterClass *getRepRegClassFor(MVT VT) const override;
618 } // end namespace llvm