1 //==- SystemZInstrFormats.td - SystemZ Instruction Formats --*- tablegen -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Basic SystemZ instruction definition
12 //===----------------------------------------------------------------------===//
14 class InstSystemZ<int size, dag outs, dag ins, string asmstr,
15 list<dag> pattern> : Instruction {
16 let Namespace = "SystemZ";
18 dag OutOperandList = outs;
19 dag InOperandList = ins;
21 let Pattern = pattern;
22 let AsmString = asmstr;
24 // Some instructions come in pairs, one having a 12-bit displacement
25 // and the other having a 20-bit displacement. Both instructions in
26 // the pair have the same DispKey and their DispSizes are "12" and "20"
29 string DispSize = "none";
31 // Many register-based <INSN>R instructions have a memory-based <INSN>
32 // counterpart. OpKey uniquely identifies <INSN>R, while OpType is
33 // "reg" for <INSN>R and "mem" for <INSN>.
35 string OpType = "none";
37 // Many distinct-operands instructions have older 2-operand equivalents.
38 // NumOpsKey uniquely identifies one of these 2-operand and 3-operand pairs,
39 // with NumOpsValue being "2" or "3" as appropriate.
40 string NumOpsKey = "";
41 string NumOpsValue = "none";
43 // True if this instruction is a simple D(X,B) load of a register
44 // (with no sign or zero extension).
45 bit SimpleBDXLoad = 0;
47 // True if this instruction is a simple D(X,B) store of a register
48 // (with no truncation).
49 bit SimpleBDXStore = 0;
51 // True if this instruction has a 20-bit displacement field.
52 bit Has20BitOffset = 0;
54 // True if addresses in this instruction have an index register.
57 // True if this is a 128-bit pseudo instruction that combines two 64-bit
61 // The access size of all memory operands in bytes, or 0 if not known.
62 bits<5> AccessBytes = 0;
64 // If the instruction sets CC to a useful value, this gives the mask
65 // of all possible CC results. The mask has the same form as
69 // The subset of CCValues that have the same meaning as they would after
70 // a comparison of the first operand against zero.
71 bits<4> CompareZeroCCMask = 0;
73 // True if the instruction is conditional and if the CC mask operand
74 // comes first (as for BRC, etc.).
77 // Similar, but true if the CC mask operand comes last (as for LOC, etc.).
80 // True if the instruction is the "logical" rather than "arithmetic" form,
81 // in cases where a distinction exists.
84 let TSFlags{0} = SimpleBDXLoad;
85 let TSFlags{1} = SimpleBDXStore;
86 let TSFlags{2} = Has20BitOffset;
87 let TSFlags{3} = HasIndex;
88 let TSFlags{4} = Is128Bit;
89 let TSFlags{9-5} = AccessBytes;
90 let TSFlags{13-10} = CCValues;
91 let TSFlags{17-14} = CompareZeroCCMask;
92 let TSFlags{18} = CCMaskFirst;
93 let TSFlags{19} = CCMaskLast;
94 let TSFlags{20} = IsLogical;
97 //===----------------------------------------------------------------------===//
98 // Mappings between instructions
99 //===----------------------------------------------------------------------===//
101 // Return the version of an instruction that has an unsigned 12-bit
103 def getDisp12Opcode : InstrMapping {
104 let FilterClass = "InstSystemZ";
105 let RowFields = ["DispKey"];
106 let ColFields = ["DispSize"];
108 let ValueCols = [["12"]];
111 // Return the version of an instruction that has a signed 20-bit displacement.
112 def getDisp20Opcode : InstrMapping {
113 let FilterClass = "InstSystemZ";
114 let RowFields = ["DispKey"];
115 let ColFields = ["DispSize"];
117 let ValueCols = [["20"]];
120 // Return the memory form of a register instruction.
121 def getMemOpcode : InstrMapping {
122 let FilterClass = "InstSystemZ";
123 let RowFields = ["OpKey"];
124 let ColFields = ["OpType"];
125 let KeyCol = ["reg"];
126 let ValueCols = [["mem"]];
129 // Return the 3-operand form of a 2-operand instruction.
130 def getThreeOperandOpcode : InstrMapping {
131 let FilterClass = "InstSystemZ";
132 let RowFields = ["NumOpsKey"];
133 let ColFields = ["NumOpsValue"];
135 let ValueCols = [["3"]];
138 //===----------------------------------------------------------------------===//
139 // Instruction formats
140 //===----------------------------------------------------------------------===//
142 // Formats are specified using operand field declarations of the form:
144 // bits<4> Rn : register input or output for operand n
145 // bits<5> Vn : vector register input or output for operand n
146 // bits<m> In : immediate value of width m for operand n
147 // bits<4> BDn : address operand n, which has a base and a displacement
148 // bits<m> XBDn : address operand n, which has an index, a base and a
150 // bits<m> VBDn : address operand n, which has a vector index, a base and a
152 // bits<4> Xn : index register for address operand n
153 // bits<4> Mn : mode value for operand n
155 // The operand numbers ("n" in the list above) follow the architecture manual.
156 // Assembly operands sometimes have a different order; in particular, R3 often
157 // is often written between operands 1 and 2.
159 //===----------------------------------------------------------------------===//
161 class InstE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
162 : InstSystemZ<2, outs, ins, asmstr, pattern> {
164 field bits<16> SoftFail = 0;
169 class InstI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
170 : InstSystemZ<2, outs, ins, asmstr, pattern> {
172 field bits<16> SoftFail = 0;
180 class InstIE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
181 : InstSystemZ<4, outs, ins, asmstr, pattern> {
183 field bits<32> SoftFail = 0;
188 let Inst{31-16} = op;
194 class InstMII<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
195 : InstSystemZ<6, outs, ins, asmstr, pattern> {
197 field bits<48> SoftFail = 0;
203 let Inst{47-40} = op;
204 let Inst{39-36} = M1;
205 let Inst{35-24} = RI2;
206 let Inst{23-0} = RI3;
209 class InstRIa<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
210 : InstSystemZ<4, outs, ins, asmstr, pattern> {
212 field bits<32> SoftFail = 0;
217 let Inst{31-24} = op{11-4};
218 let Inst{23-20} = R1;
219 let Inst{19-16} = op{3-0};
223 class InstRIb<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
224 : InstSystemZ<4, outs, ins, asmstr, pattern> {
226 field bits<32> SoftFail = 0;
231 let Inst{31-24} = op{11-4};
232 let Inst{23-20} = R1;
233 let Inst{19-16} = op{3-0};
234 let Inst{15-0} = RI2;
237 class InstRIc<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
238 : InstSystemZ<4, outs, ins, asmstr, pattern> {
240 field bits<32> SoftFail = 0;
245 let Inst{31-24} = op{11-4};
246 let Inst{23-20} = M1;
247 let Inst{19-16} = op{3-0};
248 let Inst{15-0} = RI2;
251 class InstRIEa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
252 : InstSystemZ<6, outs, ins, asmstr, pattern> {
254 field bits<48> SoftFail = 0;
260 let Inst{47-40} = op{15-8};
261 let Inst{39-36} = R1;
263 let Inst{31-16} = I2;
264 let Inst{15-12} = M3;
266 let Inst{7-0} = op{7-0};
269 class InstRIEb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
270 : InstSystemZ<6, outs, ins, asmstr, pattern> {
272 field bits<48> SoftFail = 0;
279 let Inst{47-40} = op{15-8};
280 let Inst{39-36} = R1;
281 let Inst{35-32} = R2;
282 let Inst{31-16} = RI4;
283 let Inst{15-12} = M3;
285 let Inst{7-0} = op{7-0};
288 class InstRIEc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
289 : InstSystemZ<6, outs, ins, asmstr, pattern> {
291 field bits<48> SoftFail = 0;
298 let Inst{47-40} = op{15-8};
299 let Inst{39-36} = R1;
300 let Inst{35-32} = M3;
301 let Inst{31-16} = RI4;
303 let Inst{7-0} = op{7-0};
306 class InstRIEd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
307 : InstSystemZ<6, outs, ins, asmstr, pattern> {
309 field bits<48> SoftFail = 0;
315 let Inst{47-40} = op{15-8};
316 let Inst{39-36} = R1;
317 let Inst{35-32} = R3;
318 let Inst{31-16} = I2;
320 let Inst{7-0} = op{7-0};
323 class InstRIEe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
324 : InstSystemZ<6, outs, ins, asmstr, pattern> {
326 field bits<48> SoftFail = 0;
332 let Inst{47-40} = op{15-8};
333 let Inst{39-36} = R1;
334 let Inst{35-32} = R3;
335 let Inst{31-16} = RI2;
337 let Inst{7-0} = op{7-0};
340 class InstRIEf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
341 : InstSystemZ<6, outs, ins, asmstr, pattern> {
343 field bits<48> SoftFail = 0;
351 let Inst{47-40} = op{15-8};
352 let Inst{39-36} = R1;
353 let Inst{35-32} = R2;
354 let Inst{31-24} = I3;
355 let Inst{23-16} = I4;
357 let Inst{7-0} = op{7-0};
360 class InstRIEg<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
361 : InstSystemZ<6, outs, ins, asmstr, pattern> {
363 field bits<48> SoftFail = 0;
369 let Inst{47-40} = op{15-8};
370 let Inst{39-36} = R1;
371 let Inst{35-32} = M3;
372 let Inst{31-16} = I2;
374 let Inst{7-0} = op{7-0};
377 class InstRILa<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
378 : InstSystemZ<6, outs, ins, asmstr, pattern> {
380 field bits<48> SoftFail = 0;
385 let Inst{47-40} = op{11-4};
386 let Inst{39-36} = R1;
387 let Inst{35-32} = op{3-0};
391 class InstRILb<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
392 : InstSystemZ<6, outs, ins, asmstr, pattern> {
394 field bits<48> SoftFail = 0;
399 let Inst{47-40} = op{11-4};
400 let Inst{39-36} = R1;
401 let Inst{35-32} = op{3-0};
402 let Inst{31-0} = RI2;
405 class InstRILc<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
406 : InstSystemZ<6, outs, ins, asmstr, pattern> {
408 field bits<48> SoftFail = 0;
413 let Inst{47-40} = op{11-4};
414 let Inst{39-36} = M1;
415 let Inst{35-32} = op{3-0};
416 let Inst{31-0} = RI2;
419 class InstRIS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
420 : InstSystemZ<6, outs, ins, asmstr, pattern> {
422 field bits<48> SoftFail = 0;
429 let Inst{47-40} = op{15-8};
430 let Inst{39-36} = R1;
431 let Inst{35-32} = M3;
432 let Inst{31-16} = BD4;
434 let Inst{7-0} = op{7-0};
437 class InstRR<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
438 : InstSystemZ<2, outs, ins, asmstr, pattern> {
440 field bits<16> SoftFail = 0;
450 class InstRRD<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
451 : InstSystemZ<4, outs, ins, asmstr, pattern> {
453 field bits<32> SoftFail = 0;
459 let Inst{31-16} = op;
460 let Inst{15-12} = R1;
466 class InstRRE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
467 : InstSystemZ<4, outs, ins, asmstr, pattern> {
469 field bits<32> SoftFail = 0;
474 let Inst{31-16} = op;
480 class InstRRFa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
481 : InstSystemZ<4, outs, ins, asmstr, pattern> {
483 field bits<32> SoftFail = 0;
490 let Inst{31-16} = op;
491 let Inst{15-12} = R3;
497 class InstRRFb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
498 : InstSystemZ<4, outs, ins, asmstr, pattern> {
500 field bits<32> SoftFail = 0;
507 let Inst{31-16} = op;
508 let Inst{15-12} = R3;
514 class InstRRFc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
515 : InstSystemZ<4, outs, ins, asmstr, pattern> {
517 field bits<32> SoftFail = 0;
523 let Inst{31-16} = op;
524 let Inst{15-12} = M3;
530 class InstRRFd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
531 : InstSystemZ<4, outs, ins, asmstr, pattern> {
533 field bits<32> SoftFail = 0;
539 let Inst{31-16} = op;
546 class InstRRFe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
547 : InstSystemZ<4, outs, ins, asmstr, pattern> {
549 field bits<32> SoftFail = 0;
556 let Inst{31-16} = op;
557 let Inst{15-12} = M3;
563 class InstRRS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
564 : InstSystemZ<6, outs, ins, asmstr, pattern> {
566 field bits<48> SoftFail = 0;
573 let Inst{47-40} = op{15-8};
574 let Inst{39-36} = R1;
575 let Inst{35-32} = R2;
576 let Inst{31-16} = BD4;
577 let Inst{15-12} = M3;
579 let Inst{7-0} = op{7-0};
582 class InstRXa<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
583 : InstSystemZ<4, outs, ins, asmstr, pattern> {
585 field bits<32> SoftFail = 0;
590 let Inst{31-24} = op;
591 let Inst{23-20} = R1;
592 let Inst{19-0} = XBD2;
597 class InstRXb<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
598 : InstSystemZ<4, outs, ins, asmstr, pattern> {
600 field bits<32> SoftFail = 0;
605 let Inst{31-24} = op;
606 let Inst{23-20} = M1;
607 let Inst{19-0} = XBD2;
612 class InstRXE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
613 : InstSystemZ<6, outs, ins, asmstr, pattern> {
615 field bits<48> SoftFail = 0;
621 let Inst{47-40} = op{15-8};
622 let Inst{39-36} = R1;
623 let Inst{35-16} = XBD2;
624 let Inst{15-12} = M3;
626 let Inst{7-0} = op{7-0};
631 class InstRXF<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
632 : InstSystemZ<6, outs, ins, asmstr, pattern> {
634 field bits<48> SoftFail = 0;
640 let Inst{47-40} = op{15-8};
641 let Inst{39-36} = R3;
642 let Inst{35-16} = XBD2;
643 let Inst{15-12} = R1;
645 let Inst{7-0} = op{7-0};
650 class InstRXYa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
651 : InstSystemZ<6, outs, ins, asmstr, pattern> {
653 field bits<48> SoftFail = 0;
658 let Inst{47-40} = op{15-8};
659 let Inst{39-36} = R1;
660 let Inst{35-8} = XBD2;
661 let Inst{7-0} = op{7-0};
663 let Has20BitOffset = 1;
667 class InstRXYb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
668 : InstSystemZ<6, outs, ins, asmstr, pattern> {
670 field bits<48> SoftFail = 0;
675 let Inst{47-40} = op{15-8};
676 let Inst{39-36} = M1;
677 let Inst{35-8} = XBD2;
678 let Inst{7-0} = op{7-0};
680 let Has20BitOffset = 1;
684 class InstRSa<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
685 : InstSystemZ<4, outs, ins, asmstr, pattern> {
687 field bits<32> SoftFail = 0;
693 let Inst{31-24} = op;
694 let Inst{23-20} = R1;
695 let Inst{19-16} = R3;
696 let Inst{15-0} = BD2;
699 class InstRSb<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
700 : InstSystemZ<4, outs, ins, asmstr, pattern> {
702 field bits<32> SoftFail = 0;
708 let Inst{31-24} = op;
709 let Inst{23-20} = R1;
710 let Inst{19-16} = M3;
711 let Inst{15-0} = BD2;
714 class InstRSI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
715 : InstSystemZ<4, outs, ins, asmstr, pattern> {
717 field bits<32> SoftFail = 0;
723 let Inst{31-24} = op;
724 let Inst{23-20} = R1;
725 let Inst{19-16} = R3;
726 let Inst{15-0} = RI2;
729 class InstRSLa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
730 : InstSystemZ<6, outs, ins, asmstr, pattern> {
732 field bits<48> SoftFail = 0;
736 let Inst{47-40} = op{15-8};
737 let Inst{39-36} = BDL1{19-16};
739 let Inst{31-16} = BDL1{15-0};
741 let Inst{7-0} = op{7-0};
744 class InstRSLb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
745 : InstSystemZ<6, outs, ins, asmstr, pattern> {
747 field bits<48> SoftFail = 0;
753 let Inst{47-40} = op{15-8};
754 let Inst{39-16} = BDL2;
755 let Inst{15-12} = R1;
757 let Inst{7-0} = op{7-0};
760 class InstRSYa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
761 : InstSystemZ<6, outs, ins, asmstr, pattern> {
763 field bits<48> SoftFail = 0;
769 let Inst{47-40} = op{15-8};
770 let Inst{39-36} = R1;
771 let Inst{35-32} = R3;
772 let Inst{31-8} = BD2;
773 let Inst{7-0} = op{7-0};
775 let Has20BitOffset = 1;
778 class InstRSYb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
779 : InstSystemZ<6, outs, ins, asmstr, pattern> {
781 field bits<48> SoftFail = 0;
787 let Inst{47-40} = op{15-8};
788 let Inst{39-36} = R1;
789 let Inst{35-32} = M3;
790 let Inst{31-8} = BD2;
791 let Inst{7-0} = op{7-0};
793 let Has20BitOffset = 1;
796 class InstSI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
797 : InstSystemZ<4, outs, ins, asmstr, pattern> {
799 field bits<32> SoftFail = 0;
804 let Inst{31-24} = op;
805 let Inst{23-16} = I2;
806 let Inst{15-0} = BD1;
809 class InstSIL<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
810 : InstSystemZ<6, outs, ins, asmstr, pattern> {
812 field bits<48> SoftFail = 0;
817 let Inst{47-32} = op;
818 let Inst{31-16} = BD1;
822 class InstSIY<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
823 : InstSystemZ<6, outs, ins, asmstr, pattern> {
825 field bits<48> SoftFail = 0;
830 let Inst{47-40} = op{15-8};
831 let Inst{39-32} = I2;
832 let Inst{31-8} = BD1;
833 let Inst{7-0} = op{7-0};
835 let Has20BitOffset = 1;
838 class InstSMI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
839 : InstSystemZ<6, outs, ins, asmstr, pattern> {
841 field bits<48> SoftFail = 0;
847 let Inst{47-40} = op;
848 let Inst{39-36} = M1;
850 let Inst{31-16} = BD3;
851 let Inst{15-0} = RI2;
854 class InstSSa<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
855 : InstSystemZ<6, outs, ins, asmstr, pattern> {
857 field bits<48> SoftFail = 0;
862 let Inst{47-40} = op;
863 let Inst{39-16} = BDL1;
864 let Inst{15-0} = BD2;
867 class InstSSb<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
868 : InstSystemZ<6, outs, ins, asmstr, pattern> {
870 field bits<48> SoftFail = 0;
875 let Inst{47-40} = op;
876 let Inst{39-36} = BDL1{19-16};
877 let Inst{35-32} = BDL2{19-16};
878 let Inst{31-16} = BDL1{15-0};
879 let Inst{15-0} = BDL2{15-0};
882 class InstSSc<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
883 : InstSystemZ<6, outs, ins, asmstr, pattern> {
885 field bits<48> SoftFail = 0;
891 let Inst{47-40} = op;
892 let Inst{39-36} = BDL1{19-16};
893 let Inst{35-32} = I3;
894 let Inst{31-16} = BDL1{15-0};
895 let Inst{15-0} = BD2;
898 class InstSSd<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
899 : InstSystemZ<6, outs, ins, asmstr, pattern> {
901 field bits<48> SoftFail = 0;
907 let Inst{47-40} = op;
908 let Inst{39-36} = RBD1{19-16};
909 let Inst{35-32} = R3;
910 let Inst{31-16} = RBD1{15-0};
911 let Inst{15-0} = BD2;
914 class InstSSe<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
915 : InstSystemZ<6, outs, ins, asmstr, pattern> {
917 field bits<48> SoftFail = 0;
924 let Inst{47-40} = op;
925 let Inst{39-36} = R1;
926 let Inst{35-32} = R3;
927 let Inst{31-16} = BD2;
928 let Inst{15-0} = BD4;
931 class InstSSf<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
932 : InstSystemZ<6, outs, ins, asmstr, pattern> {
934 field bits<48> SoftFail = 0;
939 let Inst{47-40} = op;
940 let Inst{39-32} = BDL2{23-16};
941 let Inst{31-16} = BD1;
942 let Inst{15-0} = BDL2{15-0};
945 class InstSSE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
946 : InstSystemZ<6, outs, ins, asmstr, pattern> {
948 field bits<48> SoftFail = 0;
953 let Inst{47-32} = op;
954 let Inst{31-16} = BD1;
955 let Inst{15-0} = BD2;
958 class InstSSF<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
959 : InstSystemZ<6, outs, ins, asmstr, pattern> {
961 field bits<48> SoftFail = 0;
967 let Inst{47-40} = op{11-4};
968 let Inst{39-36} = R3;
969 let Inst{35-32} = op{3-0};
970 let Inst{31-16} = BD1;
971 let Inst{15-0} = BD2;
974 class InstS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
975 : InstSystemZ<4, outs, ins, asmstr, pattern> {
977 field bits<32> SoftFail = 0;
981 let Inst{31-16} = op;
982 let Inst{15-0} = BD2;
985 class InstVRIa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
986 : InstSystemZ<6, outs, ins, asmstr, pattern> {
988 field bits<48> SoftFail = 0;
994 let Inst{47-40} = op{15-8};
995 let Inst{39-36} = V1{3-0};
997 let Inst{31-16} = I2;
998 let Inst{15-12} = M3;
999 let Inst{11} = V1{4};
1001 let Inst{7-0} = op{7-0};
1004 class InstVRIb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1005 : InstSystemZ<6, outs, ins, asmstr, pattern> {
1006 field bits<48> Inst;
1007 field bits<48> SoftFail = 0;
1014 let Inst{47-40} = op{15-8};
1015 let Inst{39-36} = V1{3-0};
1016 let Inst{35-32} = 0;
1017 let Inst{31-24} = I2;
1018 let Inst{23-16} = I3;
1019 let Inst{15-12} = M4;
1020 let Inst{11} = V1{4};
1022 let Inst{7-0} = op{7-0};
1025 class InstVRIc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1026 : InstSystemZ<6, outs, ins, asmstr, pattern> {
1027 field bits<48> Inst;
1028 field bits<48> SoftFail = 0;
1035 let Inst{47-40} = op{15-8};
1036 let Inst{39-36} = V1{3-0};
1037 let Inst{35-32} = V3{3-0};
1038 let Inst{31-16} = I2;
1039 let Inst{15-12} = M4;
1040 let Inst{11} = V1{4};
1041 let Inst{10} = V3{4};
1043 let Inst{7-0} = op{7-0};
1046 class InstVRId<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1047 : InstSystemZ<6, outs, ins, asmstr, pattern> {
1048 field bits<48> Inst;
1049 field bits<48> SoftFail = 0;
1057 let Inst{47-40} = op{15-8};
1058 let Inst{39-36} = V1{3-0};
1059 let Inst{35-32} = V2{3-0};
1060 let Inst{31-28} = V3{3-0};
1061 let Inst{27-24} = 0;
1062 let Inst{23-16} = I4;
1063 let Inst{15-12} = M5;
1064 let Inst{11} = V1{4};
1065 let Inst{10} = V2{4};
1066 let Inst{9} = V3{4};
1068 let Inst{7-0} = op{7-0};
1071 class InstVRIe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1072 : InstSystemZ<6, outs, ins, asmstr, pattern> {
1073 field bits<48> Inst;
1074 field bits<48> SoftFail = 0;
1082 let Inst{47-40} = op{15-8};
1083 let Inst{39-36} = V1{3-0};
1084 let Inst{35-32} = V2{3-0};
1085 let Inst{31-20} = I3;
1086 let Inst{19-16} = M5;
1087 let Inst{15-12} = M4;
1088 let Inst{11} = V1{4};
1089 let Inst{10} = V2{4};
1091 let Inst{7-0} = op{7-0};
1094 class InstVRIf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1095 : InstSystemZ<6, outs, ins, asmstr, pattern> {
1096 field bits<48> Inst;
1097 field bits<48> SoftFail = 0;
1105 let Inst{47-40} = op{15-8};
1106 let Inst{39-36} = V1{3-0};
1107 let Inst{35-32} = V2{3-0};
1108 let Inst{31-28} = V3{3-0};
1109 let Inst{27-24} = 0;
1110 let Inst{23-20} = M5;
1111 let Inst{19-12} = I4;
1112 let Inst{11} = V1{4};
1113 let Inst{10} = V2{4};
1114 let Inst{9} = V3{4};
1116 let Inst{7-0} = op{7-0};
1119 class InstVRIg<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1120 : InstSystemZ<6, outs, ins, asmstr, pattern> {
1121 field bits<48> Inst;
1122 field bits<48> SoftFail = 0;
1130 let Inst{47-40} = op{15-8};
1131 let Inst{39-36} = V1{3-0};
1132 let Inst{35-32} = V2{3-0};
1133 let Inst{31-24} = I4;
1134 let Inst{23-20} = M5;
1135 let Inst{19-12} = I3;
1136 let Inst{11} = V1{4};
1137 let Inst{10} = V2{4};
1139 let Inst{7-0} = op{7-0};
1142 class InstVRIh<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1143 : InstSystemZ<6, outs, ins, asmstr, pattern> {
1144 field bits<48> Inst;
1145 field bits<48> SoftFail = 0;
1151 let Inst{47-40} = op{15-8};
1152 let Inst{39-36} = V1{3-0};
1153 let Inst{35-32} = 0;
1154 let Inst{31-16} = I2;
1155 let Inst{15-12} = I3;
1156 let Inst{11} = V1{4};
1158 let Inst{7-0} = op{7-0};
1161 class InstVRIi<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1162 : InstSystemZ<6, outs, ins, asmstr, pattern> {
1163 field bits<48> Inst;
1164 field bits<48> SoftFail = 0;
1171 let Inst{47-40} = op{15-8};
1172 let Inst{39-36} = V1{3-0};
1173 let Inst{35-32} = R2;
1174 let Inst{31-24} = 0;
1175 let Inst{23-20} = M4;
1176 let Inst{19-12} = I3;
1177 let Inst{11} = V1{4};
1179 let Inst{7-0} = op{7-0};
1182 // Depending on the instruction mnemonic, certain bits may be or-ed into
1183 // the M4 value provided as explicit operand. These are passed as m4or.
1184 class InstVRRa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern,
1186 : InstSystemZ<6, outs, ins, asmstr, pattern> {
1187 field bits<48> Inst;
1188 field bits<48> SoftFail = 0;
1196 let Inst{47-40} = op{15-8};
1197 let Inst{39-36} = V1{3-0};
1198 let Inst{35-32} = V2{3-0};
1199 let Inst{31-24} = 0;
1200 let Inst{23-20} = M5;
1201 let Inst{19} = !if (!eq (m4or{3}, 1), 1, M4{3});
1202 let Inst{18} = !if (!eq (m4or{2}, 1), 1, M4{2});
1203 let Inst{17} = !if (!eq (m4or{1}, 1), 1, M4{1});
1204 let Inst{16} = !if (!eq (m4or{0}, 1), 1, M4{0});
1205 let Inst{15-12} = M3;
1206 let Inst{11} = V1{4};
1207 let Inst{10} = V2{4};
1209 let Inst{7-0} = op{7-0};
1212 // Depending on the instruction mnemonic, certain bits may be or-ed into
1213 // the M5 value provided as explicit operand. These are passed as m5or.
1214 class InstVRRb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern,
1216 : InstSystemZ<6, outs, ins, asmstr, pattern> {
1217 field bits<48> Inst;
1218 field bits<48> SoftFail = 0;
1226 let Inst{47-40} = op{15-8};
1227 let Inst{39-36} = V1{3-0};
1228 let Inst{35-32} = V2{3-0};
1229 let Inst{31-28} = V3{3-0};
1230 let Inst{27-24} = 0;
1231 let Inst{23} = !if (!eq (m5or{3}, 1), 1, M5{3});
1232 let Inst{22} = !if (!eq (m5or{2}, 1), 1, M5{2});
1233 let Inst{21} = !if (!eq (m5or{1}, 1), 1, M5{1});
1234 let Inst{20} = !if (!eq (m5or{0}, 1), 1, M5{0});
1235 let Inst{19-16} = 0;
1236 let Inst{15-12} = M4;
1237 let Inst{11} = V1{4};
1238 let Inst{10} = V2{4};
1239 let Inst{9} = V3{4};
1241 let Inst{7-0} = op{7-0};
1244 class InstVRRc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1245 : InstSystemZ<6, outs, ins, asmstr, pattern> {
1246 field bits<48> Inst;
1247 field bits<48> SoftFail = 0;
1256 let Inst{47-40} = op{15-8};
1257 let Inst{39-36} = V1{3-0};
1258 let Inst{35-32} = V2{3-0};
1259 let Inst{31-28} = V3{3-0};
1260 let Inst{27-24} = 0;
1261 let Inst{23-20} = M6;
1262 let Inst{19-16} = M5;
1263 let Inst{15-12} = M4;
1264 let Inst{11} = V1{4};
1265 let Inst{10} = V2{4};
1266 let Inst{9} = V3{4};
1268 let Inst{7-0} = op{7-0};
1271 // Depending on the instruction mnemonic, certain bits may be or-ed into
1272 // the M6 value provided as explicit operand. These are passed as m6or.
1273 class InstVRRd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern,
1275 : InstSystemZ<6, outs, ins, asmstr, pattern> {
1276 field bits<48> Inst;
1277 field bits<48> SoftFail = 0;
1286 let Inst{47-40} = op{15-8};
1287 let Inst{39-36} = V1{3-0};
1288 let Inst{35-32} = V2{3-0};
1289 let Inst{31-28} = V3{3-0};
1290 let Inst{27-24} = M5;
1291 let Inst{23} = !if (!eq (m6or{3}, 1), 1, M6{3});
1292 let Inst{22} = !if (!eq (m6or{2}, 1), 1, M6{2});
1293 let Inst{21} = !if (!eq (m6or{1}, 1), 1, M6{1});
1294 let Inst{20} = !if (!eq (m6or{0}, 1), 1, M6{0});
1295 let Inst{19-16} = 0;
1296 let Inst{15-12} = V4{3-0};
1297 let Inst{11} = V1{4};
1298 let Inst{10} = V2{4};
1299 let Inst{9} = V3{4};
1300 let Inst{8} = V4{4};
1301 let Inst{7-0} = op{7-0};
1304 class InstVRRe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1305 : InstSystemZ<6, outs, ins, asmstr, pattern> {
1306 field bits<48> Inst;
1307 field bits<48> SoftFail = 0;
1316 let Inst{47-40} = op{15-8};
1317 let Inst{39-36} = V1{3-0};
1318 let Inst{35-32} = V2{3-0};
1319 let Inst{31-28} = V3{3-0};
1320 let Inst{27-24} = M6;
1321 let Inst{23-20} = 0;
1322 let Inst{19-16} = M5;
1323 let Inst{15-12} = V4{3-0};
1324 let Inst{11} = V1{4};
1325 let Inst{10} = V2{4};
1326 let Inst{9} = V3{4};
1327 let Inst{8} = V4{4};
1328 let Inst{7-0} = op{7-0};
1331 class InstVRRf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1332 : InstSystemZ<6, outs, ins, asmstr, pattern> {
1333 field bits<48> Inst;
1334 field bits<48> SoftFail = 0;
1340 let Inst{47-40} = op{15-8};
1341 let Inst{39-36} = V1{3-0};
1342 let Inst{35-32} = R2;
1343 let Inst{31-28} = R3;
1344 let Inst{27-12} = 0;
1345 let Inst{11} = V1{4};
1347 let Inst{7-0} = op{7-0};
1350 class InstVRRg<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1351 : InstSystemZ<6, outs, ins, asmstr, pattern> {
1352 field bits<48> Inst;
1353 field bits<48> SoftFail = 0;
1357 let Inst{47-40} = op{15-8};
1358 let Inst{39-36} = 0;
1359 let Inst{35-32} = V1{3-0};
1360 let Inst{31-12} = 0;
1362 let Inst{10} = V1{4};
1364 let Inst{7-0} = op{7-0};
1367 class InstVRRh<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1368 : InstSystemZ<6, outs, ins, asmstr, pattern> {
1369 field bits<48> Inst;
1370 field bits<48> SoftFail = 0;
1376 let Inst{47-40} = op{15-8};
1377 let Inst{39-36} = 0;
1378 let Inst{35-32} = V1{3-0};
1379 let Inst{31-28} = V2{3-0};
1380 let Inst{27-24} = 0;
1381 let Inst{23-20} = M3;
1382 let Inst{19-12} = 0;
1384 let Inst{10} = V1{4};
1385 let Inst{9} = V2{4};
1387 let Inst{7-0} = op{7-0};
1390 class InstVRRi<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1391 : InstSystemZ<6, outs, ins, asmstr, pattern> {
1392 field bits<48> Inst;
1393 field bits<48> SoftFail = 0;
1399 let Inst{47-40} = op{15-8};
1400 let Inst{39-36} = R1;
1401 let Inst{35-32} = V2{3-0};
1402 let Inst{31-24} = 0;
1403 let Inst{23-20} = M3;
1404 let Inst{19-12} = 0;
1406 let Inst{10} = V2{4};
1408 let Inst{7-0} = op{7-0};
1411 class InstVRSa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1412 : InstSystemZ<6, outs, ins, asmstr, pattern> {
1413 field bits<48> Inst;
1414 field bits<48> SoftFail = 0;
1421 let Inst{47-40} = op{15-8};
1422 let Inst{39-36} = V1{3-0};
1423 let Inst{35-32} = V3{3-0};
1424 let Inst{31-16} = BD2;
1425 let Inst{15-12} = M4;
1426 let Inst{11} = V1{4};
1427 let Inst{10} = V3{4};
1429 let Inst{7-0} = op{7-0};
1432 class InstVRSb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1433 : InstSystemZ<6, outs, ins, asmstr, pattern> {
1434 field bits<48> Inst;
1435 field bits<48> SoftFail = 0;
1442 let Inst{47-40} = op{15-8};
1443 let Inst{39-36} = V1{3-0};
1444 let Inst{35-32} = R3;
1445 let Inst{31-16} = BD2;
1446 let Inst{15-12} = M4;
1447 let Inst{11} = V1{4};
1449 let Inst{7-0} = op{7-0};
1452 class InstVRSc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1453 : InstSystemZ<6, outs, ins, asmstr, pattern> {
1454 field bits<48> Inst;
1455 field bits<48> SoftFail = 0;
1462 let Inst{47-40} = op{15-8};
1463 let Inst{39-36} = R1;
1464 let Inst{35-32} = V3{3-0};
1465 let Inst{31-16} = BD2;
1466 let Inst{15-12} = M4;
1468 let Inst{10} = V3{4};
1470 let Inst{7-0} = op{7-0};
1473 class InstVRSd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1474 : InstSystemZ<6, outs, ins, asmstr, pattern> {
1475 field bits<48> Inst;
1476 field bits<48> SoftFail = 0;
1482 let Inst{47-40} = op{15-8};
1483 let Inst{39-36} = 0;
1484 let Inst{35-32} = R3;
1485 let Inst{31-16} = BD2;
1486 let Inst{15-12} = V1{3-0};
1488 let Inst{8} = V1{4};
1489 let Inst{7-0} = op{7-0};
1492 class InstVRV<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1493 : InstSystemZ<6, outs, ins, asmstr, pattern> {
1494 field bits<48> Inst;
1495 field bits<48> SoftFail = 0;
1501 let Inst{47-40} = op{15-8};
1502 let Inst{39-36} = V1{3-0};
1503 let Inst{35-16} = VBD2{19-0};
1504 let Inst{15-12} = M3;
1505 let Inst{11} = V1{4};
1506 let Inst{10} = VBD2{20};
1508 let Inst{7-0} = op{7-0};
1511 class InstVRX<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1512 : InstSystemZ<6, outs, ins, asmstr, pattern> {
1513 field bits<48> Inst;
1514 field bits<48> SoftFail = 0;
1520 let Inst{47-40} = op{15-8};
1521 let Inst{39-36} = V1{3-0};
1522 let Inst{35-16} = XBD2;
1523 let Inst{15-12} = M3;
1524 let Inst{11} = V1{4};
1526 let Inst{7-0} = op{7-0};
1529 class InstVSI<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1530 : InstSystemZ<6, outs, ins, asmstr, pattern> {
1531 field bits<48> Inst;
1532 field bits<48> SoftFail = 0;
1538 let Inst{47-40} = op{15-8};
1539 let Inst{39-32} = I3;
1540 let Inst{31-16} = BD2;
1541 let Inst{15-12} = V1{3-0};
1543 let Inst{8} = V1{4};
1544 let Inst{7-0} = op{7-0};
1547 //===----------------------------------------------------------------------===//
1548 // Instruction classes for .insn directives
1549 //===----------------------------------------------------------------------===//
1551 class DirectiveInsnE<dag outs, dag ins, string asmstr, list<dag> pattern>
1552 : InstE<0, outs, ins, asmstr, pattern> {
1558 class DirectiveInsnRI<dag outs, dag ins, string asmstr, list<dag> pattern>
1559 : InstRIa<0, outs, ins, asmstr, pattern> {
1562 let Inst{31-24} = enc{31-24};
1563 let Inst{19-16} = enc{19-16};
1566 class DirectiveInsnRIE<dag outs, dag ins, string asmstr, list<dag> pattern>
1567 : InstRIEd<0, outs, ins, asmstr, pattern> {
1570 let Inst{47-40} = enc{47-40};
1571 let Inst{7-0} = enc{7-0};
1574 class DirectiveInsnRIL<dag outs, dag ins, string asmstr, list<dag> pattern>
1575 : InstRILa<0, outs, ins, asmstr, pattern> {
1579 let Inst{47-40} = enc{47-40};
1580 let Inst{35-32} = enc{35-32};
1583 class DirectiveInsnRIS<dag outs, dag ins, string asmstr, list<dag> pattern>
1584 : InstRIS<0, outs, ins, asmstr, pattern> {
1587 let Inst{47-40} = enc{47-40};
1588 let Inst{7-0} = enc{7-0};
1591 class DirectiveInsnRR<dag outs, dag ins, string asmstr, list<dag> pattern>
1592 : InstRR<0, outs, ins, asmstr, pattern> {
1595 let Inst{15-8} = enc{15-8};
1598 class DirectiveInsnRRE<dag outs, dag ins, string asmstr, list<dag> pattern>
1599 : InstRRE<0, outs, ins, asmstr, pattern> {
1602 let Inst{31-16} = enc{31-16};
1605 class DirectiveInsnRRF<dag outs, dag ins, string asmstr, list<dag> pattern>
1606 : InstRRFa<0, outs, ins, asmstr, pattern> {
1609 let Inst{31-16} = enc{31-16};
1612 class DirectiveInsnRRS<dag outs, dag ins, string asmstr, list<dag> pattern>
1613 : InstRRS<0, outs, ins, asmstr, pattern> {
1616 let Inst{47-40} = enc{47-40};
1617 let Inst{7-0} = enc{7-0};
1620 class DirectiveInsnRS<dag outs, dag ins, string asmstr, list<dag> pattern>
1621 : InstRSa<0, outs, ins, asmstr, pattern> {
1624 let Inst{31-24} = enc{31-24};
1627 // RSE is like RSY except with a 12 bit displacement (instead of 20).
1628 class DirectiveInsnRSE<dag outs, dag ins, string asmstr, list<dag> pattern>
1629 : InstRSYa<6, outs, ins, asmstr, pattern> {
1632 let Inst{47-40} = enc{47-40};
1633 let Inst{31-16} = BD2{15-0};
1635 let Inst{7-0} = enc{7-0};
1638 class DirectiveInsnRSI<dag outs, dag ins, string asmstr, list<dag> pattern>
1639 : InstRSI<0, outs, ins, asmstr, pattern> {
1642 let Inst{31-24} = enc{31-24};
1645 class DirectiveInsnRSY<dag outs, dag ins, string asmstr, list<dag> pattern>
1646 : InstRSYa<0, outs, ins, asmstr, pattern> {
1649 let Inst{47-40} = enc{47-40};
1650 let Inst{7-0} = enc{7-0};
1653 class DirectiveInsnRX<dag outs, dag ins, string asmstr, list<dag> pattern>
1654 : InstRXa<0, outs, ins, asmstr, pattern> {
1657 let Inst{31-24} = enc{31-24};
1660 class DirectiveInsnRXE<dag outs, dag ins, string asmstr, list<dag> pattern>
1661 : InstRXE<0, outs, ins, asmstr, pattern> {
1666 let Inst{47-40} = enc{47-40};
1667 let Inst{7-0} = enc{7-0};
1670 class DirectiveInsnRXF<dag outs, dag ins, string asmstr, list<dag> pattern>
1671 : InstRXF<0, outs, ins, asmstr, pattern> {
1674 let Inst{47-40} = enc{47-40};
1675 let Inst{7-0} = enc{7-0};
1678 class DirectiveInsnRXY<dag outs, dag ins, string asmstr, list<dag> pattern>
1679 : InstRXYa<0, outs, ins, asmstr, pattern> {
1682 let Inst{47-40} = enc{47-40};
1683 let Inst{7-0} = enc{7-0};
1686 class DirectiveInsnS<dag outs, dag ins, string asmstr, list<dag> pattern>
1687 : InstS<0, outs, ins, asmstr, pattern> {
1690 let Inst{31-16} = enc{31-16};
1693 class DirectiveInsnSI<dag outs, dag ins, string asmstr, list<dag> pattern>
1694 : InstSI<0, outs, ins, asmstr, pattern> {
1697 let Inst{31-24} = enc{31-24};
1700 class DirectiveInsnSIY<dag outs, dag ins, string asmstr, list<dag> pattern>
1701 : InstSIY<0, outs, ins, asmstr, pattern> {
1704 let Inst{47-40} = enc{47-40};
1705 let Inst{7-0} = enc{7-0};
1708 class DirectiveInsnSIL<dag outs, dag ins, string asmstr, list<dag> pattern>
1709 : InstSIL<0, outs, ins, asmstr, pattern> {
1712 let Inst{47-32} = enc{47-32};
1715 class DirectiveInsnSS<dag outs, dag ins, string asmstr, list<dag> pattern>
1716 : InstSSd<0, outs, ins, asmstr, pattern> {
1719 let Inst{47-40} = enc{47-40};
1722 class DirectiveInsnSSE<dag outs, dag ins, string asmstr, list<dag> pattern>
1723 : InstSSE<0, outs, ins, asmstr, pattern> {
1726 let Inst{47-32} = enc{47-32};
1729 class DirectiveInsnSSF<dag outs, dag ins, string asmstr, list<dag> pattern>
1730 : InstSSF<0, outs, ins, asmstr, pattern> {
1733 let Inst{47-40} = enc{47-40};
1734 let Inst{35-32} = enc{35-32};
1737 //===----------------------------------------------------------------------===//
1738 // Variants of instructions with condition mask
1739 //===----------------------------------------------------------------------===//
1741 // For instructions using a condition mask (e.g. conditional branches,
1742 // compare-and-branch instructions, or conditional move instructions),
1743 // we generally need to create multiple instruction patterns:
1745 // - One used for code generation, which encodes the condition mask as an
1746 // MI operand, but writes out an extended mnemonic for better readability.
1747 // - One pattern for the base form of the instruction with an explicit
1748 // condition mask (encoded as a plain integer MI operand).
1749 // - Specific patterns for each extended mnemonic, where the condition mask
1750 // is implied by the pattern name and not otherwise encoded at all.
1752 // We need the latter primarily for the assembler and disassembler, since the
1753 // assembler parser is not able to decode part of an instruction mnemonic
1754 // into an operand. Thus we provide separate patterns for each mnemonic.
1756 // Note that in some cases there are two different mnemonics for the same
1757 // condition mask. In this case we cannot have both instructions available
1758 // to the disassembler at the same time since the encodings are not distinct.
1759 // Therefore the alternate forms are marked isAsmParserOnly.
1761 // We don't make one of the two names an alias of the other because
1762 // we need the custom parsing routines to select the correct register class.
1764 // This section provides helpers for generating the specific forms.
1766 //===----------------------------------------------------------------------===//
1768 // A class to describe a variant of an instruction with condition mask.
1769 class CondVariant<bits<4> ccmaskin, string suffixin, bit alternatein> {
1770 // The fixed condition mask to use.
1771 bits<4> ccmask = ccmaskin;
1773 // The suffix to use for the extended assembler mnemonic.
1774 string suffix = suffixin;
1776 // Whether this is an alternate that needs to be marked isAsmParserOnly.
1777 bit alternate = alternatein;
1780 // Condition mask 15 means "always true", which is used to define
1781 // unconditional branches as a variant of conditional branches.
1782 def CondAlways : CondVariant<15, "", 0>;
1784 // Condition masks for general instructions that can set all 4 bits.
1785 def CondVariantO : CondVariant<1, "o", 0>;
1786 def CondVariantH : CondVariant<2, "h", 0>;
1787 def CondVariantP : CondVariant<2, "p", 1>;
1788 def CondVariantNLE : CondVariant<3, "nle", 0>;
1789 def CondVariantL : CondVariant<4, "l", 0>;
1790 def CondVariantM : CondVariant<4, "m", 1>;
1791 def CondVariantNHE : CondVariant<5, "nhe", 0>;
1792 def CondVariantLH : CondVariant<6, "lh", 0>;
1793 def CondVariantNE : CondVariant<7, "ne", 0>;
1794 def CondVariantNZ : CondVariant<7, "nz", 1>;
1795 def CondVariantE : CondVariant<8, "e", 0>;
1796 def CondVariantZ : CondVariant<8, "z", 1>;
1797 def CondVariantNLH : CondVariant<9, "nlh", 0>;
1798 def CondVariantHE : CondVariant<10, "he", 0>;
1799 def CondVariantNL : CondVariant<11, "nl", 0>;
1800 def CondVariantNM : CondVariant<11, "nm", 1>;
1801 def CondVariantLE : CondVariant<12, "le", 0>;
1802 def CondVariantNH : CondVariant<13, "nh", 0>;
1803 def CondVariantNP : CondVariant<13, "np", 1>;
1804 def CondVariantNO : CondVariant<14, "no", 0>;
1806 // A helper class to look up one of the above by name.
1807 class CV<string name>
1808 : CondVariant<!cast<CondVariant>("CondVariant"#name).ccmask,
1809 !cast<CondVariant>("CondVariant"#name).suffix,
1810 !cast<CondVariant>("CondVariant"#name).alternate>;
1812 // Condition masks for integer instructions (e.g. compare-and-branch).
1813 // This is like the list above, except that condition 3 is not possible
1814 // and that the low bit of the mask is therefore always 0. This means
1815 // that each condition has two names. Conditions "o" and "no" are not used.
1816 def IntCondVariantH : CondVariant<2, "h", 0>;
1817 def IntCondVariantNLE : CondVariant<2, "nle", 1>;
1818 def IntCondVariantL : CondVariant<4, "l", 0>;
1819 def IntCondVariantNHE : CondVariant<4, "nhe", 1>;
1820 def IntCondVariantLH : CondVariant<6, "lh", 0>;
1821 def IntCondVariantNE : CondVariant<6, "ne", 1>;
1822 def IntCondVariantE : CondVariant<8, "e", 0>;
1823 def IntCondVariantNLH : CondVariant<8, "nlh", 1>;
1824 def IntCondVariantHE : CondVariant<10, "he", 0>;
1825 def IntCondVariantNL : CondVariant<10, "nl", 1>;
1826 def IntCondVariantLE : CondVariant<12, "le", 0>;
1827 def IntCondVariantNH : CondVariant<12, "nh", 1>;
1829 // A helper class to look up one of the above by name.
1830 class ICV<string name>
1831 : CondVariant<!cast<CondVariant>("IntCondVariant"#name).ccmask,
1832 !cast<CondVariant>("IntCondVariant"#name).suffix,
1833 !cast<CondVariant>("IntCondVariant"#name).alternate>;
1835 //===----------------------------------------------------------------------===//
1836 // Instruction definitions with semantics
1837 //===----------------------------------------------------------------------===//
1839 // These classes have the form [Cond]<Category><Format>, where <Format> is one
1840 // of the formats defined above and where <Category> describes the inputs
1841 // and outputs. "Cond" is used if the instruction is conditional,
1842 // in which case the 4-bit condition-code mask is added as a final operand.
1843 // <Category> can be one of:
1846 // One register output operand and no input operands.
1849 // Two register output operands and no input operands.
1852 // One address operand. The instruction stores to the address.
1854 // SideEffectInherent:
1855 // No input or output operands, but causes some side effect.
1858 // One branch target. The instruction branches to the target.
1861 // One output operand and one branch target. The instruction stores
1862 // the return address to the output operand and branches to the target.
1865 // Two input operands and one optional branch target. The instruction
1866 // compares the two input operands and branches or traps on the result.
1869 // One register output operand, one register input operand and one branch
1870 // target. The instructions stores a modified form of the source register
1871 // in the destination register and branches on the result.
1874 // One register output operand, two register input operands and one branch
1875 // target. The instructions stores a modified form of one of the source
1876 // registers in the destination register and branches on the result.
1879 // One address input operand and two explicit output operands.
1880 // The instruction loads a range of registers from the address,
1881 // with the explicit operands giving the first and last register
1882 // to load. Other loaded registers are added as implicit definitions.
1885 // Two explicit input register operands and an address operand.
1886 // The instruction stores a range of registers to the address,
1887 // with the explicit operands giving the first and last register
1888 // to store. Other stored registers are added as implicit uses.
1891 // One value operand, one length operand and one address operand.
1892 // The instruction stores the value operand to the address but
1893 // doesn't write more than the number of bytes specified by the
1897 // One register output operand and one address operand.
1899 // SideEffectAddress:
1900 // One address operand. No output operands, but causes some side effect.
1903 // One register output operand and one input operand.
1906 // One address operand and one other input operand. The instruction
1907 // stores to the address.
1910 // One input operand. No output operands, but causes some side effect.
1913 // One register output operand and two input operands.
1916 // One address operand and two other input operands. The instruction
1917 // stores to the address.
1919 // SideEffectBinary:
1920 // Two input operands. No output operands, but causes some side effect.
1923 // Two input operands and an implicit CC output operand.
1926 // One or two input operands and an implicit CC output operand. If
1927 // present, the second input operand is an "address" operand used as
1928 // a test class mask.
1931 // One register output operand and three input operands.
1933 // SideEffectTernary:
1934 // Three input operands. No output operands, but causes some side effect.
1937 // One register output operand and four input operands.
1940 // One output operand and two input operands, one of which is an address.
1941 // The instruction both reads from and writes to the address.
1944 // One output operand and three input operands, one of which is an address.
1945 // The instruction both reads from and writes to the address.
1948 // One output operand and five input operands. The first two operands
1949 // are registers and the other three are immediates.
1952 // One 4-bit immediate operand and one address operand. The immediate
1953 // operand is 1 for a load prefetch and 2 for a store prefetch.
1956 // One 4-bit immediate operand and two address operands.
1958 // The format determines which input operands are tied to output operands,
1959 // and also determines the shape of any address operand.
1961 // Multiclasses of the form <Category><Format>Pair define two instructions,
1962 // one with <Category><Format> and one with <Category><Format>Y. The name
1963 // of the first instruction has no suffix, the name of the second has
1966 //===----------------------------------------------------------------------===//
1968 class InherentRRE<string mnemonic, bits<16> opcode, RegisterOperand cls,
1969 SDPatternOperator operator>
1970 : InstRRE<opcode, (outs cls:$R1), (ins),
1972 [(set cls:$R1, (operator))]> {
1976 class InherentDualRRE<string mnemonic, bits<16> opcode, RegisterOperand cls>
1977 : InstRRE<opcode, (outs cls:$R1, cls:$R2), (ins),
1978 mnemonic#"\t$R1, $R2", []>;
1980 class InherentVRIa<string mnemonic, bits<16> opcode, bits<16> value>
1981 : InstVRIa<opcode, (outs VR128:$V1), (ins), mnemonic#"\t$V1", []> {
1986 class StoreInherentS<string mnemonic, bits<16> opcode,
1987 SDPatternOperator operator, bits<5> bytes>
1988 : InstS<opcode, (outs), (ins bdaddr12only:$BD2),
1989 mnemonic#"\t$BD2", [(operator bdaddr12only:$BD2)]> {
1991 let AccessBytes = bytes;
1994 class SideEffectInherentE<string mnemonic, bits<16>opcode>
1995 : InstE<opcode, (outs), (ins), mnemonic, []>;
1997 class SideEffectInherentS<string mnemonic, bits<16> opcode,
1998 SDPatternOperator operator>
1999 : InstS<opcode, (outs), (ins), mnemonic, [(operator)]> {
2003 class SideEffectInherentRRE<string mnemonic, bits<16> opcode>
2004 : InstRRE<opcode, (outs), (ins), mnemonic, []> {
2009 // Allow an optional TLS marker symbol to generate TLS call relocations.
2010 class CallRI<string mnemonic, bits<12> opcode>
2011 : InstRIb<opcode, (outs), (ins GR64:$R1, brtarget16tls:$RI2),
2012 mnemonic#"\t$R1, $RI2", []>;
2014 // Allow an optional TLS marker symbol to generate TLS call relocations.
2015 class CallRIL<string mnemonic, bits<12> opcode>
2016 : InstRILb<opcode, (outs), (ins GR64:$R1, brtarget32tls:$RI2),
2017 mnemonic#"\t$R1, $RI2", []>;
2019 class CallRR<string mnemonic, bits<8> opcode>
2020 : InstRR<opcode, (outs), (ins GR64:$R1, ADDR64:$R2),
2021 mnemonic#"\t$R1, $R2", []>;
2023 class CallRX<string mnemonic, bits<8> opcode>
2024 : InstRXa<opcode, (outs), (ins GR64:$R1, bdxaddr12only:$XBD2),
2025 mnemonic#"\t$R1, $XBD2", []>;
2027 class CondBranchRI<string mnemonic, bits<12> opcode,
2028 SDPatternOperator operator = null_frag>
2029 : InstRIc<opcode, (outs), (ins cond4:$valid, cond4:$M1, brtarget16:$RI2),
2030 !subst("#", "${M1}", mnemonic)#"\t$RI2",
2031 [(operator cond4:$valid, cond4:$M1, bb:$RI2)]> {
2032 let CCMaskFirst = 1;
2035 class AsmCondBranchRI<string mnemonic, bits<12> opcode>
2036 : InstRIc<opcode, (outs), (ins imm32zx4:$M1, brtarget16:$RI2),
2037 mnemonic#"\t$M1, $RI2", []>;
2039 class FixedCondBranchRI<CondVariant V, string mnemonic, bits<12> opcode,
2040 SDPatternOperator operator = null_frag>
2041 : InstRIc<opcode, (outs), (ins brtarget16:$RI2),
2042 !subst("#", V.suffix, mnemonic)#"\t$RI2", [(operator bb:$RI2)]> {
2043 let isAsmParserOnly = V.alternate;
2047 class CondBranchRIL<string mnemonic, bits<12> opcode>
2048 : InstRILc<opcode, (outs), (ins cond4:$valid, cond4:$M1, brtarget32:$RI2),
2049 !subst("#", "${M1}", mnemonic)#"\t$RI2", []> {
2050 let CCMaskFirst = 1;
2053 class AsmCondBranchRIL<string mnemonic, bits<12> opcode>
2054 : InstRILc<opcode, (outs), (ins imm32zx4:$M1, brtarget32:$RI2),
2055 mnemonic#"\t$M1, $RI2", []>;
2057 class FixedCondBranchRIL<CondVariant V, string mnemonic, bits<12> opcode>
2058 : InstRILc<opcode, (outs), (ins brtarget32:$RI2),
2059 !subst("#", V.suffix, mnemonic)#"\t$RI2", []> {
2060 let isAsmParserOnly = V.alternate;
2064 class CondBranchRR<string mnemonic, bits<8> opcode>
2065 : InstRR<opcode, (outs), (ins cond4:$valid, cond4:$R1, GR64:$R2),
2066 !subst("#", "${R1}", mnemonic)#"\t$R2", []> {
2067 let CCMaskFirst = 1;
2070 class AsmCondBranchRR<string mnemonic, bits<8> opcode>
2071 : InstRR<opcode, (outs), (ins imm32zx4:$R1, GR64:$R2),
2072 mnemonic#"\t$R1, $R2", []>;
2074 class FixedCondBranchRR<CondVariant V, string mnemonic, bits<8> opcode,
2075 SDPatternOperator operator = null_frag>
2076 : InstRR<opcode, (outs), (ins ADDR64:$R2),
2077 !subst("#", V.suffix, mnemonic)#"\t$R2", [(operator ADDR64:$R2)]> {
2078 let isAsmParserOnly = V.alternate;
2082 class CondBranchRX<string mnemonic, bits<8> opcode>
2083 : InstRXb<opcode, (outs), (ins cond4:$valid, cond4:$M1, bdxaddr12only:$XBD2),
2084 !subst("#", "${M1}", mnemonic)#"\t$XBD2", []> {
2085 let CCMaskFirst = 1;
2088 class AsmCondBranchRX<string mnemonic, bits<8> opcode>
2089 : InstRXb<opcode, (outs), (ins imm32zx4:$M1, bdxaddr12only:$XBD2),
2090 mnemonic#"\t$M1, $XBD2", []>;
2092 class FixedCondBranchRX<CondVariant V, string mnemonic, bits<8> opcode>
2093 : InstRXb<opcode, (outs), (ins bdxaddr12only:$XBD2),
2094 !subst("#", V.suffix, mnemonic)#"\t$XBD2", []> {
2095 let isAsmParserOnly = V.alternate;
2099 class CondBranchRXY<string mnemonic, bits<16> opcode>
2100 : InstRXYb<opcode, (outs), (ins cond4:$valid, cond4:$M1, bdxaddr20only:$XBD2),
2101 !subst("#", "${M1}", mnemonic)#"\t$XBD2", []> {
2102 let CCMaskFirst = 1;
2105 class AsmCondBranchRXY<string mnemonic, bits<16> opcode>
2106 : InstRXYb<opcode, (outs), (ins imm32zx4:$M1, bdxaddr20only:$XBD2),
2107 mnemonic#"\t$M1, $XBD2", []>;
2109 class FixedCondBranchRXY<CondVariant V, string mnemonic, bits<16> opcode,
2110 SDPatternOperator operator = null_frag>
2111 : InstRXYb<opcode, (outs), (ins bdxaddr20only:$XBD2),
2112 !subst("#", V.suffix, mnemonic)#"\t$XBD2",
2113 [(operator (load bdxaddr20only:$XBD2))]> {
2114 let isAsmParserOnly = V.alternate;
2118 class CmpBranchRIEa<string mnemonic, bits<16> opcode,
2119 RegisterOperand cls, Immediate imm>
2120 : InstRIEa<opcode, (outs), (ins cls:$R1, imm:$I2, cond4:$M3),
2121 mnemonic#"$M3\t$R1, $I2", []>;
2123 class AsmCmpBranchRIEa<string mnemonic, bits<16> opcode,
2124 RegisterOperand cls, Immediate imm>
2125 : InstRIEa<opcode, (outs), (ins cls:$R1, imm:$I2, imm32zx4:$M3),
2126 mnemonic#"\t$R1, $I2, $M3", []>;
2128 class FixedCmpBranchRIEa<CondVariant V, string mnemonic, bits<16> opcode,
2129 RegisterOperand cls, Immediate imm>
2130 : InstRIEa<opcode, (outs), (ins cls:$R1, imm:$I2),
2131 mnemonic#V.suffix#"\t$R1, $I2", []> {
2132 let isAsmParserOnly = V.alternate;
2136 multiclass CmpBranchRIEaPair<string mnemonic, bits<16> opcode,
2137 RegisterOperand cls, Immediate imm> {
2138 let isCodeGenOnly = 1 in
2139 def "" : CmpBranchRIEa<mnemonic, opcode, cls, imm>;
2140 def Asm : AsmCmpBranchRIEa<mnemonic, opcode, cls, imm>;
2143 class CmpBranchRIEb<string mnemonic, bits<16> opcode,
2144 RegisterOperand cls>
2145 : InstRIEb<opcode, (outs),
2146 (ins cls:$R1, cls:$R2, cond4:$M3, brtarget16:$RI4),
2147 mnemonic#"$M3\t$R1, $R2, $RI4", []>;
2149 class AsmCmpBranchRIEb<string mnemonic, bits<16> opcode,
2150 RegisterOperand cls>
2151 : InstRIEb<opcode, (outs),
2152 (ins cls:$R1, cls:$R2, imm32zx4:$M3, brtarget16:$RI4),
2153 mnemonic#"\t$R1, $R2, $M3, $RI4", []>;
2155 class FixedCmpBranchRIEb<CondVariant V, string mnemonic, bits<16> opcode,
2156 RegisterOperand cls>
2157 : InstRIEb<opcode, (outs), (ins cls:$R1, cls:$R2, brtarget16:$RI4),
2158 mnemonic#V.suffix#"\t$R1, $R2, $RI4", []> {
2159 let isAsmParserOnly = V.alternate;
2163 multiclass CmpBranchRIEbPair<string mnemonic, bits<16> opcode,
2164 RegisterOperand cls> {
2165 let isCodeGenOnly = 1 in
2166 def "" : CmpBranchRIEb<mnemonic, opcode, cls>;
2167 def Asm : AsmCmpBranchRIEb<mnemonic, opcode, cls>;
2170 class CmpBranchRIEc<string mnemonic, bits<16> opcode,
2171 RegisterOperand cls, Immediate imm>
2172 : InstRIEc<opcode, (outs),
2173 (ins cls:$R1, imm:$I2, cond4:$M3, brtarget16:$RI4),
2174 mnemonic#"$M3\t$R1, $I2, $RI4", []>;
2176 class AsmCmpBranchRIEc<string mnemonic, bits<16> opcode,
2177 RegisterOperand cls, Immediate imm>
2178 : InstRIEc<opcode, (outs),
2179 (ins cls:$R1, imm:$I2, imm32zx4:$M3, brtarget16:$RI4),
2180 mnemonic#"\t$R1, $I2, $M3, $RI4", []>;
2182 class FixedCmpBranchRIEc<CondVariant V, string mnemonic, bits<16> opcode,
2183 RegisterOperand cls, Immediate imm>
2184 : InstRIEc<opcode, (outs), (ins cls:$R1, imm:$I2, brtarget16:$RI4),
2185 mnemonic#V.suffix#"\t$R1, $I2, $RI4", []> {
2186 let isAsmParserOnly = V.alternate;
2190 multiclass CmpBranchRIEcPair<string mnemonic, bits<16> opcode,
2191 RegisterOperand cls, Immediate imm> {
2192 let isCodeGenOnly = 1 in
2193 def "" : CmpBranchRIEc<mnemonic, opcode, cls, imm>;
2194 def Asm : AsmCmpBranchRIEc<mnemonic, opcode, cls, imm>;
2197 class CmpBranchRRFc<string mnemonic, bits<16> opcode,
2198 RegisterOperand cls>
2199 : InstRRFc<opcode, (outs), (ins cls:$R1, cls:$R2, cond4:$M3),
2200 mnemonic#"$M3\t$R1, $R2", []>;
2202 class AsmCmpBranchRRFc<string mnemonic, bits<16> opcode,
2203 RegisterOperand cls>
2204 : InstRRFc<opcode, (outs), (ins cls:$R1, cls:$R2, imm32zx4:$M3),
2205 mnemonic#"\t$R1, $R2, $M3", []>;
2207 multiclass CmpBranchRRFcPair<string mnemonic, bits<16> opcode,
2208 RegisterOperand cls> {
2209 let isCodeGenOnly = 1 in
2210 def "" : CmpBranchRRFc<mnemonic, opcode, cls>;
2211 def Asm : AsmCmpBranchRRFc<mnemonic, opcode, cls>;
2214 class FixedCmpBranchRRFc<CondVariant V, string mnemonic, bits<16> opcode,
2215 RegisterOperand cls>
2216 : InstRRFc<opcode, (outs), (ins cls:$R1, cls:$R2),
2217 mnemonic#V.suffix#"\t$R1, $R2", []> {
2218 let isAsmParserOnly = V.alternate;
2222 class CmpBranchRRS<string mnemonic, bits<16> opcode,
2223 RegisterOperand cls>
2224 : InstRRS<opcode, (outs),
2225 (ins cls:$R1, cls:$R2, cond4:$M3, bdaddr12only:$BD4),
2226 mnemonic#"$M3\t$R1, $R2, $BD4", []>;
2228 class AsmCmpBranchRRS<string mnemonic, bits<16> opcode,
2229 RegisterOperand cls>
2230 : InstRRS<opcode, (outs),
2231 (ins cls:$R1, cls:$R2, imm32zx4:$M3, bdaddr12only:$BD4),
2232 mnemonic#"\t$R1, $R2, $M3, $BD4", []>;
2234 class FixedCmpBranchRRS<CondVariant V, string mnemonic, bits<16> opcode,
2235 RegisterOperand cls>
2236 : InstRRS<opcode, (outs), (ins cls:$R1, cls:$R2, bdaddr12only:$BD4),
2237 mnemonic#V.suffix#"\t$R1, $R2, $BD4", []> {
2238 let isAsmParserOnly = V.alternate;
2242 multiclass CmpBranchRRSPair<string mnemonic, bits<16> opcode,
2243 RegisterOperand cls> {
2244 let isCodeGenOnly = 1 in
2245 def "" : CmpBranchRRS<mnemonic, opcode, cls>;
2246 def Asm : AsmCmpBranchRRS<mnemonic, opcode, cls>;
2249 class CmpBranchRIS<string mnemonic, bits<16> opcode,
2250 RegisterOperand cls, Immediate imm>
2251 : InstRIS<opcode, (outs),
2252 (ins cls:$R1, imm:$I2, cond4:$M3, bdaddr12only:$BD4),
2253 mnemonic#"$M3\t$R1, $I2, $BD4", []>;
2255 class AsmCmpBranchRIS<string mnemonic, bits<16> opcode,
2256 RegisterOperand cls, Immediate imm>
2257 : InstRIS<opcode, (outs),
2258 (ins cls:$R1, imm:$I2, imm32zx4:$M3, bdaddr12only:$BD4),
2259 mnemonic#"\t$R1, $I2, $M3, $BD4", []>;
2261 class FixedCmpBranchRIS<CondVariant V, string mnemonic, bits<16> opcode,
2262 RegisterOperand cls, Immediate imm>
2263 : InstRIS<opcode, (outs), (ins cls:$R1, imm:$I2, bdaddr12only:$BD4),
2264 mnemonic#V.suffix#"\t$R1, $I2, $BD4", []> {
2265 let isAsmParserOnly = V.alternate;
2269 multiclass CmpBranchRISPair<string mnemonic, bits<16> opcode,
2270 RegisterOperand cls, Immediate imm> {
2271 let isCodeGenOnly = 1 in
2272 def "" : CmpBranchRIS<mnemonic, opcode, cls, imm>;
2273 def Asm : AsmCmpBranchRIS<mnemonic, opcode, cls, imm>;
2276 class CmpBranchRSYb<string mnemonic, bits<16> opcode,
2277 RegisterOperand cls>
2278 : InstRSYb<opcode, (outs), (ins cls:$R1, bdaddr20only:$BD2, cond4:$M3),
2279 mnemonic#"$M3\t$R1, $BD2", []>;
2281 class AsmCmpBranchRSYb<string mnemonic, bits<16> opcode,
2282 RegisterOperand cls>
2283 : InstRSYb<opcode, (outs), (ins cls:$R1, bdaddr20only:$BD2, imm32zx4:$M3),
2284 mnemonic#"\t$R1, $M3, $BD2", []>;
2286 multiclass CmpBranchRSYbPair<string mnemonic, bits<16> opcode,
2287 RegisterOperand cls> {
2288 let isCodeGenOnly = 1 in
2289 def "" : CmpBranchRSYb<mnemonic, opcode, cls>;
2290 def Asm : AsmCmpBranchRSYb<mnemonic, opcode, cls>;
2293 class FixedCmpBranchRSYb<CondVariant V, string mnemonic, bits<16> opcode,
2294 RegisterOperand cls>
2295 : InstRSYb<opcode, (outs), (ins cls:$R1, bdaddr20only:$BD2),
2296 mnemonic#V.suffix#"\t$R1, $BD2", []> {
2297 let isAsmParserOnly = V.alternate;
2301 class BranchUnaryRI<string mnemonic, bits<12> opcode, RegisterOperand cls>
2302 : InstRIb<opcode, (outs cls:$R1), (ins cls:$R1src, brtarget16:$RI2),
2303 mnemonic##"\t$R1, $RI2", []> {
2304 let Constraints = "$R1 = $R1src";
2305 let DisableEncoding = "$R1src";
2308 class BranchUnaryRIL<string mnemonic, bits<12> opcode, RegisterOperand cls>
2309 : InstRILb<opcode, (outs cls:$R1), (ins cls:$R1src, brtarget32:$RI2),
2310 mnemonic##"\t$R1, $RI2", []> {
2311 let Constraints = "$R1 = $R1src";
2312 let DisableEncoding = "$R1src";
2315 class BranchUnaryRR<string mnemonic, bits<8> opcode, RegisterOperand cls>
2316 : InstRR<opcode, (outs cls:$R1), (ins cls:$R1src, GR64:$R2),
2317 mnemonic##"\t$R1, $R2", []> {
2318 let Constraints = "$R1 = $R1src";
2319 let DisableEncoding = "$R1src";
2322 class BranchUnaryRRE<string mnemonic, bits<16> opcode, RegisterOperand cls>
2323 : InstRRE<opcode, (outs cls:$R1), (ins cls:$R1src, GR64:$R2),
2324 mnemonic##"\t$R1, $R2", []> {
2325 let Constraints = "$R1 = $R1src";
2326 let DisableEncoding = "$R1src";
2329 class BranchUnaryRX<string mnemonic, bits<8> opcode, RegisterOperand cls>
2330 : InstRXa<opcode, (outs cls:$R1), (ins cls:$R1src, bdxaddr12only:$XBD2),
2331 mnemonic##"\t$R1, $XBD2", []> {
2332 let Constraints = "$R1 = $R1src";
2333 let DisableEncoding = "$R1src";
2336 class BranchUnaryRXY<string mnemonic, bits<16> opcode, RegisterOperand cls>
2337 : InstRXYa<opcode, (outs cls:$R1), (ins cls:$R1src, bdxaddr20only:$XBD2),
2338 mnemonic##"\t$R1, $XBD2", []> {
2339 let Constraints = "$R1 = $R1src";
2340 let DisableEncoding = "$R1src";
2343 class BranchBinaryRSI<string mnemonic, bits<8> opcode, RegisterOperand cls>
2344 : InstRSI<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, brtarget16:$RI2),
2345 mnemonic##"\t$R1, $R3, $RI2", []> {
2346 let Constraints = "$R1 = $R1src";
2347 let DisableEncoding = "$R1src";
2350 class BranchBinaryRIEe<string mnemonic, bits<16> opcode, RegisterOperand cls>
2351 : InstRIEe<opcode, (outs cls:$R1),
2352 (ins cls:$R1src, cls:$R3, brtarget16:$RI2),
2353 mnemonic##"\t$R1, $R3, $RI2", []> {
2354 let Constraints = "$R1 = $R1src";
2355 let DisableEncoding = "$R1src";
2358 class BranchBinaryRS<string mnemonic, bits<8> opcode, RegisterOperand cls>
2359 : InstRSa<opcode, (outs cls:$R1),
2360 (ins cls:$R1src, cls:$R3, bdaddr12only:$BD2),
2361 mnemonic##"\t$R1, $R3, $BD2", []> {
2362 let Constraints = "$R1 = $R1src";
2363 let DisableEncoding = "$R1src";
2366 class BranchBinaryRSY<string mnemonic, bits<16> opcode, RegisterOperand cls>
2368 (outs cls:$R1), (ins cls:$R1src, cls:$R3, bdaddr20only:$BD2),
2369 mnemonic##"\t$R1, $R3, $BD2", []> {
2370 let Constraints = "$R1 = $R1src";
2371 let DisableEncoding = "$R1src";
2374 class LoadMultipleRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
2375 AddressingMode mode = bdaddr12only>
2376 : InstRSa<opcode, (outs cls:$R1, cls:$R3), (ins mode:$BD2),
2377 mnemonic#"\t$R1, $R3, $BD2", []> {
2381 class LoadMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
2382 AddressingMode mode = bdaddr20only>
2383 : InstRSYa<opcode, (outs cls:$R1, cls:$R3), (ins mode:$BD2),
2384 mnemonic#"\t$R1, $R3, $BD2", []> {
2388 multiclass LoadMultipleRSPair<string mnemonic, bits<8> rsOpcode,
2389 bits<16> rsyOpcode, RegisterOperand cls> {
2390 let DispKey = mnemonic ## #cls in {
2391 let DispSize = "12" in
2392 def "" : LoadMultipleRS<mnemonic, rsOpcode, cls, bdaddr12pair>;
2393 let DispSize = "20" in
2394 def Y : LoadMultipleRSY<mnemonic#"y", rsyOpcode, cls, bdaddr20pair>;
2398 class LoadMultipleSSe<string mnemonic, bits<8> opcode, RegisterOperand cls>
2399 : InstSSe<opcode, (outs cls:$R1, cls:$R3),
2400 (ins bdaddr12only:$BD2, bdaddr12only:$BD4),
2401 mnemonic#"\t$R1, $R3, $BD2, $BD4", []> {
2405 class LoadMultipleVRSa<string mnemonic, bits<16> opcode>
2406 : InstVRSa<opcode, (outs VR128:$V1, VR128:$V3), (ins bdaddr12only:$BD2),
2407 mnemonic#"\t$V1, $V3, $BD2", []> {
2412 class StoreRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator,
2413 RegisterOperand cls>
2414 : InstRILb<opcode, (outs), (ins cls:$R1, pcrel32:$RI2),
2415 mnemonic#"\t$R1, $RI2",
2416 [(operator cls:$R1, pcrel32:$RI2)]> {
2418 // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
2419 // However, BDXs have two extra operands and are therefore 6 units more
2421 let AddedComplexity = 7;
2424 class StoreRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
2425 RegisterOperand cls, bits<5> bytes,
2426 AddressingMode mode = bdxaddr12only>
2427 : InstRXa<opcode, (outs), (ins cls:$R1, mode:$XBD2),
2428 mnemonic#"\t$R1, $XBD2",
2429 [(operator cls:$R1, mode:$XBD2)]> {
2430 let OpKey = mnemonic#"r"#cls;
2433 let AccessBytes = bytes;
2436 class StoreRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2437 RegisterOperand cls, bits<5> bytes,
2438 AddressingMode mode = bdxaddr20only>
2439 : InstRXYa<opcode, (outs), (ins cls:$R1, mode:$XBD2),
2440 mnemonic#"\t$R1, $XBD2",
2441 [(operator cls:$R1, mode:$XBD2)]> {
2442 let OpKey = mnemonic#"r"#cls;
2445 let AccessBytes = bytes;
2448 multiclass StoreRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
2449 SDPatternOperator operator, RegisterOperand cls,
2451 let DispKey = mnemonic ## #cls in {
2452 let DispSize = "12" in
2453 def "" : StoreRX<mnemonic, rxOpcode, operator, cls, bytes, bdxaddr12pair>;
2454 let DispSize = "20" in
2455 def Y : StoreRXY<mnemonic#"y", rxyOpcode, operator, cls, bytes,
2460 class StoreVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2461 TypedReg tr, bits<5> bytes, bits<4> type = 0>
2462 : InstVRX<opcode, (outs), (ins tr.op:$V1, bdxaddr12only:$XBD2),
2463 mnemonic#"\t$V1, $XBD2",
2464 [(set tr.op:$V1, (tr.vt (operator bdxaddr12only:$XBD2)))]> {
2467 let AccessBytes = bytes;
2470 class StoreLengthVRSb<string mnemonic, bits<16> opcode,
2471 SDPatternOperator operator, bits<5> bytes>
2472 : InstVRSb<opcode, (outs), (ins VR128:$V1, GR32:$R3, bdaddr12only:$BD2),
2473 mnemonic#"\t$V1, $R3, $BD2",
2474 [(operator VR128:$V1, GR32:$R3, bdaddr12only:$BD2)]> {
2477 let AccessBytes = bytes;
2480 class StoreLengthVRSd<string mnemonic, bits<16> opcode,
2481 SDPatternOperator operator, bits<5> bytes>
2482 : InstVRSd<opcode, (outs), (ins VR128:$V1, GR32:$R3, bdaddr12only:$BD2),
2483 mnemonic#"\t$V1, $R3, $BD2",
2484 [(operator VR128:$V1, GR32:$R3, bdaddr12only:$BD2)]> {
2486 let AccessBytes = bytes;
2489 class StoreLengthVSI<string mnemonic, bits<16> opcode,
2490 SDPatternOperator operator, bits<5> bytes>
2491 : InstVSI<opcode, (outs), (ins VR128:$V1, bdaddr12only:$BD2, imm32zx8:$I3),
2492 mnemonic#"\t$V1, $BD2, $I3",
2493 [(operator VR128:$V1, imm32zx8:$I3, bdaddr12only:$BD2)]> {
2495 let AccessBytes = bytes;
2498 class StoreMultipleRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
2499 AddressingMode mode = bdaddr12only>
2500 : InstRSa<opcode, (outs), (ins cls:$R1, cls:$R3, mode:$BD2),
2501 mnemonic#"\t$R1, $R3, $BD2", []> {
2505 class StoreMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
2506 AddressingMode mode = bdaddr20only>
2507 : InstRSYa<opcode, (outs), (ins cls:$R1, cls:$R3, mode:$BD2),
2508 mnemonic#"\t$R1, $R3, $BD2", []> {
2512 multiclass StoreMultipleRSPair<string mnemonic, bits<8> rsOpcode,
2513 bits<16> rsyOpcode, RegisterOperand cls> {
2514 let DispKey = mnemonic ## #cls in {
2515 let DispSize = "12" in
2516 def "" : StoreMultipleRS<mnemonic, rsOpcode, cls, bdaddr12pair>;
2517 let DispSize = "20" in
2518 def Y : StoreMultipleRSY<mnemonic#"y", rsyOpcode, cls, bdaddr20pair>;
2522 class StoreMultipleVRSa<string mnemonic, bits<16> opcode>
2523 : InstVRSa<opcode, (outs), (ins VR128:$V1, VR128:$V3, bdaddr12only:$BD2),
2524 mnemonic#"\t$V1, $V3, $BD2", []> {
2529 // StoreSI* instructions are used to store an integer to memory, but the
2530 // addresses are more restricted than for normal stores. If we are in the
2531 // situation of having to force either the address into a register or the
2532 // constant into a register, it's usually better to do the latter.
2533 // We therefore match the address in the same way as a normal store and
2534 // only use the StoreSI* instruction if the matched address is suitable.
2535 class StoreSI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
2537 : InstSI<opcode, (outs), (ins mviaddr12pair:$BD1, imm:$I2),
2538 mnemonic#"\t$BD1, $I2",
2539 [(operator imm:$I2, mviaddr12pair:$BD1)]> {
2543 class StoreSIY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2545 : InstSIY<opcode, (outs), (ins mviaddr20pair:$BD1, imm:$I2),
2546 mnemonic#"\t$BD1, $I2",
2547 [(operator imm:$I2, mviaddr20pair:$BD1)]> {
2551 class StoreSIL<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2553 : InstSIL<opcode, (outs), (ins mviaddr12pair:$BD1, imm:$I2),
2554 mnemonic#"\t$BD1, $I2",
2555 [(operator imm:$I2, mviaddr12pair:$BD1)]> {
2559 multiclass StoreSIPair<string mnemonic, bits<8> siOpcode, bits<16> siyOpcode,
2560 SDPatternOperator operator, Immediate imm> {
2561 let DispKey = mnemonic in {
2562 let DispSize = "12" in
2563 def "" : StoreSI<mnemonic, siOpcode, operator, imm>;
2564 let DispSize = "20" in
2565 def Y : StoreSIY<mnemonic#"y", siyOpcode, operator, imm>;
2569 class StoreSSE<string mnemonic, bits<16> opcode>
2570 : InstSSE<opcode, (outs), (ins bdaddr12only:$BD1, bdaddr12only:$BD2),
2571 mnemonic#"\t$BD1, $BD2", []> {
2575 class CondStoreRSY<string mnemonic, bits<16> opcode,
2576 RegisterOperand cls, bits<5> bytes,
2577 AddressingMode mode = bdaddr20only>
2578 : InstRSYb<opcode, (outs), (ins cls:$R1, mode:$BD2, cond4:$valid, cond4:$M3),
2579 mnemonic#"$M3\t$R1, $BD2", []> {
2581 let AccessBytes = bytes;
2585 // Like CondStoreRSY, but used for the raw assembly form. The condition-code
2586 // mask is the third operand rather than being part of the mnemonic.
2587 class AsmCondStoreRSY<string mnemonic, bits<16> opcode,
2588 RegisterOperand cls, bits<5> bytes,
2589 AddressingMode mode = bdaddr20only>
2590 : InstRSYb<opcode, (outs), (ins cls:$R1, mode:$BD2, imm32zx4:$M3),
2591 mnemonic#"\t$R1, $BD2, $M3", []> {
2593 let AccessBytes = bytes;
2596 // Like CondStoreRSY, but with a fixed CC mask.
2597 class FixedCondStoreRSY<CondVariant V, string mnemonic, bits<16> opcode,
2598 RegisterOperand cls, bits<5> bytes,
2599 AddressingMode mode = bdaddr20only>
2600 : InstRSYb<opcode, (outs), (ins cls:$R1, mode:$BD2),
2601 mnemonic#V.suffix#"\t$R1, $BD2", []> {
2603 let AccessBytes = bytes;
2604 let isAsmParserOnly = V.alternate;
2608 multiclass CondStoreRSYPair<string mnemonic, bits<16> opcode,
2609 RegisterOperand cls, bits<5> bytes,
2610 AddressingMode mode = bdaddr20only> {
2611 let isCodeGenOnly = 1 in
2612 def "" : CondStoreRSY<mnemonic, opcode, cls, bytes, mode>;
2613 def Asm : AsmCondStoreRSY<mnemonic, opcode, cls, bytes, mode>;
2616 class SideEffectUnaryI<string mnemonic, bits<8> opcode, Immediate imm>
2617 : InstI<opcode, (outs), (ins imm:$I1),
2618 mnemonic#"\t$I1", []>;
2620 class SideEffectUnaryRR<string mnemonic, bits<8>opcode, RegisterOperand cls>
2621 : InstRR<opcode, (outs), (ins cls:$R1),
2622 mnemonic#"\t$R1", []> {
2626 class SideEffectUnaryRRE<string mnemonic, bits<16> opcode, RegisterOperand cls,
2627 SDPatternOperator operator>
2628 : InstRRE<opcode, (outs), (ins cls:$R1),
2629 mnemonic#"\t$R1", [(operator cls:$R1)]> {
2633 class SideEffectUnaryS<string mnemonic, bits<16> opcode,
2634 SDPatternOperator operator, bits<5> bytes,
2635 AddressingMode mode = bdaddr12only>
2636 : InstS<opcode, (outs), (ins mode:$BD2),
2637 mnemonic#"\t$BD2", [(operator mode:$BD2)]> {
2639 let AccessBytes = bytes;
2642 class SideEffectAddressS<string mnemonic, bits<16> opcode,
2643 SDPatternOperator operator,
2644 AddressingMode mode = bdaddr12only>
2645 : InstS<opcode, (outs), (ins mode:$BD2),
2646 mnemonic#"\t$BD2", [(operator mode:$BD2)]>;
2648 class LoadAddressRX<string mnemonic, bits<8> opcode,
2649 SDPatternOperator operator, AddressingMode mode>
2650 : InstRXa<opcode, (outs GR64:$R1), (ins mode:$XBD2),
2651 mnemonic#"\t$R1, $XBD2",
2652 [(set GR64:$R1, (operator mode:$XBD2))]>;
2654 class LoadAddressRXY<string mnemonic, bits<16> opcode,
2655 SDPatternOperator operator, AddressingMode mode>
2656 : InstRXYa<opcode, (outs GR64:$R1), (ins mode:$XBD2),
2657 mnemonic#"\t$R1, $XBD2",
2658 [(set GR64:$R1, (operator mode:$XBD2))]>;
2660 multiclass LoadAddressRXPair<string mnemonic, bits<8> rxOpcode,
2661 bits<16> rxyOpcode, SDPatternOperator operator> {
2662 let DispKey = mnemonic in {
2663 let DispSize = "12" in
2664 def "" : LoadAddressRX<mnemonic, rxOpcode, operator, laaddr12pair>;
2665 let DispSize = "20" in
2666 def Y : LoadAddressRXY<mnemonic#"y", rxyOpcode, operator, laaddr20pair>;
2670 class LoadAddressRIL<string mnemonic, bits<12> opcode,
2671 SDPatternOperator operator>
2672 : InstRILb<opcode, (outs GR64:$R1), (ins pcrel32:$RI2),
2673 mnemonic#"\t$R1, $RI2",
2674 [(set GR64:$R1, (operator pcrel32:$RI2))]>;
2676 class UnaryRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
2677 RegisterOperand cls1, RegisterOperand cls2>
2678 : InstRR<opcode, (outs cls1:$R1), (ins cls2:$R2),
2679 mnemonic#"\t$R1, $R2",
2680 [(set cls1:$R1, (operator cls2:$R2))]> {
2681 let OpKey = mnemonic#cls1;
2685 class UnaryRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2686 RegisterOperand cls1, RegisterOperand cls2>
2687 : InstRRE<opcode, (outs cls1:$R1), (ins cls2:$R2),
2688 mnemonic#"\t$R1, $R2",
2689 [(set cls1:$R1, (operator cls2:$R2))]> {
2690 let OpKey = mnemonic#cls1;
2694 class UnaryTiedRRE<string mnemonic, bits<16> opcode, RegisterOperand cls>
2695 : InstRRE<opcode, (outs cls:$R1), (ins cls:$R1src),
2696 mnemonic#"\t$R1", []> {
2697 let Constraints = "$R1 = $R1src";
2698 let DisableEncoding = "$R1src";
2702 class UnaryMemRRFc<string mnemonic, bits<16> opcode,
2703 RegisterOperand cls1, RegisterOperand cls2>
2704 : InstRRFc<opcode, (outs cls2:$R2, cls1:$R1), (ins cls1:$R1src),
2705 mnemonic#"\t$R1, $R2", []> {
2706 let Constraints = "$R1 = $R1src";
2707 let DisableEncoding = "$R1src";
2711 class UnaryRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
2712 RegisterOperand cls, Immediate imm>
2713 : InstRIa<opcode, (outs cls:$R1), (ins imm:$I2),
2714 mnemonic#"\t$R1, $I2",
2715 [(set cls:$R1, (operator imm:$I2))]>;
2717 class UnaryRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator,
2718 RegisterOperand cls, Immediate imm>
2719 : InstRILa<opcode, (outs cls:$R1), (ins imm:$I2),
2720 mnemonic#"\t$R1, $I2",
2721 [(set cls:$R1, (operator imm:$I2))]>;
2723 class UnaryRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator,
2724 RegisterOperand cls>
2725 : InstRILb<opcode, (outs cls:$R1), (ins pcrel32:$RI2),
2726 mnemonic#"\t$R1, $RI2",
2727 [(set cls:$R1, (operator pcrel32:$RI2))]> {
2729 // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
2730 // However, BDXs have two extra operands and are therefore 6 units more
2732 let AddedComplexity = 7;
2735 class CondUnaryRSY<string mnemonic, bits<16> opcode,
2736 SDPatternOperator operator, RegisterOperand cls,
2737 bits<5> bytes, AddressingMode mode = bdaddr20only>
2738 : InstRSYb<opcode, (outs cls:$R1),
2739 (ins cls:$R1src, mode:$BD2, cond4:$valid, cond4:$M3),
2740 mnemonic#"$M3\t$R1, $BD2",
2742 (z_select_ccmask (operator bdaddr20only:$BD2), cls:$R1src,
2743 cond4:$valid, cond4:$M3))]> {
2744 let Constraints = "$R1 = $R1src";
2745 let DisableEncoding = "$R1src";
2747 let AccessBytes = bytes;
2751 // Like CondUnaryRSY, but used for the raw assembly form. The condition-code
2752 // mask is the third operand rather than being part of the mnemonic.
2753 class AsmCondUnaryRSY<string mnemonic, bits<16> opcode,
2754 RegisterOperand cls, bits<5> bytes,
2755 AddressingMode mode = bdaddr20only>
2756 : InstRSYb<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$BD2, imm32zx4:$M3),
2757 mnemonic#"\t$R1, $BD2, $M3", []> {
2759 let AccessBytes = bytes;
2760 let Constraints = "$R1 = $R1src";
2761 let DisableEncoding = "$R1src";
2764 // Like CondUnaryRSY, but with a fixed CC mask.
2765 class FixedCondUnaryRSY<CondVariant V, string mnemonic, bits<16> opcode,
2766 RegisterOperand cls, bits<5> bytes,
2767 AddressingMode mode = bdaddr20only>
2768 : InstRSYb<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$BD2),
2769 mnemonic#V.suffix#"\t$R1, $BD2", []> {
2770 let Constraints = "$R1 = $R1src";
2771 let DisableEncoding = "$R1src";
2773 let AccessBytes = bytes;
2774 let isAsmParserOnly = V.alternate;
2778 multiclass CondUnaryRSYPair<string mnemonic, bits<16> opcode,
2779 SDPatternOperator operator,
2780 RegisterOperand cls, bits<5> bytes,
2781 AddressingMode mode = bdaddr20only> {
2782 let isCodeGenOnly = 1 in
2783 def "" : CondUnaryRSY<mnemonic, opcode, operator, cls, bytes, mode>;
2784 def Asm : AsmCondUnaryRSY<mnemonic, opcode, cls, bytes, mode>;
2788 class UnaryRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
2789 RegisterOperand cls, bits<5> bytes,
2790 AddressingMode mode = bdxaddr12only>
2791 : InstRXa<opcode, (outs cls:$R1), (ins mode:$XBD2),
2792 mnemonic#"\t$R1, $XBD2",
2793 [(set cls:$R1, (operator mode:$XBD2))]> {
2794 let OpKey = mnemonic#"r"#cls;
2797 let AccessBytes = bytes;
2800 class UnaryRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2801 RegisterOperand cls, bits<5> bytes>
2802 : InstRXE<opcode, (outs cls:$R1), (ins bdxaddr12only:$XBD2),
2803 mnemonic#"\t$R1, $XBD2",
2804 [(set cls:$R1, (operator bdxaddr12only:$XBD2))]> {
2805 let OpKey = mnemonic#"r"#cls;
2808 let AccessBytes = bytes;
2812 class UnaryRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2813 RegisterOperand cls, bits<5> bytes,
2814 AddressingMode mode = bdxaddr20only>
2815 : InstRXYa<opcode, (outs cls:$R1), (ins mode:$XBD2),
2816 mnemonic#"\t$R1, $XBD2",
2817 [(set cls:$R1, (operator mode:$XBD2))]> {
2818 let OpKey = mnemonic#"r"#cls;
2821 let AccessBytes = bytes;
2824 multiclass UnaryRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
2825 SDPatternOperator operator, RegisterOperand cls,
2827 let DispKey = mnemonic ## #cls in {
2828 let DispSize = "12" in
2829 def "" : UnaryRX<mnemonic, rxOpcode, operator, cls, bytes, bdxaddr12pair>;
2830 let DispSize = "20" in
2831 def Y : UnaryRXY<mnemonic#"y", rxyOpcode, operator, cls, bytes,
2836 class UnaryVRIa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2837 TypedReg tr, Immediate imm, bits<4> type = 0>
2838 : InstVRIa<opcode, (outs tr.op:$V1), (ins imm:$I2),
2839 mnemonic#"\t$V1, $I2",
2840 [(set tr.op:$V1, (tr.vt (operator imm:$I2)))]> {
2844 class UnaryVRIaGeneric<string mnemonic, bits<16> opcode, Immediate imm>
2845 : InstVRIa<opcode, (outs VR128:$V1), (ins imm:$I2, imm32zx4:$M3),
2846 mnemonic#"\t$V1, $I2, $M3", []>;
2848 class UnaryVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2849 TypedReg tr1, TypedReg tr2, bits<4> type = 0, bits<4> m4 = 0,
2851 : InstVRRa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2),
2852 mnemonic#"\t$V1, $V2",
2853 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2))))]> {
2859 class UnaryVRRaGeneric<string mnemonic, bits<16> opcode, bits<4> m4 = 0,
2861 : InstVRRa<opcode, (outs VR128:$V1), (ins VR128:$V2, imm32zx4:$M3),
2862 mnemonic#"\t$V1, $V2, $M3", []> {
2867 class UnaryVRRaFloatGeneric<string mnemonic, bits<16> opcode, bits<4> m5 = 0>
2868 : InstVRRa<opcode, (outs VR128:$V1),
2869 (ins VR128:$V2, imm32zx4:$M3, imm32zx4:$M4),
2870 mnemonic#"\t$V1, $V2, $M3, $M4", []> {
2874 // Declare a pair of instructions, one which sets CC and one which doesn't.
2875 // The CC-setting form ends with "S" and sets the low bit of M5.
2876 // The form that does not set CC has an extra operand to optionally allow
2877 // specifying arbitrary M5 values in assembler.
2878 multiclass UnaryExtraVRRaSPair<string mnemonic, bits<16> opcode,
2879 SDPatternOperator operator,
2880 SDPatternOperator operator_cc,
2881 TypedReg tr1, TypedReg tr2, bits<4> type> {
2882 let M3 = type, M4 = 0 in
2883 def "" : InstVRRa<opcode, (outs tr1.op:$V1),
2884 (ins tr2.op:$V2, imm32zx4:$M5),
2885 mnemonic#"\t$V1, $V2, $M5", []>;
2886 def : Pat<(tr1.vt (operator (tr2.vt tr2.op:$V2))),
2887 (!cast<Instruction>(NAME) tr2.op:$V2, 0)>;
2888 def : InstAlias<mnemonic#"\t$V1, $V2",
2889 (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2, 0)>;
2891 def S : UnaryVRRa<mnemonic##"s", opcode, operator_cc, tr1, tr2,
2895 multiclass UnaryExtraVRRaSPairGeneric<string mnemonic, bits<16> opcode> {
2897 def "" : InstVRRa<opcode, (outs VR128:$V1),
2898 (ins VR128:$V2, imm32zx4:$M3, imm32zx4:$M5),
2899 mnemonic#"\t$V1, $V2, $M3, $M5", []>;
2900 def : InstAlias<mnemonic#"\t$V1, $V2, $M3",
2901 (!cast<Instruction>(NAME) VR128:$V1, VR128:$V2,
2905 class UnaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2906 TypedReg tr, bits<5> bytes, bits<4> type = 0>
2907 : InstVRX<opcode, (outs tr.op:$V1), (ins bdxaddr12only:$XBD2),
2908 mnemonic#"\t$V1, $XBD2",
2909 [(set tr.op:$V1, (tr.vt (operator bdxaddr12only:$XBD2)))]> {
2912 let AccessBytes = bytes;
2915 class UnaryVRXGeneric<string mnemonic, bits<16> opcode>
2916 : InstVRX<opcode, (outs VR128:$V1), (ins bdxaddr12only:$XBD2, imm32zx4:$M3),
2917 mnemonic#"\t$V1, $XBD2, $M3", []> {
2921 class SideEffectBinaryRX<string mnemonic, bits<8> opcode,
2922 RegisterOperand cls>
2923 : InstRXa<opcode, (outs), (ins cls:$R1, bdxaddr12only:$XBD2),
2924 mnemonic##"\t$R1, $XBD2", []>;
2926 class SideEffectBinaryRXY<string mnemonic, bits<16> opcode,
2927 RegisterOperand cls>
2928 : InstRXYa<opcode, (outs), (ins cls:$R1, bdxaddr20only:$XBD2),
2929 mnemonic##"\t$R1, $XBD2", []>;
2931 class SideEffectBinaryRILPC<string mnemonic, bits<12> opcode,
2932 RegisterOperand cls>
2933 : InstRILb<opcode, (outs), (ins cls:$R1, pcrel32:$RI2),
2934 mnemonic##"\t$R1, $RI2", []> {
2935 // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
2936 // However, BDXs have two extra operands and are therefore 6 units more
2938 let AddedComplexity = 7;
2941 class SideEffectBinaryRRE<string mnemonic, bits<16> opcode,
2942 RegisterOperand cls1, RegisterOperand cls2>
2943 : InstRRE<opcode, (outs), (ins cls1:$R1, cls2:$R2),
2944 mnemonic#"\t$R1, $R2", []>;
2946 class SideEffectBinaryRRFa<string mnemonic, bits<16> opcode,
2947 RegisterOperand cls1, RegisterOperand cls2>
2948 : InstRRFa<opcode, (outs), (ins cls1:$R1, cls2:$R2),
2949 mnemonic#"\t$R1, $R2", []> {
2954 class SideEffectBinaryRRFc<string mnemonic, bits<16> opcode,
2955 RegisterOperand cls1, RegisterOperand cls2>
2956 : InstRRFc<opcode, (outs), (ins cls1:$R1, cls2:$R2),
2957 mnemonic#"\t$R1, $R2", []> {
2961 class SideEffectBinaryIE<string mnemonic, bits<16> opcode,
2962 Immediate imm1, Immediate imm2>
2963 : InstIE<opcode, (outs), (ins imm1:$I1, imm2:$I2),
2964 mnemonic#"\t$I1, $I2", []>;
2966 class SideEffectBinarySI<string mnemonic, bits<8> opcode, Operand imm>
2967 : InstSI<opcode, (outs), (ins bdaddr12only:$BD1, imm:$I2),
2968 mnemonic#"\t$BD1, $I2", []>;
2970 class SideEffectBinarySIL<string mnemonic, bits<16> opcode,
2971 SDPatternOperator operator, Immediate imm>
2972 : InstSIL<opcode, (outs), (ins bdaddr12only:$BD1, imm:$I2),
2973 mnemonic#"\t$BD1, $I2", [(operator bdaddr12only:$BD1, imm:$I2)]>;
2975 class SideEffectBinarySSa<string mnemonic, bits<8> opcode>
2976 : InstSSa<opcode, (outs), (ins bdladdr12onlylen8:$BDL1, bdaddr12only:$BD2),
2977 mnemonic##"\t$BDL1, $BD2", []>;
2979 class SideEffectBinarySSb<string mnemonic, bits<8> opcode>
2981 (outs), (ins bdladdr12onlylen4:$BDL1, bdladdr12onlylen4:$BDL2),
2982 mnemonic##"\t$BDL1, $BDL2", []>;
2984 class SideEffectBinarySSf<string mnemonic, bits<8> opcode>
2985 : InstSSf<opcode, (outs), (ins bdaddr12only:$BD1, bdladdr12onlylen8:$BDL2),
2986 mnemonic##"\t$BD1, $BDL2", []>;
2988 class SideEffectBinarySSE<string mnemonic, bits<16> opcode>
2989 : InstSSE<opcode, (outs), (ins bdaddr12only:$BD1, bdaddr12only:$BD2),
2990 mnemonic#"\t$BD1, $BD2", []>;
2992 class SideEffectBinaryMemMemRR<string mnemonic, bits<8> opcode,
2993 RegisterOperand cls1, RegisterOperand cls2>
2994 : InstRR<opcode, (outs cls1:$R1, cls2:$R2), (ins cls1:$R1src, cls2:$R2src),
2995 mnemonic#"\t$R1, $R2", []> {
2996 let Constraints = "$R1 = $R1src, $R2 = $R2src";
2997 let DisableEncoding = "$R1src, $R2src";
3000 class SideEffectBinaryMemRRE<string mnemonic, bits<16> opcode,
3001 RegisterOperand cls1, RegisterOperand cls2>
3002 : InstRRE<opcode, (outs cls2:$R2), (ins cls1:$R1, cls2:$R2src),
3003 mnemonic#"\t$R1, $R2", []> {
3004 let Constraints = "$R2 = $R2src";
3005 let DisableEncoding = "$R2src";
3008 class SideEffectBinaryMemMemRRE<string mnemonic, bits<16> opcode,
3009 RegisterOperand cls1, RegisterOperand cls2>
3010 : InstRRE<opcode, (outs cls1:$R1, cls2:$R2), (ins cls1:$R1src, cls2:$R2src),
3011 mnemonic#"\t$R1, $R2", []> {
3012 let Constraints = "$R1 = $R1src, $R2 = $R2src";
3013 let DisableEncoding = "$R1src, $R2src";
3016 class SideEffectBinaryMemMemRRFc<string mnemonic, bits<16> opcode,
3017 RegisterOperand cls1, RegisterOperand cls2>
3018 : InstRRFc<opcode, (outs cls1:$R1, cls2:$R2), (ins cls1:$R1src, cls2:$R2src),
3019 mnemonic#"\t$R1, $R2", []> {
3020 let Constraints = "$R1 = $R1src, $R2 = $R2src";
3021 let DisableEncoding = "$R1src, $R2src";
3025 class BinaryRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
3026 RegisterOperand cls1, RegisterOperand cls2>
3027 : InstRR<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
3028 mnemonic#"\t$R1, $R2",
3029 [(set cls1:$R1, (operator cls1:$R1src, cls2:$R2))]> {
3030 let OpKey = mnemonic#cls1;
3032 let Constraints = "$R1 = $R1src";
3033 let DisableEncoding = "$R1src";
3036 class BinaryRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3037 RegisterOperand cls1, RegisterOperand cls2>
3038 : InstRRE<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
3039 mnemonic#"\t$R1, $R2",
3040 [(set cls1:$R1, (operator cls1:$R1src, cls2:$R2))]> {
3041 let OpKey = mnemonic#cls1;
3043 let Constraints = "$R1 = $R1src";
3044 let DisableEncoding = "$R1src";
3047 class BinaryRRD<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3048 RegisterOperand cls1, RegisterOperand cls2>
3049 : InstRRD<opcode, (outs cls1:$R1), (ins cls2:$R3, cls2:$R2),
3050 mnemonic#"\t$R1, $R3, $R2",
3051 [(set cls1:$R1, (operator cls2:$R3, cls2:$R2))]> {
3052 let OpKey = mnemonic#cls;
3056 class BinaryRRFa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3057 RegisterOperand cls1, RegisterOperand cls2,
3058 RegisterOperand cls3>
3059 : InstRRFa<opcode, (outs cls1:$R1), (ins cls2:$R2, cls3:$R3),
3060 mnemonic#"\t$R1, $R2, $R3",
3061 [(set cls1:$R1, (operator cls2:$R2, cls3:$R3))]> {
3065 multiclass BinaryRRAndK<string mnemonic, bits<8> opcode1, bits<16> opcode2,
3066 SDPatternOperator operator, RegisterOperand cls1,
3067 RegisterOperand cls2> {
3068 let NumOpsKey = mnemonic in {
3069 let NumOpsValue = "3" in
3070 def K : BinaryRRFa<mnemonic#"k", opcode2, null_frag, cls1, cls1, cls2>,
3071 Requires<[FeatureDistinctOps]>;
3072 let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in
3073 def "" : BinaryRR<mnemonic, opcode1, operator, cls1, cls2>;
3077 multiclass BinaryRREAndK<string mnemonic, bits<16> opcode1, bits<16> opcode2,
3078 SDPatternOperator operator, RegisterOperand cls1,
3079 RegisterOperand cls2> {
3080 let NumOpsKey = mnemonic in {
3081 let NumOpsValue = "3" in
3082 def K : BinaryRRFa<mnemonic#"k", opcode2, null_frag, cls1, cls1, cls2>,
3083 Requires<[FeatureDistinctOps]>;
3084 let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in
3085 def "" : BinaryRRE<mnemonic, opcode1, operator, cls1, cls2>;
3089 class BinaryRRFb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3090 RegisterOperand cls1, RegisterOperand cls2,
3091 RegisterOperand cls3>
3092 : InstRRFb<opcode, (outs cls1:$R1), (ins cls2:$R2, cls3:$R3),
3093 mnemonic#"\t$R1, $R3, $R2",
3094 [(set cls1:$R1, (operator cls2:$R2, cls3:$R3))]> {
3098 class BinaryMemRRFc<string mnemonic, bits<16> opcode,
3099 RegisterOperand cls1, RegisterOperand cls2, Immediate imm>
3100 : InstRRFc<opcode, (outs cls2:$R2, cls1:$R1), (ins cls1:$R1src, imm:$M3),
3101 mnemonic#"\t$R1, $R2, $M3", []> {
3102 let Constraints = "$R1 = $R1src";
3103 let DisableEncoding = "$R1src";
3106 multiclass BinaryMemRRFcOpt<string mnemonic, bits<16> opcode,
3107 RegisterOperand cls1, RegisterOperand cls2> {
3108 def "" : BinaryMemRRFc<mnemonic, opcode, cls1, cls2, imm32zx4>;
3109 def Opt : UnaryMemRRFc<mnemonic, opcode, cls1, cls2>;
3112 class BinaryRRFd<string mnemonic, bits<16> opcode, RegisterOperand cls1,
3113 RegisterOperand cls2>
3114 : InstRRFd<opcode, (outs cls1:$R1), (ins cls2:$R2, imm32zx4:$M4),
3115 mnemonic#"\t$R1, $R2, $M4", []>;
3117 class BinaryRRFe<string mnemonic, bits<16> opcode, RegisterOperand cls1,
3118 RegisterOperand cls2>
3119 : InstRRFe<opcode, (outs cls1:$R1), (ins imm32zx4:$M3, cls2:$R2),
3120 mnemonic#"\t$R1, $M3, $R2", []> {
3124 class CondBinaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
3125 RegisterOperand cls2>
3126 : InstRRFc<opcode, (outs cls1:$R1),
3127 (ins cls1:$R1src, cls2:$R2, cond4:$valid, cond4:$M3),
3128 mnemonic#"$M3\t$R1, $R2", []> {
3129 let Constraints = "$R1 = $R1src";
3130 let DisableEncoding = "$R1src";
3134 // Like CondBinaryRRF, but used for the raw assembly form. The condition-code
3135 // mask is the third operand rather than being part of the mnemonic.
3136 class AsmCondBinaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
3137 RegisterOperand cls2>
3138 : InstRRFc<opcode, (outs cls1:$R1),
3139 (ins cls1:$R1src, cls2:$R2, imm32zx4:$M3),
3140 mnemonic#"\t$R1, $R2, $M3", []> {
3141 let Constraints = "$R1 = $R1src";
3142 let DisableEncoding = "$R1src";
3145 // Like CondBinaryRRF, but with a fixed CC mask.
3146 class FixedCondBinaryRRF<CondVariant V, string mnemonic, bits<16> opcode,
3147 RegisterOperand cls1, RegisterOperand cls2>
3148 : InstRRFc<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
3149 mnemonic#V.suffix#"\t$R1, $R2", []> {
3150 let Constraints = "$R1 = $R1src";
3151 let DisableEncoding = "$R1src";
3152 let isAsmParserOnly = V.alternate;
3156 multiclass CondBinaryRRFPair<string mnemonic, bits<16> opcode,
3157 RegisterOperand cls1, RegisterOperand cls2> {
3158 let isCodeGenOnly = 1 in
3159 def "" : CondBinaryRRF<mnemonic, opcode, cls1, cls2>;
3160 def Asm : AsmCondBinaryRRF<mnemonic, opcode, cls1, cls2>;
3163 class BinaryRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
3164 RegisterOperand cls, Immediate imm>
3165 : InstRIa<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
3166 mnemonic#"\t$R1, $I2",
3167 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
3168 let Constraints = "$R1 = $R1src";
3169 let DisableEncoding = "$R1src";
3172 class BinaryRIE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3173 RegisterOperand cls, Immediate imm>
3174 : InstRIEd<opcode, (outs cls:$R1), (ins cls:$R3, imm:$I2),
3175 mnemonic#"\t$R1, $R3, $I2",
3176 [(set cls:$R1, (operator cls:$R3, imm:$I2))]>;
3178 multiclass BinaryRIAndK<string mnemonic, bits<12> opcode1, bits<16> opcode2,
3179 SDPatternOperator operator, RegisterOperand cls,
3181 let NumOpsKey = mnemonic in {
3182 let NumOpsValue = "3" in
3183 def K : BinaryRIE<mnemonic##"k", opcode2, null_frag, cls, imm>,
3184 Requires<[FeatureDistinctOps]>;
3185 let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in
3186 def "" : BinaryRI<mnemonic, opcode1, operator, cls, imm>;
3190 class CondBinaryRIE<string mnemonic, bits<16> opcode, RegisterOperand cls,
3192 : InstRIEg<opcode, (outs cls:$R1),
3193 (ins cls:$R1src, imm:$I2, cond4:$valid, cond4:$M3),
3194 mnemonic#"$M3\t$R1, $I2",
3195 [(set cls:$R1, (z_select_ccmask imm:$I2, cls:$R1src,
3196 cond4:$valid, cond4:$M3))]> {
3197 let Constraints = "$R1 = $R1src";
3198 let DisableEncoding = "$R1src";
3202 // Like CondBinaryRIE, but used for the raw assembly form. The condition-code
3203 // mask is the third operand rather than being part of the mnemonic.
3204 class AsmCondBinaryRIE<string mnemonic, bits<16> opcode, RegisterOperand cls,
3206 : InstRIEg<opcode, (outs cls:$R1),
3207 (ins cls:$R1src, imm:$I2, imm32zx4:$M3),
3208 mnemonic#"\t$R1, $I2, $M3", []> {
3209 let Constraints = "$R1 = $R1src";
3210 let DisableEncoding = "$R1src";
3213 // Like CondBinaryRIE, but with a fixed CC mask.
3214 class FixedCondBinaryRIE<CondVariant V, string mnemonic, bits<16> opcode,
3215 RegisterOperand cls, Immediate imm>
3216 : InstRIEg<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
3217 mnemonic#V.suffix#"\t$R1, $I2", []> {
3218 let Constraints = "$R1 = $R1src";
3219 let DisableEncoding = "$R1src";
3220 let isAsmParserOnly = V.alternate;
3224 multiclass CondBinaryRIEPair<string mnemonic, bits<16> opcode,
3225 RegisterOperand cls, Immediate imm> {
3226 let isCodeGenOnly = 1 in
3227 def "" : CondBinaryRIE<mnemonic, opcode, cls, imm>;
3228 def Asm : AsmCondBinaryRIE<mnemonic, opcode, cls, imm>;
3231 class BinaryRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator,
3232 RegisterOperand cls, Immediate imm>
3233 : InstRILa<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
3234 mnemonic#"\t$R1, $I2",
3235 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
3236 let Constraints = "$R1 = $R1src";
3237 let DisableEncoding = "$R1src";
3240 class BinaryRS<string mnemonic, bits<8> opcode, SDPatternOperator operator,
3241 RegisterOperand cls>
3242 : InstRSa<opcode, (outs cls:$R1), (ins cls:$R1src, shift12only:$BD2),
3243 mnemonic#"\t$R1, $BD2",
3244 [(set cls:$R1, (operator cls:$R1src, shift12only:$BD2))]> {
3246 let Constraints = "$R1 = $R1src";
3247 let DisableEncoding = "$R1src";
3250 class BinaryRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3251 RegisterOperand cls>
3252 : InstRSYa<opcode, (outs cls:$R1), (ins cls:$R3, shift20only:$BD2),
3253 mnemonic#"\t$R1, $R3, $BD2",
3254 [(set cls:$R1, (operator cls:$R3, shift20only:$BD2))]>;
3256 multiclass BinaryRSAndK<string mnemonic, bits<8> opcode1, bits<16> opcode2,
3257 SDPatternOperator operator, RegisterOperand cls> {
3258 let NumOpsKey = mnemonic in {
3259 let NumOpsValue = "3" in
3260 def K : BinaryRSY<mnemonic##"k", opcode2, null_frag, cls>,
3261 Requires<[FeatureDistinctOps]>;
3262 let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in
3263 def "" : BinaryRS<mnemonic, opcode1, operator, cls>;
3267 class BinaryRSL<string mnemonic, bits<16> opcode, RegisterOperand cls>
3268 : InstRSLb<opcode, (outs cls:$R1),
3269 (ins bdladdr12onlylen8:$BDL2, imm32zx4:$M3),
3270 mnemonic#"\t$R1, $BDL2, $M3", []> {
3274 class BinaryRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
3275 RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
3276 AddressingMode mode = bdxaddr12only>
3277 : InstRXa<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$XBD2),
3278 mnemonic#"\t$R1, $XBD2",
3279 [(set cls:$R1, (operator cls:$R1src, (load mode:$XBD2)))]> {
3280 let OpKey = mnemonic#"r"#cls;
3282 let Constraints = "$R1 = $R1src";
3283 let DisableEncoding = "$R1src";
3285 let AccessBytes = bytes;
3288 class BinaryRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3289 RegisterOperand cls, SDPatternOperator load, bits<5> bytes>
3290 : InstRXE<opcode, (outs cls:$R1), (ins cls:$R1src, bdxaddr12only:$XBD2),
3291 mnemonic#"\t$R1, $XBD2",
3292 [(set cls:$R1, (operator cls:$R1src,
3293 (load bdxaddr12only:$XBD2)))]> {
3294 let OpKey = mnemonic#"r"#cls;
3296 let Constraints = "$R1 = $R1src";
3297 let DisableEncoding = "$R1src";
3299 let AccessBytes = bytes;
3303 class BinaryRXF<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3304 RegisterOperand cls1, RegisterOperand cls2,
3305 SDPatternOperator load, bits<5> bytes>
3306 : InstRXF<opcode, (outs cls1:$R1), (ins cls2:$R3, bdxaddr12only:$XBD2),
3307 mnemonic#"\t$R1, $R3, $XBD2",
3308 [(set cls1:$R1, (operator cls2:$R3, (load bdxaddr12only:$XBD2)))]> {
3309 let OpKey = mnemonic#"r"#cls;
3312 let AccessBytes = bytes;
3315 class BinaryRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3316 RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
3317 AddressingMode mode = bdxaddr20only>
3318 : InstRXYa<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$XBD2),
3319 mnemonic#"\t$R1, $XBD2",
3320 [(set cls:$R1, (operator cls:$R1src, (load mode:$XBD2)))]> {
3321 let OpKey = mnemonic#"r"#cls;
3323 let Constraints = "$R1 = $R1src";
3324 let DisableEncoding = "$R1src";
3326 let AccessBytes = bytes;
3329 multiclass BinaryRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
3330 SDPatternOperator operator, RegisterOperand cls,
3331 SDPatternOperator load, bits<5> bytes> {
3332 let DispKey = mnemonic ## #cls in {
3333 let DispSize = "12" in
3334 def "" : BinaryRX<mnemonic, rxOpcode, operator, cls, load, bytes,
3336 let DispSize = "20" in
3337 def Y : BinaryRXY<mnemonic#"y", rxyOpcode, operator, cls, load, bytes,
3342 class BinarySI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
3343 Operand imm, AddressingMode mode = bdaddr12only>
3344 : InstSI<opcode, (outs), (ins mode:$BD1, imm:$I2),
3345 mnemonic#"\t$BD1, $I2",
3346 [(store (operator (load mode:$BD1), imm:$I2), mode:$BD1)]> {
3351 class BinarySIY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3352 Operand imm, AddressingMode mode = bdaddr20only>
3353 : InstSIY<opcode, (outs), (ins mode:$BD1, imm:$I2),
3354 mnemonic#"\t$BD1, $I2",
3355 [(store (operator (load mode:$BD1), imm:$I2), mode:$BD1)]> {
3360 multiclass BinarySIPair<string mnemonic, bits<8> siOpcode,
3361 bits<16> siyOpcode, SDPatternOperator operator,
3363 let DispKey = mnemonic ## #cls in {
3364 let DispSize = "12" in
3365 def "" : BinarySI<mnemonic, siOpcode, operator, imm, bdaddr12pair>;
3366 let DispSize = "20" in
3367 def Y : BinarySIY<mnemonic#"y", siyOpcode, operator, imm, bdaddr20pair>;
3371 class BinarySSF<string mnemonic, bits<12> opcode, RegisterOperand cls>
3372 : InstSSF<opcode, (outs cls:$R3), (ins bdaddr12pair:$BD1, bdaddr12pair:$BD2),
3373 mnemonic#"\t$R3, $BD1, $BD2", []> {
3377 class BinaryVRIb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3378 TypedReg tr, bits<4> type>
3379 : InstVRIb<opcode, (outs tr.op:$V1), (ins imm32zx8:$I2, imm32zx8:$I3),
3380 mnemonic#"\t$V1, $I2, $I3",
3381 [(set tr.op:$V1, (tr.vt (operator imm32zx8:$I2, imm32zx8:$I3)))]> {
3385 class BinaryVRIbGeneric<string mnemonic, bits<16> opcode>
3386 : InstVRIb<opcode, (outs VR128:$V1),
3387 (ins imm32zx8:$I2, imm32zx8:$I3, imm32zx4:$M4),
3388 mnemonic#"\t$V1, $I2, $I3, $M4", []>;
3390 class BinaryVRIc<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3391 TypedReg tr1, TypedReg tr2, bits<4> type>
3392 : InstVRIc<opcode, (outs tr1.op:$V1), (ins tr2.op:$V3, imm32zx16:$I2),
3393 mnemonic#"\t$V1, $V3, $I2",
3394 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V3),
3395 imm32zx16:$I2)))]> {
3399 class BinaryVRIcGeneric<string mnemonic, bits<16> opcode>
3400 : InstVRIc<opcode, (outs VR128:$V1),
3401 (ins VR128:$V3, imm32zx16:$I2, imm32zx4:$M4),
3402 mnemonic#"\t$V1, $V3, $I2, $M4", []>;
3404 class BinaryVRIe<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3405 TypedReg tr1, TypedReg tr2, bits<4> type, bits<4> m5>
3406 : InstVRIe<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, imm32zx12:$I3),
3407 mnemonic#"\t$V1, $V2, $I3",
3408 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
3409 imm32zx12:$I3)))]> {
3414 class BinaryVRIeFloatGeneric<string mnemonic, bits<16> opcode>
3415 : InstVRIe<opcode, (outs VR128:$V1),
3416 (ins VR128:$V2, imm32zx12:$I3, imm32zx4:$M4, imm32zx4:$M5),
3417 mnemonic#"\t$V1, $V2, $I3, $M4, $M5", []>;
3419 class BinaryVRIh<string mnemonic, bits<16> opcode>
3420 : InstVRIh<opcode, (outs VR128:$V1),
3421 (ins imm32zx16:$I2, imm32zx4:$I3),
3422 mnemonic#"\t$V1, $I2, $I3", []>;
3424 class BinaryVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3425 TypedReg tr1, TypedReg tr2, bits<4> type = 0, bits<4> m4 = 0>
3426 : InstVRRa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, imm32zx4:$M5),
3427 mnemonic#"\t$V1, $V2, $M5",
3428 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
3429 imm32zx12:$M5)))]> {
3434 class BinaryVRRaFloatGeneric<string mnemonic, bits<16> opcode>
3435 : InstVRRa<opcode, (outs VR128:$V1),
3436 (ins VR128:$V2, imm32zx4:$M3, imm32zx4:$M4, imm32zx4:$M5),
3437 mnemonic#"\t$V1, $V2, $M3, $M4, $M5", []>;
3439 class BinaryVRRb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3440 TypedReg tr1, TypedReg tr2, bits<4> type = 0,
3441 bits<4> modifier = 0>
3442 : InstVRRb<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, tr2.op:$V3),
3443 mnemonic#"\t$V1, $V2, $V3",
3444 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
3445 (tr2.vt tr2.op:$V3))))]> {
3450 // Declare a pair of instructions, one which sets CC and one which doesn't.
3451 // The CC-setting form ends with "S" and sets the low bit of M5.
3452 multiclass BinaryVRRbSPair<string mnemonic, bits<16> opcode,
3453 SDPatternOperator operator,
3454 SDPatternOperator operator_cc, TypedReg tr1,
3455 TypedReg tr2, bits<4> type, bits<4> modifier = 0> {
3456 def "" : BinaryVRRb<mnemonic, opcode, operator, tr1, tr2, type,
3457 !and (modifier, 14)>;
3459 def S : BinaryVRRb<mnemonic##"s", opcode, operator_cc, tr1, tr2, type,
3460 !add (!and (modifier, 14), 1)>;
3463 class BinaryVRRbSPairGeneric<string mnemonic, bits<16> opcode>
3464 : InstVRRb<opcode, (outs VR128:$V1),
3465 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5),
3466 mnemonic#"\t$V1, $V2, $V3, $M4, $M5", []>;
3468 // Declare a pair of instructions, one which sets CC and one which doesn't.
3469 // The CC-setting form ends with "S" and sets the low bit of M5.
3470 // The form that does not set CC has an extra operand to optionally allow
3471 // specifying arbitrary M5 values in assembler.
3472 multiclass BinaryExtraVRRbSPair<string mnemonic, bits<16> opcode,
3473 SDPatternOperator operator,
3474 SDPatternOperator operator_cc,
3475 TypedReg tr1, TypedReg tr2, bits<4> type> {
3477 def "" : InstVRRb<opcode, (outs tr1.op:$V1),
3478 (ins tr2.op:$V2, tr2.op:$V3, imm32zx4:$M5),
3479 mnemonic#"\t$V1, $V2, $V3, $M5", []>;
3480 def : Pat<(tr1.vt (operator (tr2.vt tr2.op:$V2), (tr2.vt tr2.op:$V3))),
3481 (!cast<Instruction>(NAME) tr2.op:$V2, tr2.op:$V3, 0)>;
3482 def : InstAlias<mnemonic#"\t$V1, $V2, $V3",
3483 (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2,
3486 def S : BinaryVRRb<mnemonic##"s", opcode, operator_cc, tr1, tr2, type, 1>;
3489 multiclass BinaryExtraVRRbSPairGeneric<string mnemonic, bits<16> opcode> {
3490 def "" : InstVRRb<opcode, (outs VR128:$V1),
3491 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5),
3492 mnemonic#"\t$V1, $V2, $V3, $M4, $M5", []>;
3493 def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $M4",
3494 (!cast<Instruction>(NAME) VR128:$V1, VR128:$V2, VR128:$V3,
3498 class BinaryVRRc<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3499 TypedReg tr1, TypedReg tr2, bits<4> type = 0, bits<4> m5 = 0,
3501 : InstVRRc<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, tr2.op:$V3),
3502 mnemonic#"\t$V1, $V2, $V3",
3503 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
3504 (tr2.vt tr2.op:$V3))))]> {
3510 class BinaryVRRcGeneric<string mnemonic, bits<16> opcode, bits<4> m5 = 0,
3512 : InstVRRc<opcode, (outs VR128:$V1),
3513 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4),
3514 mnemonic#"\t$V1, $V2, $V3, $M4", []> {
3519 class BinaryVRRcFloatGeneric<string mnemonic, bits<16> opcode, bits<4> m6 = 0>
3520 : InstVRRc<opcode, (outs VR128:$V1),
3521 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5),
3522 mnemonic#"\t$V1, $V2, $V3, $M4, $M5", []> {
3526 // Declare a pair of instructions, one which sets CC and one which doesn't.
3527 // The CC-setting form ends with "S" and sets the low bit of M5.
3528 multiclass BinaryVRRcSPair<string mnemonic, bits<16> opcode,
3529 SDPatternOperator operator,
3530 SDPatternOperator operator_cc, TypedReg tr1,
3531 TypedReg tr2, bits<4> type, bits<4> m5,
3532 bits<4> modifier = 0> {
3533 def "" : BinaryVRRc<mnemonic, opcode, operator, tr1, tr2, type,
3534 m5, !and (modifier, 14)>;
3536 def S : BinaryVRRc<mnemonic##"s", opcode, operator_cc, tr1, tr2, type,
3537 m5, !add (!and (modifier, 14), 1)>;
3540 class BinaryVRRcSPairFloatGeneric<string mnemonic, bits<16> opcode>
3541 : InstVRRc<opcode, (outs VR128:$V1),
3542 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5,
3544 mnemonic#"\t$V1, $V2, $V3, $M4, $M5, $M6", []>;
3546 class BinaryVRRf<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3548 : InstVRRf<opcode, (outs tr.op:$V1), (ins GR64:$R2, GR64:$R3),
3549 mnemonic#"\t$V1, $R2, $R3",
3550 [(set tr.op:$V1, (tr.vt (operator GR64:$R2, GR64:$R3)))]>;
3552 class BinaryVRRi<string mnemonic, bits<16> opcode, RegisterOperand cls>
3553 : InstVRRi<opcode, (outs cls:$R1), (ins VR128:$V2, imm32zx4:$M3),
3554 mnemonic#"\t$R1, $V2, $M3", []>;
3556 class BinaryVRSa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3557 TypedReg tr1, TypedReg tr2, bits<4> type>
3558 : InstVRSa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V3, shift12only:$BD2),
3559 mnemonic#"\t$V1, $V3, $BD2",
3560 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V3),
3561 shift12only:$BD2)))]> {
3565 class BinaryVRSaGeneric<string mnemonic, bits<16> opcode>
3566 : InstVRSa<opcode, (outs VR128:$V1),
3567 (ins VR128:$V3, shift12only:$BD2, imm32zx4:$M4),
3568 mnemonic#"\t$V1, $V3, $BD2, $M4", []>;
3570 class BinaryVRSb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3572 : InstVRSb<opcode, (outs VR128:$V1), (ins GR32:$R3, bdaddr12only:$BD2),
3573 mnemonic#"\t$V1, $R3, $BD2",
3574 [(set VR128:$V1, (operator GR32:$R3, bdaddr12only:$BD2))]> {
3577 let AccessBytes = bytes;
3580 class BinaryVRSc<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3581 TypedReg tr, bits<4> type>
3582 : InstVRSc<opcode, (outs GR64:$R1), (ins tr.op:$V3, shift12only:$BD2),
3583 mnemonic#"\t$R1, $V3, $BD2",
3584 [(set GR64:$R1, (operator (tr.vt tr.op:$V3), shift12only:$BD2))]> {
3588 class BinaryVRScGeneric<string mnemonic, bits<16> opcode>
3589 : InstVRSc<opcode, (outs GR64:$R1),
3590 (ins VR128:$V3, shift12only:$BD2, imm32zx4: $M4),
3591 mnemonic#"\t$R1, $V3, $BD2, $M4", []>;
3593 class BinaryVRSd<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3595 : InstVRSd<opcode, (outs VR128:$V1), (ins GR32:$R3, bdaddr12only:$BD2),
3596 mnemonic#"\t$V1, $R3, $BD2",
3597 [(set VR128:$V1, (operator GR32:$R3, bdaddr12only:$BD2))]> {
3599 let AccessBytes = bytes;
3602 class BinaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3603 TypedReg tr, bits<5> bytes>
3604 : InstVRX<opcode, (outs VR128:$V1), (ins bdxaddr12only:$XBD2, imm32zx4:$M3),
3605 mnemonic#"\t$V1, $XBD2, $M3",
3606 [(set tr.op:$V1, (tr.vt (operator bdxaddr12only:$XBD2,
3609 let AccessBytes = bytes;
3612 class StoreBinaryRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
3613 bits<5> bytes, AddressingMode mode = bdaddr12only>
3614 : InstRSb<opcode, (outs), (ins cls:$R1, imm32zx4:$M3, mode:$BD2),
3615 mnemonic#"\t$R1, $M3, $BD2", []> {
3617 let AccessBytes = bytes;
3620 class StoreBinaryRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
3621 bits<5> bytes, AddressingMode mode = bdaddr20only>
3622 : InstRSYb<opcode, (outs), (ins cls:$R1, imm32zx4:$M3, mode:$BD2),
3623 mnemonic#"\t$R1, $M3, $BD2", []> {
3625 let AccessBytes = bytes;
3628 multiclass StoreBinaryRSPair<string mnemonic, bits<8> rsOpcode,
3629 bits<16> rsyOpcode, RegisterOperand cls,
3631 let DispKey = mnemonic ## #cls in {
3632 let DispSize = "12" in
3633 def "" : StoreBinaryRS<mnemonic, rsOpcode, cls, bytes, bdaddr12pair>;
3634 let DispSize = "20" in
3635 def Y : StoreBinaryRSY<mnemonic#"y", rsyOpcode, cls, bytes,
3640 class StoreBinaryRSL<string mnemonic, bits<16> opcode, RegisterOperand cls>
3641 : InstRSLb<opcode, (outs),
3642 (ins cls:$R1, bdladdr12onlylen8:$BDL2, imm32zx4:$M3),
3643 mnemonic#"\t$R1, $BDL2, $M3", []> {
3647 class BinaryVSI<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3649 : InstVSI<opcode, (outs VR128:$V1), (ins bdaddr12only:$BD2, imm32zx8:$I3),
3650 mnemonic#"\t$V1, $BD2, $I3",
3651 [(set VR128:$V1, (operator imm32zx8:$I3, bdaddr12only:$BD2))]> {
3653 let AccessBytes = bytes;
3656 class StoreBinaryVRV<string mnemonic, bits<16> opcode, bits<5> bytes,
3658 : InstVRV<opcode, (outs), (ins VR128:$V1, bdvaddr12only:$VBD2, index:$M3),
3659 mnemonic#"\t$V1, $VBD2, $M3", []> {
3661 let AccessBytes = bytes;
3664 class StoreBinaryVRX<string mnemonic, bits<16> opcode,
3665 SDPatternOperator operator, TypedReg tr, bits<5> bytes,
3667 : InstVRX<opcode, (outs), (ins tr.op:$V1, bdxaddr12only:$XBD2, index:$M3),
3668 mnemonic#"\t$V1, $XBD2, $M3",
3669 [(operator (tr.vt tr.op:$V1), bdxaddr12only:$XBD2, index:$M3)]> {
3671 let AccessBytes = bytes;
3674 class MemoryBinarySSd<string mnemonic, bits<8> opcode,
3675 RegisterOperand cls>
3676 : InstSSd<opcode, (outs),
3677 (ins bdraddr12only:$RBD1, bdaddr12only:$BD2, cls:$R3),
3678 mnemonic#"\t$RBD1, $BD2, $R3", []>;
3680 class CompareRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
3681 RegisterOperand cls1, RegisterOperand cls2>
3682 : InstRR<opcode, (outs), (ins cls1:$R1, cls2:$R2),
3683 mnemonic#"\t$R1, $R2",
3684 [(operator cls1:$R1, cls2:$R2)]> {
3685 let OpKey = mnemonic#cls1;
3690 class CompareRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3691 RegisterOperand cls1, RegisterOperand cls2>
3692 : InstRRE<opcode, (outs), (ins cls1:$R1, cls2:$R2),
3693 mnemonic#"\t$R1, $R2",
3694 [(operator cls1:$R1, cls2:$R2)]> {
3695 let OpKey = mnemonic#cls1;
3700 class CompareRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
3701 RegisterOperand cls, Immediate imm>
3702 : InstRIa<opcode, (outs), (ins cls:$R1, imm:$I2),
3703 mnemonic#"\t$R1, $I2",
3704 [(operator cls:$R1, imm:$I2)]> {
3708 class CompareRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator,
3709 RegisterOperand cls, Immediate imm>
3710 : InstRILa<opcode, (outs), (ins cls:$R1, imm:$I2),
3711 mnemonic#"\t$R1, $I2",
3712 [(operator cls:$R1, imm:$I2)]> {
3716 class CompareRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator,
3717 RegisterOperand cls, SDPatternOperator load>
3718 : InstRILb<opcode, (outs), (ins cls:$R1, pcrel32:$RI2),
3719 mnemonic#"\t$R1, $RI2",
3720 [(operator cls:$R1, (load pcrel32:$RI2))]> {
3723 // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
3724 // However, BDXs have two extra operands and are therefore 6 units more
3726 let AddedComplexity = 7;
3729 class CompareRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
3730 RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
3731 AddressingMode mode = bdxaddr12only>
3732 : InstRXa<opcode, (outs), (ins cls:$R1, mode:$XBD2),
3733 mnemonic#"\t$R1, $XBD2",
3734 [(operator cls:$R1, (load mode:$XBD2))]> {
3735 let OpKey = mnemonic#"r"#cls;
3739 let AccessBytes = bytes;
3742 class CompareRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3743 RegisterOperand cls, SDPatternOperator load, bits<5> bytes>
3744 : InstRXE<opcode, (outs), (ins cls:$R1, bdxaddr12only:$XBD2),
3745 mnemonic#"\t$R1, $XBD2",
3746 [(operator cls:$R1, (load bdxaddr12only:$XBD2))]> {
3747 let OpKey = mnemonic#"r"#cls;
3751 let AccessBytes = bytes;
3755 class CompareRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3756 RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
3757 AddressingMode mode = bdxaddr20only>
3758 : InstRXYa<opcode, (outs), (ins cls:$R1, mode:$XBD2),
3759 mnemonic#"\t$R1, $XBD2",
3760 [(operator cls:$R1, (load mode:$XBD2))]> {
3761 let OpKey = mnemonic#"r"#cls;
3765 let AccessBytes = bytes;
3768 multiclass CompareRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
3769 SDPatternOperator operator, RegisterOperand cls,
3770 SDPatternOperator load, bits<5> bytes> {
3771 let DispKey = mnemonic ## #cls in {
3772 let DispSize = "12" in
3773 def "" : CompareRX<mnemonic, rxOpcode, operator, cls,
3774 load, bytes, bdxaddr12pair>;
3775 let DispSize = "20" in
3776 def Y : CompareRXY<mnemonic#"y", rxyOpcode, operator, cls,
3777 load, bytes, bdxaddr20pair>;
3781 class CompareRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
3782 bits<5> bytes, AddressingMode mode = bdaddr12only>
3783 : InstRSb<opcode, (outs), (ins cls:$R1, imm32zx4:$M3, mode:$BD2),
3784 mnemonic#"\t$R1, $M3, $BD2", []> {
3786 let AccessBytes = bytes;
3789 class CompareRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
3790 bits<5> bytes, AddressingMode mode = bdaddr20only>
3791 : InstRSYb<opcode, (outs), (ins cls:$R1, imm32zx4:$M3, mode:$BD2),
3792 mnemonic#"\t$R1, $M3, $BD2", []> {
3794 let AccessBytes = bytes;
3797 multiclass CompareRSPair<string mnemonic, bits<8> rsOpcode, bits<16> rsyOpcode,
3798 RegisterOperand cls, bits<5> bytes> {
3799 let DispKey = mnemonic ## #cls in {
3800 let DispSize = "12" in
3801 def "" : CompareRS<mnemonic, rsOpcode, cls, bytes, bdaddr12pair>;
3802 let DispSize = "20" in
3803 def Y : CompareRSY<mnemonic#"y", rsyOpcode, cls, bytes, bdaddr20pair>;
3807 class CompareSSb<string mnemonic, bits<8> opcode>
3809 (outs), (ins bdladdr12onlylen4:$BDL1, bdladdr12onlylen4:$BDL2),
3810 mnemonic##"\t$BDL1, $BDL2", []> {
3815 class CompareSI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
3816 SDPatternOperator load, Immediate imm,
3817 AddressingMode mode = bdaddr12only>
3818 : InstSI<opcode, (outs), (ins mode:$BD1, imm:$I2),
3819 mnemonic#"\t$BD1, $I2",
3820 [(operator (load mode:$BD1), imm:$I2)]> {
3825 class CompareSIL<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3826 SDPatternOperator load, Immediate imm>
3827 : InstSIL<opcode, (outs), (ins bdaddr12only:$BD1, imm:$I2),
3828 mnemonic#"\t$BD1, $I2",
3829 [(operator (load bdaddr12only:$BD1), imm:$I2)]> {
3834 class CompareSIY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3835 SDPatternOperator load, Immediate imm,
3836 AddressingMode mode = bdaddr20only>
3837 : InstSIY<opcode, (outs), (ins mode:$BD1, imm:$I2),
3838 mnemonic#"\t$BD1, $I2",
3839 [(operator (load mode:$BD1), imm:$I2)]> {
3844 multiclass CompareSIPair<string mnemonic, bits<8> siOpcode, bits<16> siyOpcode,
3845 SDPatternOperator operator, SDPatternOperator load,
3847 let DispKey = mnemonic in {
3848 let DispSize = "12" in
3849 def "" : CompareSI<mnemonic, siOpcode, operator, load, imm, bdaddr12pair>;
3850 let DispSize = "20" in
3851 def Y : CompareSIY<mnemonic#"y", siyOpcode, operator, load, imm,
3856 class CompareVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3857 TypedReg tr, bits<4> type>
3858 : InstVRRa<opcode, (outs), (ins tr.op:$V1, tr.op:$V2),
3859 mnemonic#"\t$V1, $V2",
3860 [(operator (tr.vt tr.op:$V1), (tr.vt tr.op:$V2))]> {
3867 class CompareVRRaGeneric<string mnemonic, bits<16> opcode>
3868 : InstVRRa<opcode, (outs), (ins VR128:$V1, VR128:$V2, imm32zx4:$M3),
3869 mnemonic#"\t$V1, $V2, $M3", []> {
3875 class CompareVRRaFloatGeneric<string mnemonic, bits<16> opcode>
3876 : InstVRRa<opcode, (outs),
3877 (ins VR64:$V1, VR64:$V2, imm32zx4:$M3, imm32zx4:$M4),
3878 mnemonic#"\t$V1, $V2, $M3, $M4", []> {
3883 class CompareVRRh<string mnemonic, bits<16> opcode>
3884 : InstVRRh<opcode, (outs), (ins VR128:$V1, VR128:$V2, imm32zx4:$M3),
3885 mnemonic#"\t$V1, $V2, $M3", []> {
3889 class TestRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3890 RegisterOperand cls>
3891 : InstRXE<opcode, (outs), (ins cls:$R1, bdxaddr12only:$XBD2),
3892 mnemonic#"\t$R1, $XBD2",
3893 [(operator cls:$R1, bdxaddr12only:$XBD2)]> {
3897 class TestRSL<string mnemonic, bits<16> opcode>
3898 : InstRSLa<opcode, (outs), (ins bdladdr12onlylen4:$BDL1),
3899 mnemonic#"\t$BDL1", []> {
3903 class TestVRRg<string mnemonic, bits<16> opcode>
3904 : InstVRRg<opcode, (outs), (ins VR128:$V1),
3905 mnemonic#"\t$V1", []>;
3907 class SideEffectTernarySSc<string mnemonic, bits<8> opcode>
3908 : InstSSc<opcode, (outs), (ins bdladdr12onlylen4:$BDL1,
3909 shift12only:$BD2, imm32zx4:$I3),
3910 mnemonic##"\t$BDL1, $BD2, $I3", []>;
3912 class SideEffectTernaryRRFa<string mnemonic, bits<16> opcode,
3913 RegisterOperand cls1, RegisterOperand cls2,
3914 RegisterOperand cls3>
3915 : InstRRFa<opcode, (outs), (ins cls1:$R1, cls2:$R2, cls3:$R3),
3916 mnemonic#"\t$R1, $R2, $R3", []> {
3920 class SideEffectTernaryRRFb<string mnemonic, bits<16> opcode,
3921 RegisterOperand cls1, RegisterOperand cls2,
3922 RegisterOperand cls3>
3923 : InstRRFb<opcode, (outs), (ins cls1:$R1, cls2:$R2, cls3:$R3),
3924 mnemonic#"\t$R1, $R3, $R2", []> {
3928 class SideEffectTernaryMemMemMemRRFb<string mnemonic, bits<16> opcode,
3929 RegisterOperand cls1,
3930 RegisterOperand cls2,
3931 RegisterOperand cls3>
3932 : InstRRFb<opcode, (outs cls1:$R1, cls2:$R2, cls3:$R3),
3933 (ins cls1:$R1src, cls2:$R2src, cls3:$R3src),
3934 mnemonic#"\t$R1, $R3, $R2", []> {
3935 let Constraints = "$R1 = $R1src, $R2 = $R2src, $R3 = $R3src";
3936 let DisableEncoding = "$R1src, $R2src, $R3src";
3940 class SideEffectTernaryRRFc<string mnemonic, bits<16> opcode,
3941 RegisterOperand cls1, RegisterOperand cls2,
3943 : InstRRFc<opcode, (outs), (ins cls1:$R1, cls2:$R2, imm:$M3),
3944 mnemonic#"\t$R1, $R2, $M3", []>;
3946 multiclass SideEffectTernaryRRFcOpt<string mnemonic, bits<16> opcode,
3947 RegisterOperand cls1,
3948 RegisterOperand cls2> {
3949 def "" : SideEffectTernaryRRFc<mnemonic, opcode, cls1, cls2, imm32zx4>;
3950 def Opt : SideEffectBinaryRRFc<mnemonic, opcode, cls1, cls2>;
3953 class SideEffectTernaryMemMemRRFc<string mnemonic, bits<16> opcode,
3954 RegisterOperand cls1, RegisterOperand cls2,
3956 : InstRRFc<opcode, (outs cls1:$R1, cls2:$R2),
3957 (ins cls1:$R1src, cls2:$R2src, imm:$M3),
3958 mnemonic#"\t$R1, $R2, $M3", []> {
3959 let Constraints = "$R1 = $R1src, $R2 = $R2src";
3960 let DisableEncoding = "$R1src, $R2src";
3963 multiclass SideEffectTernaryMemMemRRFcOpt<string mnemonic, bits<16> opcode,
3964 RegisterOperand cls1,
3965 RegisterOperand cls2> {
3966 def "" : SideEffectTernaryMemMemRRFc<mnemonic, opcode, cls1, cls2, imm32zx4>;
3967 def Opt : SideEffectBinaryMemMemRRFc<mnemonic, opcode, cls1, cls2>;
3970 class SideEffectTernarySSF<string mnemonic, bits<12> opcode,
3971 RegisterOperand cls>
3972 : InstSSF<opcode, (outs),
3973 (ins bdaddr12only:$BD1, bdaddr12only:$BD2, cls:$R3),
3974 mnemonic#"\t$BD1, $BD2, $R3", []>;
3976 class TernaryRRFa<string mnemonic, bits<16> opcode,
3977 RegisterOperand cls1, RegisterOperand cls2,
3978 RegisterOperand cls3>
3979 : InstRRFa<opcode, (outs cls1:$R1), (ins cls2:$R2, cls3:$R3, imm32zx4:$M4),
3980 mnemonic#"\t$R1, $R2, $R3, $M4", []>;
3982 class TernaryRRFb<string mnemonic, bits<16> opcode,
3983 RegisterOperand cls1, RegisterOperand cls2,
3984 RegisterOperand cls3>
3985 : InstRRFb<opcode, (outs cls1:$R1, cls3:$R3),
3986 (ins cls1:$R1src, cls2:$R2, imm32zx4:$M4),
3987 mnemonic#"\t$R1, $R3, $R2, $M4", []> {
3988 let Constraints = "$R1 = $R1src";
3989 let DisableEncoding = "$R1src";
3992 class TernaryRRFe<string mnemonic, bits<16> opcode, RegisterOperand cls1,
3993 RegisterOperand cls2>
3994 : InstRRFe<opcode, (outs cls1:$R1),
3995 (ins imm32zx4:$M3, cls2:$R2, imm32zx4:$M4),
3996 mnemonic#"\t$R1, $M3, $R2, $M4", []>;
3998 class TernaryRRD<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3999 RegisterOperand cls1, RegisterOperand cls2>
4000 : InstRRD<opcode, (outs cls1:$R1), (ins cls2:$R1src, cls2:$R3, cls2:$R2),
4001 mnemonic#"\t$R1, $R3, $R2",
4002 [(set cls1:$R1, (operator cls2:$R1src, cls2:$R3, cls2:$R2))]> {
4003 let OpKey = mnemonic#cls;
4005 let Constraints = "$R1 = $R1src";
4006 let DisableEncoding = "$R1src";
4009 class TernaryRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
4010 bits<5> bytes, AddressingMode mode = bdaddr12only>
4011 : InstRSb<opcode, (outs cls:$R1),
4012 (ins cls:$R1src, imm32zx4:$M3, mode:$BD2),
4013 mnemonic#"\t$R1, $M3, $BD2", []> {
4015 let Constraints = "$R1 = $R1src";
4016 let DisableEncoding = "$R1src";
4018 let AccessBytes = bytes;
4021 class TernaryRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
4022 bits<5> bytes, AddressingMode mode = bdaddr20only>
4023 : InstRSYb<opcode, (outs cls:$R1),
4024 (ins cls:$R1src, imm32zx4:$M3, mode:$BD2),
4025 mnemonic#"\t$R1, $M3, $BD2", []> {
4027 let Constraints = "$R1 = $R1src";
4028 let DisableEncoding = "$R1src";
4030 let AccessBytes = bytes;
4033 multiclass TernaryRSPair<string mnemonic, bits<8> rsOpcode, bits<16> rsyOpcode,
4034 RegisterOperand cls, bits<5> bytes> {
4035 let DispKey = mnemonic ## #cls in {
4036 let DispSize = "12" in
4037 def "" : TernaryRS<mnemonic, rsOpcode, cls, bytes, bdaddr12pair>;
4038 let DispSize = "20" in
4039 def Y : TernaryRSY<mnemonic#"y", rsyOpcode, cls, bytes, bdaddr20pair>;
4043 class SideEffectTernaryRS<string mnemonic, bits<8> opcode,
4044 RegisterOperand cls1, RegisterOperand cls2>
4045 : InstRSa<opcode, (outs),
4046 (ins cls1:$R1, cls2:$R3, bdaddr12only:$BD2),
4047 mnemonic#"\t$R1, $R3, $BD2", []>;
4049 class SideEffectTernaryRSY<string mnemonic, bits<16> opcode,
4050 RegisterOperand cls1, RegisterOperand cls2>
4051 : InstRSYa<opcode, (outs),
4052 (ins cls1:$R1, cls2:$R3, bdaddr20only:$BD2),
4053 mnemonic#"\t$R1, $R3, $BD2", []>;
4055 class SideEffectTernaryMemMemRS<string mnemonic, bits<8> opcode,
4056 RegisterOperand cls1, RegisterOperand cls2>
4057 : InstRSa<opcode, (outs cls1:$R1, cls2:$R3),
4058 (ins cls1:$R1src, cls2:$R3src, shift12only:$BD2),
4059 mnemonic#"\t$R1, $R3, $BD2", []> {
4060 let Constraints = "$R1 = $R1src, $R3 = $R3src";
4061 let DisableEncoding = "$R1src, $R3src";
4064 class SideEffectTernaryMemMemRSY<string mnemonic, bits<16> opcode,
4065 RegisterOperand cls1, RegisterOperand cls2>
4066 : InstRSYa<opcode, (outs cls1:$R1, cls2:$R3),
4067 (ins cls1:$R1src, cls2:$R3src, shift20only:$BD2),
4068 mnemonic#"\t$R1, $R3, $BD2", []> {
4069 let Constraints = "$R1 = $R1src, $R3 = $R3src";
4070 let DisableEncoding = "$R1src, $R3src";
4073 class TernaryRXF<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4074 RegisterOperand cls1, RegisterOperand cls2,
4075 SDPatternOperator load, bits<5> bytes>
4076 : InstRXF<opcode, (outs cls1:$R1),
4077 (ins cls2:$R1src, cls2:$R3, bdxaddr12only:$XBD2),
4078 mnemonic#"\t$R1, $R3, $XBD2",
4079 [(set cls1:$R1, (operator cls2:$R1src, cls2:$R3,
4080 (load bdxaddr12only:$XBD2)))]> {
4081 let OpKey = mnemonic#"r"#cls;
4083 let Constraints = "$R1 = $R1src";
4084 let DisableEncoding = "$R1src";
4086 let AccessBytes = bytes;
4089 class TernaryVRIa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4090 TypedReg tr1, TypedReg tr2, Immediate imm, Immediate index>
4091 : InstVRIa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V1src, imm:$I2, index:$M3),
4092 mnemonic#"\t$V1, $I2, $M3",
4093 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V1src),
4094 imm:$I2, index:$M3)))]> {
4095 let Constraints = "$V1 = $V1src";
4096 let DisableEncoding = "$V1src";
4099 class TernaryVRId<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4100 TypedReg tr1, TypedReg tr2, bits<4> type>
4101 : InstVRId<opcode, (outs tr1.op:$V1),
4102 (ins tr2.op:$V2, tr2.op:$V3, imm32zx8:$I4),
4103 mnemonic#"\t$V1, $V2, $V3, $I4",
4104 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
4105 (tr2.vt tr2.op:$V3),
4110 class TernaryVRIi<string mnemonic, bits<16> opcode, RegisterOperand cls>
4111 : InstVRIi<opcode, (outs VR128:$V1),
4112 (ins cls:$R2, imm32zx8:$I3, imm32zx4:$M4),
4113 mnemonic#"\t$V1, $R2, $I3, $M4", []>;
4115 class TernaryVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4116 TypedReg tr1, TypedReg tr2, bits<4> type, bits<4> m4or>
4117 : InstVRRa<opcode, (outs tr1.op:$V1),
4118 (ins tr2.op:$V2, imm32zx4:$M4, imm32zx4:$M5),
4119 mnemonic#"\t$V1, $V2, $M4, $M5",
4120 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
4127 class TernaryVRRaFloatGeneric<string mnemonic, bits<16> opcode>
4128 : InstVRRa<opcode, (outs VR128:$V1),
4129 (ins VR128:$V2, imm32zx4:$M3, imm32zx4:$M4, imm32zx4:$M5),
4130 mnemonic#"\t$V1, $V2, $M3, $M4, $M5", []>;
4132 class TernaryVRRb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4133 TypedReg tr1, TypedReg tr2, bits<4> type,
4134 SDPatternOperator m5mask, bits<4> m5or>
4135 : InstVRRb<opcode, (outs tr1.op:$V1),
4136 (ins tr2.op:$V2, tr2.op:$V3, m5mask:$M5),
4137 mnemonic#"\t$V1, $V2, $V3, $M5",
4138 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
4139 (tr2.vt tr2.op:$V3),
4145 // Declare a pair of instructions, one which sets CC and one which doesn't.
4146 // The CC-setting form ends with "S" and sets the low bit of M5.
4147 // Also create aliases to make use of M5 operand optional in assembler.
4148 multiclass TernaryOptVRRbSPair<string mnemonic, bits<16> opcode,
4149 SDPatternOperator operator,
4150 SDPatternOperator operator_cc,
4151 TypedReg tr1, TypedReg tr2, bits<4> type,
4152 bits<4> modifier = 0> {
4153 def "" : TernaryVRRb<mnemonic, opcode, operator, tr1, tr2, type,
4154 imm32zx4even, !and (modifier, 14)>;
4155 def : InstAlias<mnemonic#"\t$V1, $V2, $V3",
4156 (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2,
4159 def S : TernaryVRRb<mnemonic##"s", opcode, operator_cc, tr1, tr2, type,
4160 imm32zx4even, !add(!and (modifier, 14), 1)>;
4161 def : InstAlias<mnemonic#"s\t$V1, $V2, $V3",
4162 (!cast<Instruction>(NAME#"S") tr1.op:$V1, tr2.op:$V2,
4166 multiclass TernaryOptVRRbSPairGeneric<string mnemonic, bits<16> opcode> {
4167 def "" : InstVRRb<opcode, (outs VR128:$V1),
4168 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5),
4169 mnemonic#"\t$V1, $V2, $V3, $M4, $M5", []>;
4170 def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $M4",
4171 (!cast<Instruction>(NAME) VR128:$V1, VR128:$V2, VR128:$V3,
4175 class TernaryVRRc<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4176 TypedReg tr1, TypedReg tr2>
4177 : InstVRRc<opcode, (outs tr1.op:$V1),
4178 (ins tr2.op:$V2, tr2.op:$V3, imm32zx4:$M4),
4179 mnemonic#"\t$V1, $V2, $V3, $M4",
4180 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
4181 (tr2.vt tr2.op:$V3),
4187 class TernaryVRRcFloat<string mnemonic, bits<16> opcode,
4188 SDPatternOperator operator, TypedReg tr1, TypedReg tr2,
4189 bits<4> type = 0, bits<4> m5 = 0>
4190 : InstVRRc<opcode, (outs tr1.op:$V1),
4191 (ins tr2.op:$V2, tr2.op:$V3, imm32zx4:$M6),
4192 mnemonic#"\t$V1, $V2, $V3, $M6",
4193 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
4194 (tr2.vt tr2.op:$V3),
4200 class TernaryVRRcFloatGeneric<string mnemonic, bits<16> opcode>
4201 : InstVRRc<opcode, (outs VR128:$V1),
4202 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5,
4204 mnemonic#"\t$V1, $V2, $V3, $M4, $M5, $M6", []>;
4206 class TernaryVRRd<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4207 TypedReg tr1, TypedReg tr2, bits<4> type = 0>
4208 : InstVRRd<opcode, (outs tr1.op:$V1),
4209 (ins tr2.op:$V2, tr2.op:$V3, tr1.op:$V4),
4210 mnemonic#"\t$V1, $V2, $V3, $V4",
4211 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
4212 (tr2.vt tr2.op:$V3),
4213 (tr1.vt tr1.op:$V4))))]> {
4218 class TernaryVRRdGeneric<string mnemonic, bits<16> opcode>
4219 : InstVRRd<opcode, (outs VR128:$V1),
4220 (ins VR128:$V2, VR128:$V3, VR128:$V4, imm32zx4:$M5),
4221 mnemonic#"\t$V1, $V2, $V3, $V4, $M5", []> {
4225 class TernaryVRRe<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4226 TypedReg tr1, TypedReg tr2, bits<4> m5 = 0, bits<4> type = 0>
4227 : InstVRRe<opcode, (outs tr1.op:$V1),
4228 (ins tr2.op:$V2, tr2.op:$V3, tr1.op:$V4),
4229 mnemonic#"\t$V1, $V2, $V3, $V4",
4230 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
4231 (tr2.vt tr2.op:$V3),
4232 (tr1.vt tr1.op:$V4))))]> {
4237 class TernaryVRReFloatGeneric<string mnemonic, bits<16> opcode>
4238 : InstVRRe<opcode, (outs VR128:$V1),
4239 (ins VR128:$V2, VR128:$V3, VR128:$V4, imm32zx4:$M5, imm32zx4:$M6),
4240 mnemonic#"\t$V1, $V2, $V3, $V4, $M5, $M6", []>;
4242 class TernaryVRSb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4243 TypedReg tr1, TypedReg tr2, RegisterOperand cls, bits<4> type>
4244 : InstVRSb<opcode, (outs tr1.op:$V1),
4245 (ins tr2.op:$V1src, cls:$R3, shift12only:$BD2),
4246 mnemonic#"\t$V1, $R3, $BD2",
4247 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V1src),
4249 shift12only:$BD2)))]> {
4250 let Constraints = "$V1 = $V1src";
4251 let DisableEncoding = "$V1src";
4255 class TernaryVRSbGeneric<string mnemonic, bits<16> opcode>
4256 : InstVRSb<opcode, (outs VR128:$V1),
4257 (ins VR128:$V1src, GR64:$R3, shift12only:$BD2, imm32zx4:$M4),
4258 mnemonic#"\t$V1, $R3, $BD2, $M4", []> {
4259 let Constraints = "$V1 = $V1src";
4260 let DisableEncoding = "$V1src";
4263 class TernaryVRV<string mnemonic, bits<16> opcode, bits<5> bytes,
4265 : InstVRV<opcode, (outs VR128:$V1),
4266 (ins VR128:$V1src, bdvaddr12only:$VBD2, index:$M3),
4267 mnemonic#"\t$V1, $VBD2, $M3", []> {
4268 let Constraints = "$V1 = $V1src";
4269 let DisableEncoding = "$V1src";
4271 let AccessBytes = bytes;
4274 class TernaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4275 TypedReg tr1, TypedReg tr2, bits<5> bytes, Immediate index>
4276 : InstVRX<opcode, (outs tr1.op:$V1),
4277 (ins tr2.op:$V1src, bdxaddr12only:$XBD2, index:$M3),
4278 mnemonic#"\t$V1, $XBD2, $M3",
4279 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V1src),
4280 bdxaddr12only:$XBD2,
4282 let Constraints = "$V1 = $V1src";
4283 let DisableEncoding = "$V1src";
4285 let AccessBytes = bytes;
4288 class QuaternaryVRId<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4289 TypedReg tr1, TypedReg tr2, bits<4> type>
4290 : InstVRId<opcode, (outs tr1.op:$V1),
4291 (ins tr2.op:$V1src, tr2.op:$V2, tr2.op:$V3, imm32zx8:$I4),
4292 mnemonic#"\t$V1, $V2, $V3, $I4",
4293 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V1src),
4294 (tr2.vt tr2.op:$V2),
4295 (tr2.vt tr2.op:$V3),
4297 let Constraints = "$V1 = $V1src";
4298 let DisableEncoding = "$V1src";
4302 class QuaternaryVRIdGeneric<string mnemonic, bits<16> opcode>
4303 : InstVRId<opcode, (outs VR128:$V1),
4304 (ins VR128:$V1src, VR128:$V2, VR128:$V3,
4305 imm32zx8:$I4, imm32zx4:$M5),
4306 mnemonic#"\t$V1, $V2, $V3, $I4, $M5", []> {
4307 let Constraints = "$V1 = $V1src";
4308 let DisableEncoding = "$V1src";
4311 class QuaternaryVRIf<string mnemonic, bits<16> opcode>
4312 : InstVRIf<opcode, (outs VR128:$V1),
4313 (ins VR128:$V2, VR128:$V3,
4314 imm32zx8:$I4, imm32zx4:$M5),
4315 mnemonic#"\t$V1, $V2, $V3, $I4, $M5", []>;
4317 class QuaternaryVRIg<string mnemonic, bits<16> opcode>
4318 : InstVRIg<opcode, (outs VR128:$V1),
4319 (ins VR128:$V2, imm32zx8:$I3,
4320 imm32zx8:$I4, imm32zx4:$M5),
4321 mnemonic#"\t$V1, $V2, $I3, $I4, $M5", []>;
4323 class QuaternaryVRRd<string mnemonic, bits<16> opcode,
4324 SDPatternOperator operator, TypedReg tr1, TypedReg tr2,
4325 TypedReg tr3, TypedReg tr4, bits<4> type,
4326 SDPatternOperator m6mask = imm32zx4, bits<4> m6or = 0>
4327 : InstVRRd<opcode, (outs tr1.op:$V1),
4328 (ins tr2.op:$V2, tr3.op:$V3, tr4.op:$V4, m6mask:$M6),
4329 mnemonic#"\t$V1, $V2, $V3, $V4, $M6",
4330 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
4331 (tr3.vt tr3.op:$V3),
4332 (tr4.vt tr4.op:$V4),
4338 class QuaternaryVRRdGeneric<string mnemonic, bits<16> opcode>
4339 : InstVRRd<opcode, (outs VR128:$V1),
4340 (ins VR128:$V2, VR128:$V3, VR128:$V4, imm32zx4:$M5, imm32zx4:$M6),
4341 mnemonic#"\t$V1, $V2, $V3, $V4, $M5, $M6", []>;
4343 // Declare a pair of instructions, one which sets CC and one which doesn't.
4344 // The CC-setting form ends with "S" and sets the low bit of M6.
4345 // Also create aliases to make use of M6 operand optional in assembler.
4346 multiclass QuaternaryOptVRRdSPair<string mnemonic, bits<16> opcode,
4347 SDPatternOperator operator,
4348 SDPatternOperator operator_cc,
4349 TypedReg tr1, TypedReg tr2, bits<4> type,
4350 bits<4> modifier = 0> {
4351 def "" : QuaternaryVRRd<mnemonic, opcode, operator,
4352 tr1, tr2, tr2, tr2, type,
4353 imm32zx4even, !and (modifier, 14)>;
4354 def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $V4",
4355 (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2,
4356 tr2.op:$V3, tr2.op:$V4, 0)>;
4358 def S : QuaternaryVRRd<mnemonic##"s", opcode, operator_cc,
4359 tr1, tr2, tr2, tr2, type,
4360 imm32zx4even, !add (!and (modifier, 14), 1)>;
4361 def : InstAlias<mnemonic#"s\t$V1, $V2, $V3, $V4",
4362 (!cast<Instruction>(NAME#"S") tr1.op:$V1, tr2.op:$V2,
4363 tr2.op:$V3, tr2.op:$V4, 0)>;
4366 multiclass QuaternaryOptVRRdSPairGeneric<string mnemonic, bits<16> opcode> {
4367 def "" : QuaternaryVRRdGeneric<mnemonic, opcode>;
4368 def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $V4, $M5",
4369 (!cast<Instruction>(NAME) VR128:$V1, VR128:$V2, VR128:$V3,
4370 VR128:$V4, imm32zx4:$M5, 0)>;
4373 class SideEffectQuaternaryRRFa<string mnemonic, bits<16> opcode,
4374 RegisterOperand cls1, RegisterOperand cls2,
4375 RegisterOperand cls3>
4376 : InstRRFa<opcode, (outs), (ins cls1:$R1, cls2:$R2, cls3:$R3, imm32zx4:$M4),
4377 mnemonic#"\t$R1, $R2, $R3, $M4", []>;
4379 multiclass SideEffectQuaternaryRRFaOptOpt<string mnemonic, bits<16> opcode,
4380 RegisterOperand cls1,
4381 RegisterOperand cls2,
4382 RegisterOperand cls3> {
4383 def "" : SideEffectQuaternaryRRFa<mnemonic, opcode, cls1, cls2, cls3>;
4384 def Opt : SideEffectTernaryRRFa<mnemonic, opcode, cls1, cls2, cls3>;
4385 def OptOpt : SideEffectBinaryRRFa<mnemonic, opcode, cls1, cls2>;
4388 class SideEffectQuaternaryRRFb<string mnemonic, bits<16> opcode,
4389 RegisterOperand cls1, RegisterOperand cls2,
4390 RegisterOperand cls3>
4391 : InstRRFb<opcode, (outs), (ins cls1:$R1, cls2:$R2, cls3:$R3, imm32zx4:$M4),
4392 mnemonic#"\t$R1, $R3, $R2, $M4", []>;
4394 multiclass SideEffectQuaternaryRRFbOpt<string mnemonic, bits<16> opcode,
4395 RegisterOperand cls1,
4396 RegisterOperand cls2,
4397 RegisterOperand cls3> {
4398 def "" : SideEffectQuaternaryRRFb<mnemonic, opcode, cls1, cls2, cls3>;
4399 def Opt : SideEffectTernaryRRFb<mnemonic, opcode, cls1, cls2, cls3>;
4402 class SideEffectQuaternarySSe<string mnemonic, bits<8> opcode,
4403 RegisterOperand cls>
4404 : InstSSe<opcode, (outs),
4405 (ins cls:$R1, bdaddr12only:$BD2, cls:$R3, bdaddr12only:$BD4),
4406 mnemonic#"\t$R1, $BD2, $R3, $BD4", []>;
4408 class LoadAndOpRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4409 RegisterOperand cls, AddressingMode mode = bdaddr20only>
4410 : InstRSYa<opcode, (outs cls:$R1), (ins cls:$R3, mode:$BD2),
4411 mnemonic#"\t$R1, $R3, $BD2",
4412 [(set cls:$R1, (operator mode:$BD2, cls:$R3))]> {
4417 class CmpSwapRRE<string mnemonic, bits<16> opcode,
4418 RegisterOperand cls1, RegisterOperand cls2>
4419 : InstRRE<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
4420 mnemonic#"\t$R1, $R2", []> {
4421 let Constraints = "$R1 = $R1src";
4422 let DisableEncoding = "$R1src";
4427 class CmpSwapRS<string mnemonic, bits<8> opcode, SDPatternOperator operator,
4428 RegisterOperand cls, AddressingMode mode = bdaddr12only>
4429 : InstRSa<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, mode:$BD2),
4430 mnemonic#"\t$R1, $R3, $BD2",
4431 [(set cls:$R1, (operator mode:$BD2, cls:$R1src, cls:$R3))]> {
4432 let Constraints = "$R1 = $R1src";
4433 let DisableEncoding = "$R1src";
4438 class CmpSwapRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4439 RegisterOperand cls, AddressingMode mode = bdaddr20only>
4440 : InstRSYa<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, mode:$BD2),
4441 mnemonic#"\t$R1, $R3, $BD2",
4442 [(set cls:$R1, (operator mode:$BD2, cls:$R1src, cls:$R3))]> {
4443 let Constraints = "$R1 = $R1src";
4444 let DisableEncoding = "$R1src";
4449 multiclass CmpSwapRSPair<string mnemonic, bits<8> rsOpcode, bits<16> rsyOpcode,
4450 SDPatternOperator operator, RegisterOperand cls> {
4451 let DispKey = mnemonic ## #cls in {
4452 let DispSize = "12" in
4453 def "" : CmpSwapRS<mnemonic, rsOpcode, operator, cls, bdaddr12pair>;
4454 let DispSize = "20" in
4455 def Y : CmpSwapRSY<mnemonic#"y", rsyOpcode, operator, cls, bdaddr20pair>;
4459 class RotateSelectRIEf<string mnemonic, bits<16> opcode, RegisterOperand cls1,
4460 RegisterOperand cls2>
4461 : InstRIEf<opcode, (outs cls1:$R1),
4462 (ins cls1:$R1src, cls2:$R2, imm32zx8:$I3, imm32zx8:$I4,
4464 mnemonic#"\t$R1, $R2, $I3, $I4, $I5", []> {
4465 let Constraints = "$R1 = $R1src";
4466 let DisableEncoding = "$R1src";
4469 class PrefetchRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator>
4470 : InstRXYb<opcode, (outs), (ins imm32zx4:$M1, bdxaddr20only:$XBD2),
4471 mnemonic##"\t$M1, $XBD2",
4472 [(operator imm32zx4:$M1, bdxaddr20only:$XBD2)]>;
4474 class PrefetchRILPC<string mnemonic, bits<12> opcode,
4475 SDPatternOperator operator>
4476 : InstRILc<opcode, (outs), (ins imm32zx4:$M1, pcrel32:$RI2),
4477 mnemonic##"\t$M1, $RI2",
4478 [(operator imm32zx4:$M1, pcrel32:$RI2)]> {
4479 // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
4480 // However, BDXs have two extra operands and are therefore 6 units more
4482 let AddedComplexity = 7;
4485 class BranchPreloadSMI<string mnemonic, bits<8> opcode>
4486 : InstSMI<opcode, (outs),
4487 (ins imm32zx4:$M1, brtarget16bpp:$RI2, bdxaddr12only:$BD3),
4488 mnemonic#"\t$M1, $RI2, $BD3", []>;
4490 class BranchPreloadMII<string mnemonic, bits<8> opcode>
4491 : InstMII<opcode, (outs),
4492 (ins imm32zx4:$M1, brtarget12bpp:$RI2, brtarget24bpp:$RI3),
4493 mnemonic#"\t$M1, $RI2, $RI3", []>;
4495 // A floating-point load-and test operation. Create both a normal unary
4496 // operation and one that acts as a comparison against zero.
4497 // Note that the comparison against zero operation is not available if we
4498 // have vector support, since load-and-test instructions will partially
4499 // clobber the target (vector) register.
4500 multiclass LoadAndTestRRE<string mnemonic, bits<16> opcode,
4501 RegisterOperand cls> {
4502 def "" : UnaryRRE<mnemonic, opcode, null_frag, cls, cls>;
4503 let isCodeGenOnly = 1, Predicates = [FeatureNoVector] in
4504 def Compare : CompareRRE<mnemonic, opcode, null_frag, cls, cls>;
4507 //===----------------------------------------------------------------------===//
4508 // Pseudo instructions
4509 //===----------------------------------------------------------------------===//
4511 // Convenience instructions that get lowered to real instructions
4512 // by either SystemZTargetLowering::EmitInstrWithCustomInserter()
4513 // or SystemZInstrInfo::expandPostRAPseudo().
4515 //===----------------------------------------------------------------------===//
4517 class Pseudo<dag outs, dag ins, list<dag> pattern>
4518 : InstSystemZ<0, outs, ins, "", pattern> {
4520 let isCodeGenOnly = 1;
4523 // Like SideEffectBinarySIL, but expanded later.
4524 class SideEffectBinarySILPseudo<SDPatternOperator operator, Immediate imm>
4525 : Pseudo<(outs), (ins bdaddr12only:$BD1, imm:$I2),
4526 [(operator bdaddr12only:$BD1, imm:$I2)]>;
4528 // Like UnaryRI, but expanded after RA depending on the choice of register.
4529 class UnaryRIPseudo<SDPatternOperator operator, RegisterOperand cls,
4531 : Pseudo<(outs cls:$R1), (ins imm:$I2),
4532 [(set cls:$R1, (operator imm:$I2))]>;
4534 // Like UnaryRXY, but expanded after RA depending on the choice of register.
4535 class UnaryRXYPseudo<string key, SDPatternOperator operator,
4536 RegisterOperand cls, bits<5> bytes,
4537 AddressingMode mode = bdxaddr20only>
4538 : Pseudo<(outs cls:$R1), (ins mode:$XBD2),
4539 [(set cls:$R1, (operator mode:$XBD2))]> {
4540 let OpKey = key#"r"#cls;
4543 let Has20BitOffset = 1;
4545 let AccessBytes = bytes;
4548 // Like UnaryRR, but expanded after RA depending on the choice of registers.
4549 class UnaryRRPseudo<string key, SDPatternOperator operator,
4550 RegisterOperand cls1, RegisterOperand cls2>
4551 : Pseudo<(outs cls1:$R1), (ins cls2:$R2),
4552 [(set cls1:$R1, (operator cls2:$R2))]> {
4553 let OpKey = key#cls1;
4557 // Like BinaryRI, but expanded after RA depending on the choice of register.
4558 class BinaryRIPseudo<SDPatternOperator operator, RegisterOperand cls,
4560 : Pseudo<(outs cls:$R1), (ins cls:$R1src, imm:$I2),
4561 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
4562 let Constraints = "$R1 = $R1src";
4565 // Like BinaryRIE, but expanded after RA depending on the choice of register.
4566 class BinaryRIEPseudo<SDPatternOperator operator, RegisterOperand cls,
4568 : Pseudo<(outs cls:$R1), (ins cls:$R3, imm:$I2),
4569 [(set cls:$R1, (operator cls:$R3, imm:$I2))]>;
4571 // Like BinaryRIAndK, but expanded after RA depending on the choice of register.
4572 multiclass BinaryRIAndKPseudo<string key, SDPatternOperator operator,
4573 RegisterOperand cls, Immediate imm> {
4574 let NumOpsKey = key in {
4575 let NumOpsValue = "3" in
4576 def K : BinaryRIEPseudo<null_frag, cls, imm>,
4577 Requires<[FeatureHighWord, FeatureDistinctOps]>;
4578 let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in
4579 def "" : BinaryRIPseudo<operator, cls, imm>,
4580 Requires<[FeatureHighWord]>;
4584 // Like CompareRI, but expanded after RA depending on the choice of register.
4585 class CompareRIPseudo<SDPatternOperator operator, RegisterOperand cls,
4587 : Pseudo<(outs), (ins cls:$R1, imm:$I2), [(operator cls:$R1, imm:$I2)]> {
4591 // Like CompareRXY, but expanded after RA depending on the choice of register.
4592 class CompareRXYPseudo<SDPatternOperator operator, RegisterOperand cls,
4593 SDPatternOperator load, bits<5> bytes,
4594 AddressingMode mode = bdxaddr20only>
4595 : Pseudo<(outs), (ins cls:$R1, mode:$XBD2),
4596 [(operator cls:$R1, (load mode:$XBD2))]> {
4598 let Has20BitOffset = 1;
4600 let AccessBytes = bytes;
4603 // Like CondBinaryRRF, but expanded after RA depending on the choice of
4605 class CondBinaryRRFPseudo<RegisterOperand cls1, RegisterOperand cls2>
4606 : Pseudo<(outs cls1:$R1),
4607 (ins cls1:$R1src, cls2:$R2, cond4:$valid, cond4:$M3), []> {
4608 let Constraints = "$R1 = $R1src";
4609 let DisableEncoding = "$R1src";
4613 // Like CondBinaryRIE, but expanded after RA depending on the choice of
4615 class CondBinaryRIEPseudo<RegisterOperand cls, Immediate imm>
4616 : Pseudo<(outs cls:$R1),
4617 (ins cls:$R1src, imm:$I2, cond4:$valid, cond4:$M3),
4618 [(set cls:$R1, (z_select_ccmask imm:$I2, cls:$R1src,
4619 cond4:$valid, cond4:$M3))]> {
4620 let Constraints = "$R1 = $R1src";
4621 let DisableEncoding = "$R1src";
4625 // Like CondUnaryRSY, but expanded after RA depending on the choice of
4627 class CondUnaryRSYPseudo<SDPatternOperator operator, RegisterOperand cls,
4628 bits<5> bytes, AddressingMode mode = bdaddr20only>
4629 : Pseudo<(outs cls:$R1),
4630 (ins cls:$R1src, mode:$BD2, cond4:$valid, cond4:$R3),
4632 (z_select_ccmask (operator mode:$BD2), cls:$R1src,
4633 cond4:$valid, cond4:$R3))]> {
4634 let Constraints = "$R1 = $R1src";
4635 let DisableEncoding = "$R1src";
4637 let AccessBytes = bytes;
4641 // Like CondStoreRSY, but expanded after RA depending on the choice of
4643 class CondStoreRSYPseudo<RegisterOperand cls, bits<5> bytes,
4644 AddressingMode mode = bdaddr20only>
4645 : Pseudo<(outs), (ins cls:$R1, mode:$BD2, cond4:$valid, cond4:$R3), []> {
4647 let AccessBytes = bytes;
4651 // Like StoreRXY, but expanded after RA depending on the choice of register.
4652 class StoreRXYPseudo<SDPatternOperator operator, RegisterOperand cls,
4653 bits<5> bytes, AddressingMode mode = bdxaddr20only>
4654 : Pseudo<(outs), (ins cls:$R1, mode:$XBD2),
4655 [(operator cls:$R1, mode:$XBD2)]> {
4657 let Has20BitOffset = 1;
4659 let AccessBytes = bytes;
4662 // Like RotateSelectRIEf, but expanded after RA depending on the choice
4664 class RotateSelectRIEfPseudo<RegisterOperand cls1, RegisterOperand cls2>
4665 : Pseudo<(outs cls1:$R1),
4666 (ins cls1:$R1src, cls2:$R2, imm32zx8:$I3, imm32zx8:$I4,
4669 let Constraints = "$R1 = $R1src";
4670 let DisableEncoding = "$R1src";
4673 // Implements "$dst = $cc & (8 >> CC) ? $src1 : $src2", where CC is
4674 // the value of the PSW's 2-bit condition code field.
4675 class SelectWrapper<ValueType vt, RegisterOperand cls>
4676 : Pseudo<(outs cls:$dst),
4677 (ins cls:$src1, cls:$src2, imm32zx4:$valid, imm32zx4:$cc),
4678 [(set (vt cls:$dst), (z_select_ccmask cls:$src1, cls:$src2,
4679 imm32zx4:$valid, imm32zx4:$cc))]> {
4680 let usesCustomInserter = 1;
4681 // Although the instructions used by these nodes do not in themselves
4682 // change CC, the insertion requires new blocks, and CC cannot be live
4688 // Stores $new to $addr if $cc is true ("" case) or false (Inv case).
4689 multiclass CondStores<RegisterOperand cls, SDPatternOperator store,
4690 SDPatternOperator load, AddressingMode mode> {
4691 let Defs = [CC], Uses = [CC], usesCustomInserter = 1 in {
4692 def "" : Pseudo<(outs),
4693 (ins cls:$new, mode:$addr, imm32zx4:$valid, imm32zx4:$cc),
4694 [(store (z_select_ccmask cls:$new, (load mode:$addr),
4695 imm32zx4:$valid, imm32zx4:$cc),
4697 def Inv : Pseudo<(outs),
4698 (ins cls:$new, mode:$addr, imm32zx4:$valid, imm32zx4:$cc),
4699 [(store (z_select_ccmask (load mode:$addr), cls:$new,
4700 imm32zx4:$valid, imm32zx4:$cc),
4705 // OPERATOR is ATOMIC_SWAP or an ATOMIC_LOAD_* operation. PAT and OPERAND
4706 // describe the second (non-memory) operand.
4707 class AtomicLoadBinary<SDPatternOperator operator, RegisterOperand cls,
4708 dag pat, DAGOperand operand>
4709 : Pseudo<(outs cls:$dst), (ins bdaddr20only:$ptr, operand:$src2),
4710 [(set cls:$dst, (operator bdaddr20only:$ptr, pat))]> {
4712 let Has20BitOffset = 1;
4715 let usesCustomInserter = 1;
4716 let hasNoSchedulingInfo = 1;
4719 // Specializations of AtomicLoadWBinary.
4720 class AtomicLoadBinaryReg32<SDPatternOperator operator>
4721 : AtomicLoadBinary<operator, GR32, (i32 GR32:$src2), GR32>;
4722 class AtomicLoadBinaryImm32<SDPatternOperator operator, Immediate imm>
4723 : AtomicLoadBinary<operator, GR32, (i32 imm:$src2), imm>;
4724 class AtomicLoadBinaryReg64<SDPatternOperator operator>
4725 : AtomicLoadBinary<operator, GR64, (i64 GR64:$src2), GR64>;
4726 class AtomicLoadBinaryImm64<SDPatternOperator operator, Immediate imm>
4727 : AtomicLoadBinary<operator, GR64, (i64 imm:$src2), imm>;
4729 // OPERATOR is ATOMIC_SWAPW or an ATOMIC_LOADW_* operation. PAT and OPERAND
4730 // describe the second (non-memory) operand.
4731 class AtomicLoadWBinary<SDPatternOperator operator, dag pat,
4733 : Pseudo<(outs GR32:$dst),
4734 (ins bdaddr20only:$ptr, operand:$src2, ADDR32:$bitshift,
4735 ADDR32:$negbitshift, uimm32:$bitsize),
4736 [(set GR32:$dst, (operator bdaddr20only:$ptr, pat, ADDR32:$bitshift,
4737 ADDR32:$negbitshift, uimm32:$bitsize))]> {
4739 let Has20BitOffset = 1;
4742 let usesCustomInserter = 1;
4743 let hasNoSchedulingInfo = 1;
4746 // Specializations of AtomicLoadWBinary.
4747 class AtomicLoadWBinaryReg<SDPatternOperator operator>
4748 : AtomicLoadWBinary<operator, (i32 GR32:$src2), GR32>;
4749 class AtomicLoadWBinaryImm<SDPatternOperator operator, Immediate imm>
4750 : AtomicLoadWBinary<operator, (i32 imm:$src2), imm>;
4752 // Define an instruction that operates on two fixed-length blocks of memory,
4753 // and associated pseudo instructions for operating on blocks of any size.
4754 // The Sequence form uses a straight-line sequence of instructions and
4755 // the Loop form uses a loop of length-256 instructions followed by
4756 // another instruction to handle the excess.
4757 multiclass MemorySS<string mnemonic, bits<8> opcode,
4758 SDPatternOperator sequence, SDPatternOperator loop> {
4759 def "" : SideEffectBinarySSa<mnemonic, opcode>;
4760 let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in {
4761 def Sequence : Pseudo<(outs), (ins bdaddr12only:$dest, bdaddr12only:$src,
4763 [(sequence bdaddr12only:$dest, bdaddr12only:$src,
4765 def Loop : Pseudo<(outs), (ins bdaddr12only:$dest, bdaddr12only:$src,
4766 imm64:$length, GR64:$count256),
4767 [(loop bdaddr12only:$dest, bdaddr12only:$src,
4768 imm64:$length, GR64:$count256)]>;
4772 // Define an instruction that operates on two strings, both terminated
4773 // by the character in R0. The instruction processes a CPU-determinated
4774 // number of bytes at a time and sets CC to 3 if the instruction needs
4775 // to be repeated. Also define a pseudo instruction that represents
4776 // the full loop (the main instruction plus the branch on CC==3).
4777 multiclass StringRRE<string mnemonic, bits<16> opcode,
4778 SDPatternOperator operator> {
4780 def "" : SideEffectBinaryMemMemRRE<mnemonic, opcode, GR64, GR64>;
4781 let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in
4782 def Loop : Pseudo<(outs GR64:$end),
4783 (ins GR64:$start1, GR64:$start2, GR32:$char),
4784 [(set GR64:$end, (operator GR64:$start1, GR64:$start2,
4788 // A pseudo instruction that is a direct alias of a real instruction.
4789 // These aliases are used in cases where a particular register operand is
4790 // fixed or where the same instruction is used with different register sizes.
4791 // The size parameter is the size in bytes of the associated real instruction.
4792 class Alias<int size, dag outs, dag ins, list<dag> pattern>
4793 : InstSystemZ<size, outs, ins, "", pattern> {
4795 let isCodeGenOnly = 1;
4798 class UnaryAliasVRS<RegisterOperand cls1, RegisterOperand cls2>
4799 : Alias<6, (outs cls1:$src1), (ins cls2:$src2), []>;
4801 // An alias of a UnaryVRR*, but with different register sizes.
4802 class UnaryAliasVRR<SDPatternOperator operator, TypedReg tr1, TypedReg tr2>
4803 : Alias<6, (outs tr1.op:$V1), (ins tr2.op:$V2),
4804 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2))))]>;
4806 // An alias of a UnaryVRX, but with different register sizes.
4807 class UnaryAliasVRX<SDPatternOperator operator, TypedReg tr,
4808 AddressingMode mode = bdxaddr12only>
4809 : Alias<6, (outs tr.op:$V1), (ins mode:$XBD2),
4810 [(set tr.op:$V1, (tr.vt (operator mode:$XBD2)))]>;
4812 // An alias of a StoreVRX, but with different register sizes.
4813 class StoreAliasVRX<SDPatternOperator operator, TypedReg tr,
4814 AddressingMode mode = bdxaddr12only>
4815 : Alias<6, (outs), (ins tr.op:$V1, mode:$XBD2),
4816 [(operator (tr.vt tr.op:$V1), mode:$XBD2)]>;
4818 // An alias of a BinaryRI, but with different register sizes.
4819 class BinaryAliasRI<SDPatternOperator operator, RegisterOperand cls,
4821 : Alias<4, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
4822 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
4823 let Constraints = "$R1 = $R1src";
4826 // An alias of a BinaryRIL, but with different register sizes.
4827 class BinaryAliasRIL<SDPatternOperator operator, RegisterOperand cls,
4829 : Alias<6, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
4830 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
4831 let Constraints = "$R1 = $R1src";
4834 // An alias of a BinaryVRRf, but with different register sizes.
4835 class BinaryAliasVRRf<RegisterOperand cls>
4836 : Alias<6, (outs VR128:$V1), (ins cls:$R2, cls:$R3), []>;
4838 // An alias of a CompareRI, but with different register sizes.
4839 class CompareAliasRI<SDPatternOperator operator, RegisterOperand cls,
4841 : Alias<4, (outs), (ins cls:$R1, imm:$I2), [(operator cls:$R1, imm:$I2)]> {
4845 // An alias of a RotateSelectRIEf, but with different register sizes.
4846 class RotateSelectAliasRIEf<RegisterOperand cls1, RegisterOperand cls2>
4847 : Alias<6, (outs cls1:$R1),
4848 (ins cls1:$R1src, cls2:$R2, imm32zx8:$I3, imm32zx8:$I4,
4849 imm32zx6:$I5), []> {
4850 let Constraints = "$R1 = $R1src";