1 //==- SystemZInstrFormats.td - SystemZ Instruction Formats --*- tablegen -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Basic SystemZ instruction definition
12 //===----------------------------------------------------------------------===//
14 class InstSystemZ<int size, dag outs, dag ins, string asmstr,
15 list<dag> pattern> : Instruction {
16 let Namespace = "SystemZ";
18 dag OutOperandList = outs;
19 dag InOperandList = ins;
21 let Pattern = pattern;
22 let AsmString = asmstr;
24 // Some instructions come in pairs, one having a 12-bit displacement
25 // and the other having a 20-bit displacement. Both instructions in
26 // the pair have the same DispKey and their DispSizes are "12" and "20"
29 string DispSize = "none";
31 // Many register-based <INSN>R instructions have a memory-based <INSN>
32 // counterpart. OpKey uniquely identifies <INSN>, while OpType is
33 // "reg" for <INSN>R and "mem" for <INSN>.
35 string OpType = "none";
37 // Many distinct-operands instructions have older 2-operand equivalents.
38 // NumOpsKey uniquely identifies one of these 2-operand and 3-operand pairs,
39 // with NumOpsValue being "2" or "3" as appropriate.
40 string NumOpsKey = "";
41 string NumOpsValue = "none";
43 // True if this instruction is a simple D(X,B) load of a register
44 // (with no sign or zero extension).
45 bit SimpleBDXLoad = 0;
47 // True if this instruction is a simple D(X,B) store of a register
48 // (with no truncation).
49 bit SimpleBDXStore = 0;
51 // True if this instruction has a 20-bit displacement field.
52 bit Has20BitOffset = 0;
54 // True if addresses in this instruction have an index register.
57 // True if this is a 128-bit pseudo instruction that combines two 64-bit
61 // The access size of all memory operands in bytes, or 0 if not known.
62 bits<5> AccessBytes = 0;
64 // If the instruction sets CC to a useful value, this gives the mask
65 // of all possible CC results. The mask has the same form as
69 // The subset of CCValues that have the same meaning as they would after
70 // a comparison of the first operand against zero.
71 bits<4> CompareZeroCCMask = 0;
73 // True if the instruction is conditional and if the CC mask operand
74 // comes first (as for BRC, etc.).
77 // Similar, but true if the CC mask operand comes last (as for LOC, etc.).
80 // True if the instruction is the "logical" rather than "arithmetic" form,
81 // in cases where a distinction exists.
84 let TSFlags{0} = SimpleBDXLoad;
85 let TSFlags{1} = SimpleBDXStore;
86 let TSFlags{2} = Has20BitOffset;
87 let TSFlags{3} = HasIndex;
88 let TSFlags{4} = Is128Bit;
89 let TSFlags{9-5} = AccessBytes;
90 let TSFlags{13-10} = CCValues;
91 let TSFlags{17-14} = CompareZeroCCMask;
92 let TSFlags{18} = CCMaskFirst;
93 let TSFlags{19} = CCMaskLast;
94 let TSFlags{20} = IsLogical;
97 //===----------------------------------------------------------------------===//
98 // Mappings between instructions
99 //===----------------------------------------------------------------------===//
101 // Return the version of an instruction that has an unsigned 12-bit
103 def getDisp12Opcode : InstrMapping {
104 let FilterClass = "InstSystemZ";
105 let RowFields = ["DispKey"];
106 let ColFields = ["DispSize"];
108 let ValueCols = [["12"]];
111 // Return the version of an instruction that has a signed 20-bit displacement.
112 def getDisp20Opcode : InstrMapping {
113 let FilterClass = "InstSystemZ";
114 let RowFields = ["DispKey"];
115 let ColFields = ["DispSize"];
117 let ValueCols = [["20"]];
120 // Return the memory form of a register instruction.
121 def getMemOpcode : InstrMapping {
122 let FilterClass = "InstSystemZ";
123 let RowFields = ["OpKey"];
124 let ColFields = ["OpType"];
125 let KeyCol = ["reg"];
126 let ValueCols = [["mem"]];
129 // Return the 3-operand form of a 2-operand instruction.
130 def getThreeOperandOpcode : InstrMapping {
131 let FilterClass = "InstSystemZ";
132 let RowFields = ["NumOpsKey"];
133 let ColFields = ["NumOpsValue"];
135 let ValueCols = [["3"]];
138 //===----------------------------------------------------------------------===//
139 // Instruction formats
140 //===----------------------------------------------------------------------===//
142 // Formats are specified using operand field declarations of the form:
144 // bits<4> Rn : register input or output for operand n
145 // bits<5> Vn : vector register input or output for operand n
146 // bits<m> In : immediate value of width m for operand n
147 // bits<4> BDn : address operand n, which has a base and a displacement
148 // bits<m> XBDn : address operand n, which has an index, a base and a
150 // bits<m> VBDn : address operand n, which has a vector index, a base and a
152 // bits<4> Xn : index register for address operand n
153 // bits<4> Mn : mode value for operand n
155 // The operand numbers ("n" in the list above) follow the architecture manual.
156 // Assembly operands sometimes have a different order; in particular, R3 often
157 // is often written between operands 1 and 2.
159 //===----------------------------------------------------------------------===//
161 class InstI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
162 : InstSystemZ<2, outs, ins, asmstr, pattern> {
164 field bits<16> SoftFail = 0;
172 class InstRI<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
173 : InstSystemZ<4, outs, ins, asmstr, pattern> {
175 field bits<32> SoftFail = 0;
180 let Inst{31-24} = op{11-4};
181 let Inst{23-20} = R1;
182 let Inst{19-16} = op{3-0};
186 class InstRIEa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
187 : InstSystemZ<6, outs, ins, asmstr, pattern> {
189 field bits<48> SoftFail = 0;
195 let Inst{47-40} = op{15-8};
196 let Inst{39-36} = R1;
198 let Inst{31-16} = I2;
199 let Inst{15-12} = M3;
201 let Inst{7-0} = op{7-0};
204 class InstRIEb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
205 : InstSystemZ<6, outs, ins, asmstr, pattern> {
207 field bits<48> SoftFail = 0;
214 let Inst{47-40} = op{15-8};
215 let Inst{39-36} = R1;
216 let Inst{35-32} = R2;
217 let Inst{31-16} = RI4;
218 let Inst{15-12} = M3;
220 let Inst{7-0} = op{7-0};
223 class InstRIEc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
224 : InstSystemZ<6, outs, ins, asmstr, pattern> {
226 field bits<48> SoftFail = 0;
233 let Inst{47-40} = op{15-8};
234 let Inst{39-36} = R1;
235 let Inst{35-32} = M3;
236 let Inst{31-16} = RI4;
238 let Inst{7-0} = op{7-0};
241 class InstRIEd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
242 : InstSystemZ<6, outs, ins, asmstr, pattern> {
244 field bits<48> SoftFail = 0;
250 let Inst{47-40} = op{15-8};
251 let Inst{39-36} = R1;
252 let Inst{35-32} = R3;
253 let Inst{31-16} = I2;
255 let Inst{7-0} = op{7-0};
258 class InstRIEf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
259 : InstSystemZ<6, outs, ins, asmstr, pattern> {
261 field bits<48> SoftFail = 0;
269 let Inst{47-40} = op{15-8};
270 let Inst{39-36} = R1;
271 let Inst{35-32} = R2;
272 let Inst{31-24} = I3;
273 let Inst{23-16} = I4;
275 let Inst{7-0} = op{7-0};
278 class InstRIL<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
279 : InstSystemZ<6, outs, ins, asmstr, pattern> {
281 field bits<48> SoftFail = 0;
286 let Inst{47-40} = op{11-4};
287 let Inst{39-36} = R1;
288 let Inst{35-32} = op{3-0};
292 class InstRIS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
293 : InstSystemZ<6, outs, ins, asmstr, pattern> {
295 field bits<48> SoftFail = 0;
302 let Inst{47-40} = op{15-8};
303 let Inst{39-36} = R1;
304 let Inst{35-32} = M3;
305 let Inst{31-16} = BD4;
307 let Inst{7-0} = op{7-0};
310 class InstRR<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
311 : InstSystemZ<2, outs, ins, asmstr, pattern> {
313 field bits<16> SoftFail = 0;
323 class InstRRD<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
324 : InstSystemZ<4, outs, ins, asmstr, pattern> {
326 field bits<32> SoftFail = 0;
332 let Inst{31-16} = op;
333 let Inst{15-12} = R1;
339 class InstRRE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
340 : InstSystemZ<4, outs, ins, asmstr, pattern> {
342 field bits<32> SoftFail = 0;
347 let Inst{31-16} = op;
353 class InstRRF<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
354 : InstSystemZ<4, outs, ins, asmstr, pattern> {
356 field bits<32> SoftFail = 0;
363 let Inst{31-16} = op;
364 let Inst{15-12} = R3;
370 class InstRRFc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
371 : InstSystemZ<4, outs, ins, asmstr, pattern> {
373 field bits<32> SoftFail = 0;
379 let Inst{31-16} = op;
380 let Inst{15-12} = M3;
386 class InstRRS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
387 : InstSystemZ<6, outs, ins, asmstr, pattern> {
389 field bits<48> SoftFail = 0;
396 let Inst{47-40} = op{15-8};
397 let Inst{39-36} = R1;
398 let Inst{35-32} = R2;
399 let Inst{31-16} = BD4;
400 let Inst{15-12} = M3;
402 let Inst{7-0} = op{7-0};
405 class InstRX<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
406 : InstSystemZ<4, outs, ins, asmstr, pattern> {
408 field bits<32> SoftFail = 0;
413 let Inst{31-24} = op;
414 let Inst{23-20} = R1;
415 let Inst{19-0} = XBD2;
420 class InstRXE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
421 : InstSystemZ<6, outs, ins, asmstr, pattern> {
423 field bits<48> SoftFail = 0;
429 let Inst{47-40} = op{15-8};
430 let Inst{39-36} = R1;
431 let Inst{35-16} = XBD2;
432 let Inst{15-12} = M3;
434 let Inst{7-0} = op{7-0};
439 class InstRXF<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
440 : InstSystemZ<6, outs, ins, asmstr, pattern> {
442 field bits<48> SoftFail = 0;
448 let Inst{47-40} = op{15-8};
449 let Inst{39-36} = R3;
450 let Inst{35-16} = XBD2;
451 let Inst{15-12} = R1;
453 let Inst{7-0} = op{7-0};
458 class InstRXY<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
459 : InstSystemZ<6, outs, ins, asmstr, pattern> {
461 field bits<48> SoftFail = 0;
466 let Inst{47-40} = op{15-8};
467 let Inst{39-36} = R1;
468 let Inst{35-8} = XBD2;
469 let Inst{7-0} = op{7-0};
471 let Has20BitOffset = 1;
475 class InstRS<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
476 : InstSystemZ<4, outs, ins, asmstr, pattern> {
478 field bits<32> SoftFail = 0;
484 let Inst{31-24} = op;
485 let Inst{23-20} = R1;
486 let Inst{19-16} = R3;
487 let Inst{15-0} = BD2;
490 class InstRSY<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
491 : InstSystemZ<6, outs, ins, asmstr, pattern> {
493 field bits<48> SoftFail = 0;
499 let Inst{47-40} = op{15-8};
500 let Inst{39-36} = R1;
501 let Inst{35-32} = R3;
502 let Inst{31-8} = BD2;
503 let Inst{7-0} = op{7-0};
505 let Has20BitOffset = 1;
508 class InstSI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
509 : InstSystemZ<4, outs, ins, asmstr, pattern> {
511 field bits<32> SoftFail = 0;
516 let Inst{31-24} = op;
517 let Inst{23-16} = I2;
518 let Inst{15-0} = BD1;
521 class InstSIL<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
522 : InstSystemZ<6, outs, ins, asmstr, pattern> {
524 field bits<48> SoftFail = 0;
529 let Inst{47-32} = op;
530 let Inst{31-16} = BD1;
534 class InstSIY<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
535 : InstSystemZ<6, outs, ins, asmstr, pattern> {
537 field bits<48> SoftFail = 0;
542 let Inst{47-40} = op{15-8};
543 let Inst{39-32} = I2;
544 let Inst{31-8} = BD1;
545 let Inst{7-0} = op{7-0};
547 let Has20BitOffset = 1;
550 class InstSS<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
551 : InstSystemZ<6, outs, ins, asmstr, pattern> {
553 field bits<48> SoftFail = 0;
558 let Inst{47-40} = op;
559 let Inst{39-16} = BDL1;
560 let Inst{15-0} = BD2;
563 class InstS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
564 : InstSystemZ<4, outs, ins, asmstr, pattern> {
566 field bits<32> SoftFail = 0;
570 let Inst{31-16} = op;
571 let Inst{15-0} = BD2;
574 class InstVRIa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
575 : InstSystemZ<6, outs, ins, asmstr, pattern> {
577 field bits<48> SoftFail = 0;
583 let Inst{47-40} = op{15-8};
584 let Inst{39-36} = V1{3-0};
586 let Inst{31-16} = I2;
587 let Inst{15-12} = M3;
588 let Inst{11} = V1{4};
590 let Inst{7-0} = op{7-0};
593 class InstVRIb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
594 : InstSystemZ<6, outs, ins, asmstr, pattern> {
596 field bits<48> SoftFail = 0;
603 let Inst{47-40} = op{15-8};
604 let Inst{39-36} = V1{3-0};
606 let Inst{31-24} = I2;
607 let Inst{23-16} = I3;
608 let Inst{15-12} = M4;
609 let Inst{11} = V1{4};
611 let Inst{7-0} = op{7-0};
614 class InstVRIc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
615 : InstSystemZ<6, outs, ins, asmstr, pattern> {
617 field bits<48> SoftFail = 0;
624 let Inst{47-40} = op{15-8};
625 let Inst{39-36} = V1{3-0};
626 let Inst{35-32} = V3{3-0};
627 let Inst{31-16} = I2;
628 let Inst{15-12} = M4;
629 let Inst{11} = V1{4};
630 let Inst{10} = V3{4};
632 let Inst{7-0} = op{7-0};
635 class InstVRId<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
636 : InstSystemZ<6, outs, ins, asmstr, pattern> {
638 field bits<48> SoftFail = 0;
646 let Inst{47-40} = op{15-8};
647 let Inst{39-36} = V1{3-0};
648 let Inst{35-32} = V2{3-0};
649 let Inst{31-28} = V3{3-0};
651 let Inst{23-16} = I4;
652 let Inst{15-12} = M5;
653 let Inst{11} = V1{4};
654 let Inst{10} = V2{4};
657 let Inst{7-0} = op{7-0};
660 class InstVRIe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
661 : InstSystemZ<6, outs, ins, asmstr, pattern> {
663 field bits<48> SoftFail = 0;
671 let Inst{47-40} = op{15-8};
672 let Inst{39-36} = V1{3-0};
673 let Inst{35-32} = V2{3-0};
674 let Inst{31-20} = I3;
675 let Inst{19-16} = M5;
676 let Inst{15-12} = M4;
677 let Inst{11} = V1{4};
678 let Inst{10} = V2{4};
680 let Inst{7-0} = op{7-0};
683 // Depending on the instruction mnemonic, certain bits may be or-ed into
684 // the M4 value provided as explicit operand. These are passed as m4or.
685 class InstVRRa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern,
687 : InstSystemZ<6, outs, ins, asmstr, pattern> {
689 field bits<48> SoftFail = 0;
697 let Inst{47-40} = op{15-8};
698 let Inst{39-36} = V1{3-0};
699 let Inst{35-32} = V2{3-0};
701 let Inst{23-20} = M5;
702 let Inst{19} = !if (!eq (m4or{3}, 1), 1, M4{3});
703 let Inst{18} = !if (!eq (m4or{2}, 1), 1, M4{2});
704 let Inst{17} = !if (!eq (m4or{1}, 1), 1, M4{1});
705 let Inst{16} = !if (!eq (m4or{0}, 1), 1, M4{0});
706 let Inst{15-12} = M3;
707 let Inst{11} = V1{4};
708 let Inst{10} = V2{4};
710 let Inst{7-0} = op{7-0};
713 // Depending on the instruction mnemonic, certain bits may be or-ed into
714 // the M5 value provided as explicit operand. These are passed as m5or.
715 class InstVRRb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern,
717 : InstSystemZ<6, outs, ins, asmstr, pattern> {
719 field bits<48> SoftFail = 0;
727 let Inst{47-40} = op{15-8};
728 let Inst{39-36} = V1{3-0};
729 let Inst{35-32} = V2{3-0};
730 let Inst{31-28} = V3{3-0};
732 let Inst{23} = !if (!eq (m5or{3}, 1), 1, M5{3});
733 let Inst{22} = !if (!eq (m5or{2}, 1), 1, M5{2});
734 let Inst{21} = !if (!eq (m5or{1}, 1), 1, M5{1});
735 let Inst{20} = !if (!eq (m5or{0}, 1), 1, M5{0});
737 let Inst{15-12} = M4;
738 let Inst{11} = V1{4};
739 let Inst{10} = V2{4};
742 let Inst{7-0} = op{7-0};
745 class InstVRRc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
746 : InstSystemZ<6, outs, ins, asmstr, pattern> {
748 field bits<48> SoftFail = 0;
757 let Inst{47-40} = op{15-8};
758 let Inst{39-36} = V1{3-0};
759 let Inst{35-32} = V2{3-0};
760 let Inst{31-28} = V3{3-0};
762 let Inst{23-20} = M6;
763 let Inst{19-16} = M5;
764 let Inst{15-12} = M4;
765 let Inst{11} = V1{4};
766 let Inst{10} = V2{4};
769 let Inst{7-0} = op{7-0};
772 // Depending on the instruction mnemonic, certain bits may be or-ed into
773 // the M6 value provided as explicit operand. These are passed as m6or.
774 class InstVRRd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern,
776 : InstSystemZ<6, outs, ins, asmstr, pattern> {
778 field bits<48> SoftFail = 0;
787 let Inst{47-40} = op{15-8};
788 let Inst{39-36} = V1{3-0};
789 let Inst{35-32} = V2{3-0};
790 let Inst{31-28} = V3{3-0};
791 let Inst{27-24} = M5;
792 let Inst{23} = !if (!eq (m6or{3}, 1), 1, M6{3});
793 let Inst{22} = !if (!eq (m6or{2}, 1), 1, M6{2});
794 let Inst{21} = !if (!eq (m6or{1}, 1), 1, M6{1});
795 let Inst{20} = !if (!eq (m6or{0}, 1), 1, M6{0});
797 let Inst{15-12} = V4{3-0};
798 let Inst{11} = V1{4};
799 let Inst{10} = V2{4};
802 let Inst{7-0} = op{7-0};
805 class InstVRRe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
806 : InstSystemZ<6, outs, ins, asmstr, pattern> {
808 field bits<48> SoftFail = 0;
817 let Inst{47-40} = op{15-8};
818 let Inst{39-36} = V1{3-0};
819 let Inst{35-32} = V2{3-0};
820 let Inst{31-28} = V3{3-0};
821 let Inst{27-24} = M6;
823 let Inst{19-16} = M5;
824 let Inst{15-12} = V4{3-0};
825 let Inst{11} = V1{4};
826 let Inst{10} = V2{4};
829 let Inst{7-0} = op{7-0};
832 class InstVRRf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
833 : InstSystemZ<6, outs, ins, asmstr, pattern> {
835 field bits<48> SoftFail = 0;
841 let Inst{47-40} = op{15-8};
842 let Inst{39-36} = V1{3-0};
843 let Inst{35-32} = R2;
844 let Inst{31-28} = R3;
846 let Inst{11} = V1{4};
848 let Inst{7-0} = op{7-0};
851 class InstVRSa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
852 : InstSystemZ<6, outs, ins, asmstr, pattern> {
854 field bits<48> SoftFail = 0;
861 let Inst{47-40} = op{15-8};
862 let Inst{39-36} = V1{3-0};
863 let Inst{35-32} = V3{3-0};
864 let Inst{31-16} = BD2;
865 let Inst{15-12} = M4;
866 let Inst{11} = V1{4};
867 let Inst{10} = V3{4};
869 let Inst{7-0} = op{7-0};
872 class InstVRSb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
873 : InstSystemZ<6, outs, ins, asmstr, pattern> {
875 field bits<48> SoftFail = 0;
882 let Inst{47-40} = op{15-8};
883 let Inst{39-36} = V1{3-0};
884 let Inst{35-32} = R3;
885 let Inst{31-16} = BD2;
886 let Inst{15-12} = M4;
887 let Inst{11} = V1{4};
889 let Inst{7-0} = op{7-0};
892 class InstVRSc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
893 : InstSystemZ<6, outs, ins, asmstr, pattern> {
895 field bits<48> SoftFail = 0;
902 let Inst{47-40} = op{15-8};
903 let Inst{39-36} = R1;
904 let Inst{35-32} = V3{3-0};
905 let Inst{31-16} = BD2;
906 let Inst{15-12} = M4;
908 let Inst{10} = V3{4};
910 let Inst{7-0} = op{7-0};
913 class InstVRV<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
914 : InstSystemZ<6, outs, ins, asmstr, pattern> {
916 field bits<48> SoftFail = 0;
922 let Inst{47-40} = op{15-8};
923 let Inst{39-36} = V1{3-0};
924 let Inst{35-16} = VBD2{19-0};
925 let Inst{15-12} = M3;
926 let Inst{11} = V1{4};
927 let Inst{10} = VBD2{20};
929 let Inst{7-0} = op{7-0};
932 class InstVRX<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
933 : InstSystemZ<6, outs, ins, asmstr, pattern> {
935 field bits<48> SoftFail = 0;
941 let Inst{47-40} = op{15-8};
942 let Inst{39-36} = V1{3-0};
943 let Inst{35-16} = XBD2;
944 let Inst{15-12} = M3;
945 let Inst{11} = V1{4};
947 let Inst{7-0} = op{7-0};
950 //===----------------------------------------------------------------------===//
951 // Instruction definitions with semantics
952 //===----------------------------------------------------------------------===//
954 // These classes have the form [Cond]<Category><Format>, where <Format> is one
955 // of the formats defined above and where <Category> describes the inputs
956 // and outputs. "Cond" is used if the instruction is conditional,
957 // in which case the 4-bit condition-code mask is added as a final operand.
958 // <Category> can be one of:
961 // One register output operand and no input operands.
964 // One register output operand, one register input operand and
965 // one branch displacement. The instructions stores a modified
966 // form of the source register in the destination register and
967 // branches on the result.
970 // One address input operand and two explicit output operands.
971 // The instruction loads a range of registers from the address,
972 // with the explicit operands giving the first and last register
973 // to load. Other loaded registers are added as implicit definitions.
976 // Two explicit input register operands and an address operand.
977 // The instruction stores a range of registers to the address,
978 // with the explicit operands giving the first and last register
979 // to store. Other stored registers are added as implicit uses.
982 // One value operand, one length operand and one address operand.
983 // The instruction stores the value operand to the address but
984 // doesn't write more than the number of bytes specified by the
988 // One register output operand and one input operand.
991 // One address operand and one other input operand. The instruction
992 // stores to the address.
995 // One register output operand and two input operands.
998 // One address operand and two other input operands. The instruction
999 // stores to the address.
1002 // Two input operands and an implicit CC output operand.
1005 // Two input operands and an implicit CC output operand. The second
1006 // input operand is an "address" operand used as a test class mask.
1009 // One register output operand and three input operands.
1012 // One register output operand and four input operands.
1015 // One output operand and two input operands, one of which is an address.
1016 // The instruction both reads from and writes to the address.
1019 // One output operand and three input operands, one of which is an address.
1020 // The instruction both reads from and writes to the address.
1023 // One output operand and five input operands. The first two operands
1024 // are registers and the other three are immediates.
1027 // One 4-bit immediate operand and one address operand. The immediate
1028 // operand is 1 for a load prefetch and 2 for a store prefetch.
1030 // The format determines which input operands are tied to output operands,
1031 // and also determines the shape of any address operand.
1033 // Multiclasses of the form <Category><Format>Pair define two instructions,
1034 // one with <Category><Format> and one with <Category><Format>Y. The name
1035 // of the first instruction has no suffix, the name of the second has
1038 //===----------------------------------------------------------------------===//
1040 class InherentRRE<string mnemonic, bits<16> opcode, RegisterOperand cls,
1042 : InstRRE<opcode, (outs cls:$R1), (ins),
1044 [(set cls:$R1, src)]> {
1048 class InherentVRIa<string mnemonic, bits<16> opcode, bits<16> value>
1049 : InstVRIa<opcode, (outs VR128:$V1), (ins), mnemonic#"\t$V1", []> {
1054 class BranchUnaryRI<string mnemonic, bits<12> opcode, RegisterOperand cls>
1055 : InstRI<opcode, (outs cls:$R1), (ins cls:$R1src, brtarget16:$I2),
1056 mnemonic##"\t$R1, $I2", []> {
1058 let isTerminator = 1;
1059 let Constraints = "$R1 = $R1src";
1060 let DisableEncoding = "$R1src";
1063 class LoadMultipleRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
1064 AddressingMode mode = bdaddr12only>
1065 : InstRS<opcode, (outs cls:$R1, cls:$R3), (ins mode:$BD2),
1066 mnemonic#"\t$R1, $R3, $BD2", []> {
1070 class LoadMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
1071 AddressingMode mode = bdaddr20only>
1072 : InstRSY<opcode, (outs cls:$R1, cls:$R3), (ins mode:$BD2),
1073 mnemonic#"\t$R1, $R3, $BD2", []> {
1077 multiclass LoadMultipleRSPair<string mnemonic, bits<8> rsOpcode,
1078 bits<16> rsyOpcode, RegisterOperand cls> {
1079 let DispKey = mnemonic ## #cls in {
1080 let DispSize = "12" in
1081 def "" : LoadMultipleRS<mnemonic, rsOpcode, cls, bdaddr12pair>;
1082 let DispSize = "20" in
1083 def Y : LoadMultipleRSY<mnemonic#"y", rsyOpcode, cls, bdaddr20pair>;
1087 class LoadMultipleVRSa<string mnemonic, bits<16> opcode>
1088 : InstVRSa<opcode, (outs VR128:$V1, VR128:$V3), (ins bdaddr12only:$BD2),
1089 mnemonic#"\t$V1, $V3, $BD2", []> {
1094 class StoreRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator,
1095 RegisterOperand cls>
1096 : InstRIL<opcode, (outs), (ins cls:$R1, pcrel32:$I2),
1097 mnemonic#"\t$R1, $I2",
1098 [(operator cls:$R1, pcrel32:$I2)]> {
1100 // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
1101 // However, BDXs have two extra operands and are therefore 6 units more
1103 let AddedComplexity = 7;
1106 class StoreRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
1107 RegisterOperand cls, bits<5> bytes,
1108 AddressingMode mode = bdxaddr12only>
1109 : InstRX<opcode, (outs), (ins cls:$R1, mode:$XBD2),
1110 mnemonic#"\t$R1, $XBD2",
1111 [(operator cls:$R1, mode:$XBD2)]> {
1112 let OpKey = mnemonic ## cls;
1115 let AccessBytes = bytes;
1118 class StoreRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1119 RegisterOperand cls, bits<5> bytes,
1120 AddressingMode mode = bdxaddr20only>
1121 : InstRXY<opcode, (outs), (ins cls:$R1, mode:$XBD2),
1122 mnemonic#"\t$R1, $XBD2",
1123 [(operator cls:$R1, mode:$XBD2)]> {
1124 let OpKey = mnemonic ## cls;
1127 let AccessBytes = bytes;
1130 multiclass StoreRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
1131 SDPatternOperator operator, RegisterOperand cls,
1133 let DispKey = mnemonic ## #cls in {
1134 let DispSize = "12" in
1135 def "" : StoreRX<mnemonic, rxOpcode, operator, cls, bytes, bdxaddr12pair>;
1136 let DispSize = "20" in
1137 def Y : StoreRXY<mnemonic#"y", rxyOpcode, operator, cls, bytes,
1142 class StoreVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1143 TypedReg tr, bits<5> bytes, bits<4> type = 0>
1144 : InstVRX<opcode, (outs), (ins tr.op:$V1, bdxaddr12only:$XBD2),
1145 mnemonic#"\t$V1, $XBD2",
1146 [(set tr.op:$V1, (tr.vt (operator bdxaddr12only:$XBD2)))]> {
1149 let AccessBytes = bytes;
1152 class StoreLengthVRSb<string mnemonic, bits<16> opcode,
1153 SDPatternOperator operator, bits<5> bytes>
1154 : InstVRSb<opcode, (outs), (ins VR128:$V1, GR32:$R3, bdaddr12only:$BD2),
1155 mnemonic#"\t$V1, $R3, $BD2",
1156 [(operator VR128:$V1, GR32:$R3, bdaddr12only:$BD2)]> {
1159 let AccessBytes = bytes;
1162 class StoreMultipleRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
1163 AddressingMode mode = bdaddr12only>
1164 : InstRS<opcode, (outs), (ins cls:$R1, cls:$R3, mode:$BD2),
1165 mnemonic#"\t$R1, $R3, $BD2", []> {
1169 class StoreMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
1170 AddressingMode mode = bdaddr20only>
1171 : InstRSY<opcode, (outs), (ins cls:$R1, cls:$R3, mode:$BD2),
1172 mnemonic#"\t$R1, $R3, $BD2", []> {
1176 multiclass StoreMultipleRSPair<string mnemonic, bits<8> rsOpcode,
1177 bits<16> rsyOpcode, RegisterOperand cls> {
1178 let DispKey = mnemonic ## #cls in {
1179 let DispSize = "12" in
1180 def "" : StoreMultipleRS<mnemonic, rsOpcode, cls, bdaddr12pair>;
1181 let DispSize = "20" in
1182 def Y : StoreMultipleRSY<mnemonic#"y", rsyOpcode, cls, bdaddr20pair>;
1186 class StoreMultipleVRSa<string mnemonic, bits<16> opcode>
1187 : InstVRSa<opcode, (outs), (ins VR128:$V1, VR128:$V3, bdaddr12only:$BD2),
1188 mnemonic#"\t$V1, $V3, $BD2", []> {
1193 // StoreSI* instructions are used to store an integer to memory, but the
1194 // addresses are more restricted than for normal stores. If we are in the
1195 // situation of having to force either the address into a register or the
1196 // constant into a register, it's usually better to do the latter.
1197 // We therefore match the address in the same way as a normal store and
1198 // only use the StoreSI* instruction if the matched address is suitable.
1199 class StoreSI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
1201 : InstSI<opcode, (outs), (ins mviaddr12pair:$BD1, imm:$I2),
1202 mnemonic#"\t$BD1, $I2",
1203 [(operator imm:$I2, mviaddr12pair:$BD1)]> {
1207 class StoreSIY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1209 : InstSIY<opcode, (outs), (ins mviaddr20pair:$BD1, imm:$I2),
1210 mnemonic#"\t$BD1, $I2",
1211 [(operator imm:$I2, mviaddr20pair:$BD1)]> {
1215 class StoreSIL<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1217 : InstSIL<opcode, (outs), (ins mviaddr12pair:$BD1, imm:$I2),
1218 mnemonic#"\t$BD1, $I2",
1219 [(operator imm:$I2, mviaddr12pair:$BD1)]> {
1223 multiclass StoreSIPair<string mnemonic, bits<8> siOpcode, bits<16> siyOpcode,
1224 SDPatternOperator operator, Immediate imm> {
1225 let DispKey = mnemonic in {
1226 let DispSize = "12" in
1227 def "" : StoreSI<mnemonic, siOpcode, operator, imm>;
1228 let DispSize = "20" in
1229 def Y : StoreSIY<mnemonic#"y", siyOpcode, operator, imm>;
1233 class CondStoreRSY<string mnemonic, bits<16> opcode,
1234 RegisterOperand cls, bits<5> bytes,
1235 AddressingMode mode = bdaddr20only>
1236 : InstRSY<opcode, (outs), (ins cls:$R1, mode:$BD2, cond4:$valid, cond4:$R3),
1237 mnemonic#"$R3\t$R1, $BD2", []>,
1238 Requires<[FeatureLoadStoreOnCond]> {
1240 let AccessBytes = bytes;
1244 // Like CondStoreRSY, but used for the raw assembly form. The condition-code
1245 // mask is the third operand rather than being part of the mnemonic.
1246 class AsmCondStoreRSY<string mnemonic, bits<16> opcode,
1247 RegisterOperand cls, bits<5> bytes,
1248 AddressingMode mode = bdaddr20only>
1249 : InstRSY<opcode, (outs), (ins cls:$R1, mode:$BD2, imm32zx4:$R3),
1250 mnemonic#"\t$R1, $BD2, $R3", []>,
1251 Requires<[FeatureLoadStoreOnCond]> {
1253 let AccessBytes = bytes;
1256 // Like CondStoreRSY, but with a fixed CC mask.
1257 class FixedCondStoreRSY<string mnemonic, bits<16> opcode,
1258 RegisterOperand cls, bits<4> ccmask, bits<5> bytes,
1259 AddressingMode mode = bdaddr20only>
1260 : InstRSY<opcode, (outs), (ins cls:$R1, mode:$BD2),
1261 mnemonic#"\t$R1, $BD2", []>,
1262 Requires<[FeatureLoadStoreOnCond]> {
1264 let AccessBytes = bytes;
1268 class UnaryRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
1269 RegisterOperand cls1, RegisterOperand cls2>
1270 : InstRR<opcode, (outs cls1:$R1), (ins cls2:$R2),
1271 mnemonic#"r\t$R1, $R2",
1272 [(set cls1:$R1, (operator cls2:$R2))]> {
1273 let OpKey = mnemonic ## cls1;
1277 class UnaryRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1278 RegisterOperand cls1, RegisterOperand cls2>
1279 : InstRRE<opcode, (outs cls1:$R1), (ins cls2:$R2),
1280 mnemonic#"r\t$R1, $R2",
1281 [(set cls1:$R1, (operator cls2:$R2))]> {
1282 let OpKey = mnemonic ## cls1;
1286 class UnaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
1287 RegisterOperand cls2>
1288 : InstRRF<opcode, (outs cls1:$R1), (ins imm32zx4:$R3, cls2:$R2),
1289 mnemonic#"r\t$R1, $R3, $R2", []> {
1290 let OpKey = mnemonic ## cls1;
1295 class UnaryRRF4<string mnemonic, bits<16> opcode, RegisterOperand cls1,
1296 RegisterOperand cls2>
1297 : InstRRF<opcode, (outs cls1:$R1), (ins imm32zx4:$R3, cls2:$R2, imm32zx4:$R4),
1298 mnemonic#"\t$R1, $R3, $R2, $R4", []>;
1300 // These instructions are generated by if conversion. The old value of R1
1301 // is added as an implicit use.
1302 class CondUnaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
1303 RegisterOperand cls2>
1304 : InstRRF<opcode, (outs cls1:$R1), (ins cls2:$R2, cond4:$valid, cond4:$R3),
1305 mnemonic#"r$R3\t$R1, $R2", []>,
1306 Requires<[FeatureLoadStoreOnCond]> {
1311 class CondUnaryRIE<string mnemonic, bits<16> opcode, RegisterOperand cls,
1313 : InstRIEd<opcode, (outs cls:$R1),
1314 (ins imm:$I2, cond4:$valid, cond4:$R3),
1315 mnemonic#"$R3\t$R1, $I2", []>,
1316 Requires<[FeatureLoadStoreOnCond2]> {
1320 // Like CondUnaryRRF, but used for the raw assembly form. The condition-code
1321 // mask is the third operand rather than being part of the mnemonic.
1322 class AsmCondUnaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
1323 RegisterOperand cls2>
1324 : InstRRF<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2, imm32zx4:$R3),
1325 mnemonic#"r\t$R1, $R2, $R3", []>,
1326 Requires<[FeatureLoadStoreOnCond]> {
1327 let Constraints = "$R1 = $R1src";
1328 let DisableEncoding = "$R1src";
1332 class AsmCondUnaryRIE<string mnemonic, bits<16> opcode, RegisterOperand cls,
1334 : InstRIEd<opcode, (outs cls:$R1),
1335 (ins cls:$R1src, imm:$I2, imm32zx4:$R3),
1336 mnemonic#"\t$R1, $I2, $R3", []>,
1337 Requires<[FeatureLoadStoreOnCond2]> {
1338 let Constraints = "$R1 = $R1src";
1339 let DisableEncoding = "$R1src";
1342 // Like CondUnaryRRF, but with a fixed CC mask.
1343 class FixedCondUnaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
1344 RegisterOperand cls2, bits<4> ccmask>
1345 : InstRRF<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
1346 mnemonic#"\t$R1, $R2", []>,
1347 Requires<[FeatureLoadStoreOnCond]> {
1348 let Constraints = "$R1 = $R1src";
1349 let DisableEncoding = "$R1src";
1354 class FixedCondUnaryRIE<string mnemonic, bits<16> opcode, RegisterOperand cls,
1355 Immediate imm, bits<4> ccmask>
1356 : InstRIEd<opcode, (outs cls:$R1),
1357 (ins cls:$R1src, imm:$I2),
1358 mnemonic#"\t$R1, $I2", []>,
1359 Requires<[FeatureLoadStoreOnCond2]> {
1360 let Constraints = "$R1 = $R1src";
1361 let DisableEncoding = "$R1src";
1365 class UnaryRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
1366 RegisterOperand cls, Immediate imm>
1367 : InstRI<opcode, (outs cls:$R1), (ins imm:$I2),
1368 mnemonic#"\t$R1, $I2",
1369 [(set cls:$R1, (operator imm:$I2))]>;
1371 class UnaryRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator,
1372 RegisterOperand cls, Immediate imm>
1373 : InstRIL<opcode, (outs cls:$R1), (ins imm:$I2),
1374 mnemonic#"\t$R1, $I2",
1375 [(set cls:$R1, (operator imm:$I2))]>;
1377 class UnaryRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator,
1378 RegisterOperand cls>
1379 : InstRIL<opcode, (outs cls:$R1), (ins pcrel32:$I2),
1380 mnemonic#"\t$R1, $I2",
1381 [(set cls:$R1, (operator pcrel32:$I2))]> {
1383 // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
1384 // However, BDXs have two extra operands and are therefore 6 units more
1386 let AddedComplexity = 7;
1389 class CondUnaryRSY<string mnemonic, bits<16> opcode,
1390 SDPatternOperator operator, RegisterOperand cls,
1391 bits<5> bytes, AddressingMode mode = bdaddr20only>
1392 : InstRSY<opcode, (outs cls:$R1),
1393 (ins cls:$R1src, mode:$BD2, cond4:$valid, cond4:$R3),
1394 mnemonic#"$R3\t$R1, $BD2",
1396 (z_select_ccmask (load bdaddr20only:$BD2), cls:$R1src,
1397 cond4:$valid, cond4:$R3))]>,
1398 Requires<[FeatureLoadStoreOnCond]> {
1399 let Constraints = "$R1 = $R1src";
1400 let DisableEncoding = "$R1src";
1402 let AccessBytes = bytes;
1406 // Like CondUnaryRSY, but used for the raw assembly form. The condition-code
1407 // mask is the third operand rather than being part of the mnemonic.
1408 class AsmCondUnaryRSY<string mnemonic, bits<16> opcode,
1409 RegisterOperand cls, bits<5> bytes,
1410 AddressingMode mode = bdaddr20only>
1411 : InstRSY<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$BD2, imm32zx4:$R3),
1412 mnemonic#"\t$R1, $BD2, $R3", []>,
1413 Requires<[FeatureLoadStoreOnCond]> {
1415 let AccessBytes = bytes;
1416 let Constraints = "$R1 = $R1src";
1417 let DisableEncoding = "$R1src";
1420 // Like CondUnaryRSY, but with a fixed CC mask.
1421 class FixedCondUnaryRSY<string mnemonic, bits<16> opcode,
1422 RegisterOperand cls, bits<4> ccmask, bits<5> bytes,
1423 AddressingMode mode = bdaddr20only>
1424 : InstRSY<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$BD2),
1425 mnemonic#"\t$R1, $BD2", []>,
1426 Requires<[FeatureLoadStoreOnCond]> {
1427 let Constraints = "$R1 = $R1src";
1428 let DisableEncoding = "$R1src";
1431 let AccessBytes = bytes;
1434 class UnaryRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
1435 RegisterOperand cls, bits<5> bytes,
1436 AddressingMode mode = bdxaddr12only>
1437 : InstRX<opcode, (outs cls:$R1), (ins mode:$XBD2),
1438 mnemonic#"\t$R1, $XBD2",
1439 [(set cls:$R1, (operator mode:$XBD2))]> {
1440 let OpKey = mnemonic ## cls;
1443 let AccessBytes = bytes;
1446 class UnaryRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1447 RegisterOperand cls, bits<5> bytes>
1448 : InstRXE<opcode, (outs cls:$R1), (ins bdxaddr12only:$XBD2),
1449 mnemonic#"\t$R1, $XBD2",
1450 [(set cls:$R1, (operator bdxaddr12only:$XBD2))]> {
1451 let OpKey = mnemonic ## cls;
1454 let AccessBytes = bytes;
1458 class UnaryRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1459 RegisterOperand cls, bits<5> bytes,
1460 AddressingMode mode = bdxaddr20only>
1461 : InstRXY<opcode, (outs cls:$R1), (ins mode:$XBD2),
1462 mnemonic#"\t$R1, $XBD2",
1463 [(set cls:$R1, (operator mode:$XBD2))]> {
1464 let OpKey = mnemonic ## cls;
1467 let AccessBytes = bytes;
1470 multiclass UnaryRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
1471 SDPatternOperator operator, RegisterOperand cls,
1473 let DispKey = mnemonic ## #cls in {
1474 let DispSize = "12" in
1475 def "" : UnaryRX<mnemonic, rxOpcode, operator, cls, bytes, bdxaddr12pair>;
1476 let DispSize = "20" in
1477 def Y : UnaryRXY<mnemonic#"y", rxyOpcode, operator, cls, bytes,
1482 class UnaryVRIa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1483 TypedReg tr, Immediate imm, bits<4> type = 0>
1484 : InstVRIa<opcode, (outs tr.op:$V1), (ins imm:$I2),
1485 mnemonic#"\t$V1, $I2",
1486 [(set tr.op:$V1, (tr.vt (operator imm:$I2)))]> {
1490 class UnaryVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1491 TypedReg tr1, TypedReg tr2, bits<4> type = 0, bits<4> m4 = 0,
1493 : InstVRRa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2),
1494 mnemonic#"\t$V1, $V2",
1495 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2))))]> {
1501 multiclass UnaryVRRaSPair<string mnemonic, bits<16> opcode,
1502 SDPatternOperator operator,
1503 SDPatternOperator operator_cc, TypedReg tr1,
1504 TypedReg tr2, bits<4> type, bits<4> modifier = 0,
1505 bits<4> modifier_cc = 1> {
1506 def "" : UnaryVRRa<mnemonic, opcode, operator, tr1, tr2, type, 0, modifier>;
1508 def S : UnaryVRRa<mnemonic##"s", opcode, operator_cc, tr1, tr2, type, 0,
1512 class UnaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1513 TypedReg tr, bits<5> bytes, bits<4> type = 0>
1514 : InstVRX<opcode, (outs tr.op:$V1), (ins bdxaddr12only:$XBD2),
1515 mnemonic#"\t$V1, $XBD2",
1516 [(set tr.op:$V1, (tr.vt (operator bdxaddr12only:$XBD2)))]> {
1519 let AccessBytes = bytes;
1522 class BinaryRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
1523 RegisterOperand cls1, RegisterOperand cls2>
1524 : InstRR<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
1525 mnemonic#"r\t$R1, $R2",
1526 [(set cls1:$R1, (operator cls1:$R1src, cls2:$R2))]> {
1527 let OpKey = mnemonic ## cls1;
1529 let Constraints = "$R1 = $R1src";
1530 let DisableEncoding = "$R1src";
1533 class BinaryRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1534 RegisterOperand cls1, RegisterOperand cls2>
1535 : InstRRE<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
1536 mnemonic#"r\t$R1, $R2",
1537 [(set cls1:$R1, (operator cls1:$R1src, cls2:$R2))]> {
1538 let OpKey = mnemonic ## cls1;
1540 let Constraints = "$R1 = $R1src";
1541 let DisableEncoding = "$R1src";
1544 class BinaryRRF<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1545 RegisterOperand cls1, RegisterOperand cls2>
1546 : InstRRF<opcode, (outs cls1:$R1), (ins cls1:$R2, cls2:$R3),
1547 mnemonic#"r\t$R1, $R3, $R2",
1548 [(set cls1:$R1, (operator cls1:$R2, cls2:$R3))]> {
1549 let OpKey = mnemonic ## cls1;
1554 class BinaryRRFK<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1555 RegisterOperand cls1, RegisterOperand cls2>
1556 : InstRRF<opcode, (outs cls1:$R1), (ins cls1:$R2, cls2:$R3),
1557 mnemonic#"rk\t$R1, $R2, $R3",
1558 [(set cls1:$R1, (operator cls1:$R2, cls2:$R3))]> {
1562 multiclass BinaryRRAndK<string mnemonic, bits<8> opcode1, bits<16> opcode2,
1563 SDPatternOperator operator, RegisterOperand cls1,
1564 RegisterOperand cls2> {
1565 let NumOpsKey = mnemonic in {
1566 let NumOpsValue = "3" in
1567 def K : BinaryRRFK<mnemonic, opcode2, null_frag, cls1, cls2>,
1568 Requires<[FeatureDistinctOps]>;
1569 let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in
1570 def "" : BinaryRR<mnemonic, opcode1, operator, cls1, cls2>;
1574 multiclass BinaryRREAndK<string mnemonic, bits<16> opcode1, bits<16> opcode2,
1575 SDPatternOperator operator, RegisterOperand cls1,
1576 RegisterOperand cls2> {
1577 let NumOpsKey = mnemonic in {
1578 let NumOpsValue = "3" in
1579 def K : BinaryRRFK<mnemonic, opcode2, null_frag, cls1, cls2>,
1580 Requires<[FeatureDistinctOps]>;
1581 let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in
1582 def "" : BinaryRRE<mnemonic, opcode1, operator, cls1, cls2>;
1586 class BinaryRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
1587 RegisterOperand cls, Immediate imm>
1588 : InstRI<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
1589 mnemonic#"\t$R1, $I2",
1590 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
1591 let Constraints = "$R1 = $R1src";
1592 let DisableEncoding = "$R1src";
1595 class BinaryRIE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1596 RegisterOperand cls, Immediate imm>
1597 : InstRIEd<opcode, (outs cls:$R1), (ins cls:$R3, imm:$I2),
1598 mnemonic#"\t$R1, $R3, $I2",
1599 [(set cls:$R1, (operator cls:$R3, imm:$I2))]>;
1601 multiclass BinaryRIAndK<string mnemonic, bits<12> opcode1, bits<16> opcode2,
1602 SDPatternOperator operator, RegisterOperand cls,
1604 let NumOpsKey = mnemonic in {
1605 let NumOpsValue = "3" in
1606 def K : BinaryRIE<mnemonic##"k", opcode2, null_frag, cls, imm>,
1607 Requires<[FeatureDistinctOps]>;
1608 let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in
1609 def "" : BinaryRI<mnemonic, opcode1, operator, cls, imm>;
1613 class BinaryRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator,
1614 RegisterOperand cls, Immediate imm>
1615 : InstRIL<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
1616 mnemonic#"\t$R1, $I2",
1617 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
1618 let Constraints = "$R1 = $R1src";
1619 let DisableEncoding = "$R1src";
1622 class BinaryRS<string mnemonic, bits<8> opcode, SDPatternOperator operator,
1623 RegisterOperand cls>
1624 : InstRS<opcode, (outs cls:$R1), (ins cls:$R1src, shift12only:$BD2),
1625 mnemonic#"\t$R1, $BD2",
1626 [(set cls:$R1, (operator cls:$R1src, shift12only:$BD2))]> {
1628 let Constraints = "$R1 = $R1src";
1629 let DisableEncoding = "$R1src";
1632 class BinaryRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1633 RegisterOperand cls>
1634 : InstRSY<opcode, (outs cls:$R1), (ins cls:$R3, shift20only:$BD2),
1635 mnemonic#"\t$R1, $R3, $BD2",
1636 [(set cls:$R1, (operator cls:$R3, shift20only:$BD2))]>;
1638 multiclass BinaryRSAndK<string mnemonic, bits<8> opcode1, bits<16> opcode2,
1639 SDPatternOperator operator, RegisterOperand cls> {
1640 let NumOpsKey = mnemonic in {
1641 let NumOpsValue = "3" in
1642 def K : BinaryRSY<mnemonic##"k", opcode2, null_frag, cls>,
1643 Requires<[FeatureDistinctOps]>;
1644 let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in
1645 def "" : BinaryRS<mnemonic, opcode1, operator, cls>;
1649 class BinaryRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
1650 RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
1651 AddressingMode mode = bdxaddr12only>
1652 : InstRX<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$XBD2),
1653 mnemonic#"\t$R1, $XBD2",
1654 [(set cls:$R1, (operator cls:$R1src, (load mode:$XBD2)))]> {
1655 let OpKey = mnemonic ## cls;
1657 let Constraints = "$R1 = $R1src";
1658 let DisableEncoding = "$R1src";
1660 let AccessBytes = bytes;
1663 class BinaryRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1664 RegisterOperand cls, SDPatternOperator load, bits<5> bytes>
1665 : InstRXE<opcode, (outs cls:$R1), (ins cls:$R1src, bdxaddr12only:$XBD2),
1666 mnemonic#"\t$R1, $XBD2",
1667 [(set cls:$R1, (operator cls:$R1src,
1668 (load bdxaddr12only:$XBD2)))]> {
1669 let OpKey = mnemonic ## cls;
1671 let Constraints = "$R1 = $R1src";
1672 let DisableEncoding = "$R1src";
1674 let AccessBytes = bytes;
1678 class BinaryRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1679 RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
1680 AddressingMode mode = bdxaddr20only>
1681 : InstRXY<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$XBD2),
1682 mnemonic#"\t$R1, $XBD2",
1683 [(set cls:$R1, (operator cls:$R1src, (load mode:$XBD2)))]> {
1684 let OpKey = mnemonic ## cls;
1686 let Constraints = "$R1 = $R1src";
1687 let DisableEncoding = "$R1src";
1689 let AccessBytes = bytes;
1692 multiclass BinaryRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
1693 SDPatternOperator operator, RegisterOperand cls,
1694 SDPatternOperator load, bits<5> bytes> {
1695 let DispKey = mnemonic ## #cls in {
1696 let DispSize = "12" in
1697 def "" : BinaryRX<mnemonic, rxOpcode, operator, cls, load, bytes,
1699 let DispSize = "20" in
1700 def Y : BinaryRXY<mnemonic#"y", rxyOpcode, operator, cls, load, bytes,
1705 class BinarySI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
1706 Operand imm, AddressingMode mode = bdaddr12only>
1707 : InstSI<opcode, (outs), (ins mode:$BD1, imm:$I2),
1708 mnemonic#"\t$BD1, $I2",
1709 [(store (operator (load mode:$BD1), imm:$I2), mode:$BD1)]> {
1714 class BinarySIY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1715 Operand imm, AddressingMode mode = bdaddr20only>
1716 : InstSIY<opcode, (outs), (ins mode:$BD1, imm:$I2),
1717 mnemonic#"\t$BD1, $I2",
1718 [(store (operator (load mode:$BD1), imm:$I2), mode:$BD1)]> {
1723 multiclass BinarySIPair<string mnemonic, bits<8> siOpcode,
1724 bits<16> siyOpcode, SDPatternOperator operator,
1726 let DispKey = mnemonic ## #cls in {
1727 let DispSize = "12" in
1728 def "" : BinarySI<mnemonic, siOpcode, operator, imm, bdaddr12pair>;
1729 let DispSize = "20" in
1730 def Y : BinarySIY<mnemonic#"y", siyOpcode, operator, imm, bdaddr20pair>;
1734 class BinaryVRIb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1735 TypedReg tr, bits<4> type>
1736 : InstVRIb<opcode, (outs tr.op:$V1), (ins imm32zx8:$I2, imm32zx8:$I3),
1737 mnemonic#"\t$V1, $I2, $I3",
1738 [(set tr.op:$V1, (tr.vt (operator imm32zx8:$I2, imm32zx8:$I3)))]> {
1742 class BinaryVRIc<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1743 TypedReg tr1, TypedReg tr2, bits<4> type>
1744 : InstVRIc<opcode, (outs tr1.op:$V1), (ins tr2.op:$V3, imm32zx16:$I2),
1745 mnemonic#"\t$V1, $V3, $I2",
1746 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V3),
1747 imm32zx16:$I2)))]> {
1751 class BinaryVRIe<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1752 TypedReg tr1, TypedReg tr2, bits<4> type, bits<4> m5>
1753 : InstVRIe<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, imm32zx12:$I3),
1754 mnemonic#"\t$V1, $V2, $I3",
1755 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
1756 imm32zx12:$I3)))]> {
1761 class BinaryVRRa<string mnemonic, bits<16> opcode>
1762 : InstVRRa<opcode, (outs VR128:$V1), (ins VR128:$V2, imm32zx4:$M3),
1763 mnemonic#"\t$V1, $V2, $M3", []> {
1768 class BinaryVRRb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1769 TypedReg tr1, TypedReg tr2, bits<4> type = 0,
1770 bits<4> modifier = 0>
1771 : InstVRRb<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, tr2.op:$V3),
1772 mnemonic#"\t$V1, $V2, $V3",
1773 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
1774 (tr2.vt tr2.op:$V3))))]> {
1779 // Declare a pair of instructions, one which sets CC and one which doesn't.
1780 // The CC-setting form ends with "S" and sets the low bit of M5.
1781 multiclass BinaryVRRbSPair<string mnemonic, bits<16> opcode,
1782 SDPatternOperator operator,
1783 SDPatternOperator operator_cc, TypedReg tr1,
1784 TypedReg tr2, bits<4> type,
1785 bits<4> modifier = 0, bits<4> modifier_cc = 1> {
1786 def "" : BinaryVRRb<mnemonic, opcode, operator, tr1, tr2, type, modifier>;
1788 def S : BinaryVRRb<mnemonic##"s", opcode, operator_cc, tr1, tr2, type,
1792 class BinaryVRRc<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1793 TypedReg tr1, TypedReg tr2, bits<4> type = 0, bits<4> m5 = 0,
1795 : InstVRRc<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, tr2.op:$V3),
1796 mnemonic#"\t$V1, $V2, $V3",
1797 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
1798 (tr2.vt tr2.op:$V3))))]> {
1804 multiclass BinaryVRRcSPair<string mnemonic, bits<16> opcode,
1805 SDPatternOperator operator,
1806 SDPatternOperator operator_cc, TypedReg tr1,
1807 TypedReg tr2, bits<4> type, bits<4> m5,
1808 bits<4> modifier = 0, bits<4> modifier_cc = 1> {
1809 def "" : BinaryVRRc<mnemonic, opcode, operator, tr1, tr2, type, m5, modifier>;
1811 def S : BinaryVRRc<mnemonic##"s", opcode, operator_cc, tr1, tr2, type,
1815 class BinaryVRRf<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1817 : InstVRRf<opcode, (outs tr.op:$V1), (ins GR64:$R2, GR64:$R3),
1818 mnemonic#"\t$V1, $R2, $R3",
1819 [(set tr.op:$V1, (tr.vt (operator GR64:$R2, GR64:$R3)))]>;
1821 class BinaryVRSa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1822 TypedReg tr1, TypedReg tr2, bits<4> type>
1823 : InstVRSa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V3, shift12only:$BD2),
1824 mnemonic#"\t$V1, $V3, $BD2",
1825 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V3),
1826 shift12only:$BD2)))]> {
1830 class BinaryVRSb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1832 : InstVRSb<opcode, (outs VR128:$V1), (ins GR32:$R3, bdaddr12only:$BD2),
1833 mnemonic#"\t$V1, $R3, $BD2",
1834 [(set VR128:$V1, (operator GR32:$R3, bdaddr12only:$BD2))]> {
1837 let AccessBytes = bytes;
1840 class BinaryVRSc<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1841 TypedReg tr, bits<4> type>
1842 : InstVRSc<opcode, (outs GR64:$R1), (ins tr.op:$V3, shift12only:$BD2),
1843 mnemonic#"\t$R1, $V3, $BD2",
1844 [(set GR64:$R1, (operator (tr.vt tr.op:$V3), shift12only:$BD2))]> {
1848 class BinaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1849 TypedReg tr, bits<5> bytes>
1850 : InstVRX<opcode, (outs VR128:$V1), (ins bdxaddr12only:$XBD2, imm32zx4:$M3),
1851 mnemonic#"\t$V1, $XBD2, $M3",
1852 [(set tr.op:$V1, (tr.vt (operator bdxaddr12only:$XBD2,
1855 let AccessBytes = bytes;
1858 class StoreBinaryVRV<string mnemonic, bits<16> opcode, bits<5> bytes,
1860 : InstVRV<opcode, (outs), (ins VR128:$V1, bdvaddr12only:$VBD2, index:$M3),
1861 mnemonic#"\t$V1, $VBD2, $M3", []> {
1863 let AccessBytes = bytes;
1866 class StoreBinaryVRX<string mnemonic, bits<16> opcode,
1867 SDPatternOperator operator, TypedReg tr, bits<5> bytes,
1869 : InstVRX<opcode, (outs), (ins tr.op:$V1, bdxaddr12only:$XBD2, index:$M3),
1870 mnemonic#"\t$V1, $XBD2, $M3",
1871 [(operator (tr.vt tr.op:$V1), bdxaddr12only:$XBD2, index:$M3)]> {
1873 let AccessBytes = bytes;
1876 class CompareRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
1877 RegisterOperand cls1, RegisterOperand cls2>
1878 : InstRR<opcode, (outs), (ins cls1:$R1, cls2:$R2),
1879 mnemonic#"r\t$R1, $R2",
1880 [(operator cls1:$R1, cls2:$R2)]> {
1881 let OpKey = mnemonic ## cls1;
1886 class CompareRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1887 RegisterOperand cls1, RegisterOperand cls2>
1888 : InstRRE<opcode, (outs), (ins cls1:$R1, cls2:$R2),
1889 mnemonic#"r\t$R1, $R2",
1890 [(operator cls1:$R1, cls2:$R2)]> {
1891 let OpKey = mnemonic ## cls1;
1896 class CompareRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
1897 RegisterOperand cls, Immediate imm>
1898 : InstRI<opcode, (outs), (ins cls:$R1, imm:$I2),
1899 mnemonic#"\t$R1, $I2",
1900 [(operator cls:$R1, imm:$I2)]> {
1904 class CompareRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator,
1905 RegisterOperand cls, Immediate imm>
1906 : InstRIL<opcode, (outs), (ins cls:$R1, imm:$I2),
1907 mnemonic#"\t$R1, $I2",
1908 [(operator cls:$R1, imm:$I2)]> {
1912 class CompareRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator,
1913 RegisterOperand cls, SDPatternOperator load>
1914 : InstRIL<opcode, (outs), (ins cls:$R1, pcrel32:$I2),
1915 mnemonic#"\t$R1, $I2",
1916 [(operator cls:$R1, (load pcrel32:$I2))]> {
1919 // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
1920 // However, BDXs have two extra operands and are therefore 6 units more
1922 let AddedComplexity = 7;
1925 class CompareRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
1926 RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
1927 AddressingMode mode = bdxaddr12only>
1928 : InstRX<opcode, (outs), (ins cls:$R1, mode:$XBD2),
1929 mnemonic#"\t$R1, $XBD2",
1930 [(operator cls:$R1, (load mode:$XBD2))]> {
1931 let OpKey = mnemonic ## cls;
1935 let AccessBytes = bytes;
1938 class CompareRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1939 RegisterOperand cls, SDPatternOperator load, bits<5> bytes>
1940 : InstRXE<opcode, (outs), (ins cls:$R1, bdxaddr12only:$XBD2),
1941 mnemonic#"\t$R1, $XBD2",
1942 [(operator cls:$R1, (load bdxaddr12only:$XBD2))]> {
1943 let OpKey = mnemonic ## cls;
1947 let AccessBytes = bytes;
1951 class CompareRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1952 RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
1953 AddressingMode mode = bdxaddr20only>
1954 : InstRXY<opcode, (outs), (ins cls:$R1, mode:$XBD2),
1955 mnemonic#"\t$R1, $XBD2",
1956 [(operator cls:$R1, (load mode:$XBD2))]> {
1957 let OpKey = mnemonic ## cls;
1961 let AccessBytes = bytes;
1964 multiclass CompareRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
1965 SDPatternOperator operator, RegisterOperand cls,
1966 SDPatternOperator load, bits<5> bytes> {
1967 let DispKey = mnemonic ## #cls in {
1968 let DispSize = "12" in
1969 def "" : CompareRX<mnemonic, rxOpcode, operator, cls,
1970 load, bytes, bdxaddr12pair>;
1971 let DispSize = "20" in
1972 def Y : CompareRXY<mnemonic#"y", rxyOpcode, operator, cls,
1973 load, bytes, bdxaddr20pair>;
1977 class CompareSI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
1978 SDPatternOperator load, Immediate imm,
1979 AddressingMode mode = bdaddr12only>
1980 : InstSI<opcode, (outs), (ins mode:$BD1, imm:$I2),
1981 mnemonic#"\t$BD1, $I2",
1982 [(operator (load mode:$BD1), imm:$I2)]> {
1987 class CompareSIL<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1988 SDPatternOperator load, Immediate imm>
1989 : InstSIL<opcode, (outs), (ins bdaddr12only:$BD1, imm:$I2),
1990 mnemonic#"\t$BD1, $I2",
1991 [(operator (load bdaddr12only:$BD1), imm:$I2)]> {
1996 class CompareSIY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1997 SDPatternOperator load, Immediate imm,
1998 AddressingMode mode = bdaddr20only>
1999 : InstSIY<opcode, (outs), (ins mode:$BD1, imm:$I2),
2000 mnemonic#"\t$BD1, $I2",
2001 [(operator (load mode:$BD1), imm:$I2)]> {
2006 multiclass CompareSIPair<string mnemonic, bits<8> siOpcode, bits<16> siyOpcode,
2007 SDPatternOperator operator, SDPatternOperator load,
2009 let DispKey = mnemonic in {
2010 let DispSize = "12" in
2011 def "" : CompareSI<mnemonic, siOpcode, operator, load, imm, bdaddr12pair>;
2012 let DispSize = "20" in
2013 def Y : CompareSIY<mnemonic#"y", siyOpcode, operator, load, imm,
2018 class CompareVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2019 TypedReg tr, bits<4> type>
2020 : InstVRRa<opcode, (outs), (ins tr.op:$V1, tr.op:$V2),
2021 mnemonic#"\t$V1, $V2",
2022 [(operator (tr.vt tr.op:$V1), (tr.vt tr.op:$V2))]> {
2029 class TestRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2030 RegisterOperand cls>
2031 : InstRXE<opcode, (outs), (ins cls:$R1, bdxaddr12only:$XBD2),
2032 mnemonic#"\t$R1, $XBD2",
2033 [(operator cls:$R1, bdxaddr12only:$XBD2)]> {
2037 class TernaryRRD<string mnemonic, bits<16> opcode,
2038 SDPatternOperator operator, RegisterOperand cls>
2039 : InstRRD<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, cls:$R2),
2040 mnemonic#"r\t$R1, $R3, $R2",
2041 [(set cls:$R1, (operator cls:$R1src, cls:$R3, cls:$R2))]> {
2042 let OpKey = mnemonic ## cls;
2044 let Constraints = "$R1 = $R1src";
2045 let DisableEncoding = "$R1src";
2048 class TernaryRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
2049 bits<5> bytes, AddressingMode mode = bdaddr12only>
2050 : InstRS<opcode, (outs cls:$R1),
2051 (ins cls:$R1src, imm32zx4:$R3, mode:$BD2),
2052 mnemonic#"\t$R1, $R3, $BD2", []> {
2054 let Constraints = "$R1 = $R1src";
2055 let DisableEncoding = "$R1src";
2057 let AccessBytes = bytes;
2060 class TernaryRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
2061 bits<5> bytes, AddressingMode mode = bdaddr20only>
2062 : InstRSY<opcode, (outs cls:$R1),
2063 (ins cls:$R1src, imm32zx4:$R3, mode:$BD2),
2064 mnemonic#"\t$R1, $R3, $BD2", []> {
2066 let Constraints = "$R1 = $R1src";
2067 let DisableEncoding = "$R1src";
2069 let AccessBytes = bytes;
2072 multiclass TernaryRSPair<string mnemonic, bits<8> rsOpcode, bits<16> rsyOpcode,
2073 RegisterOperand cls, bits<5> bytes> {
2074 let DispKey = mnemonic ## #cls in {
2075 let DispSize = "12" in
2076 def "" : TernaryRS<mnemonic, rsOpcode, cls, bytes, bdaddr12pair>;
2077 let DispSize = "20" in
2078 def Y : TernaryRSY<mnemonic#"y", rsyOpcode, cls, bytes, bdaddr20pair>;
2082 class TernaryRXF<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2083 RegisterOperand cls, SDPatternOperator load, bits<5> bytes>
2084 : InstRXF<opcode, (outs cls:$R1),
2085 (ins cls:$R1src, cls:$R3, bdxaddr12only:$XBD2),
2086 mnemonic#"\t$R1, $R3, $XBD2",
2087 [(set cls:$R1, (operator cls:$R1src, cls:$R3,
2088 (load bdxaddr12only:$XBD2)))]> {
2089 let OpKey = mnemonic ## cls;
2091 let Constraints = "$R1 = $R1src";
2092 let DisableEncoding = "$R1src";
2094 let AccessBytes = bytes;
2097 class TernaryVRIa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2098 TypedReg tr1, TypedReg tr2, Immediate imm, Immediate index>
2099 : InstVRIa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V1src, imm:$I2, index:$M3),
2100 mnemonic#"\t$V1, $I2, $M3",
2101 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V1src),
2102 imm:$I2, index:$M3)))]> {
2103 let Constraints = "$V1 = $V1src";
2104 let DisableEncoding = "$V1src";
2107 class TernaryVRId<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2108 TypedReg tr1, TypedReg tr2, bits<4> type>
2109 : InstVRId<opcode, (outs tr1.op:$V1),
2110 (ins tr2.op:$V2, tr2.op:$V3, imm32zx8:$I4),
2111 mnemonic#"\t$V1, $V2, $V3, $I4",
2112 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
2113 (tr2.vt tr2.op:$V3),
2118 class TernaryVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2119 TypedReg tr1, TypedReg tr2, bits<4> type, bits<4> m4or>
2120 : InstVRRa<opcode, (outs tr1.op:$V1),
2121 (ins tr2.op:$V2, imm32zx4:$M4, imm32zx4:$M5),
2122 mnemonic#"\t$V1, $V2, $M4, $M5",
2123 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
2130 class TernaryVRRb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2131 TypedReg tr1, TypedReg tr2, bits<4> type,
2132 SDPatternOperator m5mask, bits<4> m5or>
2133 : InstVRRb<opcode, (outs tr1.op:$V1),
2134 (ins tr2.op:$V2, tr2.op:$V3, m5mask:$M5),
2135 mnemonic#"\t$V1, $V2, $V3, $M5",
2136 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
2137 (tr2.vt tr2.op:$V3),
2143 multiclass TernaryVRRbSPair<string mnemonic, bits<16> opcode,
2144 SDPatternOperator operator,
2145 SDPatternOperator operator_cc, TypedReg tr1,
2146 TypedReg tr2, bits<4> type, bits<4> m5or> {
2147 def "" : TernaryVRRb<mnemonic, opcode, operator, tr1, tr2, type,
2148 imm32zx4even, !and (m5or, 14)>;
2149 def : InstAlias<mnemonic#"\t$V1, $V2, $V3",
2150 (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2,
2153 def S : TernaryVRRb<mnemonic##"s", opcode, operator_cc, tr1, tr2, type,
2154 imm32zx4even, !add(!and (m5or, 14), 1)>;
2155 def : InstAlias<mnemonic#"s\t$V1, $V2, $V3",
2156 (!cast<Instruction>(NAME#"S") tr1.op:$V1, tr2.op:$V2,
2160 class TernaryVRRc<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2161 TypedReg tr1, TypedReg tr2>
2162 : InstVRRc<opcode, (outs tr1.op:$V1),
2163 (ins tr2.op:$V2, tr2.op:$V3, imm32zx4:$M4),
2164 mnemonic#"\t$V1, $V2, $V3, $M4",
2165 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
2166 (tr2.vt tr2.op:$V3),
2172 class TernaryVRRd<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2173 TypedReg tr1, TypedReg tr2, bits<4> type = 0>
2174 : InstVRRd<opcode, (outs tr1.op:$V1),
2175 (ins tr2.op:$V2, tr2.op:$V3, tr1.op:$V4),
2176 mnemonic#"\t$V1, $V2, $V3, $V4",
2177 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
2178 (tr2.vt tr2.op:$V3),
2179 (tr1.vt tr1.op:$V4))))]> {
2184 class TernaryVRRe<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2185 TypedReg tr1, TypedReg tr2, bits<4> m5 = 0, bits<4> type = 0>
2186 : InstVRRe<opcode, (outs tr1.op:$V1),
2187 (ins tr2.op:$V2, tr2.op:$V3, tr1.op:$V4),
2188 mnemonic#"\t$V1, $V2, $V3, $V4",
2189 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
2190 (tr2.vt tr2.op:$V3),
2191 (tr1.vt tr1.op:$V4))))]> {
2196 class TernaryVRSb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2197 TypedReg tr1, TypedReg tr2, RegisterOperand cls, bits<4> type>
2198 : InstVRSb<opcode, (outs tr1.op:$V1),
2199 (ins tr2.op:$V1src, cls:$R3, shift12only:$BD2),
2200 mnemonic#"\t$V1, $R3, $BD2",
2201 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V1src),
2203 shift12only:$BD2)))]> {
2204 let Constraints = "$V1 = $V1src";
2205 let DisableEncoding = "$V1src";
2209 class TernaryVRV<string mnemonic, bits<16> opcode, bits<5> bytes,
2211 : InstVRV<opcode, (outs VR128:$V1),
2212 (ins VR128:$V1src, bdvaddr12only:$VBD2, index:$M3),
2213 mnemonic#"\t$V1, $VBD2, $M3", []> {
2214 let Constraints = "$V1 = $V1src";
2215 let DisableEncoding = "$V1src";
2217 let AccessBytes = bytes;
2220 class TernaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2221 TypedReg tr1, TypedReg tr2, bits<5> bytes, Immediate index>
2222 : InstVRX<opcode, (outs tr1.op:$V1),
2223 (ins tr2.op:$V1src, bdxaddr12only:$XBD2, index:$M3),
2224 mnemonic#"\t$V1, $XBD2, $M3",
2225 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V1src),
2226 bdxaddr12only:$XBD2,
2228 let Constraints = "$V1 = $V1src";
2229 let DisableEncoding = "$V1src";
2231 let AccessBytes = bytes;
2234 class QuaternaryVRId<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2235 TypedReg tr1, TypedReg tr2, bits<4> type>
2236 : InstVRId<opcode, (outs tr1.op:$V1),
2237 (ins tr2.op:$V1src, tr2.op:$V2, tr2.op:$V3, imm32zx8:$I4),
2238 mnemonic#"\t$V1, $V2, $V3, $I4",
2239 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V1src),
2240 (tr2.vt tr2.op:$V2),
2241 (tr2.vt tr2.op:$V3),
2243 let Constraints = "$V1 = $V1src";
2244 let DisableEncoding = "$V1src";
2248 class QuaternaryVRRd<string mnemonic, bits<16> opcode,
2249 SDPatternOperator operator, TypedReg tr1, TypedReg tr2,
2250 bits<4> type, SDPatternOperator m6mask, bits<4> m6or>
2251 : InstVRRd<opcode, (outs tr1.op:$V1),
2252 (ins tr2.op:$V2, tr2.op:$V3, tr2.op:$V4, m6mask:$M6),
2253 mnemonic#"\t$V1, $V2, $V3, $V4, $M6",
2254 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
2255 (tr2.vt tr2.op:$V3),
2256 (tr2.vt tr2.op:$V4),
2262 multiclass QuaternaryVRRdSPair<string mnemonic, bits<16> opcode,
2263 SDPatternOperator operator,
2264 SDPatternOperator operator_cc, TypedReg tr1,
2265 TypedReg tr2, bits<4> type, bits<4> m6or> {
2266 def "" : QuaternaryVRRd<mnemonic, opcode, operator, tr1, tr2, type,
2267 imm32zx4even, !and (m6or, 14)>;
2268 def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $V4",
2269 (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2,
2270 tr2.op:$V3, tr2.op:$V4, 0)>;
2272 def S : QuaternaryVRRd<mnemonic##"s", opcode, operator_cc, tr1, tr2, type,
2273 imm32zx4even, !add (!and (m6or, 14), 1)>;
2274 def : InstAlias<mnemonic#"s\t$V1, $V2, $V3, $V4",
2275 (!cast<Instruction>(NAME#"S") tr1.op:$V1, tr2.op:$V2,
2276 tr2.op:$V3, tr2.op:$V4, 0)>;
2279 class LoadAndOpRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2280 RegisterOperand cls, AddressingMode mode = bdaddr20only>
2281 : InstRSY<opcode, (outs cls:$R1), (ins cls:$R3, mode:$BD2),
2282 mnemonic#"\t$R1, $R3, $BD2",
2283 [(set cls:$R1, (operator mode:$BD2, cls:$R3))]> {
2288 class CmpSwapRS<string mnemonic, bits<8> opcode, SDPatternOperator operator,
2289 RegisterOperand cls, AddressingMode mode = bdaddr12only>
2290 : InstRS<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, mode:$BD2),
2291 mnemonic#"\t$R1, $R3, $BD2",
2292 [(set cls:$R1, (operator mode:$BD2, cls:$R1src, cls:$R3))]> {
2293 let Constraints = "$R1 = $R1src";
2294 let DisableEncoding = "$R1src";
2299 class CmpSwapRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2300 RegisterOperand cls, AddressingMode mode = bdaddr20only>
2301 : InstRSY<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, mode:$BD2),
2302 mnemonic#"\t$R1, $R3, $BD2",
2303 [(set cls:$R1, (operator mode:$BD2, cls:$R1src, cls:$R3))]> {
2304 let Constraints = "$R1 = $R1src";
2305 let DisableEncoding = "$R1src";
2310 multiclass CmpSwapRSPair<string mnemonic, bits<8> rsOpcode, bits<16> rsyOpcode,
2311 SDPatternOperator operator, RegisterOperand cls> {
2312 let DispKey = mnemonic ## #cls in {
2313 let DispSize = "12" in
2314 def "" : CmpSwapRS<mnemonic, rsOpcode, operator, cls, bdaddr12pair>;
2315 let DispSize = "20" in
2316 def Y : CmpSwapRSY<mnemonic#"y", rsyOpcode, operator, cls, bdaddr20pair>;
2320 class RotateSelectRIEf<string mnemonic, bits<16> opcode, RegisterOperand cls1,
2321 RegisterOperand cls2>
2322 : InstRIEf<opcode, (outs cls1:$R1),
2323 (ins cls1:$R1src, cls2:$R2, imm32zx8:$I3, imm32zx8:$I4,
2325 mnemonic#"\t$R1, $R2, $I3, $I4, $I5", []> {
2326 let Constraints = "$R1 = $R1src";
2327 let DisableEncoding = "$R1src";
2330 class PrefetchRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator>
2331 : InstRXY<opcode, (outs), (ins imm32zx4:$R1, bdxaddr20only:$XBD2),
2332 mnemonic##"\t$R1, $XBD2",
2333 [(operator imm32zx4:$R1, bdxaddr20only:$XBD2)]>;
2335 class PrefetchRILPC<string mnemonic, bits<12> opcode,
2336 SDPatternOperator operator>
2337 : InstRIL<opcode, (outs), (ins imm32zx4:$R1, pcrel32:$I2),
2338 mnemonic##"\t$R1, $I2",
2339 [(operator imm32zx4:$R1, pcrel32:$I2)]> {
2340 // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
2341 // However, BDXs have two extra operands and are therefore 6 units more
2343 let AddedComplexity = 7;
2346 // A floating-point load-and test operation. Create both a normal unary
2347 // operation and one that acts as a comparison against zero.
2348 // Note that the comparison against zero operation is not available if we
2349 // have vector support, since load-and-test instructions will partially
2350 // clobber the target (vector) register.
2351 multiclass LoadAndTestRRE<string mnemonic, bits<16> opcode,
2352 RegisterOperand cls> {
2353 def "" : UnaryRRE<mnemonic, opcode, null_frag, cls, cls>;
2354 let isCodeGenOnly = 1, Predicates = [FeatureNoVector] in
2355 def Compare : CompareRRE<mnemonic, opcode, null_frag, cls, cls>;
2358 //===----------------------------------------------------------------------===//
2359 // Pseudo instructions
2360 //===----------------------------------------------------------------------===//
2362 // Convenience instructions that get lowered to real instructions
2363 // by either SystemZTargetLowering::EmitInstrWithCustomInserter()
2364 // or SystemZInstrInfo::expandPostRAPseudo().
2366 //===----------------------------------------------------------------------===//
2368 class Pseudo<dag outs, dag ins, list<dag> pattern>
2369 : InstSystemZ<0, outs, ins, "", pattern> {
2371 let isCodeGenOnly = 1;
2374 // Like UnaryRI, but expanded after RA depending on the choice of register.
2375 class UnaryRIPseudo<SDPatternOperator operator, RegisterOperand cls,
2377 : Pseudo<(outs cls:$R1), (ins imm:$I2),
2378 [(set cls:$R1, (operator imm:$I2))]>;
2380 // Like UnaryRXY, but expanded after RA depending on the choice of register.
2381 class UnaryRXYPseudo<string key, SDPatternOperator operator,
2382 RegisterOperand cls, bits<5> bytes,
2383 AddressingMode mode = bdxaddr20only>
2384 : Pseudo<(outs cls:$R1), (ins mode:$XBD2),
2385 [(set cls:$R1, (operator mode:$XBD2))]> {
2386 let OpKey = key ## cls;
2389 let Has20BitOffset = 1;
2391 let AccessBytes = bytes;
2394 // Like UnaryRR, but expanded after RA depending on the choice of registers.
2395 class UnaryRRPseudo<string key, SDPatternOperator operator,
2396 RegisterOperand cls1, RegisterOperand cls2>
2397 : Pseudo<(outs cls1:$R1), (ins cls2:$R2),
2398 [(set cls1:$R1, (operator cls2:$R2))]> {
2399 let OpKey = key ## cls1;
2403 // Like BinaryRI, but expanded after RA depending on the choice of register.
2404 class BinaryRIPseudo<SDPatternOperator operator, RegisterOperand cls,
2406 : Pseudo<(outs cls:$R1), (ins cls:$R1src, imm:$I2),
2407 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
2408 let Constraints = "$R1 = $R1src";
2411 // Like BinaryRIE, but expanded after RA depending on the choice of register.
2412 class BinaryRIEPseudo<SDPatternOperator operator, RegisterOperand cls,
2414 : Pseudo<(outs cls:$R1), (ins cls:$R3, imm:$I2),
2415 [(set cls:$R1, (operator cls:$R3, imm:$I2))]>;
2417 // Like BinaryRIAndK, but expanded after RA depending on the choice of register.
2418 multiclass BinaryRIAndKPseudo<string key, SDPatternOperator operator,
2419 RegisterOperand cls, Immediate imm> {
2420 let NumOpsKey = key in {
2421 let NumOpsValue = "3" in
2422 def K : BinaryRIEPseudo<null_frag, cls, imm>,
2423 Requires<[FeatureHighWord, FeatureDistinctOps]>;
2424 let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in
2425 def "" : BinaryRIPseudo<operator, cls, imm>,
2426 Requires<[FeatureHighWord]>;
2430 // Like CompareRI, but expanded after RA depending on the choice of register.
2431 class CompareRIPseudo<SDPatternOperator operator, RegisterOperand cls,
2433 : Pseudo<(outs), (ins cls:$R1, imm:$I2), [(operator cls:$R1, imm:$I2)]>;
2435 // Like CompareRXY, but expanded after RA depending on the choice of register.
2436 class CompareRXYPseudo<SDPatternOperator operator, RegisterOperand cls,
2437 SDPatternOperator load, bits<5> bytes,
2438 AddressingMode mode = bdxaddr20only>
2439 : Pseudo<(outs), (ins cls:$R1, mode:$XBD2),
2440 [(operator cls:$R1, (load mode:$XBD2))]> {
2442 let Has20BitOffset = 1;
2444 let AccessBytes = bytes;
2447 // Like StoreRXY, but expanded after RA depending on the choice of register.
2448 class StoreRXYPseudo<SDPatternOperator operator, RegisterOperand cls,
2449 bits<5> bytes, AddressingMode mode = bdxaddr20only>
2450 : Pseudo<(outs), (ins cls:$R1, mode:$XBD2),
2451 [(operator cls:$R1, mode:$XBD2)]> {
2453 let Has20BitOffset = 1;
2455 let AccessBytes = bytes;
2458 // Like RotateSelectRIEf, but expanded after RA depending on the choice
2460 class RotateSelectRIEfPseudo<RegisterOperand cls1, RegisterOperand cls2>
2461 : Pseudo<(outs cls1:$R1),
2462 (ins cls1:$R1src, cls2:$R2, imm32zx8:$I3, imm32zx8:$I4,
2465 let Constraints = "$R1 = $R1src";
2466 let DisableEncoding = "$R1src";
2469 // Implements "$dst = $cc & (8 >> CC) ? $src1 : $src2", where CC is
2470 // the value of the PSW's 2-bit condition code field.
2471 class SelectWrapper<RegisterOperand cls>
2472 : Pseudo<(outs cls:$dst),
2473 (ins cls:$src1, cls:$src2, imm32zx4:$valid, imm32zx4:$cc),
2474 [(set cls:$dst, (z_select_ccmask cls:$src1, cls:$src2,
2475 imm32zx4:$valid, imm32zx4:$cc))]> {
2476 let usesCustomInserter = 1;
2477 // Although the instructions used by these nodes do not in themselves
2478 // change CC, the insertion requires new blocks, and CC cannot be live
2484 // Stores $new to $addr if $cc is true ("" case) or false (Inv case).
2485 multiclass CondStores<RegisterOperand cls, SDPatternOperator store,
2486 SDPatternOperator load, AddressingMode mode> {
2487 let Defs = [CC], Uses = [CC], usesCustomInserter = 1 in {
2488 def "" : Pseudo<(outs),
2489 (ins cls:$new, mode:$addr, imm32zx4:$valid, imm32zx4:$cc),
2490 [(store (z_select_ccmask cls:$new, (load mode:$addr),
2491 imm32zx4:$valid, imm32zx4:$cc),
2493 def Inv : Pseudo<(outs),
2494 (ins cls:$new, mode:$addr, imm32zx4:$valid, imm32zx4:$cc),
2495 [(store (z_select_ccmask (load mode:$addr), cls:$new,
2496 imm32zx4:$valid, imm32zx4:$cc),
2501 // OPERATOR is ATOMIC_SWAP or an ATOMIC_LOAD_* operation. PAT and OPERAND
2502 // describe the second (non-memory) operand.
2503 class AtomicLoadBinary<SDPatternOperator operator, RegisterOperand cls,
2504 dag pat, DAGOperand operand>
2505 : Pseudo<(outs cls:$dst), (ins bdaddr20only:$ptr, operand:$src2),
2506 [(set cls:$dst, (operator bdaddr20only:$ptr, pat))]> {
2508 let Has20BitOffset = 1;
2511 let usesCustomInserter = 1;
2514 // Specializations of AtomicLoadWBinary.
2515 class AtomicLoadBinaryReg32<SDPatternOperator operator>
2516 : AtomicLoadBinary<operator, GR32, (i32 GR32:$src2), GR32>;
2517 class AtomicLoadBinaryImm32<SDPatternOperator operator, Immediate imm>
2518 : AtomicLoadBinary<operator, GR32, (i32 imm:$src2), imm>;
2519 class AtomicLoadBinaryReg64<SDPatternOperator operator>
2520 : AtomicLoadBinary<operator, GR64, (i64 GR64:$src2), GR64>;
2521 class AtomicLoadBinaryImm64<SDPatternOperator operator, Immediate imm>
2522 : AtomicLoadBinary<operator, GR64, (i64 imm:$src2), imm>;
2524 // OPERATOR is ATOMIC_SWAPW or an ATOMIC_LOADW_* operation. PAT and OPERAND
2525 // describe the second (non-memory) operand.
2526 class AtomicLoadWBinary<SDPatternOperator operator, dag pat,
2528 : Pseudo<(outs GR32:$dst),
2529 (ins bdaddr20only:$ptr, operand:$src2, ADDR32:$bitshift,
2530 ADDR32:$negbitshift, uimm32:$bitsize),
2531 [(set GR32:$dst, (operator bdaddr20only:$ptr, pat, ADDR32:$bitshift,
2532 ADDR32:$negbitshift, uimm32:$bitsize))]> {
2534 let Has20BitOffset = 1;
2537 let usesCustomInserter = 1;
2540 // Specializations of AtomicLoadWBinary.
2541 class AtomicLoadWBinaryReg<SDPatternOperator operator>
2542 : AtomicLoadWBinary<operator, (i32 GR32:$src2), GR32>;
2543 class AtomicLoadWBinaryImm<SDPatternOperator operator, Immediate imm>
2544 : AtomicLoadWBinary<operator, (i32 imm:$src2), imm>;
2546 // Define an instruction that operates on two fixed-length blocks of memory,
2547 // and associated pseudo instructions for operating on blocks of any size.
2548 // The Sequence form uses a straight-line sequence of instructions and
2549 // the Loop form uses a loop of length-256 instructions followed by
2550 // another instruction to handle the excess.
2551 multiclass MemorySS<string mnemonic, bits<8> opcode,
2552 SDPatternOperator sequence, SDPatternOperator loop> {
2553 def "" : InstSS<opcode, (outs), (ins bdladdr12onlylen8:$BDL1,
2555 mnemonic##"\t$BDL1, $BD2", []>;
2556 let usesCustomInserter = 1 in {
2557 def Sequence : Pseudo<(outs), (ins bdaddr12only:$dest, bdaddr12only:$src,
2559 [(sequence bdaddr12only:$dest, bdaddr12only:$src,
2561 def Loop : Pseudo<(outs), (ins bdaddr12only:$dest, bdaddr12only:$src,
2562 imm64:$length, GR64:$count256),
2563 [(loop bdaddr12only:$dest, bdaddr12only:$src,
2564 imm64:$length, GR64:$count256)]>;
2568 // Define an instruction that operates on two strings, both terminated
2569 // by the character in R0. The instruction processes a CPU-determinated
2570 // number of bytes at a time and sets CC to 3 if the instruction needs
2571 // to be repeated. Also define a pseudo instruction that represents
2572 // the full loop (the main instruction plus the branch on CC==3).
2573 multiclass StringRRE<string mnemonic, bits<16> opcode,
2574 SDPatternOperator operator> {
2575 def "" : InstRRE<opcode, (outs GR64:$R1, GR64:$R2),
2576 (ins GR64:$R1src, GR64:$R2src),
2577 mnemonic#"\t$R1, $R2", []> {
2579 let Constraints = "$R1 = $R1src, $R2 = $R2src";
2580 let DisableEncoding = "$R1src, $R2src";
2582 let usesCustomInserter = 1 in
2583 def Loop : Pseudo<(outs GR64:$end),
2584 (ins GR64:$start1, GR64:$start2, GR32:$char),
2585 [(set GR64:$end, (operator GR64:$start1, GR64:$start2,
2589 // A pseudo instruction that is a direct alias of a real instruction.
2590 // These aliases are used in cases where a particular register operand is
2591 // fixed or where the same instruction is used with different register sizes.
2592 // The size parameter is the size in bytes of the associated real instruction.
2593 class Alias<int size, dag outs, dag ins, list<dag> pattern>
2594 : InstSystemZ<size, outs, ins, "", pattern> {
2596 let isCodeGenOnly = 1;
2599 class UnaryAliasVRS<RegisterOperand cls1, RegisterOperand cls2>
2600 : Alias<6, (outs cls1:$src1), (ins cls2:$src2), []>;
2602 // An alias of a UnaryVRR*, but with different register sizes.
2603 class UnaryAliasVRR<SDPatternOperator operator, TypedReg tr1, TypedReg tr2>
2604 : Alias<6, (outs tr1.op:$V1), (ins tr2.op:$V2),
2605 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2))))]>;
2607 // An alias of a UnaryVRX, but with different register sizes.
2608 class UnaryAliasVRX<SDPatternOperator operator, TypedReg tr,
2609 AddressingMode mode = bdxaddr12only>
2610 : Alias<6, (outs tr.op:$V1), (ins mode:$XBD2),
2611 [(set tr.op:$V1, (tr.vt (operator mode:$XBD2)))]>;
2613 // An alias of a StoreVRX, but with different register sizes.
2614 class StoreAliasVRX<SDPatternOperator operator, TypedReg tr,
2615 AddressingMode mode = bdxaddr12only>
2616 : Alias<6, (outs), (ins tr.op:$V1, mode:$XBD2),
2617 [(operator (tr.vt tr.op:$V1), mode:$XBD2)]>;
2619 // An alias of a BinaryRI, but with different register sizes.
2620 class BinaryAliasRI<SDPatternOperator operator, RegisterOperand cls,
2622 : Alias<4, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
2623 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
2624 let Constraints = "$R1 = $R1src";
2627 // An alias of a BinaryRIL, but with different register sizes.
2628 class BinaryAliasRIL<SDPatternOperator operator, RegisterOperand cls,
2630 : Alias<6, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
2631 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
2632 let Constraints = "$R1 = $R1src";
2635 // An alias of a BinaryVRRf, but with different register sizes.
2636 class BinaryAliasVRRf<RegisterOperand cls>
2637 : Alias<6, (outs VR128:$V1), (ins cls:$R2, cls:$R3), []>;
2639 // An alias of a CompareRI, but with different register sizes.
2640 class CompareAliasRI<SDPatternOperator operator, RegisterOperand cls,
2642 : Alias<4, (outs), (ins cls:$R1, imm:$I2), [(operator cls:$R1, imm:$I2)]> {
2646 // An alias of a RotateSelectRIEf, but with different register sizes.
2647 class RotateSelectAliasRIEf<RegisterOperand cls1, RegisterOperand cls2>
2648 : Alias<6, (outs cls1:$R1),
2649 (ins cls1:$R1src, cls2:$R2, imm32zx8:$I3, imm32zx8:$I4,
2650 imm32zx6:$I5), []> {
2651 let Constraints = "$R1 = $R1src";