1 //==- SystemZInstrFormats.td - SystemZ Instruction Formats --*- tablegen -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Basic SystemZ instruction definition
12 //===----------------------------------------------------------------------===//
14 class InstSystemZ<int size, dag outs, dag ins, string asmstr,
15 list<dag> pattern> : Instruction {
16 let Namespace = "SystemZ";
18 dag OutOperandList = outs;
19 dag InOperandList = ins;
21 let Pattern = pattern;
22 let AsmString = asmstr;
24 // Some instructions come in pairs, one having a 12-bit displacement
25 // and the other having a 20-bit displacement. Both instructions in
26 // the pair have the same DispKey and their DispSizes are "12" and "20"
29 string DispSize = "none";
31 // Many register-based <INSN>R instructions have a memory-based <INSN>
32 // counterpart. OpKey uniquely identifies <INSN>R, while OpType is
33 // "reg" for <INSN>R and "mem" for <INSN>.
35 string OpType = "none";
37 // Many distinct-operands instructions have older 2-operand equivalents.
38 // NumOpsKey uniquely identifies one of these 2-operand and 3-operand pairs,
39 // with NumOpsValue being "2" or "3" as appropriate.
40 string NumOpsKey = "";
41 string NumOpsValue = "none";
43 // True if this instruction is a simple D(X,B) load of a register
44 // (with no sign or zero extension).
45 bit SimpleBDXLoad = 0;
47 // True if this instruction is a simple D(X,B) store of a register
48 // (with no truncation).
49 bit SimpleBDXStore = 0;
51 // True if this instruction has a 20-bit displacement field.
52 bit Has20BitOffset = 0;
54 // True if addresses in this instruction have an index register.
57 // True if this is a 128-bit pseudo instruction that combines two 64-bit
61 // The access size of all memory operands in bytes, or 0 if not known.
62 bits<5> AccessBytes = 0;
64 // If the instruction sets CC to a useful value, this gives the mask
65 // of all possible CC results. The mask has the same form as
69 // The subset of CCValues that have the same meaning as they would after
70 // a comparison of the first operand against zero.
71 bits<4> CompareZeroCCMask = 0;
73 // True if the instruction is conditional and if the CC mask operand
74 // comes first (as for BRC, etc.).
77 // Similar, but true if the CC mask operand comes last (as for LOC, etc.).
80 // True if the instruction is the "logical" rather than "arithmetic" form,
81 // in cases where a distinction exists.
84 let TSFlags{0} = SimpleBDXLoad;
85 let TSFlags{1} = SimpleBDXStore;
86 let TSFlags{2} = Has20BitOffset;
87 let TSFlags{3} = HasIndex;
88 let TSFlags{4} = Is128Bit;
89 let TSFlags{9-5} = AccessBytes;
90 let TSFlags{13-10} = CCValues;
91 let TSFlags{17-14} = CompareZeroCCMask;
92 let TSFlags{18} = CCMaskFirst;
93 let TSFlags{19} = CCMaskLast;
94 let TSFlags{20} = IsLogical;
97 //===----------------------------------------------------------------------===//
98 // Mappings between instructions
99 //===----------------------------------------------------------------------===//
101 // Return the version of an instruction that has an unsigned 12-bit
103 def getDisp12Opcode : InstrMapping {
104 let FilterClass = "InstSystemZ";
105 let RowFields = ["DispKey"];
106 let ColFields = ["DispSize"];
108 let ValueCols = [["12"]];
111 // Return the version of an instruction that has a signed 20-bit displacement.
112 def getDisp20Opcode : InstrMapping {
113 let FilterClass = "InstSystemZ";
114 let RowFields = ["DispKey"];
115 let ColFields = ["DispSize"];
117 let ValueCols = [["20"]];
120 // Return the memory form of a register instruction.
121 def getMemOpcode : InstrMapping {
122 let FilterClass = "InstSystemZ";
123 let RowFields = ["OpKey"];
124 let ColFields = ["OpType"];
125 let KeyCol = ["reg"];
126 let ValueCols = [["mem"]];
129 // Return the 3-operand form of a 2-operand instruction.
130 def getThreeOperandOpcode : InstrMapping {
131 let FilterClass = "InstSystemZ";
132 let RowFields = ["NumOpsKey"];
133 let ColFields = ["NumOpsValue"];
135 let ValueCols = [["3"]];
138 //===----------------------------------------------------------------------===//
139 // Instruction formats
140 //===----------------------------------------------------------------------===//
142 // Formats are specified using operand field declarations of the form:
144 // bits<4> Rn : register input or output for operand n
145 // bits<5> Vn : vector register input or output for operand n
146 // bits<m> In : immediate value of width m for operand n
147 // bits<4> BDn : address operand n, which has a base and a displacement
148 // bits<m> XBDn : address operand n, which has an index, a base and a
150 // bits<m> VBDn : address operand n, which has a vector index, a base and a
152 // bits<4> Xn : index register for address operand n
153 // bits<4> Mn : mode value for operand n
155 // The operand numbers ("n" in the list above) follow the architecture manual.
156 // Assembly operands sometimes have a different order; in particular, R3 often
157 // is often written between operands 1 and 2.
159 //===----------------------------------------------------------------------===//
161 class InstE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
162 : InstSystemZ<2, outs, ins, asmstr, pattern> {
164 field bits<16> SoftFail = 0;
169 class InstI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
170 : InstSystemZ<2, outs, ins, asmstr, pattern> {
172 field bits<16> SoftFail = 0;
180 class InstIE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
181 : InstSystemZ<4, outs, ins, asmstr, pattern> {
183 field bits<32> SoftFail = 0;
188 let Inst{31-16} = op;
194 class InstMII<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
195 : InstSystemZ<6, outs, ins, asmstr, pattern> {
197 field bits<48> SoftFail = 0;
203 let Inst{47-40} = op;
204 let Inst{39-36} = M1;
205 let Inst{35-24} = RI2;
206 let Inst{23-0} = RI3;
209 class InstRIa<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
210 : InstSystemZ<4, outs, ins, asmstr, pattern> {
212 field bits<32> SoftFail = 0;
217 let Inst{31-24} = op{11-4};
218 let Inst{23-20} = R1;
219 let Inst{19-16} = op{3-0};
223 class InstRIb<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
224 : InstSystemZ<4, outs, ins, asmstr, pattern> {
226 field bits<32> SoftFail = 0;
231 let Inst{31-24} = op{11-4};
232 let Inst{23-20} = R1;
233 let Inst{19-16} = op{3-0};
234 let Inst{15-0} = RI2;
237 class InstRIc<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
238 : InstSystemZ<4, outs, ins, asmstr, pattern> {
240 field bits<32> SoftFail = 0;
245 let Inst{31-24} = op{11-4};
246 let Inst{23-20} = M1;
247 let Inst{19-16} = op{3-0};
248 let Inst{15-0} = RI2;
251 class InstRIEa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
252 : InstSystemZ<6, outs, ins, asmstr, pattern> {
254 field bits<48> SoftFail = 0;
260 let Inst{47-40} = op{15-8};
261 let Inst{39-36} = R1;
263 let Inst{31-16} = I2;
264 let Inst{15-12} = M3;
266 let Inst{7-0} = op{7-0};
269 class InstRIEb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
270 : InstSystemZ<6, outs, ins, asmstr, pattern> {
272 field bits<48> SoftFail = 0;
279 let Inst{47-40} = op{15-8};
280 let Inst{39-36} = R1;
281 let Inst{35-32} = R2;
282 let Inst{31-16} = RI4;
283 let Inst{15-12} = M3;
285 let Inst{7-0} = op{7-0};
288 class InstRIEc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
289 : InstSystemZ<6, outs, ins, asmstr, pattern> {
291 field bits<48> SoftFail = 0;
298 let Inst{47-40} = op{15-8};
299 let Inst{39-36} = R1;
300 let Inst{35-32} = M3;
301 let Inst{31-16} = RI4;
303 let Inst{7-0} = op{7-0};
306 class InstRIEd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
307 : InstSystemZ<6, outs, ins, asmstr, pattern> {
309 field bits<48> SoftFail = 0;
315 let Inst{47-40} = op{15-8};
316 let Inst{39-36} = R1;
317 let Inst{35-32} = R3;
318 let Inst{31-16} = I2;
320 let Inst{7-0} = op{7-0};
323 class InstRIEe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
324 : InstSystemZ<6, outs, ins, asmstr, pattern> {
326 field bits<48> SoftFail = 0;
332 let Inst{47-40} = op{15-8};
333 let Inst{39-36} = R1;
334 let Inst{35-32} = R3;
335 let Inst{31-16} = RI2;
337 let Inst{7-0} = op{7-0};
340 class InstRIEf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
341 : InstSystemZ<6, outs, ins, asmstr, pattern> {
343 field bits<48> SoftFail = 0;
351 let Inst{47-40} = op{15-8};
352 let Inst{39-36} = R1;
353 let Inst{35-32} = R2;
354 let Inst{31-24} = I3;
355 let Inst{23-16} = I4;
357 let Inst{7-0} = op{7-0};
360 class InstRIEg<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
361 : InstSystemZ<6, outs, ins, asmstr, pattern> {
363 field bits<48> SoftFail = 0;
369 let Inst{47-40} = op{15-8};
370 let Inst{39-36} = R1;
371 let Inst{35-32} = M3;
372 let Inst{31-16} = I2;
374 let Inst{7-0} = op{7-0};
377 class InstRILa<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
378 : InstSystemZ<6, outs, ins, asmstr, pattern> {
380 field bits<48> SoftFail = 0;
385 let Inst{47-40} = op{11-4};
386 let Inst{39-36} = R1;
387 let Inst{35-32} = op{3-0};
391 class InstRILb<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
392 : InstSystemZ<6, outs, ins, asmstr, pattern> {
394 field bits<48> SoftFail = 0;
399 let Inst{47-40} = op{11-4};
400 let Inst{39-36} = R1;
401 let Inst{35-32} = op{3-0};
402 let Inst{31-0} = RI2;
405 class InstRILc<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
406 : InstSystemZ<6, outs, ins, asmstr, pattern> {
408 field bits<48> SoftFail = 0;
413 let Inst{47-40} = op{11-4};
414 let Inst{39-36} = M1;
415 let Inst{35-32} = op{3-0};
416 let Inst{31-0} = RI2;
419 class InstRIS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
420 : InstSystemZ<6, outs, ins, asmstr, pattern> {
422 field bits<48> SoftFail = 0;
429 let Inst{47-40} = op{15-8};
430 let Inst{39-36} = R1;
431 let Inst{35-32} = M3;
432 let Inst{31-16} = BD4;
434 let Inst{7-0} = op{7-0};
437 class InstRR<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
438 : InstSystemZ<2, outs, ins, asmstr, pattern> {
440 field bits<16> SoftFail = 0;
450 class InstRRD<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
451 : InstSystemZ<4, outs, ins, asmstr, pattern> {
453 field bits<32> SoftFail = 0;
459 let Inst{31-16} = op;
460 let Inst{15-12} = R1;
466 class InstRRE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
467 : InstSystemZ<4, outs, ins, asmstr, pattern> {
469 field bits<32> SoftFail = 0;
474 let Inst{31-16} = op;
480 class InstRRFa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
481 : InstSystemZ<4, outs, ins, asmstr, pattern> {
483 field bits<32> SoftFail = 0;
490 let Inst{31-16} = op;
491 let Inst{15-12} = R3;
497 class InstRRFb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
498 : InstSystemZ<4, outs, ins, asmstr, pattern> {
500 field bits<32> SoftFail = 0;
507 let Inst{31-16} = op;
508 let Inst{15-12} = R3;
514 class InstRRFc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
515 : InstSystemZ<4, outs, ins, asmstr, pattern> {
517 field bits<32> SoftFail = 0;
523 let Inst{31-16} = op;
524 let Inst{15-12} = M3;
530 class InstRRFe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
531 : InstSystemZ<4, outs, ins, asmstr, pattern> {
533 field bits<32> SoftFail = 0;
540 let Inst{31-16} = op;
541 let Inst{15-12} = M3;
547 class InstRRS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
548 : InstSystemZ<6, outs, ins, asmstr, pattern> {
550 field bits<48> SoftFail = 0;
557 let Inst{47-40} = op{15-8};
558 let Inst{39-36} = R1;
559 let Inst{35-32} = R2;
560 let Inst{31-16} = BD4;
561 let Inst{15-12} = M3;
563 let Inst{7-0} = op{7-0};
566 class InstRXa<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
567 : InstSystemZ<4, outs, ins, asmstr, pattern> {
569 field bits<32> SoftFail = 0;
574 let Inst{31-24} = op;
575 let Inst{23-20} = R1;
576 let Inst{19-0} = XBD2;
581 class InstRXb<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
582 : InstSystemZ<4, outs, ins, asmstr, pattern> {
584 field bits<32> SoftFail = 0;
589 let Inst{31-24} = op;
590 let Inst{23-20} = M1;
591 let Inst{19-0} = XBD2;
596 class InstRXE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
597 : InstSystemZ<6, outs, ins, asmstr, pattern> {
599 field bits<48> SoftFail = 0;
605 let Inst{47-40} = op{15-8};
606 let Inst{39-36} = R1;
607 let Inst{35-16} = XBD2;
608 let Inst{15-12} = M3;
610 let Inst{7-0} = op{7-0};
615 class InstRXF<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
616 : InstSystemZ<6, outs, ins, asmstr, pattern> {
618 field bits<48> SoftFail = 0;
624 let Inst{47-40} = op{15-8};
625 let Inst{39-36} = R3;
626 let Inst{35-16} = XBD2;
627 let Inst{15-12} = R1;
629 let Inst{7-0} = op{7-0};
634 class InstRXYa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
635 : InstSystemZ<6, outs, ins, asmstr, pattern> {
637 field bits<48> SoftFail = 0;
642 let Inst{47-40} = op{15-8};
643 let Inst{39-36} = R1;
644 let Inst{35-8} = XBD2;
645 let Inst{7-0} = op{7-0};
647 let Has20BitOffset = 1;
651 class InstRXYb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
652 : InstSystemZ<6, outs, ins, asmstr, pattern> {
654 field bits<48> SoftFail = 0;
659 let Inst{47-40} = op{15-8};
660 let Inst{39-36} = M1;
661 let Inst{35-8} = XBD2;
662 let Inst{7-0} = op{7-0};
664 let Has20BitOffset = 1;
668 class InstRSa<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
669 : InstSystemZ<4, outs, ins, asmstr, pattern> {
671 field bits<32> SoftFail = 0;
677 let Inst{31-24} = op;
678 let Inst{23-20} = R1;
679 let Inst{19-16} = R3;
680 let Inst{15-0} = BD2;
683 class InstRSb<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
684 : InstSystemZ<4, outs, ins, asmstr, pattern> {
686 field bits<32> SoftFail = 0;
692 let Inst{31-24} = op;
693 let Inst{23-20} = R1;
694 let Inst{19-16} = M3;
695 let Inst{15-0} = BD2;
698 class InstRSI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
699 : InstSystemZ<4, outs, ins, asmstr, pattern> {
701 field bits<32> SoftFail = 0;
707 let Inst{31-24} = op;
708 let Inst{23-20} = R1;
709 let Inst{19-16} = R3;
710 let Inst{15-0} = RI2;
713 class InstRSYa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
714 : InstSystemZ<6, outs, ins, asmstr, pattern> {
716 field bits<48> SoftFail = 0;
722 let Inst{47-40} = op{15-8};
723 let Inst{39-36} = R1;
724 let Inst{35-32} = R3;
725 let Inst{31-8} = BD2;
726 let Inst{7-0} = op{7-0};
728 let Has20BitOffset = 1;
731 class InstRSYb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
732 : InstSystemZ<6, outs, ins, asmstr, pattern> {
734 field bits<48> SoftFail = 0;
740 let Inst{47-40} = op{15-8};
741 let Inst{39-36} = R1;
742 let Inst{35-32} = M3;
743 let Inst{31-8} = BD2;
744 let Inst{7-0} = op{7-0};
746 let Has20BitOffset = 1;
749 class InstSI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
750 : InstSystemZ<4, outs, ins, asmstr, pattern> {
752 field bits<32> SoftFail = 0;
757 let Inst{31-24} = op;
758 let Inst{23-16} = I2;
759 let Inst{15-0} = BD1;
762 class InstSIL<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
763 : InstSystemZ<6, outs, ins, asmstr, pattern> {
765 field bits<48> SoftFail = 0;
770 let Inst{47-32} = op;
771 let Inst{31-16} = BD1;
775 class InstSIY<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
776 : InstSystemZ<6, outs, ins, asmstr, pattern> {
778 field bits<48> SoftFail = 0;
783 let Inst{47-40} = op{15-8};
784 let Inst{39-32} = I2;
785 let Inst{31-8} = BD1;
786 let Inst{7-0} = op{7-0};
788 let Has20BitOffset = 1;
791 class InstSMI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
792 : InstSystemZ<6, outs, ins, asmstr, pattern> {
794 field bits<48> SoftFail = 0;
800 let Inst{47-40} = op;
801 let Inst{39-36} = M1;
803 let Inst{31-16} = BD3;
804 let Inst{15-0} = RI2;
807 class InstSSa<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
808 : InstSystemZ<6, outs, ins, asmstr, pattern> {
810 field bits<48> SoftFail = 0;
815 let Inst{47-40} = op;
816 let Inst{39-16} = BDL1;
817 let Inst{15-0} = BD2;
820 class InstSSd<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
821 : InstSystemZ<6, outs, ins, asmstr, pattern> {
823 field bits<48> SoftFail = 0;
829 let Inst{47-40} = op;
830 let Inst{39-36} = RBD1{19-16};
831 let Inst{35-32} = R3;
832 let Inst{31-16} = RBD1{15-0};
833 let Inst{15-0} = BD2;
836 class InstSSe<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
837 : InstSystemZ<6, outs, ins, asmstr, pattern> {
839 field bits<48> SoftFail = 0;
846 let Inst{47-40} = op;
847 let Inst{39-36} = R1;
848 let Inst{35-32} = R3;
849 let Inst{31-16} = BD2;
850 let Inst{15-0} = BD4;
853 class InstSSE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
854 : InstSystemZ<6, outs, ins, asmstr, pattern> {
856 field bits<48> SoftFail = 0;
861 let Inst{47-32} = op;
862 let Inst{31-16} = BD1;
863 let Inst{15-0} = BD2;
866 class InstSSF<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
867 : InstSystemZ<6, outs, ins, asmstr, pattern> {
869 field bits<48> SoftFail = 0;
875 let Inst{47-40} = op{11-4};
876 let Inst{39-36} = R3;
877 let Inst{35-32} = op{3-0};
878 let Inst{31-16} = BD1;
879 let Inst{15-0} = BD2;
882 class InstS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
883 : InstSystemZ<4, outs, ins, asmstr, pattern> {
885 field bits<32> SoftFail = 0;
889 let Inst{31-16} = op;
890 let Inst{15-0} = BD2;
893 class InstVRIa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
894 : InstSystemZ<6, outs, ins, asmstr, pattern> {
896 field bits<48> SoftFail = 0;
902 let Inst{47-40} = op{15-8};
903 let Inst{39-36} = V1{3-0};
905 let Inst{31-16} = I2;
906 let Inst{15-12} = M3;
907 let Inst{11} = V1{4};
909 let Inst{7-0} = op{7-0};
912 class InstVRIb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
913 : InstSystemZ<6, outs, ins, asmstr, pattern> {
915 field bits<48> SoftFail = 0;
922 let Inst{47-40} = op{15-8};
923 let Inst{39-36} = V1{3-0};
925 let Inst{31-24} = I2;
926 let Inst{23-16} = I3;
927 let Inst{15-12} = M4;
928 let Inst{11} = V1{4};
930 let Inst{7-0} = op{7-0};
933 class InstVRIc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
934 : InstSystemZ<6, outs, ins, asmstr, pattern> {
936 field bits<48> SoftFail = 0;
943 let Inst{47-40} = op{15-8};
944 let Inst{39-36} = V1{3-0};
945 let Inst{35-32} = V3{3-0};
946 let Inst{31-16} = I2;
947 let Inst{15-12} = M4;
948 let Inst{11} = V1{4};
949 let Inst{10} = V3{4};
951 let Inst{7-0} = op{7-0};
954 class InstVRId<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
955 : InstSystemZ<6, outs, ins, asmstr, pattern> {
957 field bits<48> SoftFail = 0;
965 let Inst{47-40} = op{15-8};
966 let Inst{39-36} = V1{3-0};
967 let Inst{35-32} = V2{3-0};
968 let Inst{31-28} = V3{3-0};
970 let Inst{23-16} = I4;
971 let Inst{15-12} = M5;
972 let Inst{11} = V1{4};
973 let Inst{10} = V2{4};
976 let Inst{7-0} = op{7-0};
979 class InstVRIe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
980 : InstSystemZ<6, outs, ins, asmstr, pattern> {
982 field bits<48> SoftFail = 0;
990 let Inst{47-40} = op{15-8};
991 let Inst{39-36} = V1{3-0};
992 let Inst{35-32} = V2{3-0};
993 let Inst{31-20} = I3;
994 let Inst{19-16} = M5;
995 let Inst{15-12} = M4;
996 let Inst{11} = V1{4};
997 let Inst{10} = V2{4};
999 let Inst{7-0} = op{7-0};
1002 // Depending on the instruction mnemonic, certain bits may be or-ed into
1003 // the M4 value provided as explicit operand. These are passed as m4or.
1004 class InstVRRa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern,
1006 : InstSystemZ<6, outs, ins, asmstr, pattern> {
1007 field bits<48> Inst;
1008 field bits<48> SoftFail = 0;
1016 let Inst{47-40} = op{15-8};
1017 let Inst{39-36} = V1{3-0};
1018 let Inst{35-32} = V2{3-0};
1019 let Inst{31-24} = 0;
1020 let Inst{23-20} = M5;
1021 let Inst{19} = !if (!eq (m4or{3}, 1), 1, M4{3});
1022 let Inst{18} = !if (!eq (m4or{2}, 1), 1, M4{2});
1023 let Inst{17} = !if (!eq (m4or{1}, 1), 1, M4{1});
1024 let Inst{16} = !if (!eq (m4or{0}, 1), 1, M4{0});
1025 let Inst{15-12} = M3;
1026 let Inst{11} = V1{4};
1027 let Inst{10} = V2{4};
1029 let Inst{7-0} = op{7-0};
1032 // Depending on the instruction mnemonic, certain bits may be or-ed into
1033 // the M5 value provided as explicit operand. These are passed as m5or.
1034 class InstVRRb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern,
1036 : InstSystemZ<6, outs, ins, asmstr, pattern> {
1037 field bits<48> Inst;
1038 field bits<48> SoftFail = 0;
1046 let Inst{47-40} = op{15-8};
1047 let Inst{39-36} = V1{3-0};
1048 let Inst{35-32} = V2{3-0};
1049 let Inst{31-28} = V3{3-0};
1050 let Inst{27-24} = 0;
1051 let Inst{23} = !if (!eq (m5or{3}, 1), 1, M5{3});
1052 let Inst{22} = !if (!eq (m5or{2}, 1), 1, M5{2});
1053 let Inst{21} = !if (!eq (m5or{1}, 1), 1, M5{1});
1054 let Inst{20} = !if (!eq (m5or{0}, 1), 1, M5{0});
1055 let Inst{19-16} = 0;
1056 let Inst{15-12} = M4;
1057 let Inst{11} = V1{4};
1058 let Inst{10} = V2{4};
1059 let Inst{9} = V3{4};
1061 let Inst{7-0} = op{7-0};
1064 class InstVRRc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1065 : InstSystemZ<6, outs, ins, asmstr, pattern> {
1066 field bits<48> Inst;
1067 field bits<48> SoftFail = 0;
1076 let Inst{47-40} = op{15-8};
1077 let Inst{39-36} = V1{3-0};
1078 let Inst{35-32} = V2{3-0};
1079 let Inst{31-28} = V3{3-0};
1080 let Inst{27-24} = 0;
1081 let Inst{23-20} = M6;
1082 let Inst{19-16} = M5;
1083 let Inst{15-12} = M4;
1084 let Inst{11} = V1{4};
1085 let Inst{10} = V2{4};
1086 let Inst{9} = V3{4};
1088 let Inst{7-0} = op{7-0};
1091 // Depending on the instruction mnemonic, certain bits may be or-ed into
1092 // the M6 value provided as explicit operand. These are passed as m6or.
1093 class InstVRRd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern,
1095 : InstSystemZ<6, outs, ins, asmstr, pattern> {
1096 field bits<48> Inst;
1097 field bits<48> SoftFail = 0;
1106 let Inst{47-40} = op{15-8};
1107 let Inst{39-36} = V1{3-0};
1108 let Inst{35-32} = V2{3-0};
1109 let Inst{31-28} = V3{3-0};
1110 let Inst{27-24} = M5;
1111 let Inst{23} = !if (!eq (m6or{3}, 1), 1, M6{3});
1112 let Inst{22} = !if (!eq (m6or{2}, 1), 1, M6{2});
1113 let Inst{21} = !if (!eq (m6or{1}, 1), 1, M6{1});
1114 let Inst{20} = !if (!eq (m6or{0}, 1), 1, M6{0});
1115 let Inst{19-16} = 0;
1116 let Inst{15-12} = V4{3-0};
1117 let Inst{11} = V1{4};
1118 let Inst{10} = V2{4};
1119 let Inst{9} = V3{4};
1120 let Inst{8} = V4{4};
1121 let Inst{7-0} = op{7-0};
1124 class InstVRRe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1125 : InstSystemZ<6, outs, ins, asmstr, pattern> {
1126 field bits<48> Inst;
1127 field bits<48> SoftFail = 0;
1136 let Inst{47-40} = op{15-8};
1137 let Inst{39-36} = V1{3-0};
1138 let Inst{35-32} = V2{3-0};
1139 let Inst{31-28} = V3{3-0};
1140 let Inst{27-24} = M6;
1141 let Inst{23-20} = 0;
1142 let Inst{19-16} = M5;
1143 let Inst{15-12} = V4{3-0};
1144 let Inst{11} = V1{4};
1145 let Inst{10} = V2{4};
1146 let Inst{9} = V3{4};
1147 let Inst{8} = V4{4};
1148 let Inst{7-0} = op{7-0};
1151 class InstVRRf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1152 : InstSystemZ<6, outs, ins, asmstr, pattern> {
1153 field bits<48> Inst;
1154 field bits<48> SoftFail = 0;
1160 let Inst{47-40} = op{15-8};
1161 let Inst{39-36} = V1{3-0};
1162 let Inst{35-32} = R2;
1163 let Inst{31-28} = R3;
1164 let Inst{27-12} = 0;
1165 let Inst{11} = V1{4};
1167 let Inst{7-0} = op{7-0};
1170 class InstVRSa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1171 : InstSystemZ<6, outs, ins, asmstr, pattern> {
1172 field bits<48> Inst;
1173 field bits<48> SoftFail = 0;
1180 let Inst{47-40} = op{15-8};
1181 let Inst{39-36} = V1{3-0};
1182 let Inst{35-32} = V3{3-0};
1183 let Inst{31-16} = BD2;
1184 let Inst{15-12} = M4;
1185 let Inst{11} = V1{4};
1186 let Inst{10} = V3{4};
1188 let Inst{7-0} = op{7-0};
1191 class InstVRSb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1192 : InstSystemZ<6, outs, ins, asmstr, pattern> {
1193 field bits<48> Inst;
1194 field bits<48> SoftFail = 0;
1201 let Inst{47-40} = op{15-8};
1202 let Inst{39-36} = V1{3-0};
1203 let Inst{35-32} = R3;
1204 let Inst{31-16} = BD2;
1205 let Inst{15-12} = M4;
1206 let Inst{11} = V1{4};
1208 let Inst{7-0} = op{7-0};
1211 class InstVRSc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1212 : InstSystemZ<6, outs, ins, asmstr, pattern> {
1213 field bits<48> Inst;
1214 field bits<48> SoftFail = 0;
1221 let Inst{47-40} = op{15-8};
1222 let Inst{39-36} = R1;
1223 let Inst{35-32} = V3{3-0};
1224 let Inst{31-16} = BD2;
1225 let Inst{15-12} = M4;
1227 let Inst{10} = V3{4};
1229 let Inst{7-0} = op{7-0};
1232 class InstVRV<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1233 : InstSystemZ<6, outs, ins, asmstr, pattern> {
1234 field bits<48> Inst;
1235 field bits<48> SoftFail = 0;
1241 let Inst{47-40} = op{15-8};
1242 let Inst{39-36} = V1{3-0};
1243 let Inst{35-16} = VBD2{19-0};
1244 let Inst{15-12} = M3;
1245 let Inst{11} = V1{4};
1246 let Inst{10} = VBD2{20};
1248 let Inst{7-0} = op{7-0};
1251 class InstVRX<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1252 : InstSystemZ<6, outs, ins, asmstr, pattern> {
1253 field bits<48> Inst;
1254 field bits<48> SoftFail = 0;
1260 let Inst{47-40} = op{15-8};
1261 let Inst{39-36} = V1{3-0};
1262 let Inst{35-16} = XBD2;
1263 let Inst{15-12} = M3;
1264 let Inst{11} = V1{4};
1266 let Inst{7-0} = op{7-0};
1269 //===----------------------------------------------------------------------===//
1270 // Instruction classes for .insn directives
1271 //===----------------------------------------------------------------------===//
1273 class DirectiveInsnE<dag outs, dag ins, string asmstr, list<dag> pattern>
1274 : InstE<0, outs, ins, asmstr, pattern> {
1280 class DirectiveInsnRI<dag outs, dag ins, string asmstr, list<dag> pattern>
1281 : InstRIa<0, outs, ins, asmstr, pattern> {
1284 let Inst{31-24} = enc{31-24};
1285 let Inst{19-16} = enc{19-16};
1288 class DirectiveInsnRIE<dag outs, dag ins, string asmstr, list<dag> pattern>
1289 : InstRIEd<0, outs, ins, asmstr, pattern> {
1292 let Inst{47-40} = enc{47-40};
1293 let Inst{7-0} = enc{7-0};
1296 class DirectiveInsnRIL<dag outs, dag ins, string asmstr, list<dag> pattern>
1297 : InstRILa<0, outs, ins, asmstr, pattern> {
1301 let Inst{47-40} = enc{47-40};
1302 let Inst{35-32} = enc{35-32};
1305 class DirectiveInsnRIS<dag outs, dag ins, string asmstr, list<dag> pattern>
1306 : InstRIS<0, outs, ins, asmstr, pattern> {
1309 let Inst{47-40} = enc{47-40};
1310 let Inst{7-0} = enc{7-0};
1313 class DirectiveInsnRR<dag outs, dag ins, string asmstr, list<dag> pattern>
1314 : InstRR<0, outs, ins, asmstr, pattern> {
1317 let Inst{15-8} = enc{15-8};
1320 class DirectiveInsnRRE<dag outs, dag ins, string asmstr, list<dag> pattern>
1321 : InstRRE<0, outs, ins, asmstr, pattern> {
1324 let Inst{31-16} = enc{31-16};
1327 class DirectiveInsnRRF<dag outs, dag ins, string asmstr, list<dag> pattern>
1328 : InstRRFa<0, outs, ins, asmstr, pattern> {
1331 let Inst{31-16} = enc{31-16};
1334 class DirectiveInsnRRS<dag outs, dag ins, string asmstr, list<dag> pattern>
1335 : InstRRS<0, outs, ins, asmstr, pattern> {
1338 let Inst{47-40} = enc{47-40};
1339 let Inst{7-0} = enc{7-0};
1342 class DirectiveInsnRS<dag outs, dag ins, string asmstr, list<dag> pattern>
1343 : InstRSa<0, outs, ins, asmstr, pattern> {
1346 let Inst{31-24} = enc{31-24};
1349 // RSE is like RSY except with a 12 bit displacement (instead of 20).
1350 class DirectiveInsnRSE<dag outs, dag ins, string asmstr, list<dag> pattern>
1351 : InstRSYa<6, outs, ins, asmstr, pattern> {
1354 let Inst{47-40} = enc{47-40};
1355 let Inst{31-16} = BD2{15-0};
1357 let Inst{7-0} = enc{7-0};
1360 class DirectiveInsnRSI<dag outs, dag ins, string asmstr, list<dag> pattern>
1361 : InstRSI<0, outs, ins, asmstr, pattern> {
1364 let Inst{31-24} = enc{31-24};
1367 class DirectiveInsnRSY<dag outs, dag ins, string asmstr, list<dag> pattern>
1368 : InstRSYa<0, outs, ins, asmstr, pattern> {
1371 let Inst{47-40} = enc{47-40};
1372 let Inst{7-0} = enc{7-0};
1375 class DirectiveInsnRX<dag outs, dag ins, string asmstr, list<dag> pattern>
1376 : InstRXa<0, outs, ins, asmstr, pattern> {
1379 let Inst{31-24} = enc{31-24};
1382 class DirectiveInsnRXE<dag outs, dag ins, string asmstr, list<dag> pattern>
1383 : InstRXE<0, outs, ins, asmstr, pattern> {
1388 let Inst{47-40} = enc{47-40};
1389 let Inst{7-0} = enc{7-0};
1392 class DirectiveInsnRXF<dag outs, dag ins, string asmstr, list<dag> pattern>
1393 : InstRXF<0, outs, ins, asmstr, pattern> {
1396 let Inst{47-40} = enc{47-40};
1397 let Inst{7-0} = enc{7-0};
1400 class DirectiveInsnRXY<dag outs, dag ins, string asmstr, list<dag> pattern>
1401 : InstRXYa<0, outs, ins, asmstr, pattern> {
1404 let Inst{47-40} = enc{47-40};
1405 let Inst{7-0} = enc{7-0};
1408 class DirectiveInsnS<dag outs, dag ins, string asmstr, list<dag> pattern>
1409 : InstS<0, outs, ins, asmstr, pattern> {
1412 let Inst{31-16} = enc{31-16};
1415 class DirectiveInsnSI<dag outs, dag ins, string asmstr, list<dag> pattern>
1416 : InstSI<0, outs, ins, asmstr, pattern> {
1419 let Inst{31-24} = enc{31-24};
1422 class DirectiveInsnSIY<dag outs, dag ins, string asmstr, list<dag> pattern>
1423 : InstSIY<0, outs, ins, asmstr, pattern> {
1426 let Inst{47-40} = enc{47-40};
1427 let Inst{7-0} = enc{7-0};
1430 class DirectiveInsnSIL<dag outs, dag ins, string asmstr, list<dag> pattern>
1431 : InstSIL<0, outs, ins, asmstr, pattern> {
1434 let Inst{47-32} = enc{47-32};
1437 class DirectiveInsnSS<dag outs, dag ins, string asmstr, list<dag> pattern>
1438 : InstSSd<0, outs, ins, asmstr, pattern> {
1441 let Inst{47-40} = enc{47-40};
1444 class DirectiveInsnSSE<dag outs, dag ins, string asmstr, list<dag> pattern>
1445 : InstSSE<0, outs, ins, asmstr, pattern> {
1448 let Inst{47-32} = enc{47-32};
1451 class DirectiveInsnSSF<dag outs, dag ins, string asmstr, list<dag> pattern>
1452 : InstSSF<0, outs, ins, asmstr, pattern> {
1455 let Inst{47-40} = enc{47-40};
1456 let Inst{35-32} = enc{35-32};
1459 //===----------------------------------------------------------------------===//
1460 // Variants of instructions with condition mask
1461 //===----------------------------------------------------------------------===//
1463 // For instructions using a condition mask (e.g. conditional branches,
1464 // compare-and-branch instructions, or conditional move instructions),
1465 // we generally need to create multiple instruction patterns:
1467 // - One used for code generation, which encodes the condition mask as an
1468 // MI operand, but writes out an extended mnemonic for better readability.
1469 // - One pattern for the base form of the instruction with an explicit
1470 // condition mask (encoded as a plain integer MI operand).
1471 // - Specific patterns for each extended mnemonic, where the condition mask
1472 // is implied by the pattern name and not otherwise encoded at all.
1474 // We need the latter primarily for the assembler and disassembler, since the
1475 // assembler parser is not able to decode part of an instruction mnemonic
1476 // into an operand. Thus we provide separate patterns for each mnemonic.
1478 // Note that in some cases there are two different mnemonics for the same
1479 // condition mask. In this case we cannot have both instructions available
1480 // to the disassembler at the same time since the encodings are not distinct.
1481 // Therefore the alternate forms are marked isAsmParserOnly.
1483 // We don't make one of the two names an alias of the other because
1484 // we need the custom parsing routines to select the correct register class.
1486 // This section provides helpers for generating the specific forms.
1488 //===----------------------------------------------------------------------===//
1490 // A class to describe a variant of an instruction with condition mask.
1491 class CondVariant<bits<4> ccmaskin, string suffixin, bit alternatein> {
1492 // The fixed condition mask to use.
1493 bits<4> ccmask = ccmaskin;
1495 // The suffix to use for the extended assembler mnemonic.
1496 string suffix = suffixin;
1498 // Whether this is an alternate that needs to be marked isAsmParserOnly.
1499 bit alternate = alternatein;
1502 // Condition mask 15 means "always true", which is used to define
1503 // unconditional branches as a variant of conditional branches.
1504 def CondAlways : CondVariant<15, "", 0>;
1506 // Condition masks for general instructions that can set all 4 bits.
1507 def CondVariantO : CondVariant<1, "o", 0>;
1508 def CondVariantH : CondVariant<2, "h", 0>;
1509 def CondVariantP : CondVariant<2, "p", 1>;
1510 def CondVariantNLE : CondVariant<3, "nle", 0>;
1511 def CondVariantL : CondVariant<4, "l", 0>;
1512 def CondVariantM : CondVariant<4, "m", 1>;
1513 def CondVariantNHE : CondVariant<5, "nhe", 0>;
1514 def CondVariantLH : CondVariant<6, "lh", 0>;
1515 def CondVariantNE : CondVariant<7, "ne", 0>;
1516 def CondVariantNZ : CondVariant<7, "nz", 1>;
1517 def CondVariantE : CondVariant<8, "e", 0>;
1518 def CondVariantZ : CondVariant<8, "z", 1>;
1519 def CondVariantNLH : CondVariant<9, "nlh", 0>;
1520 def CondVariantHE : CondVariant<10, "he", 0>;
1521 def CondVariantNL : CondVariant<11, "nl", 0>;
1522 def CondVariantNM : CondVariant<11, "nm", 1>;
1523 def CondVariantLE : CondVariant<12, "le", 0>;
1524 def CondVariantNH : CondVariant<13, "nh", 0>;
1525 def CondVariantNP : CondVariant<13, "np", 1>;
1526 def CondVariantNO : CondVariant<14, "no", 0>;
1528 // A helper class to look up one of the above by name.
1529 class CV<string name>
1530 : CondVariant<!cast<CondVariant>("CondVariant"#name).ccmask,
1531 !cast<CondVariant>("CondVariant"#name).suffix,
1532 !cast<CondVariant>("CondVariant"#name).alternate>;
1534 // Condition masks for integer instructions (e.g. compare-and-branch).
1535 // This is like the list above, except that condition 3 is not possible
1536 // and that the low bit of the mask is therefore always 0. This means
1537 // that each condition has two names. Conditions "o" and "no" are not used.
1538 def IntCondVariantH : CondVariant<2, "h", 0>;
1539 def IntCondVariantNLE : CondVariant<2, "nle", 1>;
1540 def IntCondVariantL : CondVariant<4, "l", 0>;
1541 def IntCondVariantNHE : CondVariant<4, "nhe", 1>;
1542 def IntCondVariantLH : CondVariant<6, "lh", 0>;
1543 def IntCondVariantNE : CondVariant<6, "ne", 1>;
1544 def IntCondVariantE : CondVariant<8, "e", 0>;
1545 def IntCondVariantNLH : CondVariant<8, "nlh", 1>;
1546 def IntCondVariantHE : CondVariant<10, "he", 0>;
1547 def IntCondVariantNL : CondVariant<10, "nl", 1>;
1548 def IntCondVariantLE : CondVariant<12, "le", 0>;
1549 def IntCondVariantNH : CondVariant<12, "nh", 1>;
1551 // A helper class to look up one of the above by name.
1552 class ICV<string name>
1553 : CondVariant<!cast<CondVariant>("IntCondVariant"#name).ccmask,
1554 !cast<CondVariant>("IntCondVariant"#name).suffix,
1555 !cast<CondVariant>("IntCondVariant"#name).alternate>;
1557 //===----------------------------------------------------------------------===//
1558 // Instruction definitions with semantics
1559 //===----------------------------------------------------------------------===//
1561 // These classes have the form [Cond]<Category><Format>, where <Format> is one
1562 // of the formats defined above and where <Category> describes the inputs
1563 // and outputs. "Cond" is used if the instruction is conditional,
1564 // in which case the 4-bit condition-code mask is added as a final operand.
1565 // <Category> can be one of:
1568 // One register output operand and no input operands.
1571 // One address operand. The instruction stores to the address.
1573 // SideEffectInherent:
1574 // No input or output operands, but causes some side effect.
1577 // One branch target. The instruction branches to the target.
1580 // One output operand and one branch target. The instruction stores
1581 // the return address to the output operand and branches to the target.
1584 // Two input operands and one optional branch target. The instruction
1585 // compares the two input operands and branches or traps on the result.
1588 // One register output operand, one register input operand and one branch
1589 // target. The instructions stores a modified form of the source register
1590 // in the destination register and branches on the result.
1593 // One register output operand, two register input operands and one branch
1594 // target. The instructions stores a modified form of one of the source
1595 // registers in the destination register and branches on the result.
1598 // One address input operand and two explicit output operands.
1599 // The instruction loads a range of registers from the address,
1600 // with the explicit operands giving the first and last register
1601 // to load. Other loaded registers are added as implicit definitions.
1604 // Two explicit input register operands and an address operand.
1605 // The instruction stores a range of registers to the address,
1606 // with the explicit operands giving the first and last register
1607 // to store. Other stored registers are added as implicit uses.
1610 // One value operand, one length operand and one address operand.
1611 // The instruction stores the value operand to the address but
1612 // doesn't write more than the number of bytes specified by the
1616 // One register output operand and one address operand.
1618 // SideEffectAddress:
1619 // One address operand. No output operands, but causes some side effect.
1622 // One register output operand and one input operand.
1625 // One address operand and one other input operand. The instruction
1626 // stores to the address.
1629 // One input operand. No output operands, but causes some side effect.
1632 // One register output operand and two input operands.
1635 // One address operand and two other input operands. The instruction
1636 // stores to the address.
1638 // SideEffectBinary:
1639 // Two input operands. No output operands, but causes some side effect.
1642 // Two input operands and an implicit CC output operand.
1645 // Two input operands and an implicit CC output operand. The second
1646 // input operand is an "address" operand used as a test class mask.
1649 // One register output operand and three input operands.
1651 // SideEffectTernary:
1652 // Three input operands. No output operands, but causes some side effect.
1655 // One register output operand and four input operands.
1658 // One output operand and two input operands, one of which is an address.
1659 // The instruction both reads from and writes to the address.
1662 // One output operand and three input operands, one of which is an address.
1663 // The instruction both reads from and writes to the address.
1666 // One output operand and five input operands. The first two operands
1667 // are registers and the other three are immediates.
1670 // One 4-bit immediate operand and one address operand. The immediate
1671 // operand is 1 for a load prefetch and 2 for a store prefetch.
1674 // One 4-bit immediate operand and two address operands.
1676 // The format determines which input operands are tied to output operands,
1677 // and also determines the shape of any address operand.
1679 // Multiclasses of the form <Category><Format>Pair define two instructions,
1680 // one with <Category><Format> and one with <Category><Format>Y. The name
1681 // of the first instruction has no suffix, the name of the second has
1684 //===----------------------------------------------------------------------===//
1686 class InherentRRE<string mnemonic, bits<16> opcode, RegisterOperand cls,
1687 SDPatternOperator operator>
1688 : InstRRE<opcode, (outs cls:$R1), (ins),
1690 [(set cls:$R1, (operator))]> {
1694 class InherentVRIa<string mnemonic, bits<16> opcode, bits<16> value>
1695 : InstVRIa<opcode, (outs VR128:$V1), (ins), mnemonic#"\t$V1", []> {
1700 class StoreInherentS<string mnemonic, bits<16> opcode,
1701 SDPatternOperator operator, bits<5> bytes>
1702 : InstS<opcode, (outs), (ins bdaddr12only:$BD2),
1703 mnemonic#"\t$BD2", [(operator bdaddr12only:$BD2)]> {
1705 let AccessBytes = bytes;
1708 class SideEffectInherentE<string mnemonic, bits<16>opcode>
1709 : InstE<opcode, (outs), (ins), mnemonic, []>;
1711 class SideEffectInherentS<string mnemonic, bits<16> opcode,
1712 SDPatternOperator operator>
1713 : InstS<opcode, (outs), (ins), mnemonic, [(operator)]> {
1717 // Allow an optional TLS marker symbol to generate TLS call relocations.
1718 class CallRI<string mnemonic, bits<12> opcode>
1719 : InstRIb<opcode, (outs), (ins GR64:$R1, brtarget16tls:$RI2),
1720 mnemonic#"\t$R1, $RI2", []>;
1722 // Allow an optional TLS marker symbol to generate TLS call relocations.
1723 class CallRIL<string mnemonic, bits<12> opcode>
1724 : InstRILb<opcode, (outs), (ins GR64:$R1, brtarget32tls:$RI2),
1725 mnemonic#"\t$R1, $RI2", []>;
1727 class CallRR<string mnemonic, bits<8> opcode>
1728 : InstRR<opcode, (outs), (ins GR64:$R1, ADDR64:$R2),
1729 mnemonic#"\t$R1, $R2", []>;
1731 class CallRX<string mnemonic, bits<8> opcode>
1732 : InstRXa<opcode, (outs), (ins GR64:$R1, bdxaddr12only:$XBD2),
1733 mnemonic#"\t$R1, $XBD2", []>;
1735 class CondBranchRI<string mnemonic, bits<12> opcode,
1736 SDPatternOperator operator = null_frag>
1737 : InstRIc<opcode, (outs), (ins cond4:$valid, cond4:$M1, brtarget16:$RI2),
1738 !subst("#", "${M1}", mnemonic)#"\t$RI2",
1739 [(operator cond4:$valid, cond4:$M1, bb:$RI2)]> {
1740 let CCMaskFirst = 1;
1743 class AsmCondBranchRI<string mnemonic, bits<12> opcode>
1744 : InstRIc<opcode, (outs), (ins imm32zx4:$M1, brtarget16:$RI2),
1745 mnemonic#"\t$M1, $RI2", []>;
1747 class FixedCondBranchRI<CondVariant V, string mnemonic, bits<12> opcode,
1748 SDPatternOperator operator = null_frag>
1749 : InstRIc<opcode, (outs), (ins brtarget16:$RI2),
1750 !subst("#", V.suffix, mnemonic)#"\t$RI2", [(operator bb:$RI2)]> {
1751 let isAsmParserOnly = V.alternate;
1755 class CondBranchRIL<string mnemonic, bits<12> opcode>
1756 : InstRILc<opcode, (outs), (ins cond4:$valid, cond4:$M1, brtarget32:$RI2),
1757 !subst("#", "${M1}", mnemonic)#"\t$RI2", []> {
1758 let CCMaskFirst = 1;
1761 class AsmCondBranchRIL<string mnemonic, bits<12> opcode>
1762 : InstRILc<opcode, (outs), (ins imm32zx4:$M1, brtarget32:$RI2),
1763 mnemonic#"\t$M1, $RI2", []>;
1765 class FixedCondBranchRIL<CondVariant V, string mnemonic, bits<12> opcode>
1766 : InstRILc<opcode, (outs), (ins brtarget32:$RI2),
1767 !subst("#", V.suffix, mnemonic)#"\t$RI2", []> {
1768 let isAsmParserOnly = V.alternate;
1772 class CondBranchRR<string mnemonic, bits<8> opcode>
1773 : InstRR<opcode, (outs), (ins cond4:$valid, cond4:$R1, GR64:$R2),
1774 !subst("#", "${R1}", mnemonic)#"\t$R2", []> {
1775 let CCMaskFirst = 1;
1778 class AsmCondBranchRR<string mnemonic, bits<8> opcode>
1779 : InstRR<opcode, (outs), (ins imm32zx4:$R1, GR64:$R2),
1780 mnemonic#"\t$R1, $R2", []>;
1782 class FixedCondBranchRR<CondVariant V, string mnemonic, bits<8> opcode,
1783 SDPatternOperator operator = null_frag>
1784 : InstRR<opcode, (outs), (ins ADDR64:$R2),
1785 !subst("#", V.suffix, mnemonic)#"\t$R2", [(operator ADDR64:$R2)]> {
1786 let isAsmParserOnly = V.alternate;
1790 class CondBranchRX<string mnemonic, bits<8> opcode>
1791 : InstRXb<opcode, (outs), (ins cond4:$valid, cond4:$M1, bdxaddr12only:$XBD2),
1792 !subst("#", "${M1}", mnemonic)#"\t$XBD2", []> {
1793 let CCMaskFirst = 1;
1796 class AsmCondBranchRX<string mnemonic, bits<8> opcode>
1797 : InstRXb<opcode, (outs), (ins imm32zx4:$M1, bdxaddr12only:$XBD2),
1798 mnemonic#"\t$M1, $XBD2", []>;
1800 class FixedCondBranchRX<CondVariant V, string mnemonic, bits<8> opcode>
1801 : InstRXb<opcode, (outs), (ins bdxaddr12only:$XBD2),
1802 !subst("#", V.suffix, mnemonic)#"\t$XBD2", []> {
1803 let isAsmParserOnly = V.alternate;
1807 class CmpBranchRIEa<string mnemonic, bits<16> opcode,
1808 RegisterOperand cls, Immediate imm>
1809 : InstRIEa<opcode, (outs), (ins cls:$R1, imm:$I2, cond4:$M3),
1810 mnemonic#"$M3\t$R1, $I2", []>;
1812 class AsmCmpBranchRIEa<string mnemonic, bits<16> opcode,
1813 RegisterOperand cls, Immediate imm>
1814 : InstRIEa<opcode, (outs), (ins cls:$R1, imm:$I2, imm32zx4:$M3),
1815 mnemonic#"\t$R1, $I2, $M3", []>;
1817 class FixedCmpBranchRIEa<CondVariant V, string mnemonic, bits<16> opcode,
1818 RegisterOperand cls, Immediate imm>
1819 : InstRIEa<opcode, (outs), (ins cls:$R1, imm:$I2),
1820 mnemonic#V.suffix#"\t$R1, $I2", []> {
1821 let isAsmParserOnly = V.alternate;
1825 multiclass CmpBranchRIEaPair<string mnemonic, bits<16> opcode,
1826 RegisterOperand cls, Immediate imm> {
1827 let isCodeGenOnly = 1 in
1828 def "" : CmpBranchRIEa<mnemonic, opcode, cls, imm>;
1829 def Asm : AsmCmpBranchRIEa<mnemonic, opcode, cls, imm>;
1832 class CmpBranchRIEb<string mnemonic, bits<16> opcode,
1833 RegisterOperand cls>
1834 : InstRIEb<opcode, (outs),
1835 (ins cls:$R1, cls:$R2, cond4:$M3, brtarget16:$RI4),
1836 mnemonic#"$M3\t$R1, $R2, $RI4", []>;
1838 class AsmCmpBranchRIEb<string mnemonic, bits<16> opcode,
1839 RegisterOperand cls>
1840 : InstRIEb<opcode, (outs),
1841 (ins cls:$R1, cls:$R2, imm32zx4:$M3, brtarget16:$RI4),
1842 mnemonic#"\t$R1, $R2, $M3, $RI4", []>;
1844 class FixedCmpBranchRIEb<CondVariant V, string mnemonic, bits<16> opcode,
1845 RegisterOperand cls>
1846 : InstRIEb<opcode, (outs), (ins cls:$R1, cls:$R2, brtarget16:$RI4),
1847 mnemonic#V.suffix#"\t$R1, $R2, $RI4", []> {
1848 let isAsmParserOnly = V.alternate;
1852 multiclass CmpBranchRIEbPair<string mnemonic, bits<16> opcode,
1853 RegisterOperand cls> {
1854 let isCodeGenOnly = 1 in
1855 def "" : CmpBranchRIEb<mnemonic, opcode, cls>;
1856 def Asm : AsmCmpBranchRIEb<mnemonic, opcode, cls>;
1859 class CmpBranchRIEc<string mnemonic, bits<16> opcode,
1860 RegisterOperand cls, Immediate imm>
1861 : InstRIEc<opcode, (outs),
1862 (ins cls:$R1, imm:$I2, cond4:$M3, brtarget16:$RI4),
1863 mnemonic#"$M3\t$R1, $I2, $RI4", []>;
1865 class AsmCmpBranchRIEc<string mnemonic, bits<16> opcode,
1866 RegisterOperand cls, Immediate imm>
1867 : InstRIEc<opcode, (outs),
1868 (ins cls:$R1, imm:$I2, imm32zx4:$M3, brtarget16:$RI4),
1869 mnemonic#"\t$R1, $I2, $M3, $RI4", []>;
1871 class FixedCmpBranchRIEc<CondVariant V, string mnemonic, bits<16> opcode,
1872 RegisterOperand cls, Immediate imm>
1873 : InstRIEc<opcode, (outs), (ins cls:$R1, imm:$I2, brtarget16:$RI4),
1874 mnemonic#V.suffix#"\t$R1, $I2, $RI4", []> {
1875 let isAsmParserOnly = V.alternate;
1879 multiclass CmpBranchRIEcPair<string mnemonic, bits<16> opcode,
1880 RegisterOperand cls, Immediate imm> {
1881 let isCodeGenOnly = 1 in
1882 def "" : CmpBranchRIEc<mnemonic, opcode, cls, imm>;
1883 def Asm : AsmCmpBranchRIEc<mnemonic, opcode, cls, imm>;
1886 class CmpBranchRRFc<string mnemonic, bits<16> opcode,
1887 RegisterOperand cls>
1888 : InstRRFc<opcode, (outs), (ins cls:$R1, cls:$R2, cond4:$M3),
1889 mnemonic#"$M3\t$R1, $R2", []>;
1891 class AsmCmpBranchRRFc<string mnemonic, bits<16> opcode,
1892 RegisterOperand cls>
1893 : InstRRFc<opcode, (outs), (ins cls:$R1, cls:$R2, imm32zx4:$M3),
1894 mnemonic#"\t$R1, $R2, $M3", []>;
1896 multiclass CmpBranchRRFcPair<string mnemonic, bits<16> opcode,
1897 RegisterOperand cls> {
1898 let isCodeGenOnly = 1 in
1899 def "" : CmpBranchRRFc<mnemonic, opcode, cls>;
1900 def Asm : AsmCmpBranchRRFc<mnemonic, opcode, cls>;
1903 class FixedCmpBranchRRFc<CondVariant V, string mnemonic, bits<16> opcode,
1904 RegisterOperand cls>
1905 : InstRRFc<opcode, (outs), (ins cls:$R1, cls:$R2),
1906 mnemonic#V.suffix#"\t$R1, $R2", []> {
1907 let isAsmParserOnly = V.alternate;
1911 class CmpBranchRRS<string mnemonic, bits<16> opcode,
1912 RegisterOperand cls>
1913 : InstRRS<opcode, (outs),
1914 (ins cls:$R1, cls:$R2, cond4:$M3, bdaddr12only:$BD4),
1915 mnemonic#"$M3\t$R1, $R2, $BD4", []>;
1917 class AsmCmpBranchRRS<string mnemonic, bits<16> opcode,
1918 RegisterOperand cls>
1919 : InstRRS<opcode, (outs),
1920 (ins cls:$R1, cls:$R2, imm32zx4:$M3, bdaddr12only:$BD4),
1921 mnemonic#"\t$R1, $R2, $M3, $BD4", []>;
1923 class FixedCmpBranchRRS<CondVariant V, string mnemonic, bits<16> opcode,
1924 RegisterOperand cls>
1925 : InstRRS<opcode, (outs), (ins cls:$R1, cls:$R2, bdaddr12only:$BD4),
1926 mnemonic#V.suffix#"\t$R1, $R2, $BD4", []> {
1927 let isAsmParserOnly = V.alternate;
1931 multiclass CmpBranchRRSPair<string mnemonic, bits<16> opcode,
1932 RegisterOperand cls> {
1933 let isCodeGenOnly = 1 in
1934 def "" : CmpBranchRRS<mnemonic, opcode, cls>;
1935 def Asm : AsmCmpBranchRRS<mnemonic, opcode, cls>;
1938 class CmpBranchRIS<string mnemonic, bits<16> opcode,
1939 RegisterOperand cls, Immediate imm>
1940 : InstRIS<opcode, (outs),
1941 (ins cls:$R1, imm:$I2, cond4:$M3, bdaddr12only:$BD4),
1942 mnemonic#"$M3\t$R1, $I2, $BD4", []>;
1944 class AsmCmpBranchRIS<string mnemonic, bits<16> opcode,
1945 RegisterOperand cls, Immediate imm>
1946 : InstRIS<opcode, (outs),
1947 (ins cls:$R1, imm:$I2, imm32zx4:$M3, bdaddr12only:$BD4),
1948 mnemonic#"\t$R1, $I2, $M3, $BD4", []>;
1950 class FixedCmpBranchRIS<CondVariant V, string mnemonic, bits<16> opcode,
1951 RegisterOperand cls, Immediate imm>
1952 : InstRIS<opcode, (outs), (ins cls:$R1, imm:$I2, bdaddr12only:$BD4),
1953 mnemonic#V.suffix#"\t$R1, $I2, $BD4", []> {
1954 let isAsmParserOnly = V.alternate;
1958 multiclass CmpBranchRISPair<string mnemonic, bits<16> opcode,
1959 RegisterOperand cls, Immediate imm> {
1960 let isCodeGenOnly = 1 in
1961 def "" : CmpBranchRIS<mnemonic, opcode, cls, imm>;
1962 def Asm : AsmCmpBranchRIS<mnemonic, opcode, cls, imm>;
1965 class CmpBranchRSYb<string mnemonic, bits<16> opcode,
1966 RegisterOperand cls>
1967 : InstRSYb<opcode, (outs), (ins cls:$R1, bdaddr20only:$BD2, cond4:$M3),
1968 mnemonic#"$M3\t$R1, $BD2", []>;
1970 class AsmCmpBranchRSYb<string mnemonic, bits<16> opcode,
1971 RegisterOperand cls>
1972 : InstRSYb<opcode, (outs), (ins cls:$R1, bdaddr20only:$BD2, imm32zx4:$M3),
1973 mnemonic#"\t$R1, $M3, $BD2", []>;
1975 multiclass CmpBranchRSYbPair<string mnemonic, bits<16> opcode,
1976 RegisterOperand cls> {
1977 let isCodeGenOnly = 1 in
1978 def "" : CmpBranchRSYb<mnemonic, opcode, cls>;
1979 def Asm : AsmCmpBranchRSYb<mnemonic, opcode, cls>;
1982 class FixedCmpBranchRSYb<CondVariant V, string mnemonic, bits<16> opcode,
1983 RegisterOperand cls>
1984 : InstRSYb<opcode, (outs), (ins cls:$R1, bdaddr20only:$BD2),
1985 mnemonic#V.suffix#"\t$R1, $BD2", []> {
1986 let isAsmParserOnly = V.alternate;
1990 class BranchUnaryRI<string mnemonic, bits<12> opcode, RegisterOperand cls>
1991 : InstRIb<opcode, (outs cls:$R1), (ins cls:$R1src, brtarget16:$RI2),
1992 mnemonic##"\t$R1, $RI2", []> {
1993 let Constraints = "$R1 = $R1src";
1994 let DisableEncoding = "$R1src";
1997 class BranchUnaryRIL<string mnemonic, bits<12> opcode, RegisterOperand cls>
1998 : InstRILb<opcode, (outs cls:$R1), (ins cls:$R1src, brtarget32:$RI2),
1999 mnemonic##"\t$R1, $RI2", []> {
2000 let Constraints = "$R1 = $R1src";
2001 let DisableEncoding = "$R1src";
2004 class BranchUnaryRR<string mnemonic, bits<8> opcode, RegisterOperand cls>
2005 : InstRR<opcode, (outs cls:$R1), (ins cls:$R1src, GR64:$R2),
2006 mnemonic##"\t$R1, $R2", []> {
2007 let Constraints = "$R1 = $R1src";
2008 let DisableEncoding = "$R1src";
2011 class BranchUnaryRRE<string mnemonic, bits<16> opcode, RegisterOperand cls>
2012 : InstRRE<opcode, (outs cls:$R1), (ins cls:$R1src, GR64:$R2),
2013 mnemonic##"\t$R1, $R2", []> {
2014 let Constraints = "$R1 = $R1src";
2015 let DisableEncoding = "$R1src";
2018 class BranchUnaryRX<string mnemonic, bits<8> opcode, RegisterOperand cls>
2019 : InstRXa<opcode, (outs cls:$R1), (ins cls:$R1src, bdxaddr12only:$XBD2),
2020 mnemonic##"\t$R1, $XBD2", []> {
2021 let Constraints = "$R1 = $R1src";
2022 let DisableEncoding = "$R1src";
2025 class BranchUnaryRXY<string mnemonic, bits<16> opcode, RegisterOperand cls>
2026 : InstRXYa<opcode, (outs cls:$R1), (ins cls:$R1src, bdxaddr20only:$XBD2),
2027 mnemonic##"\t$R1, $XBD2", []> {
2028 let Constraints = "$R1 = $R1src";
2029 let DisableEncoding = "$R1src";
2032 class BranchBinaryRSI<string mnemonic, bits<8> opcode, RegisterOperand cls>
2033 : InstRSI<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, brtarget16:$RI2),
2034 mnemonic##"\t$R1, $R3, $RI2", []> {
2035 let Constraints = "$R1 = $R1src";
2036 let DisableEncoding = "$R1src";
2039 class BranchBinaryRIEe<string mnemonic, bits<16> opcode, RegisterOperand cls>
2040 : InstRIEe<opcode, (outs cls:$R1),
2041 (ins cls:$R1src, cls:$R3, brtarget16:$RI2),
2042 mnemonic##"\t$R1, $R3, $RI2", []> {
2043 let Constraints = "$R1 = $R1src";
2044 let DisableEncoding = "$R1src";
2047 class BranchBinaryRS<string mnemonic, bits<8> opcode, RegisterOperand cls>
2048 : InstRSa<opcode, (outs cls:$R1),
2049 (ins cls:$R1src, cls:$R3, bdaddr12only:$BD2),
2050 mnemonic##"\t$R1, $R3, $BD2", []> {
2051 let Constraints = "$R1 = $R1src";
2052 let DisableEncoding = "$R1src";
2055 class BranchBinaryRSY<string mnemonic, bits<16> opcode, RegisterOperand cls>
2057 (outs cls:$R1), (ins cls:$R1src, cls:$R3, bdaddr20only:$BD2),
2058 mnemonic##"\t$R1, $R3, $BD2", []> {
2059 let Constraints = "$R1 = $R1src";
2060 let DisableEncoding = "$R1src";
2063 class LoadMultipleRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
2064 AddressingMode mode = bdaddr12only>
2065 : InstRSa<opcode, (outs cls:$R1, cls:$R3), (ins mode:$BD2),
2066 mnemonic#"\t$R1, $R3, $BD2", []> {
2070 class LoadMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
2071 AddressingMode mode = bdaddr20only>
2072 : InstRSYa<opcode, (outs cls:$R1, cls:$R3), (ins mode:$BD2),
2073 mnemonic#"\t$R1, $R3, $BD2", []> {
2077 multiclass LoadMultipleRSPair<string mnemonic, bits<8> rsOpcode,
2078 bits<16> rsyOpcode, RegisterOperand cls> {
2079 let DispKey = mnemonic ## #cls in {
2080 let DispSize = "12" in
2081 def "" : LoadMultipleRS<mnemonic, rsOpcode, cls, bdaddr12pair>;
2082 let DispSize = "20" in
2083 def Y : LoadMultipleRSY<mnemonic#"y", rsyOpcode, cls, bdaddr20pair>;
2087 class LoadMultipleVRSa<string mnemonic, bits<16> opcode>
2088 : InstVRSa<opcode, (outs VR128:$V1, VR128:$V3), (ins bdaddr12only:$BD2),
2089 mnemonic#"\t$V1, $V3, $BD2", []> {
2094 class StoreRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator,
2095 RegisterOperand cls>
2096 : InstRILb<opcode, (outs), (ins cls:$R1, pcrel32:$RI2),
2097 mnemonic#"\t$R1, $RI2",
2098 [(operator cls:$R1, pcrel32:$RI2)]> {
2100 // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
2101 // However, BDXs have two extra operands and are therefore 6 units more
2103 let AddedComplexity = 7;
2106 class StoreRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
2107 RegisterOperand cls, bits<5> bytes,
2108 AddressingMode mode = bdxaddr12only>
2109 : InstRXa<opcode, (outs), (ins cls:$R1, mode:$XBD2),
2110 mnemonic#"\t$R1, $XBD2",
2111 [(operator cls:$R1, mode:$XBD2)]> {
2112 let OpKey = mnemonic#"r"#cls;
2115 let AccessBytes = bytes;
2118 class StoreRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2119 RegisterOperand cls, bits<5> bytes,
2120 AddressingMode mode = bdxaddr20only>
2121 : InstRXYa<opcode, (outs), (ins cls:$R1, mode:$XBD2),
2122 mnemonic#"\t$R1, $XBD2",
2123 [(operator cls:$R1, mode:$XBD2)]> {
2124 let OpKey = mnemonic#"r"#cls;
2127 let AccessBytes = bytes;
2130 multiclass StoreRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
2131 SDPatternOperator operator, RegisterOperand cls,
2133 let DispKey = mnemonic ## #cls in {
2134 let DispSize = "12" in
2135 def "" : StoreRX<mnemonic, rxOpcode, operator, cls, bytes, bdxaddr12pair>;
2136 let DispSize = "20" in
2137 def Y : StoreRXY<mnemonic#"y", rxyOpcode, operator, cls, bytes,
2142 class StoreVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2143 TypedReg tr, bits<5> bytes, bits<4> type = 0>
2144 : InstVRX<opcode, (outs), (ins tr.op:$V1, bdxaddr12only:$XBD2),
2145 mnemonic#"\t$V1, $XBD2",
2146 [(set tr.op:$V1, (tr.vt (operator bdxaddr12only:$XBD2)))]> {
2149 let AccessBytes = bytes;
2152 class StoreLengthVRSb<string mnemonic, bits<16> opcode,
2153 SDPatternOperator operator, bits<5> bytes>
2154 : InstVRSb<opcode, (outs), (ins VR128:$V1, GR32:$R3, bdaddr12only:$BD2),
2155 mnemonic#"\t$V1, $R3, $BD2",
2156 [(operator VR128:$V1, GR32:$R3, bdaddr12only:$BD2)]> {
2159 let AccessBytes = bytes;
2162 class StoreMultipleRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
2163 AddressingMode mode = bdaddr12only>
2164 : InstRSa<opcode, (outs), (ins cls:$R1, cls:$R3, mode:$BD2),
2165 mnemonic#"\t$R1, $R3, $BD2", []> {
2169 class StoreMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
2170 AddressingMode mode = bdaddr20only>
2171 : InstRSYa<opcode, (outs), (ins cls:$R1, cls:$R3, mode:$BD2),
2172 mnemonic#"\t$R1, $R3, $BD2", []> {
2176 multiclass StoreMultipleRSPair<string mnemonic, bits<8> rsOpcode,
2177 bits<16> rsyOpcode, RegisterOperand cls> {
2178 let DispKey = mnemonic ## #cls in {
2179 let DispSize = "12" in
2180 def "" : StoreMultipleRS<mnemonic, rsOpcode, cls, bdaddr12pair>;
2181 let DispSize = "20" in
2182 def Y : StoreMultipleRSY<mnemonic#"y", rsyOpcode, cls, bdaddr20pair>;
2186 class StoreMultipleVRSa<string mnemonic, bits<16> opcode>
2187 : InstVRSa<opcode, (outs), (ins VR128:$V1, VR128:$V3, bdaddr12only:$BD2),
2188 mnemonic#"\t$V1, $V3, $BD2", []> {
2193 // StoreSI* instructions are used to store an integer to memory, but the
2194 // addresses are more restricted than for normal stores. If we are in the
2195 // situation of having to force either the address into a register or the
2196 // constant into a register, it's usually better to do the latter.
2197 // We therefore match the address in the same way as a normal store and
2198 // only use the StoreSI* instruction if the matched address is suitable.
2199 class StoreSI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
2201 : InstSI<opcode, (outs), (ins mviaddr12pair:$BD1, imm:$I2),
2202 mnemonic#"\t$BD1, $I2",
2203 [(operator imm:$I2, mviaddr12pair:$BD1)]> {
2207 class StoreSIY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2209 : InstSIY<opcode, (outs), (ins mviaddr20pair:$BD1, imm:$I2),
2210 mnemonic#"\t$BD1, $I2",
2211 [(operator imm:$I2, mviaddr20pair:$BD1)]> {
2215 class StoreSIL<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2217 : InstSIL<opcode, (outs), (ins mviaddr12pair:$BD1, imm:$I2),
2218 mnemonic#"\t$BD1, $I2",
2219 [(operator imm:$I2, mviaddr12pair:$BD1)]> {
2223 multiclass StoreSIPair<string mnemonic, bits<8> siOpcode, bits<16> siyOpcode,
2224 SDPatternOperator operator, Immediate imm> {
2225 let DispKey = mnemonic in {
2226 let DispSize = "12" in
2227 def "" : StoreSI<mnemonic, siOpcode, operator, imm>;
2228 let DispSize = "20" in
2229 def Y : StoreSIY<mnemonic#"y", siyOpcode, operator, imm>;
2233 class StoreSSE<string mnemonic, bits<16> opcode>
2234 : InstSSE<opcode, (outs), (ins bdaddr12only:$BD1, bdaddr12only:$BD2),
2235 mnemonic#"\t$BD1, $BD2", []> {
2239 class CondStoreRSY<string mnemonic, bits<16> opcode,
2240 RegisterOperand cls, bits<5> bytes,
2241 AddressingMode mode = bdaddr20only>
2242 : InstRSYb<opcode, (outs), (ins cls:$R1, mode:$BD2, cond4:$valid, cond4:$M3),
2243 mnemonic#"$M3\t$R1, $BD2", []> {
2245 let AccessBytes = bytes;
2249 // Like CondStoreRSY, but used for the raw assembly form. The condition-code
2250 // mask is the third operand rather than being part of the mnemonic.
2251 class AsmCondStoreRSY<string mnemonic, bits<16> opcode,
2252 RegisterOperand cls, bits<5> bytes,
2253 AddressingMode mode = bdaddr20only>
2254 : InstRSYb<opcode, (outs), (ins cls:$R1, mode:$BD2, imm32zx4:$M3),
2255 mnemonic#"\t$R1, $BD2, $M3", []> {
2257 let AccessBytes = bytes;
2260 // Like CondStoreRSY, but with a fixed CC mask.
2261 class FixedCondStoreRSY<CondVariant V, string mnemonic, bits<16> opcode,
2262 RegisterOperand cls, bits<5> bytes,
2263 AddressingMode mode = bdaddr20only>
2264 : InstRSYb<opcode, (outs), (ins cls:$R1, mode:$BD2),
2265 mnemonic#V.suffix#"\t$R1, $BD2", []> {
2267 let AccessBytes = bytes;
2268 let isAsmParserOnly = V.alternate;
2272 multiclass CondStoreRSYPair<string mnemonic, bits<16> opcode,
2273 RegisterOperand cls, bits<5> bytes,
2274 AddressingMode mode = bdaddr20only> {
2275 let isCodeGenOnly = 1 in
2276 def "" : CondStoreRSY<mnemonic, opcode, cls, bytes, mode>;
2277 def Asm : AsmCondStoreRSY<mnemonic, opcode, cls, bytes, mode>;
2280 class SideEffectUnaryI<string mnemonic, bits<8> opcode, Immediate imm>
2281 : InstI<opcode, (outs), (ins imm:$I1),
2282 mnemonic#"\t$I1", []>;
2284 class SideEffectUnaryRR<string mnemonic, bits<8>opcode, RegisterOperand cls>
2285 : InstRR<opcode, (outs), (ins cls:$R1),
2286 mnemonic#"\t$R1", []> {
2290 class SideEffectUnaryRRE<string mnemonic, bits<16> opcode, RegisterOperand cls,
2291 SDPatternOperator operator>
2292 : InstRRE<opcode, (outs), (ins cls:$R1),
2293 mnemonic#"\t$R1", [(operator cls:$R1)]> {
2297 class SideEffectUnaryS<string mnemonic, bits<16> opcode,
2298 SDPatternOperator operator, bits<5> bytes,
2299 AddressingMode mode = bdaddr12only>
2300 : InstS<opcode, (outs), (ins mode:$BD2),
2301 mnemonic#"\t$BD2", [(operator mode:$BD2)]> {
2303 let AccessBytes = bytes;
2306 class SideEffectAddressS<string mnemonic, bits<16> opcode,
2307 SDPatternOperator operator,
2308 AddressingMode mode = bdaddr12only>
2309 : InstS<opcode, (outs), (ins mode:$BD2),
2310 mnemonic#"\t$BD2", [(operator mode:$BD2)]>;
2312 class LoadAddressRX<string mnemonic, bits<8> opcode,
2313 SDPatternOperator operator, AddressingMode mode>
2314 : InstRXa<opcode, (outs GR64:$R1), (ins mode:$XBD2),
2315 mnemonic#"\t$R1, $XBD2",
2316 [(set GR64:$R1, (operator mode:$XBD2))]>;
2318 class LoadAddressRXY<string mnemonic, bits<16> opcode,
2319 SDPatternOperator operator, AddressingMode mode>
2320 : InstRXYa<opcode, (outs GR64:$R1), (ins mode:$XBD2),
2321 mnemonic#"\t$R1, $XBD2",
2322 [(set GR64:$R1, (operator mode:$XBD2))]>;
2324 multiclass LoadAddressRXPair<string mnemonic, bits<8> rxOpcode,
2325 bits<16> rxyOpcode, SDPatternOperator operator> {
2326 let DispKey = mnemonic in {
2327 let DispSize = "12" in
2328 def "" : LoadAddressRX<mnemonic, rxOpcode, operator, laaddr12pair>;
2329 let DispSize = "20" in
2330 def Y : LoadAddressRXY<mnemonic#"y", rxyOpcode, operator, laaddr20pair>;
2334 class LoadAddressRIL<string mnemonic, bits<12> opcode,
2335 SDPatternOperator operator>
2336 : InstRILb<opcode, (outs GR64:$R1), (ins pcrel32:$RI2),
2337 mnemonic#"\t$R1, $RI2",
2338 [(set GR64:$R1, (operator pcrel32:$RI2))]>;
2340 class UnaryRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
2341 RegisterOperand cls1, RegisterOperand cls2>
2342 : InstRR<opcode, (outs cls1:$R1), (ins cls2:$R2),
2343 mnemonic#"\t$R1, $R2",
2344 [(set cls1:$R1, (operator cls2:$R2))]> {
2345 let OpKey = mnemonic#cls1;
2349 class UnaryRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2350 RegisterOperand cls1, RegisterOperand cls2>
2351 : InstRRE<opcode, (outs cls1:$R1), (ins cls2:$R2),
2352 mnemonic#"\t$R1, $R2",
2353 [(set cls1:$R1, (operator cls2:$R2))]> {
2354 let OpKey = mnemonic#cls1;
2358 class UnaryRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
2359 RegisterOperand cls, Immediate imm>
2360 : InstRIa<opcode, (outs cls:$R1), (ins imm:$I2),
2361 mnemonic#"\t$R1, $I2",
2362 [(set cls:$R1, (operator imm:$I2))]>;
2364 class UnaryRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator,
2365 RegisterOperand cls, Immediate imm>
2366 : InstRILa<opcode, (outs cls:$R1), (ins imm:$I2),
2367 mnemonic#"\t$R1, $I2",
2368 [(set cls:$R1, (operator imm:$I2))]>;
2370 class UnaryRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator,
2371 RegisterOperand cls>
2372 : InstRILb<opcode, (outs cls:$R1), (ins pcrel32:$RI2),
2373 mnemonic#"\t$R1, $RI2",
2374 [(set cls:$R1, (operator pcrel32:$RI2))]> {
2376 // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
2377 // However, BDXs have two extra operands and are therefore 6 units more
2379 let AddedComplexity = 7;
2382 class CondUnaryRSY<string mnemonic, bits<16> opcode,
2383 SDPatternOperator operator, RegisterOperand cls,
2384 bits<5> bytes, AddressingMode mode = bdaddr20only>
2385 : InstRSYb<opcode, (outs cls:$R1),
2386 (ins cls:$R1src, mode:$BD2, cond4:$valid, cond4:$M3),
2387 mnemonic#"$M3\t$R1, $BD2",
2389 (z_select_ccmask (operator bdaddr20only:$BD2), cls:$R1src,
2390 cond4:$valid, cond4:$M3))]> {
2391 let Constraints = "$R1 = $R1src";
2392 let DisableEncoding = "$R1src";
2394 let AccessBytes = bytes;
2398 // Like CondUnaryRSY, but used for the raw assembly form. The condition-code
2399 // mask is the third operand rather than being part of the mnemonic.
2400 class AsmCondUnaryRSY<string mnemonic, bits<16> opcode,
2401 RegisterOperand cls, bits<5> bytes,
2402 AddressingMode mode = bdaddr20only>
2403 : InstRSYb<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$BD2, imm32zx4:$M3),
2404 mnemonic#"\t$R1, $BD2, $M3", []> {
2406 let AccessBytes = bytes;
2407 let Constraints = "$R1 = $R1src";
2408 let DisableEncoding = "$R1src";
2411 // Like CondUnaryRSY, but with a fixed CC mask.
2412 class FixedCondUnaryRSY<CondVariant V, string mnemonic, bits<16> opcode,
2413 RegisterOperand cls, bits<5> bytes,
2414 AddressingMode mode = bdaddr20only>
2415 : InstRSYb<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$BD2),
2416 mnemonic#V.suffix#"\t$R1, $BD2", []> {
2417 let Constraints = "$R1 = $R1src";
2418 let DisableEncoding = "$R1src";
2420 let AccessBytes = bytes;
2421 let isAsmParserOnly = V.alternate;
2425 multiclass CondUnaryRSYPair<string mnemonic, bits<16> opcode,
2426 SDPatternOperator operator,
2427 RegisterOperand cls, bits<5> bytes,
2428 AddressingMode mode = bdaddr20only> {
2429 let isCodeGenOnly = 1 in
2430 def "" : CondUnaryRSY<mnemonic, opcode, operator, cls, bytes, mode>;
2431 def Asm : AsmCondUnaryRSY<mnemonic, opcode, cls, bytes, mode>;
2435 class UnaryRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
2436 RegisterOperand cls, bits<5> bytes,
2437 AddressingMode mode = bdxaddr12only>
2438 : InstRXa<opcode, (outs cls:$R1), (ins mode:$XBD2),
2439 mnemonic#"\t$R1, $XBD2",
2440 [(set cls:$R1, (operator mode:$XBD2))]> {
2441 let OpKey = mnemonic#"r"#cls;
2444 let AccessBytes = bytes;
2447 class UnaryRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2448 RegisterOperand cls, bits<5> bytes>
2449 : InstRXE<opcode, (outs cls:$R1), (ins bdxaddr12only:$XBD2),
2450 mnemonic#"\t$R1, $XBD2",
2451 [(set cls:$R1, (operator bdxaddr12only:$XBD2))]> {
2452 let OpKey = mnemonic#"r"#cls;
2455 let AccessBytes = bytes;
2459 class UnaryRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2460 RegisterOperand cls, bits<5> bytes,
2461 AddressingMode mode = bdxaddr20only>
2462 : InstRXYa<opcode, (outs cls:$R1), (ins mode:$XBD2),
2463 mnemonic#"\t$R1, $XBD2",
2464 [(set cls:$R1, (operator mode:$XBD2))]> {
2465 let OpKey = mnemonic#"r"#cls;
2468 let AccessBytes = bytes;
2471 multiclass UnaryRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
2472 SDPatternOperator operator, RegisterOperand cls,
2474 let DispKey = mnemonic ## #cls in {
2475 let DispSize = "12" in
2476 def "" : UnaryRX<mnemonic, rxOpcode, operator, cls, bytes, bdxaddr12pair>;
2477 let DispSize = "20" in
2478 def Y : UnaryRXY<mnemonic#"y", rxyOpcode, operator, cls, bytes,
2483 class UnaryVRIa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2484 TypedReg tr, Immediate imm, bits<4> type = 0>
2485 : InstVRIa<opcode, (outs tr.op:$V1), (ins imm:$I2),
2486 mnemonic#"\t$V1, $I2",
2487 [(set tr.op:$V1, (tr.vt (operator imm:$I2)))]> {
2491 class UnaryVRIaGeneric<string mnemonic, bits<16> opcode, Immediate imm>
2492 : InstVRIa<opcode, (outs VR128:$V1), (ins imm:$I2, imm32zx4:$M3),
2493 mnemonic#"\t$V1, $I2, $M3", []>;
2495 class UnaryVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2496 TypedReg tr1, TypedReg tr2, bits<4> type = 0, bits<4> m4 = 0,
2498 : InstVRRa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2),
2499 mnemonic#"\t$V1, $V2",
2500 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2))))]> {
2506 class UnaryVRRaGeneric<string mnemonic, bits<16> opcode, bits<4> m4 = 0,
2508 : InstVRRa<opcode, (outs VR128:$V1), (ins VR128:$V2, imm32zx4:$M3),
2509 mnemonic#"\t$V1, $V2, $M3", []> {
2514 class UnaryVRRaFloatGeneric<string mnemonic, bits<16> opcode, bits<4> m5 = 0>
2515 : InstVRRa<opcode, (outs VR128:$V1),
2516 (ins VR128:$V2, imm32zx4:$M3, imm32zx4:$M4),
2517 mnemonic#"\t$V1, $V2, $M3, $M4", []> {
2521 // Declare a pair of instructions, one which sets CC and one which doesn't.
2522 // The CC-setting form ends with "S" and sets the low bit of M5.
2523 // The form that does not set CC has an extra operand to optionally allow
2524 // specifying arbitrary M5 values in assembler.
2525 multiclass UnaryExtraVRRaSPair<string mnemonic, bits<16> opcode,
2526 SDPatternOperator operator,
2527 SDPatternOperator operator_cc,
2528 TypedReg tr1, TypedReg tr2, bits<4> type> {
2529 let M3 = type, M4 = 0 in
2530 def "" : InstVRRa<opcode, (outs tr1.op:$V1),
2531 (ins tr2.op:$V2, imm32zx4:$M5),
2532 mnemonic#"\t$V1, $V2, $M5", []>;
2533 def : Pat<(tr1.vt (operator (tr2.vt tr2.op:$V2))),
2534 (!cast<Instruction>(NAME) tr2.op:$V2, 0)>;
2535 def : InstAlias<mnemonic#"\t$V1, $V2",
2536 (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2, 0)>;
2538 def S : UnaryVRRa<mnemonic##"s", opcode, operator_cc, tr1, tr2,
2542 multiclass UnaryExtraVRRaSPairGeneric<string mnemonic, bits<16> opcode> {
2544 def "" : InstVRRa<opcode, (outs VR128:$V1),
2545 (ins VR128:$V2, imm32zx4:$M3, imm32zx4:$M5),
2546 mnemonic#"\t$V1, $V2, $M3, $M5", []>;
2547 def : InstAlias<mnemonic#"\t$V1, $V2, $M3",
2548 (!cast<Instruction>(NAME) VR128:$V1, VR128:$V2,
2552 class UnaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2553 TypedReg tr, bits<5> bytes, bits<4> type = 0>
2554 : InstVRX<opcode, (outs tr.op:$V1), (ins bdxaddr12only:$XBD2),
2555 mnemonic#"\t$V1, $XBD2",
2556 [(set tr.op:$V1, (tr.vt (operator bdxaddr12only:$XBD2)))]> {
2559 let AccessBytes = bytes;
2562 class UnaryVRXGeneric<string mnemonic, bits<16> opcode>
2563 : InstVRX<opcode, (outs VR128:$V1), (ins bdxaddr12only:$XBD2, imm32zx4:$M3),
2564 mnemonic#"\t$V1, $XBD2, $M3", []> {
2568 class SideEffectBinaryRX<string mnemonic, bits<8> opcode,
2569 RegisterOperand cls>
2570 : InstRXa<opcode, (outs), (ins cls:$R1, bdxaddr12only:$XBD2),
2571 mnemonic##"\t$R1, $XBD2", []>;
2573 class SideEffectBinaryRILPC<string mnemonic, bits<12> opcode,
2574 RegisterOperand cls>
2575 : InstRILb<opcode, (outs), (ins cls:$R1, pcrel32:$RI2),
2576 mnemonic##"\t$R1, $RI2", []> {
2577 // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
2578 // However, BDXs have two extra operands and are therefore 6 units more
2580 let AddedComplexity = 7;
2583 class SideEffectBinaryIE<string mnemonic, bits<16> opcode,
2584 Immediate imm1, Immediate imm2>
2585 : InstIE<opcode, (outs), (ins imm1:$I1, imm2:$I2),
2586 mnemonic#"\t$I1, $I2", []>;
2588 class SideEffectBinarySIL<string mnemonic, bits<16> opcode,
2589 SDPatternOperator operator, Immediate imm>
2590 : InstSIL<opcode, (outs), (ins bdaddr12only:$BD1, imm:$I2),
2591 mnemonic#"\t$BD1, $I2", [(operator bdaddr12only:$BD1, imm:$I2)]>;
2593 class BinaryRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
2594 RegisterOperand cls1, RegisterOperand cls2>
2595 : InstRR<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
2596 mnemonic#"\t$R1, $R2",
2597 [(set cls1:$R1, (operator cls1:$R1src, cls2:$R2))]> {
2598 let OpKey = mnemonic#cls1;
2600 let Constraints = "$R1 = $R1src";
2601 let DisableEncoding = "$R1src";
2604 class BinaryRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2605 RegisterOperand cls1, RegisterOperand cls2>
2606 : InstRRE<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
2607 mnemonic#"\t$R1, $R2",
2608 [(set cls1:$R1, (operator cls1:$R1src, cls2:$R2))]> {
2609 let OpKey = mnemonic#cls1;
2611 let Constraints = "$R1 = $R1src";
2612 let DisableEncoding = "$R1src";
2615 class BinaryRRFa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2616 RegisterOperand cls1, RegisterOperand cls2,
2617 RegisterOperand cls3>
2618 : InstRRFa<opcode, (outs cls1:$R1), (ins cls2:$R2, cls3:$R3),
2619 mnemonic#"\t$R1, $R2, $R3",
2620 [(set cls1:$R1, (operator cls2:$R2, cls3:$R3))]> {
2624 multiclass BinaryRRAndK<string mnemonic, bits<8> opcode1, bits<16> opcode2,
2625 SDPatternOperator operator, RegisterOperand cls1,
2626 RegisterOperand cls2> {
2627 let NumOpsKey = mnemonic in {
2628 let NumOpsValue = "3" in
2629 def K : BinaryRRFa<mnemonic#"k", opcode2, null_frag, cls1, cls1, cls2>,
2630 Requires<[FeatureDistinctOps]>;
2631 let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in
2632 def "" : BinaryRR<mnemonic, opcode1, operator, cls1, cls2>;
2636 multiclass BinaryRREAndK<string mnemonic, bits<16> opcode1, bits<16> opcode2,
2637 SDPatternOperator operator, RegisterOperand cls1,
2638 RegisterOperand cls2> {
2639 let NumOpsKey = mnemonic in {
2640 let NumOpsValue = "3" in
2641 def K : BinaryRRFa<mnemonic#"k", opcode2, null_frag, cls1, cls1, cls2>,
2642 Requires<[FeatureDistinctOps]>;
2643 let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in
2644 def "" : BinaryRRE<mnemonic, opcode1, operator, cls1, cls2>;
2648 class BinaryRRFb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2649 RegisterOperand cls1, RegisterOperand cls2,
2650 RegisterOperand cls3>
2651 : InstRRFb<opcode, (outs cls1:$R1), (ins cls2:$R2, cls3:$R3),
2652 mnemonic#"\t$R1, $R3, $R2",
2653 [(set cls1:$R1, (operator cls2:$R2, cls3:$R3))]> {
2657 class BinaryRRFe<string mnemonic, bits<16> opcode, RegisterOperand cls1,
2658 RegisterOperand cls2>
2659 : InstRRFe<opcode, (outs cls1:$R1), (ins imm32zx4:$M3, cls2:$R2),
2660 mnemonic#"\t$R1, $M3, $R2", []> {
2664 class CondBinaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
2665 RegisterOperand cls2>
2666 : InstRRFc<opcode, (outs cls1:$R1),
2667 (ins cls1:$R1src, cls2:$R2, cond4:$valid, cond4:$M3),
2668 mnemonic#"$M3\t$R1, $R2", []> {
2669 let Constraints = "$R1 = $R1src";
2670 let DisableEncoding = "$R1src";
2674 // Like CondBinaryRRF, but used for the raw assembly form. The condition-code
2675 // mask is the third operand rather than being part of the mnemonic.
2676 class AsmCondBinaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
2677 RegisterOperand cls2>
2678 : InstRRFc<opcode, (outs cls1:$R1),
2679 (ins cls1:$R1src, cls2:$R2, imm32zx4:$M3),
2680 mnemonic#"\t$R1, $R2, $M3", []> {
2681 let Constraints = "$R1 = $R1src";
2682 let DisableEncoding = "$R1src";
2685 // Like CondBinaryRRF, but with a fixed CC mask.
2686 class FixedCondBinaryRRF<CondVariant V, string mnemonic, bits<16> opcode,
2687 RegisterOperand cls1, RegisterOperand cls2>
2688 : InstRRFc<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
2689 mnemonic#V.suffix#"\t$R1, $R2", []> {
2690 let Constraints = "$R1 = $R1src";
2691 let DisableEncoding = "$R1src";
2692 let isAsmParserOnly = V.alternate;
2696 multiclass CondBinaryRRFPair<string mnemonic, bits<16> opcode,
2697 RegisterOperand cls1, RegisterOperand cls2> {
2698 let isCodeGenOnly = 1 in
2699 def "" : CondBinaryRRF<mnemonic, opcode, cls1, cls2>;
2700 def Asm : AsmCondBinaryRRF<mnemonic, opcode, cls1, cls2>;
2703 class BinaryRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
2704 RegisterOperand cls, Immediate imm>
2705 : InstRIa<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
2706 mnemonic#"\t$R1, $I2",
2707 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
2708 let Constraints = "$R1 = $R1src";
2709 let DisableEncoding = "$R1src";
2712 class BinaryRIE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2713 RegisterOperand cls, Immediate imm>
2714 : InstRIEd<opcode, (outs cls:$R1), (ins cls:$R3, imm:$I2),
2715 mnemonic#"\t$R1, $R3, $I2",
2716 [(set cls:$R1, (operator cls:$R3, imm:$I2))]>;
2718 multiclass BinaryRIAndK<string mnemonic, bits<12> opcode1, bits<16> opcode2,
2719 SDPatternOperator operator, RegisterOperand cls,
2721 let NumOpsKey = mnemonic in {
2722 let NumOpsValue = "3" in
2723 def K : BinaryRIE<mnemonic##"k", opcode2, null_frag, cls, imm>,
2724 Requires<[FeatureDistinctOps]>;
2725 let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in
2726 def "" : BinaryRI<mnemonic, opcode1, operator, cls, imm>;
2730 class CondBinaryRIE<string mnemonic, bits<16> opcode, RegisterOperand cls,
2732 : InstRIEg<opcode, (outs cls:$R1),
2733 (ins cls:$R1src, imm:$I2, cond4:$valid, cond4:$M3),
2734 mnemonic#"$M3\t$R1, $I2",
2735 [(set cls:$R1, (z_select_ccmask imm:$I2, cls:$R1src,
2736 cond4:$valid, cond4:$M3))]> {
2737 let Constraints = "$R1 = $R1src";
2738 let DisableEncoding = "$R1src";
2742 // Like CondBinaryRIE, but used for the raw assembly form. The condition-code
2743 // mask is the third operand rather than being part of the mnemonic.
2744 class AsmCondBinaryRIE<string mnemonic, bits<16> opcode, RegisterOperand cls,
2746 : InstRIEg<opcode, (outs cls:$R1),
2747 (ins cls:$R1src, imm:$I2, imm32zx4:$M3),
2748 mnemonic#"\t$R1, $I2, $M3", []> {
2749 let Constraints = "$R1 = $R1src";
2750 let DisableEncoding = "$R1src";
2753 // Like CondBinaryRIE, but with a fixed CC mask.
2754 class FixedCondBinaryRIE<CondVariant V, string mnemonic, bits<16> opcode,
2755 RegisterOperand cls, Immediate imm>
2756 : InstRIEg<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
2757 mnemonic#V.suffix#"\t$R1, $I2", []> {
2758 let Constraints = "$R1 = $R1src";
2759 let DisableEncoding = "$R1src";
2760 let isAsmParserOnly = V.alternate;
2764 multiclass CondBinaryRIEPair<string mnemonic, bits<16> opcode,
2765 RegisterOperand cls, Immediate imm> {
2766 let isCodeGenOnly = 1 in
2767 def "" : CondBinaryRIE<mnemonic, opcode, cls, imm>;
2768 def Asm : AsmCondBinaryRIE<mnemonic, opcode, cls, imm>;
2771 class BinaryRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator,
2772 RegisterOperand cls, Immediate imm>
2773 : InstRILa<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
2774 mnemonic#"\t$R1, $I2",
2775 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
2776 let Constraints = "$R1 = $R1src";
2777 let DisableEncoding = "$R1src";
2780 class BinaryRS<string mnemonic, bits<8> opcode, SDPatternOperator operator,
2781 RegisterOperand cls>
2782 : InstRSa<opcode, (outs cls:$R1), (ins cls:$R1src, shift12only:$BD2),
2783 mnemonic#"\t$R1, $BD2",
2784 [(set cls:$R1, (operator cls:$R1src, shift12only:$BD2))]> {
2786 let Constraints = "$R1 = $R1src";
2787 let DisableEncoding = "$R1src";
2790 class BinaryRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2791 RegisterOperand cls>
2792 : InstRSYa<opcode, (outs cls:$R1), (ins cls:$R3, shift20only:$BD2),
2793 mnemonic#"\t$R1, $R3, $BD2",
2794 [(set cls:$R1, (operator cls:$R3, shift20only:$BD2))]>;
2796 multiclass BinaryRSAndK<string mnemonic, bits<8> opcode1, bits<16> opcode2,
2797 SDPatternOperator operator, RegisterOperand cls> {
2798 let NumOpsKey = mnemonic in {
2799 let NumOpsValue = "3" in
2800 def K : BinaryRSY<mnemonic##"k", opcode2, null_frag, cls>,
2801 Requires<[FeatureDistinctOps]>;
2802 let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in
2803 def "" : BinaryRS<mnemonic, opcode1, operator, cls>;
2807 class BinaryRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
2808 RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
2809 AddressingMode mode = bdxaddr12only>
2810 : InstRXa<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$XBD2),
2811 mnemonic#"\t$R1, $XBD2",
2812 [(set cls:$R1, (operator cls:$R1src, (load mode:$XBD2)))]> {
2813 let OpKey = mnemonic#"r"#cls;
2815 let Constraints = "$R1 = $R1src";
2816 let DisableEncoding = "$R1src";
2818 let AccessBytes = bytes;
2821 class BinaryRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2822 RegisterOperand cls, SDPatternOperator load, bits<5> bytes>
2823 : InstRXE<opcode, (outs cls:$R1), (ins cls:$R1src, bdxaddr12only:$XBD2),
2824 mnemonic#"\t$R1, $XBD2",
2825 [(set cls:$R1, (operator cls:$R1src,
2826 (load bdxaddr12only:$XBD2)))]> {
2827 let OpKey = mnemonic#"r"#cls;
2829 let Constraints = "$R1 = $R1src";
2830 let DisableEncoding = "$R1src";
2832 let AccessBytes = bytes;
2836 class BinaryRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2837 RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
2838 AddressingMode mode = bdxaddr20only>
2839 : InstRXYa<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$XBD2),
2840 mnemonic#"\t$R1, $XBD2",
2841 [(set cls:$R1, (operator cls:$R1src, (load mode:$XBD2)))]> {
2842 let OpKey = mnemonic#"r"#cls;
2844 let Constraints = "$R1 = $R1src";
2845 let DisableEncoding = "$R1src";
2847 let AccessBytes = bytes;
2850 multiclass BinaryRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
2851 SDPatternOperator operator, RegisterOperand cls,
2852 SDPatternOperator load, bits<5> bytes> {
2853 let DispKey = mnemonic ## #cls in {
2854 let DispSize = "12" in
2855 def "" : BinaryRX<mnemonic, rxOpcode, operator, cls, load, bytes,
2857 let DispSize = "20" in
2858 def Y : BinaryRXY<mnemonic#"y", rxyOpcode, operator, cls, load, bytes,
2863 class BinarySI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
2864 Operand imm, AddressingMode mode = bdaddr12only>
2865 : InstSI<opcode, (outs), (ins mode:$BD1, imm:$I2),
2866 mnemonic#"\t$BD1, $I2",
2867 [(store (operator (load mode:$BD1), imm:$I2), mode:$BD1)]> {
2872 class BinarySIY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2873 Operand imm, AddressingMode mode = bdaddr20only>
2874 : InstSIY<opcode, (outs), (ins mode:$BD1, imm:$I2),
2875 mnemonic#"\t$BD1, $I2",
2876 [(store (operator (load mode:$BD1), imm:$I2), mode:$BD1)]> {
2881 multiclass BinarySIPair<string mnemonic, bits<8> siOpcode,
2882 bits<16> siyOpcode, SDPatternOperator operator,
2884 let DispKey = mnemonic ## #cls in {
2885 let DispSize = "12" in
2886 def "" : BinarySI<mnemonic, siOpcode, operator, imm, bdaddr12pair>;
2887 let DispSize = "20" in
2888 def Y : BinarySIY<mnemonic#"y", siyOpcode, operator, imm, bdaddr20pair>;
2892 class BinarySSF<string mnemonic, bits<12> opcode, RegisterOperand cls>
2893 : InstSSF<opcode, (outs cls:$R3), (ins bdaddr12pair:$BD1, bdaddr12pair:$BD2),
2894 mnemonic#"\t$R3, $BD1, $BD2", []> {
2898 class BinaryVRIb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2899 TypedReg tr, bits<4> type>
2900 : InstVRIb<opcode, (outs tr.op:$V1), (ins imm32zx8:$I2, imm32zx8:$I3),
2901 mnemonic#"\t$V1, $I2, $I3",
2902 [(set tr.op:$V1, (tr.vt (operator imm32zx8:$I2, imm32zx8:$I3)))]> {
2906 class BinaryVRIbGeneric<string mnemonic, bits<16> opcode>
2907 : InstVRIb<opcode, (outs VR128:$V1),
2908 (ins imm32zx8:$I2, imm32zx8:$I3, imm32zx4:$M4),
2909 mnemonic#"\t$V1, $I2, $I3, $M4", []>;
2911 class BinaryVRIc<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2912 TypedReg tr1, TypedReg tr2, bits<4> type>
2913 : InstVRIc<opcode, (outs tr1.op:$V1), (ins tr2.op:$V3, imm32zx16:$I2),
2914 mnemonic#"\t$V1, $V3, $I2",
2915 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V3),
2916 imm32zx16:$I2)))]> {
2920 class BinaryVRIcGeneric<string mnemonic, bits<16> opcode>
2921 : InstVRIc<opcode, (outs VR128:$V1),
2922 (ins VR128:$V3, imm32zx16:$I2, imm32zx4:$M4),
2923 mnemonic#"\t$V1, $V3, $I2, $M4", []>;
2925 class BinaryVRIe<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2926 TypedReg tr1, TypedReg tr2, bits<4> type, bits<4> m5>
2927 : InstVRIe<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, imm32zx12:$I3),
2928 mnemonic#"\t$V1, $V2, $I3",
2929 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
2930 imm32zx12:$I3)))]> {
2935 class BinaryVRIeFloatGeneric<string mnemonic, bits<16> opcode>
2936 : InstVRIe<opcode, (outs VR128:$V1),
2937 (ins VR128:$V2, imm32zx12:$I3, imm32zx4:$M4, imm32zx4:$M5),
2938 mnemonic#"\t$V1, $V2, $I3, $M4, $M5", []>;
2940 class BinaryVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2941 TypedReg tr1, TypedReg tr2, bits<4> type = 0, bits<4> m4 = 0>
2942 : InstVRRa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, imm32zx4:$M5),
2943 mnemonic#"\t$V1, $V2, $M5",
2944 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
2945 imm32zx12:$M5)))]> {
2950 class BinaryVRRaFloatGeneric<string mnemonic, bits<16> opcode>
2951 : InstVRRa<opcode, (outs VR128:$V1),
2952 (ins VR128:$V2, imm32zx4:$M3, imm32zx4:$M4, imm32zx4:$M5),
2953 mnemonic#"\t$V1, $V2, $M3, $M4, $M5", []>;
2955 class BinaryVRRb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2956 TypedReg tr1, TypedReg tr2, bits<4> type = 0,
2957 bits<4> modifier = 0>
2958 : InstVRRb<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, tr2.op:$V3),
2959 mnemonic#"\t$V1, $V2, $V3",
2960 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
2961 (tr2.vt tr2.op:$V3))))]> {
2966 // Declare a pair of instructions, one which sets CC and one which doesn't.
2967 // The CC-setting form ends with "S" and sets the low bit of M5.
2968 multiclass BinaryVRRbSPair<string mnemonic, bits<16> opcode,
2969 SDPatternOperator operator,
2970 SDPatternOperator operator_cc, TypedReg tr1,
2971 TypedReg tr2, bits<4> type, bits<4> modifier = 0> {
2972 def "" : BinaryVRRb<mnemonic, opcode, operator, tr1, tr2, type,
2973 !and (modifier, 14)>;
2975 def S : BinaryVRRb<mnemonic##"s", opcode, operator_cc, tr1, tr2, type,
2976 !add (!and (modifier, 14), 1)>;
2979 class BinaryVRRbSPairGeneric<string mnemonic, bits<16> opcode>
2980 : InstVRRb<opcode, (outs VR128:$V1),
2981 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5),
2982 mnemonic#"\t$V1, $V2, $V3, $M4, $M5", []>;
2984 // Declare a pair of instructions, one which sets CC and one which doesn't.
2985 // The CC-setting form ends with "S" and sets the low bit of M5.
2986 // The form that does not set CC has an extra operand to optionally allow
2987 // specifying arbitrary M5 values in assembler.
2988 multiclass BinaryExtraVRRbSPair<string mnemonic, bits<16> opcode,
2989 SDPatternOperator operator,
2990 SDPatternOperator operator_cc,
2991 TypedReg tr1, TypedReg tr2, bits<4> type> {
2993 def "" : InstVRRb<opcode, (outs tr1.op:$V1),
2994 (ins tr2.op:$V2, tr2.op:$V3, imm32zx4:$M5),
2995 mnemonic#"\t$V1, $V2, $V3, $M5", []>;
2996 def : Pat<(tr1.vt (operator (tr2.vt tr2.op:$V2), (tr2.vt tr2.op:$V3))),
2997 (!cast<Instruction>(NAME) tr2.op:$V2, tr2.op:$V3, 0)>;
2998 def : InstAlias<mnemonic#"\t$V1, $V2, $V3",
2999 (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2,
3002 def S : BinaryVRRb<mnemonic##"s", opcode, operator_cc, tr1, tr2, type, 1>;
3005 multiclass BinaryExtraVRRbSPairGeneric<string mnemonic, bits<16> opcode> {
3006 def "" : InstVRRb<opcode, (outs VR128:$V1),
3007 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5),
3008 mnemonic#"\t$V1, $V2, $V3, $M4, $M5", []>;
3009 def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $M4",
3010 (!cast<Instruction>(NAME) VR128:$V1, VR128:$V2, VR128:$V3,
3014 class BinaryVRRc<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3015 TypedReg tr1, TypedReg tr2, bits<4> type = 0, bits<4> m5 = 0,
3017 : InstVRRc<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, tr2.op:$V3),
3018 mnemonic#"\t$V1, $V2, $V3",
3019 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
3020 (tr2.vt tr2.op:$V3))))]> {
3026 class BinaryVRRcGeneric<string mnemonic, bits<16> opcode, bits<4> m5 = 0,
3028 : InstVRRc<opcode, (outs VR128:$V1),
3029 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4),
3030 mnemonic#"\t$V1, $V2, $V3, $M4", []> {
3035 class BinaryVRRcFloatGeneric<string mnemonic, bits<16> opcode, bits<4> m6 = 0>
3036 : InstVRRc<opcode, (outs VR128:$V1),
3037 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5),
3038 mnemonic#"\t$V1, $V2, $V3, $M4, $M5", []> {
3042 // Declare a pair of instructions, one which sets CC and one which doesn't.
3043 // The CC-setting form ends with "S" and sets the low bit of M5.
3044 multiclass BinaryVRRcSPair<string mnemonic, bits<16> opcode,
3045 SDPatternOperator operator,
3046 SDPatternOperator operator_cc, TypedReg tr1,
3047 TypedReg tr2, bits<4> type, bits<4> m5,
3048 bits<4> modifier = 0> {
3049 def "" : BinaryVRRc<mnemonic, opcode, operator, tr1, tr2, type,
3050 m5, !and (modifier, 14)>;
3052 def S : BinaryVRRc<mnemonic##"s", opcode, operator_cc, tr1, tr2, type,
3053 m5, !add (!and (modifier, 14), 1)>;
3056 class BinaryVRRcSPairFloatGeneric<string mnemonic, bits<16> opcode>
3057 : InstVRRc<opcode, (outs VR128:$V1),
3058 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5,
3060 mnemonic#"\t$V1, $V2, $V3, $M4, $M5, $M6", []>;
3062 class BinaryVRRf<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3064 : InstVRRf<opcode, (outs tr.op:$V1), (ins GR64:$R2, GR64:$R3),
3065 mnemonic#"\t$V1, $R2, $R3",
3066 [(set tr.op:$V1, (tr.vt (operator GR64:$R2, GR64:$R3)))]>;
3068 class BinaryVRSa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3069 TypedReg tr1, TypedReg tr2, bits<4> type>
3070 : InstVRSa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V3, shift12only:$BD2),
3071 mnemonic#"\t$V1, $V3, $BD2",
3072 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V3),
3073 shift12only:$BD2)))]> {
3077 class BinaryVRSaGeneric<string mnemonic, bits<16> opcode>
3078 : InstVRSa<opcode, (outs VR128:$V1),
3079 (ins VR128:$V3, shift12only:$BD2, imm32zx4:$M4),
3080 mnemonic#"\t$V1, $V3, $BD2, $M4", []>;
3082 class BinaryVRSb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3084 : InstVRSb<opcode, (outs VR128:$V1), (ins GR32:$R3, bdaddr12only:$BD2),
3085 mnemonic#"\t$V1, $R3, $BD2",
3086 [(set VR128:$V1, (operator GR32:$R3, bdaddr12only:$BD2))]> {
3089 let AccessBytes = bytes;
3092 class BinaryVRSc<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3093 TypedReg tr, bits<4> type>
3094 : InstVRSc<opcode, (outs GR64:$R1), (ins tr.op:$V3, shift12only:$BD2),
3095 mnemonic#"\t$R1, $V3, $BD2",
3096 [(set GR64:$R1, (operator (tr.vt tr.op:$V3), shift12only:$BD2))]> {
3100 class BinaryVRScGeneric<string mnemonic, bits<16> opcode>
3101 : InstVRSc<opcode, (outs GR64:$R1),
3102 (ins VR128:$V3, shift12only:$BD2, imm32zx4: $M4),
3103 mnemonic#"\t$R1, $V3, $BD2, $M4", []>;
3105 class BinaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3106 TypedReg tr, bits<5> bytes>
3107 : InstVRX<opcode, (outs VR128:$V1), (ins bdxaddr12only:$XBD2, imm32zx4:$M3),
3108 mnemonic#"\t$V1, $XBD2, $M3",
3109 [(set tr.op:$V1, (tr.vt (operator bdxaddr12only:$XBD2,
3112 let AccessBytes = bytes;
3115 class StoreBinaryVRV<string mnemonic, bits<16> opcode, bits<5> bytes,
3117 : InstVRV<opcode, (outs), (ins VR128:$V1, bdvaddr12only:$VBD2, index:$M3),
3118 mnemonic#"\t$V1, $VBD2, $M3", []> {
3120 let AccessBytes = bytes;
3123 class StoreBinaryVRX<string mnemonic, bits<16> opcode,
3124 SDPatternOperator operator, TypedReg tr, bits<5> bytes,
3126 : InstVRX<opcode, (outs), (ins tr.op:$V1, bdxaddr12only:$XBD2, index:$M3),
3127 mnemonic#"\t$V1, $XBD2, $M3",
3128 [(operator (tr.vt tr.op:$V1), bdxaddr12only:$XBD2, index:$M3)]> {
3130 let AccessBytes = bytes;
3133 class MemoryBinarySSd<string mnemonic, bits<8> opcode,
3134 RegisterOperand cls>
3135 : InstSSd<opcode, (outs),
3136 (ins bdraddr12only:$RBD1, bdaddr12only:$BD2, cls:$R3),
3137 mnemonic#"\t$RBD1, $BD2, $R3", []>;
3139 class CompareRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
3140 RegisterOperand cls1, RegisterOperand cls2>
3141 : InstRR<opcode, (outs), (ins cls1:$R1, cls2:$R2),
3142 mnemonic#"\t$R1, $R2",
3143 [(operator cls1:$R1, cls2:$R2)]> {
3144 let OpKey = mnemonic#cls1;
3149 class CompareRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3150 RegisterOperand cls1, RegisterOperand cls2>
3151 : InstRRE<opcode, (outs), (ins cls1:$R1, cls2:$R2),
3152 mnemonic#"\t$R1, $R2",
3153 [(operator cls1:$R1, cls2:$R2)]> {
3154 let OpKey = mnemonic#cls1;
3159 class CompareRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
3160 RegisterOperand cls, Immediate imm>
3161 : InstRIa<opcode, (outs), (ins cls:$R1, imm:$I2),
3162 mnemonic#"\t$R1, $I2",
3163 [(operator cls:$R1, imm:$I2)]> {
3167 class CompareRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator,
3168 RegisterOperand cls, Immediate imm>
3169 : InstRILa<opcode, (outs), (ins cls:$R1, imm:$I2),
3170 mnemonic#"\t$R1, $I2",
3171 [(operator cls:$R1, imm:$I2)]> {
3175 class CompareRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator,
3176 RegisterOperand cls, SDPatternOperator load>
3177 : InstRILb<opcode, (outs), (ins cls:$R1, pcrel32:$RI2),
3178 mnemonic#"\t$R1, $RI2",
3179 [(operator cls:$R1, (load pcrel32:$RI2))]> {
3182 // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
3183 // However, BDXs have two extra operands and are therefore 6 units more
3185 let AddedComplexity = 7;
3188 class CompareRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
3189 RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
3190 AddressingMode mode = bdxaddr12only>
3191 : InstRXa<opcode, (outs), (ins cls:$R1, mode:$XBD2),
3192 mnemonic#"\t$R1, $XBD2",
3193 [(operator cls:$R1, (load mode:$XBD2))]> {
3194 let OpKey = mnemonic#"r"#cls;
3198 let AccessBytes = bytes;
3201 class CompareRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3202 RegisterOperand cls, SDPatternOperator load, bits<5> bytes>
3203 : InstRXE<opcode, (outs), (ins cls:$R1, bdxaddr12only:$XBD2),
3204 mnemonic#"\t$R1, $XBD2",
3205 [(operator cls:$R1, (load bdxaddr12only:$XBD2))]> {
3206 let OpKey = mnemonic#"r"#cls;
3210 let AccessBytes = bytes;
3214 class CompareRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3215 RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
3216 AddressingMode mode = bdxaddr20only>
3217 : InstRXYa<opcode, (outs), (ins cls:$R1, mode:$XBD2),
3218 mnemonic#"\t$R1, $XBD2",
3219 [(operator cls:$R1, (load mode:$XBD2))]> {
3220 let OpKey = mnemonic#"r"#cls;
3224 let AccessBytes = bytes;
3227 multiclass CompareRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
3228 SDPatternOperator operator, RegisterOperand cls,
3229 SDPatternOperator load, bits<5> bytes> {
3230 let DispKey = mnemonic ## #cls in {
3231 let DispSize = "12" in
3232 def "" : CompareRX<mnemonic, rxOpcode, operator, cls,
3233 load, bytes, bdxaddr12pair>;
3234 let DispSize = "20" in
3235 def Y : CompareRXY<mnemonic#"y", rxyOpcode, operator, cls,
3236 load, bytes, bdxaddr20pair>;
3240 class CompareSI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
3241 SDPatternOperator load, Immediate imm,
3242 AddressingMode mode = bdaddr12only>
3243 : InstSI<opcode, (outs), (ins mode:$BD1, imm:$I2),
3244 mnemonic#"\t$BD1, $I2",
3245 [(operator (load mode:$BD1), imm:$I2)]> {
3250 class CompareSIL<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3251 SDPatternOperator load, Immediate imm>
3252 : InstSIL<opcode, (outs), (ins bdaddr12only:$BD1, imm:$I2),
3253 mnemonic#"\t$BD1, $I2",
3254 [(operator (load bdaddr12only:$BD1), imm:$I2)]> {
3259 class CompareSIY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3260 SDPatternOperator load, Immediate imm,
3261 AddressingMode mode = bdaddr20only>
3262 : InstSIY<opcode, (outs), (ins mode:$BD1, imm:$I2),
3263 mnemonic#"\t$BD1, $I2",
3264 [(operator (load mode:$BD1), imm:$I2)]> {
3269 multiclass CompareSIPair<string mnemonic, bits<8> siOpcode, bits<16> siyOpcode,
3270 SDPatternOperator operator, SDPatternOperator load,
3272 let DispKey = mnemonic in {
3273 let DispSize = "12" in
3274 def "" : CompareSI<mnemonic, siOpcode, operator, load, imm, bdaddr12pair>;
3275 let DispSize = "20" in
3276 def Y : CompareSIY<mnemonic#"y", siyOpcode, operator, load, imm,
3281 class CompareVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3282 TypedReg tr, bits<4> type>
3283 : InstVRRa<opcode, (outs), (ins tr.op:$V1, tr.op:$V2),
3284 mnemonic#"\t$V1, $V2",
3285 [(operator (tr.vt tr.op:$V1), (tr.vt tr.op:$V2))]> {
3292 class CompareVRRaGeneric<string mnemonic, bits<16> opcode>
3293 : InstVRRa<opcode, (outs), (ins VR128:$V1, VR128:$V2, imm32zx4:$M3),
3294 mnemonic#"\t$V1, $V2, $M3", []> {
3300 class CompareVRRaFloatGeneric<string mnemonic, bits<16> opcode>
3301 : InstVRRa<opcode, (outs),
3302 (ins VR64:$V1, VR64:$V2, imm32zx4:$M3, imm32zx4:$M4),
3303 mnemonic#"\t$V1, $V2, $M3, $M4", []> {
3308 class TestRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3309 RegisterOperand cls>
3310 : InstRXE<opcode, (outs), (ins cls:$R1, bdxaddr12only:$XBD2),
3311 mnemonic#"\t$R1, $XBD2",
3312 [(operator cls:$R1, bdxaddr12only:$XBD2)]> {
3316 class SideEffectTernaryRRFc<string mnemonic, bits<16> opcode,
3317 RegisterOperand cls1, RegisterOperand cls2,
3319 : InstRRFc<opcode, (outs), (ins cls1:$R1, cls2:$R2, imm:$M3),
3320 mnemonic#"\t$R1, $R2, $M3", []>;
3322 class SideEffectTernarySSF<string mnemonic, bits<12> opcode,
3323 RegisterOperand cls>
3324 : InstSSF<opcode, (outs),
3325 (ins bdaddr12only:$BD1, bdaddr12only:$BD2, cls:$R3),
3326 mnemonic#"\t$BD1, $BD2, $R3", []>;
3328 class TernaryRRFe<string mnemonic, bits<16> opcode, RegisterOperand cls1,
3329 RegisterOperand cls2>
3330 : InstRRFe<opcode, (outs cls1:$R1),
3331 (ins imm32zx4:$M3, cls2:$R2, imm32zx4:$M4),
3332 mnemonic#"\t$R1, $M3, $R2, $M4", []>;
3334 class TernaryRRD<string mnemonic, bits<16> opcode,
3335 SDPatternOperator operator, RegisterOperand cls>
3336 : InstRRD<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, cls:$R2),
3337 mnemonic#"\t$R1, $R3, $R2",
3338 [(set cls:$R1, (operator cls:$R1src, cls:$R3, cls:$R2))]> {
3339 let OpKey = mnemonic#cls;
3341 let Constraints = "$R1 = $R1src";
3342 let DisableEncoding = "$R1src";
3345 class TernaryRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
3346 bits<5> bytes, AddressingMode mode = bdaddr12only>
3347 : InstRSb<opcode, (outs cls:$R1),
3348 (ins cls:$R1src, imm32zx4:$M3, mode:$BD2),
3349 mnemonic#"\t$R1, $M3, $BD2", []> {
3351 let Constraints = "$R1 = $R1src";
3352 let DisableEncoding = "$R1src";
3354 let AccessBytes = bytes;
3357 class TernaryRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
3358 bits<5> bytes, AddressingMode mode = bdaddr20only>
3359 : InstRSYb<opcode, (outs cls:$R1),
3360 (ins cls:$R1src, imm32zx4:$M3, mode:$BD2),
3361 mnemonic#"\t$R1, $M3, $BD2", []> {
3363 let Constraints = "$R1 = $R1src";
3364 let DisableEncoding = "$R1src";
3366 let AccessBytes = bytes;
3369 multiclass TernaryRSPair<string mnemonic, bits<8> rsOpcode, bits<16> rsyOpcode,
3370 RegisterOperand cls, bits<5> bytes> {
3371 let DispKey = mnemonic ## #cls in {
3372 let DispSize = "12" in
3373 def "" : TernaryRS<mnemonic, rsOpcode, cls, bytes, bdaddr12pair>;
3374 let DispSize = "20" in
3375 def Y : TernaryRSY<mnemonic#"y", rsyOpcode, cls, bytes, bdaddr20pair>;
3379 class TernaryRXF<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3380 RegisterOperand cls, SDPatternOperator load, bits<5> bytes>
3381 : InstRXF<opcode, (outs cls:$R1),
3382 (ins cls:$R1src, cls:$R3, bdxaddr12only:$XBD2),
3383 mnemonic#"\t$R1, $R3, $XBD2",
3384 [(set cls:$R1, (operator cls:$R1src, cls:$R3,
3385 (load bdxaddr12only:$XBD2)))]> {
3386 let OpKey = mnemonic#"r"#cls;
3388 let Constraints = "$R1 = $R1src";
3389 let DisableEncoding = "$R1src";
3391 let AccessBytes = bytes;
3394 class TernaryVRIa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3395 TypedReg tr1, TypedReg tr2, Immediate imm, Immediate index>
3396 : InstVRIa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V1src, imm:$I2, index:$M3),
3397 mnemonic#"\t$V1, $I2, $M3",
3398 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V1src),
3399 imm:$I2, index:$M3)))]> {
3400 let Constraints = "$V1 = $V1src";
3401 let DisableEncoding = "$V1src";
3404 class TernaryVRId<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3405 TypedReg tr1, TypedReg tr2, bits<4> type>
3406 : InstVRId<opcode, (outs tr1.op:$V1),
3407 (ins tr2.op:$V2, tr2.op:$V3, imm32zx8:$I4),
3408 mnemonic#"\t$V1, $V2, $V3, $I4",
3409 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
3410 (tr2.vt tr2.op:$V3),
3415 class TernaryVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3416 TypedReg tr1, TypedReg tr2, bits<4> type, bits<4> m4or>
3417 : InstVRRa<opcode, (outs tr1.op:$V1),
3418 (ins tr2.op:$V2, imm32zx4:$M4, imm32zx4:$M5),
3419 mnemonic#"\t$V1, $V2, $M4, $M5",
3420 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
3427 class TernaryVRRaFloatGeneric<string mnemonic, bits<16> opcode>
3428 : InstVRRa<opcode, (outs VR128:$V1),
3429 (ins VR128:$V2, imm32zx4:$M3, imm32zx4:$M4, imm32zx4:$M5),
3430 mnemonic#"\t$V1, $V2, $M3, $M4, $M5", []>;
3432 class TernaryVRRb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3433 TypedReg tr1, TypedReg tr2, bits<4> type,
3434 SDPatternOperator m5mask, bits<4> m5or>
3435 : InstVRRb<opcode, (outs tr1.op:$V1),
3436 (ins tr2.op:$V2, tr2.op:$V3, m5mask:$M5),
3437 mnemonic#"\t$V1, $V2, $V3, $M5",
3438 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
3439 (tr2.vt tr2.op:$V3),
3445 // Declare a pair of instructions, one which sets CC and one which doesn't.
3446 // The CC-setting form ends with "S" and sets the low bit of M5.
3447 // Also create aliases to make use of M5 operand optional in assembler.
3448 multiclass TernaryOptVRRbSPair<string mnemonic, bits<16> opcode,
3449 SDPatternOperator operator,
3450 SDPatternOperator operator_cc,
3451 TypedReg tr1, TypedReg tr2, bits<4> type,
3452 bits<4> modifier = 0> {
3453 def "" : TernaryVRRb<mnemonic, opcode, operator, tr1, tr2, type,
3454 imm32zx4even, !and (modifier, 14)>;
3455 def : InstAlias<mnemonic#"\t$V1, $V2, $V3",
3456 (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2,
3459 def S : TernaryVRRb<mnemonic##"s", opcode, operator_cc, tr1, tr2, type,
3460 imm32zx4even, !add(!and (modifier, 14), 1)>;
3461 def : InstAlias<mnemonic#"s\t$V1, $V2, $V3",
3462 (!cast<Instruction>(NAME#"S") tr1.op:$V1, tr2.op:$V2,
3466 multiclass TernaryOptVRRbSPairGeneric<string mnemonic, bits<16> opcode> {
3467 def "" : InstVRRb<opcode, (outs VR128:$V1),
3468 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5),
3469 mnemonic#"\t$V1, $V2, $V3, $M4, $M5", []>;
3470 def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $M4",
3471 (!cast<Instruction>(NAME) VR128:$V1, VR128:$V2, VR128:$V3,
3475 class TernaryVRRc<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3476 TypedReg tr1, TypedReg tr2>
3477 : InstVRRc<opcode, (outs tr1.op:$V1),
3478 (ins tr2.op:$V2, tr2.op:$V3, imm32zx4:$M4),
3479 mnemonic#"\t$V1, $V2, $V3, $M4",
3480 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
3481 (tr2.vt tr2.op:$V3),
3487 class TernaryVRRd<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3488 TypedReg tr1, TypedReg tr2, bits<4> type = 0>
3489 : InstVRRd<opcode, (outs tr1.op:$V1),
3490 (ins tr2.op:$V2, tr2.op:$V3, tr1.op:$V4),
3491 mnemonic#"\t$V1, $V2, $V3, $V4",
3492 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
3493 (tr2.vt tr2.op:$V3),
3494 (tr1.vt tr1.op:$V4))))]> {
3499 class TernaryVRRdGeneric<string mnemonic, bits<16> opcode>
3500 : InstVRRd<opcode, (outs VR128:$V1),
3501 (ins VR128:$V2, VR128:$V3, VR128:$V4, imm32zx4:$M5),
3502 mnemonic#"\t$V1, $V2, $V3, $V4, $M5", []> {
3506 class TernaryVRRe<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3507 TypedReg tr1, TypedReg tr2, bits<4> m5 = 0, bits<4> type = 0>
3508 : InstVRRe<opcode, (outs tr1.op:$V1),
3509 (ins tr2.op:$V2, tr2.op:$V3, tr1.op:$V4),
3510 mnemonic#"\t$V1, $V2, $V3, $V4",
3511 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
3512 (tr2.vt tr2.op:$V3),
3513 (tr1.vt tr1.op:$V4))))]> {
3518 class TernaryVRReFloatGeneric<string mnemonic, bits<16> opcode>
3519 : InstVRRe<opcode, (outs VR128:$V1),
3520 (ins VR128:$V2, VR128:$V3, VR128:$V4, imm32zx4:$M5, imm32zx4:$M6),
3521 mnemonic#"\t$V1, $V2, $V3, $V4, $M5, $M6", []>;
3523 class TernaryVRSb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3524 TypedReg tr1, TypedReg tr2, RegisterOperand cls, bits<4> type>
3525 : InstVRSb<opcode, (outs tr1.op:$V1),
3526 (ins tr2.op:$V1src, cls:$R3, shift12only:$BD2),
3527 mnemonic#"\t$V1, $R3, $BD2",
3528 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V1src),
3530 shift12only:$BD2)))]> {
3531 let Constraints = "$V1 = $V1src";
3532 let DisableEncoding = "$V1src";
3536 class TernaryVRSbGeneric<string mnemonic, bits<16> opcode>
3537 : InstVRSb<opcode, (outs VR128:$V1),
3538 (ins VR128:$V1src, GR64:$R3, shift12only:$BD2, imm32zx4:$M4),
3539 mnemonic#"\t$V1, $R3, $BD2, $M4", []> {
3540 let Constraints = "$V1 = $V1src";
3541 let DisableEncoding = "$V1src";
3544 class TernaryVRV<string mnemonic, bits<16> opcode, bits<5> bytes,
3546 : InstVRV<opcode, (outs VR128:$V1),
3547 (ins VR128:$V1src, bdvaddr12only:$VBD2, index:$M3),
3548 mnemonic#"\t$V1, $VBD2, $M3", []> {
3549 let Constraints = "$V1 = $V1src";
3550 let DisableEncoding = "$V1src";
3552 let AccessBytes = bytes;
3555 class TernaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3556 TypedReg tr1, TypedReg tr2, bits<5> bytes, Immediate index>
3557 : InstVRX<opcode, (outs tr1.op:$V1),
3558 (ins tr2.op:$V1src, bdxaddr12only:$XBD2, index:$M3),
3559 mnemonic#"\t$V1, $XBD2, $M3",
3560 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V1src),
3561 bdxaddr12only:$XBD2,
3563 let Constraints = "$V1 = $V1src";
3564 let DisableEncoding = "$V1src";
3566 let AccessBytes = bytes;
3569 class QuaternaryVRId<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3570 TypedReg tr1, TypedReg tr2, bits<4> type>
3571 : InstVRId<opcode, (outs tr1.op:$V1),
3572 (ins tr2.op:$V1src, tr2.op:$V2, tr2.op:$V3, imm32zx8:$I4),
3573 mnemonic#"\t$V1, $V2, $V3, $I4",
3574 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V1src),
3575 (tr2.vt tr2.op:$V2),
3576 (tr2.vt tr2.op:$V3),
3578 let Constraints = "$V1 = $V1src";
3579 let DisableEncoding = "$V1src";
3583 class QuaternaryVRIdGeneric<string mnemonic, bits<16> opcode>
3584 : InstVRId<opcode, (outs VR128:$V1),
3585 (ins VR128:$V1src, VR128:$V2, VR128:$V3,
3586 imm32zx8:$I4, imm32zx4:$M5),
3587 mnemonic#"\t$V1, $V2, $V3, $I4, $M5", []> {
3588 let Constraints = "$V1 = $V1src";
3589 let DisableEncoding = "$V1src";
3592 class QuaternaryVRRd<string mnemonic, bits<16> opcode,
3593 SDPatternOperator operator, TypedReg tr1, TypedReg tr2,
3594 bits<4> type, SDPatternOperator m6mask, bits<4> m6or>
3595 : InstVRRd<opcode, (outs tr1.op:$V1),
3596 (ins tr2.op:$V2, tr2.op:$V3, tr2.op:$V4, m6mask:$M6),
3597 mnemonic#"\t$V1, $V2, $V3, $V4, $M6",
3598 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
3599 (tr2.vt tr2.op:$V3),
3600 (tr2.vt tr2.op:$V4),
3606 // Declare a pair of instructions, one which sets CC and one which doesn't.
3607 // The CC-setting form ends with "S" and sets the low bit of M6.
3608 // Also create aliases to make use of M6 operand optional in assembler.
3609 multiclass QuaternaryOptVRRdSPair<string mnemonic, bits<16> opcode,
3610 SDPatternOperator operator,
3611 SDPatternOperator operator_cc,
3612 TypedReg tr1, TypedReg tr2, bits<4> type,
3613 bits<4> modifier = 0> {
3614 def "" : QuaternaryVRRd<mnemonic, opcode, operator, tr1, tr2, type,
3615 imm32zx4even, !and (modifier, 14)>;
3616 def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $V4",
3617 (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2,
3618 tr2.op:$V3, tr2.op:$V4, 0)>;
3620 def S : QuaternaryVRRd<mnemonic##"s", opcode, operator_cc, tr1, tr2, type,
3621 imm32zx4even, !add (!and (modifier, 14), 1)>;
3622 def : InstAlias<mnemonic#"s\t$V1, $V2, $V3, $V4",
3623 (!cast<Instruction>(NAME#"S") tr1.op:$V1, tr2.op:$V2,
3624 tr2.op:$V3, tr2.op:$V4, 0)>;
3627 multiclass QuaternaryOptVRRdSPairGeneric<string mnemonic, bits<16> opcode> {
3628 def "" : InstVRRd<opcode, (outs VR128:$V1),
3629 (ins VR128:$V2, VR128:$V3, VR128:$V4,
3630 imm32zx4:$M5, imm32zx4:$M6),
3631 mnemonic#"\t$V1, $V2, $V3, $V4, $M5, $M6", []>;
3632 def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $V4, $M5",
3633 (!cast<Instruction>(NAME) VR128:$V1, VR128:$V2, VR128:$V3,
3634 VR128:$V4, imm32zx4:$M5, 0)>;
3637 class SideEffectQuaternarySSe<string mnemonic, bits<8> opcode,
3638 RegisterOperand cls>
3639 : InstSSe<opcode, (outs),
3640 (ins cls:$R1, bdaddr12only:$BD2, cls:$R3, bdaddr12only:$BD4),
3641 mnemonic#"\t$R1, $BD2, $R3, $BD4", []>;
3643 class LoadAndOpRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3644 RegisterOperand cls, AddressingMode mode = bdaddr20only>
3645 : InstRSYa<opcode, (outs cls:$R1), (ins cls:$R3, mode:$BD2),
3646 mnemonic#"\t$R1, $R3, $BD2",
3647 [(set cls:$R1, (operator mode:$BD2, cls:$R3))]> {
3652 class CmpSwapRS<string mnemonic, bits<8> opcode, SDPatternOperator operator,
3653 RegisterOperand cls, AddressingMode mode = bdaddr12only>
3654 : InstRSa<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, mode:$BD2),
3655 mnemonic#"\t$R1, $R3, $BD2",
3656 [(set cls:$R1, (operator mode:$BD2, cls:$R1src, cls:$R3))]> {
3657 let Constraints = "$R1 = $R1src";
3658 let DisableEncoding = "$R1src";
3663 class CmpSwapRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3664 RegisterOperand cls, AddressingMode mode = bdaddr20only>
3665 : InstRSYa<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, mode:$BD2),
3666 mnemonic#"\t$R1, $R3, $BD2",
3667 [(set cls:$R1, (operator mode:$BD2, cls:$R1src, cls:$R3))]> {
3668 let Constraints = "$R1 = $R1src";
3669 let DisableEncoding = "$R1src";
3674 multiclass CmpSwapRSPair<string mnemonic, bits<8> rsOpcode, bits<16> rsyOpcode,
3675 SDPatternOperator operator, RegisterOperand cls> {
3676 let DispKey = mnemonic ## #cls in {
3677 let DispSize = "12" in
3678 def "" : CmpSwapRS<mnemonic, rsOpcode, operator, cls, bdaddr12pair>;
3679 let DispSize = "20" in
3680 def Y : CmpSwapRSY<mnemonic#"y", rsyOpcode, operator, cls, bdaddr20pair>;
3684 class RotateSelectRIEf<string mnemonic, bits<16> opcode, RegisterOperand cls1,
3685 RegisterOperand cls2>
3686 : InstRIEf<opcode, (outs cls1:$R1),
3687 (ins cls1:$R1src, cls2:$R2, imm32zx8:$I3, imm32zx8:$I4,
3689 mnemonic#"\t$R1, $R2, $I3, $I4, $I5", []> {
3690 let Constraints = "$R1 = $R1src";
3691 let DisableEncoding = "$R1src";
3694 class PrefetchRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator>
3695 : InstRXYb<opcode, (outs), (ins imm32zx4:$M1, bdxaddr20only:$XBD2),
3696 mnemonic##"\t$M1, $XBD2",
3697 [(operator imm32zx4:$M1, bdxaddr20only:$XBD2)]>;
3699 class PrefetchRILPC<string mnemonic, bits<12> opcode,
3700 SDPatternOperator operator>
3701 : InstRILc<opcode, (outs), (ins imm32zx4:$M1, pcrel32:$RI2),
3702 mnemonic##"\t$M1, $RI2",
3703 [(operator imm32zx4:$M1, pcrel32:$RI2)]> {
3704 // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
3705 // However, BDXs have two extra operands and are therefore 6 units more
3707 let AddedComplexity = 7;
3710 class BranchPreloadSMI<string mnemonic, bits<8> opcode>
3711 : InstSMI<opcode, (outs),
3712 (ins imm32zx4:$M1, brtarget16bpp:$RI2, bdxaddr12only:$BD3),
3713 mnemonic#"\t$M1, $RI2, $BD3", []>;
3715 class BranchPreloadMII<string mnemonic, bits<8> opcode>
3716 : InstMII<opcode, (outs),
3717 (ins imm32zx4:$M1, brtarget12bpp:$RI2, brtarget24bpp:$RI3),
3718 mnemonic#"\t$M1, $RI2, $RI3", []>;
3720 // A floating-point load-and test operation. Create both a normal unary
3721 // operation and one that acts as a comparison against zero.
3722 // Note that the comparison against zero operation is not available if we
3723 // have vector support, since load-and-test instructions will partially
3724 // clobber the target (vector) register.
3725 multiclass LoadAndTestRRE<string mnemonic, bits<16> opcode,
3726 RegisterOperand cls> {
3727 def "" : UnaryRRE<mnemonic, opcode, null_frag, cls, cls>;
3728 let isCodeGenOnly = 1, Predicates = [FeatureNoVector] in
3729 def Compare : CompareRRE<mnemonic, opcode, null_frag, cls, cls>;
3732 //===----------------------------------------------------------------------===//
3733 // Pseudo instructions
3734 //===----------------------------------------------------------------------===//
3736 // Convenience instructions that get lowered to real instructions
3737 // by either SystemZTargetLowering::EmitInstrWithCustomInserter()
3738 // or SystemZInstrInfo::expandPostRAPseudo().
3740 //===----------------------------------------------------------------------===//
3742 class Pseudo<dag outs, dag ins, list<dag> pattern>
3743 : InstSystemZ<0, outs, ins, "", pattern> {
3745 let isCodeGenOnly = 1;
3748 // Like SideEffectBinarySIL, but expanded later.
3749 class SideEffectBinarySILPseudo<SDPatternOperator operator, Immediate imm>
3750 : Pseudo<(outs), (ins bdaddr12only:$BD1, imm:$I2),
3751 [(operator bdaddr12only:$BD1, imm:$I2)]>;
3753 // Like UnaryRI, but expanded after RA depending on the choice of register.
3754 class UnaryRIPseudo<SDPatternOperator operator, RegisterOperand cls,
3756 : Pseudo<(outs cls:$R1), (ins imm:$I2),
3757 [(set cls:$R1, (operator imm:$I2))]>;
3759 // Like UnaryRXY, but expanded after RA depending on the choice of register.
3760 class UnaryRXYPseudo<string key, SDPatternOperator operator,
3761 RegisterOperand cls, bits<5> bytes,
3762 AddressingMode mode = bdxaddr20only>
3763 : Pseudo<(outs cls:$R1), (ins mode:$XBD2),
3764 [(set cls:$R1, (operator mode:$XBD2))]> {
3765 let OpKey = key#"r"#cls;
3768 let Has20BitOffset = 1;
3770 let AccessBytes = bytes;
3773 // Like UnaryRR, but expanded after RA depending on the choice of registers.
3774 class UnaryRRPseudo<string key, SDPatternOperator operator,
3775 RegisterOperand cls1, RegisterOperand cls2>
3776 : Pseudo<(outs cls1:$R1), (ins cls2:$R2),
3777 [(set cls1:$R1, (operator cls2:$R2))]> {
3778 let OpKey = key#cls1;
3782 // Like BinaryRI, but expanded after RA depending on the choice of register.
3783 class BinaryRIPseudo<SDPatternOperator operator, RegisterOperand cls,
3785 : Pseudo<(outs cls:$R1), (ins cls:$R1src, imm:$I2),
3786 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
3787 let Constraints = "$R1 = $R1src";
3790 // Like BinaryRIE, but expanded after RA depending on the choice of register.
3791 class BinaryRIEPseudo<SDPatternOperator operator, RegisterOperand cls,
3793 : Pseudo<(outs cls:$R1), (ins cls:$R3, imm:$I2),
3794 [(set cls:$R1, (operator cls:$R3, imm:$I2))]>;
3796 // Like BinaryRIAndK, but expanded after RA depending on the choice of register.
3797 multiclass BinaryRIAndKPseudo<string key, SDPatternOperator operator,
3798 RegisterOperand cls, Immediate imm> {
3799 let NumOpsKey = key in {
3800 let NumOpsValue = "3" in
3801 def K : BinaryRIEPseudo<null_frag, cls, imm>,
3802 Requires<[FeatureHighWord, FeatureDistinctOps]>;
3803 let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in
3804 def "" : BinaryRIPseudo<operator, cls, imm>,
3805 Requires<[FeatureHighWord]>;
3809 // Like CompareRI, but expanded after RA depending on the choice of register.
3810 class CompareRIPseudo<SDPatternOperator operator, RegisterOperand cls,
3812 : Pseudo<(outs), (ins cls:$R1, imm:$I2), [(operator cls:$R1, imm:$I2)]> {
3816 // Like CompareRXY, but expanded after RA depending on the choice of register.
3817 class CompareRXYPseudo<SDPatternOperator operator, RegisterOperand cls,
3818 SDPatternOperator load, bits<5> bytes,
3819 AddressingMode mode = bdxaddr20only>
3820 : Pseudo<(outs), (ins cls:$R1, mode:$XBD2),
3821 [(operator cls:$R1, (load mode:$XBD2))]> {
3823 let Has20BitOffset = 1;
3825 let AccessBytes = bytes;
3828 // Like CondBinaryRRF, but expanded after RA depending on the choice of
3830 class CondBinaryRRFPseudo<RegisterOperand cls1, RegisterOperand cls2>
3831 : Pseudo<(outs cls1:$R1),
3832 (ins cls1:$R1src, cls2:$R2, cond4:$valid, cond4:$M3), []> {
3833 let Constraints = "$R1 = $R1src";
3834 let DisableEncoding = "$R1src";
3838 // Like CondBinaryRIE, but expanded after RA depending on the choice of
3840 class CondBinaryRIEPseudo<RegisterOperand cls, Immediate imm>
3841 : Pseudo<(outs cls:$R1),
3842 (ins cls:$R1src, imm:$I2, cond4:$valid, cond4:$M3),
3843 [(set cls:$R1, (z_select_ccmask imm:$I2, cls:$R1src,
3844 cond4:$valid, cond4:$M3))]> {
3845 let Constraints = "$R1 = $R1src";
3846 let DisableEncoding = "$R1src";
3850 // Like CondUnaryRSY, but expanded after RA depending on the choice of
3852 class CondUnaryRSYPseudo<SDPatternOperator operator, RegisterOperand cls,
3853 bits<5> bytes, AddressingMode mode = bdaddr20only>
3854 : Pseudo<(outs cls:$R1),
3855 (ins cls:$R1src, mode:$BD2, cond4:$valid, cond4:$R3),
3857 (z_select_ccmask (operator mode:$BD2), cls:$R1src,
3858 cond4:$valid, cond4:$R3))]> {
3859 let Constraints = "$R1 = $R1src";
3860 let DisableEncoding = "$R1src";
3862 let AccessBytes = bytes;
3866 // Like CondStoreRSY, but expanded after RA depending on the choice of
3868 class CondStoreRSYPseudo<RegisterOperand cls, bits<5> bytes,
3869 AddressingMode mode = bdaddr20only>
3870 : Pseudo<(outs), (ins cls:$R1, mode:$BD2, cond4:$valid, cond4:$R3), []> {
3872 let AccessBytes = bytes;
3876 // Like StoreRXY, but expanded after RA depending on the choice of register.
3877 class StoreRXYPseudo<SDPatternOperator operator, RegisterOperand cls,
3878 bits<5> bytes, AddressingMode mode = bdxaddr20only>
3879 : Pseudo<(outs), (ins cls:$R1, mode:$XBD2),
3880 [(operator cls:$R1, mode:$XBD2)]> {
3882 let Has20BitOffset = 1;
3884 let AccessBytes = bytes;
3887 // Like RotateSelectRIEf, but expanded after RA depending on the choice
3889 class RotateSelectRIEfPseudo<RegisterOperand cls1, RegisterOperand cls2>
3890 : Pseudo<(outs cls1:$R1),
3891 (ins cls1:$R1src, cls2:$R2, imm32zx8:$I3, imm32zx8:$I4,
3894 let Constraints = "$R1 = $R1src";
3895 let DisableEncoding = "$R1src";
3898 // Implements "$dst = $cc & (8 >> CC) ? $src1 : $src2", where CC is
3899 // the value of the PSW's 2-bit condition code field.
3900 class SelectWrapper<RegisterOperand cls>
3901 : Pseudo<(outs cls:$dst),
3902 (ins cls:$src1, cls:$src2, imm32zx4:$valid, imm32zx4:$cc),
3903 [(set cls:$dst, (z_select_ccmask cls:$src1, cls:$src2,
3904 imm32zx4:$valid, imm32zx4:$cc))]> {
3905 let usesCustomInserter = 1;
3906 // Although the instructions used by these nodes do not in themselves
3907 // change CC, the insertion requires new blocks, and CC cannot be live
3913 // Stores $new to $addr if $cc is true ("" case) or false (Inv case).
3914 multiclass CondStores<RegisterOperand cls, SDPatternOperator store,
3915 SDPatternOperator load, AddressingMode mode> {
3916 let Defs = [CC], Uses = [CC], usesCustomInserter = 1 in {
3917 def "" : Pseudo<(outs),
3918 (ins cls:$new, mode:$addr, imm32zx4:$valid, imm32zx4:$cc),
3919 [(store (z_select_ccmask cls:$new, (load mode:$addr),
3920 imm32zx4:$valid, imm32zx4:$cc),
3922 def Inv : Pseudo<(outs),
3923 (ins cls:$new, mode:$addr, imm32zx4:$valid, imm32zx4:$cc),
3924 [(store (z_select_ccmask (load mode:$addr), cls:$new,
3925 imm32zx4:$valid, imm32zx4:$cc),
3930 // OPERATOR is ATOMIC_SWAP or an ATOMIC_LOAD_* operation. PAT and OPERAND
3931 // describe the second (non-memory) operand.
3932 class AtomicLoadBinary<SDPatternOperator operator, RegisterOperand cls,
3933 dag pat, DAGOperand operand>
3934 : Pseudo<(outs cls:$dst), (ins bdaddr20only:$ptr, operand:$src2),
3935 [(set cls:$dst, (operator bdaddr20only:$ptr, pat))]> {
3937 let Has20BitOffset = 1;
3940 let usesCustomInserter = 1;
3941 let hasNoSchedulingInfo = 1;
3944 // Specializations of AtomicLoadWBinary.
3945 class AtomicLoadBinaryReg32<SDPatternOperator operator>
3946 : AtomicLoadBinary<operator, GR32, (i32 GR32:$src2), GR32>;
3947 class AtomicLoadBinaryImm32<SDPatternOperator operator, Immediate imm>
3948 : AtomicLoadBinary<operator, GR32, (i32 imm:$src2), imm>;
3949 class AtomicLoadBinaryReg64<SDPatternOperator operator>
3950 : AtomicLoadBinary<operator, GR64, (i64 GR64:$src2), GR64>;
3951 class AtomicLoadBinaryImm64<SDPatternOperator operator, Immediate imm>
3952 : AtomicLoadBinary<operator, GR64, (i64 imm:$src2), imm>;
3954 // OPERATOR is ATOMIC_SWAPW or an ATOMIC_LOADW_* operation. PAT and OPERAND
3955 // describe the second (non-memory) operand.
3956 class AtomicLoadWBinary<SDPatternOperator operator, dag pat,
3958 : Pseudo<(outs GR32:$dst),
3959 (ins bdaddr20only:$ptr, operand:$src2, ADDR32:$bitshift,
3960 ADDR32:$negbitshift, uimm32:$bitsize),
3961 [(set GR32:$dst, (operator bdaddr20only:$ptr, pat, ADDR32:$bitshift,
3962 ADDR32:$negbitshift, uimm32:$bitsize))]> {
3964 let Has20BitOffset = 1;
3967 let usesCustomInserter = 1;
3968 let hasNoSchedulingInfo = 1;
3971 // Specializations of AtomicLoadWBinary.
3972 class AtomicLoadWBinaryReg<SDPatternOperator operator>
3973 : AtomicLoadWBinary<operator, (i32 GR32:$src2), GR32>;
3974 class AtomicLoadWBinaryImm<SDPatternOperator operator, Immediate imm>
3975 : AtomicLoadWBinary<operator, (i32 imm:$src2), imm>;
3977 // Define an instruction that operates on two fixed-length blocks of memory,
3978 // and associated pseudo instructions for operating on blocks of any size.
3979 // The Sequence form uses a straight-line sequence of instructions and
3980 // the Loop form uses a loop of length-256 instructions followed by
3981 // another instruction to handle the excess.
3982 multiclass MemorySS<string mnemonic, bits<8> opcode,
3983 SDPatternOperator sequence, SDPatternOperator loop> {
3984 def "" : InstSSa<opcode, (outs), (ins bdladdr12onlylen8:$BDL1,
3986 mnemonic##"\t$BDL1, $BD2", []>;
3987 let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in {
3988 def Sequence : Pseudo<(outs), (ins bdaddr12only:$dest, bdaddr12only:$src,
3990 [(sequence bdaddr12only:$dest, bdaddr12only:$src,
3992 def Loop : Pseudo<(outs), (ins bdaddr12only:$dest, bdaddr12only:$src,
3993 imm64:$length, GR64:$count256),
3994 [(loop bdaddr12only:$dest, bdaddr12only:$src,
3995 imm64:$length, GR64:$count256)]>;
3999 // Define an instruction that operates on two strings, both terminated
4000 // by the character in R0. The instruction processes a CPU-determinated
4001 // number of bytes at a time and sets CC to 3 if the instruction needs
4002 // to be repeated. Also define a pseudo instruction that represents
4003 // the full loop (the main instruction plus the branch on CC==3).
4004 multiclass StringRRE<string mnemonic, bits<16> opcode,
4005 SDPatternOperator operator> {
4006 def "" : InstRRE<opcode, (outs GR64:$R1, GR64:$R2),
4007 (ins GR64:$R1src, GR64:$R2src),
4008 mnemonic#"\t$R1, $R2", []> {
4010 let Constraints = "$R1 = $R1src, $R2 = $R2src";
4011 let DisableEncoding = "$R1src, $R2src";
4013 let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in
4014 def Loop : Pseudo<(outs GR64:$end),
4015 (ins GR64:$start1, GR64:$start2, GR32:$char),
4016 [(set GR64:$end, (operator GR64:$start1, GR64:$start2,
4020 // A pseudo instruction that is a direct alias of a real instruction.
4021 // These aliases are used in cases where a particular register operand is
4022 // fixed or where the same instruction is used with different register sizes.
4023 // The size parameter is the size in bytes of the associated real instruction.
4024 class Alias<int size, dag outs, dag ins, list<dag> pattern>
4025 : InstSystemZ<size, outs, ins, "", pattern> {
4027 let isCodeGenOnly = 1;
4030 class UnaryAliasVRS<RegisterOperand cls1, RegisterOperand cls2>
4031 : Alias<6, (outs cls1:$src1), (ins cls2:$src2), []>;
4033 // An alias of a UnaryVRR*, but with different register sizes.
4034 class UnaryAliasVRR<SDPatternOperator operator, TypedReg tr1, TypedReg tr2>
4035 : Alias<6, (outs tr1.op:$V1), (ins tr2.op:$V2),
4036 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2))))]>;
4038 // An alias of a UnaryVRX, but with different register sizes.
4039 class UnaryAliasVRX<SDPatternOperator operator, TypedReg tr,
4040 AddressingMode mode = bdxaddr12only>
4041 : Alias<6, (outs tr.op:$V1), (ins mode:$XBD2),
4042 [(set tr.op:$V1, (tr.vt (operator mode:$XBD2)))]>;
4044 // An alias of a StoreVRX, but with different register sizes.
4045 class StoreAliasVRX<SDPatternOperator operator, TypedReg tr,
4046 AddressingMode mode = bdxaddr12only>
4047 : Alias<6, (outs), (ins tr.op:$V1, mode:$XBD2),
4048 [(operator (tr.vt tr.op:$V1), mode:$XBD2)]>;
4050 // An alias of a BinaryRI, but with different register sizes.
4051 class BinaryAliasRI<SDPatternOperator operator, RegisterOperand cls,
4053 : Alias<4, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
4054 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
4055 let Constraints = "$R1 = $R1src";
4058 // An alias of a BinaryRIL, but with different register sizes.
4059 class BinaryAliasRIL<SDPatternOperator operator, RegisterOperand cls,
4061 : Alias<6, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
4062 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
4063 let Constraints = "$R1 = $R1src";
4066 // An alias of a BinaryVRRf, but with different register sizes.
4067 class BinaryAliasVRRf<RegisterOperand cls>
4068 : Alias<6, (outs VR128:$V1), (ins cls:$R2, cls:$R3), []>;
4070 // An alias of a CompareRI, but with different register sizes.
4071 class CompareAliasRI<SDPatternOperator operator, RegisterOperand cls,
4073 : Alias<4, (outs), (ins cls:$R1, imm:$I2), [(operator cls:$R1, imm:$I2)]> {
4077 // An alias of a RotateSelectRIEf, but with different register sizes.
4078 class RotateSelectAliasRIEf<RegisterOperand cls1, RegisterOperand cls2>
4079 : Alias<6, (outs cls1:$R1),
4080 (ins cls1:$R1src, cls2:$R2, imm32zx8:$I3, imm32zx8:$I4,
4081 imm32zx6:$I5), []> {
4082 let Constraints = "$R1 = $R1src";