1 //===-- SystemZInstrInfo.cpp - SystemZ instruction information ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the SystemZ implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "MCTargetDesc/SystemZMCTargetDesc.h"
16 #include "SystemZInstrBuilder.h"
17 #include "SystemZInstrInfo.h"
18 #include "SystemZSubtarget.h"
19 #include "llvm/CodeGen/LiveInterval.h"
20 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
21 #include "llvm/CodeGen/LiveVariables.h"
22 #include "llvm/CodeGen/MachineBasicBlock.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineInstr.h"
26 #include "llvm/CodeGen/MachineMemOperand.h"
27 #include "llvm/CodeGen/MachineOperand.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/CodeGen/SlotIndexes.h"
30 #include "llvm/MC/MCInstrDesc.h"
31 #include "llvm/MC/MCRegisterInfo.h"
32 #include "llvm/Support/BranchProbability.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/MathExtras.h"
35 #include "llvm/Target/TargetInstrInfo.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetSubtargetInfo.h"
44 #define GET_INSTRINFO_CTOR_DTOR
45 #define GET_INSTRMAP_INFO
46 #include "SystemZGenInstrInfo.inc"
48 // Return a mask with Count low bits set.
49 static uint64_t allOnes(unsigned int Count) {
50 return Count == 0 ? 0 : (uint64_t(1) << (Count - 1) << 1) - 1;
53 // Reg should be a 32-bit GPR. Return true if it is a high register rather
54 // than a low register.
55 static bool isHighReg(unsigned int Reg) {
56 if (SystemZ::GRH32BitRegClass.contains(Reg))
58 assert(SystemZ::GR32BitRegClass.contains(Reg) && "Invalid GRX32");
62 // Pin the vtable to this file.
63 void SystemZInstrInfo::anchor() {}
65 SystemZInstrInfo::SystemZInstrInfo(SystemZSubtarget &sti)
66 : SystemZGenInstrInfo(SystemZ::ADJCALLSTACKDOWN, SystemZ::ADJCALLSTACKUP),
70 // MI is a 128-bit load or store. Split it into two 64-bit loads or stores,
71 // each having the opcode given by NewOpcode.
72 void SystemZInstrInfo::splitMove(MachineBasicBlock::iterator MI,
73 unsigned NewOpcode) const {
74 MachineBasicBlock *MBB = MI->getParent();
75 MachineFunction &MF = *MBB->getParent();
77 // Get two load or store instructions. Use the original instruction for one
78 // of them (arbitrarily the second here) and create a clone for the other.
79 MachineInstr *EarlierMI = MF.CloneMachineInstr(&*MI);
80 MBB->insert(MI, EarlierMI);
82 // Set up the two 64-bit registers and remember super reg and its flags.
83 MachineOperand &HighRegOp = EarlierMI->getOperand(0);
84 MachineOperand &LowRegOp = MI->getOperand(0);
85 unsigned Reg128 = LowRegOp.getReg();
86 unsigned Reg128Killed = getKillRegState(LowRegOp.isKill());
87 unsigned Reg128Undef = getUndefRegState(LowRegOp.isUndef());
88 HighRegOp.setReg(RI.getSubReg(HighRegOp.getReg(), SystemZ::subreg_h64));
89 LowRegOp.setReg(RI.getSubReg(LowRegOp.getReg(), SystemZ::subreg_l64));
92 // Add implicit uses of the super register in case one of the subregs is
93 // undefined. We could track liveness and skip storing an undefined
94 // subreg, but this is hopefully rare (discovered with llvm-stress).
95 // If Reg128 was killed, set kill flag on MI.
96 unsigned Reg128UndefImpl = (Reg128Undef | RegState::Implicit);
97 MachineInstrBuilder(MF, EarlierMI).addReg(Reg128, Reg128UndefImpl);
98 MachineInstrBuilder(MF, MI).addReg(Reg128, (Reg128UndefImpl | Reg128Killed));
101 // The address in the first (high) instruction is already correct.
102 // Adjust the offset in the second (low) instruction.
103 MachineOperand &HighOffsetOp = EarlierMI->getOperand(2);
104 MachineOperand &LowOffsetOp = MI->getOperand(2);
105 LowOffsetOp.setImm(LowOffsetOp.getImm() + 8);
107 // Clear the kill flags for the base and index registers in the first
109 EarlierMI->getOperand(1).setIsKill(false);
110 EarlierMI->getOperand(3).setIsKill(false);
113 unsigned HighOpcode = getOpcodeForOffset(NewOpcode, HighOffsetOp.getImm());
114 unsigned LowOpcode = getOpcodeForOffset(NewOpcode, LowOffsetOp.getImm());
115 assert(HighOpcode && LowOpcode && "Both offsets should be in range");
117 EarlierMI->setDesc(get(HighOpcode));
118 MI->setDesc(get(LowOpcode));
121 // Split ADJDYNALLOC instruction MI.
122 void SystemZInstrInfo::splitAdjDynAlloc(MachineBasicBlock::iterator MI) const {
123 MachineBasicBlock *MBB = MI->getParent();
124 MachineFunction &MF = *MBB->getParent();
125 MachineFrameInfo &MFFrame = MF.getFrameInfo();
126 MachineOperand &OffsetMO = MI->getOperand(2);
128 uint64_t Offset = (MFFrame.getMaxCallFrameSize() +
129 SystemZMC::CallFrameSize +
131 unsigned NewOpcode = getOpcodeForOffset(SystemZ::LA, Offset);
132 assert(NewOpcode && "No support for huge argument lists yet");
133 MI->setDesc(get(NewOpcode));
134 OffsetMO.setImm(Offset);
137 // MI is an RI-style pseudo instruction. Replace it with LowOpcode
138 // if the first operand is a low GR32 and HighOpcode if the first operand
139 // is a high GR32. ConvertHigh is true if LowOpcode takes a signed operand
140 // and HighOpcode takes an unsigned 32-bit operand. In those cases,
141 // MI has the same kind of operand as LowOpcode, so needs to be converted
142 // if HighOpcode is used.
143 void SystemZInstrInfo::expandRIPseudo(MachineInstr &MI, unsigned LowOpcode,
145 bool ConvertHigh) const {
146 unsigned Reg = MI.getOperand(0).getReg();
147 bool IsHigh = isHighReg(Reg);
148 MI.setDesc(get(IsHigh ? HighOpcode : LowOpcode));
149 if (IsHigh && ConvertHigh)
150 MI.getOperand(1).setImm(uint32_t(MI.getOperand(1).getImm()));
153 // MI is a three-operand RIE-style pseudo instruction. Replace it with
154 // LowOpcodeK if the registers are both low GR32s, otherwise use a move
155 // followed by HighOpcode or LowOpcode, depending on whether the target
156 // is a high or low GR32.
157 void SystemZInstrInfo::expandRIEPseudo(MachineInstr &MI, unsigned LowOpcode,
159 unsigned HighOpcode) const {
160 unsigned DestReg = MI.getOperand(0).getReg();
161 unsigned SrcReg = MI.getOperand(1).getReg();
162 bool DestIsHigh = isHighReg(DestReg);
163 bool SrcIsHigh = isHighReg(SrcReg);
164 if (!DestIsHigh && !SrcIsHigh)
165 MI.setDesc(get(LowOpcodeK));
167 emitGRX32Move(*MI.getParent(), MI, MI.getDebugLoc(), DestReg, SrcReg,
168 SystemZ::LR, 32, MI.getOperand(1).isKill(),
169 MI.getOperand(1).isUndef());
170 MI.setDesc(get(DestIsHigh ? HighOpcode : LowOpcode));
171 MI.getOperand(1).setReg(DestReg);
172 MI.tieOperands(0, 1);
176 // MI is an RXY-style pseudo instruction. Replace it with LowOpcode
177 // if the first operand is a low GR32 and HighOpcode if the first operand
179 void SystemZInstrInfo::expandRXYPseudo(MachineInstr &MI, unsigned LowOpcode,
180 unsigned HighOpcode) const {
181 unsigned Reg = MI.getOperand(0).getReg();
182 unsigned Opcode = getOpcodeForOffset(isHighReg(Reg) ? HighOpcode : LowOpcode,
183 MI.getOperand(2).getImm());
184 MI.setDesc(get(Opcode));
187 // MI is a load-on-condition pseudo instruction with a single register
188 // (source or destination) operand. Replace it with LowOpcode if the
189 // register is a low GR32 and HighOpcode if the register is a high GR32.
190 void SystemZInstrInfo::expandLOCPseudo(MachineInstr &MI, unsigned LowOpcode,
191 unsigned HighOpcode) const {
192 unsigned Reg = MI.getOperand(0).getReg();
193 unsigned Opcode = isHighReg(Reg) ? HighOpcode : LowOpcode;
194 MI.setDesc(get(Opcode));
197 // MI is a load-register-on-condition pseudo instruction. Replace it with
198 // LowOpcode if source and destination are both low GR32s and HighOpcode if
199 // source and destination are both high GR32s.
200 void SystemZInstrInfo::expandLOCRPseudo(MachineInstr &MI, unsigned LowOpcode,
201 unsigned HighOpcode) const {
202 unsigned DestReg = MI.getOperand(0).getReg();
203 unsigned SrcReg = MI.getOperand(2).getReg();
204 bool DestIsHigh = isHighReg(DestReg);
205 bool SrcIsHigh = isHighReg(SrcReg);
207 if (!DestIsHigh && !SrcIsHigh)
208 MI.setDesc(get(LowOpcode));
209 else if (DestIsHigh && SrcIsHigh)
210 MI.setDesc(get(HighOpcode));
212 // If we were unable to implement the pseudo with a single instruction, we
213 // need to convert it back into a branch sequence. This cannot be done here
214 // since the caller of expandPostRAPseudo does not handle changes to the CFG
215 // correctly. This change is defered to the SystemZExpandPseudo pass.
218 // MI is an RR-style pseudo instruction that zero-extends the low Size bits
219 // of one GRX32 into another. Replace it with LowOpcode if both operands
220 // are low registers, otherwise use RISB[LH]G.
221 void SystemZInstrInfo::expandZExtPseudo(MachineInstr &MI, unsigned LowOpcode,
222 unsigned Size) const {
223 MachineInstrBuilder MIB =
224 emitGRX32Move(*MI.getParent(), MI, MI.getDebugLoc(),
225 MI.getOperand(0).getReg(), MI.getOperand(1).getReg(), LowOpcode,
226 Size, MI.getOperand(1).isKill(), MI.getOperand(1).isUndef());
228 // Keep the remaining operands as-is.
229 for (unsigned I = 2; I < MI.getNumOperands(); ++I)
230 MIB.add(MI.getOperand(I));
232 MI.eraseFromParent();
235 void SystemZInstrInfo::expandLoadStackGuard(MachineInstr *MI) const {
236 MachineBasicBlock *MBB = MI->getParent();
237 MachineFunction &MF = *MBB->getParent();
238 const unsigned Reg = MI->getOperand(0).getReg();
240 // Conveniently, all 4 instructions are cloned from LOAD_STACK_GUARD,
241 // so they already have operand 0 set to reg.
244 MachineInstr *Ear1MI = MF.CloneMachineInstr(MI);
245 MBB->insert(MI, Ear1MI);
246 Ear1MI->setDesc(get(SystemZ::EAR));
247 MachineInstrBuilder(MF, Ear1MI).addReg(SystemZ::A0);
249 // sllg <reg>, <reg>, 32
250 MachineInstr *SllgMI = MF.CloneMachineInstr(MI);
251 MBB->insert(MI, SllgMI);
252 SllgMI->setDesc(get(SystemZ::SLLG));
253 MachineInstrBuilder(MF, SllgMI).addReg(Reg).addReg(0).addImm(32);
256 MachineInstr *Ear2MI = MF.CloneMachineInstr(MI);
257 MBB->insert(MI, Ear2MI);
258 Ear2MI->setDesc(get(SystemZ::EAR));
259 MachineInstrBuilder(MF, Ear2MI).addReg(SystemZ::A1);
261 // lg <reg>, 40(<reg>)
262 MI->setDesc(get(SystemZ::LG));
263 MachineInstrBuilder(MF, MI).addReg(Reg).addImm(40).addReg(0);
266 // Emit a zero-extending move from 32-bit GPR SrcReg to 32-bit GPR
267 // DestReg before MBBI in MBB. Use LowLowOpcode when both DestReg and SrcReg
268 // are low registers, otherwise use RISB[LH]G. Size is the number of bits
269 // taken from the low end of SrcReg (8 for LLCR, 16 for LLHR and 32 for LR).
270 // KillSrc is true if this move is the last use of SrcReg.
272 SystemZInstrInfo::emitGRX32Move(MachineBasicBlock &MBB,
273 MachineBasicBlock::iterator MBBI,
274 const DebugLoc &DL, unsigned DestReg,
275 unsigned SrcReg, unsigned LowLowOpcode,
276 unsigned Size, bool KillSrc,
277 bool UndefSrc) const {
279 bool DestIsHigh = isHighReg(DestReg);
280 bool SrcIsHigh = isHighReg(SrcReg);
281 if (DestIsHigh && SrcIsHigh)
282 Opcode = SystemZ::RISBHH;
283 else if (DestIsHigh && !SrcIsHigh)
284 Opcode = SystemZ::RISBHL;
285 else if (!DestIsHigh && SrcIsHigh)
286 Opcode = SystemZ::RISBLH;
288 return BuildMI(MBB, MBBI, DL, get(LowLowOpcode), DestReg)
289 .addReg(SrcReg, getKillRegState(KillSrc) | getUndefRegState(UndefSrc));
291 unsigned Rotate = (DestIsHigh != SrcIsHigh ? 32 : 0);
292 return BuildMI(MBB, MBBI, DL, get(Opcode), DestReg)
293 .addReg(DestReg, RegState::Undef)
294 .addReg(SrcReg, getKillRegState(KillSrc) | getUndefRegState(UndefSrc))
295 .addImm(32 - Size).addImm(128 + 31).addImm(Rotate);
298 MachineInstr *SystemZInstrInfo::commuteInstructionImpl(MachineInstr &MI,
301 unsigned OpIdx2) const {
302 auto cloneIfNew = [NewMI](MachineInstr &MI) -> MachineInstr & {
304 return *MI.getParent()->getParent()->CloneMachineInstr(&MI);
308 switch (MI.getOpcode()) {
309 case SystemZ::LOCRMux:
310 case SystemZ::LOCFHR:
312 case SystemZ::LOCGR: {
313 auto &WorkingMI = cloneIfNew(MI);
315 unsigned CCValid = WorkingMI.getOperand(3).getImm();
316 unsigned CCMask = WorkingMI.getOperand(4).getImm();
317 WorkingMI.getOperand(4).setImm(CCMask ^ CCValid);
318 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
322 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
326 // If MI is a simple load or store for a frame object, return the register
327 // it loads or stores and set FrameIndex to the index of the frame object.
328 // Return 0 otherwise.
330 // Flag is SimpleBDXLoad for loads and SimpleBDXStore for stores.
331 static int isSimpleMove(const MachineInstr &MI, int &FrameIndex,
333 const MCInstrDesc &MCID = MI.getDesc();
334 if ((MCID.TSFlags & Flag) && MI.getOperand(1).isFI() &&
335 MI.getOperand(2).getImm() == 0 && MI.getOperand(3).getReg() == 0) {
336 FrameIndex = MI.getOperand(1).getIndex();
337 return MI.getOperand(0).getReg();
342 unsigned SystemZInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
343 int &FrameIndex) const {
344 return isSimpleMove(MI, FrameIndex, SystemZII::SimpleBDXLoad);
347 unsigned SystemZInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
348 int &FrameIndex) const {
349 return isSimpleMove(MI, FrameIndex, SystemZII::SimpleBDXStore);
352 bool SystemZInstrInfo::isStackSlotCopy(const MachineInstr &MI,
354 int &SrcFrameIndex) const {
355 // Check for MVC 0(Length,FI1),0(FI2)
356 const MachineFrameInfo &MFI = MI.getParent()->getParent()->getFrameInfo();
357 if (MI.getOpcode() != SystemZ::MVC || !MI.getOperand(0).isFI() ||
358 MI.getOperand(1).getImm() != 0 || !MI.getOperand(3).isFI() ||
359 MI.getOperand(4).getImm() != 0)
362 // Check that Length covers the full slots.
363 int64_t Length = MI.getOperand(2).getImm();
364 unsigned FI1 = MI.getOperand(0).getIndex();
365 unsigned FI2 = MI.getOperand(3).getIndex();
366 if (MFI.getObjectSize(FI1) != Length ||
367 MFI.getObjectSize(FI2) != Length)
370 DestFrameIndex = FI1;
375 bool SystemZInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
376 MachineBasicBlock *&TBB,
377 MachineBasicBlock *&FBB,
378 SmallVectorImpl<MachineOperand> &Cond,
379 bool AllowModify) const {
380 // Most of the code and comments here are boilerplate.
382 // Start from the bottom of the block and work up, examining the
383 // terminator instructions.
384 MachineBasicBlock::iterator I = MBB.end();
385 while (I != MBB.begin()) {
387 if (I->isDebugValue())
390 // Working from the bottom, when we see a non-terminator instruction, we're
392 if (!isUnpredicatedTerminator(*I))
395 // A terminator that isn't a branch can't easily be handled by this
400 // Can't handle indirect branches.
401 SystemZII::Branch Branch(getBranchInfo(*I));
402 if (!Branch.Target->isMBB())
405 // Punt on compound branches.
406 if (Branch.Type != SystemZII::BranchNormal)
409 if (Branch.CCMask == SystemZ::CCMASK_ANY) {
410 // Handle unconditional branches.
412 TBB = Branch.Target->getMBB();
416 // If the block has any instructions after a JMP, delete them.
417 while (std::next(I) != MBB.end())
418 std::next(I)->eraseFromParent();
423 // Delete the JMP if it's equivalent to a fall-through.
424 if (MBB.isLayoutSuccessor(Branch.Target->getMBB())) {
426 I->eraseFromParent();
431 // TBB is used to indicate the unconditinal destination.
432 TBB = Branch.Target->getMBB();
436 // Working from the bottom, handle the first conditional branch.
438 // FIXME: add X86-style branch swap
440 TBB = Branch.Target->getMBB();
441 Cond.push_back(MachineOperand::CreateImm(Branch.CCValid));
442 Cond.push_back(MachineOperand::CreateImm(Branch.CCMask));
446 // Handle subsequent conditional branches.
447 assert(Cond.size() == 2 && TBB && "Should have seen a conditional branch");
449 // Only handle the case where all conditional branches branch to the same
451 if (TBB != Branch.Target->getMBB())
454 // If the conditions are the same, we can leave them alone.
455 unsigned OldCCValid = Cond[0].getImm();
456 unsigned OldCCMask = Cond[1].getImm();
457 if (OldCCValid == Branch.CCValid && OldCCMask == Branch.CCMask)
460 // FIXME: Try combining conditions like X86 does. Should be easy on Z!
467 unsigned SystemZInstrInfo::removeBranch(MachineBasicBlock &MBB,
468 int *BytesRemoved) const {
469 assert(!BytesRemoved && "code size not handled");
471 // Most of the code and comments here are boilerplate.
472 MachineBasicBlock::iterator I = MBB.end();
475 while (I != MBB.begin()) {
477 if (I->isDebugValue())
481 if (!getBranchInfo(*I).Target->isMBB())
483 // Remove the branch.
484 I->eraseFromParent();
492 bool SystemZInstrInfo::
493 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
494 assert(Cond.size() == 2 && "Invalid condition");
495 Cond[1].setImm(Cond[1].getImm() ^ Cond[0].getImm());
499 unsigned SystemZInstrInfo::insertBranch(MachineBasicBlock &MBB,
500 MachineBasicBlock *TBB,
501 MachineBasicBlock *FBB,
502 ArrayRef<MachineOperand> Cond,
504 int *BytesAdded) const {
505 // In this function we output 32-bit branches, which should always
506 // have enough range. They can be shortened and relaxed by later code
507 // in the pipeline, if desired.
509 // Shouldn't be a fall through.
510 assert(TBB && "insertBranch must not be told to insert a fallthrough");
511 assert((Cond.size() == 2 || Cond.size() == 0) &&
512 "SystemZ branch conditions have one component!");
513 assert(!BytesAdded && "code size not handled");
516 // Unconditional branch?
517 assert(!FBB && "Unconditional branch with multiple successors!");
518 BuildMI(&MBB, DL, get(SystemZ::J)).addMBB(TBB);
522 // Conditional branch.
524 unsigned CCValid = Cond[0].getImm();
525 unsigned CCMask = Cond[1].getImm();
526 BuildMI(&MBB, DL, get(SystemZ::BRC))
527 .addImm(CCValid).addImm(CCMask).addMBB(TBB);
531 // Two-way Conditional branch. Insert the second branch.
532 BuildMI(&MBB, DL, get(SystemZ::J)).addMBB(FBB);
538 bool SystemZInstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
539 unsigned &SrcReg2, int &Mask,
541 assert(MI.isCompare() && "Caller should have checked for a comparison");
543 if (MI.getNumExplicitOperands() == 2 && MI.getOperand(0).isReg() &&
544 MI.getOperand(1).isImm()) {
545 SrcReg = MI.getOperand(0).getReg();
547 Value = MI.getOperand(1).getImm();
555 // If Reg is a virtual register, return its definition, otherwise return null.
556 static MachineInstr *getDef(unsigned Reg,
557 const MachineRegisterInfo *MRI) {
558 if (TargetRegisterInfo::isPhysicalRegister(Reg))
560 return MRI->getUniqueVRegDef(Reg);
563 // Return true if MI is a shift of type Opcode by Imm bits.
564 static bool isShift(MachineInstr *MI, unsigned Opcode, int64_t Imm) {
565 return (MI->getOpcode() == Opcode &&
566 !MI->getOperand(2).getReg() &&
567 MI->getOperand(3).getImm() == Imm);
570 // If the destination of MI has no uses, delete it as dead.
571 static void eraseIfDead(MachineInstr *MI, const MachineRegisterInfo *MRI) {
572 if (MRI->use_nodbg_empty(MI->getOperand(0).getReg()))
573 MI->eraseFromParent();
576 // Compare compares SrcReg against zero. Check whether SrcReg contains
577 // the result of an IPM sequence whose input CC survives until Compare,
578 // and whether Compare is therefore redundant. Delete it and return
580 static bool removeIPMBasedCompare(MachineInstr &Compare, unsigned SrcReg,
581 const MachineRegisterInfo *MRI,
582 const TargetRegisterInfo *TRI) {
583 MachineInstr *LGFR = nullptr;
584 MachineInstr *RLL = getDef(SrcReg, MRI);
585 if (RLL && RLL->getOpcode() == SystemZ::LGFR) {
587 RLL = getDef(LGFR->getOperand(1).getReg(), MRI);
589 if (!RLL || !isShift(RLL, SystemZ::RLL, 31))
592 MachineInstr *SRL = getDef(RLL->getOperand(1).getReg(), MRI);
593 if (!SRL || !isShift(SRL, SystemZ::SRL, SystemZ::IPM_CC))
596 MachineInstr *IPM = getDef(SRL->getOperand(1).getReg(), MRI);
597 if (!IPM || IPM->getOpcode() != SystemZ::IPM)
600 // Check that there are no assignments to CC between the IPM and Compare,
601 if (IPM->getParent() != Compare.getParent())
603 MachineBasicBlock::iterator MBBI = IPM, MBBE = Compare.getIterator();
604 for (++MBBI; MBBI != MBBE; ++MBBI) {
605 MachineInstr &MI = *MBBI;
606 if (MI.modifiesRegister(SystemZ::CC, TRI))
610 Compare.eraseFromParent();
612 eraseIfDead(LGFR, MRI);
613 eraseIfDead(RLL, MRI);
614 eraseIfDead(SRL, MRI);
615 eraseIfDead(IPM, MRI);
620 bool SystemZInstrInfo::optimizeCompareInstr(
621 MachineInstr &Compare, unsigned SrcReg, unsigned SrcReg2, int Mask,
622 int Value, const MachineRegisterInfo *MRI) const {
623 assert(!SrcReg2 && "Only optimizing constant comparisons so far");
624 bool IsLogical = (Compare.getDesc().TSFlags & SystemZII::IsLogical) != 0;
625 return Value == 0 && !IsLogical &&
626 removeIPMBasedCompare(Compare, SrcReg, MRI, &RI);
629 bool SystemZInstrInfo::canInsertSelect(const MachineBasicBlock &MBB,
630 ArrayRef<MachineOperand> Pred,
631 unsigned TrueReg, unsigned FalseReg,
632 int &CondCycles, int &TrueCycles,
633 int &FalseCycles) const {
634 // Not all subtargets have LOCR instructions.
635 if (!STI.hasLoadStoreOnCond())
637 if (Pred.size() != 2)
640 // Check register classes.
641 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
642 const TargetRegisterClass *RC =
643 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
647 // We have LOCR instructions for 32 and 64 bit general purpose registers.
648 if ((STI.hasLoadStoreOnCond2() &&
649 SystemZ::GRX32BitRegClass.hasSubClassEq(RC)) ||
650 SystemZ::GR32BitRegClass.hasSubClassEq(RC) ||
651 SystemZ::GR64BitRegClass.hasSubClassEq(RC)) {
658 // Can't do anything else.
662 void SystemZInstrInfo::insertSelect(MachineBasicBlock &MBB,
663 MachineBasicBlock::iterator I,
664 const DebugLoc &DL, unsigned DstReg,
665 ArrayRef<MachineOperand> Pred,
667 unsigned FalseReg) const {
668 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
669 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
671 assert(Pred.size() == 2 && "Invalid condition");
672 unsigned CCValid = Pred[0].getImm();
673 unsigned CCMask = Pred[1].getImm();
676 if (SystemZ::GRX32BitRegClass.hasSubClassEq(RC)) {
677 if (STI.hasLoadStoreOnCond2())
678 Opc = SystemZ::LOCRMux;
681 MRI.constrainRegClass(DstReg, &SystemZ::GR32BitRegClass);
682 unsigned TReg = MRI.createVirtualRegister(&SystemZ::GR32BitRegClass);
683 unsigned FReg = MRI.createVirtualRegister(&SystemZ::GR32BitRegClass);
684 BuildMI(MBB, I, DL, get(TargetOpcode::COPY), TReg).addReg(TrueReg);
685 BuildMI(MBB, I, DL, get(TargetOpcode::COPY), FReg).addReg(FalseReg);
689 } else if (SystemZ::GR64BitRegClass.hasSubClassEq(RC))
690 Opc = SystemZ::LOCGR;
692 llvm_unreachable("Invalid register class");
694 BuildMI(MBB, I, DL, get(Opc), DstReg)
695 .addReg(FalseReg).addReg(TrueReg)
696 .addImm(CCValid).addImm(CCMask);
699 bool SystemZInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
701 MachineRegisterInfo *MRI) const {
702 unsigned DefOpc = DefMI.getOpcode();
703 if (DefOpc != SystemZ::LHIMux && DefOpc != SystemZ::LHI &&
704 DefOpc != SystemZ::LGHI)
706 if (DefMI.getOperand(0).getReg() != Reg)
708 int32_t ImmVal = (int32_t)DefMI.getOperand(1).getImm();
710 unsigned UseOpc = UseMI.getOpcode();
715 case SystemZ::LOCRMux:
716 if (!STI.hasLoadStoreOnCond2())
718 NewUseOpc = SystemZ::LOCHIMux;
719 if (UseMI.getOperand(2).getReg() == Reg)
721 else if (UseMI.getOperand(1).getReg() == Reg)
722 UseIdx = 2, CommuteIdx = 1;
727 if (!STI.hasLoadStoreOnCond2())
729 NewUseOpc = SystemZ::LOCGHI;
730 if (UseMI.getOperand(2).getReg() == Reg)
732 else if (UseMI.getOperand(1).getReg() == Reg)
733 UseIdx = 2, CommuteIdx = 1;
741 if (CommuteIdx != -1)
742 if (!commuteInstruction(UseMI, false, CommuteIdx, UseIdx))
745 bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
746 UseMI.setDesc(get(NewUseOpc));
747 UseMI.getOperand(UseIdx).ChangeToImmediate(ImmVal);
749 DefMI.eraseFromParent();
754 bool SystemZInstrInfo::isPredicable(const MachineInstr &MI) const {
755 unsigned Opcode = MI.getOpcode();
756 if (Opcode == SystemZ::Return ||
757 Opcode == SystemZ::Trap ||
758 Opcode == SystemZ::CallJG ||
759 Opcode == SystemZ::CallBR)
764 bool SystemZInstrInfo::
765 isProfitableToIfCvt(MachineBasicBlock &MBB,
766 unsigned NumCycles, unsigned ExtraPredCycles,
767 BranchProbability Probability) const {
768 // Avoid using conditional returns at the end of a loop (since then
769 // we'd need to emit an unconditional branch to the beginning anyway,
770 // making the loop body longer). This doesn't apply for low-probability
771 // loops (eg. compare-and-swap retry), so just decide based on branch
772 // probability instead of looping structure.
773 // However, since Compare and Trap instructions cost the same as a regular
774 // Compare instruction, we should allow the if conversion to convert this
775 // into a Conditional Compare regardless of the branch probability.
776 if (MBB.getLastNonDebugInstr()->getOpcode() != SystemZ::Trap &&
777 MBB.succ_empty() && Probability < BranchProbability(1, 8))
779 // For now only convert single instructions.
780 return NumCycles == 1;
783 bool SystemZInstrInfo::
784 isProfitableToIfCvt(MachineBasicBlock &TMBB,
785 unsigned NumCyclesT, unsigned ExtraPredCyclesT,
786 MachineBasicBlock &FMBB,
787 unsigned NumCyclesF, unsigned ExtraPredCyclesF,
788 BranchProbability Probability) const {
789 // For now avoid converting mutually-exclusive cases.
793 bool SystemZInstrInfo::
794 isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
795 BranchProbability Probability) const {
796 // For now only duplicate single instructions.
797 return NumCycles == 1;
800 bool SystemZInstrInfo::PredicateInstruction(
801 MachineInstr &MI, ArrayRef<MachineOperand> Pred) const {
802 assert(Pred.size() == 2 && "Invalid condition");
803 unsigned CCValid = Pred[0].getImm();
804 unsigned CCMask = Pred[1].getImm();
805 assert(CCMask > 0 && CCMask < 15 && "Invalid predicate");
806 unsigned Opcode = MI.getOpcode();
807 if (Opcode == SystemZ::Trap) {
808 MI.setDesc(get(SystemZ::CondTrap));
809 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
810 .addImm(CCValid).addImm(CCMask)
811 .addReg(SystemZ::CC, RegState::Implicit);
814 if (Opcode == SystemZ::Return) {
815 MI.setDesc(get(SystemZ::CondReturn));
816 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
817 .addImm(CCValid).addImm(CCMask)
818 .addReg(SystemZ::CC, RegState::Implicit);
821 if (Opcode == SystemZ::CallJG) {
822 MachineOperand FirstOp = MI.getOperand(0);
823 const uint32_t *RegMask = MI.getOperand(1).getRegMask();
826 MI.setDesc(get(SystemZ::CallBRCL));
827 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
832 .addReg(SystemZ::CC, RegState::Implicit);
835 if (Opcode == SystemZ::CallBR) {
836 const uint32_t *RegMask = MI.getOperand(0).getRegMask();
838 MI.setDesc(get(SystemZ::CallBCR));
839 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
840 .addImm(CCValid).addImm(CCMask)
842 .addReg(SystemZ::CC, RegState::Implicit);
848 void SystemZInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
849 MachineBasicBlock::iterator MBBI,
850 const DebugLoc &DL, unsigned DestReg,
851 unsigned SrcReg, bool KillSrc) const {
852 // Split 128-bit GPR moves into two 64-bit moves. This handles ADDR128 too.
853 if (SystemZ::GR128BitRegClass.contains(DestReg, SrcReg)) {
854 copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_h64),
855 RI.getSubReg(SrcReg, SystemZ::subreg_h64), KillSrc);
856 copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_l64),
857 RI.getSubReg(SrcReg, SystemZ::subreg_l64), KillSrc);
861 if (SystemZ::GRX32BitRegClass.contains(DestReg, SrcReg)) {
862 emitGRX32Move(MBB, MBBI, DL, DestReg, SrcReg, SystemZ::LR, 32, KillSrc,
867 // Everything else needs only one instruction.
869 if (SystemZ::GR64BitRegClass.contains(DestReg, SrcReg))
870 Opcode = SystemZ::LGR;
871 else if (SystemZ::FP32BitRegClass.contains(DestReg, SrcReg))
872 // For z13 we prefer LDR over LER to avoid partial register dependencies.
873 Opcode = STI.hasVector() ? SystemZ::LDR32 : SystemZ::LER;
874 else if (SystemZ::FP64BitRegClass.contains(DestReg, SrcReg))
875 Opcode = SystemZ::LDR;
876 else if (SystemZ::FP128BitRegClass.contains(DestReg, SrcReg))
877 Opcode = SystemZ::LXR;
878 else if (SystemZ::VR32BitRegClass.contains(DestReg, SrcReg))
879 Opcode = SystemZ::VLR32;
880 else if (SystemZ::VR64BitRegClass.contains(DestReg, SrcReg))
881 Opcode = SystemZ::VLR64;
882 else if (SystemZ::VR128BitRegClass.contains(DestReg, SrcReg))
883 Opcode = SystemZ::VLR;
884 else if (SystemZ::AR32BitRegClass.contains(DestReg, SrcReg))
885 Opcode = SystemZ::CPYA;
886 else if (SystemZ::AR32BitRegClass.contains(DestReg) &&
887 SystemZ::GR32BitRegClass.contains(SrcReg))
888 Opcode = SystemZ::SAR;
889 else if (SystemZ::GR32BitRegClass.contains(DestReg) &&
890 SystemZ::AR32BitRegClass.contains(SrcReg))
891 Opcode = SystemZ::EAR;
893 llvm_unreachable("Impossible reg-to-reg copy");
895 BuildMI(MBB, MBBI, DL, get(Opcode), DestReg)
896 .addReg(SrcReg, getKillRegState(KillSrc));
899 void SystemZInstrInfo::storeRegToStackSlot(
900 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg,
901 bool isKill, int FrameIdx, const TargetRegisterClass *RC,
902 const TargetRegisterInfo *TRI) const {
903 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
905 // Callers may expect a single instruction, so keep 128-bit moves
906 // together for now and lower them after register allocation.
907 unsigned LoadOpcode, StoreOpcode;
908 getLoadStoreOpcodes(RC, LoadOpcode, StoreOpcode);
909 addFrameReference(BuildMI(MBB, MBBI, DL, get(StoreOpcode))
910 .addReg(SrcReg, getKillRegState(isKill)),
914 void SystemZInstrInfo::loadRegFromStackSlot(
915 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg,
916 int FrameIdx, const TargetRegisterClass *RC,
917 const TargetRegisterInfo *TRI) const {
918 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
920 // Callers may expect a single instruction, so keep 128-bit moves
921 // together for now and lower them after register allocation.
922 unsigned LoadOpcode, StoreOpcode;
923 getLoadStoreOpcodes(RC, LoadOpcode, StoreOpcode);
924 addFrameReference(BuildMI(MBB, MBBI, DL, get(LoadOpcode), DestReg),
928 // Return true if MI is a simple load or store with a 12-bit displacement
929 // and no index. Flag is SimpleBDXLoad for loads and SimpleBDXStore for stores.
930 static bool isSimpleBD12Move(const MachineInstr *MI, unsigned Flag) {
931 const MCInstrDesc &MCID = MI->getDesc();
932 return ((MCID.TSFlags & Flag) &&
933 isUInt<12>(MI->getOperand(2).getImm()) &&
934 MI->getOperand(3).getReg() == 0);
941 LogicOp(unsigned regSize, unsigned immLSB, unsigned immSize)
942 : RegSize(regSize), ImmLSB(immLSB), ImmSize(immSize) {}
944 explicit operator bool() const { return RegSize; }
946 unsigned RegSize = 0;
948 unsigned ImmSize = 0;
951 } // end anonymous namespace
953 static LogicOp interpretAndImmediate(unsigned Opcode) {
955 case SystemZ::NILMux: return LogicOp(32, 0, 16);
956 case SystemZ::NIHMux: return LogicOp(32, 16, 16);
957 case SystemZ::NILL64: return LogicOp(64, 0, 16);
958 case SystemZ::NILH64: return LogicOp(64, 16, 16);
959 case SystemZ::NIHL64: return LogicOp(64, 32, 16);
960 case SystemZ::NIHH64: return LogicOp(64, 48, 16);
961 case SystemZ::NIFMux: return LogicOp(32, 0, 32);
962 case SystemZ::NILF64: return LogicOp(64, 0, 32);
963 case SystemZ::NIHF64: return LogicOp(64, 32, 32);
964 default: return LogicOp();
968 static void transferDeadCC(MachineInstr *OldMI, MachineInstr *NewMI) {
969 if (OldMI->registerDefIsDead(SystemZ::CC)) {
970 MachineOperand *CCDef = NewMI->findRegisterDefOperand(SystemZ::CC);
971 if (CCDef != nullptr)
972 CCDef->setIsDead(true);
976 // Used to return from convertToThreeAddress after replacing two-address
977 // instruction OldMI with three-address instruction NewMI.
978 static MachineInstr *finishConvertToThreeAddress(MachineInstr *OldMI,
982 unsigned NumOps = OldMI->getNumOperands();
983 for (unsigned I = 1; I < NumOps; ++I) {
984 MachineOperand &Op = OldMI->getOperand(I);
985 if (Op.isReg() && Op.isKill())
986 LV->replaceKillInstruction(Op.getReg(), *OldMI, *NewMI);
989 transferDeadCC(OldMI, NewMI);
993 MachineInstr *SystemZInstrInfo::convertToThreeAddress(
994 MachineFunction::iterator &MFI, MachineInstr &MI, LiveVariables *LV) const {
995 MachineBasicBlock *MBB = MI.getParent();
996 MachineFunction *MF = MBB->getParent();
997 MachineRegisterInfo &MRI = MF->getRegInfo();
999 unsigned Opcode = MI.getOpcode();
1000 unsigned NumOps = MI.getNumOperands();
1002 // Try to convert something like SLL into SLLK, if supported.
1003 // We prefer to keep the two-operand form where possible both
1004 // because it tends to be shorter and because some instructions
1005 // have memory forms that can be used during spilling.
1006 if (STI.hasDistinctOps()) {
1007 MachineOperand &Dest = MI.getOperand(0);
1008 MachineOperand &Src = MI.getOperand(1);
1009 unsigned DestReg = Dest.getReg();
1010 unsigned SrcReg = Src.getReg();
1011 // AHIMux is only really a three-operand instruction when both operands
1012 // are low registers. Try to constrain both operands to be low if
1014 if (Opcode == SystemZ::AHIMux &&
1015 TargetRegisterInfo::isVirtualRegister(DestReg) &&
1016 TargetRegisterInfo::isVirtualRegister(SrcReg) &&
1017 MRI.getRegClass(DestReg)->contains(SystemZ::R1L) &&
1018 MRI.getRegClass(SrcReg)->contains(SystemZ::R1L)) {
1019 MRI.constrainRegClass(DestReg, &SystemZ::GR32BitRegClass);
1020 MRI.constrainRegClass(SrcReg, &SystemZ::GR32BitRegClass);
1022 int ThreeOperandOpcode = SystemZ::getThreeOperandOpcode(Opcode);
1023 if (ThreeOperandOpcode >= 0) {
1024 // Create three address instruction without adding the implicit
1025 // operands. Those will instead be copied over from the original
1026 // instruction by the loop below.
1027 MachineInstrBuilder MIB(
1028 *MF, MF->CreateMachineInstr(get(ThreeOperandOpcode), MI.getDebugLoc(),
1029 /*NoImplicit=*/true));
1031 // Keep the kill state, but drop the tied flag.
1032 MIB.addReg(Src.getReg(), getKillRegState(Src.isKill()), Src.getSubReg());
1033 // Keep the remaining operands as-is.
1034 for (unsigned I = 2; I < NumOps; ++I)
1035 MIB.add(MI.getOperand(I));
1036 MBB->insert(MI, MIB);
1037 return finishConvertToThreeAddress(&MI, MIB, LV);
1041 // Try to convert an AND into an RISBG-type instruction.
1042 if (LogicOp And = interpretAndImmediate(Opcode)) {
1043 uint64_t Imm = MI.getOperand(2).getImm() << And.ImmLSB;
1044 // AND IMMEDIATE leaves the other bits of the register unchanged.
1045 Imm |= allOnes(And.RegSize) & ~(allOnes(And.ImmSize) << And.ImmLSB);
1046 unsigned Start, End;
1047 if (isRxSBGMask(Imm, And.RegSize, Start, End)) {
1049 if (And.RegSize == 64) {
1050 NewOpcode = SystemZ::RISBG;
1051 // Prefer RISBGN if available, since it does not clobber CC.
1052 if (STI.hasMiscellaneousExtensions())
1053 NewOpcode = SystemZ::RISBGN;
1055 NewOpcode = SystemZ::RISBMux;
1059 MachineOperand &Dest = MI.getOperand(0);
1060 MachineOperand &Src = MI.getOperand(1);
1061 MachineInstrBuilder MIB =
1062 BuildMI(*MBB, MI, MI.getDebugLoc(), get(NewOpcode))
1065 .addReg(Src.getReg(), getKillRegState(Src.isKill()),
1070 return finishConvertToThreeAddress(&MI, MIB, LV);
1076 MachineInstr *SystemZInstrInfo::foldMemoryOperandImpl(
1077 MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
1078 MachineBasicBlock::iterator InsertPt, int FrameIndex,
1079 LiveIntervals *LIS) const {
1080 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
1081 const MachineFrameInfo &MFI = MF.getFrameInfo();
1082 unsigned Size = MFI.getObjectSize(FrameIndex);
1083 unsigned Opcode = MI.getOpcode();
1085 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
1086 if (LIS != nullptr && (Opcode == SystemZ::LA || Opcode == SystemZ::LAY) &&
1087 isInt<8>(MI.getOperand(2).getImm()) && !MI.getOperand(3).getReg()) {
1089 // Check CC liveness, since new instruction introduces a dead
1091 MCRegUnitIterator CCUnit(SystemZ::CC, TRI);
1092 LiveRange &CCLiveRange = LIS->getRegUnit(*CCUnit);
1094 assert(!CCUnit.isValid() && "CC only has one reg unit.");
1096 LIS->getSlotIndexes()->getInstructionIndex(MI).getRegSlot();
1097 if (!CCLiveRange.liveAt(MISlot)) {
1098 // LA(Y) %reg, CONST(%reg) -> AGSI %mem, CONST
1099 MachineInstr *BuiltMI = BuildMI(*InsertPt->getParent(), InsertPt,
1100 MI.getDebugLoc(), get(SystemZ::AGSI))
1101 .addFrameIndex(FrameIndex)
1103 .addImm(MI.getOperand(2).getImm());
1104 BuiltMI->findRegisterDefOperand(SystemZ::CC)->setIsDead(true);
1105 CCLiveRange.createDeadDef(MISlot, LIS->getVNInfoAllocator());
1112 // All other cases require a single operand.
1113 if (Ops.size() != 1)
1116 unsigned OpNum = Ops[0];
1119 .getRegClass(MI.getOperand(OpNum).getReg())
1121 "Invalid size combination");
1123 if ((Opcode == SystemZ::AHI || Opcode == SystemZ::AGHI) && OpNum == 0 &&
1124 isInt<8>(MI.getOperand(2).getImm())) {
1125 // A(G)HI %reg, CONST -> A(G)SI %mem, CONST
1126 Opcode = (Opcode == SystemZ::AHI ? SystemZ::ASI : SystemZ::AGSI);
1127 MachineInstr *BuiltMI =
1128 BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(), get(Opcode))
1129 .addFrameIndex(FrameIndex)
1131 .addImm(MI.getOperand(2).getImm());
1132 transferDeadCC(&MI, BuiltMI);
1136 if (Opcode == SystemZ::LGDR || Opcode == SystemZ::LDGR) {
1137 bool Op0IsGPR = (Opcode == SystemZ::LGDR);
1138 bool Op1IsGPR = (Opcode == SystemZ::LDGR);
1139 // If we're spilling the destination of an LDGR or LGDR, store the
1140 // source register instead.
1142 unsigned StoreOpcode = Op1IsGPR ? SystemZ::STG : SystemZ::STD;
1143 return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),
1145 .add(MI.getOperand(1))
1146 .addFrameIndex(FrameIndex)
1150 // If we're spilling the source of an LDGR or LGDR, load the
1151 // destination register instead.
1153 unsigned LoadOpcode = Op0IsGPR ? SystemZ::LG : SystemZ::LD;
1154 return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),
1156 .add(MI.getOperand(0))
1157 .addFrameIndex(FrameIndex)
1163 // Look for cases where the source of a simple store or the destination
1164 // of a simple load is being spilled. Try to use MVC instead.
1166 // Although MVC is in practice a fast choice in these cases, it is still
1167 // logically a bytewise copy. This means that we cannot use it if the
1168 // load or store is volatile. We also wouldn't be able to use MVC if
1169 // the two memories partially overlap, but that case cannot occur here,
1170 // because we know that one of the memories is a full frame index.
1172 // For performance reasons, we also want to avoid using MVC if the addresses
1173 // might be equal. We don't worry about that case here, because spill slot
1174 // coloring happens later, and because we have special code to remove
1175 // MVCs that turn out to be redundant.
1176 if (OpNum == 0 && MI.hasOneMemOperand()) {
1177 MachineMemOperand *MMO = *MI.memoperands_begin();
1178 if (MMO->getSize() == Size && !MMO->isVolatile()) {
1179 // Handle conversion of loads.
1180 if (isSimpleBD12Move(&MI, SystemZII::SimpleBDXLoad)) {
1181 return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),
1183 .addFrameIndex(FrameIndex)
1186 .add(MI.getOperand(1))
1187 .addImm(MI.getOperand(2).getImm())
1188 .addMemOperand(MMO);
1190 // Handle conversion of stores.
1191 if (isSimpleBD12Move(&MI, SystemZII::SimpleBDXStore)) {
1192 return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),
1194 .add(MI.getOperand(1))
1195 .addImm(MI.getOperand(2).getImm())
1197 .addFrameIndex(FrameIndex)
1199 .addMemOperand(MMO);
1204 // If the spilled operand is the final one, try to change <INSN>R
1206 int MemOpcode = SystemZ::getMemOpcode(Opcode);
1207 if (MemOpcode >= 0) {
1208 unsigned NumOps = MI.getNumExplicitOperands();
1209 if (OpNum == NumOps - 1) {
1210 const MCInstrDesc &MemDesc = get(MemOpcode);
1211 uint64_t AccessBytes = SystemZII::getAccessSize(MemDesc.TSFlags);
1212 assert(AccessBytes != 0 && "Size of access should be known");
1213 assert(AccessBytes <= Size && "Access outside the frame index");
1214 uint64_t Offset = Size - AccessBytes;
1215 MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt,
1216 MI.getDebugLoc(), get(MemOpcode));
1217 for (unsigned I = 0; I < OpNum; ++I)
1218 MIB.add(MI.getOperand(I));
1219 MIB.addFrameIndex(FrameIndex).addImm(Offset);
1220 if (MemDesc.TSFlags & SystemZII::HasIndex)
1222 transferDeadCC(&MI, MIB);
1230 MachineInstr *SystemZInstrInfo::foldMemoryOperandImpl(
1231 MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
1232 MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
1233 LiveIntervals *LIS) const {
1237 bool SystemZInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
1238 switch (MI.getOpcode()) {
1240 splitMove(MI, SystemZ::LG);
1243 case SystemZ::ST128:
1244 splitMove(MI, SystemZ::STG);
1248 splitMove(MI, SystemZ::LD);
1252 splitMove(MI, SystemZ::STD);
1255 case SystemZ::LBMux:
1256 expandRXYPseudo(MI, SystemZ::LB, SystemZ::LBH);
1259 case SystemZ::LHMux:
1260 expandRXYPseudo(MI, SystemZ::LH, SystemZ::LHH);
1263 case SystemZ::LLCRMux:
1264 expandZExtPseudo(MI, SystemZ::LLCR, 8);
1267 case SystemZ::LLHRMux:
1268 expandZExtPseudo(MI, SystemZ::LLHR, 16);
1271 case SystemZ::LLCMux:
1272 expandRXYPseudo(MI, SystemZ::LLC, SystemZ::LLCH);
1275 case SystemZ::LLHMux:
1276 expandRXYPseudo(MI, SystemZ::LLH, SystemZ::LLHH);
1280 expandRXYPseudo(MI, SystemZ::L, SystemZ::LFH);
1283 case SystemZ::LOCMux:
1284 expandLOCPseudo(MI, SystemZ::LOC, SystemZ::LOCFH);
1287 case SystemZ::LOCHIMux:
1288 expandLOCPseudo(MI, SystemZ::LOCHI, SystemZ::LOCHHI);
1291 case SystemZ::LOCRMux:
1292 expandLOCRPseudo(MI, SystemZ::LOCR, SystemZ::LOCFHR);
1295 case SystemZ::STCMux:
1296 expandRXYPseudo(MI, SystemZ::STC, SystemZ::STCH);
1299 case SystemZ::STHMux:
1300 expandRXYPseudo(MI, SystemZ::STH, SystemZ::STHH);
1303 case SystemZ::STMux:
1304 expandRXYPseudo(MI, SystemZ::ST, SystemZ::STFH);
1307 case SystemZ::STOCMux:
1308 expandLOCPseudo(MI, SystemZ::STOC, SystemZ::STOCFH);
1311 case SystemZ::LHIMux:
1312 expandRIPseudo(MI, SystemZ::LHI, SystemZ::IIHF, true);
1315 case SystemZ::IIFMux:
1316 expandRIPseudo(MI, SystemZ::IILF, SystemZ::IIHF, false);
1319 case SystemZ::IILMux:
1320 expandRIPseudo(MI, SystemZ::IILL, SystemZ::IIHL, false);
1323 case SystemZ::IIHMux:
1324 expandRIPseudo(MI, SystemZ::IILH, SystemZ::IIHH, false);
1327 case SystemZ::NIFMux:
1328 expandRIPseudo(MI, SystemZ::NILF, SystemZ::NIHF, false);
1331 case SystemZ::NILMux:
1332 expandRIPseudo(MI, SystemZ::NILL, SystemZ::NIHL, false);
1335 case SystemZ::NIHMux:
1336 expandRIPseudo(MI, SystemZ::NILH, SystemZ::NIHH, false);
1339 case SystemZ::OIFMux:
1340 expandRIPseudo(MI, SystemZ::OILF, SystemZ::OIHF, false);
1343 case SystemZ::OILMux:
1344 expandRIPseudo(MI, SystemZ::OILL, SystemZ::OIHL, false);
1347 case SystemZ::OIHMux:
1348 expandRIPseudo(MI, SystemZ::OILH, SystemZ::OIHH, false);
1351 case SystemZ::XIFMux:
1352 expandRIPseudo(MI, SystemZ::XILF, SystemZ::XIHF, false);
1355 case SystemZ::TMLMux:
1356 expandRIPseudo(MI, SystemZ::TMLL, SystemZ::TMHL, false);
1359 case SystemZ::TMHMux:
1360 expandRIPseudo(MI, SystemZ::TMLH, SystemZ::TMHH, false);
1363 case SystemZ::AHIMux:
1364 expandRIPseudo(MI, SystemZ::AHI, SystemZ::AIH, false);
1367 case SystemZ::AHIMuxK:
1368 expandRIEPseudo(MI, SystemZ::AHI, SystemZ::AHIK, SystemZ::AIH);
1371 case SystemZ::AFIMux:
1372 expandRIPseudo(MI, SystemZ::AFI, SystemZ::AIH, false);
1375 case SystemZ::CHIMux:
1376 expandRIPseudo(MI, SystemZ::CHI, SystemZ::CIH, false);
1379 case SystemZ::CFIMux:
1380 expandRIPseudo(MI, SystemZ::CFI, SystemZ::CIH, false);
1383 case SystemZ::CLFIMux:
1384 expandRIPseudo(MI, SystemZ::CLFI, SystemZ::CLIH, false);
1388 expandRXYPseudo(MI, SystemZ::C, SystemZ::CHF);
1391 case SystemZ::CLMux:
1392 expandRXYPseudo(MI, SystemZ::CL, SystemZ::CLHF);
1395 case SystemZ::RISBMux: {
1396 bool DestIsHigh = isHighReg(MI.getOperand(0).getReg());
1397 bool SrcIsHigh = isHighReg(MI.getOperand(2).getReg());
1398 if (SrcIsHigh == DestIsHigh)
1399 MI.setDesc(get(DestIsHigh ? SystemZ::RISBHH : SystemZ::RISBLL));
1401 MI.setDesc(get(DestIsHigh ? SystemZ::RISBHL : SystemZ::RISBLH));
1402 MI.getOperand(5).setImm(MI.getOperand(5).getImm() ^ 32);
1407 case SystemZ::ADJDYNALLOC:
1408 splitAdjDynAlloc(MI);
1411 case TargetOpcode::LOAD_STACK_GUARD:
1412 expandLoadStackGuard(&MI);
1420 unsigned SystemZInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
1421 if (MI.getOpcode() == TargetOpcode::INLINEASM) {
1422 const MachineFunction *MF = MI.getParent()->getParent();
1423 const char *AsmStr = MI.getOperand(0).getSymbolName();
1424 return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
1426 return MI.getDesc().getSize();
1430 SystemZInstrInfo::getBranchInfo(const MachineInstr &MI) const {
1431 switch (MI.getOpcode()) {
1435 return SystemZII::Branch(SystemZII::BranchNormal, SystemZ::CCMASK_ANY,
1436 SystemZ::CCMASK_ANY, &MI.getOperand(0));
1440 return SystemZII::Branch(SystemZII::BranchNormal, MI.getOperand(0).getImm(),
1441 MI.getOperand(1).getImm(), &MI.getOperand(2));
1444 case SystemZ::BRCTH:
1445 return SystemZII::Branch(SystemZII::BranchCT, SystemZ::CCMASK_ICMP,
1446 SystemZ::CCMASK_CMP_NE, &MI.getOperand(2));
1448 case SystemZ::BRCTG:
1449 return SystemZII::Branch(SystemZII::BranchCTG, SystemZ::CCMASK_ICMP,
1450 SystemZ::CCMASK_CMP_NE, &MI.getOperand(2));
1454 return SystemZII::Branch(SystemZII::BranchC, SystemZ::CCMASK_ICMP,
1455 MI.getOperand(2).getImm(), &MI.getOperand(3));
1459 return SystemZII::Branch(SystemZII::BranchCL, SystemZ::CCMASK_ICMP,
1460 MI.getOperand(2).getImm(), &MI.getOperand(3));
1464 return SystemZII::Branch(SystemZII::BranchCG, SystemZ::CCMASK_ICMP,
1465 MI.getOperand(2).getImm(), &MI.getOperand(3));
1467 case SystemZ::CLGIJ:
1468 case SystemZ::CLGRJ:
1469 return SystemZII::Branch(SystemZII::BranchCLG, SystemZ::CCMASK_ICMP,
1470 MI.getOperand(2).getImm(), &MI.getOperand(3));
1473 llvm_unreachable("Unrecognized branch opcode");
1477 void SystemZInstrInfo::getLoadStoreOpcodes(const TargetRegisterClass *RC,
1478 unsigned &LoadOpcode,
1479 unsigned &StoreOpcode) const {
1480 if (RC == &SystemZ::GR32BitRegClass || RC == &SystemZ::ADDR32BitRegClass) {
1481 LoadOpcode = SystemZ::L;
1482 StoreOpcode = SystemZ::ST;
1483 } else if (RC == &SystemZ::GRH32BitRegClass) {
1484 LoadOpcode = SystemZ::LFH;
1485 StoreOpcode = SystemZ::STFH;
1486 } else if (RC == &SystemZ::GRX32BitRegClass) {
1487 LoadOpcode = SystemZ::LMux;
1488 StoreOpcode = SystemZ::STMux;
1489 } else if (RC == &SystemZ::GR64BitRegClass ||
1490 RC == &SystemZ::ADDR64BitRegClass) {
1491 LoadOpcode = SystemZ::LG;
1492 StoreOpcode = SystemZ::STG;
1493 } else if (RC == &SystemZ::GR128BitRegClass ||
1494 RC == &SystemZ::ADDR128BitRegClass) {
1495 LoadOpcode = SystemZ::L128;
1496 StoreOpcode = SystemZ::ST128;
1497 } else if (RC == &SystemZ::FP32BitRegClass) {
1498 LoadOpcode = SystemZ::LE;
1499 StoreOpcode = SystemZ::STE;
1500 } else if (RC == &SystemZ::FP64BitRegClass) {
1501 LoadOpcode = SystemZ::LD;
1502 StoreOpcode = SystemZ::STD;
1503 } else if (RC == &SystemZ::FP128BitRegClass) {
1504 LoadOpcode = SystemZ::LX;
1505 StoreOpcode = SystemZ::STX;
1506 } else if (RC == &SystemZ::VR32BitRegClass) {
1507 LoadOpcode = SystemZ::VL32;
1508 StoreOpcode = SystemZ::VST32;
1509 } else if (RC == &SystemZ::VR64BitRegClass) {
1510 LoadOpcode = SystemZ::VL64;
1511 StoreOpcode = SystemZ::VST64;
1512 } else if (RC == &SystemZ::VF128BitRegClass ||
1513 RC == &SystemZ::VR128BitRegClass) {
1514 LoadOpcode = SystemZ::VL;
1515 StoreOpcode = SystemZ::VST;
1517 llvm_unreachable("Unsupported regclass to load or store");
1520 unsigned SystemZInstrInfo::getOpcodeForOffset(unsigned Opcode,
1521 int64_t Offset) const {
1522 const MCInstrDesc &MCID = get(Opcode);
1523 int64_t Offset2 = (MCID.TSFlags & SystemZII::Is128Bit ? Offset + 8 : Offset);
1524 if (isUInt<12>(Offset) && isUInt<12>(Offset2)) {
1525 // Get the instruction to use for unsigned 12-bit displacements.
1526 int Disp12Opcode = SystemZ::getDisp12Opcode(Opcode);
1527 if (Disp12Opcode >= 0)
1528 return Disp12Opcode;
1530 // All address-related instructions can use unsigned 12-bit
1534 if (isInt<20>(Offset) && isInt<20>(Offset2)) {
1535 // Get the instruction to use for signed 20-bit displacements.
1536 int Disp20Opcode = SystemZ::getDisp20Opcode(Opcode);
1537 if (Disp20Opcode >= 0)
1538 return Disp20Opcode;
1540 // Check whether Opcode allows signed 20-bit displacements.
1541 if (MCID.TSFlags & SystemZII::Has20BitOffset)
1547 unsigned SystemZInstrInfo::getLoadAndTest(unsigned Opcode) const {
1549 case SystemZ::L: return SystemZ::LT;
1550 case SystemZ::LY: return SystemZ::LT;
1551 case SystemZ::LG: return SystemZ::LTG;
1552 case SystemZ::LGF: return SystemZ::LTGF;
1553 case SystemZ::LR: return SystemZ::LTR;
1554 case SystemZ::LGFR: return SystemZ::LTGFR;
1555 case SystemZ::LGR: return SystemZ::LTGR;
1556 case SystemZ::LER: return SystemZ::LTEBR;
1557 case SystemZ::LDR: return SystemZ::LTDBR;
1558 case SystemZ::LXR: return SystemZ::LTXBR;
1559 case SystemZ::LCDFR: return SystemZ::LCDBR;
1560 case SystemZ::LPDFR: return SystemZ::LPDBR;
1561 case SystemZ::LNDFR: return SystemZ::LNDBR;
1562 case SystemZ::LCDFR_32: return SystemZ::LCEBR;
1563 case SystemZ::LPDFR_32: return SystemZ::LPEBR;
1564 case SystemZ::LNDFR_32: return SystemZ::LNEBR;
1565 // On zEC12 we prefer to use RISBGN. But if there is a chance to
1566 // actually use the condition code, we may turn it back into RISGB.
1567 // Note that RISBG is not really a "load-and-test" instruction,
1568 // but sets the same condition code values, so is OK to use here.
1569 case SystemZ::RISBGN: return SystemZ::RISBG;
1574 // Return true if Mask matches the regexp 0*1+0*, given that zero masks
1575 // have already been filtered out. Store the first set bit in LSB and
1576 // the number of set bits in Length if so.
1577 static bool isStringOfOnes(uint64_t Mask, unsigned &LSB, unsigned &Length) {
1578 unsigned First = findFirstSet(Mask);
1579 uint64_t Top = (Mask >> First) + 1;
1580 if ((Top & -Top) == Top) {
1582 Length = findFirstSet(Top);
1588 bool SystemZInstrInfo::isRxSBGMask(uint64_t Mask, unsigned BitSize,
1589 unsigned &Start, unsigned &End) const {
1590 // Reject trivial all-zero masks.
1591 Mask &= allOnes(BitSize);
1595 // Handle the 1+0+ or 0+1+0* cases. Start then specifies the index of
1596 // the msb and End specifies the index of the lsb.
1597 unsigned LSB, Length;
1598 if (isStringOfOnes(Mask, LSB, Length)) {
1599 Start = 63 - (LSB + Length - 1);
1604 // Handle the wrap-around 1+0+1+ cases. Start then specifies the msb
1605 // of the low 1s and End specifies the lsb of the high 1s.
1606 if (isStringOfOnes(Mask ^ allOnes(BitSize), LSB, Length)) {
1607 assert(LSB > 0 && "Bottom bit must be set");
1608 assert(LSB + Length < BitSize && "Top bit must be set");
1609 Start = 63 - (LSB - 1);
1610 End = 63 - (LSB + Length);
1617 unsigned SystemZInstrInfo::getFusedCompare(unsigned Opcode,
1618 SystemZII::FusedCompareType Type,
1619 const MachineInstr *MI) const {
1623 if (!(MI && isInt<8>(MI->getOperand(1).getImm())))
1627 case SystemZ::CLGFI:
1628 if (!(MI && isUInt<8>(MI->getOperand(1).getImm())))
1633 if (!STI.hasMiscellaneousExtensions())
1635 if (!(MI && MI->getOperand(3).getReg() == 0))
1640 case SystemZII::CompareAndBranch:
1643 return SystemZ::CRJ;
1645 return SystemZ::CGRJ;
1647 return SystemZ::CIJ;
1649 return SystemZ::CGIJ;
1651 return SystemZ::CLRJ;
1653 return SystemZ::CLGRJ;
1655 return SystemZ::CLIJ;
1656 case SystemZ::CLGFI:
1657 return SystemZ::CLGIJ;
1661 case SystemZII::CompareAndReturn:
1664 return SystemZ::CRBReturn;
1666 return SystemZ::CGRBReturn;
1668 return SystemZ::CIBReturn;
1670 return SystemZ::CGIBReturn;
1672 return SystemZ::CLRBReturn;
1674 return SystemZ::CLGRBReturn;
1676 return SystemZ::CLIBReturn;
1677 case SystemZ::CLGFI:
1678 return SystemZ::CLGIBReturn;
1682 case SystemZII::CompareAndSibcall:
1685 return SystemZ::CRBCall;
1687 return SystemZ::CGRBCall;
1689 return SystemZ::CIBCall;
1691 return SystemZ::CGIBCall;
1693 return SystemZ::CLRBCall;
1695 return SystemZ::CLGRBCall;
1697 return SystemZ::CLIBCall;
1698 case SystemZ::CLGFI:
1699 return SystemZ::CLGIBCall;
1703 case SystemZII::CompareAndTrap:
1706 return SystemZ::CRT;
1708 return SystemZ::CGRT;
1710 return SystemZ::CIT;
1712 return SystemZ::CGIT;
1714 return SystemZ::CLRT;
1716 return SystemZ::CLGRT;
1718 return SystemZ::CLFIT;
1719 case SystemZ::CLGFI:
1720 return SystemZ::CLGIT;
1722 return SystemZ::CLT;
1724 return SystemZ::CLGT;
1732 unsigned SystemZInstrInfo::getLoadAndTrap(unsigned Opcode) const {
1733 if (!STI.hasLoadAndTrap())
1738 return SystemZ::LAT;
1740 return SystemZ::LGAT;
1742 return SystemZ::LFHAT;
1744 return SystemZ::LLGFAT;
1746 return SystemZ::LLGTAT;
1751 void SystemZInstrInfo::loadImmediate(MachineBasicBlock &MBB,
1752 MachineBasicBlock::iterator MBBI,
1753 unsigned Reg, uint64_t Value) const {
1754 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
1756 if (isInt<16>(Value))
1757 Opcode = SystemZ::LGHI;
1758 else if (SystemZ::isImmLL(Value))
1759 Opcode = SystemZ::LLILL;
1760 else if (SystemZ::isImmLH(Value)) {
1761 Opcode = SystemZ::LLILH;
1764 assert(isInt<32>(Value) && "Huge values not handled yet");
1765 Opcode = SystemZ::LGFI;
1767 BuildMI(MBB, MBBI, DL, get(Opcode), Reg).addImm(Value);
1770 bool SystemZInstrInfo::
1771 areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,
1772 AliasAnalysis *AA) const {
1774 if (!MIa.hasOneMemOperand() || !MIb.hasOneMemOperand())
1777 // If mem-operands show that the same address Value is used by both
1778 // instructions, check for non-overlapping offsets and widths. Not
1779 // sure if a register based analysis would be an improvement...
1781 MachineMemOperand *MMOa = *MIa.memoperands_begin();
1782 MachineMemOperand *MMOb = *MIb.memoperands_begin();
1783 const Value *VALa = MMOa->getValue();
1784 const Value *VALb = MMOb->getValue();
1785 bool SameVal = (VALa && VALb && (VALa == VALb));
1787 const PseudoSourceValue *PSVa = MMOa->getPseudoValue();
1788 const PseudoSourceValue *PSVb = MMOb->getPseudoValue();
1789 if (PSVa && PSVb && (PSVa == PSVb))
1793 int OffsetA = MMOa->getOffset(), OffsetB = MMOb->getOffset();
1794 int WidthA = MMOa->getSize(), WidthB = MMOb->getSize();
1795 int LowOffset = OffsetA < OffsetB ? OffsetA : OffsetB;
1796 int HighOffset = OffsetA < OffsetB ? OffsetB : OffsetA;
1797 int LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
1798 if (LowOffset + LowWidth <= HighOffset)