1 //===-- SystemZInstrInfo.h - SystemZ instruction information ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the SystemZ implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZINSTRINFO_H
15 #define LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZINSTRINFO_H
18 #include "SystemZRegisterInfo.h"
19 #include "llvm/ADT/ArrayRef.h"
20 #include "llvm/CodeGen/MachineBasicBlock.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/Target/TargetInstrInfo.h"
26 #define GET_INSTRINFO_HEADER
27 #include "SystemZGenInstrInfo.inc"
31 class SystemZSubtarget;
36 // See comments in SystemZInstrFormats.td.
37 SimpleBDXLoad = (1 << 0),
38 SimpleBDXStore = (1 << 1),
39 Has20BitOffset = (1 << 2),
42 AccessSizeMask = (31 << 5),
44 CCValuesMask = (15 << 10),
46 CompareZeroCCMaskMask = (15 << 14),
47 CompareZeroCCMaskShift = 14,
48 CCMaskFirst = (1 << 18),
49 CCMaskLast = (1 << 19),
53 static inline unsigned getAccessSize(unsigned int Flags) {
54 return (Flags & AccessSizeMask) >> AccessSizeShift;
57 static inline unsigned getCCValues(unsigned int Flags) {
58 return (Flags & CCValuesMask) >> CCValuesShift;
61 static inline unsigned getCompareZeroCCMask(unsigned int Flags) {
62 return (Flags & CompareZeroCCMaskMask) >> CompareZeroCCMaskShift;
65 // SystemZ MachineOperand target flags.
67 // Masks out the bits for the access model.
68 MO_SYMBOL_MODIFIER = (3 << 0),
74 MO_INDNTPOFF = (2 << 0)
77 // Classifies a branch.
79 // An instruction that branches on the current value of CC.
82 // An instruction that peforms a 32-bit signed comparison and branches
86 // An instruction that peforms a 32-bit unsigned comparison and branches
90 // An instruction that peforms a 64-bit signed comparison and branches
94 // An instruction that peforms a 64-bit unsigned comparison and branches
98 // An instruction that decrements a 32-bit register and branches if
99 // the result is nonzero.
102 // An instruction that decrements a 64-bit register and branches if
103 // the result is nonzero.
107 // Information about a branch instruction.
109 // The type of the branch.
112 // CCMASK_<N> is set if CC might be equal to N.
115 // CCMASK_<N> is set if the branch should be taken when CC == N.
118 // The target of the branch.
119 const MachineOperand *Target;
121 Branch(BranchType type, unsigned ccValid, unsigned ccMask,
122 const MachineOperand *target)
123 : Type(type), CCValid(ccValid), CCMask(ccMask), Target(target) {}
126 // Kinds of fused compares in compare-and-* instructions. Together with type
127 // of the converted compare, this identifies the compare-and-*
129 enum FusedCompareType {
130 // Relative branch - CRJ etc.
133 // Indirect branch, used for return - CRBReturn etc.
136 // Indirect branch, used for sibcall - CRBCall etc.
143 } // end namespace SystemZII
145 class SystemZInstrInfo : public SystemZGenInstrInfo {
146 const SystemZRegisterInfo RI;
147 SystemZSubtarget &STI;
149 void splitMove(MachineBasicBlock::iterator MI, unsigned NewOpcode) const;
150 void splitAdjDynAlloc(MachineBasicBlock::iterator MI) const;
151 void expandRIPseudo(MachineInstr &MI, unsigned LowOpcode, unsigned HighOpcode,
152 bool ConvertHigh) const;
153 void expandRIEPseudo(MachineInstr &MI, unsigned LowOpcode,
154 unsigned LowOpcodeK, unsigned HighOpcode) const;
155 void expandRXYPseudo(MachineInstr &MI, unsigned LowOpcode,
156 unsigned HighOpcode) const;
157 void expandLOCPseudo(MachineInstr &MI, unsigned LowOpcode,
158 unsigned HighOpcode) const;
159 void expandLOCRPseudo(MachineInstr &MI, unsigned LowOpcode,
160 unsigned HighOpcode) const;
161 void expandZExtPseudo(MachineInstr &MI, unsigned LowOpcode,
162 unsigned Size) const;
163 void expandLoadStackGuard(MachineInstr *MI) const;
166 emitGRX32Move(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
167 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
168 unsigned LowLowOpcode, unsigned Size, bool KillSrc,
169 bool UndefSrc) const;
171 virtual void anchor();
174 /// Commutes the operands in the given instruction by changing the operands
175 /// order and/or changing the instruction's opcode and/or the immediate value
178 /// The arguments 'CommuteOpIdx1' and 'CommuteOpIdx2' specify the operands
181 /// Do not call this method for a non-commutable instruction or
182 /// non-commutable operands.
183 /// Even though the instruction is commutable, the method may still
184 /// fail to commute the operands, null pointer is returned in such cases.
185 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
186 unsigned CommuteOpIdx1,
187 unsigned CommuteOpIdx2) const override;
190 explicit SystemZInstrInfo(SystemZSubtarget &STI);
192 // Override TargetInstrInfo.
193 unsigned isLoadFromStackSlot(const MachineInstr &MI,
194 int &FrameIndex) const override;
195 unsigned isStoreToStackSlot(const MachineInstr &MI,
196 int &FrameIndex) const override;
197 bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex,
198 int &SrcFrameIndex) const override;
199 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
200 MachineBasicBlock *&FBB,
201 SmallVectorImpl<MachineOperand> &Cond,
202 bool AllowModify) const override;
203 unsigned removeBranch(MachineBasicBlock &MBB,
204 int *BytesRemoved = nullptr) const override;
205 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
206 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
208 int *BytesAdded = nullptr) const override;
209 bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
210 unsigned &SrcReg2, int &Mask, int &Value) const override;
211 bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
212 unsigned SrcReg2, int Mask, int Value,
213 const MachineRegisterInfo *MRI) const override;
214 bool canInsertSelect(const MachineBasicBlock&, ArrayRef<MachineOperand> Cond,
215 unsigned, unsigned, int&, int&, int&) const override;
216 void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
217 const DebugLoc &DL, unsigned DstReg,
218 ArrayRef<MachineOperand> Cond, unsigned TrueReg,
219 unsigned FalseReg) const override;
220 bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg,
221 MachineRegisterInfo *MRI) const override;
222 bool isPredicable(const MachineInstr &MI) const override;
223 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
224 unsigned ExtraPredCycles,
225 BranchProbability Probability) const override;
226 bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
227 unsigned NumCyclesT, unsigned ExtraPredCyclesT,
228 MachineBasicBlock &FMBB,
229 unsigned NumCyclesF, unsigned ExtraPredCyclesF,
230 BranchProbability Probability) const override;
231 bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
232 BranchProbability Probability) const override;
233 bool PredicateInstruction(MachineInstr &MI,
234 ArrayRef<MachineOperand> Pred) const override;
235 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
236 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
237 bool KillSrc) const override;
238 void storeRegToStackSlot(MachineBasicBlock &MBB,
239 MachineBasicBlock::iterator MBBI,
240 unsigned SrcReg, bool isKill, int FrameIndex,
241 const TargetRegisterClass *RC,
242 const TargetRegisterInfo *TRI) const override;
243 void loadRegFromStackSlot(MachineBasicBlock &MBB,
244 MachineBasicBlock::iterator MBBI,
245 unsigned DestReg, int FrameIdx,
246 const TargetRegisterClass *RC,
247 const TargetRegisterInfo *TRI) const override;
248 MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
250 LiveVariables *LV) const override;
252 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
253 ArrayRef<unsigned> Ops,
254 MachineBasicBlock::iterator InsertPt, int FrameIndex,
255 LiveIntervals *LIS = nullptr) const override;
256 MachineInstr *foldMemoryOperandImpl(
257 MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
258 MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
259 LiveIntervals *LIS = nullptr) const override;
260 bool expandPostRAPseudo(MachineInstr &MBBI) const override;
261 bool reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
264 // Return the SystemZRegisterInfo, which this class owns.
265 const SystemZRegisterInfo &getRegisterInfo() const { return RI; }
267 // Return the size in bytes of MI.
268 unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
270 // Return true if MI is a conditional or unconditional branch.
271 // When returning true, set Cond to the mask of condition-code
272 // values on which the instruction will branch, and set Target
273 // to the operand that contains the branch target. This target
274 // can be a register or a basic block.
275 SystemZII::Branch getBranchInfo(const MachineInstr &MI) const;
277 // Get the load and store opcodes for a given register class.
278 void getLoadStoreOpcodes(const TargetRegisterClass *RC,
279 unsigned &LoadOpcode, unsigned &StoreOpcode) const;
281 // Opcode is the opcode of an instruction that has an address operand,
282 // and the caller wants to perform that instruction's operation on an
283 // address that has displacement Offset. Return the opcode of a suitable
284 // instruction (which might be Opcode itself) or 0 if no such instruction
286 unsigned getOpcodeForOffset(unsigned Opcode, int64_t Offset) const;
288 // If Opcode is a load instruction that has a LOAD AND TEST form,
289 // return the opcode for the testing form, otherwise return 0.
290 unsigned getLoadAndTest(unsigned Opcode) const;
292 // Return true if ROTATE AND ... SELECTED BITS can be used to select bits
293 // Mask of the R2 operand, given that only the low BitSize bits of Mask are
294 // significant. Set Start and End to the I3 and I4 operands if so.
295 bool isRxSBGMask(uint64_t Mask, unsigned BitSize,
296 unsigned &Start, unsigned &End) const;
298 // If Opcode is a COMPARE opcode for which an associated fused COMPARE AND *
299 // operation exists, return the opcode for the latter, otherwise return 0.
300 // MI, if nonnull, is the compare instruction.
301 unsigned getFusedCompare(unsigned Opcode,
302 SystemZII::FusedCompareType Type,
303 const MachineInstr *MI = nullptr) const;
305 // If Opcode is a LOAD opcode for with an associated LOAD AND TRAP
306 // operation exists, returh the opcode for the latter, otherwise return 0.
307 unsigned getLoadAndTrap(unsigned Opcode) const;
309 // Emit code before MBBI in MI to move immediate value Value into
310 // physical register Reg.
311 void loadImmediate(MachineBasicBlock &MBB,
312 MachineBasicBlock::iterator MBBI,
313 unsigned Reg, uint64_t Value) const;
315 // Sometimes, it is possible for the target to tell, even without
316 // aliasing information, that two MIs access different memory
317 // addresses. This function returns true if two MIs access different
318 // memory addresses and false otherwise.
320 areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,
321 AliasAnalysis *AA = nullptr) const override;
324 } // end namespace llvm
326 #endif // LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZINSTRINFO_H