1 //===-- SystemZLongBranch.cpp - Branch lengthening for SystemZ ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass makes sure that all branches are in range. There are several ways
11 // in which this could be done. One aggressive approach is to assume that all
12 // branches are in range and successively replace those that turn out not
13 // to be in range with a longer form (branch relaxation). A simple
14 // implementation is to continually walk through the function relaxing
15 // branches until no more changes are needed and a fixed point is reached.
16 // However, in the pathological worst case, this implementation is
17 // quadratic in the number of blocks; relaxing branch N can make branch N-1
18 // go out of range, which in turn can make branch N-2 go out of range,
21 // An alternative approach is to assume that all branches must be
22 // converted to their long forms, then reinstate the short forms of
23 // branches that, even under this pessimistic assumption, turn out to be
24 // in range (branch shortening). This too can be implemented as a function
25 // walk that is repeated until a fixed point is reached. In general,
26 // the result of shortening is not as good as that of relaxation, and
27 // shortening is also quadratic in the worst case; shortening branch N
28 // can bring branch N-1 in range of the short form, which in turn can do
29 // the same for branch N-2, and so on. The main advantage of shortening
30 // is that each walk through the function produces valid code, so it is
31 // possible to stop at any point after the first walk. The quadraticness
32 // could therefore be handled with a maximum pass count, although the
33 // question then becomes: what maximum count should be used?
35 // On SystemZ, long branches are only needed for functions bigger than 64k,
36 // which are relatively rare to begin with, and the long branch sequences
37 // are actually relatively cheap. It therefore doesn't seem worth spending
38 // much compilation time on the problem. Instead, the approach we take is:
40 // (1) Work out the address that each block would have if no branches
41 // need relaxing. Exit the pass early if all branches are in range
42 // according to this assumption.
44 // (2) Work out the address that each block would have if all branches
47 // (3) Walk through the block calculating the final address of each instruction
48 // and relaxing those that need to be relaxed. For backward branches,
49 // this check uses the final address of the target block, as calculated
50 // earlier in the walk. For forward branches, this check uses the
51 // address of the target block that was calculated in (2). Both checks
52 // give a conservatively-correct range.
54 //===----------------------------------------------------------------------===//
56 #include "SystemZTargetMachine.h"
57 #include "llvm/ADT/Statistic.h"
58 #include "llvm/CodeGen/MachineFunctionPass.h"
59 #include "llvm/CodeGen/MachineInstrBuilder.h"
60 #include "llvm/IR/Function.h"
61 #include "llvm/Support/MathExtras.h"
62 #include "llvm/Target/TargetInstrInfo.h"
63 #include "llvm/Target/TargetMachine.h"
64 #include "llvm/Target/TargetRegisterInfo.h"
68 #define DEBUG_TYPE "systemz-long-branch"
70 STATISTIC(LongBranches, "Number of long branches.");
73 // Represents positional information about a basic block.
75 // The address that we currently assume the block has.
78 // The size of the block in bytes, excluding terminators.
79 // This value never changes.
82 // The minimum alignment of the block, as a log2 value.
83 // This value never changes.
86 // The number of terminators in this block. This value never changes.
87 unsigned NumTerminators;
90 : Address(0), Size(0), Alignment(0), NumTerminators(0) {}
93 // Represents the state of a block terminator.
94 struct TerminatorInfo {
95 // If this terminator is a relaxable branch, this points to the branch
96 // instruction, otherwise it is null.
99 // The address that we currently assume the terminator has.
102 // The current size of the terminator in bytes.
105 // If Branch is nonnull, this is the number of the target block,
106 // otherwise it is unused.
107 unsigned TargetBlock;
109 // If Branch is nonnull, this is the length of the longest relaxed form,
110 // otherwise it is zero.
111 unsigned ExtraRelaxSize;
113 TerminatorInfo() : Branch(nullptr), Size(0), TargetBlock(0),
117 // Used to keep track of the current position while iterating over the blocks.
118 struct BlockPosition {
119 // The address that we assume this position has.
122 // The number of low bits in Address that are known to be the same
123 // as the runtime address.
126 BlockPosition(unsigned InitialAlignment)
127 : Address(0), KnownBits(InitialAlignment) {}
130 class SystemZLongBranch : public MachineFunctionPass {
133 SystemZLongBranch(const SystemZTargetMachine &tm)
134 : MachineFunctionPass(ID), TII(nullptr) {}
136 StringRef getPassName() const override { return "SystemZ Long Branch"; }
138 bool runOnMachineFunction(MachineFunction &F) override;
139 MachineFunctionProperties getRequiredProperties() const override {
140 return MachineFunctionProperties().set(
141 MachineFunctionProperties::Property::NoVRegs);
145 void skipNonTerminators(BlockPosition &Position, MBBInfo &Block);
146 void skipTerminator(BlockPosition &Position, TerminatorInfo &Terminator,
148 TerminatorInfo describeTerminator(MachineInstr &MI);
149 uint64_t initMBBInfo();
150 bool mustRelaxBranch(const TerminatorInfo &Terminator, uint64_t Address);
151 bool mustRelaxABranch();
152 void setWorstCaseAddresses();
153 void splitBranchOnCount(MachineInstr *MI, unsigned AddOpcode);
154 void splitCompareBranch(MachineInstr *MI, unsigned CompareOpcode);
155 void relaxBranch(TerminatorInfo &Terminator);
156 void relaxBranches();
158 const SystemZInstrInfo *TII;
160 SmallVector<MBBInfo, 16> MBBs;
161 SmallVector<TerminatorInfo, 16> Terminators;
164 char SystemZLongBranch::ID = 0;
166 const uint64_t MaxBackwardRange = 0x10000;
167 const uint64_t MaxForwardRange = 0xfffe;
168 } // end anonymous namespace
170 FunctionPass *llvm::createSystemZLongBranchPass(SystemZTargetMachine &TM) {
171 return new SystemZLongBranch(TM);
174 // Position describes the state immediately before Block. Update Block
175 // accordingly and move Position to the end of the block's non-terminator
177 void SystemZLongBranch::skipNonTerminators(BlockPosition &Position,
179 if (Block.Alignment > Position.KnownBits) {
180 // When calculating the address of Block, we need to conservatively
181 // assume that Block had the worst possible misalignment.
182 Position.Address += ((uint64_t(1) << Block.Alignment) -
183 (uint64_t(1) << Position.KnownBits));
184 Position.KnownBits = Block.Alignment;
187 // Align the addresses.
188 uint64_t AlignMask = (uint64_t(1) << Block.Alignment) - 1;
189 Position.Address = (Position.Address + AlignMask) & ~AlignMask;
191 // Record the block's position.
192 Block.Address = Position.Address;
194 // Move past the non-terminators in the block.
195 Position.Address += Block.Size;
198 // Position describes the state immediately before Terminator.
199 // Update Terminator accordingly and move Position past it.
200 // Assume that Terminator will be relaxed if AssumeRelaxed.
201 void SystemZLongBranch::skipTerminator(BlockPosition &Position,
202 TerminatorInfo &Terminator,
203 bool AssumeRelaxed) {
204 Terminator.Address = Position.Address;
205 Position.Address += Terminator.Size;
207 Position.Address += Terminator.ExtraRelaxSize;
210 // Return a description of terminator instruction MI.
211 TerminatorInfo SystemZLongBranch::describeTerminator(MachineInstr &MI) {
212 TerminatorInfo Terminator;
213 Terminator.Size = TII->getInstSizeInBytes(MI);
214 if (MI.isConditionalBranch() || MI.isUnconditionalBranch()) {
215 switch (MI.getOpcode()) {
217 // Relaxes to JG, which is 2 bytes longer.
218 Terminator.ExtraRelaxSize = 2;
221 // Relaxes to BRCL, which is 2 bytes longer.
222 Terminator.ExtraRelaxSize = 2;
226 // Relaxes to A(G)HI and BRCL, which is 6 bytes longer.
227 Terminator.ExtraRelaxSize = 6;
230 // Never needs to be relaxed.
231 Terminator.ExtraRelaxSize = 0;
235 // Relaxes to a C(L)R/BRCL sequence, which is 2 bytes longer.
236 Terminator.ExtraRelaxSize = 2;
240 // Relaxes to a C(L)GR/BRCL sequence, which is 4 bytes longer.
241 Terminator.ExtraRelaxSize = 4;
245 // Relaxes to a C(G)HI/BRCL sequence, which is 4 bytes longer.
246 Terminator.ExtraRelaxSize = 4;
250 // Relaxes to a CL(G)FI/BRCL sequence, which is 6 bytes longer.
251 Terminator.ExtraRelaxSize = 6;
254 llvm_unreachable("Unrecognized branch instruction");
256 Terminator.Branch = &MI;
257 Terminator.TargetBlock =
258 TII->getBranchInfo(MI).Target->getMBB()->getNumber();
263 // Fill MBBs and Terminators, setting the addresses on the assumption
264 // that no branches need relaxation. Return the size of the function under
266 uint64_t SystemZLongBranch::initMBBInfo() {
267 MF->RenumberBlocks();
268 unsigned NumBlocks = MF->size();
271 MBBs.resize(NumBlocks);
274 Terminators.reserve(NumBlocks);
276 BlockPosition Position(MF->getAlignment());
277 for (unsigned I = 0; I < NumBlocks; ++I) {
278 MachineBasicBlock *MBB = MF->getBlockNumbered(I);
279 MBBInfo &Block = MBBs[I];
281 // Record the alignment, for quick access.
282 Block.Alignment = MBB->getAlignment();
284 // Calculate the size of the fixed part of the block.
285 MachineBasicBlock::iterator MI = MBB->begin();
286 MachineBasicBlock::iterator End = MBB->end();
287 while (MI != End && !MI->isTerminator()) {
288 Block.Size += TII->getInstSizeInBytes(*MI);
291 skipNonTerminators(Position, Block);
293 // Add the terminators.
295 if (!MI->isDebugValue()) {
296 assert(MI->isTerminator() && "Terminator followed by non-terminator");
297 Terminators.push_back(describeTerminator(*MI));
298 skipTerminator(Position, Terminators.back(), false);
299 ++Block.NumTerminators;
305 return Position.Address;
308 // Return true if, under current assumptions, Terminator would need to be
309 // relaxed if it were placed at address Address.
310 bool SystemZLongBranch::mustRelaxBranch(const TerminatorInfo &Terminator,
312 if (!Terminator.Branch)
315 const MBBInfo &Target = MBBs[Terminator.TargetBlock];
316 if (Address >= Target.Address) {
317 if (Address - Target.Address <= MaxBackwardRange)
320 if (Target.Address - Address <= MaxForwardRange)
327 // Return true if, under current assumptions, any terminator needs
329 bool SystemZLongBranch::mustRelaxABranch() {
330 for (auto &Terminator : Terminators)
331 if (mustRelaxBranch(Terminator, Terminator.Address))
336 // Set the address of each block on the assumption that all branches
338 void SystemZLongBranch::setWorstCaseAddresses() {
339 SmallVector<TerminatorInfo, 16>::iterator TI = Terminators.begin();
340 BlockPosition Position(MF->getAlignment());
341 for (auto &Block : MBBs) {
342 skipNonTerminators(Position, Block);
343 for (unsigned BTI = 0, BTE = Block.NumTerminators; BTI != BTE; ++BTI) {
344 skipTerminator(Position, *TI, true);
350 // Split BRANCH ON COUNT MI into the addition given by AddOpcode followed
351 // by a BRCL on the result.
352 void SystemZLongBranch::splitBranchOnCount(MachineInstr *MI,
353 unsigned AddOpcode) {
354 MachineBasicBlock *MBB = MI->getParent();
355 DebugLoc DL = MI->getDebugLoc();
356 BuildMI(*MBB, MI, DL, TII->get(AddOpcode))
357 .addOperand(MI->getOperand(0))
358 .addOperand(MI->getOperand(1))
360 MachineInstr *BRCL = BuildMI(*MBB, MI, DL, TII->get(SystemZ::BRCL))
361 .addImm(SystemZ::CCMASK_ICMP)
362 .addImm(SystemZ::CCMASK_CMP_NE)
363 .addOperand(MI->getOperand(2));
364 // The implicit use of CC is a killing use.
365 BRCL->addRegisterKilled(SystemZ::CC, &TII->getRegisterInfo());
366 MI->eraseFromParent();
369 // Split MI into the comparison given by CompareOpcode followed
370 // a BRCL on the result.
371 void SystemZLongBranch::splitCompareBranch(MachineInstr *MI,
372 unsigned CompareOpcode) {
373 MachineBasicBlock *MBB = MI->getParent();
374 DebugLoc DL = MI->getDebugLoc();
375 BuildMI(*MBB, MI, DL, TII->get(CompareOpcode))
376 .addOperand(MI->getOperand(0))
377 .addOperand(MI->getOperand(1));
378 MachineInstr *BRCL = BuildMI(*MBB, MI, DL, TII->get(SystemZ::BRCL))
379 .addImm(SystemZ::CCMASK_ICMP)
380 .addOperand(MI->getOperand(2))
381 .addOperand(MI->getOperand(3));
382 // The implicit use of CC is a killing use.
383 BRCL->addRegisterKilled(SystemZ::CC, &TII->getRegisterInfo());
384 MI->eraseFromParent();
387 // Relax the branch described by Terminator.
388 void SystemZLongBranch::relaxBranch(TerminatorInfo &Terminator) {
389 MachineInstr *Branch = Terminator.Branch;
390 switch (Branch->getOpcode()) {
392 Branch->setDesc(TII->get(SystemZ::JG));
395 Branch->setDesc(TII->get(SystemZ::BRCL));
398 splitBranchOnCount(Branch, SystemZ::AHI);
401 splitBranchOnCount(Branch, SystemZ::AGHI);
404 splitCompareBranch(Branch, SystemZ::CR);
407 splitCompareBranch(Branch, SystemZ::CGR);
410 splitCompareBranch(Branch, SystemZ::CHI);
413 splitCompareBranch(Branch, SystemZ::CGHI);
416 splitCompareBranch(Branch, SystemZ::CLR);
419 splitCompareBranch(Branch, SystemZ::CLGR);
422 splitCompareBranch(Branch, SystemZ::CLFI);
425 splitCompareBranch(Branch, SystemZ::CLGFI);
428 llvm_unreachable("Unrecognized branch");
431 Terminator.Size += Terminator.ExtraRelaxSize;
432 Terminator.ExtraRelaxSize = 0;
433 Terminator.Branch = nullptr;
438 // Run a shortening pass and relax any branches that need to be relaxed.
439 void SystemZLongBranch::relaxBranches() {
440 SmallVector<TerminatorInfo, 16>::iterator TI = Terminators.begin();
441 BlockPosition Position(MF->getAlignment());
442 for (auto &Block : MBBs) {
443 skipNonTerminators(Position, Block);
444 for (unsigned BTI = 0, BTE = Block.NumTerminators; BTI != BTE; ++BTI) {
445 assert(Position.Address <= TI->Address &&
446 "Addresses shouldn't go forwards");
447 if (mustRelaxBranch(*TI, Position.Address))
449 skipTerminator(Position, *TI, false);
455 bool SystemZLongBranch::runOnMachineFunction(MachineFunction &F) {
456 TII = static_cast<const SystemZInstrInfo *>(F.getSubtarget().getInstrInfo());
458 uint64_t Size = initMBBInfo();
459 if (Size <= MaxForwardRange || !mustRelaxABranch())
462 setWorstCaseAddresses();