1 //===-- SystemZOperators.td - SystemZ-specific operators ------*- tblgen-*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
13 def SDT_CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i64>,
15 def SDT_CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i64>,
17 def SDT_ZCall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
18 def SDT_ZCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
19 def SDT_ZICmp : SDTypeProfile<0, 3,
22 def SDT_ZBRCCMask : SDTypeProfile<0, 3,
25 SDTCisVT<2, OtherVT>]>;
26 def SDT_ZSelectCCMask : SDTypeProfile<1, 4,
31 def SDT_ZWrapPtr : SDTypeProfile<1, 1,
34 def SDT_ZWrapOffset : SDTypeProfile<1, 2,
38 def SDT_ZAdjDynAlloc : SDTypeProfile<1, 0, [SDTCisVT<0, i64>]>;
39 def SDT_ZGR128Binary : SDTypeProfile<1, 2,
40 [SDTCisVT<0, untyped>,
43 def SDT_ZAtomicLoadBinaryW : SDTypeProfile<1, 5,
50 def SDT_ZAtomicCmpSwapW : SDTypeProfile<1, 6,
58 def SDT_ZMemMemLength : SDTypeProfile<0, 3,
62 def SDT_ZMemMemLoop : SDTypeProfile<0, 4,
67 def SDT_ZString : SDTypeProfile<1, 3,
72 def SDT_ZI32Intrinsic : SDTypeProfile<1, 0, [SDTCisVT<0, i32>]>;
73 def SDT_ZPrefetch : SDTypeProfile<0, 2,
76 def SDT_ZLoadBSwap : SDTypeProfile<1, 2,
79 SDTCisVT<2, OtherVT>]>;
80 def SDT_ZStoreBSwap : SDTypeProfile<0, 3,
83 SDTCisVT<2, OtherVT>]>;
84 def SDT_ZTBegin : SDTypeProfile<0, 2,
87 def SDT_ZInsertVectorElt : SDTypeProfile<1, 3,
91 def SDT_ZExtractVectorElt : SDTypeProfile<1, 2,
94 def SDT_ZReplicate : SDTypeProfile<1, 1,
96 def SDT_ZVecUnaryConv : SDTypeProfile<1, 1,
99 def SDT_ZVecUnary : SDTypeProfile<1, 1,
101 SDTCisSameAs<0, 1>]>;
102 def SDT_ZVecBinary : SDTypeProfile<1, 2,
105 SDTCisSameAs<0, 2>]>;
106 def SDT_ZVecBinaryInt : SDTypeProfile<1, 2,
110 def SDT_ZVecBinaryConv : SDTypeProfile<1, 2,
113 SDTCisSameAs<1, 2>]>;
114 def SDT_ZVecBinaryConvInt : SDTypeProfile<1, 2,
118 def SDT_ZRotateMask : SDTypeProfile<1, 2,
122 def SDT_ZJoinDwords : SDTypeProfile<1, 2,
126 def SDT_ZVecTernary : SDTypeProfile<1, 3,
130 SDTCisSameAs<0, 3>]>;
131 def SDT_ZVecTernaryInt : SDTypeProfile<1, 3,
136 def SDT_ZVecQuaternaryInt : SDTypeProfile<1, 4,
142 def SDT_ZTest : SDTypeProfile<0, 2, [SDTCisVT<1, i64>]>;
144 //===----------------------------------------------------------------------===//
146 //===----------------------------------------------------------------------===//
148 // These are target-independent nodes, but have target-specific formats.
149 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_CallSeqStart,
150 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
151 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_CallSeqEnd,
152 [SDNPHasChain, SDNPSideEffect, SDNPOptInGlue,
154 def global_offset_table : SDNode<"ISD::GLOBAL_OFFSET_TABLE", SDTPtrLeaf>;
156 // Nodes for SystemZISD::*. See SystemZISelLowering.h for more details.
157 def z_retflag : SDNode<"SystemZISD::RET_FLAG", SDTNone,
158 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
159 def z_call : SDNode<"SystemZISD::CALL", SDT_ZCall,
160 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
162 def z_sibcall : SDNode<"SystemZISD::SIBCALL", SDT_ZCall,
163 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
165 def z_tls_gdcall : SDNode<"SystemZISD::TLS_GDCALL", SDT_ZCall,
166 [SDNPHasChain, SDNPInGlue, SDNPOutGlue,
168 def z_tls_ldcall : SDNode<"SystemZISD::TLS_LDCALL", SDT_ZCall,
169 [SDNPHasChain, SDNPInGlue, SDNPOutGlue,
171 def z_pcrel_wrapper : SDNode<"SystemZISD::PCREL_WRAPPER", SDT_ZWrapPtr, []>;
172 def z_pcrel_offset : SDNode<"SystemZISD::PCREL_OFFSET",
173 SDT_ZWrapOffset, []>;
174 def z_iabs : SDNode<"SystemZISD::IABS", SDTIntUnaryOp, []>;
175 def z_icmp : SDNode<"SystemZISD::ICMP", SDT_ZICmp, [SDNPOutGlue]>;
176 def z_fcmp : SDNode<"SystemZISD::FCMP", SDT_ZCmp, [SDNPOutGlue]>;
177 def z_tm : SDNode<"SystemZISD::TM", SDT_ZICmp, [SDNPOutGlue]>;
178 def z_br_ccmask : SDNode<"SystemZISD::BR_CCMASK", SDT_ZBRCCMask,
179 [SDNPHasChain, SDNPInGlue]>;
180 def z_select_ccmask : SDNode<"SystemZISD::SELECT_CCMASK", SDT_ZSelectCCMask,
182 def z_adjdynalloc : SDNode<"SystemZISD::ADJDYNALLOC", SDT_ZAdjDynAlloc>;
183 def z_popcnt : SDNode<"SystemZISD::POPCNT", SDTIntUnaryOp>;
184 def z_smul_lohi : SDNode<"SystemZISD::SMUL_LOHI", SDT_ZGR128Binary>;
185 def z_umul_lohi : SDNode<"SystemZISD::UMUL_LOHI", SDT_ZGR128Binary>;
186 def z_sdivrem : SDNode<"SystemZISD::SDIVREM", SDT_ZGR128Binary>;
187 def z_udivrem : SDNode<"SystemZISD::UDIVREM", SDT_ZGR128Binary>;
189 def z_membarrier : SDNode<"SystemZISD::MEMBARRIER", SDTNone,
190 [SDNPHasChain, SDNPSideEffect]>;
192 def z_loadbswap : SDNode<"SystemZISD::LRV", SDT_ZLoadBSwap,
193 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
194 def z_storebswap : SDNode<"SystemZISD::STRV", SDT_ZStoreBSwap,
195 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
197 def z_tdc : SDNode<"SystemZISD::TDC", SDT_ZTest, [SDNPOutGlue]>;
199 // Defined because the index is an i32 rather than a pointer.
200 def z_vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT",
201 SDT_ZInsertVectorElt>;
202 def z_vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT",
203 SDT_ZExtractVectorElt>;
204 def z_byte_mask : SDNode<"SystemZISD::BYTE_MASK", SDT_ZReplicate>;
205 def z_rotate_mask : SDNode<"SystemZISD::ROTATE_MASK", SDT_ZRotateMask>;
206 def z_replicate : SDNode<"SystemZISD::REPLICATE", SDT_ZReplicate>;
207 def z_join_dwords : SDNode<"SystemZISD::JOIN_DWORDS", SDT_ZJoinDwords>;
208 def z_splat : SDNode<"SystemZISD::SPLAT", SDT_ZVecBinaryInt>;
209 def z_merge_high : SDNode<"SystemZISD::MERGE_HIGH", SDT_ZVecBinary>;
210 def z_merge_low : SDNode<"SystemZISD::MERGE_LOW", SDT_ZVecBinary>;
211 def z_shl_double : SDNode<"SystemZISD::SHL_DOUBLE", SDT_ZVecTernaryInt>;
212 def z_permute_dwords : SDNode<"SystemZISD::PERMUTE_DWORDS",
214 def z_permute : SDNode<"SystemZISD::PERMUTE", SDT_ZVecTernary>;
215 def z_pack : SDNode<"SystemZISD::PACK", SDT_ZVecBinaryConv>;
216 def z_packs_cc : SDNode<"SystemZISD::PACKS_CC", SDT_ZVecBinaryConv,
218 def z_packls_cc : SDNode<"SystemZISD::PACKLS_CC", SDT_ZVecBinaryConv,
220 def z_unpack_high : SDNode<"SystemZISD::UNPACK_HIGH", SDT_ZVecUnaryConv>;
221 def z_unpackl_high : SDNode<"SystemZISD::UNPACKL_HIGH", SDT_ZVecUnaryConv>;
222 def z_unpack_low : SDNode<"SystemZISD::UNPACK_LOW", SDT_ZVecUnaryConv>;
223 def z_unpackl_low : SDNode<"SystemZISD::UNPACKL_LOW", SDT_ZVecUnaryConv>;
224 def z_vshl_by_scalar : SDNode<"SystemZISD::VSHL_BY_SCALAR",
226 def z_vsrl_by_scalar : SDNode<"SystemZISD::VSRL_BY_SCALAR",
228 def z_vsra_by_scalar : SDNode<"SystemZISD::VSRA_BY_SCALAR",
230 def z_vsum : SDNode<"SystemZISD::VSUM", SDT_ZVecBinaryConv>;
231 def z_vicmpe : SDNode<"SystemZISD::VICMPE", SDT_ZVecBinary>;
232 def z_vicmph : SDNode<"SystemZISD::VICMPH", SDT_ZVecBinary>;
233 def z_vicmphl : SDNode<"SystemZISD::VICMPHL", SDT_ZVecBinary>;
234 def z_vicmpes : SDNode<"SystemZISD::VICMPES", SDT_ZVecBinary,
236 def z_vicmphs : SDNode<"SystemZISD::VICMPHS", SDT_ZVecBinary,
238 def z_vicmphls : SDNode<"SystemZISD::VICMPHLS", SDT_ZVecBinary,
240 def z_vfcmpe : SDNode<"SystemZISD::VFCMPE", SDT_ZVecBinaryConv>;
241 def z_vfcmph : SDNode<"SystemZISD::VFCMPH", SDT_ZVecBinaryConv>;
242 def z_vfcmphe : SDNode<"SystemZISD::VFCMPHE", SDT_ZVecBinaryConv>;
243 def z_vfcmpes : SDNode<"SystemZISD::VFCMPES", SDT_ZVecBinaryConv,
245 def z_vfcmphs : SDNode<"SystemZISD::VFCMPHS", SDT_ZVecBinaryConv,
247 def z_vfcmphes : SDNode<"SystemZISD::VFCMPHES", SDT_ZVecBinaryConv,
249 def z_vextend : SDNode<"SystemZISD::VEXTEND", SDT_ZVecUnaryConv>;
250 def z_vround : SDNode<"SystemZISD::VROUND", SDT_ZVecUnaryConv>;
251 def z_vtm : SDNode<"SystemZISD::VTM", SDT_ZCmp, [SDNPOutGlue]>;
252 def z_vfae_cc : SDNode<"SystemZISD::VFAE_CC", SDT_ZVecTernaryInt,
254 def z_vfaez_cc : SDNode<"SystemZISD::VFAEZ_CC", SDT_ZVecTernaryInt,
256 def z_vfee_cc : SDNode<"SystemZISD::VFEE_CC", SDT_ZVecBinary,
258 def z_vfeez_cc : SDNode<"SystemZISD::VFEEZ_CC", SDT_ZVecBinary,
260 def z_vfene_cc : SDNode<"SystemZISD::VFENE_CC", SDT_ZVecBinary,
262 def z_vfenez_cc : SDNode<"SystemZISD::VFENEZ_CC", SDT_ZVecBinary,
264 def z_vistr_cc : SDNode<"SystemZISD::VISTR_CC", SDT_ZVecUnary,
266 def z_vstrc_cc : SDNode<"SystemZISD::VSTRC_CC", SDT_ZVecQuaternaryInt,
268 def z_vstrcz_cc : SDNode<"SystemZISD::VSTRCZ_CC",
269 SDT_ZVecQuaternaryInt, [SDNPOutGlue]>;
270 def z_vftci : SDNode<"SystemZISD::VFTCI", SDT_ZVecBinaryConvInt,
273 class AtomicWOp<string name, SDTypeProfile profile = SDT_ZAtomicLoadBinaryW>
274 : SDNode<"SystemZISD::"##name, profile,
275 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
277 def z_atomic_swapw : AtomicWOp<"ATOMIC_SWAPW">;
278 def z_atomic_loadw_add : AtomicWOp<"ATOMIC_LOADW_ADD">;
279 def z_atomic_loadw_sub : AtomicWOp<"ATOMIC_LOADW_SUB">;
280 def z_atomic_loadw_and : AtomicWOp<"ATOMIC_LOADW_AND">;
281 def z_atomic_loadw_or : AtomicWOp<"ATOMIC_LOADW_OR">;
282 def z_atomic_loadw_xor : AtomicWOp<"ATOMIC_LOADW_XOR">;
283 def z_atomic_loadw_nand : AtomicWOp<"ATOMIC_LOADW_NAND">;
284 def z_atomic_loadw_min : AtomicWOp<"ATOMIC_LOADW_MIN">;
285 def z_atomic_loadw_max : AtomicWOp<"ATOMIC_LOADW_MAX">;
286 def z_atomic_loadw_umin : AtomicWOp<"ATOMIC_LOADW_UMIN">;
287 def z_atomic_loadw_umax : AtomicWOp<"ATOMIC_LOADW_UMAX">;
288 def z_atomic_cmp_swapw : AtomicWOp<"ATOMIC_CMP_SWAPW", SDT_ZAtomicCmpSwapW>;
290 def z_mvc : SDNode<"SystemZISD::MVC", SDT_ZMemMemLength,
291 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
292 def z_mvc_loop : SDNode<"SystemZISD::MVC_LOOP", SDT_ZMemMemLoop,
293 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
294 def z_nc : SDNode<"SystemZISD::NC", SDT_ZMemMemLength,
295 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
296 def z_nc_loop : SDNode<"SystemZISD::NC_LOOP", SDT_ZMemMemLoop,
297 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
298 def z_oc : SDNode<"SystemZISD::OC", SDT_ZMemMemLength,
299 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
300 def z_oc_loop : SDNode<"SystemZISD::OC_LOOP", SDT_ZMemMemLoop,
301 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
302 def z_xc : SDNode<"SystemZISD::XC", SDT_ZMemMemLength,
303 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
304 def z_xc_loop : SDNode<"SystemZISD::XC_LOOP", SDT_ZMemMemLoop,
305 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
306 def z_clc : SDNode<"SystemZISD::CLC", SDT_ZMemMemLength,
307 [SDNPHasChain, SDNPOutGlue, SDNPMayLoad]>;
308 def z_clc_loop : SDNode<"SystemZISD::CLC_LOOP", SDT_ZMemMemLoop,
309 [SDNPHasChain, SDNPOutGlue, SDNPMayLoad]>;
310 def z_strcmp : SDNode<"SystemZISD::STRCMP", SDT_ZString,
311 [SDNPHasChain, SDNPOutGlue, SDNPMayLoad]>;
312 def z_stpcpy : SDNode<"SystemZISD::STPCPY", SDT_ZString,
313 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
314 def z_search_string : SDNode<"SystemZISD::SEARCH_STRING", SDT_ZString,
315 [SDNPHasChain, SDNPOutGlue, SDNPMayLoad]>;
316 def z_ipm : SDNode<"SystemZISD::IPM", SDT_ZI32Intrinsic,
318 def z_prefetch : SDNode<"SystemZISD::PREFETCH", SDT_ZPrefetch,
319 [SDNPHasChain, SDNPMayLoad, SDNPMayStore,
322 def z_tbegin : SDNode<"SystemZISD::TBEGIN", SDT_ZTBegin,
323 [SDNPHasChain, SDNPOutGlue, SDNPMayStore,
325 def z_tbegin_nofloat : SDNode<"SystemZISD::TBEGIN_NOFLOAT", SDT_ZTBegin,
326 [SDNPHasChain, SDNPOutGlue, SDNPMayStore,
328 def z_tend : SDNode<"SystemZISD::TEND", SDTNone,
329 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
331 def z_vshl : SDNode<"ISD::SHL", SDT_ZVecBinary>;
332 def z_vsra : SDNode<"ISD::SRA", SDT_ZVecBinary>;
333 def z_vsrl : SDNode<"ISD::SRL", SDT_ZVecBinary>;
335 //===----------------------------------------------------------------------===//
337 //===----------------------------------------------------------------------===//
339 def z_lrvh : PatFrag<(ops node:$addr), (z_loadbswap node:$addr, i16)>;
340 def z_lrv : PatFrag<(ops node:$addr), (z_loadbswap node:$addr, i32)>;
341 def z_lrvg : PatFrag<(ops node:$addr), (z_loadbswap node:$addr, i64)>;
343 def z_strvh : PatFrag<(ops node:$src, node:$addr),
344 (z_storebswap node:$src, node:$addr, i16)>;
345 def z_strv : PatFrag<(ops node:$src, node:$addr),
346 (z_storebswap node:$src, node:$addr, i32)>;
347 def z_strvg : PatFrag<(ops node:$src, node:$addr),
348 (z_storebswap node:$src, node:$addr, i64)>;
350 // Signed and unsigned comparisons.
351 def z_scmp : PatFrag<(ops node:$a, node:$b), (z_icmp node:$a, node:$b, imm), [{
352 unsigned Type = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue();
353 return Type != SystemZICMP::UnsignedOnly;
355 def z_ucmp : PatFrag<(ops node:$a, node:$b), (z_icmp node:$a, node:$b, imm), [{
356 unsigned Type = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue();
357 return Type != SystemZICMP::SignedOnly;
360 // Register- and memory-based TEST UNDER MASK.
361 def z_tm_reg : PatFrag<(ops node:$a, node:$b), (z_tm node:$a, node:$b, imm)>;
362 def z_tm_mem : PatFrag<(ops node:$a, node:$b), (z_tm node:$a, node:$b, 0)>;
364 // Register sign-extend operations. Sub-32-bit values are represented as i32s.
365 def sext8 : PatFrag<(ops node:$src), (sext_inreg node:$src, i8)>;
366 def sext16 : PatFrag<(ops node:$src), (sext_inreg node:$src, i16)>;
367 def sext32 : PatFrag<(ops node:$src), (sext (i32 node:$src))>;
369 // Match extensions of an i32 to an i64, followed by an in-register sign
370 // extension from a sub-i32 value.
371 def sext8dbl : PatFrag<(ops node:$src), (sext8 (anyext node:$src))>;
372 def sext16dbl : PatFrag<(ops node:$src), (sext16 (anyext node:$src))>;
374 // Register zero-extend operations. Sub-32-bit values are represented as i32s.
375 def zext8 : PatFrag<(ops node:$src), (and node:$src, 0xff)>;
376 def zext16 : PatFrag<(ops node:$src), (and node:$src, 0xffff)>;
377 def zext32 : PatFrag<(ops node:$src), (zext (i32 node:$src))>;
379 // Extending loads in which the extension type can be signed.
380 def asextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
381 unsigned Type = cast<LoadSDNode>(N)->getExtensionType();
382 return Type == ISD::EXTLOAD || Type == ISD::SEXTLOAD;
384 def asextloadi8 : PatFrag<(ops node:$ptr), (asextload node:$ptr), [{
385 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
387 def asextloadi16 : PatFrag<(ops node:$ptr), (asextload node:$ptr), [{
388 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
390 def asextloadi32 : PatFrag<(ops node:$ptr), (asextload node:$ptr), [{
391 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
394 // Extending loads in which the extension type can be unsigned.
395 def azextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
396 unsigned Type = cast<LoadSDNode>(N)->getExtensionType();
397 return Type == ISD::EXTLOAD || Type == ISD::ZEXTLOAD;
399 def azextloadi8 : PatFrag<(ops node:$ptr), (azextload node:$ptr), [{
400 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
402 def azextloadi16 : PatFrag<(ops node:$ptr), (azextload node:$ptr), [{
403 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
405 def azextloadi32 : PatFrag<(ops node:$ptr), (azextload node:$ptr), [{
406 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
409 // Extending loads in which the extension type doesn't matter.
410 def anyextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
411 return cast<LoadSDNode>(N)->getExtensionType() != ISD::NON_EXTLOAD;
413 def anyextloadi8 : PatFrag<(ops node:$ptr), (anyextload node:$ptr), [{
414 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
416 def anyextloadi16 : PatFrag<(ops node:$ptr), (anyextload node:$ptr), [{
417 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
419 def anyextloadi32 : PatFrag<(ops node:$ptr), (anyextload node:$ptr), [{
420 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
424 class AlignedLoad<SDPatternOperator load>
425 : PatFrag<(ops node:$addr), (load node:$addr), [{
426 auto *Load = cast<LoadSDNode>(N);
427 return Load->getAlignment() >= Load->getMemoryVT().getStoreSize();
429 def aligned_load : AlignedLoad<load>;
430 def aligned_asextloadi16 : AlignedLoad<asextloadi16>;
431 def aligned_asextloadi32 : AlignedLoad<asextloadi32>;
432 def aligned_azextloadi16 : AlignedLoad<azextloadi16>;
433 def aligned_azextloadi32 : AlignedLoad<azextloadi32>;
436 class AlignedStore<SDPatternOperator store>
437 : PatFrag<(ops node:$src, node:$addr), (store node:$src, node:$addr), [{
438 auto *Store = cast<StoreSDNode>(N);
439 return Store->getAlignment() >= Store->getMemoryVT().getStoreSize();
441 def aligned_store : AlignedStore<store>;
442 def aligned_truncstorei16 : AlignedStore<truncstorei16>;
443 def aligned_truncstorei32 : AlignedStore<truncstorei32>;
445 // Non-volatile loads. Used for instructions that might access the storage
446 // location multiple times.
447 class NonvolatileLoad<SDPatternOperator load>
448 : PatFrag<(ops node:$addr), (load node:$addr), [{
449 auto *Load = cast<LoadSDNode>(N);
450 return !Load->isVolatile();
452 def nonvolatile_load : NonvolatileLoad<load>;
453 def nonvolatile_anyextloadi8 : NonvolatileLoad<anyextloadi8>;
454 def nonvolatile_anyextloadi16 : NonvolatileLoad<anyextloadi16>;
455 def nonvolatile_anyextloadi32 : NonvolatileLoad<anyextloadi32>;
457 // Non-volatile stores.
458 class NonvolatileStore<SDPatternOperator store>
459 : PatFrag<(ops node:$src, node:$addr), (store node:$src, node:$addr), [{
460 auto *Store = cast<StoreSDNode>(N);
461 return !Store->isVolatile();
463 def nonvolatile_store : NonvolatileStore<store>;
464 def nonvolatile_truncstorei8 : NonvolatileStore<truncstorei8>;
465 def nonvolatile_truncstorei16 : NonvolatileStore<truncstorei16>;
466 def nonvolatile_truncstorei32 : NonvolatileStore<truncstorei32>;
468 // A store of a load that can be implemented using MVC.
469 def mvc_store : PatFrag<(ops node:$value, node:$addr),
470 (unindexedstore node:$value, node:$addr),
471 [{ return storeLoadCanUseMVC(N); }]>;
473 // Binary read-modify-write operations on memory in which the other
474 // operand is also memory and for which block operations like NC can
475 // be used. There are two patterns for each operator, depending on
476 // which operand contains the "other" load.
477 multiclass block_op<SDPatternOperator operator> {
478 def "1" : PatFrag<(ops node:$value, node:$addr),
479 (unindexedstore (operator node:$value,
480 (unindexedload node:$addr)),
482 [{ return storeLoadCanUseBlockBinary(N, 0); }]>;
483 def "2" : PatFrag<(ops node:$value, node:$addr),
484 (unindexedstore (operator (unindexedload node:$addr),
487 [{ return storeLoadCanUseBlockBinary(N, 1); }]>;
489 defm block_and : block_op<and>;
490 defm block_or : block_op<or>;
491 defm block_xor : block_op<xor>;
494 def inserti8 : PatFrag<(ops node:$src1, node:$src2),
495 (or (and node:$src1, -256), node:$src2)>;
496 def insertll : PatFrag<(ops node:$src1, node:$src2),
497 (or (and node:$src1, 0xffffffffffff0000), node:$src2)>;
498 def insertlh : PatFrag<(ops node:$src1, node:$src2),
499 (or (and node:$src1, 0xffffffff0000ffff), node:$src2)>;
500 def inserthl : PatFrag<(ops node:$src1, node:$src2),
501 (or (and node:$src1, 0xffff0000ffffffff), node:$src2)>;
502 def inserthh : PatFrag<(ops node:$src1, node:$src2),
503 (or (and node:$src1, 0x0000ffffffffffff), node:$src2)>;
504 def insertlf : PatFrag<(ops node:$src1, node:$src2),
505 (or (and node:$src1, 0xffffffff00000000), node:$src2)>;
506 def inserthf : PatFrag<(ops node:$src1, node:$src2),
507 (or (and node:$src1, 0x00000000ffffffff), node:$src2)>;
509 // ORs that can be treated as insertions.
510 def or_as_inserti8 : PatFrag<(ops node:$src1, node:$src2),
511 (or node:$src1, node:$src2), [{
512 unsigned BitWidth = N->getValueType(0).getScalarSizeInBits();
513 return CurDAG->MaskedValueIsZero(N->getOperand(0),
514 APInt::getLowBitsSet(BitWidth, 8));
517 // ORs that can be treated as reversed insertions.
518 def or_as_revinserti8 : PatFrag<(ops node:$src1, node:$src2),
519 (or node:$src1, node:$src2), [{
520 unsigned BitWidth = N->getValueType(0).getScalarSizeInBits();
521 return CurDAG->MaskedValueIsZero(N->getOperand(1),
522 APInt::getLowBitsSet(BitWidth, 8));
525 // Negative integer absolute.
526 def z_inegabs : PatFrag<(ops node:$src), (ineg (z_iabs node:$src))>;
528 // Integer absolute, matching the canonical form generated by DAGCombiner.
529 def z_iabs32 : PatFrag<(ops node:$src),
530 (xor (add node:$src, (sra node:$src, (i32 31))),
531 (sra node:$src, (i32 31)))>;
532 def z_iabs64 : PatFrag<(ops node:$src),
533 (xor (add node:$src, (sra node:$src, (i32 63))),
534 (sra node:$src, (i32 63)))>;
535 def z_inegabs32 : PatFrag<(ops node:$src), (ineg (z_iabs32 node:$src))>;
536 def z_inegabs64 : PatFrag<(ops node:$src), (ineg (z_iabs64 node:$src))>;
538 // Integer multiply-and-add
539 def z_muladd : PatFrag<(ops node:$src1, node:$src2, node:$src3),
540 (add (mul node:$src1, node:$src2), node:$src3)>;
542 // Fused multiply-subtract, using the natural operand order.
543 def fms : PatFrag<(ops node:$src1, node:$src2, node:$src3),
544 (fma node:$src1, node:$src2, (fneg node:$src3))>;
546 // Fused multiply-add and multiply-subtract, but with the order of the
547 // operands matching SystemZ's MA and MS instructions.
548 def z_fma : PatFrag<(ops node:$src1, node:$src2, node:$src3),
549 (fma node:$src2, node:$src3, node:$src1)>;
550 def z_fms : PatFrag<(ops node:$src1, node:$src2, node:$src3),
551 (fma node:$src2, node:$src3, (fneg node:$src1))>;
553 // Negative fused multiply-add and multiply-subtract.
554 def fnma : PatFrag<(ops node:$src1, node:$src2, node:$src3),
555 (fneg (fma node:$src1, node:$src2, node:$src3))>;
556 def fnms : PatFrag<(ops node:$src1, node:$src2, node:$src3),
557 (fneg (fms node:$src1, node:$src2, node:$src3))>;
559 // Floating-point negative absolute.
560 def fnabs : PatFrag<(ops node:$ptr), (fneg (fabs node:$ptr))>;
562 // Create a unary operator that loads from memory and then performs
563 // the given operation on it.
564 class loadu<SDPatternOperator operator, SDPatternOperator load = load>
565 : PatFrag<(ops node:$addr), (operator (load node:$addr))>;
567 // Create a store operator that performs the given unary operation
568 // on the value before storing it.
569 class storeu<SDPatternOperator operator, SDPatternOperator store = store>
570 : PatFrag<(ops node:$value, node:$addr),
571 (store (operator node:$value), node:$addr)>;
573 // Create a store operator that performs the given inherent operation
574 // and stores the resulting value.
575 class storei<SDPatternOperator operator, SDPatternOperator store = store>
576 : PatFrag<(ops node:$addr),
577 (store (operator), node:$addr)>;
579 // Vector representation of all-zeros and all-ones.
580 def z_vzero : PatFrag<(ops), (bitconvert (v16i8 (z_byte_mask (i32 0))))>;
581 def z_vones : PatFrag<(ops), (bitconvert (v16i8 (z_byte_mask (i32 65535))))>;
583 // Load a scalar and replicate it in all elements of a vector.
584 class z_replicate_load<ValueType scalartype, SDPatternOperator load>
585 : PatFrag<(ops node:$addr),
586 (z_replicate (scalartype (load node:$addr)))>;
587 def z_replicate_loadi8 : z_replicate_load<i32, anyextloadi8>;
588 def z_replicate_loadi16 : z_replicate_load<i32, anyextloadi16>;
589 def z_replicate_loadi32 : z_replicate_load<i32, load>;
590 def z_replicate_loadi64 : z_replicate_load<i64, load>;
591 def z_replicate_loadf32 : z_replicate_load<f32, load>;
592 def z_replicate_loadf64 : z_replicate_load<f64, load>;
594 // Load a scalar and insert it into a single element of a vector.
595 class z_vle<ValueType scalartype, SDPatternOperator load>
596 : PatFrag<(ops node:$vec, node:$addr, node:$index),
597 (z_vector_insert node:$vec, (scalartype (load node:$addr)),
599 def z_vlei8 : z_vle<i32, anyextloadi8>;
600 def z_vlei16 : z_vle<i32, anyextloadi16>;
601 def z_vlei32 : z_vle<i32, load>;
602 def z_vlei64 : z_vle<i64, load>;
603 def z_vlef32 : z_vle<f32, load>;
604 def z_vlef64 : z_vle<f64, load>;
606 // Load a scalar and insert it into the low element of the high i64 of a
608 class z_vllez<ValueType scalartype, SDPatternOperator load, int index>
609 : PatFrag<(ops node:$addr),
610 (z_vector_insert (z_vzero),
611 (scalartype (load node:$addr)), (i32 index))>;
612 def z_vllezi8 : z_vllez<i32, anyextloadi8, 7>;
613 def z_vllezi16 : z_vllez<i32, anyextloadi16, 3>;
614 def z_vllezi32 : z_vllez<i32, load, 1>;
615 def z_vllezi64 : PatFrag<(ops node:$addr),
616 (z_join_dwords (i64 (load node:$addr)), (i64 0))>;
617 // We use high merges to form a v4f32 from four f32s. Propagating zero
618 // into all elements but index 1 gives this expression.
619 def z_vllezf32 : PatFrag<(ops node:$addr),
626 (v4f32 (scalar_to_vector
627 (f32 (load node:$addr)))))))),
628 (v2i64 (z_vzero))))>;
629 def z_vllezf64 : PatFrag<(ops node:$addr),
631 (scalar_to_vector (f64 (load node:$addr))),
634 // Similarly for the high element of a zeroed vector.
635 def z_vllezli32 : z_vllez<i32, load, 0>;
636 def z_vllezlf32 : PatFrag<(ops node:$addr),
642 (v4f32 (scalar_to_vector
643 (f32 (load node:$addr)))),
644 (v4f32 (z_vzero))))),
645 (v2i64 (z_vzero))))>;
647 // Store one element of a vector.
648 class z_vste<ValueType scalartype, SDPatternOperator store>
649 : PatFrag<(ops node:$vec, node:$addr, node:$index),
650 (store (scalartype (z_vector_extract node:$vec, node:$index)),
652 def z_vstei8 : z_vste<i32, truncstorei8>;
653 def z_vstei16 : z_vste<i32, truncstorei16>;
654 def z_vstei32 : z_vste<i32, store>;
655 def z_vstei64 : z_vste<i64, store>;
656 def z_vstef32 : z_vste<f32, store>;
657 def z_vstef64 : z_vste<f64, store>;
659 // Arithmetic negation on vectors.
660 def z_vneg : PatFrag<(ops node:$x), (sub (z_vzero), node:$x)>;
662 // Bitwise negation on vectors.
663 def z_vnot : PatFrag<(ops node:$x), (xor node:$x, (z_vones))>;
665 // Signed "integer greater than zero" on vectors.
666 def z_vicmph_zero : PatFrag<(ops node:$x), (z_vicmph node:$x, (z_vzero))>;
668 // Signed "integer less than zero" on vectors.
669 def z_vicmpl_zero : PatFrag<(ops node:$x), (z_vicmph (z_vzero), node:$x)>;
671 // Integer absolute on vectors.
672 class z_viabs<int shift>
673 : PatFrag<(ops node:$src),
674 (xor (add node:$src, (z_vsra_by_scalar node:$src, (i32 shift))),
675 (z_vsra_by_scalar node:$src, (i32 shift)))>;
676 def z_viabs8 : z_viabs<7>;
677 def z_viabs16 : z_viabs<15>;
678 def z_viabs32 : z_viabs<31>;
679 def z_viabs64 : z_viabs<63>;
681 // Sign-extend the i64 elements of a vector.
682 class z_vse<int shift>
683 : PatFrag<(ops node:$src),
684 (z_vsra_by_scalar (z_vshl_by_scalar node:$src, shift), shift)>;
685 def z_vsei8 : z_vse<56>;
686 def z_vsei16 : z_vse<48>;
687 def z_vsei32 : z_vse<32>;
689 // ...and again with the extensions being done on individual i64 scalars.
690 class z_vse_by_parts<SDPatternOperator operator, int index1, int index2>
691 : PatFrag<(ops node:$src),
693 (operator (z_vector_extract node:$src, index1)),
694 (operator (z_vector_extract node:$src, index2)))>;
695 def z_vsei8_by_parts : z_vse_by_parts<sext8dbl, 7, 15>;
696 def z_vsei16_by_parts : z_vse_by_parts<sext16dbl, 3, 7>;
697 def z_vsei32_by_parts : z_vse_by_parts<sext32, 1, 3>;